Bachelor/vhdl-modules: VHDL implementation of transceiver, job parser and hardware accelerator modules @ v0.3.0

subDesTagesMitExtraKaese 3d6c997e9b added float relu and sigmoid		пре 4 година
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bd	57b56ee006 constraints	пре 4 година
constraints	49c489734b init	пре 5 година
hdl	41cdf232fd fixed conv2d timings	пре 4 година
ip	3d6c997e9b added float relu and sigmoid	пре 4 година
ip_repo	b7e2c5f4c6 deleted old ips	пре 4 година
testbench	41cdf232fd fixed conv2d timings	пре 4 година