Bachelor/vhdl-modules: VHDL implementation of transceiver, job parser and hardware accelerator modules @ v0.3.0

subDesTagesMitExtraKaese 3d6c997e9b added float relu and sigmoid		%!s(int64=4) %!d(string=hai) anos
..
bd	57b56ee006 constraints	%!s(int64=4) %!d(string=hai) anos
constraints	49c489734b init	%!s(int64=5) %!d(string=hai) anos
hdl	41cdf232fd fixed conv2d timings	%!s(int64=4) %!d(string=hai) anos
ip	3d6c997e9b added float relu and sigmoid	%!s(int64=4) %!d(string=hai) anos
ip_repo	b7e2c5f4c6 deleted old ips	%!s(int64=4) %!d(string=hai) anos
testbench	41cdf232fd fixed conv2d timings	%!s(int64=4) %!d(string=hai) anos