Bachelor/vhdl-modules: VHDL implementation of transceiver, job parser and hardware accelerator modules @ v0.3.0

subDesTagesMitExtraKaese 3d6c997e9b added float relu and sigmoid		4 lat temu
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bd	57b56ee006 constraints	4 lat temu
constraints	49c489734b init	5 lat temu
hdl	41cdf232fd fixed conv2d timings	4 lat temu
ip	3d6c997e9b added float relu and sigmoid	4 lat temu
ip_repo	b7e2c5f4c6 deleted old ips	4 lat temu
testbench	41cdf232fd fixed conv2d timings	4 lat temu