niosii hello world

.gitignore

@@ -0,0 +1,71 @@
+# from https://github.com/thomasrussellmurphy/quartus-DE0-project/blob/master/.gitignore
+
+# Working with Altera Quartus II (Q2) and do proper versioning is not that easy
+# but if you follow some rules it can be accomplished. :)
+# This file should be placed into the main directory where the .qpf file is
+# found. Generally Q2 throws all entities and so on in the main directory, but
+# you can place all stuff also in separate folders. This approach is followed
+# here. So when you create a new design create one or more folders where your
+# entities will be located and put a .gitignore in there that overrides the
+# ignores of this file, e.g. one single rule stating "!*" which allows now all
+# type of files. When you add a MegaFunction or another entity to your design,
+# simply add it to one of your private folders and Q2 will be happy and manage
+# everything quite good. When you want to do versioning of your generated
+# SOF/POF files, you can do this by redirecting the generated output to an own
+# folder. To do this go to:
+# "Assignments"
+# -> "Settings
+# -> "Compilation Process Settings"
+# -> "Save project output files in specified directory"
+# Now you can either place a .gitignore in the directory and allow the following
+# list of types:
+# !*.sof
+# !*.pof
+# or you create an own submodule in the folder to keep binary files out of your
+# design.
+
+# Need to keep all HDL files
+# *.vhd
+# *.v
+
+# ignore Quartus II generated files
+*_generation_script*
+*_inst.vhd
+*.bak
+*.cmp
+*.done
+*.eqn
+*.hex
+*.html
+*.jdi
+*.jpg
+*.mif
+*.pin
+*.pof
+*.ptf.*
+*.qar
+*.qarlog
+*.qws
+*.rpt
+*.smsg
+*.sof
+*.sopc_builder
+*.summary
+*.tcl
+*.txt # Explicitly add any text files used
+*~
+*example*
+*sopc_*
+# *.sdc # I want those timing files
+
+# ignore Quartus II generated folders
+db/
+incremental_db/
+simulation/
+timing/
+testbench/
+*_sim/
+
+# ignore eclipse temp files
+obj/
+*.log

.qsys_edit/filters.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="18.1" />

.qsys_edit/nios2_uc.xml

@@ -0,0 +1,2167 @@
+<?xml version='1.0'?>
+<root>
+	<resource name="dock.ui.ThemeMap">
+		<key>eclipse</key>
+	</resource>
+	<resource name="ccontrol.frontend">
+		<frontend>
+			<settings>
+				<setting name="main">
+					<base>
+						<roots>
+							<root name="external">
+								<layout factory="predefined">
+									<replacement id="rootexternal"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>external</id>
+										<root>true</root>
+										<content delegate="screen dock">
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CExternalizeArea</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol north">
+								<layout factory="predefined">
+									<replacement id="rootccontrol north"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol north</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol south">
+								<layout factory="predefined">
+									<replacement id="rootccontrol south"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol south</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol east">
+								<layout factory="predefined">
+									<replacement id="rootccontrol east"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol east</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+							<root name="ccontrol center">
+								<layout factory="predefined" placeholder="dock.single.ccontrol\ center">
+									<replacement id="rootccontrol center"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol center</id>
+										<root>true</root>
+										<content delegate="SplitDockStationFactory">
+											<fullscreen-action>false</fullscreen-action>
+											<node nodeId="-1" orientation="HORIZONTAL" divider="0.2">
+												<leaf id="0" nodeId="-1"/>
+												<node nodeId="-1" orientation="VERTICAL" divider="0.75">
+													<node nodeId="-1" orientation="HORIZONTAL" divider="0.75">
+														<node nodeId="-1" orientation="HORIZONTAL" divider="0.3333333333333333">
+															<leaf id="1" nodeId="-1"/>
+															<node nodeId="-1" orientation="VERTICAL" divider="0.75">
+																<leaf id="2" nodeId="-1"/>
+																<leaf id="3" nodeId="-1"/>
+															</node>
+														</node>
+														<node nodeId="-1" orientation="VERTICAL" divider="0.5">
+															<leaf id="4" nodeId="-1"/>
+															<leaf id="5" nodeId="-1"/>
+														</node>
+													</node>
+													<leaf id="6" nodeId="-1"/>
+												</node>
+											</node>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.center</type>
+									</layout>
+								</adjacent>
+								<children ignore="false">
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.IP\ Catalog</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.IP\ Catalog</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
+													<replacement id="dockablesingle IP Catalog"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>IP\ Catalog</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Hierarchy</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Hierarchy">
+													<replacement id="dockablesingle Hierarchy"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Hierarchy</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.System\ Contents</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.System\ Contents</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Address\ Map</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">1</item>
+													<item key="dock.index" type="i">1</item>
+													<item key="dock.placeholder" type="s">dock.single.Address\ Map</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Instrumentation</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">2</item>
+													<item key="dock.index" type="i">2</item>
+													<item key="dock.placeholder" type="s">dock.single.Instrumentation</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Clock\ Settings</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">3</item>
+													<item key="dock.index" type="i">3</item>
+													<item key="dock.placeholder" type="s">dock.single.Clock\ Settings</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Instance\ Parameters</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">4</item>
+													<item key="dock.index" type="i">4</item>
+													<item key="dock.placeholder" type="s">dock.single.Instance\ Parameters</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.HDL\ Example</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">6</item>
+													<item key="dock.index" type="i">6</item>
+													<item key="dock.placeholder" type="s">dock.single.HDL\ Example</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Generation</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">7</item>
+													<item key="dock.index" type="i">7</item>
+													<item key="dock.placeholder" type="s">dock.single.Generation</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Connections</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">8</item>
+													<item key="dock.index" type="i">8</item>
+													<item key="dock.placeholder" type="s">dock.single.Connections</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Domains</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">10</item>
+													<item key="dock.index" type="i">10</item>
+													<item key="dock.placeholder" type="s">dock.single.Domains</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.System\ Contents">
+													<replacement id="dockablesingle System Contents"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>System Contents</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Address\ Map">
+													<replacement id="dockablesingle Address Map"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Address Map</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Instrumentation">
+													<replacement id="dockablesingle Instrumentation"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Instrumentation</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Clock\ Settings">
+													<replacement id="dockablesingle Clock Settings"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Clock Settings</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Instance\ Parameters">
+													<replacement id="dockablesingle Instance Parameters"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Instance Parameters</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.HDL\ Example">
+													<replacement id="dockablesingle HDL Example"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>HDL Example</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Generation">
+													<replacement id="dockablesingle Generation"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Generation</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Connections">
+													<replacement id="dockablesingle Connections"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Connections</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Domains">
+													<replacement id="dockablesingle Domains"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Domains</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Parameter\ Editor</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Parameter\ Editor</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Parameter\ Editor">
+													<replacement id="dockablesingle Parameter Editor"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Parameter Editor</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Block\ Symbol</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Block\ Symbol</item>
+												</entry>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Element\ Docs</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">1</item>
+													<item key="dock.index" type="i">1</item>
+													<item key="dock.placeholder" type="s">dock.single.Element\ Docs</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Block\ Symbol">
+													<replacement id="dockablesingle Block Symbol"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Block Symbol</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Element\ Docs">
+													<replacement id="dockablesingle Element Docs"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Element Docs</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Presets</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Presets</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Presets">
+													<replacement id="dockablesingle Presets"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Presets</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+									<child>
+										<layout factory="delegate_StackDockStationFactory">
+											<selected>0</selected>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+												<entry>
+													<key shared="false">
+														<placeholder>dock.single.Messages</placeholder>
+													</key>
+													<item key="convert" type="b">true</item>
+													<item key="convert-keys" type="a">
+														<item type="s">id</item>
+														<item type="s">index</item>
+														<item type="s">placeholder</item>
+													</item>
+													<item key="dock.id" type="i">0</item>
+													<item key="dock.index" type="i">0</item>
+													<item key="dock.placeholder" type="s">dock.single.Messages</item>
+												</entry>
+											</placeholders>
+										</layout>
+										<children ignore="false">
+											<child>
+												<layout factory="predefined" placeholder="dock.single.Messages">
+													<replacement id="dockablesingle Messages"/>
+													<delegate id="delegate_ccontrol backup factory id">
+														<id>Messages</id>
+														<area/>
+													</delegate>
+												</layout>
+												<children ignore="false"/>
+											</child>
+										</children>
+									</child>
+								</children>
+							</root>
+							<root name="ccontrol west">
+								<layout factory="predefined">
+									<replacement id="rootccontrol west"/>
+									<delegate id="delegate_CommonDockStationFactory">
+										<id>ccontrol west</id>
+										<root>true</root>
+										<content delegate="flap dock">
+											<window auto="true" direction="SOUTH"/>
+											<placeholders>
+												<version>0</version>
+												<format>dock.PlaceholderList</format>
+											</placeholders>
+										</content>
+									</delegate>
+								</layout>
+								<adjacent>
+									<layout factory="dock.RootStationAdjacentFactory">
+										<type>dock.CContentArea.minimize</type>
+									</layout>
+								</adjacent>
+								<children ignore="false"/>
+							</root>
+						</roots>
+						<children/>
+					</base>
+					<modes>
+						<dockables>
+							<entry id="single ccontrol center">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single IP Catalog">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Hierarchy">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single System Contents">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Address Map">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Instrumentation">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Clock Settings">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Instance Parameters">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single HDL Example">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Generation">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Connections">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Domains">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Parameter Editor">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Block Symbol">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Element Docs">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Presets">
+								<history/>
+								<properties/>
+							</entry>
+							<entry id="single Messages">
+								<history/>
+								<properties/>
+							</entry>
+						</dockables>
+						<modes/>
+					</modes>
+				</setting>
+			</settings>
+			<current name="main">
+				<base>
+					<roots>
+						<root name="external">
+							<layout factory="predefined">
+								<replacement id="rootexternal"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="screen dock">
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CExternalizeArea</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol north">
+							<layout factory="predefined">
+								<replacement id="rootccontrol north"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="SOUTH"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Hierarchy</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+													<placeholder>dock.single.IP\ Catalog</placeholder>
+													<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+												</key>
+												<item key="map" type="p">
+													<version>0</version>
+													<format>dock.PlaceholderList</format>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.IP\ Catalog</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+														</key>
+													</entry>
+													<entry>
+														<key shared="false">
+															<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+														</key>
+													</entry>
+												</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+												</key>
+											</entry>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol south">
+							<layout factory="predefined">
+								<replacement id="rootccontrol south"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="NORTH"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol east">
+							<layout factory="predefined">
+								<replacement id="rootccontrol east"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="EAST"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+						<root name="ccontrol center">
+							<layout factory="predefined" placeholder="dock.single.ccontrol\ center">
+								<replacement id="rootccontrol center"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<id>ccontrol center</id>
+									<root>true</root>
+									<content delegate="SplitDockStationFactory">
+										<fullscreen-action>false</fullscreen-action>
+										<node nodeId="1372710005721" orientation="HORIZONTAL" divider="0.22181146025878004">
+											<node nodeId="1375985011088" orientation="VERTICAL" divider="0.504054054054054">
+												<leaf id="3" nodeId="1375985003630">
+													<placeholders>
+														<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+														<placeholder>dock.single.IP\ Catalog</placeholder>
+														<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.IP\ Catalog</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+												<leaf id="1" nodeId="1375985011087">
+													<placeholders>
+														<placeholder>dock.single.Hierarchy</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Hierarchy</placeholder>
+															</key>
+															<item key="convert" type="b">true</item>
+															<item key="convert-keys" type="a"/>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Device\ Family</placeholder>
+															</key>
+															<item key="convert" type="b">true</item>
+															<item key="convert-keys" type="a"/>
+														</entry>
+													</placeholder-map>
+												</leaf>
+											</node>
+											<node nodeId="1372710005725" orientation="VERTICAL" divider="0.75">
+												<node nodeId="1372710005727" orientation="HORIZONTAL" divider="0.6183193900785428">
+													<node nodeId="1372710005733" orientation="VERTICAL" divider="0.75">
+														<leaf id="2" nodeId="1372710005735">
+															<placeholders>
+																<placeholder>dock.single.Connections</placeholder>
+																<placeholder>dock.single.System\ Contents</placeholder>
+																<placeholder>dock.single.Assignments</placeholder>
+																<placeholder>dock.single.Schematic</placeholder>
+																<placeholder>dock.single.Clocks</placeholder>
+																<placeholder>dock.single.Interface\ Requirements\ \-\ Alpha</placeholder>
+																<placeholder>dock.single.Generation</placeholder>
+																<placeholder>dock.single.Clock\ Settings</placeholder>
+																<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+																<placeholder>dock.single.HDL\ Example</placeholder>
+																<placeholder>dock.single.Clock\ Domains</placeholder>
+																<placeholder>dock.single.Interface\ Requirements</placeholder>
+																<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+																<placeholder>dock.single.Instrumentation</placeholder>
+																<placeholder>dock.single.Instance\ Parameters</placeholder>
+																<placeholder>dock.single.Domains</placeholder>
+															</placeholders>
+															<placeholder-map>
+																<version>0</version>
+																<format>dock.PlaceholderList</format>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.System\ Contents</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Address\ Map</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+																	</key>
+																	<item key="convert" type="b">true</item>
+																	<item key="convert-keys" type="a"/>
+																</entry>
+															</placeholder-map>
+														</leaf>
+														<leaf id="-1" nodeId="1372710005737">
+															<placeholders>
+																<placeholder>dock.single.Parameter\ Editor</placeholder>
+															</placeholders>
+														</leaf>
+													</node>
+													<node nodeId="1389812802503" orientation="VERTICAL" divider="0.6704331450094162">
+														<leaf id="4" nodeId="1389812800464">
+															<placeholders>
+																<placeholder>dock.single.Details</placeholder>
+																<placeholder>dock.single.Parameters</placeholder>
+																<placeholder>dock.single.Block\ Symbol</placeholder>
+																<placeholder>dock.single.Presets</placeholder>
+															</placeholders>
+															<placeholder-map>
+																<version>0</version>
+																<format>dock.PlaceholderList</format>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Block\ Symbol</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Details</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Parameters</placeholder>
+																	</key>
+																</entry>
+																<entry>
+																	<key shared="false">
+																		<placeholder>dock.single.Presets</placeholder>
+																	</key>
+																</entry>
+															</placeholder-map>
+														</leaf>
+														<leaf id="-1" nodeId="1372710005741">
+															<placeholders>
+																<placeholder>dock.single.Element\ Docs</placeholder>
+															</placeholders>
+														</leaf>
+													</node>
+												</node>
+												<leaf id="0" nodeId="1372710005745">
+													<placeholders>
+														<placeholder>dock.single.Messages</placeholder>
+														<placeholder>dock.single.Generation\ Messages</placeholder>
+													</placeholders>
+													<placeholder-map>
+														<version>0</version>
+														<format>dock.PlaceholderList</format>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Messages</placeholder>
+															</key>
+														</entry>
+														<entry>
+															<key shared="false">
+																<placeholder>dock.single.Generation\ Messages</placeholder>
+															</key>
+														</entry>
+													</placeholder-map>
+												</leaf>
+											</node>
+										</node>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.center</type>
+								</layout>
+							</adjacent>
+							<children ignore="false">
+								<child>
+									<layout factory="predefined" placeholder="dock.single.Messages">
+										<replacement id="dockablesingle Messages"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>Messages</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+								<child>
+									<layout factory="delegate_StackDockStationFactory">
+										<selected>0</selected>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Hierarchy</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Device\ Family</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">1</item>
+												<item key="dock.id" type="i">1</item>
+												<item key="dock.placeholder" type="s">dock.single.Device\ Family</item>
+											</entry>
+										</placeholders>
+									</layout>
+									<children ignore="false">
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Hierarchy">
+												<replacement id="dockablesingle Hierarchy"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Hierarchy</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Device\ Family">
+												<replacement id="dockablesingle Device Family"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Device Family</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+									</children>
+								</child>
+								<child>
+									<layout factory="delegate_StackDockStationFactory">
+										<selected>0</selected>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.System\ Contents</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">0</item>
+												<item key="dock.id" type="i">0</item>
+												<item key="dock.placeholder" type="s">dock.single.System\ Contents</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Address\ Map</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">1</item>
+												<item key="dock.id" type="i">1</item>
+												<item key="dock.placeholder" type="s">dock.single.Address\ Map</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+												</key>
+												<item key="convert" type="b">true</item>
+												<item key="convert-keys" type="a">
+													<item type="s">index</item>
+													<item type="s">id</item>
+													<item type="s">placeholder</item>
+												</item>
+												<item key="dock.index" type="i">2</item>
+												<item key="dock.id" type="i">2</item>
+												<item key="dock.placeholder" type="s">dock.single.Interconnect\ Requirements</item>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Assignments</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Connections</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Instance\ Parameters</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+												</key>
+											</entry>
+											<entry>
+												<key shared="false">
+													<placeholder>dock.single.Schematic</placeholder>
+												</key>
+											</entry>
+										</placeholders>
+									</layout>
+									<children ignore="false">
+										<child>
+											<layout factory="predefined" placeholder="dock.single.System\ Contents">
+												<replacement id="dockablesingle System Contents"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>System Contents</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Address\ Map">
+												<replacement id="dockablesingle Address Map"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Address Map</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+										<child>
+											<layout factory="predefined" placeholder="dock.single.Interconnect\ Requirements">
+												<replacement id="dockablesingle Interconnect Requirements"/>
+												<delegate id="delegate_ccontrol backup factory id">
+													<id>Interconnect Requirements</id>
+													<area/>
+												</delegate>
+											</layout>
+											<children ignore="false"/>
+										</child>
+									</children>
+								</child>
+								<child>
+									<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
+										<replacement id="dockablesingle IP Catalog"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>IP Catalog</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+								<child>
+									<layout factory="predefined" placeholder="dock.single.Parameters">
+										<replacement id="dockablesingle Parameters"/>
+										<delegate id="delegate_ccontrol backup factory id">
+											<id>Parameters</id>
+											<area/>
+										</delegate>
+									</layout>
+									<children ignore="false"/>
+								</child>
+							</children>
+						</root>
+						<root name="ccontrol west">
+							<layout factory="predefined">
+								<replacement id="rootccontrol west"/>
+								<delegate id="delegate_CommonDockStationFactory">
+									<root>true</root>
+									<content delegate="flap dock">
+										<window auto="true" direction="EAST"/>
+										<placeholders>
+											<version>0</version>
+											<format>dock.PlaceholderList</format>
+										</placeholders>
+									</content>
+								</delegate>
+							</layout>
+							<adjacent>
+								<layout factory="dock.RootStationAdjacentFactory">
+									<type>dock.CContentArea.minimize</type>
+								</layout>
+							</adjacent>
+							<children ignore="false"/>
+						</root>
+					</roots>
+					<children>
+						<child key="single Details" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Details</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Details</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Details">
+									<replacement id="dockablesingle Details"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Details</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Assignments" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Assignments</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>3</index>
+									<placeholder>dock.single.Assignments</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Assignments">
+									<replacement id="dockablesingle Assignments"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Assignments</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Schematic" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Schematic</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>7</index>
+									<placeholder>dock.single.Schematic</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Schematic">
+									<replacement id="dockablesingle Schematic"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Schematic</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Presets" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Presets</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>3</index>
+									<placeholder>dock.single.Presets</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Presets">
+									<replacement id="dockablesingle Presets"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Presets</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Clock Domains - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+										<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+										<leaf id="1375985003630"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Clock\ Domains\ \-\ Beta">
+									<replacement id="dockablesingle Clock Domains - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Clock Domains - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Generation Messages" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Generation\ Messages</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="BOTTOM" size="0.25" id="1372710005725"/>
+										<leaf id="1372710005745"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Generation\ Messages</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Generation\ Messages">
+									<replacement id="dockablesingle Generation Messages"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Generation Messages</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Connections" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Connections</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>4</index>
+									<placeholder>dock.single.Connections</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Connections">
+									<replacement id="dockablesingle Connections"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Connections</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Instance Parameters" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Instance\ Parameters</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>5</index>
+									<placeholder>dock.single.Instance\ Parameters</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Instance\ Parameters">
+									<replacement id="dockablesingle Instance Parameters"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Instance Parameters</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Instrumentation - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+										<node location="TOP" size="0.75" id="1372710005733"/>
+										<leaf id="1372710005735"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>6</index>
+									<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Instrumentation\ \-\ Beta">
+									<replacement id="dockablesingle Instrumentation - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Instrumentation - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Block Symbol" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Block\ Symbol</placeholder>
+									<backup-path>
+										<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+										<node location="TOP" size="0.75" id="1372710005725"/>
+										<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+										<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+										<leaf id="1389812800464"/>
+									</backup-path>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Block\ Symbol">
+									<replacement id="dockablesingle Block Symbol"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Block Symbol</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+						<child key="single Reset Domains - Beta" root="ccontrol center" location="true">
+							<location>
+								<property factory="SplitDockPlaceholderProperty">
+									<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+									<backup-path>
+										<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+										<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+										<leaf id="1375985003630"/>
+									</backup-path>
+								</property>
+								<property factory="StackDockPropertyFactory">
+									<index>1</index>
+									<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+								</property>
+							</location>
+							<layout>
+								<layout factory="predefined" placeholder="dock.single.Reset\ Domains\ \-\ Beta">
+									<replacement id="dockablesingle Reset Domains - Beta"/>
+									<delegate id="delegate_ccontrol backup factory id">
+										<id>Reset Domains - Beta</id>
+										<area/>
+									</delegate>
+								</layout>
+								<children ignore="false"/>
+							</layout>
+						</child>
+					</children>
+				</base>
+				<modes>
+					<dockables>
+						<entry id="single Details">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Details</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+												<leaf id="1389812800464"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Details</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Parameters" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol west</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Parameters</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="BOTTOM" size="0.47858823529411765" id="1389812862722"/>
+												<leaf id="1389812862721"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Assignments">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Assignments</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<node location="TOP" size="0.6682769726247987" id="1411773509398"/>
+												<leaf id="1411773473878"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Address Map" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Address\ Map</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Address\ Map</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Schematic">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Schematic</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Schematic</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Presets">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Presets</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="BOTTOM" size="0.5" id="1372710005739"/>
+												<leaf id="1372710005743"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Messages" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Messages</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="BOTTOM" size="0.25" id="1372710005725"/>
+												<leaf id="1372710005745"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Device Family" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Device\ Family</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<node location="BOTTOM" size="0.3317230273752013" id="1411773509398"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Device\ Family</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Clock Domains - Beta">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Generation Messages">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Generation\ Messages</placeholder>
+											<backup-path>
+												<node location="TOP" size="0.5" id="1411773534479"/>
+												<leaf id="1411773534477"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Connections">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Connections</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>5</index>
+											<placeholder>dock.single.Connections</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single System Contents" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.System\ Contents</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.System\ Contents</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Interconnect Requirements" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>2</index>
+											<placeholder>dock.single.Interconnect\ Requirements</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Instrumentation - Beta">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.6183193900785428" id="1372710005727"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<node location="TOP" size="0.5214117647058824" id="1389812862722"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Instrumentation\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Instance Parameters">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Instance\ Parameters</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.8" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="LEFT" size="0.75" id="1372710005727"/>
+												<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
+												<node location="TOP" size="0.75" id="1372710005733"/>
+												<leaf id="1372710005735"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>4</index>
+											<placeholder>dock.single.Instance\ Parameters</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single IP Catalog" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>0</index>
+											<placeholder>dock.single.IP\ Catalog</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Hierarchy" current="dock.mode.normal">
+							<history>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Hierarchy</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Hierarchy</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.2" id="1372710005721"/>
+												<node location="BOTTOM" size="0.2928870292887029" id="1375985011088"/>
+												<leaf id="1375985011087"/>
+											</backup-path>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Block Symbol">
+							<history>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Block\ Symbol</placeholder>
+											<backup-path>
+												<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
+												<node location="TOP" size="0.75" id="1372710005725"/>
+												<node location="RIGHT" size="0.38168060992145725" id="1372710005727"/>
+												<node location="TOP" size="0.6704331450094162" id="1389812802503"/>
+												<leaf id="1389812800464"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Block\ Symbol</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+						<entry id="single Reset Domains - Beta">
+							<history>
+								<mode>dock.mode.maximized</mode>
+								<mode>dock.mode.minimized</mode>
+								<mode>dock.mode.normal</mode>
+							</history>
+							<properties>
+								<property id="dock.mode.maximized">
+									<mode>dock.mode.maximized</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockFullScreenPropertyFactory"/>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.minimized">
+									<mode>dock.mode.minimized</mode>
+									<root>ccontrol north</root>
+									<location>
+										<property factory="flap dock">
+											<index>0</index>
+											<holding>false</holding>
+											<size>400</size>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+								<property id="dock.mode.normal">
+									<mode>dock.mode.normal</mode>
+									<root>ccontrol center</root>
+									<location>
+										<property factory="SplitDockPlaceholderProperty">
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+											<backup-path>
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</backup-path>
+										</property>
+										<property factory="StackDockPropertyFactory">
+											<index>1</index>
+											<placeholder>dock.single.Reset\ Domains\ \-\ Beta</placeholder>
+										</property>
+									</location>
+								</property>
+							</properties>
+						</entry>
+					</dockables>
+					<modes>
+						<entry id="dock.mode.maximized">
+							<maximized>
+								<item id="ccontrol center">
+									<mode>dock.mode.normal</mode>
+									<location>
+										<mode>dock.mode.normal</mode>
+										<root>ccontrol center</root>
+										<location>
+											<property factory="SplitDockPathProperty">
+												<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
+												<node location="TOP" size="0.504054054054054" id="1375985011088"/>
+												<leaf id="1375985003630"/>
+											</property>
+										</location>
+									</location>
+								</item>
+							</maximized>
+						</entry>
+					</modes>
+				</modes>
+			</current>
+		</frontend>
+	</resource>
+	<resource name="ccontrol.preferences"/>
+</root>

.qsys_edit/nios2_uc_schematic.nlv

@@ -0,0 +1,8 @@
+# # File gsaved with Nlview version 6.3.8  2013-12-19 bk=1.2992 VDI=34 GEI=35
+# 
+preplace inst unsaved.clk_0 -pg 1 -lvl 1 -y 30
+preplace inst unsaved -pg 1 -lvl 1 -y 40 -regy -20
+preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.reset,(SLAVE)clk_0.clk_in_reset) 1 0 1 NJ
+preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)clk_0.clk_in,(SLAVE)unsaved.clk) 1 0 1 NJ
+levelinfo -pg 1 0 50 270
+levelinfo -hier unsaved 60 90 260

.qsys_edit/preferences.xml

@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="All Interfaces">
+  <columns>
+   <connections preferredWidth="143" />
+   <irq preferredWidth="34" />
+  </columns>
+ </systemtable>
+ <library
+   expandedCategories="Library/Processors and Peripherals,Library/Processors and Peripherals/Peripherals,Library,Library/Interface Protocols,Library/Interface Protocols/PCI Express/QSYS Example Designs,Project,Library/Interface Protocols/PCI Express" />
+ <window width="1440" height="860" x="0" y="-1" />
+ <hdlexample language="VHDL" />
+ <generation synthesis="VHDL" />
+</preferences>

myfirst_niosii.qpf

@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+# Date created = 15:57:19  November 19, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.1"
+DATE = "15:57:19  November 19, 2020"
+
+# Revisions
+
+PROJECT_REVISION = "myfirst_niosii"

myfirst_niosii.qsf

@@ -0,0 +1,109 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+# Date created = 15:57:19  November 19, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		myfirst_niosii_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE115F29C7
+set_global_assignment -name TOP_LEVEL_ENTITY myfirst_niosii
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:57:19  NOVEMBER 19, 2020"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Blast FPGA" -entity nios2_uc.qip
+set_global_assignment -name EDA_INPUT_GND_NAME GND -entity nios2_uc.qip -section_id eda_design_synthesis
+set_global_assignment -name EDA_INPUT_VCC_NAME VDD -entity nios2_uc.qip -section_id eda_design_synthesis
+set_global_assignment -name EDA_LMF_FILE blast.lmf -entity nios2_uc.qip -section_id eda_design_synthesis
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES OFF -entity nios2_uc.qip -section_id eda_design_synthesis
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -entity nios2_uc.qip -section_id eda_design_synthesis
+set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -entity nios2_uc.qip -section_id eda_design_synthesis
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name QIP_FILE nios2_uc/synthesis/nios2_uc.qip
+set_global_assignment -name VHDL_FILE myfirst_niosii.vhd
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Blast FPGA" -entity myfirst_niosii.vhd
+set_global_assignment -name EDA_INPUT_GND_NAME GND -entity myfirst_niosii.vhd -section_id eda_design_synthesis
+set_global_assignment -name EDA_INPUT_VCC_NAME VDD -entity myfirst_niosii.vhd -section_id eda_design_synthesis
+set_global_assignment -name EDA_LMF_FILE blast.lmf -entity myfirst_niosii.vhd -section_id eda_design_synthesis
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES OFF -entity myfirst_niosii.vhd -section_id eda_design_synthesis
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -entity myfirst_niosii.vhd -section_id eda_design_synthesis
+set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -entity myfirst_niosii.vhd -section_id eda_design_synthesis
+set_location_assignment PIN_E21 -to pio_led[0]
+set_location_assignment PIN_E22 -to pio_led[1]
+set_location_assignment PIN_E25 -to pio_led[2]
+set_location_assignment PIN_E24 -to pio_led[3]
+set_location_assignment PIN_H21 -to pio_led[4]
+set_location_assignment PIN_G20 -to pio_led[5]
+set_location_assignment PIN_G22 -to pio_led[6]
+set_location_assignment PIN_G21 -to pio_led[7]
+set_location_assignment PIN_G19 -to pio_led[8]
+set_location_assignment PIN_Y23 -to rst
+set_location_assignment PIN_Y2 -to clk
+set_location_assignment PIN_F19 -to pio_led[9]
+set_location_assignment PIN_E19 -to pio_led[10]
+set_location_assignment PIN_F21 -to pio_led[11]
+set_location_assignment PIN_F18 -to pio_led[12]
+set_location_assignment PIN_E18 -to pio_led[13]
+set_location_assignment PIN_J19 -to pio_led[14]
+set_location_assignment PIN_H19 -to pio_led[15]
+set_location_assignment PIN_J17 -to pio_led[16]
+set_location_assignment PIN_G17 -to pio_led[17]
+set_location_assignment PIN_J15 -to pio_led[18]
+set_location_assignment PIN_H16 -to pio_led[19]
+set_location_assignment PIN_J16 -to pio_led[20]
+set_location_assignment PIN_H17 -to pio_led[21]
+set_location_assignment PIN_F15 -to pio_led[22]
+set_location_assignment PIN_G15 -to pio_led[23]
+set_location_assignment PIN_G16 -to pio_led[24]
+set_location_assignment PIN_H15 -to pio_led[25]
+set_location_assignment PIN_M23 -to toggle_button
+set_location_assignment PIN_F17 -to toggle_led
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

myfirst_niosii.vhd

@@ -0,0 +1,63 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_arith.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity myfirst_niosii is port (
+		clk: in std_logic;
+		rst: in std_logic;
+		pio_led: out std_logic_vector(31 downto 0);
+		toggle_button: in std_logic;
+		toggle_led: out std_logic
+	);
+end myfirst_niosii;
+
+architecture behav of myfirst_niosii is
+    component nios2_uc is
+        port (
+            clk_clk                 : in  std_logic                     := 'X'; -- clk
+            pio_led_ext_conn_export : out std_logic_vector(31 downto 0);        -- export
+            reset_reset_n           : in  std_logic                     := 'X'  -- reset_n
+        );
+    end component nios2_uc;
+	 
+	 signal toggle_led_s: std_logic := '0';
+	 signal state: std_logic := '0';
+	 signal counter: integer range 0 to 2**15-1 := 0;
+
+begin
+	 
+	     u0 : component nios2_uc
+        port map (
+            clk_clk                 => clk,                 --              clk.clk
+            pio_led_ext_conn_export => pio_led, -- pio_led_ext_conn.export
+            reset_reset_n           => rst            --            reset.reset_n
+        );
+		  
+		  
+		  toggle: process(clk, rst)
+
+				
+		  begin
+				if rst = '0' then
+					counter <= 0;
+					state <= '0';
+				elsif rising_edge(clk) then
+					if counter = 2**15-1 then
+						counter <= 0;
+						if toggle_button = not state then
+							state <= toggle_button;
+							if toggle_button = '1' then
+								toggle_led_s <= not toggle_led_s;
+							end if;
+						end if;
+					else
+						counter <= counter + 1;
+					end if;
+				end if;
+		  end process;
+		  
+		  toggle_led <= toggle_led_s;
+end behav;
+

nios2_uc/nios2_uc.bsf

@@ -0,0 +1,71 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2019  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 416 184)
+	(text "nios2_uc" (rect 182 -1 217 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 168 20 180)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
+		(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 176 72)(line_width 1))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
+		(text "reset_reset_n" (rect 4 141 82 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 176 152)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(output)
+		(text "pio_led_ext_conn_export[31..0]" (rect 0 0 123 12)(font "Arial" (font_size 8)))
+		(text "pio_led_ext_conn_export[31..0]" (rect 4 101 184 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 176 112)(line_width 3))
+	)
+	(drawing
+		(text "clk" (rect 161 43 340 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 181 67 380 144)(font "Arial" (color 0 0 0)))
+		(text "pio_led_ext_conn" (rect 75 83 246 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 181 107 398 224)(font "Arial" (color 0 0 0)))
+		(text "reset" (rect 147 123 324 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset_n" (rect 181 147 404 304)(font "Arial" (color 0 0 0)))
+		(text " nios2_uc " (rect 375 168 810 346)(font "Arial" ))
+		(line (pt 176 32)(pt 240 32)(line_width 1))
+		(line (pt 240 32)(pt 240 168)(line_width 1))
+		(line (pt 176 168)(pt 240 168)(line_width 1))
+		(line (pt 176 32)(pt 176 168)(line_width 1))
+		(line (pt 177 52)(pt 177 76)(line_width 1))
+		(line (pt 178 52)(pt 178 76)(line_width 1))
+		(line (pt 177 92)(pt 177 116)(line_width 1))
+		(line (pt 178 92)(pt 178 116)(line_width 1))
+		(line (pt 177 132)(pt 177 156)(line_width 1))
+		(line (pt 178 132)(pt 178 156)(line_width 1))
+		(line (pt 0 0)(pt 416 0)(line_width 1))
+		(line (pt 416 0)(pt 416 184)(line_width 1))
+		(line (pt 0 184)(pt 416 184)(line_width 1))
+		(line (pt 0 0)(pt 0 184)(line_width 1))
+	)
+)

nios2_uc/nios2_uc_bb.v

@@ -0,0 +1,10 @@
+
+module nios2_uc (
+	clk_clk,
+	reset_reset_n,
+	pio_led_ext_conn_export);	
+
+	input		clk_clk;
+	input		reset_reset_n;
+	output	[31:0]	pio_led_ext_conn_export;
+endmodule

nios2_uc/nios2_uc_inst.v

@@ -0,0 +1,6 @@
+	nios2_uc u0 (
+		.clk_clk                 (<connected-to-clk_clk>),                 //              clk.clk
+		.reset_reset_n           (<connected-to-reset_reset_n>),           //            reset.reset_n
+		.pio_led_ext_conn_export (<connected-to-pio_led_ext_conn_export>)  // pio_led_ext_conn.export
+	);
+

nios2_uc/synthesis/nios2_uc.regmap

@@ -0,0 +1,212 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
+<name>nios2_uc</name>
+<peripherals>
+<peripheral>
+      <name>nios2_uc_pio_LED_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress> 
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>32</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>     
+         <name>DATA</name>  
+         <displayName>Data</displayName>
+         <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
+         <addressOffset>0x0</addressOffset>
+         <size>32</size>
+         <access>read-write</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>data</name>
+           <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>read-write</access>
+        </field>
+       </fields>
+     </register> 
+        <register>     
+         <name>DIRECTION</name>  
+         <displayName>Direction</displayName>
+         <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
+         <addressOffset>0x4</addressOffset>
+         <size>32</size>
+         <access>read-write</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>direction</name>
+            <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>read-write</access>
+        </field>
+       </fields>
+     </register> 
+        <register>     
+         <name>IRQ_MASK</name>  
+         <displayName>Interrupt mask</displayName>
+         <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
+         <addressOffset>0x8</addressOffset>
+         <size>32</size>
+         <access>read-write</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>interruptmask</name>
+            <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>read-write</access>
+        </field>
+       </fields>
+     </register> 
+        <register>     
+         <name>EDGE_CAP</name>  
+         <displayName>Edge capture</displayName>
+         <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
+         <addressOffset>0xc</addressOffset>
+         <size>32</size>
+         <access>read-write</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>edgecapture</name>
+            <description>Edge detection for each input port.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>read-write</access>
+        </field>
+       </fields>
+     </register> 
+        <register>
+         <name>SET_BIT</name>  
+         <displayName>Outset</displayName>
+         <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
+         <addressOffset>0x10</addressOffset>
+         <size>32</size>
+         <access>write-only</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>outset</name>
+            <description>Specifies which bit of the output port to set.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>write-only</access>
+        </field>
+       </fields>
+     </register> 
+        <register>     
+         <name>CLEAR_BITS</name>  
+         <displayName>Outclear</displayName>
+         <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
+         <addressOffset>0x14</addressOffset>
+         <size>32</size>
+         <access>write-only</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>outclear</name>
+            <description>Specifies which output bit to clear.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>32</bitWidth>
+            <access>write-only</access>
+        </field>
+       </fields>
+     </register>            
+    </registers>
+   </peripheral>
+  <peripheral>
+      <name>nios2_uc_jtag_uart_avalon_jtag_slave_altera_avalon_jtag_uart</name><baseAddress>0x00000000</baseAddress> 
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>     
+         <name>DATA</name>  
+         <displayName>Data</displayName>
+         <description>Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.</description>
+         <addressOffset>0x0</addressOffset>
+         <size>32</size>
+         <access>read-write</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>data</name>
+           <description>The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>8</bitWidth>
+            <access>read-write</access>
+        </field>
+           <field><name>rvalid</name>
+           <description>Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.</description>
+            <bitOffset>0xf</bitOffset>
+            <bitWidth>1</bitWidth>
+            <access>read-only</access>
+        </field>
+           <field><name>ravail</name>
+           <description>The number of characters remaining in the read FIFO (after the current read).</description>
+            <bitOffset>0x10</bitOffset>
+            <bitWidth>16</bitWidth>
+            <access>read-only</access>
+        </field>
+       </fields>
+     </register> 
+        <register>     
+         <name>CONTROL</name>  
+         <displayName>Control</displayName>
+         <description>Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.</description>
+         <addressOffset>0x4</addressOffset>
+         <size>32</size>
+         <access>read-write</access>
+         <resetValue>0x0</resetValue>
+         <resetMask>0xffffffff</resetMask> 
+         <fields>
+           <field><name>re</name>
+            <description>Interrupt-enable bit for read interrupts.</description>
+            <bitOffset>0x0</bitOffset>
+            <bitWidth>1</bitWidth>
+            <access>read-write</access>
+        </field>
+           <field><name>we</name>
+            <description>Interrupt-enable bit for write interrupts</description>
+            <bitOffset>0x1</bitOffset>
+            <bitWidth>1</bitWidth>
+            <access>read-write</access>
+        </field>
+           <field><name>ri</name>
+            <description>Indicates that the read interrupt is pending.</description>
+            <bitOffset>0x8</bitOffset>
+            <bitWidth>1</bitWidth>
+            <access>read-only</access>
+        </field>
+           <field><name>wi</name>
+            <description>Indicates that the write interrupt is pending.</description>
+            <bitOffset>0x9</bitOffset>
+            <bitWidth>1</bitWidth>
+            <access>read-only</access>
+        </field>
+           <field><name>ac</name>
+            <description>Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.</description>
+            <bitOffset>0xa</bitOffset>
+            <bitWidth>1</bitWidth>
+            <access>read-write</access>
+        </field>
+           <field><name>wspace</name>
+            <description>The number of spaces available in the write FIFO</description>
+            <bitOffset>0x10</bitOffset>
+            <bitWidth>16</bitWidth>
+            <access>read-only</access>
+        </field>
+       </fields>
+     </register>            
+    </registers>
+   </peripheral>
+  </peripherals>
+</device>

nios2_uc/synthesis/nios2_uc.vhd

@@ -0,0 +1,465 @@
+-- nios2_uc.vhd
+
+-- Generated using ACDS version 18.1 646
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity nios2_uc is
+	port (
+		clk_clk                 : in  std_logic                     := '0'; --              clk.clk
+		pio_led_ext_conn_export : out std_logic_vector(31 downto 0);        -- pio_led_ext_conn.export
+		reset_reset_n           : in  std_logic                     := '0'  --            reset.reset_n
+	);
+end entity nios2_uc;
+
+architecture rtl of nios2_uc is
+	component nios2_uc_jtag_uart is
+		port (
+			clk            : in  std_logic                     := 'X';             -- clk
+			rst_n          : in  std_logic                     := 'X';             -- reset_n
+			av_chipselect  : in  std_logic                     := 'X';             -- chipselect
+			av_address     : in  std_logic                     := 'X';             -- address
+			av_read_n      : in  std_logic                     := 'X';             -- read_n
+			av_readdata    : out std_logic_vector(31 downto 0);                    -- readdata
+			av_write_n     : in  std_logic                     := 'X';             -- write_n
+			av_writedata   : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+			av_waitrequest : out std_logic;                                        -- waitrequest
+			av_irq         : out std_logic                                         -- irq
+		);
+	end component nios2_uc_jtag_uart;
+
+	component nios2_uc_nios2 is
+		port (
+			clk                                 : in  std_logic                     := 'X';             -- clk
+			reset_n                             : in  std_logic                     := 'X';             -- reset_n
+			reset_req                           : in  std_logic                     := 'X';             -- reset_req
+			d_address                           : out std_logic_vector(19 downto 0);                    -- address
+			d_byteenable                        : out std_logic_vector(3 downto 0);                     -- byteenable
+			d_read                              : out std_logic;                                        -- read
+			d_readdata                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+			d_waitrequest                       : in  std_logic                     := 'X';             -- waitrequest
+			d_write                             : out std_logic;                                        -- write
+			d_writedata                         : out std_logic_vector(31 downto 0);                    -- writedata
+			debug_mem_slave_debugaccess_to_roms : out std_logic;                                        -- debugaccess
+			i_address                           : out std_logic_vector(19 downto 0);                    -- address
+			i_read                              : out std_logic;                                        -- read
+			i_readdata                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+			i_waitrequest                       : in  std_logic                     := 'X';             -- waitrequest
+			irq                                 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- irq
+			debug_reset_request                 : out std_logic;                                        -- reset
+			debug_mem_slave_address             : in  std_logic_vector(8 downto 0)  := (others => 'X'); -- address
+			debug_mem_slave_byteenable          : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
+			debug_mem_slave_debugaccess         : in  std_logic                     := 'X';             -- debugaccess
+			debug_mem_slave_read                : in  std_logic                     := 'X';             -- read
+			debug_mem_slave_readdata            : out std_logic_vector(31 downto 0);                    -- readdata
+			debug_mem_slave_waitrequest         : out std_logic;                                        -- waitrequest
+			debug_mem_slave_write               : in  std_logic                     := 'X';             -- write
+			debug_mem_slave_writedata           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+			dummy_ci_port                       : out std_logic                                         -- readra
+		);
+	end component nios2_uc_nios2;
+
+	component nios2_uc_onchip_memory2 is
+		port (
+			clk        : in  std_logic                     := 'X';             -- clk
+			address    : in  std_logic_vector(15 downto 0) := (others => 'X'); -- address
+			clken      : in  std_logic                     := 'X';             -- clken
+			chipselect : in  std_logic                     := 'X';             -- chipselect
+			write      : in  std_logic                     := 'X';             -- write
+			readdata   : out std_logic_vector(31 downto 0);                    -- readdata
+			writedata  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+			byteenable : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
+			reset      : in  std_logic                     := 'X';             -- reset
+			reset_req  : in  std_logic                     := 'X';             -- reset_req
+			freeze     : in  std_logic                     := 'X'              -- freeze
+		);
+	end component nios2_uc_onchip_memory2;
+
+	component nios2_uc_pio_LED is
+		port (
+			clk        : in  std_logic                     := 'X';             -- clk
+			reset_n    : in  std_logic                     := 'X';             -- reset_n
+			address    : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- address
+			write_n    : in  std_logic                     := 'X';             -- write_n
+			writedata  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+			chipselect : in  std_logic                     := 'X';             -- chipselect
+			readdata   : out std_logic_vector(31 downto 0);                    -- readdata
+			out_port   : out std_logic_vector(31 downto 0)                     -- export
+		);
+	end component nios2_uc_pio_LED;
+
+	component nios2_uc_mm_interconnect_0 is
+		port (
+			clk_50_clk_clk                          : in  std_logic                     := 'X';             -- clk
+			nios2_reset_reset_bridge_in_reset_reset : in  std_logic                     := 'X';             -- reset
+			nios2_data_master_address               : in  std_logic_vector(19 downto 0) := (others => 'X'); -- address
+			nios2_data_master_waitrequest           : out std_logic;                                        -- waitrequest
+			nios2_data_master_byteenable            : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
+			nios2_data_master_read                  : in  std_logic                     := 'X';             -- read
+			nios2_data_master_readdata              : out std_logic_vector(31 downto 0);                    -- readdata
+			nios2_data_master_write                 : in  std_logic                     := 'X';             -- write
+			nios2_data_master_writedata             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+			nios2_data_master_debugaccess           : in  std_logic                     := 'X';             -- debugaccess
+			nios2_instruction_master_address        : in  std_logic_vector(19 downto 0) := (others => 'X'); -- address
+			nios2_instruction_master_waitrequest    : out std_logic;                                        -- waitrequest
+			nios2_instruction_master_read           : in  std_logic                     := 'X';             -- read
+			nios2_instruction_master_readdata       : out std_logic_vector(31 downto 0);                    -- readdata
+			jtag_uart_avalon_jtag_slave_address     : out std_logic_vector(0 downto 0);                     -- address
+			jtag_uart_avalon_jtag_slave_write       : out std_logic;                                        -- write
+			jtag_uart_avalon_jtag_slave_read        : out std_logic;                                        -- read
+			jtag_uart_avalon_jtag_slave_readdata    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+			jtag_uart_avalon_jtag_slave_writedata   : out std_logic_vector(31 downto 0);                    -- writedata
+			jtag_uart_avalon_jtag_slave_waitrequest : in  std_logic                     := 'X';             -- waitrequest
+			jtag_uart_avalon_jtag_slave_chipselect  : out std_logic;                                        -- chipselect
+			nios2_debug_mem_slave_address           : out std_logic_vector(8 downto 0);                     -- address
+			nios2_debug_mem_slave_write             : out std_logic;                                        -- write
+			nios2_debug_mem_slave_read              : out std_logic;                                        -- read
+			nios2_debug_mem_slave_readdata          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+			nios2_debug_mem_slave_writedata         : out std_logic_vector(31 downto 0);                    -- writedata
+			nios2_debug_mem_slave_byteenable        : out std_logic_vector(3 downto 0);                     -- byteenable
+			nios2_debug_mem_slave_waitrequest       : in  std_logic                     := 'X';             -- waitrequest
+			nios2_debug_mem_slave_debugaccess       : out std_logic;                                        -- debugaccess
+			onchip_memory2_s1_address               : out std_logic_vector(15 downto 0);                    -- address
+			onchip_memory2_s1_write                 : out std_logic;                                        -- write
+			onchip_memory2_s1_readdata              : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+			onchip_memory2_s1_writedata             : out std_logic_vector(31 downto 0);                    -- writedata
+			onchip_memory2_s1_byteenable            : out std_logic_vector(3 downto 0);                     -- byteenable
+			onchip_memory2_s1_chipselect            : out std_logic;                                        -- chipselect
+			onchip_memory2_s1_clken                 : out std_logic;                                        -- clken
+			pio_LED_s1_address                      : out std_logic_vector(1 downto 0);                     -- address
+			pio_LED_s1_write                        : out std_logic;                                        -- write
+			pio_LED_s1_readdata                     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+			pio_LED_s1_writedata                    : out std_logic_vector(31 downto 0);                    -- writedata
+			pio_LED_s1_chipselect                   : out std_logic                                         -- chipselect
+		);
+	end component nios2_uc_mm_interconnect_0;
+
+	component nios2_uc_irq_mapper is
+		port (
+			clk           : in  std_logic                     := 'X'; -- clk
+			reset         : in  std_logic                     := 'X'; -- reset
+			receiver0_irq : in  std_logic                     := 'X'; -- irq
+			sender_irq    : out std_logic_vector(31 downto 0)         -- irq
+		);
+	end component nios2_uc_irq_mapper;
+
+	component altera_reset_controller is
+		generic (
+			NUM_RESET_INPUTS          : integer := 6;
+			OUTPUT_RESET_SYNC_EDGES   : string  := "deassert";
+			SYNC_DEPTH                : integer := 2;
+			RESET_REQUEST_PRESENT     : integer := 0;
+			RESET_REQ_WAIT_TIME       : integer := 1;
+			MIN_RST_ASSERTION_TIME    : integer := 3;
+			RESET_REQ_EARLY_DSRT_TIME : integer := 1;
+			USE_RESET_REQUEST_IN0     : integer := 0;
+			USE_RESET_REQUEST_IN1     : integer := 0;
+			USE_RESET_REQUEST_IN2     : integer := 0;
+			USE_RESET_REQUEST_IN3     : integer := 0;
+			USE_RESET_REQUEST_IN4     : integer := 0;
+			USE_RESET_REQUEST_IN5     : integer := 0;
+			USE_RESET_REQUEST_IN6     : integer := 0;
+			USE_RESET_REQUEST_IN7     : integer := 0;
+			USE_RESET_REQUEST_IN8     : integer := 0;
+			USE_RESET_REQUEST_IN9     : integer := 0;
+			USE_RESET_REQUEST_IN10    : integer := 0;
+			USE_RESET_REQUEST_IN11    : integer := 0;
+			USE_RESET_REQUEST_IN12    : integer := 0;
+			USE_RESET_REQUEST_IN13    : integer := 0;
+			USE_RESET_REQUEST_IN14    : integer := 0;
+			USE_RESET_REQUEST_IN15    : integer := 0;
+			ADAPT_RESET_REQUEST       : integer := 0
+		);
+		port (
+			reset_in0      : in  std_logic := 'X'; -- reset
+			reset_in1      : in  std_logic := 'X'; -- reset
+			clk            : in  std_logic := 'X'; -- clk
+			reset_out      : out std_logic;        -- reset
+			reset_req      : out std_logic;        -- reset_req
+			reset_req_in0  : in  std_logic := 'X'; -- reset_req
+			reset_req_in1  : in  std_logic := 'X'; -- reset_req
+			reset_in2      : in  std_logic := 'X'; -- reset
+			reset_req_in2  : in  std_logic := 'X'; -- reset_req
+			reset_in3      : in  std_logic := 'X'; -- reset
+			reset_req_in3  : in  std_logic := 'X'; -- reset_req
+			reset_in4      : in  std_logic := 'X'; -- reset
+			reset_req_in4  : in  std_logic := 'X'; -- reset_req
+			reset_in5      : in  std_logic := 'X'; -- reset
+			reset_req_in5  : in  std_logic := 'X'; -- reset_req
+			reset_in6      : in  std_logic := 'X'; -- reset
+			reset_req_in6  : in  std_logic := 'X'; -- reset_req
+			reset_in7      : in  std_logic := 'X'; -- reset
+			reset_req_in7  : in  std_logic := 'X'; -- reset_req
+			reset_in8      : in  std_logic := 'X'; -- reset
+			reset_req_in8  : in  std_logic := 'X'; -- reset_req
+			reset_in9      : in  std_logic := 'X'; -- reset
+			reset_req_in9  : in  std_logic := 'X'; -- reset_req
+			reset_in10     : in  std_logic := 'X'; -- reset
+			reset_req_in10 : in  std_logic := 'X'; -- reset_req
+			reset_in11     : in  std_logic := 'X'; -- reset
+			reset_req_in11 : in  std_logic := 'X'; -- reset_req
+			reset_in12     : in  std_logic := 'X'; -- reset
+			reset_req_in12 : in  std_logic := 'X'; -- reset_req
+			reset_in13     : in  std_logic := 'X'; -- reset
+			reset_req_in13 : in  std_logic := 'X'; -- reset_req
+			reset_in14     : in  std_logic := 'X'; -- reset
+			reset_req_in14 : in  std_logic := 'X'; -- reset_req
+			reset_in15     : in  std_logic := 'X'; -- reset
+			reset_req_in15 : in  std_logic := 'X'  -- reset_req
+		);
+	end component altera_reset_controller;
+
+	signal nios2_data_master_readdata                                    : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_data_master_readdata -> nios2:d_readdata
+	signal nios2_data_master_waitrequest                                 : std_logic;                     -- mm_interconnect_0:nios2_data_master_waitrequest -> nios2:d_waitrequest
+	signal nios2_data_master_debugaccess                                 : std_logic;                     -- nios2:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_data_master_debugaccess
+	signal nios2_data_master_address                                     : std_logic_vector(19 downto 0); -- nios2:d_address -> mm_interconnect_0:nios2_data_master_address
+	signal nios2_data_master_byteenable                                  : std_logic_vector(3 downto 0);  -- nios2:d_byteenable -> mm_interconnect_0:nios2_data_master_byteenable
+	signal nios2_data_master_read                                        : std_logic;                     -- nios2:d_read -> mm_interconnect_0:nios2_data_master_read
+	signal nios2_data_master_write                                       : std_logic;                     -- nios2:d_write -> mm_interconnect_0:nios2_data_master_write
+	signal nios2_data_master_writedata                                   : std_logic_vector(31 downto 0); -- nios2:d_writedata -> mm_interconnect_0:nios2_data_master_writedata
+	signal nios2_instruction_master_readdata                             : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_instruction_master_readdata -> nios2:i_readdata
+	signal nios2_instruction_master_waitrequest                          : std_logic;                     -- mm_interconnect_0:nios2_instruction_master_waitrequest -> nios2:i_waitrequest
+	signal nios2_instruction_master_address                              : std_logic_vector(19 downto 0); -- nios2:i_address -> mm_interconnect_0:nios2_instruction_master_address
+	signal nios2_instruction_master_read                                 : std_logic;                     -- nios2:i_read -> mm_interconnect_0:nios2_instruction_master_read
+	signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect      : std_logic;                     -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
+	signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata        : std_logic_vector(31 downto 0); -- jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
+	signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest     : std_logic;                     -- jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
+	signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_address         : std_logic_vector(0 downto 0);  -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
+	signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_read            : std_logic;                     -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> mm_interconnect_0_jtag_uart_avalon_jtag_slave_read:in
+	signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_write           : std_logic;                     -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> mm_interconnect_0_jtag_uart_avalon_jtag_slave_write:in
+	signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata       : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
+	signal mm_interconnect_0_nios2_debug_mem_slave_readdata              : std_logic_vector(31 downto 0); -- nios2:debug_mem_slave_readdata -> mm_interconnect_0:nios2_debug_mem_slave_readdata
+	signal mm_interconnect_0_nios2_debug_mem_slave_waitrequest           : std_logic;                     -- nios2:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_debug_mem_slave_waitrequest
+	signal mm_interconnect_0_nios2_debug_mem_slave_debugaccess           : std_logic;                     -- mm_interconnect_0:nios2_debug_mem_slave_debugaccess -> nios2:debug_mem_slave_debugaccess
+	signal mm_interconnect_0_nios2_debug_mem_slave_address               : std_logic_vector(8 downto 0);  -- mm_interconnect_0:nios2_debug_mem_slave_address -> nios2:debug_mem_slave_address
+	signal mm_interconnect_0_nios2_debug_mem_slave_read                  : std_logic;                     -- mm_interconnect_0:nios2_debug_mem_slave_read -> nios2:debug_mem_slave_read
+	signal mm_interconnect_0_nios2_debug_mem_slave_byteenable            : std_logic_vector(3 downto 0);  -- mm_interconnect_0:nios2_debug_mem_slave_byteenable -> nios2:debug_mem_slave_byteenable
+	signal mm_interconnect_0_nios2_debug_mem_slave_write                 : std_logic;                     -- mm_interconnect_0:nios2_debug_mem_slave_write -> nios2:debug_mem_slave_write
+	signal mm_interconnect_0_nios2_debug_mem_slave_writedata             : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_debug_mem_slave_writedata -> nios2:debug_mem_slave_writedata
+	signal mm_interconnect_0_onchip_memory2_s1_chipselect                : std_logic;                     -- mm_interconnect_0:onchip_memory2_s1_chipselect -> onchip_memory2:chipselect
+	signal mm_interconnect_0_onchip_memory2_s1_readdata                  : std_logic_vector(31 downto 0); -- onchip_memory2:readdata -> mm_interconnect_0:onchip_memory2_s1_readdata
+	signal mm_interconnect_0_onchip_memory2_s1_address                   : std_logic_vector(15 downto 0); -- mm_interconnect_0:onchip_memory2_s1_address -> onchip_memory2:address
+	signal mm_interconnect_0_onchip_memory2_s1_byteenable                : std_logic_vector(3 downto 0);  -- mm_interconnect_0:onchip_memory2_s1_byteenable -> onchip_memory2:byteenable
+	signal mm_interconnect_0_onchip_memory2_s1_write                     : std_logic;                     -- mm_interconnect_0:onchip_memory2_s1_write -> onchip_memory2:write
+	signal mm_interconnect_0_onchip_memory2_s1_writedata                 : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_s1_writedata -> onchip_memory2:writedata
+	signal mm_interconnect_0_onchip_memory2_s1_clken                     : std_logic;                     -- mm_interconnect_0:onchip_memory2_s1_clken -> onchip_memory2:clken
+	signal mm_interconnect_0_pio_led_s1_chipselect                       : std_logic;                     -- mm_interconnect_0:pio_LED_s1_chipselect -> pio_LED:chipselect
+	signal mm_interconnect_0_pio_led_s1_readdata                         : std_logic_vector(31 downto 0); -- pio_LED:readdata -> mm_interconnect_0:pio_LED_s1_readdata
+	signal mm_interconnect_0_pio_led_s1_address                          : std_logic_vector(1 downto 0);  -- mm_interconnect_0:pio_LED_s1_address -> pio_LED:address
+	signal mm_interconnect_0_pio_led_s1_write                            : std_logic;                     -- mm_interconnect_0:pio_LED_s1_write -> mm_interconnect_0_pio_led_s1_write:in
+	signal mm_interconnect_0_pio_led_s1_writedata                        : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_LED_s1_writedata -> pio_LED:writedata
+	signal irq_mapper_receiver0_irq                                      : std_logic;                     -- jtag_uart:av_irq -> irq_mapper:receiver0_irq
+	signal nios2_irq_irq                                                 : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2:irq
+	signal rst_controller_reset_out_reset                                : std_logic;                     -- rst_controller:reset_out -> [irq_mapper:reset, mm_interconnect_0:nios2_reset_reset_bridge_in_reset_reset, onchip_memory2:reset, rst_controller_reset_out_reset:in, rst_translator:in_reset]
+	signal rst_controller_reset_out_reset_req                            : std_logic;                     -- rst_controller:reset_req -> [nios2:reset_req, onchip_memory2:reset_req, rst_translator:reset_req_in]
+	signal nios2_debug_reset_request_reset                               : std_logic;                     -- nios2:debug_reset_request -> rst_controller:reset_in1
+	signal reset_reset_n_ports_inv                                       : std_logic;                     -- reset_reset_n:inv -> rst_controller:reset_in0
+	signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_read_ports_inv  : std_logic;                     -- mm_interconnect_0_jtag_uart_avalon_jtag_slave_read:inv -> jtag_uart:av_read_n
+	signal mm_interconnect_0_jtag_uart_avalon_jtag_slave_write_ports_inv : std_logic;                     -- mm_interconnect_0_jtag_uart_avalon_jtag_slave_write:inv -> jtag_uart:av_write_n
+	signal mm_interconnect_0_pio_led_s1_write_ports_inv                  : std_logic;                     -- mm_interconnect_0_pio_led_s1_write:inv -> pio_LED:write_n
+	signal rst_controller_reset_out_reset_ports_inv                      : std_logic;                     -- rst_controller_reset_out_reset:inv -> [jtag_uart:rst_n, nios2:reset_n, pio_LED:reset_n]
+
+begin
+
+	jtag_uart : component nios2_uc_jtag_uart
+		port map (
+			clk            => clk_clk,                                                       --               clk.clk
+			rst_n          => rst_controller_reset_out_reset_ports_inv,                      --             reset.reset_n
+			av_chipselect  => mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect,      -- avalon_jtag_slave.chipselect
+			av_address     => mm_interconnect_0_jtag_uart_avalon_jtag_slave_address(0),      --                  .address
+			av_read_n      => mm_interconnect_0_jtag_uart_avalon_jtag_slave_read_ports_inv,  --                  .read_n
+			av_readdata    => mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata,        --                  .readdata
+			av_write_n     => mm_interconnect_0_jtag_uart_avalon_jtag_slave_write_ports_inv, --                  .write_n
+			av_writedata   => mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata,       --                  .writedata
+			av_waitrequest => mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest,     --                  .waitrequest
+			av_irq         => irq_mapper_receiver0_irq                                       --               irq.irq
+		);
+
+	nios2 : component nios2_uc_nios2
+		port map (
+			clk                                 => clk_clk,                                             --                       clk.clk
+			reset_n                             => rst_controller_reset_out_reset_ports_inv,            --                     reset.reset_n
+			reset_req                           => rst_controller_reset_out_reset_req,                  --                          .reset_req
+			d_address                           => nios2_data_master_address,                           --               data_master.address
+			d_byteenable                        => nios2_data_master_byteenable,                        --                          .byteenable
+			d_read                              => nios2_data_master_read,                              --                          .read
+			d_readdata                          => nios2_data_master_readdata,                          --                          .readdata
+			d_waitrequest                       => nios2_data_master_waitrequest,                       --                          .waitrequest
+			d_write                             => nios2_data_master_write,                             --                          .write
+			d_writedata                         => nios2_data_master_writedata,                         --                          .writedata
+			debug_mem_slave_debugaccess_to_roms => nios2_data_master_debugaccess,                       --                          .debugaccess
+			i_address                           => nios2_instruction_master_address,                    --        instruction_master.address
+			i_read                              => nios2_instruction_master_read,                       --                          .read
+			i_readdata                          => nios2_instruction_master_readdata,                   --                          .readdata
+			i_waitrequest                       => nios2_instruction_master_waitrequest,                --                          .waitrequest
+			irq                                 => nios2_irq_irq,                                       --                       irq.irq
+			debug_reset_request                 => nios2_debug_reset_request_reset,                     --       debug_reset_request.reset
+			debug_mem_slave_address             => mm_interconnect_0_nios2_debug_mem_slave_address,     --           debug_mem_slave.address
+			debug_mem_slave_byteenable          => mm_interconnect_0_nios2_debug_mem_slave_byteenable,  --                          .byteenable
+			debug_mem_slave_debugaccess         => mm_interconnect_0_nios2_debug_mem_slave_debugaccess, --                          .debugaccess
+			debug_mem_slave_read                => mm_interconnect_0_nios2_debug_mem_slave_read,        --                          .read
+			debug_mem_slave_readdata            => mm_interconnect_0_nios2_debug_mem_slave_readdata,    --                          .readdata
+			debug_mem_slave_waitrequest         => mm_interconnect_0_nios2_debug_mem_slave_waitrequest, --                          .waitrequest
+			debug_mem_slave_write               => mm_interconnect_0_nios2_debug_mem_slave_write,       --                          .write
+			debug_mem_slave_writedata           => mm_interconnect_0_nios2_debug_mem_slave_writedata,   --                          .writedata
+			dummy_ci_port                       => open                                                 -- custom_instruction_master.readra
+		);
+
+	onchip_memory2 : component nios2_uc_onchip_memory2
+		port map (
+			clk        => clk_clk,                                        --   clk1.clk
+			address    => mm_interconnect_0_onchip_memory2_s1_address,    --     s1.address
+			clken      => mm_interconnect_0_onchip_memory2_s1_clken,      --       .clken
+			chipselect => mm_interconnect_0_onchip_memory2_s1_chipselect, --       .chipselect
+			write      => mm_interconnect_0_onchip_memory2_s1_write,      --       .write
+			readdata   => mm_interconnect_0_onchip_memory2_s1_readdata,   --       .readdata
+			writedata  => mm_interconnect_0_onchip_memory2_s1_writedata,  --       .writedata
+			byteenable => mm_interconnect_0_onchip_memory2_s1_byteenable, --       .byteenable
+			reset      => rst_controller_reset_out_reset,                 -- reset1.reset
+			reset_req  => rst_controller_reset_out_reset_req,             --       .reset_req
+			freeze     => '0'                                             -- (terminated)
+		);
+
+	pio_led : component nios2_uc_pio_LED
+		port map (
+			clk        => clk_clk,                                      --                 clk.clk
+			reset_n    => rst_controller_reset_out_reset_ports_inv,     --               reset.reset_n
+			address    => mm_interconnect_0_pio_led_s1_address,         --                  s1.address
+			write_n    => mm_interconnect_0_pio_led_s1_write_ports_inv, --                    .write_n
+			writedata  => mm_interconnect_0_pio_led_s1_writedata,       --                    .writedata
+			chipselect => mm_interconnect_0_pio_led_s1_chipselect,      --                    .chipselect
+			readdata   => mm_interconnect_0_pio_led_s1_readdata,        --                    .readdata
+			out_port   => pio_led_ext_conn_export                       -- external_connection.export
+		);
+
+	mm_interconnect_0 : component nios2_uc_mm_interconnect_0
+		port map (
+			clk_50_clk_clk                          => clk_clk,                                                   --                        clk_50_clk.clk
+			nios2_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset,                            -- nios2_reset_reset_bridge_in_reset.reset
+			nios2_data_master_address               => nios2_data_master_address,                                 --                 nios2_data_master.address
+			nios2_data_master_waitrequest           => nios2_data_master_waitrequest,                             --                                  .waitrequest
+			nios2_data_master_byteenable            => nios2_data_master_byteenable,                              --                                  .byteenable
+			nios2_data_master_read                  => nios2_data_master_read,                                    --                                  .read
+			nios2_data_master_readdata              => nios2_data_master_readdata,                                --                                  .readdata
+			nios2_data_master_write                 => nios2_data_master_write,                                   --                                  .write
+			nios2_data_master_writedata             => nios2_data_master_writedata,                               --                                  .writedata
+			nios2_data_master_debugaccess           => nios2_data_master_debugaccess,                             --                                  .debugaccess
+			nios2_instruction_master_address        => nios2_instruction_master_address,                          --          nios2_instruction_master.address
+			nios2_instruction_master_waitrequest    => nios2_instruction_master_waitrequest,                      --                                  .waitrequest
+			nios2_instruction_master_read           => nios2_instruction_master_read,                             --                                  .read
+			nios2_instruction_master_readdata       => nios2_instruction_master_readdata,                         --                                  .readdata
+			jtag_uart_avalon_jtag_slave_address     => mm_interconnect_0_jtag_uart_avalon_jtag_slave_address,     --       jtag_uart_avalon_jtag_slave.address
+			jtag_uart_avalon_jtag_slave_write       => mm_interconnect_0_jtag_uart_avalon_jtag_slave_write,       --                                  .write
+			jtag_uart_avalon_jtag_slave_read        => mm_interconnect_0_jtag_uart_avalon_jtag_slave_read,        --                                  .read
+			jtag_uart_avalon_jtag_slave_readdata    => mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata,    --                                  .readdata
+			jtag_uart_avalon_jtag_slave_writedata   => mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata,   --                                  .writedata
+			jtag_uart_avalon_jtag_slave_waitrequest => mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest, --                                  .waitrequest
+			jtag_uart_avalon_jtag_slave_chipselect  => mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect,  --                                  .chipselect
+			nios2_debug_mem_slave_address           => mm_interconnect_0_nios2_debug_mem_slave_address,           --             nios2_debug_mem_slave.address
+			nios2_debug_mem_slave_write             => mm_interconnect_0_nios2_debug_mem_slave_write,             --                                  .write
+			nios2_debug_mem_slave_read              => mm_interconnect_0_nios2_debug_mem_slave_read,              --                                  .read
+			nios2_debug_mem_slave_readdata          => mm_interconnect_0_nios2_debug_mem_slave_readdata,          --                                  .readdata
+			nios2_debug_mem_slave_writedata         => mm_interconnect_0_nios2_debug_mem_slave_writedata,         --                                  .writedata
+			nios2_debug_mem_slave_byteenable        => mm_interconnect_0_nios2_debug_mem_slave_byteenable,        --                                  .byteenable
+			nios2_debug_mem_slave_waitrequest       => mm_interconnect_0_nios2_debug_mem_slave_waitrequest,       --                                  .waitrequest
+			nios2_debug_mem_slave_debugaccess       => mm_interconnect_0_nios2_debug_mem_slave_debugaccess,       --                                  .debugaccess
+			onchip_memory2_s1_address               => mm_interconnect_0_onchip_memory2_s1_address,               --                 onchip_memory2_s1.address
+			onchip_memory2_s1_write                 => mm_interconnect_0_onchip_memory2_s1_write,                 --                                  .write
+			onchip_memory2_s1_readdata              => mm_interconnect_0_onchip_memory2_s1_readdata,              --                                  .readdata
+			onchip_memory2_s1_writedata             => mm_interconnect_0_onchip_memory2_s1_writedata,             --                                  .writedata
+			onchip_memory2_s1_byteenable            => mm_interconnect_0_onchip_memory2_s1_byteenable,            --                                  .byteenable
+			onchip_memory2_s1_chipselect            => mm_interconnect_0_onchip_memory2_s1_chipselect,            --                                  .chipselect
+			onchip_memory2_s1_clken                 => mm_interconnect_0_onchip_memory2_s1_clken,                 --                                  .clken
+			pio_LED_s1_address                      => mm_interconnect_0_pio_led_s1_address,                      --                        pio_LED_s1.address
+			pio_LED_s1_write                        => mm_interconnect_0_pio_led_s1_write,                        --                                  .write
+			pio_LED_s1_readdata                     => mm_interconnect_0_pio_led_s1_readdata,                     --                                  .readdata
+			pio_LED_s1_writedata                    => mm_interconnect_0_pio_led_s1_writedata,                    --                                  .writedata
+			pio_LED_s1_chipselect                   => mm_interconnect_0_pio_led_s1_chipselect                    --                                  .chipselect
+		);
+
+	irq_mapper : component nios2_uc_irq_mapper
+		port map (
+			clk           => clk_clk,                        --       clk.clk
+			reset         => rst_controller_reset_out_reset, -- clk_reset.reset
+			receiver0_irq => irq_mapper_receiver0_irq,       -- receiver0.irq
+			sender_irq    => nios2_irq_irq                   --    sender.irq
+		);
+
+	rst_controller : component altera_reset_controller
+		generic map (
+			NUM_RESET_INPUTS          => 2,
+			OUTPUT_RESET_SYNC_EDGES   => "deassert",
+			SYNC_DEPTH                => 2,
+			RESET_REQUEST_PRESENT     => 1,
+			RESET_REQ_WAIT_TIME       => 1,
+			MIN_RST_ASSERTION_TIME    => 3,
+			RESET_REQ_EARLY_DSRT_TIME => 1,
+			USE_RESET_REQUEST_IN0     => 0,
+			USE_RESET_REQUEST_IN1     => 0,
+			USE_RESET_REQUEST_IN2     => 0,
+			USE_RESET_REQUEST_IN3     => 0,
+			USE_RESET_REQUEST_IN4     => 0,
+			USE_RESET_REQUEST_IN5     => 0,
+			USE_RESET_REQUEST_IN6     => 0,
+			USE_RESET_REQUEST_IN7     => 0,
+			USE_RESET_REQUEST_IN8     => 0,
+			USE_RESET_REQUEST_IN9     => 0,
+			USE_RESET_REQUEST_IN10    => 0,
+			USE_RESET_REQUEST_IN11    => 0,
+			USE_RESET_REQUEST_IN12    => 0,
+			USE_RESET_REQUEST_IN13    => 0,
+			USE_RESET_REQUEST_IN14    => 0,
+			USE_RESET_REQUEST_IN15    => 0,
+			ADAPT_RESET_REQUEST       => 0
+		)
+		port map (
+			reset_in0      => reset_reset_n_ports_inv,            -- reset_in0.reset
+			reset_in1      => nios2_debug_reset_request_reset,    -- reset_in1.reset
+			clk            => clk_clk,                            --       clk.clk
+			reset_out      => rst_controller_reset_out_reset,     -- reset_out.reset
+			reset_req      => rst_controller_reset_out_reset_req, --          .reset_req
+			reset_req_in0  => '0',                                -- (terminated)
+			reset_req_in1  => '0',                                -- (terminated)
+			reset_in2      => '0',                                -- (terminated)
+			reset_req_in2  => '0',                                -- (terminated)
+			reset_in3      => '0',                                -- (terminated)
+			reset_req_in3  => '0',                                -- (terminated)
+			reset_in4      => '0',                                -- (terminated)
+			reset_req_in4  => '0',                                -- (terminated)
+			reset_in5      => '0',                                -- (terminated)
+			reset_req_in5  => '0',                                -- (terminated)
+			reset_in6      => '0',                                -- (terminated)
+			reset_req_in6  => '0',                                -- (terminated)
+			reset_in7      => '0',                                -- (terminated)
+			reset_req_in7  => '0',                                -- (terminated)
+			reset_in8      => '0',                                -- (terminated)
+			reset_req_in8  => '0',                                -- (terminated)
+			reset_in9      => '0',                                -- (terminated)
+			reset_req_in9  => '0',                                -- (terminated)
+			reset_in10     => '0',                                -- (terminated)
+			reset_req_in10 => '0',                                -- (terminated)
+			reset_in11     => '0',                                -- (terminated)
+			reset_req_in11 => '0',                                -- (terminated)
+			reset_in12     => '0',                                -- (terminated)
+			reset_req_in12 => '0',                                -- (terminated)
+			reset_in13     => '0',                                -- (terminated)
+			reset_req_in13 => '0',                                -- (terminated)
+			reset_in14     => '0',                                -- (terminated)
+			reset_req_in14 => '0',                                -- (terminated)
+			reset_in15     => '0',                                -- (terminated)
+			reset_req_in15 => '0'                                 -- (terminated)
+		);
+
+	reset_reset_n_ports_inv <= not reset_reset_n;
+
+	mm_interconnect_0_jtag_uart_avalon_jtag_slave_read_ports_inv <= not mm_interconnect_0_jtag_uart_avalon_jtag_slave_read;
+
+	mm_interconnect_0_jtag_uart_avalon_jtag_slave_write_ports_inv <= not mm_interconnect_0_jtag_uart_avalon_jtag_slave_write;
+
+	mm_interconnect_0_pio_led_s1_write_ports_inv <= not mm_interconnect_0_pio_led_s1_write;
+
+	rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
+
+end architecture rtl; -- of nios2_uc

nios2_uc/synthesis/submodules/altera_avalon_sc_fifo.v

@@ -0,0 +1,915 @@
+// -----------------------------------------------------------
+// Legal Notice: (C)2007 Altera Corporation. All rights reserved.  Your
+// use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any
+// output files any of the foregoing (including device programming or
+// simulation files), and any associated documentation or information are
+// expressly subject to the terms and conditions of the Altera Program
+// License Subscription Agreement or other applicable license agreement,
+// including, without limitation, that your use is for the sole purpose
+// of programming logic devices manufactured by Altera and sold by Altera
+// or its authorized distributors.  Please refer to the applicable
+// agreement for further details.
+//
+// Description: Single clock Avalon-ST FIFO.
+// -----------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+//altera message_off 10036
+module altera_avalon_sc_fifo
+#(
+    // --------------------------------------------------
+    // Parameters
+    // --------------------------------------------------
+    parameter SYMBOLS_PER_BEAT  = 1,
+    parameter BITS_PER_SYMBOL   = 8,
+    parameter FIFO_DEPTH        = 16,
+    parameter CHANNEL_WIDTH     = 0,
+    parameter ERROR_WIDTH       = 0,
+    parameter USE_PACKETS       = 0,
+    parameter USE_FILL_LEVEL    = 0,
+    parameter USE_STORE_FORWARD = 0,
+    parameter USE_ALMOST_FULL_IF = 0,
+    parameter USE_ALMOST_EMPTY_IF = 0,
+
+    // --------------------------------------------------
+    // Empty latency is defined as the number of cycles
+    // required for a write to deassert the empty flag.
+    // For example, a latency of 1 means that the empty
+    // flag is deasserted on the cycle after a write.
+    //
+    // Another way to think of it is the latency for a
+    // write to propagate to the output. 
+    // 
+    // An empty latency of 0 implies lookahead, which is
+    // only implemented for the register-based FIFO.
+    // --------------------------------------------------
+    parameter EMPTY_LATENCY     = 3,
+    parameter USE_MEMORY_BLOCKS = 1,
+
+    // --------------------------------------------------
+    // Internal Parameters
+    // --------------------------------------------------
+    parameter DATA_WIDTH  = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
+    parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
+)
+(
+    // --------------------------------------------------
+    // Ports
+    // --------------------------------------------------
+    input                       clk,
+    input                       reset,
+
+    input [DATA_WIDTH-1: 0]     in_data,
+    input                       in_valid,
+    input                       in_startofpacket,
+    input                       in_endofpacket,
+    input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0]     in_empty,
+    input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0]     in_error,
+    input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0]  in_channel,
+    output                      in_ready,
+
+    output [DATA_WIDTH-1 : 0]   out_data,
+    output reg                  out_valid,
+    output                      out_startofpacket,
+    output                      out_endofpacket,
+    output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0]    out_empty,
+    output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0]    out_error,
+    output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
+    input                       out_ready,
+
+    input [(USE_STORE_FORWARD ? 2 : 1) : 0]   csr_address,
+    input                       csr_write,
+    input                       csr_read,
+    input [31 : 0]              csr_writedata,
+    output reg [31 : 0]         csr_readdata,
+
+    output  wire                almost_full_data,
+    output  wire                almost_empty_data
+);
+
+    // --------------------------------------------------
+    // Local Parameters
+    // --------------------------------------------------
+    localparam ADDR_WIDTH   = log2ceil(FIFO_DEPTH);
+    localparam DEPTH        = FIFO_DEPTH;
+    localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
+    localparam PAYLOAD_WIDTH     = (USE_PACKETS == 1) ? 
+                   2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
+                   DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
+
+    // --------------------------------------------------
+    // Internal Signals
+    // --------------------------------------------------
+    genvar i;
+
+    reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
+    reg [ADDR_WIDTH-1 : 0]  wr_ptr;
+    reg [ADDR_WIDTH-1 : 0]  rd_ptr;
+    reg [DEPTH-1      : 0]  mem_used;
+
+    wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
+    wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
+    wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
+    wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
+
+    wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
+
+    wire read;
+    wire write;
+
+    reg empty;
+    reg next_empty;
+    reg full;
+    reg next_full;
+
+    wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
+    wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
+    wire [PAYLOAD_WIDTH-1 : 0] in_payload;
+    reg  [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
+    reg  [PAYLOAD_WIDTH-1 : 0] out_payload;
+
+    reg  internal_out_valid;
+    wire internal_out_ready;
+
+    reg  [ADDR_WIDTH : 0] fifo_fill_level;
+    reg  [ADDR_WIDTH : 0] fill_level;
+
+    reg  [ADDR_WIDTH-1 : 0]   sop_ptr = 0;
+    wire [ADDR_WIDTH-1 : 0]   curr_sop_ptr;
+    reg  [23:0]   almost_full_threshold;
+    reg  [23:0]   almost_empty_threshold;
+    reg  [23:0]   cut_through_threshold;
+    reg  [15:0]   pkt_cnt;
+    reg           drop_on_error_en;
+    reg           error_in_pkt;
+    reg           pkt_has_started;
+    reg           sop_has_left_fifo;
+    reg           fifo_too_small_r;
+    reg           pkt_cnt_eq_zero;
+    reg           pkt_cnt_eq_one;
+
+    wire          wait_for_threshold;
+    reg           pkt_mode;
+    wire          wait_for_pkt;
+    wire          ok_to_forward;
+    wire          in_pkt_eop_arrive;
+    wire          out_pkt_leave;
+    wire          in_pkt_start;
+    wire          in_pkt_error;
+    wire          drop_on_error;
+    wire          fifo_too_small;
+    wire          out_pkt_sop_leave;
+    wire [31:0]   max_fifo_size;
+    reg           fifo_fill_level_lt_cut_through_threshold;
+
+    // --------------------------------------------------
+    // Define Payload
+    //
+    // Icky part where we decide which signals form the
+    // payload to the FIFO with generate blocks.
+    // --------------------------------------------------
+    generate
+        if (EMPTY_WIDTH > 0) begin : gen_blk1
+            assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
+            assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
+        end 
+        else begin : gen_blk1_else
+            assign out_empty = in_error;
+            assign in_packet_signals = {in_startofpacket, in_endofpacket};
+            assign {out_startofpacket, out_endofpacket} = out_packet_signals;
+        end
+    endgenerate
+
+    generate
+        if (USE_PACKETS) begin : gen_blk2
+            if (ERROR_WIDTH > 0) begin : gen_blk3
+                if (CHANNEL_WIDTH > 0) begin : gen_blk4
+                    assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
+                    assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
+                end
+                else begin : gen_blk4_else
+                    assign out_channel = in_channel;
+                    assign in_payload = {in_packet_signals, in_data, in_error};
+                    assign {out_packet_signals, out_data, out_error} = out_payload;
+                end
+            end
+            else begin : gen_blk3_else
+                assign out_error = in_error;
+                if (CHANNEL_WIDTH > 0) begin : gen_blk5
+                    assign in_payload = {in_packet_signals, in_data, in_channel};
+                    assign {out_packet_signals, out_data, out_channel} = out_payload;
+                end
+                else begin : gen_blk5_else
+                    assign out_channel = in_channel;
+                    assign in_payload = {in_packet_signals, in_data};
+                    assign {out_packet_signals, out_data} = out_payload;
+                end
+            end
+        end
+        else begin : gen_blk2_else
+            assign out_packet_signals = 0;
+            if (ERROR_WIDTH > 0) begin : gen_blk6
+                if (CHANNEL_WIDTH > 0) begin : gen_blk7
+                    assign in_payload = {in_data, in_error, in_channel};
+                    assign {out_data, out_error, out_channel} = out_payload;
+                end
+                else begin : gen_blk7_else
+                    assign out_channel = in_channel;
+                    assign in_payload = {in_data, in_error};
+                    assign {out_data, out_error} = out_payload;
+                end
+            end
+            else begin : gen_blk6_else
+                assign out_error = in_error;
+                if (CHANNEL_WIDTH > 0) begin : gen_blk8
+                    assign in_payload = {in_data, in_channel};
+                    assign {out_data, out_channel} = out_payload;
+                end
+                else begin : gen_blk8_else
+                    assign out_channel = in_channel;
+                    assign in_payload = in_data;
+                    assign out_data = out_payload;
+                end
+            end
+        end
+    endgenerate
+
+    // --------------------------------------------------
+    // Memory-based FIFO storage
+    //
+    // To allow a ready latency of 0, the read index is 
+    // obtained from the next read pointer and memory 
+    // outputs are unregistered.
+    //
+    // If the empty latency is 1, we infer bypass logic
+    // around the memory so writes propagate to the
+    // outputs on the next cycle.
+    //
+    // Do not change the way this is coded: Quartus needs
+    // a perfect match to the template, and any attempt to 
+    // refactor the two always blocks into one will break
+    // memory inference.
+    // --------------------------------------------------
+    generate if (USE_MEMORY_BLOCKS == 1) begin  : gen_blk9
+
+        if (EMPTY_LATENCY == 1) begin : gen_blk10
+
+            always @(posedge clk) begin
+                if (in_valid && in_ready)
+                    mem[wr_ptr] = in_payload;
+
+                internal_out_payload = mem[mem_rd_ptr];
+            end
+
+        end else begin : gen_blk10_else
+
+            always @(posedge clk) begin
+                if (in_valid && in_ready)
+                    mem[wr_ptr] <= in_payload;
+
+                internal_out_payload <= mem[mem_rd_ptr];
+            end
+
+        end
+
+        assign mem_rd_ptr = next_rd_ptr;
+    
+    end else begin : gen_blk9_else
+
+    // --------------------------------------------------
+    // Register-based FIFO storage
+    //
+    // Uses a shift register as the storage element. Each
+    // shift register slot has a bit which indicates if
+    // the slot is occupied (credit to Sam H for the idea).
+    // The occupancy bits are contiguous and start from the
+    // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
+    // FIFO.
+    // 
+    // Each slot is enabled during a read or when it
+    // is unoccupied. New data is always written to every
+    // going-to-be-empty slot (we keep track of which ones
+    // are actually useful with the occupancy bits). On a
+    // read we shift occupied slots.
+    // 
+    // The exception is the last slot, which always gets 
+    // new data when it is unoccupied.
+    // --------------------------------------------------
+        for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    mem[i] <= 0;
+                end 
+                else if (read || !mem_used[i]) begin
+                    if (!mem_used[i+1])
+                        mem[i] <= in_payload;
+                    else
+                        mem[i] <= mem[i+1];
+                end
+            end
+        end
+
+        always @(posedge clk, posedge reset) begin
+            if (reset) begin
+                mem[DEPTH-1] <= 0;
+            end 
+            else begin
+                if (DEPTH == 1) begin
+                    if (write)
+                        mem[DEPTH-1] <= in_payload;
+                end
+                else if (!mem_used[DEPTH-1])
+                    mem[DEPTH-1] <= in_payload;    
+            end
+        end
+
+    end
+    endgenerate
+
+    assign read  = internal_out_ready && internal_out_valid  && ok_to_forward;
+    assign write = in_ready && in_valid;
+
+    // --------------------------------------------------
+    // Pointer Management
+    // --------------------------------------------------
+    generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
+
+        assign incremented_wr_ptr = wr_ptr + 1'b1;
+        assign incremented_rd_ptr = rd_ptr + 1'b1;
+        assign next_wr_ptr =  drop_on_error ? curr_sop_ptr : write ?  incremented_wr_ptr : wr_ptr;
+        assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
+
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                wr_ptr <= 0;
+                rd_ptr <= 0;
+            end
+            else begin
+                wr_ptr <= next_wr_ptr;
+                rd_ptr <= next_rd_ptr;
+            end
+        end
+
+    end else begin : gen_blk11_else
+
+    // --------------------------------------------------
+    // Shift Register Occupancy Bits
+    //
+    // Consider a 4-deep FIFO with 2 entries: 0011
+    // On a read and write, do not modify the bits.
+    // On a write, left-shift the bits to get 0111.
+    // On a read, right-shift the bits to get 0001.
+    //
+    // Also, on a write we set bit0 (the head), while
+    // clearing the tail on a read.
+    // --------------------------------------------------
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                mem_used[0] <= 0;
+            end 
+            else begin
+                if (write ^ read) begin
+                    if (write)
+                        mem_used[0] <= 1;
+                    else if (read) begin
+                        if (DEPTH > 1)
+                            mem_used[0] <= mem_used[1];
+                        else
+                            mem_used[0] <= 0;
+                    end    
+                end
+            end
+        end
+
+        if (DEPTH > 1) begin : gen_blk12
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    mem_used[DEPTH-1] <= 0;
+                end
+                else begin 
+                    if (write ^ read) begin            
+                        mem_used[DEPTH-1] <= 0;
+                        if (write)
+                            mem_used[DEPTH-1] <= mem_used[DEPTH-2];
+                    end
+                end
+            end
+          end
+     
+        for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
+            always @(posedge clk, posedge reset) begin
+                if (reset) begin
+                    mem_used[i] <= 0;
+                end 
+                else begin
+                    if (write ^ read) begin
+                        if (write)
+                            mem_used[i] <= mem_used[i-1];
+                        else if (read)
+                            mem_used[i] <= mem_used[i+1];     
+                    end
+                end
+            end
+        end
+     
+    end
+    endgenerate
+
+
+    // --------------------------------------------------
+    // Memory FIFO Status Management
+    //
+    // Generates the full and empty signals from the
+    // pointers. The FIFO is full when the next write 
+    // pointer will be equal to the read pointer after
+    // a write. Reading from a FIFO clears full.
+    //
+    // The FIFO is empty when the next read pointer will
+    // be equal to the write pointer after a read. Writing
+    // to a FIFO clears empty.
+    //
+    // A simultaneous read and write must not change any of 
+    // the empty or full flags unless there is a drop on error event.
+    // --------------------------------------------------
+    generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
+
+        always @* begin
+            next_full = full;
+            next_empty = empty;
+     
+            if (read && !write) begin
+                next_full = 1'b0;
+     
+                if (incremented_rd_ptr == wr_ptr)
+                    next_empty = 1'b1;
+            end
+            
+            if (write && !read) begin
+                if (!drop_on_error)
+                  next_empty = 1'b0;
+                else if (curr_sop_ptr == rd_ptr)   // drop on error and only 1 pkt in fifo
+                  next_empty = 1'b1;
+     
+                if (incremented_wr_ptr == rd_ptr && !drop_on_error)
+                    next_full = 1'b1;
+            end
+
+            if (write && read && drop_on_error) begin
+                if (curr_sop_ptr == next_rd_ptr)
+                  next_empty = 1'b1;
+            end
+        end
+     
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                empty <= 1;
+                full  <= 0;
+            end
+            else begin 
+                empty <= next_empty;
+                full  <= next_full;
+            end
+        end
+
+    end else begin : gen_blk13_else
+    // --------------------------------------------------
+    // Register FIFO Status Management
+    //
+    // Full when the tail occupancy bit is 1. Empty when
+    // the head occupancy bit is 0.
+    // --------------------------------------------------
+        always @* begin
+            full  = mem_used[DEPTH-1];
+            empty = !mem_used[0];
+
+            // ------------------------------------------
+            // For a single slot FIFO, reading clears the
+            // full status immediately.
+            // ------------------------------------------
+            if (DEPTH == 1)
+                full = mem_used[0] && !read;
+
+            internal_out_payload = mem[0];
+
+            // ------------------------------------------
+            // Writes clear empty immediately for lookahead modes.
+            // Note that we use in_valid instead of write to avoid
+            // combinational loops (in lookahead mode, qualifying
+            // with in_ready is meaningless).
+            //
+            // In a 1-deep FIFO, a possible combinational loop runs
+            // from write -> out_valid -> out_ready -> write
+            // ------------------------------------------
+            if (EMPTY_LATENCY == 0) begin
+                empty = !mem_used[0] && !in_valid;
+
+                if (!mem_used[0] && in_valid)
+                    internal_out_payload = in_payload;
+            end
+        end
+
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Avalon-ST Signals
+    //
+    // The in_ready signal is straightforward. 
+    //
+    // To match memory latency when empty latency > 1, 
+    // out_valid assertions must be delayed by one clock
+    // cycle.
+    //
+    // Note: out_valid deassertions must not be delayed or 
+    // the FIFO will underflow.
+    // --------------------------------------------------
+    assign in_ready = !full;
+    assign internal_out_ready = out_ready || !out_valid;
+
+    generate if (EMPTY_LATENCY > 1) begin : gen_blk14
+        always @(posedge clk or posedge reset) begin
+            if (reset)
+                internal_out_valid <= 0;
+            else begin
+                internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
+
+                if (read) begin
+                    if (incremented_rd_ptr == wr_ptr)
+                        internal_out_valid <= 1'b0;
+                end
+            end
+        end
+    end else begin : gen_blk14_else
+        always @* begin
+            internal_out_valid = !empty & ok_to_forward;
+        end
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Single Output Pipeline Stage
+    //
+    // This output pipeline stage is enabled if the FIFO's 
+    // empty latency is set to 3 (default). It is disabled
+    // for all other allowed latencies.
+    //
+    // Reason: The memory outputs are unregistered, so we have to
+    // register the output or fmax will drop if combinatorial
+    // logic is present on the output datapath.
+    // 
+    // Q: The Avalon-ST spec says that I have to register my outputs
+    //    But isn't the memory counted as a register?
+    // A: The path from the address lookup to the memory output is
+    //    slow. Registering the memory outputs is a good idea. 
+    //
+    // The registers get packed into the memory by the fitter
+    // which means minimal resources are consumed (the result
+    // is a altsyncram with registered outputs, available on 
+    // all modern Altera devices). 
+    //
+    // This output stage acts as an extra slot in the FIFO, 
+    // and complicates the fill level.
+    // --------------------------------------------------
+    generate if (EMPTY_LATENCY == 3) begin : gen_blk15
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                out_valid   <= 0;
+                out_payload <= 0;
+            end
+            else begin
+                if (internal_out_ready) begin
+                    out_valid   <= internal_out_valid & ok_to_forward;
+                    out_payload <= internal_out_payload;
+                end
+            end
+        end
+    end
+    else begin : gen_blk15_else
+        always @* begin
+            out_valid   = internal_out_valid;
+            out_payload = internal_out_payload;
+        end
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Fill Level
+    //
+    // The fill level is calculated from the next write
+    // and read pointers to avoid unnecessary latency
+    // and logic.
+    //
+    // However, if the store-and-forward mode of the FIFO
+    // is enabled, the fill level is an up-down counter
+    // for fmax optimization reasons.
+    //
+    // If the output pipeline is enabled, the fill level 
+    // must account for it, or we'll always be off by one.
+    // This may, or may not be important depending on the
+    // application.
+    //
+    // For now, we'll always calculate the exact fill level
+    // at the cost of an extra adder when the output stage
+    // is enabled.
+    // --------------------------------------------------
+    generate if (USE_FILL_LEVEL) begin : gen_blk16
+        wire [31:0] depth32;
+        assign depth32 = DEPTH;
+
+        if (USE_STORE_FORWARD) begin
+
+            reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
+            
+            // --------------------------------------------------
+            // We only drop on endofpacket. As long as we don't add to the fill
+            // level on the dropped endofpacket cycle, we can simply subtract
+            // (packet length - 1) from the fill level for dropped packets.
+            // --------------------------------------------------
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    curr_packet_len_less_one <= 0;
+                end else begin
+                    if (write) begin
+                        curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
+                        if (in_endofpacket)
+                            curr_packet_len_less_one <= 0;
+                    end
+                end
+            end
+
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    fifo_fill_level <= 0;
+                end else if (drop_on_error) begin
+                    fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
+                    if (read)
+                        fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
+                end else if (write && !read) begin
+                    fifo_fill_level <= fifo_fill_level + 1'b1;
+                end else if (read && !write) begin
+                    fifo_fill_level <= fifo_fill_level - 1'b1;
+                end
+            end
+
+        end else begin
+
+            always @(posedge clk or posedge reset) begin
+                if (reset) 
+                    fifo_fill_level <= 0;
+                else if (next_full & !drop_on_error)
+                    fifo_fill_level <= depth32[ADDR_WIDTH:0];
+                else begin
+                    fifo_fill_level[ADDR_WIDTH]     <= 1'b0;
+                    fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
+                end
+            end
+
+        end
+
+        always @* begin
+            fill_level = fifo_fill_level;
+
+            if (EMPTY_LATENCY == 3)
+                fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
+        end
+    end
+    else begin : gen_blk16_else
+        always @* begin
+            fill_level = 0;
+        end  
+    end
+    endgenerate
+
+    generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
+      assign almost_full_data = (fill_level >= almost_full_threshold);
+    end
+    else
+      assign almost_full_data = 0;
+    endgenerate
+
+    generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
+      assign almost_empty_data = (fill_level <= almost_empty_threshold);
+    end
+    else
+      assign almost_empty_data = 0;
+    endgenerate
+
+    // --------------------------------------------------
+    // Avalon-MM Status & Control Connection Point
+    //
+    // Register map:
+    //
+    // | Addr   | RW |     31 - 0      |
+    // |  0     | R  |   Fill level    |
+    //
+    // The registering of this connection point means
+    // that there is a cycle of latency between 
+    // reads/writes and the updating of the fill level.
+    // --------------------------------------------------
+    generate if (USE_STORE_FORWARD) begin : gen_blk19
+    assign max_fifo_size = FIFO_DEPTH - 1;
+      always @(posedge clk or posedge reset) begin
+          if (reset) begin
+              almost_full_threshold  <= max_fifo_size[23 : 0];
+              almost_empty_threshold <= 0;
+              cut_through_threshold  <= 0;
+              drop_on_error_en       <= 0;
+              csr_readdata           <= 0;
+              pkt_mode               <= 1'b1;
+          end
+          else begin
+              if (csr_read) begin
+                csr_readdata <= 32'b0;
+                if (csr_address == 5)
+                    csr_readdata <= {31'b0, drop_on_error_en};
+                else if (csr_address == 4)
+                    csr_readdata <= {8'b0, cut_through_threshold};
+                else if (csr_address == 3)
+                    csr_readdata <= {8'b0, almost_empty_threshold};
+                else if (csr_address == 2)
+                    csr_readdata <= {8'b0, almost_full_threshold};
+                else if (csr_address == 0)
+                    csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+             end
+             else if (csr_write) begin
+               if(csr_address == 3'b101)
+                   drop_on_error_en       <= csr_writedata[0];
+               else if(csr_address == 3'b100) begin
+                   cut_through_threshold  <= csr_writedata[23:0];
+                   pkt_mode <= (csr_writedata[23:0] == 0);
+               end
+               else if(csr_address == 3'b011)
+                    almost_empty_threshold <= csr_writedata[23:0];
+               else if(csr_address == 3'b010)
+                  almost_full_threshold  <= csr_writedata[23:0];
+             end     
+          end
+      end
+    end
+    else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
+    assign max_fifo_size = FIFO_DEPTH - 1;
+      always @(posedge clk or posedge reset) begin
+          if (reset) begin
+              almost_full_threshold  <= max_fifo_size[23 : 0];
+              almost_empty_threshold <= 0;
+              csr_readdata           <= 0;
+          end
+          else begin
+             if (csr_read) begin
+                csr_readdata <= 32'b0;
+                if (csr_address == 3)
+                    csr_readdata <= {8'b0, almost_empty_threshold};
+                else if (csr_address == 2)
+                    csr_readdata <= {8'b0, almost_full_threshold};
+                else if (csr_address == 0)
+                    csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+             end
+             else if (csr_write) begin
+               if(csr_address == 3'b011)
+                   almost_empty_threshold <= csr_writedata[23:0];
+               else if(csr_address == 3'b010)
+                  almost_full_threshold  <= csr_writedata[23:0];
+             end       
+          end
+      end
+    end
+    else begin : gen_blk19_else2
+      always @(posedge clk or posedge reset) begin
+          if (reset) begin
+              csr_readdata <= 0;
+          end
+          else if (csr_read) begin
+              csr_readdata <= 0;
+
+              if (csr_address == 0) 
+                  csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+          end
+      end
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Store and forward logic
+    // --------------------------------------------------
+    // if the fifo gets full before the entire packet or the
+    // cut-threshold condition is met then start sending out
+    // data in order to avoid dead-lock situation
+
+    generate if (USE_STORE_FORWARD) begin : gen_blk20
+      assign wait_for_threshold   = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
+      assign wait_for_pkt         = pkt_cnt_eq_zero  | (pkt_cnt_eq_one  & out_pkt_leave);
+      assign ok_to_forward        = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : 
+                                     ~wait_for_threshold) | fifo_too_small_r;
+      assign in_pkt_eop_arrive    = in_valid & in_ready & in_endofpacket;
+      assign in_pkt_start         = in_valid & in_ready & in_startofpacket;
+      assign in_pkt_error         = in_valid & in_ready & |in_error;
+      assign out_pkt_sop_leave    = out_valid & out_ready & out_startofpacket;
+      assign out_pkt_leave        = out_valid & out_ready & out_endofpacket;
+      assign fifo_too_small       = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
+
+      // count packets coming and going into the fifo
+      always @(posedge clk or posedge reset) begin
+        if (reset) begin
+          pkt_cnt           <= 0;
+          pkt_has_started   <= 0;
+          sop_has_left_fifo <= 0;
+          fifo_too_small_r  <= 0;
+          pkt_cnt_eq_zero   <= 1'b1;
+          pkt_cnt_eq_one    <= 1'b0;
+          fifo_fill_level_lt_cut_through_threshold <= 1'b1;
+        end
+        else begin
+          fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
+          fifo_too_small_r <= fifo_too_small;
+
+          if( in_pkt_eop_arrive )
+            sop_has_left_fifo <= 1'b0;
+          else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
+            sop_has_left_fifo <= 1'b1;
+
+          if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
+            pkt_cnt <= pkt_cnt + 1'b1;
+            pkt_cnt_eq_zero <= 0;
+            if (pkt_cnt == 0)
+              pkt_cnt_eq_one <= 1'b1;
+            else
+              pkt_cnt_eq_one <= 1'b0;
+          end
+          else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
+            pkt_cnt <= pkt_cnt - 1'b1;
+            if (pkt_cnt == 1) 
+              pkt_cnt_eq_zero <= 1'b1;
+            else
+              pkt_cnt_eq_zero <= 1'b0;
+            if (pkt_cnt == 2) 
+              pkt_cnt_eq_one <= 1'b1;
+            else
+              pkt_cnt_eq_one <= 1'b0;
+          end
+
+          if (in_pkt_start)
+            pkt_has_started <= 1'b1;
+          else if (in_pkt_eop_arrive)
+            pkt_has_started <= 1'b0;
+        end
+      end
+
+      // drop on error logic
+      always @(posedge clk or posedge reset) begin
+        if (reset) begin
+          sop_ptr <= 0;
+          error_in_pkt <= 0;
+        end
+        else begin
+          // save the location of the SOP
+          if ( in_pkt_start ) 
+            sop_ptr <= wr_ptr;
+
+          // remember if error in pkt
+          // log error only if packet has already started
+          if (in_pkt_eop_arrive)
+            error_in_pkt <= 1'b0;
+          else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
+            error_in_pkt <= 1'b1;
+        end
+      end
+
+      assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & 
+                            ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
+
+      assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
+
+    end
+    else begin : gen_blk20_else
+      assign ok_to_forward = 1'b1;
+      assign drop_on_error = 1'b0;
+      if (ADDR_WIDTH <= 1)
+        assign curr_sop_ptr = 1'b0;
+      else
+        assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
+    end
+    endgenerate
+
+
+    // --------------------------------------------------
+    // Calculates the log2ceil of the input value
+    // --------------------------------------------------
+    function integer log2ceil;
+        input integer val;
+        reg[31:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i[30:0] << 1;
+            end
+        end
+    endfunction
+
+endmodule

nios2_uc/synthesis/submodules/altera_merlin_arbitrator.sv

@@ -0,0 +1,272 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
+// $Revision: #3 $
+// $Date: 2010/07/07 $
+// $Author: jyeap $
+
+/* -----------------------------------------------------------------------
+Round-robin/fixed arbitration implementation.
+
+Q: how do you find the least-significant set-bit in an n-bit binary number, X?
+
+A: M = X & (~X + 1)
+
+Example: X = 101000100
+ 101000100 & 
+ 010111011 + 1 =
+
+ 101000100 &
+ 010111100 =
+ -----------
+ 000000100
+
+The method can be generalized to find the first set-bit
+at a bit index no lower than bit-index N, simply by adding
+2**N rather than 1.
+
+
+Q: how does this relate to round-robin arbitration?
+A:
+Let X be the concatenation of all request signals.
+Let the number to be added to X (hereafter called the
+top_priority) initialize to 1, and be assigned from the
+concatenation of the previous saved-grant, left-rotated
+by one position, each time arbitration occurs.  The
+concatenation of grants is then M.
+
+Problem: consider this case:
+
+top_priority            = 010000
+request                 = 001001
+~request + top_priority = 000110
+next_grant              = 000000 <- no one is granted!
+
+There was no "set bit at a bit index no lower than bit-index 4", so 
+the result was 0.
+
+We need to propagate the carry out from (~request + top_priority) to the LSB, so
+that the sum becomes 000111, and next_grant is 000001.  This operation could be
+called a "circular add". 
+
+A bit of experimentation on the circular add reveals a significant amount of 
+delay in exiting and re-entering the carry chain - this will vary with device
+family.  Quartus also reports a combinational loop warning.  Finally, 
+Modelsim 6.3g has trouble with the expression, evaluating it to 'X'.  But 
+Modelsim _doesn't_ report a combinational loop!)
+
+An alternate solution: concatenate the request vector with itself, and OR
+corresponding bits from the top and bottom halves to determine next_grant.
+
+Example:
+
+top_priority                        =        010000
+{request, request}                  = 001001 001001
+{~request, ~request} + top_priority = 110111 000110
+result of & operation               = 000001 000000
+next_grant                          =        000001
+
+Notice that if request = 0, the sum operation will overflow, but we can ignore
+this; the next_grant result is 0 (no one granted), as you might expect.
+In the implementation, the last-granted value must be maintained as
+a non-zero value - best probably simply not to update it when no requests
+occur.
+
+----------------------------------------------------------------------- */ 
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_arbitrator
+#(
+    parameter NUM_REQUESTERS = 8,
+    // --------------------------------------
+    // Implemented schemes
+    // "round-robin"
+    // "fixed-priority"
+    // "no-arb"
+    // --------------------------------------
+    parameter SCHEME         = "round-robin",
+    parameter PIPELINE       = 0
+)
+(
+    input clk,
+    input reset,
+   
+    // --------------------------------------
+    // Requests
+    // --------------------------------------
+    input [NUM_REQUESTERS-1:0]  request,
+   
+    // --------------------------------------
+    // Grants
+    // --------------------------------------
+    output [NUM_REQUESTERS-1:0] grant,
+
+    // --------------------------------------
+    // Control Signals
+    // --------------------------------------
+    input                       increment_top_priority,
+    input                       save_top_priority
+);
+
+    // --------------------------------------
+    // Signals
+    // --------------------------------------
+    wire [NUM_REQUESTERS-1:0]   top_priority;
+    reg  [NUM_REQUESTERS-1:0]   top_priority_reg;
+    reg  [NUM_REQUESTERS-1:0]   last_grant;
+    wire [2*NUM_REQUESTERS-1:0] result;
+
+    // --------------------------------------
+    // Scheme Selection
+    // --------------------------------------
+    generate
+        if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
+            assign top_priority = top_priority_reg;
+        end
+        else begin
+            // Fixed arbitration (or single-requester corner case)
+            assign top_priority = 1'b1;
+        end
+    endgenerate
+
+    // --------------------------------------
+    // Decision Logic
+    // --------------------------------------
+    altera_merlin_arb_adder
+    #(
+        .WIDTH (2 * NUM_REQUESTERS)
+    ) 
+    adder
+    (
+        .a ({ ~request, ~request }),
+        .b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
+        .sum (result)
+    );
+
+  
+    generate if (SCHEME == "no-arb") begin
+
+        // --------------------------------------
+        // No arbitration: just wire request directly to grant
+        // --------------------------------------
+        assign grant = request;
+
+    end else begin
+        // Do the math in double-vector domain
+        wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
+        assign grant_double_vector = {request, request} & result;
+
+        // --------------------------------------
+        // Extract grant from the top and bottom halves
+        // of the double vector.
+        // --------------------------------------
+        assign grant =
+            grant_double_vector[NUM_REQUESTERS - 1 : 0] |
+            grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
+
+    end
+    endgenerate
+
+    // --------------------------------------
+    // Left-rotate the last grant vector to create top_priority.
+    // --------------------------------------
+    always @(posedge clk or posedge reset) begin
+        if (reset) begin
+            top_priority_reg <= 1'b1;
+        end
+        else begin
+            if (PIPELINE) begin
+                if (increment_top_priority) begin
+                    top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
+                        grant[NUM_REQUESTERS-1]} : top_priority_reg;
+                end
+            end else begin
+                if (increment_top_priority) begin
+                    if (|request)
+                        top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
+                            grant[NUM_REQUESTERS-1] };
+                    else
+                        top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
+                end
+                else if (save_top_priority) begin
+                    top_priority_reg <= grant; 
+                end
+            end
+        end
+    end
+
+endmodule
+
+// ----------------------------------------------
+// Adder for the standard arbitrator
+// ----------------------------------------------
+module altera_merlin_arb_adder
+#(
+    parameter WIDTH = 8
+)
+(
+    input [WIDTH-1:0] a,
+    input [WIDTH-1:0] b,
+
+    output [WIDTH-1:0] sum
+);
+
+    wire [WIDTH:0] sum_lint;
+    // ----------------------------------------------
+    // Benchmarks indicate that for small widths, the full
+    // adder has higher fmax because synthesis can merge
+    // it with the mux, allowing partial decisions to be 
+    // made early.
+    //
+    // The magic number is 4 requesters, which means an
+    // 8 bit adder.
+    // ----------------------------------------------
+    genvar i;
+    generate if (WIDTH <= 8) begin : full_adder
+
+        wire cout[WIDTH-1:0];
+
+        assign sum[0]  = (a[0] ^ b[0]);
+        assign cout[0] = (a[0] & b[0]);
+
+        for (i = 1; i < WIDTH; i = i+1) begin : arb
+
+            assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
+            assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
+
+        end
+
+    end else begin : carry_chain
+
+        assign sum_lint = a + b;
+        assign sum = sum_lint[WIDTH-1:0];
+
+    end
+    endgenerate
+
+endmodule

nios2_uc/synthesis/submodules/altera_merlin_burst_uncompressor.sv

@@ -0,0 +1,296 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Burst Uncompressor
+//
+// Compressed read bursts -> uncompressed
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_burst_uncompressor
+#(
+    parameter ADDR_W      = 16,
+    parameter BURSTWRAP_W = 3,
+    parameter BYTE_CNT_W  = 4,
+    parameter PKT_SYMBOLS = 4,
+    parameter BURST_SIZE_W = 3
+)
+(
+    input clk,
+    input reset,
+   
+    // sink ST signals
+    input sink_startofpacket,
+    input sink_endofpacket,
+    input sink_valid,
+    output sink_ready,
+   
+    // sink ST "data"
+    input [ADDR_W - 1: 0] sink_addr,
+    input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
+    input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
+    input sink_is_compressed,
+    input [BURST_SIZE_W-1 : 0] sink_burstsize,
+   
+    // source ST signals
+    output source_startofpacket,
+    output source_endofpacket,
+    output source_valid,
+    input source_ready,
+   
+    // source ST "data"
+    output [ADDR_W - 1: 0] source_addr,
+    output [BURSTWRAP_W - 1 : 0] source_burstwrap,
+    output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
+   
+    // Note: in the slave agent, the output should always be uncompressed.  In
+    // other applications, it may be required to leave-compressed or not. How to
+    // control?  Seems like a simple mux - pass-through if no uncompression is
+    // required.
+    output source_is_compressed,
+    output [BURST_SIZE_W-1 : 0] source_burstsize
+);
+
+//----------------------------------------------------
+// AXSIZE decoding
+//
+// Turns the axsize value into the actual number of bytes
+// being transferred.
+// ---------------------------------------------------
+function reg[63:0] bytes_in_transfer;
+    input [BURST_SIZE_W-1:0] axsize;
+    case (axsize)
+        4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
+        4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
+        4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
+        4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
+        4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
+        4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
+        4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
+        4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
+        4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000;
+        4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000;
+        default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
+    endcase
+
+endfunction  
+
+   // num_symbols is PKT_SYMBOLS, appropriately sized.
+   wire [31:0] int_num_symbols = PKT_SYMBOLS;
+   wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
+  
+   // def: Burst Compression.  In a merlin network, a compressed burst is one 
+   // which is transmitted in a single beat.  Example: read burst.  In 
+   // constrast, an uncompressed burst (example: write burst) is transmitted in
+   // one beat per writedata item.
+   //
+   // For compressed bursts which require response packets, burst
+   // uncompression is required.  Concrete example: a read burst of size 8
+   // occupies one response-fifo position.  When that fifo position reaches the
+   // front of the FIFO, the slave starts providing the required 8 readdatavalid
+   // pulses.  The 8 return response beats must be provided in a single packet,
+   // with incrementing address and decrementing byte_cnt fields.  Upon receipt
+   // of the final readdata item of the burst, the response FIFO item is
+   // retired.
+   // Burst uncompression logic provides:
+   //   a) 2-state FSM (idle, busy)
+   //     reset to idle state
+   //     transition to busy state for 2nd and subsequent rdv pulses
+   //     - a single-cycle burst (aka non-burst read) causes no transition to
+   //     busy state.
+   //   b) response startofpacket/endofpacket logic.  The response FIFO item 
+   //   will have sop asserted, and may have eop asserted. (In the case of
+   //   multiple read bursts transmit in the command fabric in a single packet,
+   //   the eop assertion will come in a later FIFO item.)  To support packet
+   //   conservation, and emit a well-formed packet on the response fabric,
+   //     i) response fabric startofpacket is asserted only for the first resp.
+   //     beat;
+   //     ii) response fabric endofpacket is asserted only for the last resp.
+   //     beat.
+   //   c) response address field.  The response address field contains an
+   //   incrementing sequence, such that each readdata item is associated with
+   //   its slave-map location.  N.b. a) computing the address correctly requires
+   //   knowledge of burstwrap behavior b) there may be no clients of the address
+   //   field, which makes this field a good target for optimization.  See
+   //   burst_uncompress_address_counter below.
+   //   d) response byte_cnt field.  The response byte_cnt field contains a
+   //   decrementing sequence, such that each beat of the response contains the
+   //   count of bytes to follow.  In the case of sub-bursts in a single packet,
+   //   the byte_cnt field may decrement down to num_symbols, then back up to
+   //   some value, multiple times in the packet.
+  
+   reg burst_uncompress_busy;
+   reg [BYTE_CNT_W:0] burst_uncompress_byte_counter;
+   wire [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint;
+   wire first_packet_beat;
+   wire last_packet_beat;
+
+   assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
+   assign burst_uncompress_byte_counter_lint = burst_uncompress_byte_counter[BYTE_CNT_W-1:0];
+
+   // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
+   // the output.
+   assign source_byte_cnt =
+     first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint;
+   assign source_valid = sink_valid;
+  
+   // Last packet beat is set throughout receipt of an uncompressed read burst
+   // from the response FIFO - this forces all the burst uncompression machinery
+   // idle.
+   assign last_packet_beat = ~sink_is_compressed |
+     (
+     burst_uncompress_busy ?
+       (sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) :
+         sink_valid & (sink_byte_cnt == num_symbols)
+     );
+  
+   always @(posedge clk or posedge reset) begin
+     if (reset) begin
+       burst_uncompress_busy <= '0;
+       burst_uncompress_byte_counter <= '0;
+     end
+     else begin
+       if (source_valid & source_ready & sink_valid) begin
+         // No matter what the current state, last_packet_beat leads to
+         // idle.
+         if (last_packet_beat) begin
+           burst_uncompress_busy <= '0;
+           burst_uncompress_byte_counter <= '0;
+         end
+         else begin
+           if (burst_uncompress_busy) begin
+             burst_uncompress_byte_counter <= (burst_uncompress_byte_counter > 0) ? 
+               (burst_uncompress_byte_counter_lint - num_symbols) :
+               (sink_byte_cnt - num_symbols);
+           end
+           else begin // not busy, at least one more beat to go
+             burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols;
+             // To do: should busy go true for numsymbols-size compressed
+             // bursts?
+             burst_uncompress_busy <= 1'b1;
+           end
+         end
+       end
+     end
+   end
+  
+   reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
+   reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
+
+   wire [63:0] decoded_burstsize_wire;
+   wire [ADDR_W-1:0] decoded_burstsize;
+
+
+   localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W;
+   wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap;
+   // The input burstwrap value can be used as a mask against address values,
+   // but with one caveat: the address width may be (probably is) wider than 
+   // the burstwrap width.  The spec says: extend the msb of the burstwrap 
+   // value out over the entire address width (but only if the address width
+   // actually is wider than the burstwrap width; otherwise it's a 0-width or
+   // negative range and concatenation multiplier). 
+   generate
+      if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
+         // Sign-extend, just wires:
+            assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
+                {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
+            assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0];
+      end
+      else begin
+            assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap;
+      end
+   endgenerate
+
+   always @(posedge clk or posedge reset) begin
+     if (reset) begin
+       burst_uncompress_address_base <= '0;
+     end
+     else if (first_packet_beat & source_ready) begin
+       burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
+     end
+   end
+
+   assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize);  //expand it to 64 bits
+   assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0];      //then take the width that is needed
+
+   wire [ADDR_W : 0] p1_burst_uncompress_address_offset =
+   (
+     (first_packet_beat ?
+       sink_addr :
+       burst_uncompress_address_offset) + decoded_burstsize
+    ) &
+    addr_width_burstwrap[ADDR_W-1:0];
+    wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0];
+
+   always @(posedge clk or posedge reset) begin
+     if (reset) begin
+       burst_uncompress_address_offset <= '0;
+     end
+     else begin
+       if (source_ready & source_valid) begin
+         burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
+         // if (first_packet_beat) begin
+         //   burst_uncompress_address_offset <=
+         //     (sink_addr + num_symbols) & addr_width_burstwrap;
+         // end
+         // else begin
+         //   burst_uncompress_address_offset <=
+         //     (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
+         // end
+       end
+     end
+   end
+  
+   // On the first packet beat, send the input address out unchanged, 
+   // while values are computed/registered for 2nd and subsequent beats.
+   assign source_addr = first_packet_beat ? sink_addr :
+       burst_uncompress_address_base | burst_uncompress_address_offset;
+   assign source_burstwrap = sink_burstwrap;
+   assign source_burstsize = sink_burstsize;
+  
+   //-------------------------------------------------------------------
+   // A single (compressed) read burst will have sop/eop in the same beat.
+   // A sequence of read sub-bursts emitted by a burst adapter in response to a
+   // single read burst will have sop on the first sub-burst, eop on the last.
+   // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve 
+   // packet conservation.
+   assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
+   assign source_endofpacket   = sink_endofpacket & last_packet_beat;
+   assign sink_ready = source_valid & source_ready & last_packet_beat;
+  
+   // This is correct for the slave agent usage, but won't always be true in the
+   // width adapter.  To do: add an "please uncompress" input, and use it to
+   // pass-through or modify, and set source_is_compressed accordingly.
+   assign source_is_compressed = 1'b0;
+endmodule
+

nios2_uc/synthesis/submodules/altera_merlin_master_agent.sv

@@ -0,0 +1,303 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// --------------------------------------
+// Merlin Master Agent
+//
+// Converts Avalon-MM transactions into
+// Merlin network packets.
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_master_agent
+#(
+   // -------------------
+   // Packet Format Parameters
+   // -------------------
+   parameter 
+   PKT_QOS_H                  = 109,
+   PKT_QOS_L                  = 106,
+   PKT_DATA_SIDEBAND_H        = 105,
+   PKT_DATA_SIDEBAND_L        = 98,
+   PKT_ADDR_SIDEBAND_H        = 97, 
+   PKT_ADDR_SIDEBAND_L        = 93,
+   PKT_CACHE_H                = 92,
+   PKT_CACHE_L                = 89,
+   PKT_THREAD_ID_H            = 88,
+   PKT_THREAD_ID_L            = 87,
+   PKT_BEGIN_BURST            = 81,
+   PKT_PROTECTION_H           = 80,
+   PKT_PROTECTION_L           = 80,
+   PKT_BURSTWRAP_H            = 79,
+   PKT_BURSTWRAP_L            = 77,
+   PKT_BYTE_CNT_H             = 76,
+   PKT_BYTE_CNT_L             = 74,
+   PKT_ADDR_H                 = 73,
+   PKT_ADDR_L                 = 42,
+   PKT_BURST_SIZE_H           = 86,
+   PKT_BURST_SIZE_L           = 84,
+   PKT_BURST_TYPE_H           = 94,
+   PKT_BURST_TYPE_L           = 93,
+   PKT_TRANS_EXCLUSIVE        = 83,
+   PKT_TRANS_LOCK             = 82,
+   PKT_TRANS_COMPRESSED_READ  = 41,
+   PKT_TRANS_POSTED           = 40,
+   PKT_TRANS_WRITE            = 39,
+   PKT_TRANS_READ             = 38,
+   PKT_DATA_H                 = 37,
+   PKT_DATA_L                 = 6,
+   PKT_BYTEEN_H               = 5,
+   PKT_BYTEEN_L               = 2,
+   PKT_SRC_ID_H               = 1,
+   PKT_SRC_ID_L               = 1,
+   PKT_DEST_ID_H              = 0,
+   PKT_DEST_ID_L              = 0,
+   PKT_RESPONSE_STATUS_L      = 110,
+   PKT_RESPONSE_STATUS_H      = 111,
+   PKT_ORI_BURST_SIZE_L       = 112,
+   PKT_ORI_BURST_SIZE_H       = 114,
+   ST_DATA_W                  = 115,
+   ST_CHANNEL_W               = 1,
+
+   // -------------------
+   // Agent Parameters
+   // -------------------
+   AV_BURSTCOUNT_W       = 3,
+   ID                    = 1,
+   SUPPRESS_0_BYTEEN_RSP = 1,
+   BURSTWRAP_VALUE       = 4,
+   CACHE_VALUE           = 0,
+   SECURE_ACCESS_BIT     = 1,
+   USE_READRESPONSE      = 0,
+   USE_WRITERESPONSE     = 0,
+
+   // -------------------
+   // Derived Parameters
+   // -------------------
+   PKT_BURSTWRAP_W   = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
+   PKT_BYTE_CNT_W    = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
+   PKT_PROTECTION_W  = PKT_PROTECTION_H - PKT_PROTECTION_L + 1,
+   PKT_ADDR_W        = PKT_ADDR_H - PKT_ADDR_L + 1,
+   PKT_DATA_W        = PKT_DATA_H - PKT_DATA_L + 1,
+   PKT_BYTEEN_W      = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
+   PKT_SRC_ID_W      = PKT_SRC_ID_H - PKT_SRC_ID_L + 1,
+   PKT_DEST_ID_W     = PKT_DEST_ID_H - PKT_DEST_ID_L + 1,
+   PKT_BURST_SIZE_W  = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1
+) (
+   // -------------------
+   // Clock & Reset
+   // -------------------
+   input                         clk,
+   input                         reset,
+
+   // -------------------
+   // Avalon-MM Anti-Master
+   // -------------------
+   input [PKT_ADDR_W-1 : 0]      av_address,
+   input                         av_write,
+   input                         av_read,
+   input [PKT_DATA_W-1 : 0]      av_writedata,
+   output reg [PKT_DATA_W-1 : 0] av_readdata,
+   output reg                    av_waitrequest,
+   output reg                    av_readdatavalid,
+   input [PKT_BYTEEN_W-1 : 0]    av_byteenable,
+   input [AV_BURSTCOUNT_W-1 : 0] av_burstcount,
+   input                         av_debugaccess,
+   input                         av_lock,
+   output reg [1 : 0]            av_response,
+   output reg                    av_writeresponsevalid,
+
+   // -------------------
+   // Command Source
+   // -------------------
+   output reg                    cp_valid,
+   output reg [ST_DATA_W-1 : 0]  cp_data,
+   output wire                   cp_startofpacket,
+   output wire                   cp_endofpacket,
+   input                         cp_ready,
+
+   // -------------------
+   // Response Sink
+   // -------------------
+   input                         rp_valid,
+   input [ST_DATA_W-1 : 0]       rp_data,
+   input [ST_CHANNEL_W-1 : 0]    rp_channel,
+   input                         rp_startofpacket,
+   input                         rp_endofpacket,
+   output reg                    rp_ready
+);
+    // ------------------------------------------------------------
+    // Utility Functions
+    // ------------------------------------------------------------
+   function integer clogb2;
+      input [31 : 0] value;
+      begin
+         for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+            value = value >> 1;
+         clogb2 = clogb2 - 1;
+      end
+   endfunction // clogb2
+
+   localparam MAX_BURST    = 1 << (AV_BURSTCOUNT_W - 1);
+   localparam NUMSYMBOLS   = PKT_BYTEEN_W; 
+   localparam BURSTING     = (MAX_BURST > NUMSYMBOLS);
+   localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS);
+   localparam BURST_SIZE   = clogb2(NUMSYMBOLS);
+
+   typedef enum bit  [1 : 0]
+   {
+      FIXED       = 2'b00,
+      INCR        = 2'b01,
+      WRAP        = 2'b10,
+      OTHER_WRAP  = 2'b11
+   } MerlinBurstType;
+
+   // --------------------------------------
+   // Potential optimization: compare in words to save bits?
+   // --------------------------------------
+   wire is_burst;
+   assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS);
+
+   wire [31 : 0] burstwrap_value_int = BURSTWRAP_VALUE;
+   wire [31 : 0] id_int              = ID; 
+   wire [PKT_BURST_SIZE_W-1 : 0] burstsize_sig = BURST_SIZE[PKT_BURST_SIZE_W-1 : 0];
+   wire [1 : 0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP;
+
+   // --------------------------------------
+   // Address alignment
+   //
+   // The packet format requires that addresses be aligned to
+   // the transaction size.
+   // --------------------------------------
+   wire [PKT_ADDR_W-1 : 0] av_address_aligned;
+   generate 
+      if (NUMSYMBOLS > 1) begin
+         assign av_address_aligned = 
+         {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}};
+      end
+      else begin
+         assign av_address_aligned = av_address;
+      end 
+   endgenerate
+
+   // --------------------------------------
+   // Command & Response Construction
+   // --------------------------------------
+   always_comb begin
+      cp_data                                              = '0;
+
+      cp_data[PKT_PROTECTION_L]                            = av_debugaccess;    
+      cp_data[PKT_PROTECTION_L+1]                          = SECURE_ACCESS_BIT[0];  // secure cache bit
+      cp_data[PKT_PROTECTION_L+2]                          = 1'b0;                  // instruction/data cache bit
+      cp_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L]           = burstwrap_value_int[PKT_BURSTWRAP_W-1 : 0];
+      cp_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L]             = av_burstcount;
+      cp_data[PKT_ADDR_H : PKT_ADDR_L]                     = av_address_aligned;
+      cp_data[PKT_TRANS_EXCLUSIVE]                         = 1'b0;
+      cp_data[PKT_TRANS_LOCK]                              = av_lock;
+      cp_data[PKT_TRANS_COMPRESSED_READ]                   = av_read & is_burst;
+      cp_data[PKT_TRANS_READ]                              = av_read;
+      cp_data[PKT_TRANS_WRITE]                             = av_write;
+      cp_data[PKT_TRANS_POSTED]                            = av_write & !USE_WRITERESPONSE;
+      cp_data[PKT_DATA_H : PKT_DATA_L]                     = av_writedata;
+      cp_data[PKT_BYTEEN_H : PKT_BYTEEN_L]                 = av_byteenable;
+      cp_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L]         = burstsize_sig;
+      cp_data[PKT_ORI_BURST_SIZE_H : PKT_ORI_BURST_SIZE_L] = burstsize_sig;
+      cp_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L]         = bursttype_value;
+      cp_data[PKT_SRC_ID_H : PKT_SRC_ID_L]                 = id_int[PKT_SRC_ID_W-1 : 0];
+      cp_data[PKT_THREAD_ID_H : PKT_THREAD_ID_L]           = '0;
+      cp_data[PKT_CACHE_H : PKT_CACHE_L]                   = CACHE_VALUE[3 : 0];
+      cp_data[PKT_QOS_H : PKT_QOS_L]                       = '0;        
+      cp_data[PKT_ADDR_SIDEBAND_H : PKT_ADDR_SIDEBAND_L]   = '0;
+      cp_data[PKT_DATA_SIDEBAND_H : PKT_DATA_SIDEBAND_L]   = '0;
+
+      av_readdata                                          = rp_data[PKT_DATA_H : PKT_DATA_L];
+      if (USE_WRITERESPONSE || USE_READRESPONSE)
+         av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L];
+      else
+         av_response = '0;
+      end
+
+   // --------------------------------------
+   // Command Control
+   // --------------------------------------
+   reg hold_waitrequest;
+
+   always @ (posedge clk, posedge reset) begin
+      if (reset)
+         hold_waitrequest <= 1'b1;
+      else
+         hold_waitrequest <= 1'b0;
+   end  
+   
+   always_comb begin
+      cp_valid = 0;
+
+      if ((av_write || av_read) && ~hold_waitrequest)
+         cp_valid = 1;
+   end
+
+   generate if (BURSTING) begin
+      reg sop_enable;
+
+      always @(posedge clk, posedge reset) begin
+         if (reset) begin
+            sop_enable <= 1'b1;
+         end
+         else begin
+            if (cp_valid && cp_ready) begin
+               sop_enable <= 1'b0;
+               if (cp_endofpacket)
+                  sop_enable <= 1'b1;
+            end
+         end
+      end
+
+      assign cp_startofpacket = sop_enable;
+      assign cp_endofpacket   = (av_read) | (av_burstcount == NUMSYMBOLS);
+
+   end 
+   else begin
+
+      assign cp_startofpacket = 1'b1;
+      assign cp_endofpacket   = 1'b1;
+
+   end
+   endgenerate
+
+   // --------------------------------------
+   // Backpressure & Readdatavalid
+   // --------------------------------------
+   always_comb begin
+      rp_ready              = 1;
+      av_readdatavalid      = 0;
+      av_writeresponsevalid = 0;
+      av_waitrequest = hold_waitrequest | !cp_ready;
+
+      if (USE_WRITERESPONSE && (rp_data[PKT_TRANS_WRITE] == 1))
+         av_writeresponsevalid = rp_valid;
+      else
+         av_readdatavalid      = rp_valid;
+
+      if (SUPPRESS_0_BYTEEN_RSP) begin
+         if (rp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] == 0)
+            av_readdatavalid = 0;
+      end
+   end
+
+endmodule

nios2_uc/synthesis/submodules/altera_merlin_master_translator.sv

@@ -0,0 +1,556 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// --------------------------------------
+// Merlin Master Translator
+//
+// Converts an Avalon-MM master interface into an 
+// Avalon-MM "universal" master interface.
+//
+// The universal interface is defined as the superset of ports
+// and parameters that can represent any legal Avalon 
+// interface.
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_master_translator #(
+   parameter
+      // widths
+      AV_ADDRESS_W                = 32,
+      AV_DATA_W                   = 32,
+      AV_BURSTCOUNT_W             = 4,
+      AV_BYTEENABLE_W             = 4,
+
+      UAV_ADDRESS_W               = 38,
+      UAV_BURSTCOUNT_W            = 10,
+  
+      // optional ports
+      USE_BURSTCOUNT              = 1,
+      USE_BEGINBURSTTRANSFER      = 0,
+      USE_BEGINTRANSFER           = 0,
+      USE_CHIPSELECT              = 0,
+      USE_READ                    = 1,
+      USE_READDATAVALID           = 1,
+      USE_WRITE                   = 1,
+      USE_WAITREQUEST             = 1,
+      USE_WRITERESPONSE           = 0,
+      USE_READRESPONSE            = 0,
+   
+      AV_REGISTERINCOMINGSIGNALS  = 0,
+      AV_SYMBOLS_PER_WORD         = 4,
+      AV_ADDRESS_SYMBOLS          = 0,
+      // must be enabled for a bursting master
+      AV_CONSTANT_BURST_BEHAVIOR  = 1,
+      UAV_CONSTANT_BURST_BEHAVIOR = 0,
+      AV_BURSTCOUNT_SYMBOLS       = 0,
+      AV_LINEWRAPBURSTS           = 0
+)(
+   input wire                           clk,
+   input wire                           reset,
+
+   // Universal Avalon Master
+   output reg                           uav_write,
+   output reg                           uav_read,
+   output reg [UAV_ADDRESS_W -1 : 0]    uav_address,
+   output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount,
+   output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable,
+   output wire [AV_DATA_W -1 : 0]       uav_writedata,
+   output wire                          uav_lock,
+   output wire                          uav_debugaccess,
+   output wire                          uav_clken,
+
+   input wire [AV_DATA_W -1 : 0]        uav_readdata,
+   input wire                           uav_readdatavalid,
+   input wire                           uav_waitrequest,
+   input wire [1 : 0]                   uav_response,
+   input wire                           uav_writeresponsevalid,
+
+   // Avalon-MM Anti-master (slave)
+   input reg                            av_write,
+   input reg                            av_read,
+   input wire [AV_ADDRESS_W -1 : 0]     av_address,
+   input wire [AV_BYTEENABLE_W -1 : 0]  av_byteenable,
+   input wire [AV_BURSTCOUNT_W -1 : 0]  av_burstcount,
+   input wire [AV_DATA_W -1 : 0]        av_writedata,
+   input wire                           av_begintransfer,
+   input wire                           av_beginbursttransfer,
+   input wire                           av_lock,
+   input wire                           av_chipselect,
+   input wire                           av_debugaccess,
+   input wire                           av_clken,
+
+   output wire [AV_DATA_W -1 : 0]       av_readdata,
+   output wire                          av_readdatavalid,
+   output reg                           av_waitrequest,
+   output reg [1 : 0]                   av_response,
+   output reg                           av_writeresponsevalid
+);
+
+   localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD);
+   localparam AV_MAX_SYMBOL_BURST = flog2(pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : AV_SYMBOLS_PER_WORD));
+   localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0;
+   localparam UAV_BURSTCOUNT_H_OR_31 = (UAV_BURSTCOUNT_W > 32) ? 31 : UAV_BURSTCOUNT_W - 1;
+   localparam UAV_ADDRESS_H_OR_31 = (UAV_ADDRESS_W > 32) ? 31 : UAV_ADDRESS_W - 1;
+
+   localparam BITS_PER_WORD_BURSTCOUNT = (UAV_BURSTCOUNT_W == 1) ? 0 : BITS_PER_WORD;
+   localparam BITS_PER_WORD_ADDRESS    = (UAV_ADDRESS_W == 1) ? 0 : BITS_PER_WORD;
+
+   localparam ADDRESS_LOW     = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS;
+   localparam BURSTCOUNT_LOW  = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT;
+
+   localparam ADDRESS_HIGH    = (UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW) ? AV_ADDRESS_W : (UAV_ADDRESS_W - ADDRESS_LOW);
+   localparam BURSTCOUNT_HIGH = (UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW) ? AV_BURSTCOUNT_W : (UAV_BURSTCOUNT_W - BURSTCOUNT_LOW);
+
+   function integer flog2;
+      input [31:0]  depth;
+      integer       i;
+      begin
+         i = depth;
+         if ( i <= 0 ) flog2 = 0;
+         else begin
+            for (flog2 = -1; i > 0; flog2 = flog2 + 1)
+               i = i >> 1;
+         end
+      end
+   endfunction // flog2
+
+    // ------------------------------------------------------------
+    // Calculates the ceil(log2()) of the input val.
+    //
+    // Limited to a positive 32-bit input value.
+    // ------------------------------------------------------------
+    function integer clog2;
+        input[31:0] val;
+        reg[31:0] i;
+
+        begin
+            i = 1;
+            clog2 = 0;
+
+            while (i < val) begin
+                clog2 = clog2 + 1;
+                i = i[30:0] << 1;
+            end
+        end
+    endfunction
+
+   function integer pow2;
+      input [31:0] toShift;
+      begin
+         pow2 = 1;
+         pow2 = pow2 << toShift;
+      end
+   endfunction // pow2
+
+   // -------------------------------------------------
+   // Assign some constants to appropriately-sized signals to
+   // avoid synthesis warnings. This also helps some simulators
+   // with their inferred sensitivity lists.
+   //
+   // The symbols per word calculation here rounds non-power of two
+   // symbols to the next highest power of two, which is what we want
+   // when calculating the decrementing byte count.
+   // -------------------------------------------------
+   wire [31 : 0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_H_OR_31 : 0]));
+   wire [UAV_BURSTCOUNT_H_OR_31 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_H_OR_31 : 0];
+
+   reg                            internal_beginbursttransfer;
+   reg                            internal_begintransfer;
+   reg [UAV_ADDRESS_W -1 : 0]     uav_address_pre;
+   reg [UAV_BURSTCOUNT_W -1 : 0]  uav_burstcount_pre;
+
+   reg uav_read_pre;
+   reg uav_write_pre;
+   reg read_accepted;
+
+   // -------------------------------------------------
+   // Pass through signals that we don't touch
+   // -------------------------------------------------
+   assign uav_writedata    = av_writedata;
+   assign uav_byteenable   = av_byteenable;
+   assign uav_lock         = av_lock;
+   assign uav_debugaccess  = av_debugaccess;
+   assign uav_clken        = av_clken;
+
+   assign av_readdata      = uav_readdata;
+   assign av_readdatavalid = uav_readdatavalid;
+
+   // -------------------------------------------------
+   // Response signals
+   // -------------------------------------------------
+   always_comb begin
+      if (!USE_READRESPONSE && !USE_WRITERESPONSE)
+         av_response = '0;
+      else
+         av_response = uav_response;
+
+      if (USE_WRITERESPONSE) begin
+         av_writeresponsevalid = uav_writeresponsevalid;
+      end else begin
+         av_writeresponsevalid = '0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Convert byte and word addresses into byte addresses
+   // -------------------------------------------------
+   always_comb begin
+      uav_address_pre = {UAV_ADDRESS_W{1'b0}};
+
+      if (AV_ADDRESS_SYMBOLS)
+         uav_address_pre[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
+      else begin
+         uav_address_pre[ADDRESS_LOW + ADDRESS_HIGH - 1 : ADDRESS_LOW] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
+      end
+   end
+
+   // -------------------------------------------------
+   // Convert burstcount into symbol units
+   // -------------------------------------------------
+   always_comb begin
+      uav_burstcount_pre = symbols_per_word;  // default to a single transfer
+
+      if (USE_BURSTCOUNT) begin
+         uav_burstcount_pre = {UAV_BURSTCOUNT_W{1'b0}};
+         if (AV_BURSTCOUNT_SYMBOLS)
+            uav_burstcount_pre[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) :0] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
+         else begin
+            uav_burstcount_pre[UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
+         end
+      end
+   end
+
+   // -------------------------------------------------
+   // This is where we perform the per-transfer address and burstcount 
+   // calculations that are required by downstream modules.
+   // -------------------------------------------------
+   reg [UAV_ADDRESS_W -1 : 0] address_register;
+   wire [UAV_BURSTCOUNT_W -1 : 0] burstcount_register;
+   reg [UAV_BURSTCOUNT_W : 0] burstcount_register_lint;
+
+   assign burstcount_register = burstcount_register_lint[UAV_BURSTCOUNT_W -1 : 0];
+
+   always_comb begin
+      uav_address = uav_address_pre;
+      uav_burstcount = uav_burstcount_pre;
+
+      if (AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin
+         uav_address = address_register;
+         uav_burstcount = burstcount_register;
+      end
+   end
+
+   reg first_burst_stalled;
+   reg burst_stalled;
+
+   wire [UAV_ADDRESS_W -1 : 0] combi_burst_addr_reg;
+   wire [UAV_ADDRESS_W -1 : 0] combi_addr_reg;
+
+   generate
+      if (AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST != 0) begin
+         if (AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin
+            assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
+            assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
+         end
+         else begin
+            assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
+            assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
+         end
+      end
+      else begin
+         assign combi_burst_addr_reg = uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
+         assign combi_addr_reg = address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
+      end
+   endgenerate
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         address_register <= '0;
+         burstcount_register_lint <= '0;
+      end else begin
+         address_register <= address_register;
+         burstcount_register_lint <= burstcount_register_lint;
+
+         if (internal_beginbursttransfer || first_burst_stalled) begin
+            if (av_waitrequest) begin
+               address_register <= uav_address_pre;
+               burstcount_register_lint[UAV_BURSTCOUNT_W - 1 : 0] <= uav_burstcount_pre;
+            end else begin
+               address_register <= combi_burst_addr_reg;
+               burstcount_register_lint <= uav_burstcount_pre - symbols_per_word;
+            end
+         end else if (internal_begintransfer || burst_stalled) begin
+            if (~av_waitrequest) begin
+               address_register <= combi_addr_reg;
+               burstcount_register_lint <= burstcount_register - symbols_per_word;
+            end
+         end
+      end
+   end
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         first_burst_stalled <= 1'b0;
+         burst_stalled <= 1'b0;
+      end else begin
+         if (internal_beginbursttransfer || first_burst_stalled) begin
+            if (av_waitrequest) begin
+               first_burst_stalled <= 1'b1;
+            end else begin
+               first_burst_stalled <= 1'b0;
+            end
+         end else if (internal_begintransfer || burst_stalled) begin
+            if (~av_waitrequest) begin
+               burst_stalled <= 1'b0;
+            end else begin
+               burst_stalled <= 1'b1;
+            end
+         end
+      end
+   end
+
+   // -------------------------------------------------
+   // Waitrequest translation
+   // -------------------------------------------------
+   always @(posedge clk, posedge reset) begin
+      if (reset)
+         read_accepted <= 1'b0;
+      else begin
+         read_accepted <= read_accepted;
+         if (read_accepted == 0)
+            read_accepted <= av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0;
+         else if (read_accepted == 1 && uav_readdatavalid == 1)  // reset acceptance only when rdv arrives
+            read_accepted <= 1'b0;
+      end
+
+   end
+
+   reg write_accepted = 0;
+   generate if (AV_REGISTERINCOMINGSIGNALS) begin
+      always @(posedge clk, posedge reset) begin
+         if (reset)
+            write_accepted <= 1'b0;
+         else begin
+            write_accepted <=
+            ~av_waitrequest ? 1'b0 :
+            uav_write & ~uav_waitrequest? 1'b1 :
+            write_accepted;
+         end
+      end
+   end endgenerate
+
+   always_comb begin
+      av_waitrequest = uav_waitrequest;
+
+      if (USE_READDATAVALID == 0) begin
+         av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest;
+      end
+
+      if (AV_REGISTERINCOMINGSIGNALS) begin
+         av_waitrequest =
+            uav_read_pre ? ~uav_readdatavalid :
+            uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted :
+            1'b1;
+      end
+
+      if (USE_WAITREQUEST == 0) begin
+         av_waitrequest = 0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Determine the output read and write signals from 
+   // the read/write/chipselect input signals.
+   // -------------------------------------------------
+   always_comb begin
+      uav_write      =  1'b0;
+      uav_write_pre  =  1'b0;
+      uav_read       =  1'b0;
+      uav_read_pre   =  1'b0;
+
+      if (!USE_CHIPSELECT) begin
+         if (USE_READ) begin
+            uav_read_pre = av_read;
+         end
+     
+         if (USE_WRITE) begin
+            uav_write_pre = av_write;
+         end
+      end else begin
+         if (!USE_WRITE && USE_READ) begin
+            uav_write_pre = av_chipselect & ~av_read;
+            uav_read_pre = av_read;
+         end else if (!USE_READ && USE_WRITE) begin
+            uav_write_pre = av_write;
+            uav_read_pre = av_chipselect & ~av_write;
+         end else if (USE_READ && USE_WRITE) begin
+            uav_write_pre = av_write;
+            uav_read_pre = av_read;
+         end
+      end
+
+      if (USE_READDATAVALID == 0)
+         uav_read = uav_read_pre & ~read_accepted;
+      else
+         uav_read = uav_read_pre;
+
+      if (AV_REGISTERINCOMINGSIGNALS == 0)
+         uav_write = uav_write_pre;
+      else
+         uav_write = uav_write_pre & ~write_accepted;
+   end
+
+   // -------------------------------------------------
+   // Begintransfer assignment
+   // -------------------------------------------------
+   reg end_begintransfer;
+
+   always_comb begin
+      if (USE_BEGINTRANSFER) begin
+         internal_begintransfer = av_begintransfer;
+      end else begin
+         internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
+      end
+   end
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         end_begintransfer <= 1'b0;
+      end else begin
+         if (internal_begintransfer == 1 && uav_waitrequest)
+            end_begintransfer <= 1'b1;
+         else if (uav_waitrequest)
+            end_begintransfer <= end_begintransfer;
+         else
+            end_begintransfer <= 1'b0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Beginbursttransfer assignment
+   // -------------------------------------------------
+   reg   end_beginbursttransfer;
+   wire  last_burst_transfer_pre;
+   wire  last_burst_transfer_reg;
+   wire  last_burst_transfer;
+
+   // compare values before the mux to shorten critical path; benchmark before changing
+   assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word);
+   assign last_burst_transfer_reg = (burstcount_register == symbols_per_word);
+   assign last_burst_transfer     = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg;
+
+   always_comb begin
+      if (USE_BEGINBURSTTRANSFER) begin
+         internal_beginbursttransfer = av_beginbursttransfer;
+      end else begin
+         internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer;
+      end
+   end
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         end_beginbursttransfer <= 1'b0;
+      end else begin
+         end_beginbursttransfer <= end_beginbursttransfer;
+         if (last_burst_transfer && internal_begintransfer || uav_read) begin
+            end_beginbursttransfer <= 1'b0;
+         end
+         else if (uav_write && internal_begintransfer) begin
+            end_beginbursttransfer <= 1'b1;
+         end
+      end
+   end
+
+   // synthesis translate_off
+
+   // ------------------------------------------------
+   // check_1   : for waitrequest signal violation
+   //             Ensure that when waitreqeust is asserted, the master is not allowed to change its controls
+   // Exception : begintransfer / beginbursttransfer
+   //           : previously not in any transaction (idle)
+   // Note : Not checking clken which is not exactly part of Avalon controls/inputs
+   //      : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE
+   // ------------------------------------------------
+
+   reg av_waitrequest_r;
+   reg av_write_r, av_read_r, av_lock_r, av_chipselect_r, av_debugaccess_r;
+   reg [AV_ADDRESS_W-1:0]    av_address_r;
+   reg [AV_BYTEENABLE_W-1:0] av_byteenable_r;
+   reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r;
+   reg [AV_DATA_W-1:0]       av_writedata_r;
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         av_waitrequest_r           <= '0;
+         av_write_r                 <= '0;
+         av_read_r                  <= '0;
+         av_lock_r                  <= '0;
+         av_chipselect_r            <= '0;
+         av_debugaccess_r           <= '0;
+         av_address_r               <= '0;
+         av_byteenable_r            <= '0;
+         av_burstcount_r            <= '0;
+         av_writedata_r             <= '0;
+      end else begin
+         av_waitrequest_r           <= av_waitrequest;
+         av_write_r                 <= av_write;
+         av_read_r                  <= av_read;
+         av_lock_r                  <= av_lock;
+         av_chipselect_r            <= av_chipselect;
+         av_debugaccess_r           <= av_debugaccess;
+         av_address_r               <= av_address;
+         av_byteenable_r            <= av_byteenable;
+         av_burstcount_r            <= av_burstcount;
+         av_writedata_r             <= av_writedata;
+   
+         if (
+            av_waitrequest_r && // When waitrequest is asserted
+            (
+               (av_write                  != av_write_r) ||   // Checks that : Input controls/data does not change
+               (av_read                   != av_read_r)  ||
+               (av_lock                   != av_lock_r)  ||
+               (av_debugaccess            != av_debugaccess_r) ||
+               (av_address                != av_address_r) ||
+               (av_byteenable             != av_byteenable_r) ||
+               (av_burstcount             != av_burstcount_r)
+            )  &&
+            (av_write_r | av_read_r) &&         // Check only when : previously initiated a write/read
+            (!USE_CHIPSELECT | av_chipselect_r) //                   and chipselect was asserted (or unused)
+         ) begin
+            $display( "%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.", $time());
+            $display("av_address                %x --> %x", av_address_r               , av_address               );
+            $display("av_byteenable             %x --> %x", av_byteenable_r            , av_byteenable            );
+            $display("av_burstcount             %x --> %x", av_burstcount_r            , av_burstcount            );
+            $display("av_writedata              %x --> %x", av_writedata_r             , av_writedata             );
+            $display("av_write                  %x --> %x", av_write_r                 , av_write                 );
+            $display("av_read                   %x --> %x", av_read_r                  , av_read                  );
+            $display("av_lock                   %x --> %x", av_lock_r                  , av_lock                  );
+            $display("av_chipselect             %x --> %x", av_chipselect_r            , av_chipselect            );
+            $display("av_debugaccess            %x --> %x", av_debugaccess_r           , av_debugaccess           );
+         end
+      end
+   
+   // end check_1
+   
+   end
+
+  // synthesis translate_on
+
+
+endmodule

nios2_uc/synthesis/submodules/altera_merlin_slave_agent.sv

@@ -0,0 +1,622 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2011 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_slave_agent
+#(
+   // Packet parameters
+   parameter PKT_BEGIN_BURST           = 81,
+   parameter PKT_DATA_H                = 31,
+   parameter PKT_DATA_L                = 0,
+   parameter PKT_SYMBOL_W              = 8,
+   parameter PKT_BYTEEN_H              = 71,
+   parameter PKT_BYTEEN_L              = 68,
+   parameter PKT_ADDR_H                = 63,
+   parameter PKT_ADDR_L                = 32,
+   parameter PKT_TRANS_LOCK            = 87,
+   parameter PKT_TRANS_COMPRESSED_READ = 67,
+   parameter PKT_TRANS_POSTED          = 66, 
+   parameter PKT_TRANS_WRITE           = 65,
+   parameter PKT_TRANS_READ            = 64,
+   parameter PKT_SRC_ID_H              = 74,
+   parameter PKT_SRC_ID_L              = 72,
+   parameter PKT_DEST_ID_H             = 77,
+   parameter PKT_DEST_ID_L             = 75,
+   parameter PKT_BURSTWRAP_H           = 85,
+   parameter PKT_BURSTWRAP_L           = 82,
+   parameter PKT_BYTE_CNT_H            = 81,
+   parameter PKT_BYTE_CNT_L            = 78,
+   parameter PKT_PROTECTION_H          = 86,
+   parameter PKT_PROTECTION_L          = 86,
+   parameter PKT_RESPONSE_STATUS_H     = 89,
+   parameter PKT_RESPONSE_STATUS_L     = 88,
+   parameter PKT_BURST_SIZE_H          = 92,
+   parameter PKT_BURST_SIZE_L          = 90,
+   parameter PKT_ORI_BURST_SIZE_L      = 93,
+   parameter PKT_ORI_BURST_SIZE_H      = 95,
+   parameter ST_DATA_W                 = 96,
+   parameter ST_CHANNEL_W              = 32,
+
+   // Slave parameters
+   parameter ADDR_W           = PKT_ADDR_H - PKT_ADDR_L + 1,
+   parameter AVS_DATA_W       = PKT_DATA_H - PKT_DATA_L + 1,
+   parameter AVS_BURSTCOUNT_W = 4,
+   parameter PKT_SYMBOLS      = AVS_DATA_W / PKT_SYMBOL_W,
+
+   // Slave agent parameters
+   parameter PREVENT_FIFO_OVERFLOW = 0,
+   parameter SUPPRESS_0_BYTEEN_CMD = 1,
+   parameter USE_READRESPONSE      = 0,
+   parameter USE_WRITERESPONSE     = 0,
+
+   // Derived slave parameters
+   parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
+   parameter BURST_SIZE_W = 3,
+
+   // Derived FIFO width
+   parameter FIFO_DATA_W = ST_DATA_W + 1,
+   
+   // ECC parameter
+   parameter ECC_ENABLE = 0
+) (
+   input                         clk,
+   input                         reset,
+
+   // Universal-Avalon anti-slave
+   output [ADDR_W-1:0]           m0_address,
+   output [AVS_BURSTCOUNT_W-1:0] m0_burstcount,
+   output [AVS_BE_W-1:0]         m0_byteenable,
+   output                        m0_read,
+   input [AVS_DATA_W-1:0]        m0_readdata,
+   input                         m0_waitrequest,
+   output                        m0_write,
+   output [AVS_DATA_W-1:0]       m0_writedata,
+   input                         m0_readdatavalid,
+   output                        m0_debugaccess,
+   output                        m0_lock,
+   input [1:0]                   m0_response,
+   input                         m0_writeresponsevalid,
+
+   // Avalon-ST FIFO interfaces.
+   // Note: there's no need to include the "data" field here, at least for
+   // reads, since readdata is filled in from slave info.  To keep life
+   // simple, have a data field, but fill it with 0s.
+   // Av-st response fifo source interface
+   output reg [FIFO_DATA_W-1:0]  rf_source_data,
+   output                        rf_source_valid,
+   output                        rf_source_startofpacket,
+   output                        rf_source_endofpacket,
+   input                         rf_source_ready,
+
+   // Av-st response fifo sink interface
+   input [FIFO_DATA_W-1:0]       rf_sink_data,
+   input                         rf_sink_valid,
+   input                         rf_sink_startofpacket,
+   input                         rf_sink_endofpacket,
+   output                        rf_sink_ready,
+
+   // Av-st readdata fifo src interface, data and response
+   // extra 2 bits for storing RESPONSE STATUS
+   output [AVS_DATA_W+1:0]       rdata_fifo_src_data,
+   output                        rdata_fifo_src_valid,
+   input                         rdata_fifo_src_ready,
+
+   // Av-st readdata fifo sink interface
+   input [AVS_DATA_W+1:0]        rdata_fifo_sink_data,
+   input                         rdata_fifo_sink_valid,
+   output                        rdata_fifo_sink_ready,
+   input                         rdata_fifo_sink_error,
+
+   // Av-st sink command packet interface
+   output                        cp_ready,
+   input                         cp_valid,
+   input [ST_DATA_W-1:0]         cp_data,
+   input [ST_CHANNEL_W-1:0]      cp_channel,
+   input                         cp_startofpacket,
+   input                         cp_endofpacket,
+
+   // Av-st source response packet interface
+   input                         rp_ready,
+   output reg                    rp_valid,
+   output reg [ST_DATA_W-1:0]    rp_data,
+   output                        rp_startofpacket,
+   output                        rp_endofpacket
+);
+
+   // --------------------------------------------------
+   // Ceil(log2()) function log2ceil of 4 = 2
+   // --------------------------------------------------
+   function integer log2ceil;
+      input reg[63:0] val;
+      reg [63:0] i;
+   
+      begin
+         i = 1;
+         log2ceil = 0;
+
+         while (i < val) begin
+            log2ceil = log2ceil + 1;
+            i = i << 1;
+         end
+      end
+   endfunction     
+
+   // ------------------------------------------------
+   // Local Parameters
+   // ------------------------------------------------
+   localparam DATA_W       = PKT_DATA_H - PKT_DATA_L + 1;
+   localparam BE_W         = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
+   localparam MID_W        = PKT_SRC_ID_H - PKT_SRC_ID_L + 1;
+   localparam SID_W        = PKT_DEST_ID_H - PKT_DEST_ID_L + 1;
+   localparam BYTE_CNT_W   = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1;
+   localparam BURSTWRAP_W  = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1;
+   localparam BURSTSIZE_W  = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1;
+   localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS);
+   localparam MAX_BURST    = 1 << (AVS_BURSTCOUNT_W - 1);
+   localparam BURSTING     = (MAX_BURST > PKT_SYMBOLS);
+
+   // ------------------------------------------------
+   // Signals
+   // ------------------------------------------------
+   wire [DATA_W-1:0]      cmd_data;
+   wire [BE_W-1:0]        cmd_byteen;
+   wire [ADDR_W-1:0]      cmd_addr;
+   wire [MID_W-1:0]       cmd_mid;
+   wire [SID_W-1:0]       cmd_sid;
+   wire                   cmd_read;
+   wire                   cmd_write;
+   wire                   cmd_compressed;
+   wire                   cmd_posted;
+   wire [BYTE_CNT_W-1:0]  cmd_byte_cnt;
+   wire [BURSTWRAP_W-1:0] cmd_burstwrap;
+   wire [BURSTSIZE_W-1:0] cmd_burstsize;
+   wire                   cmd_debugaccess;
+
+   wire                   suppress_cmd;
+   wire                   byteen_asserted;
+   wire                   suppress_read;
+   wire                   suppress_write;
+   wire                   needs_response_synthesis;
+   wire                   generate_response;
+
+   // Assign command fields
+   assign cmd_data         = cp_data[PKT_DATA_H  :PKT_DATA_L  ];
+   assign cmd_byteen       = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L];
+   assign cmd_addr         = cp_data[PKT_ADDR_H  :PKT_ADDR_L  ];
+   assign cmd_compressed   = cp_data[PKT_TRANS_COMPRESSED_READ];
+   assign cmd_posted       = cp_data[PKT_TRANS_POSTED];
+   assign cmd_write        = cp_data[PKT_TRANS_WRITE];
+   assign cmd_read         = cp_data[PKT_TRANS_READ];
+   assign cmd_mid          = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L];
+   assign cmd_sid          = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L];
+   assign cmd_byte_cnt     = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
+   assign cmd_burstwrap    = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
+   assign cmd_burstsize    = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
+   assign cmd_debugaccess  = cp_data[PKT_PROTECTION_L];
+
+   // Local "ready_for_command" signal: deasserted when the agent is unable to accept
+   // another command, e.g. rdv FIFO is full, (local readdata storage is full &&
+   // ~rp_ready), ...
+   // Say, this could depend on the type of command, for example, even if the
+   // rdv FIFO is full, a write request can be accepted.  For later.
+   wire ready_for_command;
+
+   wire local_lock  = cp_valid & cp_data[PKT_TRANS_LOCK];
+   wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE];
+   wire local_read  = cp_valid & cp_data[PKT_TRANS_READ];
+   wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ];
+   wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket;
+
+   // num_symbols is PKT_SYMBOLS, appropriately sized.
+   wire [31:0] int_num_symbols = PKT_SYMBOLS;
+   wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
+
+   generate
+      if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow_block
+         // ---------------------------------------------------
+         // Backpressure if the slave says to, or if FIFO overflow may occur.
+         // 
+         // All commands are backpressured once the FIFO is full
+         // even if they don't need storage. This breaks a long
+         // combinatorial path from the master read/write through
+         // this logic and back to the master via the backpressure
+         // path.
+         //
+         // To avoid a loss of throughput the FIFO will be parameterized 
+         // one slot deeper. The extra slot should never be used in normal
+         // operation, but should a slave misbehave and accept one more
+         // read than it should then backpressure will kick in.
+         //
+         // An example: assume a slave with MPRT = 2. It can accept a
+         // command sequence RRWW without backpressuring. If the FIFO is
+         // only 2 deep, we'd backpressure the writes leading to loss of
+         // throughput. If the FIFO is 3 deep, we'll only backpressure when
+         // RRR... which is an illegal condition anyway.
+         // ---------------------------------------------------
+
+         assign ready_for_command = rf_source_ready;
+         assign cp_ready = (~m0_waitrequest | suppress_cmd) && ready_for_command;
+
+      end else begin : no_prevent_fifo_overflow_block
+
+         // Do not suppress the command or the slave will
+         // not be able to waitrequest
+         assign ready_for_command = 1'b1;
+         // Backpressure only if the slave says to.
+         assign cp_ready = ~m0_waitrequest | suppress_cmd;
+
+      end
+   endgenerate
+
+   generate if (SUPPRESS_0_BYTEEN_CMD && !BURSTING) begin : suppress_0_byteen_cmd_non_bursting
+      assign byteen_asserted  = |cmd_byteen;
+      assign suppress_read    = ~byteen_asserted;
+      assign suppress_write   = ~byteen_asserted;
+      assign suppress_cmd     = ~byteen_asserted;
+   end else if (SUPPRESS_0_BYTEEN_CMD && BURSTING) begin: suppress_0_byteen_cmd_bursting
+      assign byteen_asserted  = |cmd_byteen;
+      assign suppress_read    = ~byteen_asserted;
+      assign suppress_write   = 1'b0;
+      assign suppress_cmd     = ~byteen_asserted && cmd_read;
+   end else begin : no_suppress_0_byteen_cmd
+      assign suppress_read    = 1'b0;
+      assign suppress_write   = 1'b0;
+      assign suppress_cmd     = 1'b0;
+   end
+   endgenerate
+
+   // -------------------------------------------------------------------
+   // Extract avalon signals from command packet.
+   // -------------------------------------------------------------------
+   // Mask off the lower bits of address.
+   // The burst adapter before this component will break narrow sized packets
+   // into sub-bursts of length 1. However, the packet addresses are preserved,
+   // which means this component may see size-aligned addresses.
+   //
+   // Masking ensures that the addresses seen by an Avalon slave are aligned to 
+   // the full data width instead of the size.
+   //
+   // Example:
+   // output from burst adapter (datawidth=4, size=2 bytes):
+   // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6
+   // expected output from slave agent:
+   // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4
+   generate 
+      if (BITS_TO_MASK > 0) begin : mask_address
+
+         assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} };
+
+      end else begin : no_mask_address
+
+         assign m0_address = cmd_addr;
+
+      end
+   endgenerate
+
+   assign m0_byteenable = cmd_byteen;
+   assign m0_writedata  = cmd_data;
+
+   // Note: no Avalon-MM slave in existence accepts uncompressed read bursts -
+   // this sort of burst exists only in merlin fabric ST packets. What to do
+   // if we see such a burst? All beats in that burst need to be transmitted
+   // to the slave so we have enough space-time for byteenable expression.
+   //
+   // There can be multiple bursts in a packet, but only one beat per burst
+   // in <most> cases. The exception is when we've decided not to insert a
+   // burst adapter for efficiency reasons, in which case this agent is also
+   // responsible for driving burstcount to 1 on each beat of an uncompressed
+   // read burst.
+
+   assign m0_read = ready_for_command & !suppress_read & (local_compressed_read | local_read);
+
+   generate 
+       // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal.  Assign m0_burstcount
+       // from a sub-range, or 0-pad, as appropriate.
+       if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin : m0_burstcount_zero_pad
+          wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}};
+          assign m0_burstcount = (local_read & ~local_compressed_read) ?
+             {zero_pad, num_symbols} :
+             {zero_pad, cmd_byte_cnt};
+       end
+       else begin : m0_burstcount_no_pad
+          assign m0_burstcount = (local_read & ~local_compressed_read) ? 
+          num_symbols[AVS_BURSTCOUNT_W-1:0] : 
+          cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0];
+       end
+   endgenerate
+
+   assign m0_write = ready_for_command & local_write & !suppress_write;
+   assign m0_lock  = ready_for_command & local_lock & (m0_read | m0_write);
+   assign m0_debugaccess  = cmd_debugaccess;
+
+   // -------------------------------------------------------------------
+   // Indirection layer for response packet values.  Some may always wire
+   // directly from the slave translator; others will no doubt emerge from
+   // various FIFOs.
+   // What to put in resp_data when a write occured? Answer: it does not
+   // matter, because only response status is needed for non-posted writes,
+   // and the packet already has a field for that.
+   //
+   // We use the rdata_fifo to store write responses as well. This allows us
+   // to handle backpressure on the response path, and allows write response
+   // merging.
+   assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid;
+   assign rdata_fifo_src_data  = {m0_response, m0_readdata};
+
+   // ------------------------------------------------------------------
+   // Generate a token when read commands are suppressed. The token
+   // is stored in the response FIFO, and will be used to synthesize 
+   // a read response. The same token is used for non-posted write
+   // response synthesis.
+   //
+   // Note: this token is not generated for suppressed uncompressed read cycles;
+   // the burst uncompression logic at the read side of the response FIFO
+   // generates the correct number of responses.
+   //
+   // When the slave can return the response, let it do its job. Don't 
+   // synthesize a response in that case, unless we've suppressed the
+   // the last transfer in a write sub-burst.
+   // ------------------------------------------------------------------
+   wire write_end_of_subburst;
+   assign needs_response_synthesis = ((local_read | local_compressed_read) & suppress_read) || 
+                                        (!USE_WRITERESPONSE && nonposted_write_endofpacket) ||
+                                        (USE_WRITERESPONSE && write_end_of_subburst && suppress_write);
+
+   // Avalon-ST interfaces to external response FIFO.
+   //
+   // For efficiency, when synthesizing a write response we only store a non-posted write 
+   // transaction at its endofpacket, even if it was split into multiple sub-bursts.
+   //
+   // When not synthesizing write responses, we store each sub-burst in the FIFO.
+   // Each sub-burst to the slave will return a response, which corresponds to one 
+   // entry in the FIFO. We merge all the sub-burst responses on the final
+   // sub-burst and send it on the response channel.
+
+   wire internal_cp_endofburst;
+   wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning
+   wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount;
+
+   assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0];
+   assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount);
+   assign write_end_of_subburst = local_write & internal_cp_endofburst;
+
+   assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && internal_cp_endofburst && local_write))
+                             & ready_for_command & cp_ready;
+   assign rf_source_startofpacket = cp_startofpacket;
+   assign rf_source_endofpacket   = cp_endofpacket;
+   always @* begin
+      // default: assign every command packet field to the response FIFO...
+      rf_source_data                                  = {1'b0, cp_data};
+
+      // ... and override select fields as needed.
+      rf_source_data[FIFO_DATA_W-1]                      = needs_response_synthesis;
+      rf_source_data[PKT_DATA_H   :PKT_DATA_L]           = {DATA_W {1'b0}};
+      rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L]         = cmd_byteen;
+      rf_source_data[PKT_ADDR_H   :PKT_ADDR_L]           = cmd_addr;
+      rf_source_data[PKT_TRANS_COMPRESSED_READ]          = cmd_compressed;
+      rf_source_data[PKT_TRANS_POSTED]                   = cmd_posted;
+      rf_source_data[PKT_TRANS_WRITE]                    = cmd_write;
+      rf_source_data[PKT_TRANS_READ]                     = cmd_read;
+      rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L]         = cmd_mid;
+      rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L]        = cmd_sid;
+      rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]      = cmd_byte_cnt;
+      rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]    = cmd_burstwrap;
+      rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]  = cmd_burstsize;
+      rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L]  = '0;
+      rf_source_data[PKT_PROTECTION_L]                   = cmd_debugaccess;
+   end
+
+   wire uncompressor_source_valid;
+   wire [BURSTSIZE_W-1:0] uncompressor_burstsize;
+   wire last_write_response;
+
+   // last_write_response indicates the last response of the broken-up write burst (sub-bursts).
+   // At this time, the final merged response is sent, and rp_valid is only asserted
+   // once for the whole burst.
+   generate
+      if (USE_WRITERESPONSE) begin
+         assign last_write_response = rf_sink_data[PKT_TRANS_WRITE] & rf_sink_endofpacket;
+         always @* begin
+            if (rf_sink_data[PKT_TRANS_WRITE] == 1) 
+               rp_valid = (rdata_fifo_sink_valid | generate_response) & last_write_response & !rf_sink_data[PKT_TRANS_POSTED];
+            else
+               rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
+         end
+      end else begin
+         assign last_write_response = 1'b0;
+         always @* begin
+            rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
+         end
+      end
+   endgenerate
+
+   // ------------------------------------------------------------------
+   // Response merging
+   // ------------------------------------------------------------------
+   reg [1:0] current_response;
+   reg [1:0] response_merged;
+   generate
+     if (USE_WRITERESPONSE) begin : response_merging_all
+        reg first_write_response;
+        reg reset_merged_output;
+        reg [1:0] previous_response_in;
+        reg [1:0]  previous_response;
+
+        always_ff @(posedge clk, posedge reset) begin
+           if (reset) begin
+              first_write_response  <= 1'b1;
+           end 
+           else begin // Merging work for write response, for read: previous_response_in = current_response
+              if (rf_sink_valid & (rdata_fifo_sink_valid | generate_response) & rf_sink_data[PKT_TRANS_WRITE]) begin
+                 first_write_response <= 1'b0;
+                 if (rf_sink_endofpacket)
+                    first_write_response <= 1'b1;
+              end
+           end
+        end
+
+        always_comb begin
+           current_response = generate_response ? 2'b00 : rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | {2{rdata_fifo_sink_error}};
+           reset_merged_output = first_write_response && (rdata_fifo_sink_valid || generate_response);
+           previous_response_in = reset_merged_output ? current_response : previous_response;
+           response_merged = current_response >= previous_response ? current_response: previous_response_in;
+        end
+
+        always_ff @(posedge clk or posedge reset) begin
+           if (reset) begin 
+              previous_response <= 2'b00;
+           end
+           else begin
+              if (rf_sink_valid & (rdata_fifo_sink_valid || generate_response)) begin
+                 previous_response <= response_merged;
+              end
+           end
+        end
+     end else begin : response_merging_read_only
+        always @* begin
+           current_response = generate_response ? 2'b00: rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | 
+                                                         {2{rdata_fifo_sink_error}};
+           response_merged = current_response;
+        end
+     end
+   endgenerate
+
+   assign generate_response = rf_sink_data[FIFO_DATA_W-1];
+
+   wire [BYTE_CNT_W-1:0]  rf_sink_byte_cnt   = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
+   wire                   rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ];
+   wire [BURSTWRAP_W-1:0] rf_sink_burstwrap  = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
+   wire [BURSTSIZE_W-1:0] rf_sink_burstsize  = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
+   wire [ADDR_W-1:0]      rf_sink_addr       = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L];
+   // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo
+   wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket;    
+
+   wire [BYTE_CNT_W-1:0]   burst_byte_cnt;
+   wire [BURSTWRAP_W-1:0]  rp_burstwrap;
+   wire [ADDR_W-1:0]       rp_address;
+   wire                    rp_is_compressed;
+   wire                    ready_for_response;
+
+   // ------------------------------------------------------------------
+   // We're typically ready for a response if the network is ready. There
+   // is one exception:
+   //
+   // If the slave issues write responses, we only issue a merged response on 
+   // the final sub-burst. As a result, we only care about response channel 
+   // availability on the final burst when we send out the merged response.
+   // ------------------------------------------------------------------
+   assign ready_for_response = (USE_WRITERESPONSE) ? 
+                            rp_ready || (rf_sink_data[PKT_TRANS_WRITE] && !last_write_response) || rf_sink_data[PKT_TRANS_POSTED]: 
+                            rp_ready;
+
+   // ------------------------------------------------------------------
+   // Backpressure the readdata fifo if we're supposed to synthesize a response.
+   // This may be a read response (for suppressed reads) or a write response
+   // (for non-posted writes).
+   // ------------------------------------------------------------------
+   assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & ready_for_response & ~(rf_sink_valid & generate_response);
+
+   always @* begin
+      // By default, return all fields...
+      rp_data                                               = rf_sink_data[ST_DATA_W - 1 : 0];
+
+      // ... and override specific fields.
+      rp_data[PKT_DATA_H   :PKT_DATA_L]                     = rdata_fifo_sink_data[AVS_DATA_W-1:0];
+      // Assignments directly from the response fifo.
+      rp_data[PKT_TRANS_POSTED]                             = rf_sink_data[PKT_TRANS_POSTED];
+      rp_data[PKT_TRANS_WRITE]                              = rf_sink_data[PKT_TRANS_WRITE];
+      rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]                   = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+      rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]                  = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L];
+      rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L]                   = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L];
+      rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L]            = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L];
+
+      // Burst uncompressor assignments
+      rp_data[PKT_ADDR_H   :PKT_ADDR_L]                     = rp_address;
+      rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]              = rp_burstwrap;
+      rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]                = burst_byte_cnt;
+      rp_data[PKT_TRANS_READ]                               = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ];
+      rp_data[PKT_TRANS_COMPRESSED_READ]                    = rp_is_compressed;
+
+      rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L]  = response_merged;
+      rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]            = uncompressor_burstsize;
+      // bounce the original size back to the master untouched
+      rp_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L]    = rf_sink_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L];
+   end
+
+   // ------------------------------------------------------------------
+   // Note: the burst uncompressor may be asked to generate responses for
+   // write packets; these are treated the same as single-cycle uncompressed 
+   // reads.
+   // ------------------------------------------------------------------
+   altera_merlin_burst_uncompressor #(
+      .ADDR_W               (ADDR_W),
+      .BURSTWRAP_W          (BURSTWRAP_W),
+      .BYTE_CNT_W           (BYTE_CNT_W),
+      .PKT_SYMBOLS          (PKT_SYMBOLS),
+      .BURST_SIZE_W         (BURSTSIZE_W)
+   ) uncompressor (
+      .clk                  (clk),
+      .reset                (reset),
+      .sink_startofpacket   (rf_sink_startofpacket_wire),
+      .sink_endofpacket     (rf_sink_endofpacket),
+      .sink_valid           (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)),
+      .sink_ready           (rf_sink_ready),
+      .sink_addr            (rf_sink_addr),
+      .sink_burstwrap       (rf_sink_burstwrap),
+      .sink_byte_cnt        (rf_sink_byte_cnt),
+      .sink_is_compressed   (rf_sink_compressed),
+      .sink_burstsize       (rf_sink_burstsize),
+
+      .source_startofpacket (rp_startofpacket),
+      .source_endofpacket   (rp_endofpacket),
+      .source_valid         (uncompressor_source_valid),
+      .source_ready         (ready_for_response),
+      .source_addr          (rp_address),
+      .source_burstwrap     (rp_burstwrap),
+      .source_byte_cnt      (burst_byte_cnt),
+      .source_is_compressed (rp_is_compressed),
+      .source_burstsize     (uncompressor_burstsize)
+   );
+
+   //--------------------------------------
+   // Assertion: In case slave support response. The slave needs return response in order
+   // Ex: non-posted write followed by a read: write response must complete before read data 
+   //--------------------------------------
+   // synthesis translate_off      
+   ERROR_write_response_and_read_response_cannot_happen_same_time:
+   assert property ( @(posedge clk)
+      disable iff (reset) !(m0_writeresponsevalid  && m0_readdatavalid)
+   );    
+
+   // synthesis translate_on
+endmodule
+

nios2_uc/synthesis/submodules/altera_merlin_slave_translator.sv

@@ -0,0 +1,482 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Slave Translator
+//
+// Translates Universal Avalon  MM Slave
+// to any Avalon MM Slave
+// -------------------------------------
+//
+//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
+//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
+//The key feature here is that no same cycle turnaround data is processed through the fabric.
+
+//import avalon_utilities_pkg::*;
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_slave_translator #(
+   parameter
+   //Widths
+   AV_ADDRESS_W           = 32,
+   AV_DATA_W              = 32,
+   AV_BURSTCOUNT_W        = 4,
+   AV_BYTEENABLE_W        = 4,
+   UAV_BYTEENABLE_W       = 4,
+
+   //Read Latency
+   AV_READLATENCY          = 1,
+
+   //Timing
+   AV_READ_WAIT_CYCLES     = 0,
+   AV_WRITE_WAIT_CYCLES    = 0,
+   AV_SETUP_WAIT_CYCLES    = 0,
+   AV_DATA_HOLD_CYCLES     = 0,
+
+   //Optional Port Declarations
+   USE_READDATAVALID       = 1,
+   USE_WAITREQUEST         = 1,
+   USE_READRESPONSE        = 0,
+   USE_WRITERESPONSE       = 0,
+
+   //Variable Addressing
+   AV_SYMBOLS_PER_WORD     = 4,
+   AV_ADDRESS_SYMBOLS      = 0,
+   AV_BURSTCOUNT_SYMBOLS   = 0,
+   BITS_PER_WORD           = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
+   UAV_ADDRESS_W           = 38,
+   UAV_BURSTCOUNT_W        = 10,
+   UAV_DATA_W              = 32,
+
+   AV_CONSTANT_BURST_BEHAVIOR       = 0,
+   UAV_CONSTANT_BURST_BEHAVIOR      = 0,
+   CHIPSELECT_THROUGH_READLATENCY   = 0,
+
+   // Tightly-Coupled Options
+   USE_UAV_CLKEN           = 0,
+   AV_REQUIRE_UNALIGNED_ADDRESSES = 0
+) (
+
+   // -------------------
+   // Clock & Reset
+   // -------------------
+   input wire                             clk,
+   input wire                             reset,
+
+   // -------------------
+   // Universal Avalon Slave
+   // -------------------
+
+   input wire [UAV_ADDRESS_W - 1 : 0]     uav_address,
+   input wire [UAV_DATA_W - 1 : 0]        uav_writedata,
+   input wire                             uav_write,
+   input wire                             uav_read,
+   input wire [UAV_BURSTCOUNT_W - 1 : 0]  uav_burstcount,
+   input wire [UAV_BYTEENABLE_W - 1 : 0]  uav_byteenable,
+   input wire                             uav_lock,
+   input wire                             uav_debugaccess,
+   input wire                             uav_clken,
+
+   output logic                           uav_readdatavalid,
+   output logic                           uav_waitrequest,
+   output logic [UAV_DATA_W - 1 : 0]      uav_readdata,
+   output logic [1:0]                     uav_response,
+   // input wire                             uav_writeresponserequest,
+   output logic                           uav_writeresponsevalid,
+
+   // -------------------
+   // Customizable Avalon Master
+   // -------------------
+   output logic [AV_ADDRESS_W - 1 : 0]    av_address,
+   output logic [AV_DATA_W - 1 : 0]       av_writedata,
+   output logic                           av_write,
+   output logic                           av_read,
+   output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
+   output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
+   output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
+   output logic                           av_begintransfer,
+   output wire                            av_chipselect,
+   output logic                           av_beginbursttransfer,
+   output logic                           av_lock,
+   output wire                            av_clken,
+   output wire                            av_debugaccess,
+   output wire                            av_outputenable,
+
+   input logic [AV_DATA_W - 1 : 0]        av_readdata,
+   input logic                            av_readdatavalid,
+   input logic                            av_waitrequest,
+
+   input logic [1:0]                      av_response,
+   // output logic                           av_writeresponserequest,
+   input wire                             av_writeresponsevalid
+
+);
+
+   function integer clog2_plusone;
+      input [31:0] Depth;
+      integer i;
+      begin
+         i = Depth;
+         for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
+            i = i >> 1;
+      end
+   endfunction
+
+   function integer max;
+      //returns the larger of two passed arguments
+      input [31:0] one;
+      input [31:0] two;
+      if(one > two)
+         max=one;
+      else
+         max=two;
+   endfunction // int
+
+   localparam AV_READ_WAIT_INDEXED      = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
+   localparam AV_WRITE_WAIT_INDEXED     = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
+   localparam AV_DATA_HOLD_INDEXED      = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
+   localparam LOG2_OF_LATENCY_SUM       = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
+   localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
+   localparam ADDRESS_SHIFT_SELECTOR    = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
+   localparam ADDRESS_HIGH              = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
+                                          AV_ADDRESS_W :
+                                          UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
+   localparam BURSTCOUNT_HIGH           = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
+                                          AV_BURSTCOUNT_W :
+                                          UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
+   localparam BYTEENABLE_ADDRESS_BITS   = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
+
+
+   // Calculate the symbols per word as the power of 2 extended symbols per word
+   wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
+   wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
+
+   // +--------------------------------
+   // |Backwards Compatibility Signals
+   // +--------------------------------
+   assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
+   assign av_debugaccess = uav_debugaccess;
+
+   // +-------------------
+   // |Passthru Signals
+   // +-------------------
+
+   reg [1 : 0] av_response_delayed;
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         av_response_delayed <= 2'b0;
+      end else begin
+         av_response_delayed <= av_response;
+      end
+   end
+
+   always_comb
+   begin
+      if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
+         uav_response = '0;
+      end else begin
+         if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
+            uav_response = av_response;
+         end else begin
+            uav_response = av_response_delayed;
+         end
+      end
+   end
+   // assign av_writeresponserequest = uav_writeresponserequest;
+   assign uav_writeresponsevalid = av_writeresponsevalid;
+
+   //-------------------------
+   //Writedata and Byteenable
+   //-------------------------
+
+   always@* begin
+      av_byteenable = '0;
+      av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
+   end
+
+   always@* begin
+      av_writedata = '0;
+      av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
+   end
+
+   // +-------------------
+   // |Calculated Signals
+   // +-------------------
+
+   logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
+
+   function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
+      input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
+
+      for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
+         if(byteenable[i] == 1) begin
+            return i;
+         end
+      end
+
+      return '0;
+
+   endfunction
+
+   reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
+   reg [AV_ADDRESS_W    - 1 : 0] address_reg;
+   always@(posedge clk, posedge reset) begin
+      if(reset) begin
+         burstcount_reg <= '0;
+         address_reg    <= '0;
+      end else begin
+         burstcount_reg <= burstcount_reg;
+         address_reg    <= address_reg;
+         if(av_beginbursttransfer) begin
+            burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
+            address_reg    <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
+         end
+      end
+   end
+
+   logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
+
+   always@* begin
+      if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
+         temp_wire = decode_byteenable(uav_byteenable);
+         real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
+      end else begin
+         real_uav_address = uav_address;
+      end
+
+      av_address = real_uav_address[ADDRESS_HIGH - 1  + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
+      if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
+         av_address = address_reg;
+   end
+
+   always@* begin
+      av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
+      if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
+         av_burstcount = burstcount_reg;
+   end
+
+   always@* begin
+      av_lock = uav_lock;
+   end
+
+   // -------------------
+   // Writebyteenable Assignment
+   // -------------------
+   always@* begin
+      av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
+   end
+
+   // -------------------
+   // Waitrequest Assignment
+   // -------------------
+
+   reg av_waitrequest_generated;
+   reg av_waitrequest_generated_read;
+   reg av_waitrequest_generated_write;
+   reg waitrequest_reset_override;
+   reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
+
+   always@(posedge reset, posedge clk) begin
+      if(reset) begin
+         wait_latency_counter <= '0;
+         waitrequest_reset_override <= 1'h1;
+      end else begin
+         waitrequest_reset_override <= 1'h0;
+         wait_latency_counter <= '0;
+         if( ~uav_waitrequest | waitrequest_reset_override )
+            wait_latency_counter <= '0;
+         else if( uav_read | uav_write )
+            wait_latency_counter <= wait_latency_counter + 1'h1;
+      end
+   end
+
+
+   always @* begin
+
+      av_read  = uav_read;
+      av_write = uav_write;
+      av_waitrequest_generated         = 1'h1;
+      av_waitrequest_generated_read    = 1'h1;
+      av_waitrequest_generated_write   = 1'h1;
+
+      if(LOG2_OF_LATENCY_SUM == 1)
+         av_waitrequest_generated = 0;
+
+      if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
+         av_read  = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
+         av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
+         av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
+         av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
+
+         if(uav_write)
+            av_waitrequest_generated = av_waitrequest_generated_write;
+         else
+            av_waitrequest_generated = av_waitrequest_generated_read;
+
+      end
+
+      if(USE_WAITREQUEST) begin
+         uav_waitrequest = av_waitrequest;
+      end else begin
+         uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
+      end
+
+   end
+
+   // --------------
+   // Readdata Assignment
+   // --------------
+
+   reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
+
+   always@(posedge clk, posedge reset) begin
+      if(reset)
+         av_readdata_pre <= 'b0;
+      else
+         av_readdata_pre <= av_readdata;
+   end
+
+   always@* begin
+      uav_readdata = {UAV_DATA_W{1'b0}};
+      if( AV_READLATENCY != 0  || USE_READDATAVALID ) begin
+         uav_readdata[AV_DATA_W-1:0] = av_readdata;
+      end else begin
+         uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
+      end
+   end
+   
+   // -------------------
+   // Readdatavalid Assigment
+   // -------------------
+   reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
+   reg top_read_latency_shift_reg;
+
+   always@* begin
+      uav_readdatavalid=top_read_latency_shift_reg;
+      if(USE_READDATAVALID) begin
+         uav_readdatavalid = av_readdatavalid;
+      end
+   end
+
+   always@* begin
+      top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
+      if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
+         top_read_latency_shift_reg=read_latency_shift_reg;
+      end
+      if (AV_READLATENCY > 1) begin
+         top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
+      end
+   end
+
+   always@(posedge reset, posedge clk) begin
+      if (reset) begin
+         read_latency_shift_reg <= '0;
+      end else if (av_clken) begin
+         read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override;
+         for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
+            read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
+         end
+      end
+   end
+
+   // ------------
+   // Chipselect and OutputEnable
+   // ------------
+   reg av_chipselect_pre;
+   wire cs_extension;
+   reg av_outputenable_pre;
+   
+   assign av_chipselect  = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
+   assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
+   assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
+
+   always@(posedge reset, posedge clk) begin
+      if(reset)
+         av_outputenable_pre <= 1'b0;
+      else if( AV_READLATENCY == 0  && AV_READ_WAIT_INDEXED != 0 )
+         av_outputenable_pre <= 0;
+      else
+         av_outputenable_pre <= cs_extension | uav_read;
+   end
+
+   always@(posedge reset, posedge clk) begin
+      if(reset) begin
+         av_chipselect_pre  <= 1'b0;
+      end else begin
+         av_chipselect_pre  <= 1'b0;
+         if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
+            //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
+            //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
+            if(uav_read) begin
+               av_chipselect_pre <= 1'b1;
+            end else if(cs_extension == 1) begin
+               av_chipselect_pre <= 1'b1;
+            end
+         end
+      end
+   end
+
+   // -------------------
+   // Begintransfer Assigment
+   // -------------------
+   reg end_begintransfer;
+
+   always@* begin
+      av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
+   end
+
+   always@ ( posedge clk or posedge reset ) begin
+      if(reset) begin
+         end_begintransfer <= 1'b0;
+      end else begin
+         if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
+            end_begintransfer <= 1'b1;
+         else if(uav_waitrequest)
+            end_begintransfer <= end_begintransfer;
+         else
+            end_begintransfer <= 1'b0;
+      end
+   end
+
+   // -------------------
+   // Beginbursttransfer Assigment
+   // -------------------
+   reg end_beginbursttransfer;
+   reg in_transfer;
+
+   always@* begin
+      av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
+   end
+
+   always@ ( posedge clk or posedge reset ) begin
+      if(reset) begin
+         end_beginbursttransfer <= 1'b0;
+         in_transfer <= 1'b0;
+      end else begin
+         end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
+         if(uav_write && uav_burstcount == symbols_per_word)
+            in_transfer <=1'b0;
+         else if(uav_write)
+            in_transfer <=1'b1;
+      end
+   end
+
+endmodule

nios2_uc/synthesis/submodules/altera_reset_controller.sdc

@@ -0,0 +1,30 @@
+# (C) 2001-2019 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and other 
+# software and tools, and its AMPP partner logic functions, and any output 
+# files from any of the foregoing (including device programming or simulation 
+# files), and any associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License Subscription 
+# Agreement, Intel FPGA IP License Agreement, or other applicable 
+# license agreement, including, without limitation, that your use is for the 
+# sole purpose of programming logic devices manufactured by Intel and sold by 
+# Intel or its authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+
+
+# +---------------------------------------------------
+# | Cut the async clear paths
+# +---------------------------------------------------
+set aclr_counter 0
+set clrn_counter 0
+set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
+set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
+set aclr_counter [get_collection_size $aclr_collection]
+set clrn_counter [get_collection_size $clrn_collection]
+
+if {$aclr_counter > 0} {
+    set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
+}
+
+if {$clrn_counter > 0} {
+    set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
+}

nios2_uc/synthesis/submodules/altera_reset_controller.v

@@ -0,0 +1,319 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// --------------------------------------
+// Reset controller
+//
+// Combines all the input resets and synchronizes
+// the result to the clk.
+// ACDS13.1 - Added reset request as part of reset sequencing
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_reset_controller
+#(
+    parameter NUM_RESET_INPUTS              = 6,
+    parameter USE_RESET_REQUEST_IN0 = 0,
+    parameter USE_RESET_REQUEST_IN1 = 0,
+    parameter USE_RESET_REQUEST_IN2 = 0,
+    parameter USE_RESET_REQUEST_IN3 = 0,
+    parameter USE_RESET_REQUEST_IN4 = 0,
+    parameter USE_RESET_REQUEST_IN5 = 0,
+    parameter USE_RESET_REQUEST_IN6 = 0,
+    parameter USE_RESET_REQUEST_IN7 = 0,
+    parameter USE_RESET_REQUEST_IN8 = 0,
+    parameter USE_RESET_REQUEST_IN9 = 0,
+    parameter USE_RESET_REQUEST_IN10 = 0,
+    parameter USE_RESET_REQUEST_IN11 = 0,
+    parameter USE_RESET_REQUEST_IN12 = 0,
+    parameter USE_RESET_REQUEST_IN13 = 0,
+    parameter USE_RESET_REQUEST_IN14 = 0,
+    parameter USE_RESET_REQUEST_IN15 = 0,
+    parameter OUTPUT_RESET_SYNC_EDGES       = "deassert",
+    parameter SYNC_DEPTH                    = 2,
+    parameter RESET_REQUEST_PRESENT         = 0,
+    parameter RESET_REQ_WAIT_TIME           = 3,
+    parameter MIN_RST_ASSERTION_TIME        = 11,
+    parameter RESET_REQ_EARLY_DSRT_TIME     = 4,
+    parameter ADAPT_RESET_REQUEST          = 0
+)
+(
+    // --------------------------------------
+    // We support up to 16 reset inputs, for now
+    // --------------------------------------
+    input reset_in0,
+    input reset_in1,
+    input reset_in2,
+    input reset_in3,
+    input reset_in4,
+    input reset_in5,
+    input reset_in6,
+    input reset_in7,
+    input reset_in8,
+    input reset_in9,
+    input reset_in10,
+    input reset_in11,
+    input reset_in12,
+    input reset_in13,
+    input reset_in14,
+    input reset_in15,
+    input reset_req_in0,
+    input reset_req_in1,
+    input reset_req_in2,
+    input reset_req_in3,
+    input reset_req_in4,
+    input reset_req_in5,
+    input reset_req_in6,
+    input reset_req_in7,
+    input reset_req_in8,
+    input reset_req_in9,
+    input reset_req_in10,
+    input reset_req_in11,
+    input reset_req_in12,
+    input reset_req_in13,
+    input reset_req_in14,
+    input reset_req_in15,
+
+
+    input  clk,
+    output reg reset_out,
+    output reg reset_req
+);
+
+   // Always use async reset synchronizer if reset_req is used
+   localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
+
+   // --------------------------------------
+   // Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
+   // --------------------------------------
+   localparam MIN_METASTABLE = 3;
+   localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
+
+   localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
+
+   localparam ASSERTION_CHAIN_LENGTH =  (MIN_METASTABLE > LARGER) ? 
+                                            MIN_RST_ASSERTION_TIME + 1 :
+                                        (
+                                        (MIN_RST_ASSERTION_TIME > LARGER)? 
+                                            MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
+                                            MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
+                                        );
+
+   localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
+   // --------------------------------------
+
+   wire merged_reset;
+   wire merged_reset_req_in;
+   wire reset_out_pre;
+   wire reset_req_pre;
+
+   // Registers and Interconnect
+   (*preserve*) reg  [RSTREQ_ASRT_SYNC_TAP: 0]  altera_reset_synchronizer_int_chain;
+   reg [ASSERTION_CHAIN_LENGTH-1: 0]            r_sync_rst_chain;
+   reg                                          r_sync_rst;
+   reg                                          r_early_rst;
+
+    // --------------------------------------
+    // "Or" all the input resets together
+    // --------------------------------------
+    assign merged_reset = (  
+                              reset_in0 | 
+                              reset_in1 | 
+                              reset_in2 | 
+                              reset_in3 | 
+                              reset_in4 | 
+                              reset_in5 | 
+                              reset_in6 | 
+                              reset_in7 | 
+                              reset_in8 | 
+                              reset_in9 | 
+                              reset_in10 | 
+                              reset_in11 | 
+                              reset_in12 | 
+                              reset_in13 | 
+                              reset_in14 | 
+                              reset_in15
+                          );
+
+    assign merged_reset_req_in = (
+                              ( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0) 
+                            );
+
+
+    // --------------------------------------
+    // And if required, synchronize it to the required clock domain,
+    // with the correct synchronization type
+    // --------------------------------------
+    generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
+
+        assign reset_out_pre = merged_reset;
+        assign reset_req_pre = merged_reset_req_in;
+
+    end else begin
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH),
+            .ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
+        )
+        alt_rst_sync_uq1
+        (
+            .clk        (clk),
+            .reset_in   (merged_reset),
+            .reset_out  (reset_out_pre)
+        );
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH),
+            .ASYNC_RESET(0)
+        )
+        alt_rst_req_sync_uq1
+        (
+            .clk        (clk),
+            .reset_in   (merged_reset_req_in),
+            .reset_out  (reset_req_pre)
+        );
+
+    end
+    endgenerate
+
+    generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
+                  ( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
+        always @* begin
+            reset_out = reset_out_pre;
+            reset_req = reset_req_pre;
+        end
+    end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
+
+        wire reset_out_pre2;
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH+1),
+            .ASYNC_RESET(0)
+        )
+        alt_rst_sync_uq2
+        (
+            .clk        (clk),
+            .reset_in   (reset_out_pre),
+            .reset_out  (reset_out_pre2)
+        );
+
+        always @* begin
+            reset_out = reset_out_pre2;
+            reset_req = reset_req_pre;
+        end
+
+    end
+    else begin
+
+    // 3-FF Metastability Synchronizer
+    initial
+    begin
+        altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
+    end
+
+    always @(posedge clk)
+    begin
+        altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <= 
+            {altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre}; 
+    end
+
+    // Synchronous reset pipe
+    initial
+    begin
+        r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
+    end
+
+    always @(posedge clk)
+    begin
+        if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
+        begin
+            r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
+    end
+    else
+    begin
+        r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
+    end
+    end
+
+    // Standard synchronous reset output.  From 0-1, the transition lags the early output.  For 1->0, the transition
+    // matches the early input.
+
+    always @(posedge clk)
+    begin
+        case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
+            3'b000:   r_sync_rst <= 1'b0; // Not reset
+            3'b001:   r_sync_rst <= 1'b0;
+            3'b010:   r_sync_rst <= 1'b0;
+            3'b011:   r_sync_rst <= 1'b1;
+            3'b100:   r_sync_rst <= 1'b1; 
+            3'b101:   r_sync_rst <= 1'b1;
+            3'b110:   r_sync_rst <= 1'b1;
+            3'b111:   r_sync_rst <= 1'b1; // In Reset
+            default:  r_sync_rst <= 1'b1;
+        endcase
+
+        case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
+            2'b00:   r_early_rst <= 1'b0; // Not reset
+            2'b01:   r_early_rst <= 1'b1; // Coming out of reset
+            2'b10:   r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
+            2'b11:   r_early_rst <= 1'b1; // Held in reset
+            default: r_early_rst <= 1'b1;
+        endcase
+    end
+
+    always @* begin
+        reset_out = r_sync_rst;
+        reset_req = r_early_rst;
+    end
+
+    end
+    endgenerate
+
+endmodule

nios2_uc/synthesis/submodules/altera_reset_synchronizer.v

@@ -0,0 +1,87 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -----------------------------------------------
+// Reset Synchronizer
+// -----------------------------------------------
+`timescale 1 ns / 1 ns
+
+module altera_reset_synchronizer
+#(
+    parameter ASYNC_RESET = 1,
+    parameter DEPTH       = 2
+)
+(
+    input   reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
+
+    input   clk,
+    output  reset_out
+);
+
+    // -----------------------------------------------
+    // Synchronizer register chain. We cannot reuse the
+    // standard synchronizer in this implementation 
+    // because our timing constraints are different.
+    //
+    // Instead of cutting the timing path to the d-input 
+    // on the first flop we need to cut the aclr input.
+    // 
+    // We omit the "preserve" attribute on the final
+    // output register, so that the synthesis tool can
+    // duplicate it where needed.
+    // -----------------------------------------------
+    (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
+    reg altera_reset_synchronizer_int_chain_out;
+
+    generate if (ASYNC_RESET) begin
+
+        // -----------------------------------------------
+        // Assert asynchronously, deassert synchronously.
+        // -----------------------------------------------
+        always @(posedge clk or posedge reset_in) begin
+            if (reset_in) begin
+                altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
+                altera_reset_synchronizer_int_chain_out <= 1'b1;
+            end
+            else begin
+                altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
+                altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
+                altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
+            end
+        end
+
+        assign reset_out = altera_reset_synchronizer_int_chain_out;
+     
+    end else begin
+
+        // -----------------------------------------------
+        // Assert synchronously, deassert synchronously.
+        // -----------------------------------------------
+        always @(posedge clk) begin
+            altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
+            altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
+            altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
+        end
+
+        assign reset_out = altera_reset_synchronizer_int_chain_out;
+ 
+    end
+    endgenerate
+
+endmodule
+

nios2_uc/synthesis/submodules/nios2_uc_irq_mapper.sv

@@ -0,0 +1,58 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Altera IRQ Mapper
+//
+// Parameters
+//   NUM_RCVRS        : 1
+//   SENDER_IRW_WIDTH : 32
+//   IRQ_MAP          : 0:0
+//
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module nios2_uc_irq_mapper
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // IRQ Receivers
+    // -------------------
+    input                receiver0_irq,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output reg [31 : 0] sender_irq
+);
+
+
+    always @* begin
+	sender_irq = 0;
+
+        sender_irq[0] = receiver0_irq;
+    end
+
+endmodule
+

nios2_uc/synthesis/submodules/nios2_uc_jtag_uart.v

@@ -0,0 +1,588 @@
+//Legal Notice: (C)2020 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_jtag_uart_sim_scfifo_w (
+                                         // inputs:
+                                          clk,
+                                          fifo_wdata,
+                                          fifo_wr,
+
+                                         // outputs:
+                                          fifo_FF,
+                                          r_dat,
+                                          wfifo_empty,
+                                          wfifo_used
+                                       )
+;
+
+  output           fifo_FF;
+  output  [  7: 0] r_dat;
+  output           wfifo_empty;
+  output  [  5: 0] wfifo_used;
+  input            clk;
+  input   [  7: 0] fifo_wdata;
+  input            fifo_wr;
+
+
+wire             fifo_FF;
+wire    [  7: 0] r_dat;
+wire             wfifo_empty;
+wire    [  5: 0] wfifo_used;
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  always @(posedge clk)
+    begin
+      if (fifo_wr)
+          $write("%c", fifo_wdata);
+    end
+
+
+  assign wfifo_used = {6{1'b0}};
+  assign r_dat = {8{1'b0}};
+  assign fifo_FF = 1'b0;
+  assign wfifo_empty = 1'b1;
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_jtag_uart_scfifo_w (
+                                     // inputs:
+                                      clk,
+                                      fifo_clear,
+                                      fifo_wdata,
+                                      fifo_wr,
+                                      rd_wfifo,
+
+                                     // outputs:
+                                      fifo_FF,
+                                      r_dat,
+                                      wfifo_empty,
+                                      wfifo_used
+                                   )
+;
+
+  output           fifo_FF;
+  output  [  7: 0] r_dat;
+  output           wfifo_empty;
+  output  [  5: 0] wfifo_used;
+  input            clk;
+  input            fifo_clear;
+  input   [  7: 0] fifo_wdata;
+  input            fifo_wr;
+  input            rd_wfifo;
+
+
+wire             fifo_FF;
+wire    [  7: 0] r_dat;
+wire             wfifo_empty;
+wire    [  5: 0] wfifo_used;
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  nios2_uc_jtag_uart_sim_scfifo_w the_nios2_uc_jtag_uart_sim_scfifo_w
+    (
+      .clk         (clk),
+      .fifo_FF     (fifo_FF),
+      .fifo_wdata  (fifo_wdata),
+      .fifo_wr     (fifo_wr),
+      .r_dat       (r_dat),
+      .wfifo_empty (wfifo_empty),
+      .wfifo_used  (wfifo_used)
+    );
+
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  scfifo wfifo
+//    (
+//      .aclr (fifo_clear),
+//      .clock (clk),
+//      .data (fifo_wdata),
+//      .empty (wfifo_empty),
+//      .full (fifo_FF),
+//      .q (r_dat),
+//      .rdreq (rd_wfifo),
+//      .usedw (wfifo_used),
+//      .wrreq (fifo_wr)
+//    );
+//
+//  defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
+//           wfifo.lpm_numwords = 64,
+//           wfifo.lpm_showahead = "OFF",
+//           wfifo.lpm_type = "scfifo",
+//           wfifo.lpm_width = 8,
+//           wfifo.lpm_widthu = 6,
+//           wfifo.overflow_checking = "OFF",
+//           wfifo.underflow_checking = "OFF",
+//           wfifo.use_eab = "ON";
+//
+//synthesis read_comments_as_HDL off
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_jtag_uart_sim_scfifo_r (
+                                         // inputs:
+                                          clk,
+                                          fifo_rd,
+                                          rst_n,
+
+                                         // outputs:
+                                          fifo_EF,
+                                          fifo_rdata,
+                                          rfifo_full,
+                                          rfifo_used
+                                       )
+;
+
+  output           fifo_EF;
+  output  [  7: 0] fifo_rdata;
+  output           rfifo_full;
+  output  [  5: 0] rfifo_used;
+  input            clk;
+  input            fifo_rd;
+  input            rst_n;
+
+
+reg     [ 31: 0] bytes_left;
+wire             fifo_EF;
+reg              fifo_rd_d;
+wire    [  7: 0] fifo_rdata;
+wire             new_rom;
+wire    [ 31: 0] num_bytes;
+wire    [  6: 0] rfifo_entries;
+wire             rfifo_full;
+wire    [  5: 0] rfifo_used;
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  // Generate rfifo_entries for simulation
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (rst_n == 0)
+        begin
+          bytes_left <= 32'h0;
+          fifo_rd_d <= 1'b0;
+        end
+      else 
+        begin
+          fifo_rd_d <= fifo_rd;
+          // decrement on read
+          if (fifo_rd_d)
+              bytes_left <= bytes_left - 1'b1;
+          // catch new contents
+          if (new_rom)
+              bytes_left <= num_bytes;
+        end
+    end
+
+
+  assign fifo_EF = bytes_left == 32'b0;
+  assign rfifo_full = bytes_left > 7'h40;
+  assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
+  assign rfifo_used = rfifo_entries[5 : 0];
+  assign new_rom = 1'b0;
+  assign num_bytes = 32'b0;
+  assign fifo_rdata = 8'b0;
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_jtag_uart_scfifo_r (
+                                     // inputs:
+                                      clk,
+                                      fifo_clear,
+                                      fifo_rd,
+                                      rst_n,
+                                      t_dat,
+                                      wr_rfifo,
+
+                                     // outputs:
+                                      fifo_EF,
+                                      fifo_rdata,
+                                      rfifo_full,
+                                      rfifo_used
+                                   )
+;
+
+  output           fifo_EF;
+  output  [  7: 0] fifo_rdata;
+  output           rfifo_full;
+  output  [  5: 0] rfifo_used;
+  input            clk;
+  input            fifo_clear;
+  input            fifo_rd;
+  input            rst_n;
+  input   [  7: 0] t_dat;
+  input            wr_rfifo;
+
+
+wire             fifo_EF;
+wire    [  7: 0] fifo_rdata;
+wire             rfifo_full;
+wire    [  5: 0] rfifo_used;
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  nios2_uc_jtag_uart_sim_scfifo_r the_nios2_uc_jtag_uart_sim_scfifo_r
+    (
+      .clk        (clk),
+      .fifo_EF    (fifo_EF),
+      .fifo_rd    (fifo_rd),
+      .fifo_rdata (fifo_rdata),
+      .rfifo_full (rfifo_full),
+      .rfifo_used (rfifo_used),
+      .rst_n      (rst_n)
+    );
+
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  scfifo rfifo
+//    (
+//      .aclr (fifo_clear),
+//      .clock (clk),
+//      .data (t_dat),
+//      .empty (fifo_EF),
+//      .full (rfifo_full),
+//      .q (fifo_rdata),
+//      .rdreq (fifo_rd),
+//      .usedw (rfifo_used),
+//      .wrreq (wr_rfifo)
+//    );
+//
+//  defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
+//           rfifo.lpm_numwords = 64,
+//           rfifo.lpm_showahead = "OFF",
+//           rfifo.lpm_type = "scfifo",
+//           rfifo.lpm_width = 8,
+//           rfifo.lpm_widthu = 6,
+//           rfifo.overflow_checking = "OFF",
+//           rfifo.underflow_checking = "OFF",
+//           rfifo.use_eab = "ON";
+//
+//synthesis read_comments_as_HDL off
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_jtag_uart (
+                            // inputs:
+                             av_address,
+                             av_chipselect,
+                             av_read_n,
+                             av_write_n,
+                             av_writedata,
+                             clk,
+                             rst_n,
+
+                            // outputs:
+                             av_irq,
+                             av_readdata,
+                             av_waitrequest,
+                             dataavailable,
+                             readyfordata
+                          )
+  /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
+
+  output           av_irq;
+  output  [ 31: 0] av_readdata;
+  output           av_waitrequest;
+  output           dataavailable;
+  output           readyfordata;
+  input            av_address;
+  input            av_chipselect;
+  input            av_read_n;
+  input            av_write_n;
+  input   [ 31: 0] av_writedata;
+  input            clk;
+  input            rst_n;
+
+
+reg              ac;
+wire             activity;
+wire             av_irq;
+wire    [ 31: 0] av_readdata;
+reg              av_waitrequest;
+reg              dataavailable;
+reg              fifo_AE;
+reg              fifo_AF;
+wire             fifo_EF;
+wire             fifo_FF;
+wire             fifo_clear;
+wire             fifo_rd;
+wire    [  7: 0] fifo_rdata;
+wire    [  7: 0] fifo_wdata;
+reg              fifo_wr;
+reg              ien_AE;
+reg              ien_AF;
+wire             ipen_AE;
+wire             ipen_AF;
+reg              pause_irq;
+wire    [  7: 0] r_dat;
+wire             r_ena;
+reg              r_val;
+wire             rd_wfifo;
+reg              read_0;
+reg              readyfordata;
+wire             rfifo_full;
+wire    [  5: 0] rfifo_used;
+reg              rvalid;
+reg              sim_r_ena;
+reg              sim_t_dat;
+reg              sim_t_ena;
+reg              sim_t_pause;
+wire    [  7: 0] t_dat;
+reg              t_dav;
+wire             t_ena;
+wire             t_pause;
+wire             wfifo_empty;
+wire    [  5: 0] wfifo_used;
+reg              woverflow;
+wire             wr_rfifo;
+  //avalon_jtag_slave, which is an e_avalon_slave
+  assign rd_wfifo = r_ena & ~wfifo_empty;
+  assign wr_rfifo = t_ena & ~rfifo_full;
+  assign fifo_clear = ~rst_n;
+  nios2_uc_jtag_uart_scfifo_w the_nios2_uc_jtag_uart_scfifo_w
+    (
+      .clk         (clk),
+      .fifo_FF     (fifo_FF),
+      .fifo_clear  (fifo_clear),
+      .fifo_wdata  (fifo_wdata),
+      .fifo_wr     (fifo_wr),
+      .r_dat       (r_dat),
+      .rd_wfifo    (rd_wfifo),
+      .wfifo_empty (wfifo_empty),
+      .wfifo_used  (wfifo_used)
+    );
+
+  nios2_uc_jtag_uart_scfifo_r the_nios2_uc_jtag_uart_scfifo_r
+    (
+      .clk        (clk),
+      .fifo_EF    (fifo_EF),
+      .fifo_clear (fifo_clear),
+      .fifo_rd    (fifo_rd),
+      .fifo_rdata (fifo_rdata),
+      .rfifo_full (rfifo_full),
+      .rfifo_used (rfifo_used),
+      .rst_n      (rst_n),
+      .t_dat      (t_dat),
+      .wr_rfifo   (wr_rfifo)
+    );
+
+  assign ipen_AE = ien_AE & fifo_AE;
+  assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
+  assign av_irq = ipen_AE | ipen_AF;
+  assign activity = t_pause | t_ena;
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (rst_n == 0)
+          pause_irq <= 1'b0;
+      else // only if fifo is not empty...
+      if (t_pause & ~fifo_EF)
+          pause_irq <= 1'b1;
+      else if (read_0)
+          pause_irq <= 1'b0;
+    end
+
+
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (rst_n == 0)
+        begin
+          r_val <= 1'b0;
+          t_dav <= 1'b1;
+        end
+      else 
+        begin
+          r_val <= r_ena & ~wfifo_empty;
+          t_dav <= ~rfifo_full;
+        end
+    end
+
+
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (rst_n == 0)
+        begin
+          fifo_AE <= 1'b0;
+          fifo_AF <= 1'b0;
+          fifo_wr <= 1'b0;
+          rvalid <= 1'b0;
+          read_0 <= 1'b0;
+          ien_AE <= 1'b0;
+          ien_AF <= 1'b0;
+          ac <= 1'b0;
+          woverflow <= 1'b0;
+          av_waitrequest <= 1'b1;
+        end
+      else 
+        begin
+          fifo_AE <= {fifo_FF,wfifo_used} <= 8;
+          fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
+          fifo_wr <= 1'b0;
+          read_0 <= 1'b0;
+          av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
+          if (activity)
+              ac <= 1'b1;
+          // write
+          if (av_chipselect & ~av_write_n & av_waitrequest)
+              // addr 1 is control; addr 0 is data
+              if (av_address)
+                begin
+                  ien_AF <= av_writedata[0];
+                  ien_AE <= av_writedata[1];
+                  if (av_writedata[10] & ~activity)
+                      ac <= 1'b0;
+                end
+              else 
+                begin
+                  fifo_wr <= ~fifo_FF;
+                  woverflow <= fifo_FF;
+                end
+          // read
+          if (av_chipselect & ~av_read_n & av_waitrequest)
+            begin
+              // addr 1 is interrupt; addr 0 is data
+              if (~av_address)
+                  rvalid <= ~fifo_EF;
+              read_0 <= ~av_address;
+            end
+        end
+    end
+
+
+  assign fifo_wdata = av_writedata[7 : 0];
+  assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
+  assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
+  always @(posedge clk or negedge rst_n)
+    begin
+      if (rst_n == 0)
+          readyfordata <= 0;
+      else 
+        readyfordata <= ~fifo_FF;
+    end
+
+
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  // Tie off Atlantic Interface signals not used for simulation
+  always @(posedge clk)
+    begin
+      sim_t_pause <= 1'b0;
+      sim_t_ena <= 1'b0;
+      sim_t_dat <= t_dav ? r_dat : {8{r_val}};
+      sim_r_ena <= 1'b0;
+    end
+
+
+  assign r_ena = sim_r_ena;
+  assign t_ena = sim_t_ena;
+  assign t_dat = sim_t_dat;
+  assign t_pause = sim_t_pause;
+  always @(fifo_EF)
+    begin
+      dataavailable = ~fifo_EF;
+    end
+
+
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  alt_jtag_atlantic nios2_uc_jtag_uart_alt_jtag_atlantic
+//    (
+//      .clk (clk),
+//      .r_dat (r_dat),
+//      .r_ena (r_ena),
+//      .r_val (r_val),
+//      .rst_n (rst_n),
+//      .t_dat (t_dat),
+//      .t_dav (t_dav),
+//      .t_ena (t_ena),
+//      .t_pause (t_pause)
+//    );
+//
+//  defparam nios2_uc_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
+//           nios2_uc_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
+//           nios2_uc_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
+//           nios2_uc_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
+//
+//  always @(posedge clk or negedge rst_n)
+//    begin
+//      if (rst_n == 0)
+//          dataavailable <= 0;
+//      else 
+//        dataavailable <= ~fifo_EF;
+//    end
+//
+//
+//synthesis read_comments_as_HDL off
+
+endmodule
+

nios2_uc/synthesis/submodules/nios2_uc_mm_interconnect_0.v

@@ -0,0 +1,1960 @@
+// nios2_uc_mm_interconnect_0.v
+
+// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.1 646
+
+`timescale 1 ps / 1 ps
+module nios2_uc_mm_interconnect_0 (
+		input  wire        clk_50_clk_clk,                          //                        clk_50_clk.clk
+		input  wire        nios2_reset_reset_bridge_in_reset_reset, // nios2_reset_reset_bridge_in_reset.reset
+		input  wire [19:0] nios2_data_master_address,               //                 nios2_data_master.address
+		output wire        nios2_data_master_waitrequest,           //                                  .waitrequest
+		input  wire [3:0]  nios2_data_master_byteenable,            //                                  .byteenable
+		input  wire        nios2_data_master_read,                  //                                  .read
+		output wire [31:0] nios2_data_master_readdata,              //                                  .readdata
+		input  wire        nios2_data_master_write,                 //                                  .write
+		input  wire [31:0] nios2_data_master_writedata,             //                                  .writedata
+		input  wire        nios2_data_master_debugaccess,           //                                  .debugaccess
+		input  wire [19:0] nios2_instruction_master_address,        //          nios2_instruction_master.address
+		output wire        nios2_instruction_master_waitrequest,    //                                  .waitrequest
+		input  wire        nios2_instruction_master_read,           //                                  .read
+		output wire [31:0] nios2_instruction_master_readdata,       //                                  .readdata
+		output wire [0:0]  jtag_uart_avalon_jtag_slave_address,     //       jtag_uart_avalon_jtag_slave.address
+		output wire        jtag_uart_avalon_jtag_slave_write,       //                                  .write
+		output wire        jtag_uart_avalon_jtag_slave_read,        //                                  .read
+		input  wire [31:0] jtag_uart_avalon_jtag_slave_readdata,    //                                  .readdata
+		output wire [31:0] jtag_uart_avalon_jtag_slave_writedata,   //                                  .writedata
+		input  wire        jtag_uart_avalon_jtag_slave_waitrequest, //                                  .waitrequest
+		output wire        jtag_uart_avalon_jtag_slave_chipselect,  //                                  .chipselect
+		output wire [8:0]  nios2_debug_mem_slave_address,           //             nios2_debug_mem_slave.address
+		output wire        nios2_debug_mem_slave_write,             //                                  .write
+		output wire        nios2_debug_mem_slave_read,              //                                  .read
+		input  wire [31:0] nios2_debug_mem_slave_readdata,          //                                  .readdata
+		output wire [31:0] nios2_debug_mem_slave_writedata,         //                                  .writedata
+		output wire [3:0]  nios2_debug_mem_slave_byteenable,        //                                  .byteenable
+		input  wire        nios2_debug_mem_slave_waitrequest,       //                                  .waitrequest
+		output wire        nios2_debug_mem_slave_debugaccess,       //                                  .debugaccess
+		output wire [15:0] onchip_memory2_s1_address,               //                 onchip_memory2_s1.address
+		output wire        onchip_memory2_s1_write,                 //                                  .write
+		input  wire [31:0] onchip_memory2_s1_readdata,              //                                  .readdata
+		output wire [31:0] onchip_memory2_s1_writedata,             //                                  .writedata
+		output wire [3:0]  onchip_memory2_s1_byteenable,            //                                  .byteenable
+		output wire        onchip_memory2_s1_chipselect,            //                                  .chipselect
+		output wire        onchip_memory2_s1_clken,                 //                                  .clken
+		output wire [1:0]  pio_LED_s1_address,                      //                        pio_LED_s1.address
+		output wire        pio_LED_s1_write,                        //                                  .write
+		input  wire [31:0] pio_LED_s1_readdata,                     //                                  .readdata
+		output wire [31:0] pio_LED_s1_writedata,                    //                                  .writedata
+		output wire        pio_LED_s1_chipselect                    //                                  .chipselect
+	);
+
+	wire         nios2_data_master_translator_avalon_universal_master_0_waitrequest;          // nios2_data_master_agent:av_waitrequest -> nios2_data_master_translator:uav_waitrequest
+	wire  [31:0] nios2_data_master_translator_avalon_universal_master_0_readdata;             // nios2_data_master_agent:av_readdata -> nios2_data_master_translator:uav_readdata
+	wire         nios2_data_master_translator_avalon_universal_master_0_debugaccess;          // nios2_data_master_translator:uav_debugaccess -> nios2_data_master_agent:av_debugaccess
+	wire  [19:0] nios2_data_master_translator_avalon_universal_master_0_address;              // nios2_data_master_translator:uav_address -> nios2_data_master_agent:av_address
+	wire         nios2_data_master_translator_avalon_universal_master_0_read;                 // nios2_data_master_translator:uav_read -> nios2_data_master_agent:av_read
+	wire   [3:0] nios2_data_master_translator_avalon_universal_master_0_byteenable;           // nios2_data_master_translator:uav_byteenable -> nios2_data_master_agent:av_byteenable
+	wire         nios2_data_master_translator_avalon_universal_master_0_readdatavalid;        // nios2_data_master_agent:av_readdatavalid -> nios2_data_master_translator:uav_readdatavalid
+	wire         nios2_data_master_translator_avalon_universal_master_0_lock;                 // nios2_data_master_translator:uav_lock -> nios2_data_master_agent:av_lock
+	wire         nios2_data_master_translator_avalon_universal_master_0_write;                // nios2_data_master_translator:uav_write -> nios2_data_master_agent:av_write
+	wire  [31:0] nios2_data_master_translator_avalon_universal_master_0_writedata;            // nios2_data_master_translator:uav_writedata -> nios2_data_master_agent:av_writedata
+	wire   [2:0] nios2_data_master_translator_avalon_universal_master_0_burstcount;           // nios2_data_master_translator:uav_burstcount -> nios2_data_master_agent:av_burstcount
+	wire         rsp_mux_src_valid;                                                           // rsp_mux:src_valid -> nios2_data_master_agent:rp_valid
+	wire  [93:0] rsp_mux_src_data;                                                            // rsp_mux:src_data -> nios2_data_master_agent:rp_data
+	wire         rsp_mux_src_ready;                                                           // nios2_data_master_agent:rp_ready -> rsp_mux:src_ready
+	wire   [3:0] rsp_mux_src_channel;                                                         // rsp_mux:src_channel -> nios2_data_master_agent:rp_channel
+	wire         rsp_mux_src_startofpacket;                                                   // rsp_mux:src_startofpacket -> nios2_data_master_agent:rp_startofpacket
+	wire         rsp_mux_src_endofpacket;                                                     // rsp_mux:src_endofpacket -> nios2_data_master_agent:rp_endofpacket
+	wire         nios2_instruction_master_translator_avalon_universal_master_0_waitrequest;   // nios2_instruction_master_agent:av_waitrequest -> nios2_instruction_master_translator:uav_waitrequest
+	wire  [31:0] nios2_instruction_master_translator_avalon_universal_master_0_readdata;      // nios2_instruction_master_agent:av_readdata -> nios2_instruction_master_translator:uav_readdata
+	wire         nios2_instruction_master_translator_avalon_universal_master_0_debugaccess;   // nios2_instruction_master_translator:uav_debugaccess -> nios2_instruction_master_agent:av_debugaccess
+	wire  [19:0] nios2_instruction_master_translator_avalon_universal_master_0_address;       // nios2_instruction_master_translator:uav_address -> nios2_instruction_master_agent:av_address
+	wire         nios2_instruction_master_translator_avalon_universal_master_0_read;          // nios2_instruction_master_translator:uav_read -> nios2_instruction_master_agent:av_read
+	wire   [3:0] nios2_instruction_master_translator_avalon_universal_master_0_byteenable;    // nios2_instruction_master_translator:uav_byteenable -> nios2_instruction_master_agent:av_byteenable
+	wire         nios2_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_instruction_master_agent:av_readdatavalid -> nios2_instruction_master_translator:uav_readdatavalid
+	wire         nios2_instruction_master_translator_avalon_universal_master_0_lock;          // nios2_instruction_master_translator:uav_lock -> nios2_instruction_master_agent:av_lock
+	wire         nios2_instruction_master_translator_avalon_universal_master_0_write;         // nios2_instruction_master_translator:uav_write -> nios2_instruction_master_agent:av_write
+	wire  [31:0] nios2_instruction_master_translator_avalon_universal_master_0_writedata;     // nios2_instruction_master_translator:uav_writedata -> nios2_instruction_master_agent:av_writedata
+	wire   [2:0] nios2_instruction_master_translator_avalon_universal_master_0_burstcount;    // nios2_instruction_master_translator:uav_burstcount -> nios2_instruction_master_agent:av_burstcount
+	wire         rsp_mux_001_src_valid;                                                       // rsp_mux_001:src_valid -> nios2_instruction_master_agent:rp_valid
+	wire  [93:0] rsp_mux_001_src_data;                                                        // rsp_mux_001:src_data -> nios2_instruction_master_agent:rp_data
+	wire         rsp_mux_001_src_ready;                                                       // nios2_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
+	wire   [3:0] rsp_mux_001_src_channel;                                                     // rsp_mux_001:src_channel -> nios2_instruction_master_agent:rp_channel
+	wire         rsp_mux_001_src_startofpacket;                                               // rsp_mux_001:src_startofpacket -> nios2_instruction_master_agent:rp_startofpacket
+	wire         rsp_mux_001_src_endofpacket;                                                 // rsp_mux_001:src_endofpacket -> nios2_instruction_master_agent:rp_endofpacket
+	wire  [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata;                               // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
+	wire         jtag_uart_avalon_jtag_slave_agent_m0_waitrequest;                            // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
+	wire         jtag_uart_avalon_jtag_slave_agent_m0_debugaccess;                            // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
+	wire  [19:0] jtag_uart_avalon_jtag_slave_agent_m0_address;                                // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
+	wire   [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable;                             // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
+	wire         jtag_uart_avalon_jtag_slave_agent_m0_read;                                   // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
+	wire         jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid;                          // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
+	wire         jtag_uart_avalon_jtag_slave_agent_m0_lock;                                   // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
+	wire  [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata;                              // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
+	wire         jtag_uart_avalon_jtag_slave_agent_m0_write;                                  // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
+	wire   [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount;                             // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
+	wire         jtag_uart_avalon_jtag_slave_agent_rf_source_valid;                           // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
+	wire  [94:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data;                            // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
+	wire         jtag_uart_avalon_jtag_slave_agent_rf_source_ready;                           // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
+	wire         jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket;                   // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
+	wire         jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket;                     // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
+	wire         jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid;                        // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
+	wire  [94:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data;                         // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
+	wire         jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready;                        // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
+	wire         jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket;                // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
+	wire         jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket;                  // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
+	wire         cmd_mux_src_valid;                                                           // cmd_mux:src_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
+	wire  [93:0] cmd_mux_src_data;                                                            // cmd_mux:src_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
+	wire         cmd_mux_src_ready;                                                           // jtag_uart_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
+	wire   [3:0] cmd_mux_src_channel;                                                         // cmd_mux:src_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
+	wire         cmd_mux_src_startofpacket;                                                   // cmd_mux:src_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
+	wire         cmd_mux_src_endofpacket;                                                     // cmd_mux:src_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
+	wire  [31:0] nios2_debug_mem_slave_agent_m0_readdata;                                     // nios2_debug_mem_slave_translator:uav_readdata -> nios2_debug_mem_slave_agent:m0_readdata
+	wire         nios2_debug_mem_slave_agent_m0_waitrequest;                                  // nios2_debug_mem_slave_translator:uav_waitrequest -> nios2_debug_mem_slave_agent:m0_waitrequest
+	wire         nios2_debug_mem_slave_agent_m0_debugaccess;                                  // nios2_debug_mem_slave_agent:m0_debugaccess -> nios2_debug_mem_slave_translator:uav_debugaccess
+	wire  [19:0] nios2_debug_mem_slave_agent_m0_address;                                      // nios2_debug_mem_slave_agent:m0_address -> nios2_debug_mem_slave_translator:uav_address
+	wire   [3:0] nios2_debug_mem_slave_agent_m0_byteenable;                                   // nios2_debug_mem_slave_agent:m0_byteenable -> nios2_debug_mem_slave_translator:uav_byteenable
+	wire         nios2_debug_mem_slave_agent_m0_read;                                         // nios2_debug_mem_slave_agent:m0_read -> nios2_debug_mem_slave_translator:uav_read
+	wire         nios2_debug_mem_slave_agent_m0_readdatavalid;                                // nios2_debug_mem_slave_translator:uav_readdatavalid -> nios2_debug_mem_slave_agent:m0_readdatavalid
+	wire         nios2_debug_mem_slave_agent_m0_lock;                                         // nios2_debug_mem_slave_agent:m0_lock -> nios2_debug_mem_slave_translator:uav_lock
+	wire  [31:0] nios2_debug_mem_slave_agent_m0_writedata;                                    // nios2_debug_mem_slave_agent:m0_writedata -> nios2_debug_mem_slave_translator:uav_writedata
+	wire         nios2_debug_mem_slave_agent_m0_write;                                        // nios2_debug_mem_slave_agent:m0_write -> nios2_debug_mem_slave_translator:uav_write
+	wire   [2:0] nios2_debug_mem_slave_agent_m0_burstcount;                                   // nios2_debug_mem_slave_agent:m0_burstcount -> nios2_debug_mem_slave_translator:uav_burstcount
+	wire         nios2_debug_mem_slave_agent_rf_source_valid;                                 // nios2_debug_mem_slave_agent:rf_source_valid -> nios2_debug_mem_slave_agent_rsp_fifo:in_valid
+	wire  [94:0] nios2_debug_mem_slave_agent_rf_source_data;                                  // nios2_debug_mem_slave_agent:rf_source_data -> nios2_debug_mem_slave_agent_rsp_fifo:in_data
+	wire         nios2_debug_mem_slave_agent_rf_source_ready;                                 // nios2_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_debug_mem_slave_agent:rf_source_ready
+	wire         nios2_debug_mem_slave_agent_rf_source_startofpacket;                         // nios2_debug_mem_slave_agent:rf_source_startofpacket -> nios2_debug_mem_slave_agent_rsp_fifo:in_startofpacket
+	wire         nios2_debug_mem_slave_agent_rf_source_endofpacket;                           // nios2_debug_mem_slave_agent:rf_source_endofpacket -> nios2_debug_mem_slave_agent_rsp_fifo:in_endofpacket
+	wire         nios2_debug_mem_slave_agent_rsp_fifo_out_valid;                              // nios2_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_debug_mem_slave_agent:rf_sink_valid
+	wire  [94:0] nios2_debug_mem_slave_agent_rsp_fifo_out_data;                               // nios2_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_debug_mem_slave_agent:rf_sink_data
+	wire         nios2_debug_mem_slave_agent_rsp_fifo_out_ready;                              // nios2_debug_mem_slave_agent:rf_sink_ready -> nios2_debug_mem_slave_agent_rsp_fifo:out_ready
+	wire         nios2_debug_mem_slave_agent_rsp_fifo_out_startofpacket;                      // nios2_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_debug_mem_slave_agent:rf_sink_startofpacket
+	wire         nios2_debug_mem_slave_agent_rsp_fifo_out_endofpacket;                        // nios2_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_debug_mem_slave_agent:rf_sink_endofpacket
+	wire         cmd_mux_001_src_valid;                                                       // cmd_mux_001:src_valid -> nios2_debug_mem_slave_agent:cp_valid
+	wire  [93:0] cmd_mux_001_src_data;                                                        // cmd_mux_001:src_data -> nios2_debug_mem_slave_agent:cp_data
+	wire         cmd_mux_001_src_ready;                                                       // nios2_debug_mem_slave_agent:cp_ready -> cmd_mux_001:src_ready
+	wire   [3:0] cmd_mux_001_src_channel;                                                     // cmd_mux_001:src_channel -> nios2_debug_mem_slave_agent:cp_channel
+	wire         cmd_mux_001_src_startofpacket;                                               // cmd_mux_001:src_startofpacket -> nios2_debug_mem_slave_agent:cp_startofpacket
+	wire         cmd_mux_001_src_endofpacket;                                                 // cmd_mux_001:src_endofpacket -> nios2_debug_mem_slave_agent:cp_endofpacket
+	wire  [31:0] onchip_memory2_s1_agent_m0_readdata;                                         // onchip_memory2_s1_translator:uav_readdata -> onchip_memory2_s1_agent:m0_readdata
+	wire         onchip_memory2_s1_agent_m0_waitrequest;                                      // onchip_memory2_s1_translator:uav_waitrequest -> onchip_memory2_s1_agent:m0_waitrequest
+	wire         onchip_memory2_s1_agent_m0_debugaccess;                                      // onchip_memory2_s1_agent:m0_debugaccess -> onchip_memory2_s1_translator:uav_debugaccess
+	wire  [19:0] onchip_memory2_s1_agent_m0_address;                                          // onchip_memory2_s1_agent:m0_address -> onchip_memory2_s1_translator:uav_address
+	wire   [3:0] onchip_memory2_s1_agent_m0_byteenable;                                       // onchip_memory2_s1_agent:m0_byteenable -> onchip_memory2_s1_translator:uav_byteenable
+	wire         onchip_memory2_s1_agent_m0_read;                                             // onchip_memory2_s1_agent:m0_read -> onchip_memory2_s1_translator:uav_read
+	wire         onchip_memory2_s1_agent_m0_readdatavalid;                                    // onchip_memory2_s1_translator:uav_readdatavalid -> onchip_memory2_s1_agent:m0_readdatavalid
+	wire         onchip_memory2_s1_agent_m0_lock;                                             // onchip_memory2_s1_agent:m0_lock -> onchip_memory2_s1_translator:uav_lock
+	wire  [31:0] onchip_memory2_s1_agent_m0_writedata;                                        // onchip_memory2_s1_agent:m0_writedata -> onchip_memory2_s1_translator:uav_writedata
+	wire         onchip_memory2_s1_agent_m0_write;                                            // onchip_memory2_s1_agent:m0_write -> onchip_memory2_s1_translator:uav_write
+	wire   [2:0] onchip_memory2_s1_agent_m0_burstcount;                                       // onchip_memory2_s1_agent:m0_burstcount -> onchip_memory2_s1_translator:uav_burstcount
+	wire         onchip_memory2_s1_agent_rf_source_valid;                                     // onchip_memory2_s1_agent:rf_source_valid -> onchip_memory2_s1_agent_rsp_fifo:in_valid
+	wire  [94:0] onchip_memory2_s1_agent_rf_source_data;                                      // onchip_memory2_s1_agent:rf_source_data -> onchip_memory2_s1_agent_rsp_fifo:in_data
+	wire         onchip_memory2_s1_agent_rf_source_ready;                                     // onchip_memory2_s1_agent_rsp_fifo:in_ready -> onchip_memory2_s1_agent:rf_source_ready
+	wire         onchip_memory2_s1_agent_rf_source_startofpacket;                             // onchip_memory2_s1_agent:rf_source_startofpacket -> onchip_memory2_s1_agent_rsp_fifo:in_startofpacket
+	wire         onchip_memory2_s1_agent_rf_source_endofpacket;                               // onchip_memory2_s1_agent:rf_source_endofpacket -> onchip_memory2_s1_agent_rsp_fifo:in_endofpacket
+	wire         onchip_memory2_s1_agent_rsp_fifo_out_valid;                                  // onchip_memory2_s1_agent_rsp_fifo:out_valid -> onchip_memory2_s1_agent:rf_sink_valid
+	wire  [94:0] onchip_memory2_s1_agent_rsp_fifo_out_data;                                   // onchip_memory2_s1_agent_rsp_fifo:out_data -> onchip_memory2_s1_agent:rf_sink_data
+	wire         onchip_memory2_s1_agent_rsp_fifo_out_ready;                                  // onchip_memory2_s1_agent:rf_sink_ready -> onchip_memory2_s1_agent_rsp_fifo:out_ready
+	wire         onchip_memory2_s1_agent_rsp_fifo_out_startofpacket;                          // onchip_memory2_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_s1_agent:rf_sink_startofpacket
+	wire         onchip_memory2_s1_agent_rsp_fifo_out_endofpacket;                            // onchip_memory2_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_s1_agent:rf_sink_endofpacket
+	wire         cmd_mux_002_src_valid;                                                       // cmd_mux_002:src_valid -> onchip_memory2_s1_agent:cp_valid
+	wire  [93:0] cmd_mux_002_src_data;                                                        // cmd_mux_002:src_data -> onchip_memory2_s1_agent:cp_data
+	wire         cmd_mux_002_src_ready;                                                       // onchip_memory2_s1_agent:cp_ready -> cmd_mux_002:src_ready
+	wire   [3:0] cmd_mux_002_src_channel;                                                     // cmd_mux_002:src_channel -> onchip_memory2_s1_agent:cp_channel
+	wire         cmd_mux_002_src_startofpacket;                                               // cmd_mux_002:src_startofpacket -> onchip_memory2_s1_agent:cp_startofpacket
+	wire         cmd_mux_002_src_endofpacket;                                                 // cmd_mux_002:src_endofpacket -> onchip_memory2_s1_agent:cp_endofpacket
+	wire  [31:0] pio_led_s1_agent_m0_readdata;                                                // pio_LED_s1_translator:uav_readdata -> pio_LED_s1_agent:m0_readdata
+	wire         pio_led_s1_agent_m0_waitrequest;                                             // pio_LED_s1_translator:uav_waitrequest -> pio_LED_s1_agent:m0_waitrequest
+	wire         pio_led_s1_agent_m0_debugaccess;                                             // pio_LED_s1_agent:m0_debugaccess -> pio_LED_s1_translator:uav_debugaccess
+	wire  [19:0] pio_led_s1_agent_m0_address;                                                 // pio_LED_s1_agent:m0_address -> pio_LED_s1_translator:uav_address
+	wire   [3:0] pio_led_s1_agent_m0_byteenable;                                              // pio_LED_s1_agent:m0_byteenable -> pio_LED_s1_translator:uav_byteenable
+	wire         pio_led_s1_agent_m0_read;                                                    // pio_LED_s1_agent:m0_read -> pio_LED_s1_translator:uav_read
+	wire         pio_led_s1_agent_m0_readdatavalid;                                           // pio_LED_s1_translator:uav_readdatavalid -> pio_LED_s1_agent:m0_readdatavalid
+	wire         pio_led_s1_agent_m0_lock;                                                    // pio_LED_s1_agent:m0_lock -> pio_LED_s1_translator:uav_lock
+	wire  [31:0] pio_led_s1_agent_m0_writedata;                                               // pio_LED_s1_agent:m0_writedata -> pio_LED_s1_translator:uav_writedata
+	wire         pio_led_s1_agent_m0_write;                                                   // pio_LED_s1_agent:m0_write -> pio_LED_s1_translator:uav_write
+	wire   [2:0] pio_led_s1_agent_m0_burstcount;                                              // pio_LED_s1_agent:m0_burstcount -> pio_LED_s1_translator:uav_burstcount
+	wire         pio_led_s1_agent_rf_source_valid;                                            // pio_LED_s1_agent:rf_source_valid -> pio_LED_s1_agent_rsp_fifo:in_valid
+	wire  [94:0] pio_led_s1_agent_rf_source_data;                                             // pio_LED_s1_agent:rf_source_data -> pio_LED_s1_agent_rsp_fifo:in_data
+	wire         pio_led_s1_agent_rf_source_ready;                                            // pio_LED_s1_agent_rsp_fifo:in_ready -> pio_LED_s1_agent:rf_source_ready
+	wire         pio_led_s1_agent_rf_source_startofpacket;                                    // pio_LED_s1_agent:rf_source_startofpacket -> pio_LED_s1_agent_rsp_fifo:in_startofpacket
+	wire         pio_led_s1_agent_rf_source_endofpacket;                                      // pio_LED_s1_agent:rf_source_endofpacket -> pio_LED_s1_agent_rsp_fifo:in_endofpacket
+	wire         pio_led_s1_agent_rsp_fifo_out_valid;                                         // pio_LED_s1_agent_rsp_fifo:out_valid -> pio_LED_s1_agent:rf_sink_valid
+	wire  [94:0] pio_led_s1_agent_rsp_fifo_out_data;                                          // pio_LED_s1_agent_rsp_fifo:out_data -> pio_LED_s1_agent:rf_sink_data
+	wire         pio_led_s1_agent_rsp_fifo_out_ready;                                         // pio_LED_s1_agent:rf_sink_ready -> pio_LED_s1_agent_rsp_fifo:out_ready
+	wire         pio_led_s1_agent_rsp_fifo_out_startofpacket;                                 // pio_LED_s1_agent_rsp_fifo:out_startofpacket -> pio_LED_s1_agent:rf_sink_startofpacket
+	wire         pio_led_s1_agent_rsp_fifo_out_endofpacket;                                   // pio_LED_s1_agent_rsp_fifo:out_endofpacket -> pio_LED_s1_agent:rf_sink_endofpacket
+	wire         cmd_mux_003_src_valid;                                                       // cmd_mux_003:src_valid -> pio_LED_s1_agent:cp_valid
+	wire  [93:0] cmd_mux_003_src_data;                                                        // cmd_mux_003:src_data -> pio_LED_s1_agent:cp_data
+	wire         cmd_mux_003_src_ready;                                                       // pio_LED_s1_agent:cp_ready -> cmd_mux_003:src_ready
+	wire   [3:0] cmd_mux_003_src_channel;                                                     // cmd_mux_003:src_channel -> pio_LED_s1_agent:cp_channel
+	wire         cmd_mux_003_src_startofpacket;                                               // cmd_mux_003:src_startofpacket -> pio_LED_s1_agent:cp_startofpacket
+	wire         cmd_mux_003_src_endofpacket;                                                 // cmd_mux_003:src_endofpacket -> pio_LED_s1_agent:cp_endofpacket
+	wire         nios2_data_master_agent_cp_valid;                                            // nios2_data_master_agent:cp_valid -> router:sink_valid
+	wire  [93:0] nios2_data_master_agent_cp_data;                                             // nios2_data_master_agent:cp_data -> router:sink_data
+	wire         nios2_data_master_agent_cp_ready;                                            // router:sink_ready -> nios2_data_master_agent:cp_ready
+	wire         nios2_data_master_agent_cp_startofpacket;                                    // nios2_data_master_agent:cp_startofpacket -> router:sink_startofpacket
+	wire         nios2_data_master_agent_cp_endofpacket;                                      // nios2_data_master_agent:cp_endofpacket -> router:sink_endofpacket
+	wire         router_src_valid;                                                            // router:src_valid -> cmd_demux:sink_valid
+	wire  [93:0] router_src_data;                                                             // router:src_data -> cmd_demux:sink_data
+	wire         router_src_ready;                                                            // cmd_demux:sink_ready -> router:src_ready
+	wire   [3:0] router_src_channel;                                                          // router:src_channel -> cmd_demux:sink_channel
+	wire         router_src_startofpacket;                                                    // router:src_startofpacket -> cmd_demux:sink_startofpacket
+	wire         router_src_endofpacket;                                                      // router:src_endofpacket -> cmd_demux:sink_endofpacket
+	wire         nios2_instruction_master_agent_cp_valid;                                     // nios2_instruction_master_agent:cp_valid -> router_001:sink_valid
+	wire  [93:0] nios2_instruction_master_agent_cp_data;                                      // nios2_instruction_master_agent:cp_data -> router_001:sink_data
+	wire         nios2_instruction_master_agent_cp_ready;                                     // router_001:sink_ready -> nios2_instruction_master_agent:cp_ready
+	wire         nios2_instruction_master_agent_cp_startofpacket;                             // nios2_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
+	wire         nios2_instruction_master_agent_cp_endofpacket;                               // nios2_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
+	wire         router_001_src_valid;                                                        // router_001:src_valid -> cmd_demux_001:sink_valid
+	wire  [93:0] router_001_src_data;                                                         // router_001:src_data -> cmd_demux_001:sink_data
+	wire         router_001_src_ready;                                                        // cmd_demux_001:sink_ready -> router_001:src_ready
+	wire   [3:0] router_001_src_channel;                                                      // router_001:src_channel -> cmd_demux_001:sink_channel
+	wire         router_001_src_startofpacket;                                                // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
+	wire         router_001_src_endofpacket;                                                  // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
+	wire         jtag_uart_avalon_jtag_slave_agent_rp_valid;                                  // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
+	wire  [93:0] jtag_uart_avalon_jtag_slave_agent_rp_data;                                   // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
+	wire         jtag_uart_avalon_jtag_slave_agent_rp_ready;                                  // router_002:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
+	wire         jtag_uart_avalon_jtag_slave_agent_rp_startofpacket;                          // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
+	wire         jtag_uart_avalon_jtag_slave_agent_rp_endofpacket;                            // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
+	wire         router_002_src_valid;                                                        // router_002:src_valid -> rsp_demux:sink_valid
+	wire  [93:0] router_002_src_data;                                                         // router_002:src_data -> rsp_demux:sink_data
+	wire         router_002_src_ready;                                                        // rsp_demux:sink_ready -> router_002:src_ready
+	wire   [3:0] router_002_src_channel;                                                      // router_002:src_channel -> rsp_demux:sink_channel
+	wire         router_002_src_startofpacket;                                                // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
+	wire         router_002_src_endofpacket;                                                  // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
+	wire         nios2_debug_mem_slave_agent_rp_valid;                                        // nios2_debug_mem_slave_agent:rp_valid -> router_003:sink_valid
+	wire  [93:0] nios2_debug_mem_slave_agent_rp_data;                                         // nios2_debug_mem_slave_agent:rp_data -> router_003:sink_data
+	wire         nios2_debug_mem_slave_agent_rp_ready;                                        // router_003:sink_ready -> nios2_debug_mem_slave_agent:rp_ready
+	wire         nios2_debug_mem_slave_agent_rp_startofpacket;                                // nios2_debug_mem_slave_agent:rp_startofpacket -> router_003:sink_startofpacket
+	wire         nios2_debug_mem_slave_agent_rp_endofpacket;                                  // nios2_debug_mem_slave_agent:rp_endofpacket -> router_003:sink_endofpacket
+	wire         router_003_src_valid;                                                        // router_003:src_valid -> rsp_demux_001:sink_valid
+	wire  [93:0] router_003_src_data;                                                         // router_003:src_data -> rsp_demux_001:sink_data
+	wire         router_003_src_ready;                                                        // rsp_demux_001:sink_ready -> router_003:src_ready
+	wire   [3:0] router_003_src_channel;                                                      // router_003:src_channel -> rsp_demux_001:sink_channel
+	wire         router_003_src_startofpacket;                                                // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
+	wire         router_003_src_endofpacket;                                                  // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
+	wire         onchip_memory2_s1_agent_rp_valid;                                            // onchip_memory2_s1_agent:rp_valid -> router_004:sink_valid
+	wire  [93:0] onchip_memory2_s1_agent_rp_data;                                             // onchip_memory2_s1_agent:rp_data -> router_004:sink_data
+	wire         onchip_memory2_s1_agent_rp_ready;                                            // router_004:sink_ready -> onchip_memory2_s1_agent:rp_ready
+	wire         onchip_memory2_s1_agent_rp_startofpacket;                                    // onchip_memory2_s1_agent:rp_startofpacket -> router_004:sink_startofpacket
+	wire         onchip_memory2_s1_agent_rp_endofpacket;                                      // onchip_memory2_s1_agent:rp_endofpacket -> router_004:sink_endofpacket
+	wire         router_004_src_valid;                                                        // router_004:src_valid -> rsp_demux_002:sink_valid
+	wire  [93:0] router_004_src_data;                                                         // router_004:src_data -> rsp_demux_002:sink_data
+	wire         router_004_src_ready;                                                        // rsp_demux_002:sink_ready -> router_004:src_ready
+	wire   [3:0] router_004_src_channel;                                                      // router_004:src_channel -> rsp_demux_002:sink_channel
+	wire         router_004_src_startofpacket;                                                // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
+	wire         router_004_src_endofpacket;                                                  // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
+	wire         pio_led_s1_agent_rp_valid;                                                   // pio_LED_s1_agent:rp_valid -> router_005:sink_valid
+	wire  [93:0] pio_led_s1_agent_rp_data;                                                    // pio_LED_s1_agent:rp_data -> router_005:sink_data
+	wire         pio_led_s1_agent_rp_ready;                                                   // router_005:sink_ready -> pio_LED_s1_agent:rp_ready
+	wire         pio_led_s1_agent_rp_startofpacket;                                           // pio_LED_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
+	wire         pio_led_s1_agent_rp_endofpacket;                                             // pio_LED_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
+	wire         router_005_src_valid;                                                        // router_005:src_valid -> rsp_demux_003:sink_valid
+	wire  [93:0] router_005_src_data;                                                         // router_005:src_data -> rsp_demux_003:sink_data
+	wire         router_005_src_ready;                                                        // rsp_demux_003:sink_ready -> router_005:src_ready
+	wire   [3:0] router_005_src_channel;                                                      // router_005:src_channel -> rsp_demux_003:sink_channel
+	wire         router_005_src_startofpacket;                                                // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
+	wire         router_005_src_endofpacket;                                                  // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
+	wire         cmd_demux_src0_valid;                                                        // cmd_demux:src0_valid -> cmd_mux:sink0_valid
+	wire  [93:0] cmd_demux_src0_data;                                                         // cmd_demux:src0_data -> cmd_mux:sink0_data
+	wire         cmd_demux_src0_ready;                                                        // cmd_mux:sink0_ready -> cmd_demux:src0_ready
+	wire   [3:0] cmd_demux_src0_channel;                                                      // cmd_demux:src0_channel -> cmd_mux:sink0_channel
+	wire         cmd_demux_src0_startofpacket;                                                // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
+	wire         cmd_demux_src0_endofpacket;                                                  // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
+	wire         cmd_demux_src1_valid;                                                        // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
+	wire  [93:0] cmd_demux_src1_data;                                                         // cmd_demux:src1_data -> cmd_mux_001:sink0_data
+	wire         cmd_demux_src1_ready;                                                        // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
+	wire   [3:0] cmd_demux_src1_channel;                                                      // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
+	wire         cmd_demux_src1_startofpacket;                                                // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
+	wire         cmd_demux_src1_endofpacket;                                                  // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
+	wire         cmd_demux_src2_valid;                                                        // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
+	wire  [93:0] cmd_demux_src2_data;                                                         // cmd_demux:src2_data -> cmd_mux_002:sink0_data
+	wire         cmd_demux_src2_ready;                                                        // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
+	wire   [3:0] cmd_demux_src2_channel;                                                      // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
+	wire         cmd_demux_src2_startofpacket;                                                // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
+	wire         cmd_demux_src2_endofpacket;                                                  // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
+	wire         cmd_demux_src3_valid;                                                        // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
+	wire  [93:0] cmd_demux_src3_data;                                                         // cmd_demux:src3_data -> cmd_mux_003:sink0_data
+	wire         cmd_demux_src3_ready;                                                        // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
+	wire   [3:0] cmd_demux_src3_channel;                                                      // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
+	wire         cmd_demux_src3_startofpacket;                                                // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
+	wire         cmd_demux_src3_endofpacket;                                                  // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
+	wire         cmd_demux_001_src0_valid;                                                    // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
+	wire  [93:0] cmd_demux_001_src0_data;                                                     // cmd_demux_001:src0_data -> cmd_mux:sink1_data
+	wire         cmd_demux_001_src0_ready;                                                    // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
+	wire   [3:0] cmd_demux_001_src0_channel;                                                  // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
+	wire         cmd_demux_001_src0_startofpacket;                                            // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
+	wire         cmd_demux_001_src0_endofpacket;                                              // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
+	wire         cmd_demux_001_src1_valid;                                                    // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
+	wire  [93:0] cmd_demux_001_src1_data;                                                     // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
+	wire         cmd_demux_001_src1_ready;                                                    // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
+	wire   [3:0] cmd_demux_001_src1_channel;                                                  // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
+	wire         cmd_demux_001_src1_startofpacket;                                            // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
+	wire         cmd_demux_001_src1_endofpacket;                                              // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
+	wire         cmd_demux_001_src2_valid;                                                    // cmd_demux_001:src2_valid -> cmd_mux_002:sink1_valid
+	wire  [93:0] cmd_demux_001_src2_data;                                                     // cmd_demux_001:src2_data -> cmd_mux_002:sink1_data
+	wire         cmd_demux_001_src2_ready;                                                    // cmd_mux_002:sink1_ready -> cmd_demux_001:src2_ready
+	wire   [3:0] cmd_demux_001_src2_channel;                                                  // cmd_demux_001:src2_channel -> cmd_mux_002:sink1_channel
+	wire         cmd_demux_001_src2_startofpacket;                                            // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
+	wire         cmd_demux_001_src2_endofpacket;                                              // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
+	wire         cmd_demux_001_src3_valid;                                                    // cmd_demux_001:src3_valid -> cmd_mux_003:sink1_valid
+	wire  [93:0] cmd_demux_001_src3_data;                                                     // cmd_demux_001:src3_data -> cmd_mux_003:sink1_data
+	wire         cmd_demux_001_src3_ready;                                                    // cmd_mux_003:sink1_ready -> cmd_demux_001:src3_ready
+	wire   [3:0] cmd_demux_001_src3_channel;                                                  // cmd_demux_001:src3_channel -> cmd_mux_003:sink1_channel
+	wire         cmd_demux_001_src3_startofpacket;                                            // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink1_startofpacket
+	wire         cmd_demux_001_src3_endofpacket;                                              // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink1_endofpacket
+	wire         rsp_demux_src0_valid;                                                        // rsp_demux:src0_valid -> rsp_mux:sink0_valid
+	wire  [93:0] rsp_demux_src0_data;                                                         // rsp_demux:src0_data -> rsp_mux:sink0_data
+	wire         rsp_demux_src0_ready;                                                        // rsp_mux:sink0_ready -> rsp_demux:src0_ready
+	wire   [3:0] rsp_demux_src0_channel;                                                      // rsp_demux:src0_channel -> rsp_mux:sink0_channel
+	wire         rsp_demux_src0_startofpacket;                                                // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
+	wire         rsp_demux_src0_endofpacket;                                                  // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
+	wire         rsp_demux_src1_valid;                                                        // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
+	wire  [93:0] rsp_demux_src1_data;                                                         // rsp_demux:src1_data -> rsp_mux_001:sink0_data
+	wire         rsp_demux_src1_ready;                                                        // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
+	wire   [3:0] rsp_demux_src1_channel;                                                      // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
+	wire         rsp_demux_src1_startofpacket;                                                // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
+	wire         rsp_demux_src1_endofpacket;                                                  // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
+	wire         rsp_demux_001_src0_valid;                                                    // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
+	wire  [93:0] rsp_demux_001_src0_data;                                                     // rsp_demux_001:src0_data -> rsp_mux:sink1_data
+	wire         rsp_demux_001_src0_ready;                                                    // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
+	wire   [3:0] rsp_demux_001_src0_channel;                                                  // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
+	wire         rsp_demux_001_src0_startofpacket;                                            // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
+	wire         rsp_demux_001_src0_endofpacket;                                              // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
+	wire         rsp_demux_001_src1_valid;                                                    // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
+	wire  [93:0] rsp_demux_001_src1_data;                                                     // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
+	wire         rsp_demux_001_src1_ready;                                                    // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
+	wire   [3:0] rsp_demux_001_src1_channel;                                                  // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
+	wire         rsp_demux_001_src1_startofpacket;                                            // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
+	wire         rsp_demux_001_src1_endofpacket;                                              // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
+	wire         rsp_demux_002_src0_valid;                                                    // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
+	wire  [93:0] rsp_demux_002_src0_data;                                                     // rsp_demux_002:src0_data -> rsp_mux:sink2_data
+	wire         rsp_demux_002_src0_ready;                                                    // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
+	wire   [3:0] rsp_demux_002_src0_channel;                                                  // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
+	wire         rsp_demux_002_src0_startofpacket;                                            // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
+	wire         rsp_demux_002_src0_endofpacket;                                              // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
+	wire         rsp_demux_002_src1_valid;                                                    // rsp_demux_002:src1_valid -> rsp_mux_001:sink2_valid
+	wire  [93:0] rsp_demux_002_src1_data;                                                     // rsp_demux_002:src1_data -> rsp_mux_001:sink2_data
+	wire         rsp_demux_002_src1_ready;                                                    // rsp_mux_001:sink2_ready -> rsp_demux_002:src1_ready
+	wire   [3:0] rsp_demux_002_src1_channel;                                                  // rsp_demux_002:src1_channel -> rsp_mux_001:sink2_channel
+	wire         rsp_demux_002_src1_startofpacket;                                            // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
+	wire         rsp_demux_002_src1_endofpacket;                                              // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
+	wire         rsp_demux_003_src0_valid;                                                    // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
+	wire  [93:0] rsp_demux_003_src0_data;                                                     // rsp_demux_003:src0_data -> rsp_mux:sink3_data
+	wire         rsp_demux_003_src0_ready;                                                    // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
+	wire   [3:0] rsp_demux_003_src0_channel;                                                  // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
+	wire         rsp_demux_003_src0_startofpacket;                                            // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
+	wire         rsp_demux_003_src0_endofpacket;                                              // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
+	wire         rsp_demux_003_src1_valid;                                                    // rsp_demux_003:src1_valid -> rsp_mux_001:sink3_valid
+	wire  [93:0] rsp_demux_003_src1_data;                                                     // rsp_demux_003:src1_data -> rsp_mux_001:sink3_data
+	wire         rsp_demux_003_src1_ready;                                                    // rsp_mux_001:sink3_ready -> rsp_demux_003:src1_ready
+	wire   [3:0] rsp_demux_003_src1_channel;                                                  // rsp_demux_003:src1_channel -> rsp_mux_001:sink3_channel
+	wire         rsp_demux_003_src1_startofpacket;                                            // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink3_startofpacket
+	wire         rsp_demux_003_src1_endofpacket;                                              // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink3_endofpacket
+	wire         jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid;                      // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
+	wire  [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data;                       // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
+	wire         jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready;                      // avalon_st_adapter:in_0_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
+	wire         avalon_st_adapter_out_0_valid;                                               // avalon_st_adapter:out_0_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
+	wire  [33:0] avalon_st_adapter_out_0_data;                                                // avalon_st_adapter:out_0_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
+	wire         avalon_st_adapter_out_0_ready;                                               // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
+	wire   [0:0] avalon_st_adapter_out_0_error;                                               // avalon_st_adapter:out_0_error -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_error
+	wire         nios2_debug_mem_slave_agent_rdata_fifo_src_valid;                            // nios2_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
+	wire  [33:0] nios2_debug_mem_slave_agent_rdata_fifo_src_data;                             // nios2_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
+	wire         nios2_debug_mem_slave_agent_rdata_fifo_src_ready;                            // avalon_st_adapter_001:in_0_ready -> nios2_debug_mem_slave_agent:rdata_fifo_src_ready
+	wire         avalon_st_adapter_001_out_0_valid;                                           // avalon_st_adapter_001:out_0_valid -> nios2_debug_mem_slave_agent:rdata_fifo_sink_valid
+	wire  [33:0] avalon_st_adapter_001_out_0_data;                                            // avalon_st_adapter_001:out_0_data -> nios2_debug_mem_slave_agent:rdata_fifo_sink_data
+	wire         avalon_st_adapter_001_out_0_ready;                                           // nios2_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
+	wire   [0:0] avalon_st_adapter_001_out_0_error;                                           // avalon_st_adapter_001:out_0_error -> nios2_debug_mem_slave_agent:rdata_fifo_sink_error
+	wire         onchip_memory2_s1_agent_rdata_fifo_src_valid;                                // onchip_memory2_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
+	wire  [33:0] onchip_memory2_s1_agent_rdata_fifo_src_data;                                 // onchip_memory2_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
+	wire         onchip_memory2_s1_agent_rdata_fifo_src_ready;                                // avalon_st_adapter_002:in_0_ready -> onchip_memory2_s1_agent:rdata_fifo_src_ready
+	wire         avalon_st_adapter_002_out_0_valid;                                           // avalon_st_adapter_002:out_0_valid -> onchip_memory2_s1_agent:rdata_fifo_sink_valid
+	wire  [33:0] avalon_st_adapter_002_out_0_data;                                            // avalon_st_adapter_002:out_0_data -> onchip_memory2_s1_agent:rdata_fifo_sink_data
+	wire         avalon_st_adapter_002_out_0_ready;                                           // onchip_memory2_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
+	wire   [0:0] avalon_st_adapter_002_out_0_error;                                           // avalon_st_adapter_002:out_0_error -> onchip_memory2_s1_agent:rdata_fifo_sink_error
+	wire         pio_led_s1_agent_rdata_fifo_src_valid;                                       // pio_LED_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
+	wire  [33:0] pio_led_s1_agent_rdata_fifo_src_data;                                        // pio_LED_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
+	wire         pio_led_s1_agent_rdata_fifo_src_ready;                                       // avalon_st_adapter_003:in_0_ready -> pio_LED_s1_agent:rdata_fifo_src_ready
+	wire         avalon_st_adapter_003_out_0_valid;                                           // avalon_st_adapter_003:out_0_valid -> pio_LED_s1_agent:rdata_fifo_sink_valid
+	wire  [33:0] avalon_st_adapter_003_out_0_data;                                            // avalon_st_adapter_003:out_0_data -> pio_LED_s1_agent:rdata_fifo_sink_data
+	wire         avalon_st_adapter_003_out_0_ready;                                           // pio_LED_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
+	wire   [0:0] avalon_st_adapter_003_out_0_error;                                           // avalon_st_adapter_003:out_0_error -> pio_LED_s1_agent:rdata_fifo_sink_error
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (20),
+		.AV_DATA_W                   (32),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (4),
+		.UAV_ADDRESS_W               (20),
+		.UAV_BURSTCOUNT_W            (3),
+		.USE_READ                    (1),
+		.USE_WRITE                   (1),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (0),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (0),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (0),
+		.USE_WRITERESPONSE           (0),
+		.AV_SYMBOLS_PER_WORD         (4),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (0),
+		.AV_REGISTERINCOMINGSIGNALS  (1)
+	) nios2_data_master_translator (
+		.clk                    (clk_50_clk_clk),                                                       //                       clk.clk
+		.reset                  (nios2_reset_reset_bridge_in_reset_reset),                              //                     reset.reset
+		.uav_address            (nios2_data_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
+		.uav_burstcount         (nios2_data_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
+		.uav_read               (nios2_data_master_translator_avalon_universal_master_0_read),          //                          .read
+		.uav_write              (nios2_data_master_translator_avalon_universal_master_0_write),         //                          .write
+		.uav_waitrequest        (nios2_data_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
+		.uav_readdatavalid      (nios2_data_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
+		.uav_byteenable         (nios2_data_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
+		.uav_readdata           (nios2_data_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
+		.uav_writedata          (nios2_data_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
+		.uav_lock               (nios2_data_master_translator_avalon_universal_master_0_lock),          //                          .lock
+		.uav_debugaccess        (nios2_data_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
+		.av_address             (nios2_data_master_address),                                            //      avalon_anti_master_0.address
+		.av_waitrequest         (nios2_data_master_waitrequest),                                        //                          .waitrequest
+		.av_byteenable          (nios2_data_master_byteenable),                                         //                          .byteenable
+		.av_read                (nios2_data_master_read),                                               //                          .read
+		.av_readdata            (nios2_data_master_readdata),                                           //                          .readdata
+		.av_write               (nios2_data_master_write),                                              //                          .write
+		.av_writedata           (nios2_data_master_writedata),                                          //                          .writedata
+		.av_debugaccess         (nios2_data_master_debugaccess),                                        //                          .debugaccess
+		.av_burstcount          (1'b1),                                                                 //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                 //               (terminated)
+		.av_begintransfer       (1'b0),                                                                 //               (terminated)
+		.av_chipselect          (1'b0),                                                                 //               (terminated)
+		.av_readdatavalid       (),                                                                     //               (terminated)
+		.av_lock                (1'b0),                                                                 //               (terminated)
+		.uav_clken              (),                                                                     //               (terminated)
+		.av_clken               (1'b1),                                                                 //               (terminated)
+		.uav_response           (2'b00),                                                                //               (terminated)
+		.av_response            (),                                                                     //               (terminated)
+		.uav_writeresponsevalid (1'b0),                                                                 //               (terminated)
+		.av_writeresponsevalid  ()                                                                      //               (terminated)
+	);
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (20),
+		.AV_DATA_W                   (32),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (4),
+		.UAV_ADDRESS_W               (20),
+		.UAV_BURSTCOUNT_W            (3),
+		.USE_READ                    (1),
+		.USE_WRITE                   (0),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (0),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (0),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (0),
+		.USE_WRITERESPONSE           (0),
+		.AV_SYMBOLS_PER_WORD         (4),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (1),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) nios2_instruction_master_translator (
+		.clk                    (clk_50_clk_clk),                                                              //                       clk.clk
+		.reset                  (nios2_reset_reset_bridge_in_reset_reset),                                     //                     reset.reset
+		.uav_address            (nios2_instruction_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
+		.uav_burstcount         (nios2_instruction_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
+		.uav_read               (nios2_instruction_master_translator_avalon_universal_master_0_read),          //                          .read
+		.uav_write              (nios2_instruction_master_translator_avalon_universal_master_0_write),         //                          .write
+		.uav_waitrequest        (nios2_instruction_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
+		.uav_readdatavalid      (nios2_instruction_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
+		.uav_byteenable         (nios2_instruction_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
+		.uav_readdata           (nios2_instruction_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
+		.uav_writedata          (nios2_instruction_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
+		.uav_lock               (nios2_instruction_master_translator_avalon_universal_master_0_lock),          //                          .lock
+		.uav_debugaccess        (nios2_instruction_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
+		.av_address             (nios2_instruction_master_address),                                            //      avalon_anti_master_0.address
+		.av_waitrequest         (nios2_instruction_master_waitrequest),                                        //                          .waitrequest
+		.av_read                (nios2_instruction_master_read),                                               //                          .read
+		.av_readdata            (nios2_instruction_master_readdata),                                           //                          .readdata
+		.av_burstcount          (1'b1),                                                                        //               (terminated)
+		.av_byteenable          (4'b1111),                                                                     //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                        //               (terminated)
+		.av_begintransfer       (1'b0),                                                                        //               (terminated)
+		.av_chipselect          (1'b0),                                                                        //               (terminated)
+		.av_readdatavalid       (),                                                                            //               (terminated)
+		.av_write               (1'b0),                                                                        //               (terminated)
+		.av_writedata           (32'b00000000000000000000000000000000),                                        //               (terminated)
+		.av_lock                (1'b0),                                                                        //               (terminated)
+		.av_debugaccess         (1'b0),                                                                        //               (terminated)
+		.uav_clken              (),                                                                            //               (terminated)
+		.av_clken               (1'b1),                                                                        //               (terminated)
+		.uav_response           (2'b00),                                                                       //               (terminated)
+		.av_response            (),                                                                            //               (terminated)
+		.uav_writeresponsevalid (1'b0),                                                                        //               (terminated)
+		.av_writeresponsevalid  ()                                                                             //               (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (1),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (1),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (20),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) jtag_uart_avalon_jtag_slave_translator (
+		.clk                    (clk_50_clk_clk),                                     //                      clk.clk
+		.reset                  (nios2_reset_reset_bridge_in_reset_reset),            //                    reset.reset
+		.uav_address            (jtag_uart_avalon_jtag_slave_agent_m0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (jtag_uart_avalon_jtag_slave_agent_m0_burstcount),    //                         .burstcount
+		.uav_read               (jtag_uart_avalon_jtag_slave_agent_m0_read),          //                         .read
+		.uav_write              (jtag_uart_avalon_jtag_slave_agent_m0_write),         //                         .write
+		.uav_waitrequest        (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (jtag_uart_avalon_jtag_slave_agent_m0_byteenable),    //                         .byteenable
+		.uav_readdata           (jtag_uart_avalon_jtag_slave_agent_m0_readdata),      //                         .readdata
+		.uav_writedata          (jtag_uart_avalon_jtag_slave_agent_m0_writedata),     //                         .writedata
+		.uav_lock               (jtag_uart_avalon_jtag_slave_agent_m0_lock),          //                         .lock
+		.uav_debugaccess        (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess),   //                         .debugaccess
+		.av_address             (jtag_uart_avalon_jtag_slave_address),                //      avalon_anti_slave_0.address
+		.av_write               (jtag_uart_avalon_jtag_slave_write),                  //                         .write
+		.av_read                (jtag_uart_avalon_jtag_slave_read),                   //                         .read
+		.av_readdata            (jtag_uart_avalon_jtag_slave_readdata),               //                         .readdata
+		.av_writedata           (jtag_uart_avalon_jtag_slave_writedata),              //                         .writedata
+		.av_waitrequest         (jtag_uart_avalon_jtag_slave_waitrequest),            //                         .waitrequest
+		.av_chipselect          (jtag_uart_avalon_jtag_slave_chipselect),             //                         .chipselect
+		.av_begintransfer       (),                                                   //              (terminated)
+		.av_beginbursttransfer  (),                                                   //              (terminated)
+		.av_burstcount          (),                                                   //              (terminated)
+		.av_byteenable          (),                                                   //              (terminated)
+		.av_readdatavalid       (1'b0),                                               //              (terminated)
+		.av_writebyteenable     (),                                                   //              (terminated)
+		.av_lock                (),                                                   //              (terminated)
+		.av_clken               (),                                                   //              (terminated)
+		.uav_clken              (1'b0),                                               //              (terminated)
+		.av_debugaccess         (),                                                   //              (terminated)
+		.av_outputenable        (),                                                   //              (terminated)
+		.uav_response           (),                                                   //              (terminated)
+		.av_response            (2'b00),                                              //              (terminated)
+		.uav_writeresponsevalid (),                                                   //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                                //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (9),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (20),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) nios2_debug_mem_slave_translator (
+		.clk                    (clk_50_clk_clk),                               //                      clk.clk
+		.reset                  (nios2_reset_reset_bridge_in_reset_reset),      //                    reset.reset
+		.uav_address            (nios2_debug_mem_slave_agent_m0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (nios2_debug_mem_slave_agent_m0_burstcount),    //                         .burstcount
+		.uav_read               (nios2_debug_mem_slave_agent_m0_read),          //                         .read
+		.uav_write              (nios2_debug_mem_slave_agent_m0_write),         //                         .write
+		.uav_waitrequest        (nios2_debug_mem_slave_agent_m0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (nios2_debug_mem_slave_agent_m0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (nios2_debug_mem_slave_agent_m0_byteenable),    //                         .byteenable
+		.uav_readdata           (nios2_debug_mem_slave_agent_m0_readdata),      //                         .readdata
+		.uav_writedata          (nios2_debug_mem_slave_agent_m0_writedata),     //                         .writedata
+		.uav_lock               (nios2_debug_mem_slave_agent_m0_lock),          //                         .lock
+		.uav_debugaccess        (nios2_debug_mem_slave_agent_m0_debugaccess),   //                         .debugaccess
+		.av_address             (nios2_debug_mem_slave_address),                //      avalon_anti_slave_0.address
+		.av_write               (nios2_debug_mem_slave_write),                  //                         .write
+		.av_read                (nios2_debug_mem_slave_read),                   //                         .read
+		.av_readdata            (nios2_debug_mem_slave_readdata),               //                         .readdata
+		.av_writedata           (nios2_debug_mem_slave_writedata),              //                         .writedata
+		.av_byteenable          (nios2_debug_mem_slave_byteenable),             //                         .byteenable
+		.av_waitrequest         (nios2_debug_mem_slave_waitrequest),            //                         .waitrequest
+		.av_debugaccess         (nios2_debug_mem_slave_debugaccess),            //                         .debugaccess
+		.av_begintransfer       (),                                             //              (terminated)
+		.av_beginbursttransfer  (),                                             //              (terminated)
+		.av_burstcount          (),                                             //              (terminated)
+		.av_readdatavalid       (1'b0),                                         //              (terminated)
+		.av_writebyteenable     (),                                             //              (terminated)
+		.av_lock                (),                                             //              (terminated)
+		.av_chipselect          (),                                             //              (terminated)
+		.av_clken               (),                                             //              (terminated)
+		.uav_clken              (1'b0),                                         //              (terminated)
+		.av_outputenable        (),                                             //              (terminated)
+		.uav_response           (),                                             //              (terminated)
+		.av_response            (2'b00),                                        //              (terminated)
+		.uav_writeresponsevalid (),                                             //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                          //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (16),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (20),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (1),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (0),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) onchip_memory2_s1_translator (
+		.clk                    (clk_50_clk_clk),                           //                      clk.clk
+		.reset                  (nios2_reset_reset_bridge_in_reset_reset),  //                    reset.reset
+		.uav_address            (onchip_memory2_s1_agent_m0_address),       // avalon_universal_slave_0.address
+		.uav_burstcount         (onchip_memory2_s1_agent_m0_burstcount),    //                         .burstcount
+		.uav_read               (onchip_memory2_s1_agent_m0_read),          //                         .read
+		.uav_write              (onchip_memory2_s1_agent_m0_write),         //                         .write
+		.uav_waitrequest        (onchip_memory2_s1_agent_m0_waitrequest),   //                         .waitrequest
+		.uav_readdatavalid      (onchip_memory2_s1_agent_m0_readdatavalid), //                         .readdatavalid
+		.uav_byteenable         (onchip_memory2_s1_agent_m0_byteenable),    //                         .byteenable
+		.uav_readdata           (onchip_memory2_s1_agent_m0_readdata),      //                         .readdata
+		.uav_writedata          (onchip_memory2_s1_agent_m0_writedata),     //                         .writedata
+		.uav_lock               (onchip_memory2_s1_agent_m0_lock),          //                         .lock
+		.uav_debugaccess        (onchip_memory2_s1_agent_m0_debugaccess),   //                         .debugaccess
+		.av_address             (onchip_memory2_s1_address),                //      avalon_anti_slave_0.address
+		.av_write               (onchip_memory2_s1_write),                  //                         .write
+		.av_readdata            (onchip_memory2_s1_readdata),               //                         .readdata
+		.av_writedata           (onchip_memory2_s1_writedata),              //                         .writedata
+		.av_byteenable          (onchip_memory2_s1_byteenable),             //                         .byteenable
+		.av_chipselect          (onchip_memory2_s1_chipselect),             //                         .chipselect
+		.av_clken               (onchip_memory2_s1_clken),                  //                         .clken
+		.av_read                (),                                         //              (terminated)
+		.av_begintransfer       (),                                         //              (terminated)
+		.av_beginbursttransfer  (),                                         //              (terminated)
+		.av_burstcount          (),                                         //              (terminated)
+		.av_readdatavalid       (1'b0),                                     //              (terminated)
+		.av_waitrequest         (1'b0),                                     //              (terminated)
+		.av_writebyteenable     (),                                         //              (terminated)
+		.av_lock                (),                                         //              (terminated)
+		.uav_clken              (1'b0),                                     //              (terminated)
+		.av_debugaccess         (),                                         //              (terminated)
+		.av_outputenable        (),                                         //              (terminated)
+		.uav_response           (),                                         //              (terminated)
+		.av_response            (2'b00),                                    //              (terminated)
+		.uav_writeresponsevalid (),                                         //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                      //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (2),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (1),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (20),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) pio_led_s1_translator (
+		.clk                    (clk_50_clk_clk),                          //                      clk.clk
+		.reset                  (nios2_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (pio_led_s1_agent_m0_address),             // avalon_universal_slave_0.address
+		.uav_burstcount         (pio_led_s1_agent_m0_burstcount),          //                         .burstcount
+		.uav_read               (pio_led_s1_agent_m0_read),                //                         .read
+		.uav_write              (pio_led_s1_agent_m0_write),               //                         .write
+		.uav_waitrequest        (pio_led_s1_agent_m0_waitrequest),         //                         .waitrequest
+		.uav_readdatavalid      (pio_led_s1_agent_m0_readdatavalid),       //                         .readdatavalid
+		.uav_byteenable         (pio_led_s1_agent_m0_byteenable),          //                         .byteenable
+		.uav_readdata           (pio_led_s1_agent_m0_readdata),            //                         .readdata
+		.uav_writedata          (pio_led_s1_agent_m0_writedata),           //                         .writedata
+		.uav_lock               (pio_led_s1_agent_m0_lock),                //                         .lock
+		.uav_debugaccess        (pio_led_s1_agent_m0_debugaccess),         //                         .debugaccess
+		.av_address             (pio_LED_s1_address),                      //      avalon_anti_slave_0.address
+		.av_write               (pio_LED_s1_write),                        //                         .write
+		.av_readdata            (pio_LED_s1_readdata),                     //                         .readdata
+		.av_writedata           (pio_LED_s1_writedata),                    //                         .writedata
+		.av_chipselect          (pio_LED_s1_chipselect),                   //                         .chipselect
+		.av_read                (),                                        //              (terminated)
+		.av_begintransfer       (),                                        //              (terminated)
+		.av_beginbursttransfer  (),                                        //              (terminated)
+		.av_burstcount          (),                                        //              (terminated)
+		.av_byteenable          (),                                        //              (terminated)
+		.av_readdatavalid       (1'b0),                                    //              (terminated)
+		.av_waitrequest         (1'b0),                                    //              (terminated)
+		.av_writebyteenable     (),                                        //              (terminated)
+		.av_lock                (),                                        //              (terminated)
+		.av_clken               (),                                        //              (terminated)
+		.uav_clken              (1'b0),                                    //              (terminated)
+		.av_debugaccess         (),                                        //              (terminated)
+		.av_outputenable        (),                                        //              (terminated)
+		.uav_response           (),                                        //              (terminated)
+		.av_response            (2'b00),                                   //              (terminated)
+		.uav_writeresponsevalid (),                                        //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                     //              (terminated)
+	);
+
+	altera_merlin_master_agent #(
+		.PKT_ORI_BURST_SIZE_H      (93),
+		.PKT_ORI_BURST_SIZE_L      (91),
+		.PKT_RESPONSE_STATUS_H     (90),
+		.PKT_RESPONSE_STATUS_L     (89),
+		.PKT_QOS_H                 (76),
+		.PKT_QOS_L                 (76),
+		.PKT_DATA_SIDEBAND_H       (74),
+		.PKT_DATA_SIDEBAND_L       (74),
+		.PKT_ADDR_SIDEBAND_H       (73),
+		.PKT_ADDR_SIDEBAND_L       (73),
+		.PKT_BURST_TYPE_H          (72),
+		.PKT_BURST_TYPE_L          (71),
+		.PKT_CACHE_H               (88),
+		.PKT_CACHE_L               (85),
+		.PKT_THREAD_ID_H           (81),
+		.PKT_THREAD_ID_L           (81),
+		.PKT_BURST_SIZE_H          (70),
+		.PKT_BURST_SIZE_L          (68),
+		.PKT_TRANS_EXCLUSIVE       (61),
+		.PKT_TRANS_LOCK            (60),
+		.PKT_BEGIN_BURST           (75),
+		.PKT_PROTECTION_H          (84),
+		.PKT_PROTECTION_L          (82),
+		.PKT_BURSTWRAP_H           (67),
+		.PKT_BURSTWRAP_L           (65),
+		.PKT_BYTE_CNT_H            (64),
+		.PKT_BYTE_CNT_L            (62),
+		.PKT_ADDR_H                (55),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (56),
+		.PKT_TRANS_POSTED          (57),
+		.PKT_TRANS_WRITE           (58),
+		.PKT_TRANS_READ            (59),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (78),
+		.PKT_SRC_ID_L              (77),
+		.PKT_DEST_ID_H             (80),
+		.PKT_DEST_ID_L             (79),
+		.ST_DATA_W                 (94),
+		.ST_CHANNEL_W              (4),
+		.AV_BURSTCOUNT_W           (3),
+		.SUPPRESS_0_BYTEEN_RSP     (0),
+		.ID                        (0),
+		.BURSTWRAP_VALUE           (7),
+		.CACHE_VALUE               (0),
+		.SECURE_ACCESS_BIT         (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0)
+	) nios2_data_master_agent (
+		.clk                   (clk_50_clk_clk),                                                       //       clk.clk
+		.reset                 (nios2_reset_reset_bridge_in_reset_reset),                              // clk_reset.reset
+		.av_address            (nios2_data_master_translator_avalon_universal_master_0_address),       //        av.address
+		.av_write              (nios2_data_master_translator_avalon_universal_master_0_write),         //          .write
+		.av_read               (nios2_data_master_translator_avalon_universal_master_0_read),          //          .read
+		.av_writedata          (nios2_data_master_translator_avalon_universal_master_0_writedata),     //          .writedata
+		.av_readdata           (nios2_data_master_translator_avalon_universal_master_0_readdata),      //          .readdata
+		.av_waitrequest        (nios2_data_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
+		.av_readdatavalid      (nios2_data_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
+		.av_byteenable         (nios2_data_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
+		.av_burstcount         (nios2_data_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
+		.av_debugaccess        (nios2_data_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
+		.av_lock               (nios2_data_master_translator_avalon_universal_master_0_lock),          //          .lock
+		.cp_valid              (nios2_data_master_agent_cp_valid),                                     //        cp.valid
+		.cp_data               (nios2_data_master_agent_cp_data),                                      //          .data
+		.cp_startofpacket      (nios2_data_master_agent_cp_startofpacket),                             //          .startofpacket
+		.cp_endofpacket        (nios2_data_master_agent_cp_endofpacket),                               //          .endofpacket
+		.cp_ready              (nios2_data_master_agent_cp_ready),                                     //          .ready
+		.rp_valid              (rsp_mux_src_valid),                                                    //        rp.valid
+		.rp_data               (rsp_mux_src_data),                                                     //          .data
+		.rp_channel            (rsp_mux_src_channel),                                                  //          .channel
+		.rp_startofpacket      (rsp_mux_src_startofpacket),                                            //          .startofpacket
+		.rp_endofpacket        (rsp_mux_src_endofpacket),                                              //          .endofpacket
+		.rp_ready              (rsp_mux_src_ready),                                                    //          .ready
+		.av_response           (),                                                                     // (terminated)
+		.av_writeresponsevalid ()                                                                      // (terminated)
+	);
+
+	altera_merlin_master_agent #(
+		.PKT_ORI_BURST_SIZE_H      (93),
+		.PKT_ORI_BURST_SIZE_L      (91),
+		.PKT_RESPONSE_STATUS_H     (90),
+		.PKT_RESPONSE_STATUS_L     (89),
+		.PKT_QOS_H                 (76),
+		.PKT_QOS_L                 (76),
+		.PKT_DATA_SIDEBAND_H       (74),
+		.PKT_DATA_SIDEBAND_L       (74),
+		.PKT_ADDR_SIDEBAND_H       (73),
+		.PKT_ADDR_SIDEBAND_L       (73),
+		.PKT_BURST_TYPE_H          (72),
+		.PKT_BURST_TYPE_L          (71),
+		.PKT_CACHE_H               (88),
+		.PKT_CACHE_L               (85),
+		.PKT_THREAD_ID_H           (81),
+		.PKT_THREAD_ID_L           (81),
+		.PKT_BURST_SIZE_H          (70),
+		.PKT_BURST_SIZE_L          (68),
+		.PKT_TRANS_EXCLUSIVE       (61),
+		.PKT_TRANS_LOCK            (60),
+		.PKT_BEGIN_BURST           (75),
+		.PKT_PROTECTION_H          (84),
+		.PKT_PROTECTION_L          (82),
+		.PKT_BURSTWRAP_H           (67),
+		.PKT_BURSTWRAP_L           (65),
+		.PKT_BYTE_CNT_H            (64),
+		.PKT_BYTE_CNT_L            (62),
+		.PKT_ADDR_H                (55),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (56),
+		.PKT_TRANS_POSTED          (57),
+		.PKT_TRANS_WRITE           (58),
+		.PKT_TRANS_READ            (59),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (78),
+		.PKT_SRC_ID_L              (77),
+		.PKT_DEST_ID_H             (80),
+		.PKT_DEST_ID_L             (79),
+		.ST_DATA_W                 (94),
+		.ST_CHANNEL_W              (4),
+		.AV_BURSTCOUNT_W           (3),
+		.SUPPRESS_0_BYTEEN_RSP     (0),
+		.ID                        (1),
+		.BURSTWRAP_VALUE           (3),
+		.CACHE_VALUE               (0),
+		.SECURE_ACCESS_BIT         (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0)
+	) nios2_instruction_master_agent (
+		.clk                   (clk_50_clk_clk),                                                              //       clk.clk
+		.reset                 (nios2_reset_reset_bridge_in_reset_reset),                                     // clk_reset.reset
+		.av_address            (nios2_instruction_master_translator_avalon_universal_master_0_address),       //        av.address
+		.av_write              (nios2_instruction_master_translator_avalon_universal_master_0_write),         //          .write
+		.av_read               (nios2_instruction_master_translator_avalon_universal_master_0_read),          //          .read
+		.av_writedata          (nios2_instruction_master_translator_avalon_universal_master_0_writedata),     //          .writedata
+		.av_readdata           (nios2_instruction_master_translator_avalon_universal_master_0_readdata),      //          .readdata
+		.av_waitrequest        (nios2_instruction_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
+		.av_readdatavalid      (nios2_instruction_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
+		.av_byteenable         (nios2_instruction_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
+		.av_burstcount         (nios2_instruction_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
+		.av_debugaccess        (nios2_instruction_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
+		.av_lock               (nios2_instruction_master_translator_avalon_universal_master_0_lock),          //          .lock
+		.cp_valid              (nios2_instruction_master_agent_cp_valid),                                     //        cp.valid
+		.cp_data               (nios2_instruction_master_agent_cp_data),                                      //          .data
+		.cp_startofpacket      (nios2_instruction_master_agent_cp_startofpacket),                             //          .startofpacket
+		.cp_endofpacket        (nios2_instruction_master_agent_cp_endofpacket),                               //          .endofpacket
+		.cp_ready              (nios2_instruction_master_agent_cp_ready),                                     //          .ready
+		.rp_valid              (rsp_mux_001_src_valid),                                                       //        rp.valid
+		.rp_data               (rsp_mux_001_src_data),                                                        //          .data
+		.rp_channel            (rsp_mux_001_src_channel),                                                     //          .channel
+		.rp_startofpacket      (rsp_mux_001_src_startofpacket),                                               //          .startofpacket
+		.rp_endofpacket        (rsp_mux_001_src_endofpacket),                                                 //          .endofpacket
+		.rp_ready              (rsp_mux_001_src_ready),                                                       //          .ready
+		.av_response           (),                                                                            // (terminated)
+		.av_writeresponsevalid ()                                                                             // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (93),
+		.PKT_ORI_BURST_SIZE_L      (91),
+		.PKT_RESPONSE_STATUS_H     (90),
+		.PKT_RESPONSE_STATUS_L     (89),
+		.PKT_BURST_SIZE_H          (70),
+		.PKT_BURST_SIZE_L          (68),
+		.PKT_TRANS_LOCK            (60),
+		.PKT_BEGIN_BURST           (75),
+		.PKT_PROTECTION_H          (84),
+		.PKT_PROTECTION_L          (82),
+		.PKT_BURSTWRAP_H           (67),
+		.PKT_BURSTWRAP_L           (65),
+		.PKT_BYTE_CNT_H            (64),
+		.PKT_BYTE_CNT_L            (62),
+		.PKT_ADDR_H                (55),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (56),
+		.PKT_TRANS_POSTED          (57),
+		.PKT_TRANS_WRITE           (58),
+		.PKT_TRANS_READ            (59),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (78),
+		.PKT_SRC_ID_L              (77),
+		.PKT_DEST_ID_H             (80),
+		.PKT_DEST_ID_L             (79),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (4),
+		.ST_DATA_W                 (94),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) jtag_uart_avalon_jtag_slave_agent (
+		.clk                     (clk_50_clk_clk),                                               //             clk.clk
+		.reset                   (nios2_reset_reset_bridge_in_reset_reset),                      //       clk_reset.reset
+		.m0_address              (jtag_uart_avalon_jtag_slave_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (jtag_uart_avalon_jtag_slave_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (jtag_uart_avalon_jtag_slave_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (jtag_uart_avalon_jtag_slave_agent_m0_lock),                    //                .lock
+		.m0_readdata             (jtag_uart_avalon_jtag_slave_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (jtag_uart_avalon_jtag_slave_agent_m0_read),                    //                .read
+		.m0_waitrequest          (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (jtag_uart_avalon_jtag_slave_agent_m0_writedata),               //                .writedata
+		.m0_write                (jtag_uart_avalon_jtag_slave_agent_m0_write),                   //                .write
+		.rp_endofpacket          (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (jtag_uart_avalon_jtag_slave_agent_rp_ready),                   //                .ready
+		.rp_valid                (jtag_uart_avalon_jtag_slave_agent_rp_valid),                   //                .valid
+		.rp_data                 (jtag_uart_avalon_jtag_slave_agent_rp_data),                    //                .data
+		.rp_startofpacket        (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_src_ready),                                            //              cp.ready
+		.cp_valid                (cmd_mux_src_valid),                                            //                .valid
+		.cp_data                 (cmd_mux_src_data),                                             //                .data
+		.cp_startofpacket        (cmd_mux_src_startofpacket),                                    //                .startofpacket
+		.cp_endofpacket          (cmd_mux_src_endofpacket),                                      //                .endofpacket
+		.cp_channel              (cmd_mux_src_channel),                                          //                .channel
+		.rf_sink_ready           (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (jtag_uart_avalon_jtag_slave_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (jtag_uart_avalon_jtag_slave_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (jtag_uart_avalon_jtag_slave_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                                // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                                //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                                 //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                                //                .error
+		.rdata_fifo_src_ready    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                                        //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                          //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (95),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
+		.clk               (clk_50_clk_clk),                                               //       clk.clk
+		.reset             (nios2_reset_reset_bridge_in_reset_reset),                      // clk_reset.reset
+		.in_data           (jtag_uart_avalon_jtag_slave_agent_rf_source_data),             //        in.data
+		.in_valid          (jtag_uart_avalon_jtag_slave_agent_rf_source_valid),            //          .valid
+		.in_ready          (jtag_uart_avalon_jtag_slave_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                                        // (terminated)
+		.csr_read          (1'b0),                                                         // (terminated)
+		.csr_write         (1'b0),                                                         // (terminated)
+		.csr_readdata      (),                                                             // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated)
+		.almost_full_data  (),                                                             // (terminated)
+		.almost_empty_data (),                                                             // (terminated)
+		.in_empty          (1'b0),                                                         // (terminated)
+		.out_empty         (),                                                             // (terminated)
+		.in_error          (1'b0),                                                         // (terminated)
+		.out_error         (),                                                             // (terminated)
+		.in_channel        (1'b0),                                                         // (terminated)
+		.out_channel       ()                                                              // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (93),
+		.PKT_ORI_BURST_SIZE_L      (91),
+		.PKT_RESPONSE_STATUS_H     (90),
+		.PKT_RESPONSE_STATUS_L     (89),
+		.PKT_BURST_SIZE_H          (70),
+		.PKT_BURST_SIZE_L          (68),
+		.PKT_TRANS_LOCK            (60),
+		.PKT_BEGIN_BURST           (75),
+		.PKT_PROTECTION_H          (84),
+		.PKT_PROTECTION_L          (82),
+		.PKT_BURSTWRAP_H           (67),
+		.PKT_BURSTWRAP_L           (65),
+		.PKT_BYTE_CNT_H            (64),
+		.PKT_BYTE_CNT_L            (62),
+		.PKT_ADDR_H                (55),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (56),
+		.PKT_TRANS_POSTED          (57),
+		.PKT_TRANS_WRITE           (58),
+		.PKT_TRANS_READ            (59),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (78),
+		.PKT_SRC_ID_L              (77),
+		.PKT_DEST_ID_H             (80),
+		.PKT_DEST_ID_L             (79),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (4),
+		.ST_DATA_W                 (94),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) nios2_debug_mem_slave_agent (
+		.clk                     (clk_50_clk_clk),                                         //             clk.clk
+		.reset                   (nios2_reset_reset_bridge_in_reset_reset),                //       clk_reset.reset
+		.m0_address              (nios2_debug_mem_slave_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (nios2_debug_mem_slave_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (nios2_debug_mem_slave_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (nios2_debug_mem_slave_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (nios2_debug_mem_slave_agent_m0_lock),                    //                .lock
+		.m0_readdata             (nios2_debug_mem_slave_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (nios2_debug_mem_slave_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (nios2_debug_mem_slave_agent_m0_read),                    //                .read
+		.m0_waitrequest          (nios2_debug_mem_slave_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (nios2_debug_mem_slave_agent_m0_writedata),               //                .writedata
+		.m0_write                (nios2_debug_mem_slave_agent_m0_write),                   //                .write
+		.rp_endofpacket          (nios2_debug_mem_slave_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (nios2_debug_mem_slave_agent_rp_ready),                   //                .ready
+		.rp_valid                (nios2_debug_mem_slave_agent_rp_valid),                   //                .valid
+		.rp_data                 (nios2_debug_mem_slave_agent_rp_data),                    //                .data
+		.rp_startofpacket        (nios2_debug_mem_slave_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_001_src_ready),                                  //              cp.ready
+		.cp_valid                (cmd_mux_001_src_valid),                                  //                .valid
+		.cp_data                 (cmd_mux_001_src_data),                                   //                .data
+		.cp_startofpacket        (cmd_mux_001_src_startofpacket),                          //                .startofpacket
+		.cp_endofpacket          (cmd_mux_001_src_endofpacket),                            //                .endofpacket
+		.cp_channel              (cmd_mux_001_src_channel),                                //                .channel
+		.rf_sink_ready           (nios2_debug_mem_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (nios2_debug_mem_slave_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (nios2_debug_mem_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (nios2_debug_mem_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (nios2_debug_mem_slave_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (nios2_debug_mem_slave_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (nios2_debug_mem_slave_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (nios2_debug_mem_slave_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (nios2_debug_mem_slave_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (nios2_debug_mem_slave_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_001_out_0_ready),                      // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_001_out_0_valid),                      //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_001_out_0_data),                       //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_001_out_0_error),                      //                .error
+		.rdata_fifo_src_ready    (nios2_debug_mem_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (nios2_debug_mem_slave_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (nios2_debug_mem_slave_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                                  //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                    //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (95),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) nios2_debug_mem_slave_agent_rsp_fifo (
+		.clk               (clk_50_clk_clk),                                         //       clk.clk
+		.reset             (nios2_reset_reset_bridge_in_reset_reset),                // clk_reset.reset
+		.in_data           (nios2_debug_mem_slave_agent_rf_source_data),             //        in.data
+		.in_valid          (nios2_debug_mem_slave_agent_rf_source_valid),            //          .valid
+		.in_ready          (nios2_debug_mem_slave_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (nios2_debug_mem_slave_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (nios2_debug_mem_slave_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (nios2_debug_mem_slave_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (nios2_debug_mem_slave_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (nios2_debug_mem_slave_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (nios2_debug_mem_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (nios2_debug_mem_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                                  // (terminated)
+		.csr_read          (1'b0),                                                   // (terminated)
+		.csr_write         (1'b0),                                                   // (terminated)
+		.csr_readdata      (),                                                       // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),                   // (terminated)
+		.almost_full_data  (),                                                       // (terminated)
+		.almost_empty_data (),                                                       // (terminated)
+		.in_empty          (1'b0),                                                   // (terminated)
+		.out_empty         (),                                                       // (terminated)
+		.in_error          (1'b0),                                                   // (terminated)
+		.out_error         (),                                                       // (terminated)
+		.in_channel        (1'b0),                                                   // (terminated)
+		.out_channel       ()                                                        // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (93),
+		.PKT_ORI_BURST_SIZE_L      (91),
+		.PKT_RESPONSE_STATUS_H     (90),
+		.PKT_RESPONSE_STATUS_L     (89),
+		.PKT_BURST_SIZE_H          (70),
+		.PKT_BURST_SIZE_L          (68),
+		.PKT_TRANS_LOCK            (60),
+		.PKT_BEGIN_BURST           (75),
+		.PKT_PROTECTION_H          (84),
+		.PKT_PROTECTION_L          (82),
+		.PKT_BURSTWRAP_H           (67),
+		.PKT_BURSTWRAP_L           (65),
+		.PKT_BYTE_CNT_H            (64),
+		.PKT_BYTE_CNT_L            (62),
+		.PKT_ADDR_H                (55),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (56),
+		.PKT_TRANS_POSTED          (57),
+		.PKT_TRANS_WRITE           (58),
+		.PKT_TRANS_READ            (59),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (78),
+		.PKT_SRC_ID_L              (77),
+		.PKT_DEST_ID_H             (80),
+		.PKT_DEST_ID_L             (79),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (4),
+		.ST_DATA_W                 (94),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) onchip_memory2_s1_agent (
+		.clk                     (clk_50_clk_clk),                                     //             clk.clk
+		.reset                   (nios2_reset_reset_bridge_in_reset_reset),            //       clk_reset.reset
+		.m0_address              (onchip_memory2_s1_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (onchip_memory2_s1_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (onchip_memory2_s1_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (onchip_memory2_s1_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (onchip_memory2_s1_agent_m0_lock),                    //                .lock
+		.m0_readdata             (onchip_memory2_s1_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (onchip_memory2_s1_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (onchip_memory2_s1_agent_m0_read),                    //                .read
+		.m0_waitrequest          (onchip_memory2_s1_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (onchip_memory2_s1_agent_m0_writedata),               //                .writedata
+		.m0_write                (onchip_memory2_s1_agent_m0_write),                   //                .write
+		.rp_endofpacket          (onchip_memory2_s1_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (onchip_memory2_s1_agent_rp_ready),                   //                .ready
+		.rp_valid                (onchip_memory2_s1_agent_rp_valid),                   //                .valid
+		.rp_data                 (onchip_memory2_s1_agent_rp_data),                    //                .data
+		.rp_startofpacket        (onchip_memory2_s1_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_002_src_ready),                              //              cp.ready
+		.cp_valid                (cmd_mux_002_src_valid),                              //                .valid
+		.cp_data                 (cmd_mux_002_src_data),                               //                .data
+		.cp_startofpacket        (cmd_mux_002_src_startofpacket),                      //                .startofpacket
+		.cp_endofpacket          (cmd_mux_002_src_endofpacket),                        //                .endofpacket
+		.cp_channel              (cmd_mux_002_src_channel),                            //                .channel
+		.rf_sink_ready           (onchip_memory2_s1_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (onchip_memory2_s1_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (onchip_memory2_s1_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (onchip_memory2_s1_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (onchip_memory2_s1_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (onchip_memory2_s1_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (onchip_memory2_s1_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (onchip_memory2_s1_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (onchip_memory2_s1_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (onchip_memory2_s1_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_002_out_0_ready),                  // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_002_out_0_valid),                  //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_002_out_0_data),                   //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_002_out_0_error),                  //                .error
+		.rdata_fifo_src_ready    (onchip_memory2_s1_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (onchip_memory2_s1_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (onchip_memory2_s1_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                              //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (95),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) onchip_memory2_s1_agent_rsp_fifo (
+		.clk               (clk_50_clk_clk),                                     //       clk.clk
+		.reset             (nios2_reset_reset_bridge_in_reset_reset),            // clk_reset.reset
+		.in_data           (onchip_memory2_s1_agent_rf_source_data),             //        in.data
+		.in_valid          (onchip_memory2_s1_agent_rf_source_valid),            //          .valid
+		.in_ready          (onchip_memory2_s1_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (onchip_memory2_s1_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (onchip_memory2_s1_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (onchip_memory2_s1_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (onchip_memory2_s1_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (onchip_memory2_s1_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (onchip_memory2_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (onchip_memory2_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                              // (terminated)
+		.csr_read          (1'b0),                                               // (terminated)
+		.csr_write         (1'b0),                                               // (terminated)
+		.csr_readdata      (),                                                   // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),               // (terminated)
+		.almost_full_data  (),                                                   // (terminated)
+		.almost_empty_data (),                                                   // (terminated)
+		.in_empty          (1'b0),                                               // (terminated)
+		.out_empty         (),                                                   // (terminated)
+		.in_error          (1'b0),                                               // (terminated)
+		.out_error         (),                                                   // (terminated)
+		.in_channel        (1'b0),                                               // (terminated)
+		.out_channel       ()                                                    // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (93),
+		.PKT_ORI_BURST_SIZE_L      (91),
+		.PKT_RESPONSE_STATUS_H     (90),
+		.PKT_RESPONSE_STATUS_L     (89),
+		.PKT_BURST_SIZE_H          (70),
+		.PKT_BURST_SIZE_L          (68),
+		.PKT_TRANS_LOCK            (60),
+		.PKT_BEGIN_BURST           (75),
+		.PKT_PROTECTION_H          (84),
+		.PKT_PROTECTION_L          (82),
+		.PKT_BURSTWRAP_H           (67),
+		.PKT_BURSTWRAP_L           (65),
+		.PKT_BYTE_CNT_H            (64),
+		.PKT_BYTE_CNT_L            (62),
+		.PKT_ADDR_H                (55),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (56),
+		.PKT_TRANS_POSTED          (57),
+		.PKT_TRANS_WRITE           (58),
+		.PKT_TRANS_READ            (59),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (78),
+		.PKT_SRC_ID_L              (77),
+		.PKT_DEST_ID_H             (80),
+		.PKT_DEST_ID_L             (79),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (4),
+		.ST_DATA_W                 (94),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) pio_led_s1_agent (
+		.clk                     (clk_50_clk_clk),                              //             clk.clk
+		.reset                   (nios2_reset_reset_bridge_in_reset_reset),     //       clk_reset.reset
+		.m0_address              (pio_led_s1_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (pio_led_s1_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (pio_led_s1_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (pio_led_s1_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (pio_led_s1_agent_m0_lock),                    //                .lock
+		.m0_readdata             (pio_led_s1_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (pio_led_s1_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (pio_led_s1_agent_m0_read),                    //                .read
+		.m0_waitrequest          (pio_led_s1_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (pio_led_s1_agent_m0_writedata),               //                .writedata
+		.m0_write                (pio_led_s1_agent_m0_write),                   //                .write
+		.rp_endofpacket          (pio_led_s1_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (pio_led_s1_agent_rp_ready),                   //                .ready
+		.rp_valid                (pio_led_s1_agent_rp_valid),                   //                .valid
+		.rp_data                 (pio_led_s1_agent_rp_data),                    //                .data
+		.rp_startofpacket        (pio_led_s1_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_003_src_ready),                       //              cp.ready
+		.cp_valid                (cmd_mux_003_src_valid),                       //                .valid
+		.cp_data                 (cmd_mux_003_src_data),                        //                .data
+		.cp_startofpacket        (cmd_mux_003_src_startofpacket),               //                .startofpacket
+		.cp_endofpacket          (cmd_mux_003_src_endofpacket),                 //                .endofpacket
+		.cp_channel              (cmd_mux_003_src_channel),                     //                .channel
+		.rf_sink_ready           (pio_led_s1_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (pio_led_s1_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (pio_led_s1_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (pio_led_s1_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (pio_led_s1_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (pio_led_s1_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (pio_led_s1_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (pio_led_s1_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (pio_led_s1_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (pio_led_s1_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_003_out_0_ready),           // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_003_out_0_valid),           //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_003_out_0_data),            //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_003_out_0_error),           //                .error
+		.rdata_fifo_src_ready    (pio_led_s1_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (pio_led_s1_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (pio_led_s1_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                       //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                         //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (95),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) pio_led_s1_agent_rsp_fifo (
+		.clk               (clk_50_clk_clk),                              //       clk.clk
+		.reset             (nios2_reset_reset_bridge_in_reset_reset),     // clk_reset.reset
+		.in_data           (pio_led_s1_agent_rf_source_data),             //        in.data
+		.in_valid          (pio_led_s1_agent_rf_source_valid),            //          .valid
+		.in_ready          (pio_led_s1_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (pio_led_s1_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (pio_led_s1_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (pio_led_s1_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (pio_led_s1_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (pio_led_s1_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (pio_led_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (pio_led_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                       // (terminated)
+		.csr_read          (1'b0),                                        // (terminated)
+		.csr_write         (1'b0),                                        // (terminated)
+		.csr_readdata      (),                                            // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),        // (terminated)
+		.almost_full_data  (),                                            // (terminated)
+		.almost_empty_data (),                                            // (terminated)
+		.in_empty          (1'b0),                                        // (terminated)
+		.out_empty         (),                                            // (terminated)
+		.in_error          (1'b0),                                        // (terminated)
+		.out_error         (),                                            // (terminated)
+		.in_channel        (1'b0),                                        // (terminated)
+		.out_channel       ()                                             // (terminated)
+	);
+
+	nios2_uc_mm_interconnect_0_router router (
+		.sink_ready         (nios2_data_master_agent_cp_ready),         //      sink.ready
+		.sink_valid         (nios2_data_master_agent_cp_valid),         //          .valid
+		.sink_data          (nios2_data_master_agent_cp_data),          //          .data
+		.sink_startofpacket (nios2_data_master_agent_cp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (nios2_data_master_agent_cp_endofpacket),   //          .endofpacket
+		.clk                (clk_50_clk_clk),                           //       clk.clk
+		.reset              (nios2_reset_reset_bridge_in_reset_reset),  // clk_reset.reset
+		.src_ready          (router_src_ready),                         //       src.ready
+		.src_valid          (router_src_valid),                         //          .valid
+		.src_data           (router_src_data),                          //          .data
+		.src_channel        (router_src_channel),                       //          .channel
+		.src_startofpacket  (router_src_startofpacket),                 //          .startofpacket
+		.src_endofpacket    (router_src_endofpacket)                    //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_router router_001 (
+		.sink_ready         (nios2_instruction_master_agent_cp_ready),         //      sink.ready
+		.sink_valid         (nios2_instruction_master_agent_cp_valid),         //          .valid
+		.sink_data          (nios2_instruction_master_agent_cp_data),          //          .data
+		.sink_startofpacket (nios2_instruction_master_agent_cp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (nios2_instruction_master_agent_cp_endofpacket),   //          .endofpacket
+		.clk                (clk_50_clk_clk),                                  //       clk.clk
+		.reset              (nios2_reset_reset_bridge_in_reset_reset),         // clk_reset.reset
+		.src_ready          (router_001_src_ready),                            //       src.ready
+		.src_valid          (router_001_src_valid),                            //          .valid
+		.src_data           (router_001_src_data),                             //          .data
+		.src_channel        (router_001_src_channel),                          //          .channel
+		.src_startofpacket  (router_001_src_startofpacket),                    //          .startofpacket
+		.src_endofpacket    (router_001_src_endofpacket)                       //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_router_002 router_002 (
+		.sink_ready         (jtag_uart_avalon_jtag_slave_agent_rp_ready),         //      sink.ready
+		.sink_valid         (jtag_uart_avalon_jtag_slave_agent_rp_valid),         //          .valid
+		.sink_data          (jtag_uart_avalon_jtag_slave_agent_rp_data),          //          .data
+		.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket),   //          .endofpacket
+		.clk                (clk_50_clk_clk),                                     //       clk.clk
+		.reset              (nios2_reset_reset_bridge_in_reset_reset),            // clk_reset.reset
+		.src_ready          (router_002_src_ready),                               //       src.ready
+		.src_valid          (router_002_src_valid),                               //          .valid
+		.src_data           (router_002_src_data),                                //          .data
+		.src_channel        (router_002_src_channel),                             //          .channel
+		.src_startofpacket  (router_002_src_startofpacket),                       //          .startofpacket
+		.src_endofpacket    (router_002_src_endofpacket)                          //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_router_002 router_003 (
+		.sink_ready         (nios2_debug_mem_slave_agent_rp_ready),         //      sink.ready
+		.sink_valid         (nios2_debug_mem_slave_agent_rp_valid),         //          .valid
+		.sink_data          (nios2_debug_mem_slave_agent_rp_data),          //          .data
+		.sink_startofpacket (nios2_debug_mem_slave_agent_rp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (nios2_debug_mem_slave_agent_rp_endofpacket),   //          .endofpacket
+		.clk                (clk_50_clk_clk),                               //       clk.clk
+		.reset              (nios2_reset_reset_bridge_in_reset_reset),      // clk_reset.reset
+		.src_ready          (router_003_src_ready),                         //       src.ready
+		.src_valid          (router_003_src_valid),                         //          .valid
+		.src_data           (router_003_src_data),                          //          .data
+		.src_channel        (router_003_src_channel),                       //          .channel
+		.src_startofpacket  (router_003_src_startofpacket),                 //          .startofpacket
+		.src_endofpacket    (router_003_src_endofpacket)                    //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_router_002 router_004 (
+		.sink_ready         (onchip_memory2_s1_agent_rp_ready),         //      sink.ready
+		.sink_valid         (onchip_memory2_s1_agent_rp_valid),         //          .valid
+		.sink_data          (onchip_memory2_s1_agent_rp_data),          //          .data
+		.sink_startofpacket (onchip_memory2_s1_agent_rp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (onchip_memory2_s1_agent_rp_endofpacket),   //          .endofpacket
+		.clk                (clk_50_clk_clk),                           //       clk.clk
+		.reset              (nios2_reset_reset_bridge_in_reset_reset),  // clk_reset.reset
+		.src_ready          (router_004_src_ready),                     //       src.ready
+		.src_valid          (router_004_src_valid),                     //          .valid
+		.src_data           (router_004_src_data),                      //          .data
+		.src_channel        (router_004_src_channel),                   //          .channel
+		.src_startofpacket  (router_004_src_startofpacket),             //          .startofpacket
+		.src_endofpacket    (router_004_src_endofpacket)                //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_router_002 router_005 (
+		.sink_ready         (pio_led_s1_agent_rp_ready),               //      sink.ready
+		.sink_valid         (pio_led_s1_agent_rp_valid),               //          .valid
+		.sink_data          (pio_led_s1_agent_rp_data),                //          .data
+		.sink_startofpacket (pio_led_s1_agent_rp_startofpacket),       //          .startofpacket
+		.sink_endofpacket   (pio_led_s1_agent_rp_endofpacket),         //          .endofpacket
+		.clk                (clk_50_clk_clk),                          //       clk.clk
+		.reset              (nios2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_005_src_ready),                    //       src.ready
+		.src_valid          (router_005_src_valid),                    //          .valid
+		.src_data           (router_005_src_data),                     //          .data
+		.src_channel        (router_005_src_channel),                  //          .channel
+		.src_startofpacket  (router_005_src_startofpacket),            //          .startofpacket
+		.src_endofpacket    (router_005_src_endofpacket)               //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_cmd_demux cmd_demux (
+		.clk                (clk_50_clk_clk),                          //       clk.clk
+		.reset              (nios2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_src_ready),                        //      sink.ready
+		.sink_channel       (router_src_channel),                      //          .channel
+		.sink_data          (router_src_data),                         //          .data
+		.sink_startofpacket (router_src_startofpacket),                //          .startofpacket
+		.sink_endofpacket   (router_src_endofpacket),                  //          .endofpacket
+		.sink_valid         (router_src_valid),                        //          .valid
+		.src0_ready         (cmd_demux_src0_ready),                    //      src0.ready
+		.src0_valid         (cmd_demux_src0_valid),                    //          .valid
+		.src0_data          (cmd_demux_src0_data),                     //          .data
+		.src0_channel       (cmd_demux_src0_channel),                  //          .channel
+		.src0_startofpacket (cmd_demux_src0_startofpacket),            //          .startofpacket
+		.src0_endofpacket   (cmd_demux_src0_endofpacket),              //          .endofpacket
+		.src1_ready         (cmd_demux_src1_ready),                    //      src1.ready
+		.src1_valid         (cmd_demux_src1_valid),                    //          .valid
+		.src1_data          (cmd_demux_src1_data),                     //          .data
+		.src1_channel       (cmd_demux_src1_channel),                  //          .channel
+		.src1_startofpacket (cmd_demux_src1_startofpacket),            //          .startofpacket
+		.src1_endofpacket   (cmd_demux_src1_endofpacket),              //          .endofpacket
+		.src2_ready         (cmd_demux_src2_ready),                    //      src2.ready
+		.src2_valid         (cmd_demux_src2_valid),                    //          .valid
+		.src2_data          (cmd_demux_src2_data),                     //          .data
+		.src2_channel       (cmd_demux_src2_channel),                  //          .channel
+		.src2_startofpacket (cmd_demux_src2_startofpacket),            //          .startofpacket
+		.src2_endofpacket   (cmd_demux_src2_endofpacket),              //          .endofpacket
+		.src3_ready         (cmd_demux_src3_ready),                    //      src3.ready
+		.src3_valid         (cmd_demux_src3_valid),                    //          .valid
+		.src3_data          (cmd_demux_src3_data),                     //          .data
+		.src3_channel       (cmd_demux_src3_channel),                  //          .channel
+		.src3_startofpacket (cmd_demux_src3_startofpacket),            //          .startofpacket
+		.src3_endofpacket   (cmd_demux_src3_endofpacket)               //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_cmd_demux cmd_demux_001 (
+		.clk                (clk_50_clk_clk),                          //       clk.clk
+		.reset              (nios2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_001_src_ready),                    //      sink.ready
+		.sink_channel       (router_001_src_channel),                  //          .channel
+		.sink_data          (router_001_src_data),                     //          .data
+		.sink_startofpacket (router_001_src_startofpacket),            //          .startofpacket
+		.sink_endofpacket   (router_001_src_endofpacket),              //          .endofpacket
+		.sink_valid         (router_001_src_valid),                    //          .valid
+		.src0_ready         (cmd_demux_001_src0_ready),                //      src0.ready
+		.src0_valid         (cmd_demux_001_src0_valid),                //          .valid
+		.src0_data          (cmd_demux_001_src0_data),                 //          .data
+		.src0_channel       (cmd_demux_001_src0_channel),              //          .channel
+		.src0_startofpacket (cmd_demux_001_src0_startofpacket),        //          .startofpacket
+		.src0_endofpacket   (cmd_demux_001_src0_endofpacket),          //          .endofpacket
+		.src1_ready         (cmd_demux_001_src1_ready),                //      src1.ready
+		.src1_valid         (cmd_demux_001_src1_valid),                //          .valid
+		.src1_data          (cmd_demux_001_src1_data),                 //          .data
+		.src1_channel       (cmd_demux_001_src1_channel),              //          .channel
+		.src1_startofpacket (cmd_demux_001_src1_startofpacket),        //          .startofpacket
+		.src1_endofpacket   (cmd_demux_001_src1_endofpacket),          //          .endofpacket
+		.src2_ready         (cmd_demux_001_src2_ready),                //      src2.ready
+		.src2_valid         (cmd_demux_001_src2_valid),                //          .valid
+		.src2_data          (cmd_demux_001_src2_data),                 //          .data
+		.src2_channel       (cmd_demux_001_src2_channel),              //          .channel
+		.src2_startofpacket (cmd_demux_001_src2_startofpacket),        //          .startofpacket
+		.src2_endofpacket   (cmd_demux_001_src2_endofpacket),          //          .endofpacket
+		.src3_ready         (cmd_demux_001_src3_ready),                //      src3.ready
+		.src3_valid         (cmd_demux_001_src3_valid),                //          .valid
+		.src3_data          (cmd_demux_001_src3_data),                 //          .data
+		.src3_channel       (cmd_demux_001_src3_channel),              //          .channel
+		.src3_startofpacket (cmd_demux_001_src3_startofpacket),        //          .startofpacket
+		.src3_endofpacket   (cmd_demux_001_src3_endofpacket)           //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_cmd_mux cmd_mux (
+		.clk                 (clk_50_clk_clk),                          //       clk.clk
+		.reset               (nios2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_src_ready),                       //       src.ready
+		.src_valid           (cmd_mux_src_valid),                       //          .valid
+		.src_data            (cmd_mux_src_data),                        //          .data
+		.src_channel         (cmd_mux_src_channel),                     //          .channel
+		.src_startofpacket   (cmd_mux_src_startofpacket),               //          .startofpacket
+		.src_endofpacket     (cmd_mux_src_endofpacket),                 //          .endofpacket
+		.sink0_ready         (cmd_demux_src0_ready),                    //     sink0.ready
+		.sink0_valid         (cmd_demux_src0_valid),                    //          .valid
+		.sink0_channel       (cmd_demux_src0_channel),                  //          .channel
+		.sink0_data          (cmd_demux_src0_data),                     //          .data
+		.sink0_startofpacket (cmd_demux_src0_startofpacket),            //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src0_endofpacket),              //          .endofpacket
+		.sink1_ready         (cmd_demux_001_src0_ready),                //     sink1.ready
+		.sink1_valid         (cmd_demux_001_src0_valid),                //          .valid
+		.sink1_channel       (cmd_demux_001_src0_channel),              //          .channel
+		.sink1_data          (cmd_demux_001_src0_data),                 //          .data
+		.sink1_startofpacket (cmd_demux_001_src0_startofpacket),        //          .startofpacket
+		.sink1_endofpacket   (cmd_demux_001_src0_endofpacket)           //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_cmd_mux cmd_mux_001 (
+		.clk                 (clk_50_clk_clk),                          //       clk.clk
+		.reset               (nios2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_001_src_ready),                   //       src.ready
+		.src_valid           (cmd_mux_001_src_valid),                   //          .valid
+		.src_data            (cmd_mux_001_src_data),                    //          .data
+		.src_channel         (cmd_mux_001_src_channel),                 //          .channel
+		.src_startofpacket   (cmd_mux_001_src_startofpacket),           //          .startofpacket
+		.src_endofpacket     (cmd_mux_001_src_endofpacket),             //          .endofpacket
+		.sink0_ready         (cmd_demux_src1_ready),                    //     sink0.ready
+		.sink0_valid         (cmd_demux_src1_valid),                    //          .valid
+		.sink0_channel       (cmd_demux_src1_channel),                  //          .channel
+		.sink0_data          (cmd_demux_src1_data),                     //          .data
+		.sink0_startofpacket (cmd_demux_src1_startofpacket),            //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src1_endofpacket),              //          .endofpacket
+		.sink1_ready         (cmd_demux_001_src1_ready),                //     sink1.ready
+		.sink1_valid         (cmd_demux_001_src1_valid),                //          .valid
+		.sink1_channel       (cmd_demux_001_src1_channel),              //          .channel
+		.sink1_data          (cmd_demux_001_src1_data),                 //          .data
+		.sink1_startofpacket (cmd_demux_001_src1_startofpacket),        //          .startofpacket
+		.sink1_endofpacket   (cmd_demux_001_src1_endofpacket)           //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_cmd_mux cmd_mux_002 (
+		.clk                 (clk_50_clk_clk),                          //       clk.clk
+		.reset               (nios2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_002_src_ready),                   //       src.ready
+		.src_valid           (cmd_mux_002_src_valid),                   //          .valid
+		.src_data            (cmd_mux_002_src_data),                    //          .data
+		.src_channel         (cmd_mux_002_src_channel),                 //          .channel
+		.src_startofpacket   (cmd_mux_002_src_startofpacket),           //          .startofpacket
+		.src_endofpacket     (cmd_mux_002_src_endofpacket),             //          .endofpacket
+		.sink0_ready         (cmd_demux_src2_ready),                    //     sink0.ready
+		.sink0_valid         (cmd_demux_src2_valid),                    //          .valid
+		.sink0_channel       (cmd_demux_src2_channel),                  //          .channel
+		.sink0_data          (cmd_demux_src2_data),                     //          .data
+		.sink0_startofpacket (cmd_demux_src2_startofpacket),            //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src2_endofpacket),              //          .endofpacket
+		.sink1_ready         (cmd_demux_001_src2_ready),                //     sink1.ready
+		.sink1_valid         (cmd_demux_001_src2_valid),                //          .valid
+		.sink1_channel       (cmd_demux_001_src2_channel),              //          .channel
+		.sink1_data          (cmd_demux_001_src2_data),                 //          .data
+		.sink1_startofpacket (cmd_demux_001_src2_startofpacket),        //          .startofpacket
+		.sink1_endofpacket   (cmd_demux_001_src2_endofpacket)           //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_cmd_mux cmd_mux_003 (
+		.clk                 (clk_50_clk_clk),                          //       clk.clk
+		.reset               (nios2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_003_src_ready),                   //       src.ready
+		.src_valid           (cmd_mux_003_src_valid),                   //          .valid
+		.src_data            (cmd_mux_003_src_data),                    //          .data
+		.src_channel         (cmd_mux_003_src_channel),                 //          .channel
+		.src_startofpacket   (cmd_mux_003_src_startofpacket),           //          .startofpacket
+		.src_endofpacket     (cmd_mux_003_src_endofpacket),             //          .endofpacket
+		.sink0_ready         (cmd_demux_src3_ready),                    //     sink0.ready
+		.sink0_valid         (cmd_demux_src3_valid),                    //          .valid
+		.sink0_channel       (cmd_demux_src3_channel),                  //          .channel
+		.sink0_data          (cmd_demux_src3_data),                     //          .data
+		.sink0_startofpacket (cmd_demux_src3_startofpacket),            //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src3_endofpacket),              //          .endofpacket
+		.sink1_ready         (cmd_demux_001_src3_ready),                //     sink1.ready
+		.sink1_valid         (cmd_demux_001_src3_valid),                //          .valid
+		.sink1_channel       (cmd_demux_001_src3_channel),              //          .channel
+		.sink1_data          (cmd_demux_001_src3_data),                 //          .data
+		.sink1_startofpacket (cmd_demux_001_src3_startofpacket),        //          .startofpacket
+		.sink1_endofpacket   (cmd_demux_001_src3_endofpacket)           //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_rsp_demux rsp_demux (
+		.clk                (clk_50_clk_clk),                          //       clk.clk
+		.reset              (nios2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_002_src_ready),                    //      sink.ready
+		.sink_channel       (router_002_src_channel),                  //          .channel
+		.sink_data          (router_002_src_data),                     //          .data
+		.sink_startofpacket (router_002_src_startofpacket),            //          .startofpacket
+		.sink_endofpacket   (router_002_src_endofpacket),              //          .endofpacket
+		.sink_valid         (router_002_src_valid),                    //          .valid
+		.src0_ready         (rsp_demux_src0_ready),                    //      src0.ready
+		.src0_valid         (rsp_demux_src0_valid),                    //          .valid
+		.src0_data          (rsp_demux_src0_data),                     //          .data
+		.src0_channel       (rsp_demux_src0_channel),                  //          .channel
+		.src0_startofpacket (rsp_demux_src0_startofpacket),            //          .startofpacket
+		.src0_endofpacket   (rsp_demux_src0_endofpacket),              //          .endofpacket
+		.src1_ready         (rsp_demux_src1_ready),                    //      src1.ready
+		.src1_valid         (rsp_demux_src1_valid),                    //          .valid
+		.src1_data          (rsp_demux_src1_data),                     //          .data
+		.src1_channel       (rsp_demux_src1_channel),                  //          .channel
+		.src1_startofpacket (rsp_demux_src1_startofpacket),            //          .startofpacket
+		.src1_endofpacket   (rsp_demux_src1_endofpacket)               //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_rsp_demux rsp_demux_001 (
+		.clk                (clk_50_clk_clk),                          //       clk.clk
+		.reset              (nios2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_003_src_ready),                    //      sink.ready
+		.sink_channel       (router_003_src_channel),                  //          .channel
+		.sink_data          (router_003_src_data),                     //          .data
+		.sink_startofpacket (router_003_src_startofpacket),            //          .startofpacket
+		.sink_endofpacket   (router_003_src_endofpacket),              //          .endofpacket
+		.sink_valid         (router_003_src_valid),                    //          .valid
+		.src0_ready         (rsp_demux_001_src0_ready),                //      src0.ready
+		.src0_valid         (rsp_demux_001_src0_valid),                //          .valid
+		.src0_data          (rsp_demux_001_src0_data),                 //          .data
+		.src0_channel       (rsp_demux_001_src0_channel),              //          .channel
+		.src0_startofpacket (rsp_demux_001_src0_startofpacket),        //          .startofpacket
+		.src0_endofpacket   (rsp_demux_001_src0_endofpacket),          //          .endofpacket
+		.src1_ready         (rsp_demux_001_src1_ready),                //      src1.ready
+		.src1_valid         (rsp_demux_001_src1_valid),                //          .valid
+		.src1_data          (rsp_demux_001_src1_data),                 //          .data
+		.src1_channel       (rsp_demux_001_src1_channel),              //          .channel
+		.src1_startofpacket (rsp_demux_001_src1_startofpacket),        //          .startofpacket
+		.src1_endofpacket   (rsp_demux_001_src1_endofpacket)           //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_rsp_demux rsp_demux_002 (
+		.clk                (clk_50_clk_clk),                          //       clk.clk
+		.reset              (nios2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_004_src_ready),                    //      sink.ready
+		.sink_channel       (router_004_src_channel),                  //          .channel
+		.sink_data          (router_004_src_data),                     //          .data
+		.sink_startofpacket (router_004_src_startofpacket),            //          .startofpacket
+		.sink_endofpacket   (router_004_src_endofpacket),              //          .endofpacket
+		.sink_valid         (router_004_src_valid),                    //          .valid
+		.src0_ready         (rsp_demux_002_src0_ready),                //      src0.ready
+		.src0_valid         (rsp_demux_002_src0_valid),                //          .valid
+		.src0_data          (rsp_demux_002_src0_data),                 //          .data
+		.src0_channel       (rsp_demux_002_src0_channel),              //          .channel
+		.src0_startofpacket (rsp_demux_002_src0_startofpacket),        //          .startofpacket
+		.src0_endofpacket   (rsp_demux_002_src0_endofpacket),          //          .endofpacket
+		.src1_ready         (rsp_demux_002_src1_ready),                //      src1.ready
+		.src1_valid         (rsp_demux_002_src1_valid),                //          .valid
+		.src1_data          (rsp_demux_002_src1_data),                 //          .data
+		.src1_channel       (rsp_demux_002_src1_channel),              //          .channel
+		.src1_startofpacket (rsp_demux_002_src1_startofpacket),        //          .startofpacket
+		.src1_endofpacket   (rsp_demux_002_src1_endofpacket)           //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_rsp_demux rsp_demux_003 (
+		.clk                (clk_50_clk_clk),                          //       clk.clk
+		.reset              (nios2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_005_src_ready),                    //      sink.ready
+		.sink_channel       (router_005_src_channel),                  //          .channel
+		.sink_data          (router_005_src_data),                     //          .data
+		.sink_startofpacket (router_005_src_startofpacket),            //          .startofpacket
+		.sink_endofpacket   (router_005_src_endofpacket),              //          .endofpacket
+		.sink_valid         (router_005_src_valid),                    //          .valid
+		.src0_ready         (rsp_demux_003_src0_ready),                //      src0.ready
+		.src0_valid         (rsp_demux_003_src0_valid),                //          .valid
+		.src0_data          (rsp_demux_003_src0_data),                 //          .data
+		.src0_channel       (rsp_demux_003_src0_channel),              //          .channel
+		.src0_startofpacket (rsp_demux_003_src0_startofpacket),        //          .startofpacket
+		.src0_endofpacket   (rsp_demux_003_src0_endofpacket),          //          .endofpacket
+		.src1_ready         (rsp_demux_003_src1_ready),                //      src1.ready
+		.src1_valid         (rsp_demux_003_src1_valid),                //          .valid
+		.src1_data          (rsp_demux_003_src1_data),                 //          .data
+		.src1_channel       (rsp_demux_003_src1_channel),              //          .channel
+		.src1_startofpacket (rsp_demux_003_src1_startofpacket),        //          .startofpacket
+		.src1_endofpacket   (rsp_demux_003_src1_endofpacket)           //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_rsp_mux rsp_mux (
+		.clk                 (clk_50_clk_clk),                          //       clk.clk
+		.reset               (nios2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (rsp_mux_src_ready),                       //       src.ready
+		.src_valid           (rsp_mux_src_valid),                       //          .valid
+		.src_data            (rsp_mux_src_data),                        //          .data
+		.src_channel         (rsp_mux_src_channel),                     //          .channel
+		.src_startofpacket   (rsp_mux_src_startofpacket),               //          .startofpacket
+		.src_endofpacket     (rsp_mux_src_endofpacket),                 //          .endofpacket
+		.sink0_ready         (rsp_demux_src0_ready),                    //     sink0.ready
+		.sink0_valid         (rsp_demux_src0_valid),                    //          .valid
+		.sink0_channel       (rsp_demux_src0_channel),                  //          .channel
+		.sink0_data          (rsp_demux_src0_data),                     //          .data
+		.sink0_startofpacket (rsp_demux_src0_startofpacket),            //          .startofpacket
+		.sink0_endofpacket   (rsp_demux_src0_endofpacket),              //          .endofpacket
+		.sink1_ready         (rsp_demux_001_src0_ready),                //     sink1.ready
+		.sink1_valid         (rsp_demux_001_src0_valid),                //          .valid
+		.sink1_channel       (rsp_demux_001_src0_channel),              //          .channel
+		.sink1_data          (rsp_demux_001_src0_data),                 //          .data
+		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),        //          .startofpacket
+		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket),          //          .endofpacket
+		.sink2_ready         (rsp_demux_002_src0_ready),                //     sink2.ready
+		.sink2_valid         (rsp_demux_002_src0_valid),                //          .valid
+		.sink2_channel       (rsp_demux_002_src0_channel),              //          .channel
+		.sink2_data          (rsp_demux_002_src0_data),                 //          .data
+		.sink2_startofpacket (rsp_demux_002_src0_startofpacket),        //          .startofpacket
+		.sink2_endofpacket   (rsp_demux_002_src0_endofpacket),          //          .endofpacket
+		.sink3_ready         (rsp_demux_003_src0_ready),                //     sink3.ready
+		.sink3_valid         (rsp_demux_003_src0_valid),                //          .valid
+		.sink3_channel       (rsp_demux_003_src0_channel),              //          .channel
+		.sink3_data          (rsp_demux_003_src0_data),                 //          .data
+		.sink3_startofpacket (rsp_demux_003_src0_startofpacket),        //          .startofpacket
+		.sink3_endofpacket   (rsp_demux_003_src0_endofpacket)           //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_rsp_mux rsp_mux_001 (
+		.clk                 (clk_50_clk_clk),                          //       clk.clk
+		.reset               (nios2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (rsp_mux_001_src_ready),                   //       src.ready
+		.src_valid           (rsp_mux_001_src_valid),                   //          .valid
+		.src_data            (rsp_mux_001_src_data),                    //          .data
+		.src_channel         (rsp_mux_001_src_channel),                 //          .channel
+		.src_startofpacket   (rsp_mux_001_src_startofpacket),           //          .startofpacket
+		.src_endofpacket     (rsp_mux_001_src_endofpacket),             //          .endofpacket
+		.sink0_ready         (rsp_demux_src1_ready),                    //     sink0.ready
+		.sink0_valid         (rsp_demux_src1_valid),                    //          .valid
+		.sink0_channel       (rsp_demux_src1_channel),                  //          .channel
+		.sink0_data          (rsp_demux_src1_data),                     //          .data
+		.sink0_startofpacket (rsp_demux_src1_startofpacket),            //          .startofpacket
+		.sink0_endofpacket   (rsp_demux_src1_endofpacket),              //          .endofpacket
+		.sink1_ready         (rsp_demux_001_src1_ready),                //     sink1.ready
+		.sink1_valid         (rsp_demux_001_src1_valid),                //          .valid
+		.sink1_channel       (rsp_demux_001_src1_channel),              //          .channel
+		.sink1_data          (rsp_demux_001_src1_data),                 //          .data
+		.sink1_startofpacket (rsp_demux_001_src1_startofpacket),        //          .startofpacket
+		.sink1_endofpacket   (rsp_demux_001_src1_endofpacket),          //          .endofpacket
+		.sink2_ready         (rsp_demux_002_src1_ready),                //     sink2.ready
+		.sink2_valid         (rsp_demux_002_src1_valid),                //          .valid
+		.sink2_channel       (rsp_demux_002_src1_channel),              //          .channel
+		.sink2_data          (rsp_demux_002_src1_data),                 //          .data
+		.sink2_startofpacket (rsp_demux_002_src1_startofpacket),        //          .startofpacket
+		.sink2_endofpacket   (rsp_demux_002_src1_endofpacket),          //          .endofpacket
+		.sink3_ready         (rsp_demux_003_src1_ready),                //     sink3.ready
+		.sink3_valid         (rsp_demux_003_src1_valid),                //          .valid
+		.sink3_channel       (rsp_demux_003_src1_channel),              //          .channel
+		.sink3_data          (rsp_demux_003_src1_data),                 //          .data
+		.sink3_startofpacket (rsp_demux_003_src1_startofpacket),        //          .startofpacket
+		.sink3_endofpacket   (rsp_demux_003_src1_endofpacket)           //          .endofpacket
+	);
+
+	nios2_uc_mm_interconnect_0_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter (
+		.in_clk_0_clk   (clk_50_clk_clk),                                         // in_clk_0.clk
+		.in_rst_0_reset (nios2_reset_reset_bridge_in_reset_reset),                // in_rst_0.reset
+		.in_0_data      (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_out_0_data),                           //    out_0.data
+		.out_0_valid    (avalon_st_adapter_out_0_valid),                          //         .valid
+		.out_0_ready    (avalon_st_adapter_out_0_ready),                          //         .ready
+		.out_0_error    (avalon_st_adapter_out_0_error)                           //         .error
+	);
+
+	nios2_uc_mm_interconnect_0_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_001 (
+		.in_clk_0_clk   (clk_50_clk_clk),                                   // in_clk_0.clk
+		.in_rst_0_reset (nios2_reset_reset_bridge_in_reset_reset),          // in_rst_0.reset
+		.in_0_data      (nios2_debug_mem_slave_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (nios2_debug_mem_slave_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (nios2_debug_mem_slave_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_001_out_0_data),                 //    out_0.data
+		.out_0_valid    (avalon_st_adapter_001_out_0_valid),                //         .valid
+		.out_0_ready    (avalon_st_adapter_001_out_0_ready),                //         .ready
+		.out_0_error    (avalon_st_adapter_001_out_0_error)                 //         .error
+	);
+
+	nios2_uc_mm_interconnect_0_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_002 (
+		.in_clk_0_clk   (clk_50_clk_clk),                               // in_clk_0.clk
+		.in_rst_0_reset (nios2_reset_reset_bridge_in_reset_reset),      // in_rst_0.reset
+		.in_0_data      (onchip_memory2_s1_agent_rdata_fifo_src_data),  //     in_0.data
+		.in_0_valid     (onchip_memory2_s1_agent_rdata_fifo_src_valid), //         .valid
+		.in_0_ready     (onchip_memory2_s1_agent_rdata_fifo_src_ready), //         .ready
+		.out_0_data     (avalon_st_adapter_002_out_0_data),             //    out_0.data
+		.out_0_valid    (avalon_st_adapter_002_out_0_valid),            //         .valid
+		.out_0_ready    (avalon_st_adapter_002_out_0_ready),            //         .ready
+		.out_0_error    (avalon_st_adapter_002_out_0_error)             //         .error
+	);
+
+	nios2_uc_mm_interconnect_0_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_003 (
+		.in_clk_0_clk   (clk_50_clk_clk),                          // in_clk_0.clk
+		.in_rst_0_reset (nios2_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (pio_led_s1_agent_rdata_fifo_src_data),    //     in_0.data
+		.in_0_valid     (pio_led_s1_agent_rdata_fifo_src_valid),   //         .valid
+		.in_0_ready     (pio_led_s1_agent_rdata_fifo_src_ready),   //         .ready
+		.out_0_data     (avalon_st_adapter_003_out_0_data),        //    out_0.data
+		.out_0_valid    (avalon_st_adapter_003_out_0_valid),       //         .valid
+		.out_0_ready    (avalon_st_adapter_003_out_0_ready),       //         .ready
+		.out_0_error    (avalon_st_adapter_003_out_0_error)        //         .error
+	);
+
+endmodule

nios2_uc/synthesis/submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter.v

@@ -0,0 +1,202 @@
+// nios2_uc_mm_interconnect_0_avalon_st_adapter.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.1 646
+
+`timescale 1 ps / 1 ps
+module nios2_uc_mm_interconnect_0_avalon_st_adapter #(
+		parameter inBitsPerSymbol = 34,
+		parameter inUsePackets    = 0,
+		parameter inDataWidth     = 34,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 0,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 34,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 1,
+		parameter outUseEmptyPort = 0,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,   // in_clk_0.clk
+		input  wire        in_rst_0_reset, // in_rst_0.reset
+		input  wire [33:0] in_0_data,      //     in_0.data
+		input  wire        in_0_valid,     //         .valid
+		output wire        in_0_ready,     //         .ready
+		output wire [33:0] out_0_data,     //    out_0.data
+		output wire        out_0_valid,    //         .valid
+		input  wire        out_0_ready,    //         .ready
+		output wire [0:0]  out_0_error     //         .error
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	nios2_uc_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
+		.clk       (in_clk_0_clk),    //   clk.clk
+		.reset_n   (~in_rst_0_reset), // reset.reset_n
+		.in_data   (in_0_data),       //    in.data
+		.in_valid  (in_0_valid),      //      .valid
+		.in_ready  (in_0_ready),      //      .ready
+		.out_data  (out_0_data),      //   out.data
+		.out_valid (out_0_valid),     //      .valid
+		.out_ready (out_0_ready),     //      .ready
+		.out_error (out_0_error)      //      .error
+	);
+
+endmodule

nios2_uc/synthesis/submodules/nios2_uc_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv

@@ -0,0 +1,107 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        nios2_uc_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+//   use_ready:          true
+//   use_packets:        false
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         34
+//   channel_width:      0
+//   in_error_width:     0
+//   out_error_width:    1
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module nios2_uc_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [34-1: 0]     in_data,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [34-1: 0] out_data,
+ output reg [0:0]         out_error,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+   reg in_error = 0;
+   initial in_error = 0;
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+

nios2_uc/synthesis/submodules/nios2_uc_mm_interconnect_0_cmd_demux.sv

@@ -0,0 +1,145 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         nios2_uc_mm_interconnect_0_cmd_demux
+//   ST_DATA_W:           94
+//   ST_CHANNEL_W:        4
+//   NUM_OUTPUTS:         4
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module nios2_uc_mm_interconnect_0_cmd_demux
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [94-1    : 0]   sink_data, // ST_DATA_W=94
+    input  [4-1 : 0]   sink_channel, // ST_CHANNEL_W=4
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [94-1    : 0] src0_data, // ST_DATA_W=94
+    output reg [4-1 : 0] src0_channel, // ST_CHANNEL_W=4
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [94-1    : 0] src1_data, // ST_DATA_W=94
+    output reg [4-1 : 0] src1_channel, // ST_CHANNEL_W=4
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+    output reg                      src2_valid,
+    output reg [94-1    : 0] src2_data, // ST_DATA_W=94
+    output reg [4-1 : 0] src2_channel, // ST_CHANNEL_W=4
+    output reg                      src2_startofpacket,
+    output reg                      src2_endofpacket,
+    input                           src2_ready,
+
+    output reg                      src3_valid,
+    output reg [94-1    : 0] src3_data, // ST_DATA_W=94
+    output reg [4-1 : 0] src3_channel, // ST_CHANNEL_W=4
+    output reg                      src3_startofpacket,
+    output reg                      src3_endofpacket,
+    input                           src3_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 4;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+        src2_data          = sink_data;
+        src2_startofpacket = sink_startofpacket;
+        src2_endofpacket   = sink_endofpacket;
+        src2_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src2_valid         = sink_channel[2] && sink_valid;
+
+        src3_data          = sink_data;
+        src3_startofpacket = sink_startofpacket;
+        src3_endofpacket   = sink_endofpacket;
+        src3_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src3_valid         = sink_channel[3] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+    assign ready_vector[2] = src2_ready;
+    assign ready_vector[3] = src3_ready;
+
+    assign sink_ready = |(sink_channel & ready_vector);
+
+endmodule
+

nios2_uc/synthesis/submodules/nios2_uc_mm_interconnect_0_cmd_mux.sv

@@ -0,0 +1,322 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         nios2_uc_mm_interconnect_0_cmd_mux
+//   NUM_INPUTS:          2
+//   ARBITRATION_SHARES:  1 1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        1
+//   PKT_TRANS_LOCK:      60 (arbitration locking enabled)
+//   ST_DATA_W:           94
+//   ST_CHANNEL_W:        4
+// ------------------------------------------
+
+module nios2_uc_mm_interconnect_0_cmd_mux
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [94-1   : 0]  sink0_data,
+    input [4-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [94-1   : 0]  sink1_data,
+    input [4-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [94-1    : 0] src_data,
+    output [4-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 94 + 4 + 2;
+    localparam NUM_INPUTS       = 2;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 1;
+    localparam ST_DATA_W        = 94;
+    localparam ST_CHANNEL_W     = 4;
+    localparam PKT_TRANS_LOCK   = 60;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+
+    wire [NUM_INPUTS - 1 : 0] eop;
+    assign eop[0] = sink0_endofpacket;
+    assign eop[1] = sink1_endofpacket;
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[60];
+      lock[1] = sink1_data[60];
+    end
+    reg [NUM_INPUTS - 1 : 0] locked = '0;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        locked <= '0;
+      end
+      else begin
+        locked <= next_grant & lock;
+      end
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+        // Update the counter, but don't decrement below 0.
+      p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (update_grant) begin
+          share_count <= next_grant_share;
+          share_count_zero_flag <= (next_grant_share == '0);
+        end
+        else if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // The pipeline delays grant by one cycle, so
+        // we have to calculate the update_grant signal
+        // one cycle ahead of time.
+        //
+        // Possible optimization: omit the first clause
+        //    "if (!packet_in_progress & ~src_valid) ..."
+        //   cost: one idle cycle at the the beginning of each 
+        //     grant cycle.
+        //   benefit: save a small amount of logic.
+        // ------------------------------------------
+    if (!packet_in_progress & !src_valid)
+      update_grant = 1;
+    if (last_cycle && share_count_zero_flag)
+      update_grant = 1;
+    end
+
+    wire save_grant;
+    assign save_grant = update_grant;
+    assign grant = saved_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] prev_request;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        prev_request <= '0;
+      else
+        prev_request <= request & ~(valid & eop);
+    end
+
+    assign request = (PIPELINE_ARB == 1) ? valid | locked :
+    prev_request | valid | locked;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("round-robin"),
+    .PIPELINE (1)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+

nios2_uc/synthesis/submodules/nios2_uc_mm_interconnect_0_router.sv

@@ -0,0 +1,241 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module nios2_uc_mm_interconnect_0_router_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 2,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 2 
+   )
+  (output [80 - 79 : 0] default_destination_id,
+   output [4-1 : 0] default_wr_channel,
+   output [4-1 : 0] default_rd_channel,
+   output [4-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[80 - 79 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 4'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 4'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 4'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module nios2_uc_mm_interconnect_0_router
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [94-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [94-1    : 0] src_data,
+    output reg [4-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 55;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 80;
+    localparam PKT_DEST_ID_L = 79;
+    localparam PKT_PROTECTION_H = 84;
+    localparam PKT_PROTECTION_L = 82;
+    localparam ST_DATA_W = 94;
+    localparam ST_CHANNEL_W = 4;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 58;
+    localparam PKT_TRANS_READ  = 59;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h80000 - 64'h40000); 
+    localparam PAD1 = log2ceil(64'h81000 - 64'h80800); 
+    localparam PAD2 = log2ceil(64'h81020 - 64'h81010); 
+    localparam PAD3 = log2ceil(64'h81030 - 64'h81028); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h81030;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH-1;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+      reg [PKT_ADDR_W-1 : 0] address;
+      always @* begin
+        address = {PKT_ADDR_W{1'b0}};
+        address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
+      end   
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [4-1 : 0] default_src_channel;
+
+
+
+
+
+
+    nios2_uc_mm_interconnect_0_router_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+
+    // ( 0x40000 .. 0x80000 )
+    if ( {address[RG:PAD0],{PAD0{1'b0}}} == 20'h40000   ) begin
+            src_channel = 4'b0100;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
+    end
+
+    // ( 0x80800 .. 0x81000 )
+    if ( {address[RG:PAD1],{PAD1{1'b0}}} == 20'h80800   ) begin
+            src_channel = 4'b0010;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
+    end
+
+    // ( 0x81010 .. 0x81020 )
+    if ( {address[RG:PAD2],{PAD2{1'b0}}} == 20'h81010   ) begin
+            src_channel = 4'b1000;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
+    end
+
+    // ( 0x81028 .. 0x81030 )
+    if ( {address[RG:PAD3],{PAD3{1'b0}}} == 20'h81028   ) begin
+            src_channel = 4'b0001;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
+    end
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+

nios2_uc/synthesis/submodules/nios2_uc_mm_interconnect_0_router_002.sv

@@ -0,0 +1,224 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module nios2_uc_mm_interconnect_0_router_002_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [80 - 79 : 0] default_destination_id,
+   output [4-1 : 0] default_wr_channel,
+   output [4-1 : 0] default_rd_channel,
+   output [4-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[80 - 79 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 4'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 4'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 4'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module nios2_uc_mm_interconnect_0_router_002
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [94-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [94-1    : 0] src_data,
+    output reg [4-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 55;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 80;
+    localparam PKT_DEST_ID_L = 79;
+    localparam PKT_PROTECTION_H = 84;
+    localparam PKT_PROTECTION_L = 82;
+    localparam ST_DATA_W = 94;
+    localparam ST_CHANNEL_W = 4;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 58;
+    localparam PKT_TRANS_READ  = 59;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [4-1 : 0] default_src_channel;
+
+
+
+
+    // -------------------------------------------------------
+    // Write and read transaction signals
+    // -------------------------------------------------------
+    wire read_transaction;
+    assign read_transaction  = sink_data[PKT_TRANS_READ];
+
+
+    nios2_uc_mm_interconnect_0_router_002_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 4'b01;
+        end
+
+        if (destid == 1  && read_transaction) begin
+            src_channel = 4'b10;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+

nios2_uc/synthesis/submodules/nios2_uc_mm_interconnect_0_rsp_demux.sv

@@ -0,0 +1,115 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         nios2_uc_mm_interconnect_0_rsp_demux
+//   ST_DATA_W:           94
+//   ST_CHANNEL_W:        4
+//   NUM_OUTPUTS:         2
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module nios2_uc_mm_interconnect_0_rsp_demux
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [94-1    : 0]   sink_data, // ST_DATA_W=94
+    input  [4-1 : 0]   sink_channel, // ST_CHANNEL_W=4
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [94-1    : 0] src0_data, // ST_DATA_W=94
+    output reg [4-1 : 0] src0_channel, // ST_CHANNEL_W=4
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [94-1    : 0] src1_data, // ST_DATA_W=94
+    output reg [4-1 : 0] src1_channel, // ST_CHANNEL_W=4
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 2;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+
+    assign sink_ready = |(sink_channel & {{2{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+

nios2_uc/synthesis/submodules/nios2_uc_mm_interconnect_0_rsp_mux.sv

@@ -0,0 +1,385 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/19.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2018/11/07 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         nios2_uc_mm_interconnect_0_rsp_mux
+//   NUM_INPUTS:          4
+//   ARBITRATION_SHARES:  1 1 1 1
+//   ARBITRATION_SCHEME   "no-arb"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      60 (arbitration locking enabled)
+//   ST_DATA_W:           94
+//   ST_CHANNEL_W:        4
+// ------------------------------------------
+
+module nios2_uc_mm_interconnect_0_rsp_mux
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [94-1   : 0]  sink0_data,
+    input [4-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [94-1   : 0]  sink1_data,
+    input [4-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+    input                       sink2_valid,
+    input [94-1   : 0]  sink2_data,
+    input [4-1: 0]  sink2_channel,
+    input                       sink2_startofpacket,
+    input                       sink2_endofpacket,
+    output                      sink2_ready,
+
+    input                       sink3_valid,
+    input [94-1   : 0]  sink3_data,
+    input [4-1: 0]  sink3_channel,
+    input                       sink3_startofpacket,
+    input                       sink3_endofpacket,
+    output                      sink3_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [94-1    : 0] src_data,
+    output [4-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 94 + 4 + 2;
+    localparam NUM_INPUTS       = 4;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 94;
+    localparam ST_CHANNEL_W     = 4;
+    localparam PKT_TRANS_LOCK   = 60;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+    wire [PAYLOAD_W - 1 : 0] sink2_payload;
+    wire [PAYLOAD_W - 1 : 0] sink3_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+    assign valid[2] = sink2_valid;
+    assign valid[3] = sink3_valid;
+
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[60];
+      lock[1] = sink1_data[60];
+      lock[2] = sink2_data[60];
+      lock[3] = sink3_data[60];
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+    // 2      |      1       |  0
+    // 3      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
+    share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
+    share_3 & { SHARE_COUNTER_W {next_grant[3]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+    wire final_packet_2 = 1'b1;
+
+    wire final_packet_3 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_3,
+    final_packet_2,
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    assign request = valid;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("no-arb"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+    assign sink2_ready = src_ready && grant[2];
+    assign sink3_ready = src_ready && grant[3];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} } |
+      sink2_payload & {PAYLOAD_W {grant[2]} } |
+      sink3_payload & {PAYLOAD_W {grant[3]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+    assign sink2_payload = {sink2_channel,sink2_data,
+    sink2_startofpacket,sink2_endofpacket};
+    assign sink3_payload = {sink3_channel,sink3_data,
+    sink3_startofpacket,sink3_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+

nios2_uc/synthesis/submodules/nios2_uc_nios2.v

@@ -0,0 +1,67 @@
+// nios2_uc_nios2.v
+
+// This file was auto-generated from altera_nios2_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 18.1 646
+
+`timescale 1 ps / 1 ps
+module nios2_uc_nios2 (
+		input  wire        clk,                                 //                       clk.clk
+		input  wire        reset_n,                             //                     reset.reset_n
+		input  wire        reset_req,                           //                          .reset_req
+		output wire [19:0] d_address,                           //               data_master.address
+		output wire [3:0]  d_byteenable,                        //                          .byteenable
+		output wire        d_read,                              //                          .read
+		input  wire [31:0] d_readdata,                          //                          .readdata
+		input  wire        d_waitrequest,                       //                          .waitrequest
+		output wire        d_write,                             //                          .write
+		output wire [31:0] d_writedata,                         //                          .writedata
+		output wire        debug_mem_slave_debugaccess_to_roms, //                          .debugaccess
+		output wire [19:0] i_address,                           //        instruction_master.address
+		output wire        i_read,                              //                          .read
+		input  wire [31:0] i_readdata,                          //                          .readdata
+		input  wire        i_waitrequest,                       //                          .waitrequest
+		input  wire [31:0] irq,                                 //                       irq.irq
+		output wire        debug_reset_request,                 //       debug_reset_request.reset
+		input  wire [8:0]  debug_mem_slave_address,             //           debug_mem_slave.address
+		input  wire [3:0]  debug_mem_slave_byteenable,          //                          .byteenable
+		input  wire        debug_mem_slave_debugaccess,         //                          .debugaccess
+		input  wire        debug_mem_slave_read,                //                          .read
+		output wire [31:0] debug_mem_slave_readdata,            //                          .readdata
+		output wire        debug_mem_slave_waitrequest,         //                          .waitrequest
+		input  wire        debug_mem_slave_write,               //                          .write
+		input  wire [31:0] debug_mem_slave_writedata,           //                          .writedata
+		output wire        dummy_ci_port                        // custom_instruction_master.readra
+	);
+
+	nios2_uc_nios2_cpu cpu (
+		.clk                                 (clk),                                 //                       clk.clk
+		.reset_n                             (reset_n),                             //                     reset.reset_n
+		.reset_req                           (reset_req),                           //                          .reset_req
+		.d_address                           (d_address),                           //               data_master.address
+		.d_byteenable                        (d_byteenable),                        //                          .byteenable
+		.d_read                              (d_read),                              //                          .read
+		.d_readdata                          (d_readdata),                          //                          .readdata
+		.d_waitrequest                       (d_waitrequest),                       //                          .waitrequest
+		.d_write                             (d_write),                             //                          .write
+		.d_writedata                         (d_writedata),                         //                          .writedata
+		.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), //                          .debugaccess
+		.i_address                           (i_address),                           //        instruction_master.address
+		.i_read                              (i_read),                              //                          .read
+		.i_readdata                          (i_readdata),                          //                          .readdata
+		.i_waitrequest                       (i_waitrequest),                       //                          .waitrequest
+		.irq                                 (irq),                                 //                       irq.irq
+		.debug_reset_request                 (debug_reset_request),                 //       debug_reset_request.reset
+		.debug_mem_slave_address             (debug_mem_slave_address),             //           debug_mem_slave.address
+		.debug_mem_slave_byteenable          (debug_mem_slave_byteenable),          //                          .byteenable
+		.debug_mem_slave_debugaccess         (debug_mem_slave_debugaccess),         //                          .debugaccess
+		.debug_mem_slave_read                (debug_mem_slave_read),                //                          .read
+		.debug_mem_slave_readdata            (debug_mem_slave_readdata),            //                          .readdata
+		.debug_mem_slave_waitrequest         (debug_mem_slave_waitrequest),         //                          .waitrequest
+		.debug_mem_slave_write               (debug_mem_slave_write),               //                          .write
+		.debug_mem_slave_writedata           (debug_mem_slave_writedata),           //                          .writedata
+		.dummy_ci_port                       (dummy_ci_port)                        // custom_instruction_master.readra
+	);
+
+endmodule

nios2_uc/synthesis/submodules/nios2_uc_nios2_cpu.sdc

@@ -0,0 +1,53 @@
+# Legal Notice: (C)2020 Altera Corporation. All rights reserved.  Your
+# use of Altera Corporation's design tools, logic functions and other
+# software and tools, and its AMPP partner logic functions, and any
+# output files any of the foregoing (including device programming or
+# simulation files), and any associated documentation or information are
+# expressly subject to the terms and conditions of the Altera Program
+# License Subscription Agreement or other applicable license agreement,
+# including, without limitation, that your use is for the sole purpose
+# of programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors.  Please refer to the applicable
+# agreement for further details.
+
+#**************************************************************
+# Timequest JTAG clock definition
+#   Uncommenting the following lines will define the JTAG
+#   clock in TimeQuest Timing Analyzer
+#**************************************************************
+
+#create_clock -period 10MHz {altera_reserved_tck}
+#set_clock_groups -asynchronous -group {altera_reserved_tck}
+
+#**************************************************************
+# Set TCL Path Variables 
+#**************************************************************
+
+set 	nios2_uc_nios2_cpu 	nios2_uc_nios2_cpu:*
+set 	nios2_uc_nios2_cpu_oci 	nios2_uc_nios2_cpu_nios2_oci:the_nios2_uc_nios2_cpu_nios2_oci
+set 	nios2_uc_nios2_cpu_oci_break 	nios2_uc_nios2_cpu_nios2_oci_break:the_nios2_uc_nios2_cpu_nios2_oci_break
+set 	nios2_uc_nios2_cpu_ocimem 	nios2_uc_nios2_cpu_nios2_ocimem:the_nios2_uc_nios2_cpu_nios2_ocimem
+set 	nios2_uc_nios2_cpu_oci_debug 	nios2_uc_nios2_cpu_nios2_oci_debug:the_nios2_uc_nios2_cpu_nios2_oci_debug
+set 	nios2_uc_nios2_cpu_wrapper 	nios2_uc_nios2_cpu_debug_slave_wrapper:the_nios2_uc_nios2_cpu_debug_slave_wrapper
+set 	nios2_uc_nios2_cpu_jtag_tck 	nios2_uc_nios2_cpu_debug_slave_tck:the_nios2_uc_nios2_cpu_debug_slave_tck
+set 	nios2_uc_nios2_cpu_jtag_sysclk 	nios2_uc_nios2_cpu_debug_slave_sysclk:the_nios2_uc_nios2_cpu_debug_slave_sysclk
+set 	nios2_uc_nios2_cpu_oci_path 	 [format "%s|%s" $nios2_uc_nios2_cpu $nios2_uc_nios2_cpu_oci]
+set 	nios2_uc_nios2_cpu_oci_break_path 	 [format "%s|%s" $nios2_uc_nios2_cpu_oci_path $nios2_uc_nios2_cpu_oci_break]
+set 	nios2_uc_nios2_cpu_ocimem_path 	 [format "%s|%s" $nios2_uc_nios2_cpu_oci_path $nios2_uc_nios2_cpu_ocimem]
+set 	nios2_uc_nios2_cpu_oci_debug_path 	 [format "%s|%s" $nios2_uc_nios2_cpu_oci_path $nios2_uc_nios2_cpu_oci_debug]
+set 	nios2_uc_nios2_cpu_jtag_tck_path 	 [format "%s|%s|%s" $nios2_uc_nios2_cpu_oci_path $nios2_uc_nios2_cpu_wrapper $nios2_uc_nios2_cpu_jtag_tck]
+set 	nios2_uc_nios2_cpu_jtag_sysclk_path 	 [format "%s|%s|%s" $nios2_uc_nios2_cpu_oci_path $nios2_uc_nios2_cpu_wrapper $nios2_uc_nios2_cpu_jtag_sysclk]
+set 	nios2_uc_nios2_cpu_jtag_sr 	 [format "%s|*sr" $nios2_uc_nios2_cpu_jtag_tck_path]
+
+#**************************************************************
+# Set False Paths
+#**************************************************************
+
+set_false_path -from [get_keepers *$nios2_uc_nios2_cpu_oci_break_path|break_readreg*] -to [get_keepers *$nios2_uc_nios2_cpu_jtag_sr*]
+set_false_path -from [get_keepers *$nios2_uc_nios2_cpu_oci_debug_path|*resetlatch]     -to [get_keepers *$nios2_uc_nios2_cpu_jtag_sr[33]]
+set_false_path -from [get_keepers *$nios2_uc_nios2_cpu_oci_debug_path|monitor_ready]  -to [get_keepers *$nios2_uc_nios2_cpu_jtag_sr[0]]
+set_false_path -from [get_keepers *$nios2_uc_nios2_cpu_oci_debug_path|monitor_error]  -to [get_keepers *$nios2_uc_nios2_cpu_jtag_sr[34]]
+set_false_path -from [get_keepers *$nios2_uc_nios2_cpu_ocimem_path|*MonDReg*] -to [get_keepers *$nios2_uc_nios2_cpu_jtag_sr*]
+set_false_path -from *$nios2_uc_nios2_cpu_jtag_sr*    -to *$nios2_uc_nios2_cpu_jtag_sysclk_path|*jdo*
+set_false_path -from sld_hub:*|irf_reg* -to *$nios2_uc_nios2_cpu_jtag_sysclk_path|ir*
+set_false_path -from sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1] -to *$nios2_uc_nios2_cpu_oci_debug_path|monitor_go

nios2_uc/synthesis/submodules/nios2_uc_nios2_cpu.v

@@ -0,0 +1,5658 @@
+//Legal Notice: (C)2020 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_register_bank_a_module (
+                                                   // inputs:
+                                                    clock,
+                                                    data,
+                                                    rdaddress,
+                                                    wraddress,
+                                                    wren,
+
+                                                   // outputs:
+                                                    q
+                                                 )
+;
+
+  parameter lpm_file = "UNUSED";
+
+
+  output  [ 31: 0] q;
+  input            clock;
+  input   [ 31: 0] data;
+  input   [  4: 0] rdaddress;
+  input   [  4: 0] wraddress;
+  input            wren;
+
+
+wire    [ 31: 0] q;
+wire    [ 31: 0] ram_data;
+wire    [ 31: 0] ram_q;
+  assign q = ram_q;
+  assign ram_data = data;
+  altsyncram the_altsyncram
+    (
+      .address_a (wraddress),
+      .address_b (rdaddress),
+      .clock0 (clock),
+      .data_a (ram_data),
+      .q_b (ram_q),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK0",
+           the_altsyncram.init_file = lpm_file,
+           the_altsyncram.maximum_depth = 0,
+           the_altsyncram.numwords_a = 32,
+           the_altsyncram.numwords_b = 32,
+           the_altsyncram.operation_mode = "DUAL_PORT",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.rdcontrol_reg_b = "CLOCK0",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.width_a = 32,
+           the_altsyncram.width_b = 32,
+           the_altsyncram.widthad_a = 5,
+           the_altsyncram.widthad_b = 5;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_register_bank_b_module (
+                                                   // inputs:
+                                                    clock,
+                                                    data,
+                                                    rdaddress,
+                                                    wraddress,
+                                                    wren,
+
+                                                   // outputs:
+                                                    q
+                                                 )
+;
+
+  parameter lpm_file = "UNUSED";
+
+
+  output  [ 31: 0] q;
+  input            clock;
+  input   [ 31: 0] data;
+  input   [  4: 0] rdaddress;
+  input   [  4: 0] wraddress;
+  input            wren;
+
+
+wire    [ 31: 0] q;
+wire    [ 31: 0] ram_data;
+wire    [ 31: 0] ram_q;
+  assign q = ram_q;
+  assign ram_data = data;
+  altsyncram the_altsyncram
+    (
+      .address_a (wraddress),
+      .address_b (rdaddress),
+      .clock0 (clock),
+      .data_a (ram_data),
+      .q_b (ram_q),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.address_reg_b = "CLOCK0",
+           the_altsyncram.init_file = lpm_file,
+           the_altsyncram.maximum_depth = 0,
+           the_altsyncram.numwords_a = 32,
+           the_altsyncram.numwords_b = 32,
+           the_altsyncram.operation_mode = "DUAL_PORT",
+           the_altsyncram.outdata_reg_b = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.rdcontrol_reg_b = "CLOCK0",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.width_a = 32,
+           the_altsyncram.width_b = 32,
+           the_altsyncram.widthad_a = 5,
+           the_altsyncram.widthad_b = 5;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_oci_debug (
+                                            // inputs:
+                                             clk,
+                                             dbrk_break,
+                                             debugreq,
+                                             hbreak_enabled,
+                                             jdo,
+                                             jrst_n,
+                                             ocireg_ers,
+                                             ocireg_mrs,
+                                             reset,
+                                             st_ready_test_idle,
+                                             take_action_ocimem_a,
+                                             take_action_ocireg,
+                                             xbrk_break,
+
+                                            // outputs:
+                                             debugack,
+                                             monitor_error,
+                                             monitor_go,
+                                             monitor_ready,
+                                             oci_hbreak_req,
+                                             resetlatch,
+                                             resetrequest
+                                          )
+;
+
+  output           debugack;
+  output           monitor_error;
+  output           monitor_go;
+  output           monitor_ready;
+  output           oci_hbreak_req;
+  output           resetlatch;
+  output           resetrequest;
+  input            clk;
+  input            dbrk_break;
+  input            debugreq;
+  input            hbreak_enabled;
+  input   [ 37: 0] jdo;
+  input            jrst_n;
+  input            ocireg_ers;
+  input            ocireg_mrs;
+  input            reset;
+  input            st_ready_test_idle;
+  input            take_action_ocimem_a;
+  input            take_action_ocireg;
+  input            xbrk_break;
+
+
+reg              break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+wire             debugack;
+reg              jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg              monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101"  */;
+reg              monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101"  */;
+reg              monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101"  */;
+wire             oci_hbreak_req;
+wire             reset_sync;
+reg              resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg              resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+wire             unxcomplemented_resetxx0;
+  assign unxcomplemented_resetxx0 = jrst_n;
+  altera_std_synchronizer the_altera_std_synchronizer
+    (
+      .clk (clk),
+      .din (reset),
+      .dout (reset_sync),
+      .reset_n (unxcomplemented_resetxx0)
+    );
+
+  defparam the_altera_std_synchronizer.depth = 2;
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          resetrequest <= 1'b0;
+          break_on_reset <= 1'b0;
+          jtag_break <= 1'b0;
+        end
+      else if (take_action_ocimem_a)
+        begin
+          resetrequest <= jdo[22];
+          jtag_break <= jdo[21]     ? 1 
+                    : jdo[20]  ? 0 
+                    : jtag_break;
+
+          break_on_reset <= jdo[19]     ? 1
+                    : jdo[18]  ? 0
+                    :  break_on_reset;
+
+          resetlatch <= jdo[24] ? 0 : resetlatch;
+        end
+      else if (reset_sync)
+        begin
+          jtag_break <= break_on_reset;
+          resetlatch <= 1;
+        end
+      else if (debugreq & ~debugack & break_on_reset)
+          jtag_break <= 1'b1;
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          monitor_ready <= 1'b0;
+          monitor_error <= 1'b0;
+          monitor_go <= 1'b0;
+        end
+      else 
+        begin
+          if (take_action_ocimem_a && jdo[25])
+              monitor_ready <= 1'b0;
+          else if (take_action_ocireg && ocireg_mrs)
+              monitor_ready <= 1'b1;
+          if (take_action_ocimem_a && jdo[25])
+              monitor_error <= 1'b0;
+          else if (take_action_ocireg && ocireg_ers)
+              monitor_error <= 1'b1;
+          if (take_action_ocimem_a && jdo[23])
+              monitor_go <= 1'b1;
+          else if (st_ready_test_idle)
+              monitor_go <= 1'b0;
+        end
+    end
+
+
+  assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
+  assign debugack = ~hbreak_enabled;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_oci_break (
+                                            // inputs:
+                                             clk,
+                                             dbrk_break,
+                                             dbrk_goto0,
+                                             dbrk_goto1,
+                                             jdo,
+                                             jrst_n,
+                                             take_action_break_a,
+                                             take_action_break_b,
+                                             take_action_break_c,
+                                             take_no_action_break_a,
+                                             take_no_action_break_b,
+                                             take_no_action_break_c,
+                                             xbrk_goto0,
+                                             xbrk_goto1,
+
+                                            // outputs:
+                                             break_readreg,
+                                             dbrk_hit0_latch,
+                                             dbrk_hit1_latch,
+                                             dbrk_hit2_latch,
+                                             dbrk_hit3_latch,
+                                             trigbrktype,
+                                             trigger_state_0,
+                                             trigger_state_1,
+                                             xbrk_ctrl0,
+                                             xbrk_ctrl1,
+                                             xbrk_ctrl2,
+                                             xbrk_ctrl3
+                                          )
+;
+
+  output  [ 31: 0] break_readreg;
+  output           dbrk_hit0_latch;
+  output           dbrk_hit1_latch;
+  output           dbrk_hit2_latch;
+  output           dbrk_hit3_latch;
+  output           trigbrktype;
+  output           trigger_state_0;
+  output           trigger_state_1;
+  output  [  7: 0] xbrk_ctrl0;
+  output  [  7: 0] xbrk_ctrl1;
+  output  [  7: 0] xbrk_ctrl2;
+  output  [  7: 0] xbrk_ctrl3;
+  input            clk;
+  input            dbrk_break;
+  input            dbrk_goto0;
+  input            dbrk_goto1;
+  input   [ 37: 0] jdo;
+  input            jrst_n;
+  input            take_action_break_a;
+  input            take_action_break_b;
+  input            take_action_break_c;
+  input            take_no_action_break_a;
+  input            take_no_action_break_b;
+  input            take_no_action_break_c;
+  input            xbrk_goto0;
+  input            xbrk_goto1;
+
+
+wire    [  3: 0] break_a_wpr;
+wire    [  1: 0] break_a_wpr_high_bits;
+wire    [  1: 0] break_a_wpr_low_bits;
+wire    [  1: 0] break_b_rr;
+wire    [  1: 0] break_c_rr;
+reg     [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+wire             dbrk0_high_value;
+wire             dbrk0_low_value;
+wire             dbrk1_high_value;
+wire             dbrk1_low_value;
+wire             dbrk2_high_value;
+wire             dbrk2_low_value;
+wire             dbrk3_high_value;
+wire             dbrk3_low_value;
+wire             dbrk_hit0_latch;
+wire             dbrk_hit1_latch;
+wire             dbrk_hit2_latch;
+wire             dbrk_hit3_latch;
+wire             take_action_any_break;
+reg              trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg              trigger_state;
+wire             trigger_state_0;
+wire             trigger_state_1;
+wire    [ 31: 0] xbrk0_value;
+wire    [ 31: 0] xbrk1_value;
+wire    [ 31: 0] xbrk2_value;
+wire    [ 31: 0] xbrk3_value;
+reg     [  7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg     [  7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg     [  7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg     [  7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+  assign break_a_wpr = jdo[35 : 32];
+  assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
+  assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
+  assign break_b_rr = jdo[33 : 32];
+  assign break_c_rr = jdo[33 : 32];
+  assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          xbrk_ctrl0 <= 0;
+          xbrk_ctrl1 <= 0;
+          xbrk_ctrl2 <= 0;
+          xbrk_ctrl3 <= 0;
+          trigbrktype <= 0;
+        end
+      else 
+        begin
+          if (take_action_any_break)
+              trigbrktype <= 0;
+          else if (dbrk_break)
+              trigbrktype <= 1;
+          if (take_action_break_b)
+            begin
+              if ((break_b_rr == 2'b00) && (0 >= 1))
+                begin
+                  xbrk_ctrl0[0] <= jdo[27];
+                  xbrk_ctrl0[1] <= jdo[28];
+                  xbrk_ctrl0[2] <= jdo[29];
+                  xbrk_ctrl0[3] <= jdo[30];
+                  xbrk_ctrl0[4] <= jdo[21];
+                  xbrk_ctrl0[5] <= jdo[20];
+                  xbrk_ctrl0[6] <= jdo[19];
+                  xbrk_ctrl0[7] <= jdo[18];
+                end
+              if ((break_b_rr == 2'b01) && (0 >= 2))
+                begin
+                  xbrk_ctrl1[0] <= jdo[27];
+                  xbrk_ctrl1[1] <= jdo[28];
+                  xbrk_ctrl1[2] <= jdo[29];
+                  xbrk_ctrl1[3] <= jdo[30];
+                  xbrk_ctrl1[4] <= jdo[21];
+                  xbrk_ctrl1[5] <= jdo[20];
+                  xbrk_ctrl1[6] <= jdo[19];
+                  xbrk_ctrl1[7] <= jdo[18];
+                end
+              if ((break_b_rr == 2'b10) && (0 >= 3))
+                begin
+                  xbrk_ctrl2[0] <= jdo[27];
+                  xbrk_ctrl2[1] <= jdo[28];
+                  xbrk_ctrl2[2] <= jdo[29];
+                  xbrk_ctrl2[3] <= jdo[30];
+                  xbrk_ctrl2[4] <= jdo[21];
+                  xbrk_ctrl2[5] <= jdo[20];
+                  xbrk_ctrl2[6] <= jdo[19];
+                  xbrk_ctrl2[7] <= jdo[18];
+                end
+              if ((break_b_rr == 2'b11) && (0 >= 4))
+                begin
+                  xbrk_ctrl3[0] <= jdo[27];
+                  xbrk_ctrl3[1] <= jdo[28];
+                  xbrk_ctrl3[2] <= jdo[29];
+                  xbrk_ctrl3[3] <= jdo[30];
+                  xbrk_ctrl3[4] <= jdo[21];
+                  xbrk_ctrl3[5] <= jdo[20];
+                  xbrk_ctrl3[6] <= jdo[19];
+                  xbrk_ctrl3[7] <= jdo[18];
+                end
+            end
+        end
+    end
+
+
+  assign dbrk_hit0_latch = 1'b0;
+  assign dbrk0_low_value = 0;
+  assign dbrk0_high_value = 0;
+  assign dbrk_hit1_latch = 1'b0;
+  assign dbrk1_low_value = 0;
+  assign dbrk1_high_value = 0;
+  assign dbrk_hit2_latch = 1'b0;
+  assign dbrk2_low_value = 0;
+  assign dbrk2_high_value = 0;
+  assign dbrk_hit3_latch = 1'b0;
+  assign dbrk3_low_value = 0;
+  assign dbrk3_high_value = 0;
+  assign xbrk0_value = 32'b0;
+  assign xbrk1_value = 32'b0;
+  assign xbrk2_value = 32'b0;
+  assign xbrk3_value = 32'b0;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          break_readreg <= 32'b0;
+      else if (take_action_any_break)
+          break_readreg <= jdo[31 : 0];
+      else if (take_no_action_break_a)
+          case (break_a_wpr_high_bits)
+          
+              2'd0: begin
+                  case (break_a_wpr_low_bits) // synthesis full_case
+                  
+                      2'd0: begin
+                          break_readreg <= xbrk0_value;
+                      end // 2'd0 
+                  
+                      2'd1: begin
+                          break_readreg <= xbrk1_value;
+                      end // 2'd1 
+                  
+                      2'd2: begin
+                          break_readreg <= xbrk2_value;
+                      end // 2'd2 
+                  
+                      2'd3: begin
+                          break_readreg <= xbrk3_value;
+                      end // 2'd3 
+                  
+                  endcase // break_a_wpr_low_bits
+              end // 2'd0 
+          
+              2'd1: begin
+                  break_readreg <= 32'b0;
+              end // 2'd1 
+          
+              2'd2: begin
+                  case (break_a_wpr_low_bits) // synthesis full_case
+                  
+                      2'd0: begin
+                          break_readreg <= dbrk0_low_value;
+                      end // 2'd0 
+                  
+                      2'd1: begin
+                          break_readreg <= dbrk1_low_value;
+                      end // 2'd1 
+                  
+                      2'd2: begin
+                          break_readreg <= dbrk2_low_value;
+                      end // 2'd2 
+                  
+                      2'd3: begin
+                          break_readreg <= dbrk3_low_value;
+                      end // 2'd3 
+                  
+                  endcase // break_a_wpr_low_bits
+              end // 2'd2 
+          
+              2'd3: begin
+                  case (break_a_wpr_low_bits) // synthesis full_case
+                  
+                      2'd0: begin
+                          break_readreg <= dbrk0_high_value;
+                      end // 2'd0 
+                  
+                      2'd1: begin
+                          break_readreg <= dbrk1_high_value;
+                      end // 2'd1 
+                  
+                      2'd2: begin
+                          break_readreg <= dbrk2_high_value;
+                      end // 2'd2 
+                  
+                      2'd3: begin
+                          break_readreg <= dbrk3_high_value;
+                      end // 2'd3 
+                  
+                  endcase // break_a_wpr_low_bits
+              end // 2'd3 
+          
+          endcase // break_a_wpr_high_bits
+      else if (take_no_action_break_b)
+          break_readreg <= jdo[31 : 0];
+      else if (take_no_action_break_c)
+          break_readreg <= jdo[31 : 0];
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          trigger_state <= 0;
+      else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
+          trigger_state <= 0;
+      else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
+          trigger_state <= -1;
+    end
+
+
+  assign trigger_state_0 = ~trigger_state;
+  assign trigger_state_1 = trigger_state;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_oci_xbrk (
+                                           // inputs:
+                                            D_valid,
+                                            E_valid,
+                                            F_pc,
+                                            clk,
+                                            reset_n,
+                                            trigger_state_0,
+                                            trigger_state_1,
+                                            xbrk_ctrl0,
+                                            xbrk_ctrl1,
+                                            xbrk_ctrl2,
+                                            xbrk_ctrl3,
+
+                                           // outputs:
+                                            xbrk_break,
+                                            xbrk_goto0,
+                                            xbrk_goto1,
+                                            xbrk_traceoff,
+                                            xbrk_traceon,
+                                            xbrk_trigout
+                                         )
+;
+
+  output           xbrk_break;
+  output           xbrk_goto0;
+  output           xbrk_goto1;
+  output           xbrk_traceoff;
+  output           xbrk_traceon;
+  output           xbrk_trigout;
+  input            D_valid;
+  input            E_valid;
+  input   [ 17: 0] F_pc;
+  input            clk;
+  input            reset_n;
+  input            trigger_state_0;
+  input            trigger_state_1;
+  input   [  7: 0] xbrk_ctrl0;
+  input   [  7: 0] xbrk_ctrl1;
+  input   [  7: 0] xbrk_ctrl2;
+  input   [  7: 0] xbrk_ctrl3;
+
+
+wire             D_cpu_addr_en;
+wire             E_cpu_addr_en;
+reg              E_xbrk_goto0;
+reg              E_xbrk_goto1;
+reg              E_xbrk_traceoff;
+reg              E_xbrk_traceon;
+reg              E_xbrk_trigout;
+wire    [ 19: 0] cpu_i_address;
+wire             xbrk0_armed;
+wire             xbrk0_break_hit;
+wire             xbrk0_goto0_hit;
+wire             xbrk0_goto1_hit;
+wire             xbrk0_toff_hit;
+wire             xbrk0_ton_hit;
+wire             xbrk0_tout_hit;
+wire             xbrk1_armed;
+wire             xbrk1_break_hit;
+wire             xbrk1_goto0_hit;
+wire             xbrk1_goto1_hit;
+wire             xbrk1_toff_hit;
+wire             xbrk1_ton_hit;
+wire             xbrk1_tout_hit;
+wire             xbrk2_armed;
+wire             xbrk2_break_hit;
+wire             xbrk2_goto0_hit;
+wire             xbrk2_goto1_hit;
+wire             xbrk2_toff_hit;
+wire             xbrk2_ton_hit;
+wire             xbrk2_tout_hit;
+wire             xbrk3_armed;
+wire             xbrk3_break_hit;
+wire             xbrk3_goto0_hit;
+wire             xbrk3_goto1_hit;
+wire             xbrk3_toff_hit;
+wire             xbrk3_ton_hit;
+wire             xbrk3_tout_hit;
+reg              xbrk_break;
+wire             xbrk_break_hit;
+wire             xbrk_goto0;
+wire             xbrk_goto0_hit;
+wire             xbrk_goto1;
+wire             xbrk_goto1_hit;
+wire             xbrk_toff_hit;
+wire             xbrk_ton_hit;
+wire             xbrk_tout_hit;
+wire             xbrk_traceoff;
+wire             xbrk_traceon;
+wire             xbrk_trigout;
+  assign cpu_i_address = {F_pc, 2'b00};
+  assign D_cpu_addr_en = D_valid;
+  assign E_cpu_addr_en = E_valid;
+  assign xbrk0_break_hit = 0;
+  assign xbrk0_ton_hit = 0;
+  assign xbrk0_toff_hit = 0;
+  assign xbrk0_tout_hit = 0;
+  assign xbrk0_goto0_hit = 0;
+  assign xbrk0_goto1_hit = 0;
+  assign xbrk1_break_hit = 0;
+  assign xbrk1_ton_hit = 0;
+  assign xbrk1_toff_hit = 0;
+  assign xbrk1_tout_hit = 0;
+  assign xbrk1_goto0_hit = 0;
+  assign xbrk1_goto1_hit = 0;
+  assign xbrk2_break_hit = 0;
+  assign xbrk2_ton_hit = 0;
+  assign xbrk2_toff_hit = 0;
+  assign xbrk2_tout_hit = 0;
+  assign xbrk2_goto0_hit = 0;
+  assign xbrk2_goto1_hit = 0;
+  assign xbrk3_break_hit = 0;
+  assign xbrk3_ton_hit = 0;
+  assign xbrk3_toff_hit = 0;
+  assign xbrk3_tout_hit = 0;
+  assign xbrk3_goto0_hit = 0;
+  assign xbrk3_goto1_hit = 0;
+  assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
+  assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
+  assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
+  assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
+  assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
+  assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          xbrk_break <= 0;
+      else if (E_cpu_addr_en)
+          xbrk_break <= xbrk_break_hit;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_xbrk_traceon <= 0;
+      else if (E_cpu_addr_en)
+          E_xbrk_traceon <= xbrk_ton_hit;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_xbrk_traceoff <= 0;
+      else if (E_cpu_addr_en)
+          E_xbrk_traceoff <= xbrk_toff_hit;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_xbrk_trigout <= 0;
+      else if (E_cpu_addr_en)
+          E_xbrk_trigout <= xbrk_tout_hit;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_xbrk_goto0 <= 0;
+      else if (E_cpu_addr_en)
+          E_xbrk_goto0 <= xbrk_goto0_hit;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_xbrk_goto1 <= 0;
+      else if (E_cpu_addr_en)
+          E_xbrk_goto1 <= xbrk_goto1_hit;
+    end
+
+
+  assign xbrk_traceon = 1'b0;
+  assign xbrk_traceoff = 1'b0;
+  assign xbrk_trigout = 1'b0;
+  assign xbrk_goto0 = 1'b0;
+  assign xbrk_goto1 = 1'b0;
+  assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
+    (xbrk_ctrl0[5] & trigger_state_1);
+
+  assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
+    (xbrk_ctrl1[5] & trigger_state_1);
+
+  assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
+    (xbrk_ctrl2[5] & trigger_state_1);
+
+  assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
+    (xbrk_ctrl3[5] & trigger_state_1);
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_oci_dbrk (
+                                           // inputs:
+                                            E_st_data,
+                                            av_ld_data_aligned_filtered,
+                                            clk,
+                                            d_address,
+                                            d_read,
+                                            d_waitrequest,
+                                            d_write,
+                                            debugack,
+                                            reset_n,
+
+                                           // outputs:
+                                            cpu_d_address,
+                                            cpu_d_read,
+                                            cpu_d_readdata,
+                                            cpu_d_wait,
+                                            cpu_d_write,
+                                            cpu_d_writedata,
+                                            dbrk_break,
+                                            dbrk_goto0,
+                                            dbrk_goto1,
+                                            dbrk_traceme,
+                                            dbrk_traceoff,
+                                            dbrk_traceon,
+                                            dbrk_trigout
+                                         )
+;
+
+  output  [ 19: 0] cpu_d_address;
+  output           cpu_d_read;
+  output  [ 31: 0] cpu_d_readdata;
+  output           cpu_d_wait;
+  output           cpu_d_write;
+  output  [ 31: 0] cpu_d_writedata;
+  output           dbrk_break;
+  output           dbrk_goto0;
+  output           dbrk_goto1;
+  output           dbrk_traceme;
+  output           dbrk_traceoff;
+  output           dbrk_traceon;
+  output           dbrk_trigout;
+  input   [ 31: 0] E_st_data;
+  input   [ 31: 0] av_ld_data_aligned_filtered;
+  input            clk;
+  input   [ 19: 0] d_address;
+  input            d_read;
+  input            d_waitrequest;
+  input            d_write;
+  input            debugack;
+  input            reset_n;
+
+
+wire    [ 19: 0] cpu_d_address;
+wire             cpu_d_read;
+wire    [ 31: 0] cpu_d_readdata;
+wire             cpu_d_wait;
+wire             cpu_d_write;
+wire    [ 31: 0] cpu_d_writedata;
+wire             dbrk0_armed;
+wire             dbrk0_break_pulse;
+wire             dbrk0_goto0;
+wire             dbrk0_goto1;
+wire             dbrk0_traceme;
+wire             dbrk0_traceoff;
+wire             dbrk0_traceon;
+wire             dbrk0_trigout;
+wire             dbrk1_armed;
+wire             dbrk1_break_pulse;
+wire             dbrk1_goto0;
+wire             dbrk1_goto1;
+wire             dbrk1_traceme;
+wire             dbrk1_traceoff;
+wire             dbrk1_traceon;
+wire             dbrk1_trigout;
+wire             dbrk2_armed;
+wire             dbrk2_break_pulse;
+wire             dbrk2_goto0;
+wire             dbrk2_goto1;
+wire             dbrk2_traceme;
+wire             dbrk2_traceoff;
+wire             dbrk2_traceon;
+wire             dbrk2_trigout;
+wire             dbrk3_armed;
+wire             dbrk3_break_pulse;
+wire             dbrk3_goto0;
+wire             dbrk3_goto1;
+wire             dbrk3_traceme;
+wire             dbrk3_traceoff;
+wire             dbrk3_traceon;
+wire             dbrk3_trigout;
+reg              dbrk_break;
+reg              dbrk_break_pulse;
+wire    [ 31: 0] dbrk_data;
+reg              dbrk_goto0;
+reg              dbrk_goto1;
+reg              dbrk_traceme;
+reg              dbrk_traceoff;
+reg              dbrk_traceon;
+reg              dbrk_trigout;
+  assign cpu_d_address = d_address;
+  assign cpu_d_readdata = av_ld_data_aligned_filtered;
+  assign cpu_d_read = d_read;
+  assign cpu_d_writedata = E_st_data;
+  assign cpu_d_write = d_write;
+  assign cpu_d_wait = d_waitrequest;
+  assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          dbrk_break <= 0;
+      else 
+        dbrk_break <= dbrk_break   ? ~debugack   
+                : dbrk_break_pulse;
+
+    end
+
+
+  assign dbrk0_armed = 1'b0;
+  assign dbrk0_trigout = 1'b0;
+  assign dbrk0_break_pulse = 1'b0;
+  assign dbrk0_traceoff = 1'b0;
+  assign dbrk0_traceon = 1'b0;
+  assign dbrk0_traceme = 1'b0;
+  assign dbrk0_goto0 = 1'b0;
+  assign dbrk0_goto1 = 1'b0;
+  assign dbrk1_armed = 1'b0;
+  assign dbrk1_trigout = 1'b0;
+  assign dbrk1_break_pulse = 1'b0;
+  assign dbrk1_traceoff = 1'b0;
+  assign dbrk1_traceon = 1'b0;
+  assign dbrk1_traceme = 1'b0;
+  assign dbrk1_goto0 = 1'b0;
+  assign dbrk1_goto1 = 1'b0;
+  assign dbrk2_armed = 1'b0;
+  assign dbrk2_trigout = 1'b0;
+  assign dbrk2_break_pulse = 1'b0;
+  assign dbrk2_traceoff = 1'b0;
+  assign dbrk2_traceon = 1'b0;
+  assign dbrk2_traceme = 1'b0;
+  assign dbrk2_goto0 = 1'b0;
+  assign dbrk2_goto1 = 1'b0;
+  assign dbrk3_armed = 1'b0;
+  assign dbrk3_trigout = 1'b0;
+  assign dbrk3_break_pulse = 1'b0;
+  assign dbrk3_traceoff = 1'b0;
+  assign dbrk3_traceon = 1'b0;
+  assign dbrk3_traceme = 1'b0;
+  assign dbrk3_goto0 = 1'b0;
+  assign dbrk3_goto1 = 1'b0;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+          dbrk_trigout <= 0;
+          dbrk_break_pulse <= 0;
+          dbrk_traceoff <= 0;
+          dbrk_traceon <= 0;
+          dbrk_traceme <= 0;
+          dbrk_goto0 <= 0;
+          dbrk_goto1 <= 0;
+        end
+      else 
+        begin
+          dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
+          dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
+          dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
+          dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
+          dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
+          dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
+          dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
+        end
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_oci_itrace (
+                                             // inputs:
+                                              clk,
+                                              dbrk_traceoff,
+                                              dbrk_traceon,
+                                              jdo,
+                                              jrst_n,
+                                              take_action_tracectrl,
+                                              xbrk_traceoff,
+                                              xbrk_traceon,
+                                              xbrk_wrap_traceoff,
+
+                                             // outputs:
+                                              itm,
+                                              trc_ctrl,
+                                              trc_on
+                                           )
+;
+
+  output  [ 35: 0] itm;
+  output  [ 15: 0] trc_ctrl;
+  output           trc_on;
+  input            clk;
+  input            dbrk_traceoff;
+  input            dbrk_traceon;
+  input   [ 15: 0] jdo;
+  input            jrst_n;
+  input            take_action_tracectrl;
+  input            xbrk_traceoff;
+  input            xbrk_traceon;
+  input            xbrk_wrap_traceoff;
+
+
+wire             advanced_exc_occured;
+wire             curr_pid;
+wire    [  1: 0] dct_code;
+wire             dct_is_taken;
+wire    [ 31: 0] eic_addr;
+wire    [ 31: 0] exc_addr;
+wire             instr_retired;
+wire             is_cond_dct;
+wire             is_dct;
+wire             is_exception_no_break;
+wire             is_external_interrupt;
+wire             is_fast_tlb_miss_exception;
+wire             is_idct;
+wire    [ 35: 0] itm;
+wire             not_in_debug_mode;
+wire             record_dct_outcome_in_sync;
+wire             record_itrace;
+wire    [ 31: 0] retired_pcb;
+wire    [  1: 0] sync_code;
+wire    [  6: 0] sync_interval;
+wire    [  6: 0] sync_timer;
+wire    [  6: 0] sync_timer_next;
+wire             sync_timer_reached_zero;
+wire    [ 15: 0] trc_ctrl;
+reg     [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire             trc_on;
+  assign is_cond_dct = 1'b0;
+  assign is_dct = 1'b0;
+  assign dct_is_taken = 1'b0;
+  assign is_idct = 1'b0;
+  assign retired_pcb = 32'b0;
+  assign not_in_debug_mode = 1'b0;
+  assign instr_retired = 1'b0;
+  assign advanced_exc_occured = 1'b0;
+  assign is_exception_no_break = 1'b0;
+  assign is_external_interrupt = 1'b0;
+  assign is_fast_tlb_miss_exception = 1'b0;
+  assign curr_pid = 1'b0;
+  assign exc_addr = 32'b0;
+  assign eic_addr = 32'b0;
+  assign sync_code = trc_ctrl[3 : 2];
+  assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
+  assign sync_timer_reached_zero = sync_timer == 0;
+  assign record_dct_outcome_in_sync = dct_is_taken & sync_timer_reached_zero;
+  assign sync_timer_next = sync_timer_reached_zero ? sync_timer : (sync_timer - 1);
+  assign record_itrace = trc_on & trc_ctrl[4];
+  assign dct_code = {is_cond_dct, dct_is_taken};
+  assign itm = 36'd0;
+  assign sync_timer = 7'd1;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          trc_ctrl_reg[0] <= 1'b0;
+          trc_ctrl_reg[1] <= 1'b0;
+          trc_ctrl_reg[3 : 2] <= 2'b00;
+          trc_ctrl_reg[4] <= 1'b0;
+          trc_ctrl_reg[7 : 5] <= 3'b000;
+          trc_ctrl_reg[8] <= 0;
+          trc_ctrl_reg[9] <= 1'b0;
+          trc_ctrl_reg[10] <= 1'b0;
+        end
+      else if (take_action_tracectrl)
+        begin
+          trc_ctrl_reg[0] <= jdo[5];
+          trc_ctrl_reg[1] <= jdo[6];
+          trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
+          trc_ctrl_reg[4] <= jdo[9];
+          trc_ctrl_reg[9] <= jdo[14];
+          trc_ctrl_reg[10] <= jdo[2];
+          trc_ctrl_reg[7 : 5] <= 3'b000;
+          trc_ctrl_reg[8] <= 1'b0;
+        end
+      else if (xbrk_wrap_traceoff)
+        begin
+          trc_ctrl_reg[1] <= 0;
+          trc_ctrl_reg[0] <= 0;
+        end
+      else if (dbrk_traceoff | xbrk_traceoff)
+          trc_ctrl_reg[1] <= 0;
+      else if (trc_ctrl_reg[0] & 
+                                  (dbrk_traceon | xbrk_traceon))
+          trc_ctrl_reg[1] <= 1;
+    end
+
+
+  assign trc_ctrl = 0;
+  assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_oci_td_mode (
+                                              // inputs:
+                                               ctrl,
+
+                                              // outputs:
+                                               td_mode
+                                            )
+;
+
+  output  [  3: 0] td_mode;
+  input   [  8: 0] ctrl;
+
+
+wire    [  2: 0] ctrl_bits_for_mux;
+reg     [  3: 0] td_mode;
+  assign ctrl_bits_for_mux = ctrl[7 : 5];
+  always @(ctrl_bits_for_mux)
+    begin
+      case (ctrl_bits_for_mux)
+      
+          3'b000: begin
+              td_mode = 4'b0000;
+          end // 3'b000 
+      
+          3'b001: begin
+              td_mode = 4'b1000;
+          end // 3'b001 
+      
+          3'b010: begin
+              td_mode = 4'b0100;
+          end // 3'b010 
+      
+          3'b011: begin
+              td_mode = 4'b1100;
+          end // 3'b011 
+      
+          3'b100: begin
+              td_mode = 4'b0010;
+          end // 3'b100 
+      
+          3'b101: begin
+              td_mode = 4'b1010;
+          end // 3'b101 
+      
+          3'b110: begin
+              td_mode = 4'b0101;
+          end // 3'b110 
+      
+          3'b111: begin
+              td_mode = 4'b1111;
+          end // 3'b111 
+      
+      endcase // ctrl_bits_for_mux
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_oci_dtrace (
+                                             // inputs:
+                                              clk,
+                                              cpu_d_address,
+                                              cpu_d_read,
+                                              cpu_d_readdata,
+                                              cpu_d_wait,
+                                              cpu_d_write,
+                                              cpu_d_writedata,
+                                              jrst_n,
+                                              trc_ctrl,
+
+                                             // outputs:
+                                              atm,
+                                              dtm
+                                           )
+;
+
+  output  [ 35: 0] atm;
+  output  [ 35: 0] dtm;
+  input            clk;
+  input   [ 19: 0] cpu_d_address;
+  input            cpu_d_read;
+  input   [ 31: 0] cpu_d_readdata;
+  input            cpu_d_wait;
+  input            cpu_d_write;
+  input   [ 31: 0] cpu_d_writedata;
+  input            jrst_n;
+  input   [ 15: 0] trc_ctrl;
+
+
+reg     [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101"  */;
+wire    [ 31: 0] cpu_d_address_0_padded;
+wire    [ 31: 0] cpu_d_readdata_0_padded;
+wire    [ 31: 0] cpu_d_writedata_0_padded;
+reg     [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101"  */;
+wire             dummy_tie_off;
+wire             record_load_addr;
+wire             record_load_data;
+wire             record_store_addr;
+wire             record_store_data;
+wire    [  3: 0] td_mode_trc_ctrl;
+  assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
+  assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
+  assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
+  //nios2_uc_nios2_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
+  nios2_uc_nios2_cpu_nios2_oci_td_mode nios2_uc_nios2_cpu_nios2_oci_trc_ctrl_td_mode
+    (
+      .ctrl    (trc_ctrl[8 : 0]),
+      .td_mode (td_mode_trc_ctrl)
+    );
+
+  assign {record_load_addr, record_store_addr,
+         record_load_data, record_store_data} = td_mode_trc_ctrl;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          atm <= 0;
+          dtm <= 0;
+        end
+      else 
+        begin
+          atm <= 0;
+          dtm <= 0;
+        end
+    end
+
+
+  assign dummy_tie_off = cpu_d_wait|cpu_d_read|cpu_d_write;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_oci_compute_input_tm_cnt (
+                                                           // inputs:
+                                                            atm_valid,
+                                                            dtm_valid,
+                                                            itm_valid,
+
+                                                           // outputs:
+                                                            compute_input_tm_cnt
+                                                         )
+;
+
+  output  [  1: 0] compute_input_tm_cnt;
+  input            atm_valid;
+  input            dtm_valid;
+  input            itm_valid;
+
+
+reg     [  1: 0] compute_input_tm_cnt;
+wire    [  2: 0] switch_for_mux;
+  assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
+  always @(switch_for_mux)
+    begin
+      case (switch_for_mux)
+      
+          3'b000: begin
+              compute_input_tm_cnt = 0;
+          end // 3'b000 
+      
+          3'b001: begin
+              compute_input_tm_cnt = 1;
+          end // 3'b001 
+      
+          3'b010: begin
+              compute_input_tm_cnt = 1;
+          end // 3'b010 
+      
+          3'b011: begin
+              compute_input_tm_cnt = 2;
+          end // 3'b011 
+      
+          3'b100: begin
+              compute_input_tm_cnt = 1;
+          end // 3'b100 
+      
+          3'b101: begin
+              compute_input_tm_cnt = 2;
+          end // 3'b101 
+      
+          3'b110: begin
+              compute_input_tm_cnt = 2;
+          end // 3'b110 
+      
+          3'b111: begin
+              compute_input_tm_cnt = 3;
+          end // 3'b111 
+      
+      endcase // switch_for_mux
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_oci_fifo_wrptr_inc (
+                                                     // inputs:
+                                                      ge2_free,
+                                                      ge3_free,
+                                                      input_tm_cnt,
+
+                                                     // outputs:
+                                                      fifo_wrptr_inc
+                                                   )
+;
+
+  output  [  3: 0] fifo_wrptr_inc;
+  input            ge2_free;
+  input            ge3_free;
+  input   [  1: 0] input_tm_cnt;
+
+
+reg     [  3: 0] fifo_wrptr_inc;
+  always @(ge2_free or ge3_free or input_tm_cnt)
+    begin
+      if (ge3_free & (input_tm_cnt == 3))
+          fifo_wrptr_inc = 3;
+      else if (ge2_free & (input_tm_cnt >= 2))
+          fifo_wrptr_inc = 2;
+      else if (input_tm_cnt >= 1)
+          fifo_wrptr_inc = 1;
+      else 
+        fifo_wrptr_inc = 0;
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_oci_fifo_cnt_inc (
+                                                   // inputs:
+                                                    empty,
+                                                    ge2_free,
+                                                    ge3_free,
+                                                    input_tm_cnt,
+
+                                                   // outputs:
+                                                    fifo_cnt_inc
+                                                 )
+;
+
+  output  [  4: 0] fifo_cnt_inc;
+  input            empty;
+  input            ge2_free;
+  input            ge3_free;
+  input   [  1: 0] input_tm_cnt;
+
+
+reg     [  4: 0] fifo_cnt_inc;
+  always @(empty or ge2_free or ge3_free or input_tm_cnt)
+    begin
+      if (empty)
+          fifo_cnt_inc = input_tm_cnt[1 : 0];
+      else if (ge3_free & (input_tm_cnt == 3))
+          fifo_cnt_inc = 2;
+      else if (ge2_free & (input_tm_cnt >= 2))
+          fifo_cnt_inc = 1;
+      else if (input_tm_cnt >= 1)
+          fifo_cnt_inc = 0;
+      else 
+        fifo_cnt_inc = {5{1'b1}};
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_oci_fifo (
+                                           // inputs:
+                                            atm,
+                                            clk,
+                                            dbrk_traceme,
+                                            dbrk_traceoff,
+                                            dbrk_traceon,
+                                            dtm,
+                                            itm,
+                                            jrst_n,
+                                            reset_n,
+                                            trc_on,
+
+                                           // outputs:
+                                            tw
+                                         )
+;
+
+  output  [ 35: 0] tw;
+  input   [ 35: 0] atm;
+  input            clk;
+  input            dbrk_traceme;
+  input            dbrk_traceoff;
+  input            dbrk_traceon;
+  input   [ 35: 0] dtm;
+  input   [ 35: 0] itm;
+  input            jrst_n;
+  input            reset_n;
+  input            trc_on;
+
+
+wire             atm_valid;
+wire    [  1: 0] compute_input_tm_cnt;
+wire             dtm_valid;
+wire             empty;
+reg     [ 35: 0] fifo_0;
+wire             fifo_0_enable;
+wire    [ 35: 0] fifo_0_mux;
+reg     [ 35: 0] fifo_1;
+reg     [ 35: 0] fifo_10;
+wire             fifo_10_enable;
+wire    [ 35: 0] fifo_10_mux;
+reg     [ 35: 0] fifo_11;
+wire             fifo_11_enable;
+wire    [ 35: 0] fifo_11_mux;
+reg     [ 35: 0] fifo_12;
+wire             fifo_12_enable;
+wire    [ 35: 0] fifo_12_mux;
+reg     [ 35: 0] fifo_13;
+wire             fifo_13_enable;
+wire    [ 35: 0] fifo_13_mux;
+reg     [ 35: 0] fifo_14;
+wire             fifo_14_enable;
+wire    [ 35: 0] fifo_14_mux;
+reg     [ 35: 0] fifo_15;
+wire             fifo_15_enable;
+wire    [ 35: 0] fifo_15_mux;
+wire             fifo_1_enable;
+wire    [ 35: 0] fifo_1_mux;
+reg     [ 35: 0] fifo_2;
+wire             fifo_2_enable;
+wire    [ 35: 0] fifo_2_mux;
+reg     [ 35: 0] fifo_3;
+wire             fifo_3_enable;
+wire    [ 35: 0] fifo_3_mux;
+reg     [ 35: 0] fifo_4;
+wire             fifo_4_enable;
+wire    [ 35: 0] fifo_4_mux;
+reg     [ 35: 0] fifo_5;
+wire             fifo_5_enable;
+wire    [ 35: 0] fifo_5_mux;
+reg     [ 35: 0] fifo_6;
+wire             fifo_6_enable;
+wire    [ 35: 0] fifo_6_mux;
+reg     [ 35: 0] fifo_7;
+wire             fifo_7_enable;
+wire    [ 35: 0] fifo_7_mux;
+reg     [ 35: 0] fifo_8;
+wire             fifo_8_enable;
+wire    [ 35: 0] fifo_8_mux;
+reg     [ 35: 0] fifo_9;
+wire             fifo_9_enable;
+wire    [ 35: 0] fifo_9_mux;
+reg     [  4: 0] fifo_cnt /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101"  */;
+wire    [  4: 0] fifo_cnt_inc;
+wire    [ 35: 0] fifo_head;
+reg     [  3: 0] fifo_rdptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101"  */;
+wire    [ 35: 0] fifo_read_mux;
+reg     [  3: 0] fifo_wrptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101"  */;
+wire    [  3: 0] fifo_wrptr_inc;
+wire    [  3: 0] fifo_wrptr_plus1;
+wire    [  3: 0] fifo_wrptr_plus2;
+wire             ge2_free;
+wire             ge3_free;
+wire             input_ge1;
+wire             input_ge2;
+wire             input_ge3;
+wire    [  1: 0] input_tm_cnt;
+wire             itm_valid;
+reg              overflow_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101"  */;
+wire    [ 35: 0] overflow_pending_atm;
+wire    [ 35: 0] overflow_pending_dtm;
+wire             trc_this;
+wire    [ 35: 0] tw;
+  assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
+  assign itm_valid = |itm[35 : 32];
+  assign atm_valid = |atm[35 : 32] & trc_this;
+  assign dtm_valid = |dtm[35 : 32] & trc_this;
+  assign ge2_free = ~fifo_cnt[4];
+  assign ge3_free = ge2_free & ~&fifo_cnt[3 : 0];
+  assign empty = ~|fifo_cnt;
+  assign fifo_wrptr_plus1 = fifo_wrptr + 1;
+  assign fifo_wrptr_plus2 = fifo_wrptr + 2;
+  nios2_uc_nios2_cpu_nios2_oci_compute_input_tm_cnt the_nios2_uc_nios2_cpu_nios2_oci_compute_input_tm_cnt
+    (
+      .atm_valid            (atm_valid),
+      .compute_input_tm_cnt (compute_input_tm_cnt),
+      .dtm_valid            (dtm_valid),
+      .itm_valid            (itm_valid)
+    );
+
+  assign input_tm_cnt = compute_input_tm_cnt;
+  nios2_uc_nios2_cpu_nios2_oci_fifo_wrptr_inc the_nios2_uc_nios2_cpu_nios2_oci_fifo_wrptr_inc
+    (
+      .fifo_wrptr_inc (fifo_wrptr_inc),
+      .ge2_free       (ge2_free),
+      .ge3_free       (ge3_free),
+      .input_tm_cnt   (input_tm_cnt)
+    );
+
+  nios2_uc_nios2_cpu_nios2_oci_fifo_cnt_inc the_nios2_uc_nios2_cpu_nios2_oci_fifo_cnt_inc
+    (
+      .empty        (empty),
+      .fifo_cnt_inc (fifo_cnt_inc),
+      .ge2_free     (ge2_free),
+      .ge3_free     (ge3_free),
+      .input_tm_cnt (input_tm_cnt)
+    );
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          fifo_rdptr <= 0;
+          fifo_wrptr <= 0;
+          fifo_cnt <= 0;
+          overflow_pending <= 1;
+        end
+      else 
+        begin
+          fifo_wrptr <= fifo_wrptr + fifo_wrptr_inc;
+          fifo_cnt <= fifo_cnt + fifo_cnt_inc;
+          if (~empty)
+              fifo_rdptr <= fifo_rdptr + 1;
+          if (~trc_this || (~ge2_free & input_ge2) || (~ge3_free & input_ge3))
+              overflow_pending <= 1;
+          else if (atm_valid | dtm_valid)
+              overflow_pending <= 0;
+        end
+    end
+
+
+  assign fifo_head = fifo_read_mux;
+  assign tw = itm;
+  assign fifo_0_enable = ((fifo_wrptr == 4'd0) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd0) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd0) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_0 <= 0;
+      else if (fifo_0_enable)
+          fifo_0 <= fifo_0_mux;
+    end
+
+
+  assign fifo_0_mux = (((fifo_wrptr == 4'd0) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd0) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd0) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd0) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_1_enable = ((fifo_wrptr == 4'd1) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd1) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd1) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_1 <= 0;
+      else if (fifo_1_enable)
+          fifo_1 <= fifo_1_mux;
+    end
+
+
+  assign fifo_1_mux = (((fifo_wrptr == 4'd1) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd1) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd1) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd1) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_2_enable = ((fifo_wrptr == 4'd2) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd2) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd2) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_2 <= 0;
+      else if (fifo_2_enable)
+          fifo_2 <= fifo_2_mux;
+    end
+
+
+  assign fifo_2_mux = (((fifo_wrptr == 4'd2) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd2) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd2) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd2) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_3_enable = ((fifo_wrptr == 4'd3) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd3) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd3) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_3 <= 0;
+      else if (fifo_3_enable)
+          fifo_3 <= fifo_3_mux;
+    end
+
+
+  assign fifo_3_mux = (((fifo_wrptr == 4'd3) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd3) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd3) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd3) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_4_enable = ((fifo_wrptr == 4'd4) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd4) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd4) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_4 <= 0;
+      else if (fifo_4_enable)
+          fifo_4 <= fifo_4_mux;
+    end
+
+
+  assign fifo_4_mux = (((fifo_wrptr == 4'd4) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd4) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd4) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd4) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_5_enable = ((fifo_wrptr == 4'd5) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd5) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd5) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_5 <= 0;
+      else if (fifo_5_enable)
+          fifo_5 <= fifo_5_mux;
+    end
+
+
+  assign fifo_5_mux = (((fifo_wrptr == 4'd5) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd5) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd5) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd5) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_6_enable = ((fifo_wrptr == 4'd6) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd6) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd6) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_6 <= 0;
+      else if (fifo_6_enable)
+          fifo_6 <= fifo_6_mux;
+    end
+
+
+  assign fifo_6_mux = (((fifo_wrptr == 4'd6) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd6) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd6) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd6) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_7_enable = ((fifo_wrptr == 4'd7) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd7) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd7) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_7 <= 0;
+      else if (fifo_7_enable)
+          fifo_7 <= fifo_7_mux;
+    end
+
+
+  assign fifo_7_mux = (((fifo_wrptr == 4'd7) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd7) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd7) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd7) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_8_enable = ((fifo_wrptr == 4'd8) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd8) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd8) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_8 <= 0;
+      else if (fifo_8_enable)
+          fifo_8 <= fifo_8_mux;
+    end
+
+
+  assign fifo_8_mux = (((fifo_wrptr == 4'd8) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd8) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd8) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd8) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_9_enable = ((fifo_wrptr == 4'd9) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd9) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd9) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_9 <= 0;
+      else if (fifo_9_enable)
+          fifo_9 <= fifo_9_mux;
+    end
+
+
+  assign fifo_9_mux = (((fifo_wrptr == 4'd9) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd9) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd9) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd9) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_10_enable = ((fifo_wrptr == 4'd10) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd10) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd10) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_10 <= 0;
+      else if (fifo_10_enable)
+          fifo_10 <= fifo_10_mux;
+    end
+
+
+  assign fifo_10_mux = (((fifo_wrptr == 4'd10) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd10) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd10) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd10) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_11_enable = ((fifo_wrptr == 4'd11) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd11) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd11) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_11 <= 0;
+      else if (fifo_11_enable)
+          fifo_11 <= fifo_11_mux;
+    end
+
+
+  assign fifo_11_mux = (((fifo_wrptr == 4'd11) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd11) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd11) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd11) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_12_enable = ((fifo_wrptr == 4'd12) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd12) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd12) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_12 <= 0;
+      else if (fifo_12_enable)
+          fifo_12 <= fifo_12_mux;
+    end
+
+
+  assign fifo_12_mux = (((fifo_wrptr == 4'd12) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd12) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd12) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd12) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_13_enable = ((fifo_wrptr == 4'd13) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd13) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd13) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_13 <= 0;
+      else if (fifo_13_enable)
+          fifo_13 <= fifo_13_mux;
+    end
+
+
+  assign fifo_13_mux = (((fifo_wrptr == 4'd13) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd13) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd13) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd13) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_14_enable = ((fifo_wrptr == 4'd14) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd14) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd14) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_14 <= 0;
+      else if (fifo_14_enable)
+          fifo_14 <= fifo_14_mux;
+    end
+
+
+  assign fifo_14_mux = (((fifo_wrptr == 4'd14) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd14) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd14) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd14) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign fifo_15_enable = ((fifo_wrptr == 4'd15) && input_ge1)  || (ge2_free && (fifo_wrptr_plus1== 4'd15) && input_ge2)  ||(ge3_free && (fifo_wrptr_plus2== 4'd15) && input_ge3);
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          fifo_15 <= 0;
+      else if (fifo_15_enable)
+          fifo_15 <= fifo_15_mux;
+    end
+
+
+  assign fifo_15_mux = (((fifo_wrptr == 4'd15) && itm_valid))? itm :
+    (((fifo_wrptr == 4'd15) && atm_valid))? overflow_pending_atm :
+    (((fifo_wrptr == 4'd15) && dtm_valid))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
+    (((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
+    (((fifo_wrptr_plus1 == 4'd15) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
+    overflow_pending_dtm;
+
+  assign input_ge1 = |input_tm_cnt;
+  assign input_ge2 = input_tm_cnt[1];
+  assign input_ge3 = &input_tm_cnt;
+  assign overflow_pending_atm = {overflow_pending, atm[34 : 0]};
+  assign overflow_pending_dtm = {overflow_pending, dtm[34 : 0]};
+  assign fifo_read_mux = (fifo_rdptr == 4'd0)? fifo_0 :
+    (fifo_rdptr == 4'd1)? fifo_1 :
+    (fifo_rdptr == 4'd2)? fifo_2 :
+    (fifo_rdptr == 4'd3)? fifo_3 :
+    (fifo_rdptr == 4'd4)? fifo_4 :
+    (fifo_rdptr == 4'd5)? fifo_5 :
+    (fifo_rdptr == 4'd6)? fifo_6 :
+    (fifo_rdptr == 4'd7)? fifo_7 :
+    (fifo_rdptr == 4'd8)? fifo_8 :
+    (fifo_rdptr == 4'd9)? fifo_9 :
+    (fifo_rdptr == 4'd10)? fifo_10 :
+    (fifo_rdptr == 4'd11)? fifo_11 :
+    (fifo_rdptr == 4'd12)? fifo_12 :
+    (fifo_rdptr == 4'd13)? fifo_13 :
+    (fifo_rdptr == 4'd14)? fifo_14 :
+    fifo_15;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_oci_pib (
+                                          // outputs:
+                                           tr_data
+                                        )
+;
+
+  output  [ 35: 0] tr_data;
+
+
+wire    [ 35: 0] tr_data;
+  assign tr_data = 0;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_oci_im (
+                                         // inputs:
+                                          clk,
+                                          jrst_n,
+                                          trc_ctrl,
+                                          tw,
+
+                                         // outputs:
+                                          tracemem_on,
+                                          tracemem_trcdata,
+                                          tracemem_tw,
+                                          trc_im_addr,
+                                          trc_wrap,
+                                          xbrk_wrap_traceoff
+                                       )
+;
+
+  output           tracemem_on;
+  output  [ 35: 0] tracemem_trcdata;
+  output           tracemem_tw;
+  output  [  6: 0] trc_im_addr;
+  output           trc_wrap;
+  output           xbrk_wrap_traceoff;
+  input            clk;
+  input            jrst_n;
+  input   [ 15: 0] trc_ctrl;
+  input   [ 35: 0] tw;
+
+
+wire             tracemem_on;
+wire    [ 35: 0] tracemem_trcdata;
+wire             tracemem_tw;
+reg     [  6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire    [ 35: 0] trc_im_data;
+wire             trc_on_chip;
+reg              trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire             tw_valid;
+wire             xbrk_wrap_traceoff;
+  assign trc_im_data = tw;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          trc_im_addr <= 0;
+          trc_wrap <= 0;
+        end
+      else 
+        begin
+          trc_im_addr <= 0;
+          trc_wrap <= 0;
+        end
+    end
+
+
+  assign trc_on_chip = ~trc_ctrl[8];
+  assign tw_valid = |trc_im_data[35 : 32];
+  assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
+  assign tracemem_trcdata = 0;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_performance_monitors 
+;
+
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_avalon_reg (
+                                             // inputs:
+                                              address,
+                                              clk,
+                                              debugaccess,
+                                              monitor_error,
+                                              monitor_go,
+                                              monitor_ready,
+                                              reset_n,
+                                              write,
+                                              writedata,
+
+                                             // outputs:
+                                              oci_ienable,
+                                              oci_reg_readdata,
+                                              oci_single_step_mode,
+                                              ocireg_ers,
+                                              ocireg_mrs,
+                                              take_action_ocireg
+                                           )
+;
+
+  output  [ 31: 0] oci_ienable;
+  output  [ 31: 0] oci_reg_readdata;
+  output           oci_single_step_mode;
+  output           ocireg_ers;
+  output           ocireg_mrs;
+  output           take_action_ocireg;
+  input   [  8: 0] address;
+  input            clk;
+  input            debugaccess;
+  input            monitor_error;
+  input            monitor_go;
+  input            monitor_ready;
+  input            reset_n;
+  input            write;
+  input   [ 31: 0] writedata;
+
+
+reg     [ 31: 0] oci_ienable;
+wire             oci_reg_00_addressed;
+wire             oci_reg_01_addressed;
+wire    [ 31: 0] oci_reg_readdata;
+reg              oci_single_step_mode;
+wire             ocireg_ers;
+wire             ocireg_mrs;
+wire             ocireg_sstep;
+wire             take_action_oci_intr_mask_reg;
+wire             take_action_ocireg;
+wire             write_strobe;
+  assign oci_reg_00_addressed = address == 9'h100;
+  assign oci_reg_01_addressed = address == 9'h101;
+  assign write_strobe = write & debugaccess;
+  assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
+  assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
+  assign ocireg_ers = writedata[1];
+  assign ocireg_mrs = writedata[0];
+  assign ocireg_sstep = writedata[3];
+  assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
+    monitor_ready, monitor_error} : 
+    oci_reg_01_addressed ?  oci_ienable :   
+    32'b0;
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          oci_single_step_mode <= 1'b0;
+      else if (take_action_ocireg)
+          oci_single_step_mode <= ocireg_sstep;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          oci_ienable <= 32'b00000000000000000000000000000001;
+      else if (take_action_oci_intr_mask_reg)
+          oci_ienable <= writedata | ~(32'b00000000000000000000000000000001);
+    end
+
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_ociram_sp_ram_module (
+                                                 // inputs:
+                                                  address,
+                                                  byteenable,
+                                                  clock,
+                                                  data,
+                                                  reset_req,
+                                                  wren,
+
+                                                 // outputs:
+                                                  q
+                                               )
+;
+
+  parameter lpm_file = "UNUSED";
+
+
+  output  [ 31: 0] q;
+  input   [  7: 0] address;
+  input   [  3: 0] byteenable;
+  input            clock;
+  input   [ 31: 0] data;
+  input            reset_req;
+  input            wren;
+
+
+wire             clocken;
+wire    [ 31: 0] q;
+wire    [ 31: 0] ram_q;
+  assign q = ram_q;
+  assign clocken = ~reset_req;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .byteena_a (byteenable),
+      .clock0 (clock),
+      .clocken0 (clocken),
+      .data_a (data),
+      .q_a (ram_q),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.init_file = lpm_file,
+           the_altsyncram.maximum_depth = 0,
+           the_altsyncram.numwords_a = 256,
+           the_altsyncram.operation_mode = "SINGLE_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
+           the_altsyncram.width_a = 32,
+           the_altsyncram.width_byteena_a = 4,
+           the_altsyncram.widthad_a = 8;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_ocimem (
+                                         // inputs:
+                                          address,
+                                          byteenable,
+                                          clk,
+                                          debugaccess,
+                                          jdo,
+                                          jrst_n,
+                                          read,
+                                          reset_req,
+                                          take_action_ocimem_a,
+                                          take_action_ocimem_b,
+                                          take_no_action_ocimem_a,
+                                          write,
+                                          writedata,
+
+                                         // outputs:
+                                          MonDReg,
+                                          ociram_readdata,
+                                          waitrequest
+                                       )
+;
+
+  output  [ 31: 0] MonDReg;
+  output  [ 31: 0] ociram_readdata;
+  output           waitrequest;
+  input   [  8: 0] address;
+  input   [  3: 0] byteenable;
+  input            clk;
+  input            debugaccess;
+  input   [ 37: 0] jdo;
+  input            jrst_n;
+  input            read;
+  input            reset_req;
+  input            take_action_ocimem_a;
+  input            take_action_ocimem_b;
+  input            take_no_action_ocimem_a;
+  input            write;
+  input   [ 31: 0] writedata;
+
+
+reg     [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire    [  8: 0] MonARegAddrInc;
+wire             MonARegAddrIncAccessingRAM;
+reg     [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+reg              avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire             avalon_ram_wr;
+wire    [ 31: 0] cfgrom_readdata;
+reg              jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+reg              jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+reg              jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+reg              jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+reg              jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+reg              jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire    [  7: 0] ociram_addr;
+wire    [  3: 0] ociram_byteenable;
+wire    [ 31: 0] ociram_readdata;
+wire             ociram_reset_req;
+wire    [ 31: 0] ociram_wr_data;
+wire             ociram_wr_en;
+reg              waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+        begin
+          jtag_rd <= 1'b0;
+          jtag_rd_d1 <= 1'b0;
+          jtag_ram_wr <= 1'b0;
+          jtag_ram_rd <= 1'b0;
+          jtag_ram_rd_d1 <= 1'b0;
+          jtag_ram_access <= 1'b0;
+          MonAReg <= 0;
+          MonDReg <= 0;
+          waitrequest <= 1'b1;
+          avalon_ociram_readdata_ready <= 1'b0;
+        end
+      else 
+        begin
+          if (take_no_action_ocimem_a)
+            begin
+              MonAReg[10 : 2] <= MonARegAddrInc;
+              jtag_rd <= 1'b1;
+              jtag_ram_rd <= MonARegAddrIncAccessingRAM;
+              jtag_ram_access <= MonARegAddrIncAccessingRAM;
+            end
+          else if (take_action_ocimem_a)
+            begin
+              MonAReg[10 : 2] <= { jdo[17],
+                            jdo[33 : 26] };
+
+              jtag_rd <= 1'b1;
+              jtag_ram_rd <= ~jdo[17];
+              jtag_ram_access <= ~jdo[17];
+            end
+          else if (take_action_ocimem_b)
+            begin
+              MonAReg[10 : 2] <= MonARegAddrInc;
+              MonDReg <= jdo[34 : 3];
+              jtag_ram_wr <= MonARegAddrIncAccessingRAM;
+              jtag_ram_access <= MonARegAddrIncAccessingRAM;
+            end
+          else 
+            begin
+              jtag_rd <= 0;
+              jtag_ram_wr <= 0;
+              jtag_ram_rd <= 0;
+              jtag_ram_access <= 0;
+              if (jtag_rd_d1)
+                  MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata;
+            end
+          jtag_rd_d1 <= jtag_rd;
+          jtag_ram_rd_d1 <= jtag_ram_rd;
+          if (~waitrequest)
+            begin
+              waitrequest <= 1'b1;
+              avalon_ociram_readdata_ready <= 1'b0;
+            end
+          else if (write)
+              waitrequest <= ~address[8] & jtag_ram_access;
+          else if (read)
+            begin
+              avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access);
+              waitrequest <= ~avalon_ociram_readdata_ready;
+            end
+          else 
+            begin
+              waitrequest <= 1'b1;
+              avalon_ociram_readdata_ready <= 1'b0;
+            end
+        end
+    end
+
+
+  assign MonARegAddrInc = MonAReg[10 : 2]+1;
+  assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8];
+  assign avalon_ram_wr = write & ~address[8] & debugaccess;
+  assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0];
+  assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata;
+  assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable;
+  assign ociram_wr_en = jtag_ram_access ? jtag_ram_wr : avalon_ram_wr;
+  assign ociram_reset_req = reset_req & ~jtag_ram_access;
+//nios2_uc_nios2_cpu_ociram_sp_ram, which is an nios_sp_ram
+nios2_uc_nios2_cpu_ociram_sp_ram_module nios2_uc_nios2_cpu_ociram_sp_ram
+  (
+    .address    (ociram_addr),
+    .byteenable (ociram_byteenable),
+    .clock      (clk),
+    .data       (ociram_wr_data),
+    .q          (ociram_readdata),
+    .reset_req  (ociram_reset_req),
+    .wren       (ociram_wr_en)
+  );
+
+//synthesis translate_off
+`ifdef NO_PLI
+defparam nios2_uc_nios2_cpu_ociram_sp_ram.lpm_file = "nios2_uc_nios2_cpu_ociram_default_contents.dat";
+`else
+defparam nios2_uc_nios2_cpu_ociram_sp_ram.lpm_file = "nios2_uc_nios2_cpu_ociram_default_contents.hex";
+`endif
+//synthesis translate_on
+  assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00040020 :
+    (MonAReg[4 : 2] == 3'd1)? 32'h00001414 :
+    (MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
+    (MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
+    (MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
+    (MonAReg[4 : 2] == 3'd5)? 32'h00040000 :
+    (MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
+    32'h00000000;
+
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_nios2_oci (
+                                      // inputs:
+                                       D_valid,
+                                       E_st_data,
+                                       E_valid,
+                                       F_pc,
+                                       address_nxt,
+                                       av_ld_data_aligned_filtered,
+                                       byteenable_nxt,
+                                       clk,
+                                       d_address,
+                                       d_read,
+                                       d_waitrequest,
+                                       d_write,
+                                       debugaccess_nxt,
+                                       hbreak_enabled,
+                                       read_nxt,
+                                       reset,
+                                       reset_n,
+                                       reset_req,
+                                       write_nxt,
+                                       writedata_nxt,
+
+                                      // outputs:
+                                       debug_mem_slave_debugaccess_to_roms,
+                                       oci_hbreak_req,
+                                       oci_ienable,
+                                       oci_single_step_mode,
+                                       readdata,
+                                       resetrequest,
+                                       waitrequest
+                                    )
+;
+
+  output           debug_mem_slave_debugaccess_to_roms;
+  output           oci_hbreak_req;
+  output  [ 31: 0] oci_ienable;
+  output           oci_single_step_mode;
+  output  [ 31: 0] readdata;
+  output           resetrequest;
+  output           waitrequest;
+  input            D_valid;
+  input   [ 31: 0] E_st_data;
+  input            E_valid;
+  input   [ 17: 0] F_pc;
+  input   [  8: 0] address_nxt;
+  input   [ 31: 0] av_ld_data_aligned_filtered;
+  input   [  3: 0] byteenable_nxt;
+  input            clk;
+  input   [ 19: 0] d_address;
+  input            d_read;
+  input            d_waitrequest;
+  input            d_write;
+  input            debugaccess_nxt;
+  input            hbreak_enabled;
+  input            read_nxt;
+  input            reset;
+  input            reset_n;
+  input            reset_req;
+  input            write_nxt;
+  input   [ 31: 0] writedata_nxt;
+
+
+wire    [ 31: 0] MonDReg;
+reg     [  8: 0] address;
+wire    [ 35: 0] atm;
+wire    [ 31: 0] break_readreg;
+reg     [  3: 0] byteenable;
+wire    [ 19: 0] cpu_d_address;
+wire             cpu_d_read;
+wire    [ 31: 0] cpu_d_readdata;
+wire             cpu_d_wait;
+wire             cpu_d_write;
+wire    [ 31: 0] cpu_d_writedata;
+wire             dbrk_break;
+wire             dbrk_goto0;
+wire             dbrk_goto1;
+wire             dbrk_hit0_latch;
+wire             dbrk_hit1_latch;
+wire             dbrk_hit2_latch;
+wire             dbrk_hit3_latch;
+wire             dbrk_traceme;
+wire             dbrk_traceoff;
+wire             dbrk_traceon;
+wire             dbrk_trigout;
+wire             debug_mem_slave_debugaccess_to_roms;
+reg              debugaccess;
+wire             debugack;
+wire             debugreq;
+wire    [ 35: 0] dtm;
+wire             dummy_sink;
+wire    [ 35: 0] itm;
+wire    [ 37: 0] jdo;
+wire             jrst_n;
+wire             monitor_error;
+wire             monitor_go;
+wire             monitor_ready;
+wire             oci_hbreak_req;
+wire    [ 31: 0] oci_ienable;
+wire    [ 31: 0] oci_reg_readdata;
+wire             oci_single_step_mode;
+wire    [ 31: 0] ociram_readdata;
+wire             ocireg_ers;
+wire             ocireg_mrs;
+reg              read;
+reg     [ 31: 0] readdata;
+wire             resetlatch;
+wire             resetrequest;
+wire             st_ready_test_idle;
+wire             take_action_break_a;
+wire             take_action_break_b;
+wire             take_action_break_c;
+wire             take_action_ocimem_a;
+wire             take_action_ocimem_b;
+wire             take_action_ocireg;
+wire             take_action_tracectrl;
+wire             take_no_action_break_a;
+wire             take_no_action_break_b;
+wire             take_no_action_break_c;
+wire             take_no_action_ocimem_a;
+wire    [ 35: 0] tr_data;
+wire             tracemem_on;
+wire    [ 35: 0] tracemem_trcdata;
+wire             tracemem_tw;
+wire    [ 15: 0] trc_ctrl;
+wire    [  6: 0] trc_im_addr;
+wire             trc_on;
+wire             trc_wrap;
+wire             trigbrktype;
+wire             trigger_state_0;
+wire             trigger_state_1;
+wire             trigout;
+wire    [ 35: 0] tw;
+wire             waitrequest;
+reg              write;
+reg     [ 31: 0] writedata;
+wire             xbrk_break;
+wire    [  7: 0] xbrk_ctrl0;
+wire    [  7: 0] xbrk_ctrl1;
+wire    [  7: 0] xbrk_ctrl2;
+wire    [  7: 0] xbrk_ctrl3;
+wire             xbrk_goto0;
+wire             xbrk_goto1;
+wire             xbrk_traceoff;
+wire             xbrk_traceon;
+wire             xbrk_trigout;
+wire             xbrk_wrap_traceoff;
+  nios2_uc_nios2_cpu_nios2_oci_debug the_nios2_uc_nios2_cpu_nios2_oci_debug
+    (
+      .clk                  (clk),
+      .dbrk_break           (dbrk_break),
+      .debugack             (debugack),
+      .debugreq             (debugreq),
+      .hbreak_enabled       (hbreak_enabled),
+      .jdo                  (jdo),
+      .jrst_n               (jrst_n),
+      .monitor_error        (monitor_error),
+      .monitor_go           (monitor_go),
+      .monitor_ready        (monitor_ready),
+      .oci_hbreak_req       (oci_hbreak_req),
+      .ocireg_ers           (ocireg_ers),
+      .ocireg_mrs           (ocireg_mrs),
+      .reset                (reset),
+      .resetlatch           (resetlatch),
+      .resetrequest         (resetrequest),
+      .st_ready_test_idle   (st_ready_test_idle),
+      .take_action_ocimem_a (take_action_ocimem_a),
+      .take_action_ocireg   (take_action_ocireg),
+      .xbrk_break           (xbrk_break)
+    );
+
+  nios2_uc_nios2_cpu_nios2_oci_break the_nios2_uc_nios2_cpu_nios2_oci_break
+    (
+      .break_readreg          (break_readreg),
+      .clk                    (clk),
+      .dbrk_break             (dbrk_break),
+      .dbrk_goto0             (dbrk_goto0),
+      .dbrk_goto1             (dbrk_goto1),
+      .dbrk_hit0_latch        (dbrk_hit0_latch),
+      .dbrk_hit1_latch        (dbrk_hit1_latch),
+      .dbrk_hit2_latch        (dbrk_hit2_latch),
+      .dbrk_hit3_latch        (dbrk_hit3_latch),
+      .jdo                    (jdo),
+      .jrst_n                 (jrst_n),
+      .take_action_break_a    (take_action_break_a),
+      .take_action_break_b    (take_action_break_b),
+      .take_action_break_c    (take_action_break_c),
+      .take_no_action_break_a (take_no_action_break_a),
+      .take_no_action_break_b (take_no_action_break_b),
+      .take_no_action_break_c (take_no_action_break_c),
+      .trigbrktype            (trigbrktype),
+      .trigger_state_0        (trigger_state_0),
+      .trigger_state_1        (trigger_state_1),
+      .xbrk_ctrl0             (xbrk_ctrl0),
+      .xbrk_ctrl1             (xbrk_ctrl1),
+      .xbrk_ctrl2             (xbrk_ctrl2),
+      .xbrk_ctrl3             (xbrk_ctrl3),
+      .xbrk_goto0             (xbrk_goto0),
+      .xbrk_goto1             (xbrk_goto1)
+    );
+
+  nios2_uc_nios2_cpu_nios2_oci_xbrk the_nios2_uc_nios2_cpu_nios2_oci_xbrk
+    (
+      .D_valid         (D_valid),
+      .E_valid         (E_valid),
+      .F_pc            (F_pc),
+      .clk             (clk),
+      .reset_n         (reset_n),
+      .trigger_state_0 (trigger_state_0),
+      .trigger_state_1 (trigger_state_1),
+      .xbrk_break      (xbrk_break),
+      .xbrk_ctrl0      (xbrk_ctrl0),
+      .xbrk_ctrl1      (xbrk_ctrl1),
+      .xbrk_ctrl2      (xbrk_ctrl2),
+      .xbrk_ctrl3      (xbrk_ctrl3),
+      .xbrk_goto0      (xbrk_goto0),
+      .xbrk_goto1      (xbrk_goto1),
+      .xbrk_traceoff   (xbrk_traceoff),
+      .xbrk_traceon    (xbrk_traceon),
+      .xbrk_trigout    (xbrk_trigout)
+    );
+
+  nios2_uc_nios2_cpu_nios2_oci_dbrk the_nios2_uc_nios2_cpu_nios2_oci_dbrk
+    (
+      .E_st_data                   (E_st_data),
+      .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
+      .clk                         (clk),
+      .cpu_d_address               (cpu_d_address),
+      .cpu_d_read                  (cpu_d_read),
+      .cpu_d_readdata              (cpu_d_readdata),
+      .cpu_d_wait                  (cpu_d_wait),
+      .cpu_d_write                 (cpu_d_write),
+      .cpu_d_writedata             (cpu_d_writedata),
+      .d_address                   (d_address),
+      .d_read                      (d_read),
+      .d_waitrequest               (d_waitrequest),
+      .d_write                     (d_write),
+      .dbrk_break                  (dbrk_break),
+      .dbrk_goto0                  (dbrk_goto0),
+      .dbrk_goto1                  (dbrk_goto1),
+      .dbrk_traceme                (dbrk_traceme),
+      .dbrk_traceoff               (dbrk_traceoff),
+      .dbrk_traceon                (dbrk_traceon),
+      .dbrk_trigout                (dbrk_trigout),
+      .debugack                    (debugack),
+      .reset_n                     (reset_n)
+    );
+
+  nios2_uc_nios2_cpu_nios2_oci_itrace the_nios2_uc_nios2_cpu_nios2_oci_itrace
+    (
+      .clk                   (clk),
+      .dbrk_traceoff         (dbrk_traceoff),
+      .dbrk_traceon          (dbrk_traceon),
+      .itm                   (itm),
+      .jdo                   (jdo),
+      .jrst_n                (jrst_n),
+      .take_action_tracectrl (take_action_tracectrl),
+      .trc_ctrl              (trc_ctrl),
+      .trc_on                (trc_on),
+      .xbrk_traceoff         (xbrk_traceoff),
+      .xbrk_traceon          (xbrk_traceon),
+      .xbrk_wrap_traceoff    (xbrk_wrap_traceoff)
+    );
+
+  nios2_uc_nios2_cpu_nios2_oci_dtrace the_nios2_uc_nios2_cpu_nios2_oci_dtrace
+    (
+      .atm             (atm),
+      .clk             (clk),
+      .cpu_d_address   (cpu_d_address),
+      .cpu_d_read      (cpu_d_read),
+      .cpu_d_readdata  (cpu_d_readdata),
+      .cpu_d_wait      (cpu_d_wait),
+      .cpu_d_write     (cpu_d_write),
+      .cpu_d_writedata (cpu_d_writedata),
+      .dtm             (dtm),
+      .jrst_n          (jrst_n),
+      .trc_ctrl        (trc_ctrl)
+    );
+
+  nios2_uc_nios2_cpu_nios2_oci_fifo the_nios2_uc_nios2_cpu_nios2_oci_fifo
+    (
+      .atm           (atm),
+      .clk           (clk),
+      .dbrk_traceme  (dbrk_traceme),
+      .dbrk_traceoff (dbrk_traceoff),
+      .dbrk_traceon  (dbrk_traceon),
+      .dtm           (dtm),
+      .itm           (itm),
+      .jrst_n        (jrst_n),
+      .reset_n       (reset_n),
+      .trc_on        (trc_on),
+      .tw            (tw)
+    );
+
+  nios2_uc_nios2_cpu_nios2_oci_pib the_nios2_uc_nios2_cpu_nios2_oci_pib
+    (
+      .tr_data (tr_data)
+    );
+
+  nios2_uc_nios2_cpu_nios2_oci_im the_nios2_uc_nios2_cpu_nios2_oci_im
+    (
+      .clk                (clk),
+      .jrst_n             (jrst_n),
+      .tracemem_on        (tracemem_on),
+      .tracemem_trcdata   (tracemem_trcdata),
+      .tracemem_tw        (tracemem_tw),
+      .trc_ctrl           (trc_ctrl),
+      .trc_im_addr        (trc_im_addr),
+      .trc_wrap           (trc_wrap),
+      .tw                 (tw),
+      .xbrk_wrap_traceoff (xbrk_wrap_traceoff)
+    );
+
+  nios2_uc_nios2_cpu_nios2_avalon_reg the_nios2_uc_nios2_cpu_nios2_avalon_reg
+    (
+      .address              (address),
+      .clk                  (clk),
+      .debugaccess          (debugaccess),
+      .monitor_error        (monitor_error),
+      .monitor_go           (monitor_go),
+      .monitor_ready        (monitor_ready),
+      .oci_ienable          (oci_ienable),
+      .oci_reg_readdata     (oci_reg_readdata),
+      .oci_single_step_mode (oci_single_step_mode),
+      .ocireg_ers           (ocireg_ers),
+      .ocireg_mrs           (ocireg_mrs),
+      .reset_n              (reset_n),
+      .take_action_ocireg   (take_action_ocireg),
+      .write                (write),
+      .writedata            (writedata)
+    );
+
+  nios2_uc_nios2_cpu_nios2_ocimem the_nios2_uc_nios2_cpu_nios2_ocimem
+    (
+      .MonDReg                 (MonDReg),
+      .address                 (address),
+      .byteenable              (byteenable),
+      .clk                     (clk),
+      .debugaccess             (debugaccess),
+      .jdo                     (jdo),
+      .jrst_n                  (jrst_n),
+      .ociram_readdata         (ociram_readdata),
+      .read                    (read),
+      .reset_req               (reset_req),
+      .take_action_ocimem_a    (take_action_ocimem_a),
+      .take_action_ocimem_b    (take_action_ocimem_b),
+      .take_no_action_ocimem_a (take_no_action_ocimem_a),
+      .waitrequest             (waitrequest),
+      .write                   (write),
+      .writedata               (writedata)
+    );
+
+  assign trigout = dbrk_trigout | xbrk_trigout;
+  assign debug_mem_slave_debugaccess_to_roms = debugack;
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          address <= 0;
+      else 
+        address <= address_nxt;
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          byteenable <= 0;
+      else 
+        byteenable <= byteenable_nxt;
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          writedata <= 0;
+      else 
+        writedata <= writedata_nxt;
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          debugaccess <= 0;
+      else 
+        debugaccess <= debugaccess_nxt;
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          read <= 0;
+      else 
+        read <= read ? waitrequest : read_nxt;
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          write <= 0;
+      else 
+        write <= write ? waitrequest : write_nxt;
+    end
+
+
+  always @(posedge clk or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          readdata <= 0;
+      else 
+        readdata <= address[8] ? oci_reg_readdata : ociram_readdata;
+    end
+
+
+  nios2_uc_nios2_cpu_debug_slave_wrapper the_nios2_uc_nios2_cpu_debug_slave_wrapper
+    (
+      .MonDReg                 (MonDReg),
+      .break_readreg           (break_readreg),
+      .clk                     (clk),
+      .dbrk_hit0_latch         (dbrk_hit0_latch),
+      .dbrk_hit1_latch         (dbrk_hit1_latch),
+      .dbrk_hit2_latch         (dbrk_hit2_latch),
+      .dbrk_hit3_latch         (dbrk_hit3_latch),
+      .debugack                (debugack),
+      .jdo                     (jdo),
+      .jrst_n                  (jrst_n),
+      .monitor_error           (monitor_error),
+      .monitor_ready           (monitor_ready),
+      .reset_n                 (reset_n),
+      .resetlatch              (resetlatch),
+      .st_ready_test_idle      (st_ready_test_idle),
+      .take_action_break_a     (take_action_break_a),
+      .take_action_break_b     (take_action_break_b),
+      .take_action_break_c     (take_action_break_c),
+      .take_action_ocimem_a    (take_action_ocimem_a),
+      .take_action_ocimem_b    (take_action_ocimem_b),
+      .take_action_tracectrl   (take_action_tracectrl),
+      .take_no_action_break_a  (take_no_action_break_a),
+      .take_no_action_break_b  (take_no_action_break_b),
+      .take_no_action_break_c  (take_no_action_break_c),
+      .take_no_action_ocimem_a (take_no_action_ocimem_a),
+      .tracemem_on             (tracemem_on),
+      .tracemem_trcdata        (tracemem_trcdata),
+      .tracemem_tw             (tracemem_tw),
+      .trc_im_addr             (trc_im_addr),
+      .trc_on                  (trc_on),
+      .trc_wrap                (trc_wrap),
+      .trigbrktype             (trigbrktype),
+      .trigger_state_1         (trigger_state_1)
+    );
+
+  //dummy sink, which is an e_mux
+  assign dummy_sink = tr_data |
+    trigout |
+    debugack;
+
+  assign debugreq = 0;
+
+endmodule
+
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu (
+                            // inputs:
+                             clk,
+                             d_readdata,
+                             d_waitrequest,
+                             debug_mem_slave_address,
+                             debug_mem_slave_byteenable,
+                             debug_mem_slave_debugaccess,
+                             debug_mem_slave_read,
+                             debug_mem_slave_write,
+                             debug_mem_slave_writedata,
+                             i_readdata,
+                             i_waitrequest,
+                             irq,
+                             reset_n,
+                             reset_req,
+
+                            // outputs:
+                             d_address,
+                             d_byteenable,
+                             d_read,
+                             d_write,
+                             d_writedata,
+                             debug_mem_slave_debugaccess_to_roms,
+                             debug_mem_slave_readdata,
+                             debug_mem_slave_waitrequest,
+                             debug_reset_request,
+                             dummy_ci_port,
+                             i_address,
+                             i_read
+                          )
+;
+
+  output  [ 19: 0] d_address;
+  output  [  3: 0] d_byteenable;
+  output           d_read;
+  output           d_write;
+  output  [ 31: 0] d_writedata;
+  output           debug_mem_slave_debugaccess_to_roms;
+  output  [ 31: 0] debug_mem_slave_readdata;
+  output           debug_mem_slave_waitrequest;
+  output           debug_reset_request;
+  output           dummy_ci_port;
+  output  [ 19: 0] i_address;
+  output           i_read;
+  input            clk;
+  input   [ 31: 0] d_readdata;
+  input            d_waitrequest;
+  input   [  8: 0] debug_mem_slave_address;
+  input   [  3: 0] debug_mem_slave_byteenable;
+  input            debug_mem_slave_debugaccess;
+  input            debug_mem_slave_read;
+  input            debug_mem_slave_write;
+  input   [ 31: 0] debug_mem_slave_writedata;
+  input   [ 31: 0] i_readdata;
+  input            i_waitrequest;
+  input   [ 31: 0] irq;
+  input            reset_n;
+  input            reset_req;
+
+
+reg              A_valid_from_M /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
+wire    [  1: 0] D_compare_op;
+wire             D_ctrl_alu_force_and;
+wire             D_ctrl_alu_force_xor;
+wire             D_ctrl_alu_signed_comparison;
+wire             D_ctrl_alu_subtract;
+wire             D_ctrl_b_is_dst;
+wire             D_ctrl_br;
+wire             D_ctrl_br_cmp;
+wire             D_ctrl_br_uncond;
+wire             D_ctrl_break;
+wire             D_ctrl_crst;
+wire             D_ctrl_custom;
+wire             D_ctrl_custom_multi;
+wire             D_ctrl_exception;
+wire             D_ctrl_force_src2_zero;
+wire             D_ctrl_hi_imm16;
+wire             D_ctrl_ignore_dst;
+wire             D_ctrl_implicit_dst_eretaddr;
+wire             D_ctrl_implicit_dst_retaddr;
+wire             D_ctrl_intr_inst;
+wire             D_ctrl_jmp_direct;
+wire             D_ctrl_jmp_indirect;
+wire             D_ctrl_ld;
+wire             D_ctrl_ld_ex;
+wire             D_ctrl_ld_io;
+wire             D_ctrl_ld_non_io;
+wire             D_ctrl_ld_signed;
+wire             D_ctrl_ld_st_ex;
+wire             D_ctrl_logic;
+wire             D_ctrl_mem16;
+wire             D_ctrl_mem32;
+wire             D_ctrl_mem8;
+wire             D_ctrl_rd_ctl_reg;
+wire             D_ctrl_retaddr;
+wire             D_ctrl_rot_right;
+wire             D_ctrl_set_src2_rem_imm;
+wire             D_ctrl_shift_logical;
+wire             D_ctrl_shift_right_arith;
+wire             D_ctrl_shift_rot;
+wire             D_ctrl_shift_rot_right;
+wire             D_ctrl_signed_imm12;
+wire             D_ctrl_src2_choose_imm;
+wire             D_ctrl_src_imm5_shift_rot;
+wire             D_ctrl_st;
+wire             D_ctrl_st_ex;
+wire             D_ctrl_uncond_cti_non_br;
+wire             D_ctrl_unsigned_lo_imm16;
+wire             D_ctrl_wrctl_inst;
+wire    [  4: 0] D_dst_regnum;
+wire    [ 55: 0] D_inst;
+wire             D_is_opx_inst;
+reg     [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
+wire    [  4: 0] D_iw_a;
+wire    [  4: 0] D_iw_b;
+wire    [  4: 0] D_iw_c;
+wire    [  4: 0] D_iw_control_regnum;
+wire    [  7: 0] D_iw_custom_n;
+wire             D_iw_custom_readra;
+wire             D_iw_custom_readrb;
+wire             D_iw_custom_writerc;
+wire    [ 15: 0] D_iw_imm16;
+wire    [ 25: 0] D_iw_imm26;
+wire    [  4: 0] D_iw_imm5;
+wire    [  1: 0] D_iw_memsz;
+wire    [  5: 0] D_iw_op;
+wire    [  5: 0] D_iw_opx;
+wire    [ 17: 0] D_jmp_direct_target_waddr;
+wire    [  1: 0] D_logic_op;
+wire    [  1: 0] D_logic_op_raw;
+wire             D_mem16;
+wire             D_mem32;
+wire             D_mem8;
+wire             D_op_add;
+wire             D_op_addi;
+wire             D_op_and;
+wire             D_op_andhi;
+wire             D_op_andi;
+wire             D_op_beq;
+wire             D_op_bge;
+wire             D_op_bgeu;
+wire             D_op_blt;
+wire             D_op_bltu;
+wire             D_op_bne;
+wire             D_op_br;
+wire             D_op_break;
+wire             D_op_bret;
+wire             D_op_call;
+wire             D_op_callr;
+wire             D_op_cmpeq;
+wire             D_op_cmpeqi;
+wire             D_op_cmpge;
+wire             D_op_cmpgei;
+wire             D_op_cmpgeu;
+wire             D_op_cmpgeui;
+wire             D_op_cmplt;
+wire             D_op_cmplti;
+wire             D_op_cmpltu;
+wire             D_op_cmpltui;
+wire             D_op_cmpne;
+wire             D_op_cmpnei;
+wire             D_op_crst;
+wire             D_op_custom;
+wire             D_op_div;
+wire             D_op_divu;
+wire             D_op_eret;
+wire             D_op_flushd;
+wire             D_op_flushda;
+wire             D_op_flushi;
+wire             D_op_flushp;
+wire             D_op_hbreak;
+wire             D_op_initd;
+wire             D_op_initda;
+wire             D_op_initi;
+wire             D_op_intr;
+wire             D_op_jmp;
+wire             D_op_jmpi;
+wire             D_op_ldb;
+wire             D_op_ldbio;
+wire             D_op_ldbu;
+wire             D_op_ldbuio;
+wire             D_op_ldh;
+wire             D_op_ldhio;
+wire             D_op_ldhu;
+wire             D_op_ldhuio;
+wire             D_op_ldl;
+wire             D_op_ldw;
+wire             D_op_ldwio;
+wire             D_op_mul;
+wire             D_op_muli;
+wire             D_op_mulxss;
+wire             D_op_mulxsu;
+wire             D_op_mulxuu;
+wire             D_op_nextpc;
+wire             D_op_nor;
+wire             D_op_op_rsv02;
+wire             D_op_op_rsv09;
+wire             D_op_op_rsv10;
+wire             D_op_op_rsv17;
+wire             D_op_op_rsv18;
+wire             D_op_op_rsv25;
+wire             D_op_op_rsv26;
+wire             D_op_op_rsv33;
+wire             D_op_op_rsv34;
+wire             D_op_op_rsv41;
+wire             D_op_op_rsv42;
+wire             D_op_op_rsv49;
+wire             D_op_op_rsv57;
+wire             D_op_op_rsv61;
+wire             D_op_op_rsv62;
+wire             D_op_op_rsv63;
+wire             D_op_opx_rsv00;
+wire             D_op_opx_rsv10;
+wire             D_op_opx_rsv15;
+wire             D_op_opx_rsv17;
+wire             D_op_opx_rsv21;
+wire             D_op_opx_rsv25;
+wire             D_op_opx_rsv33;
+wire             D_op_opx_rsv34;
+wire             D_op_opx_rsv35;
+wire             D_op_opx_rsv42;
+wire             D_op_opx_rsv43;
+wire             D_op_opx_rsv44;
+wire             D_op_opx_rsv47;
+wire             D_op_opx_rsv50;
+wire             D_op_opx_rsv51;
+wire             D_op_opx_rsv55;
+wire             D_op_opx_rsv56;
+wire             D_op_opx_rsv60;
+wire             D_op_opx_rsv63;
+wire             D_op_or;
+wire             D_op_orhi;
+wire             D_op_ori;
+wire             D_op_rdctl;
+wire             D_op_rdprs;
+wire             D_op_ret;
+wire             D_op_rol;
+wire             D_op_roli;
+wire             D_op_ror;
+wire             D_op_sll;
+wire             D_op_slli;
+wire             D_op_sra;
+wire             D_op_srai;
+wire             D_op_srl;
+wire             D_op_srli;
+wire             D_op_stb;
+wire             D_op_stbio;
+wire             D_op_stc;
+wire             D_op_sth;
+wire             D_op_sthio;
+wire             D_op_stw;
+wire             D_op_stwio;
+wire             D_op_sub;
+wire             D_op_sync;
+wire             D_op_trap;
+wire             D_op_wrctl;
+wire             D_op_wrprs;
+wire             D_op_xor;
+wire             D_op_xorhi;
+wire             D_op_xori;
+reg              D_valid;
+wire    [ 71: 0] D_vinst;
+wire             D_wr_dst_reg;
+wire    [ 31: 0] E_alu_result;
+reg              E_alu_sub;
+wire    [ 32: 0] E_arith_result;
+wire    [ 31: 0] E_arith_src1;
+wire    [ 31: 0] E_arith_src2;
+wire             E_ci_multi_stall;
+wire    [ 31: 0] E_ci_result;
+wire             E_cmp_result;
+wire    [ 31: 0] E_control_rd_data;
+wire             E_eq;
+reg              E_invert_arith_src_msb;
+wire             E_ld_stall;
+wire    [ 31: 0] E_logic_result;
+wire             E_logic_result_is_0;
+wire             E_lt;
+wire    [ 19: 0] E_mem_baddr;
+wire    [  3: 0] E_mem_byte_en;
+reg              E_new_inst;
+wire             E_rf_ecc_recoverable_valid;
+wire             E_rf_ecc_unrecoverable_valid;
+wire             E_rf_ecc_valid_any;
+reg     [  4: 0] E_shift_rot_cnt;
+wire    [  4: 0] E_shift_rot_cnt_nxt;
+wire             E_shift_rot_done;
+wire             E_shift_rot_fill_bit;
+reg     [ 31: 0] E_shift_rot_result;
+wire    [ 31: 0] E_shift_rot_result_nxt;
+wire    [  4: 0] E_shift_rot_shfcnt;
+wire             E_shift_rot_stall;
+reg     [ 31: 0] E_src1;
+reg     [ 31: 0] E_src2;
+wire    [ 31: 0] E_st_data;
+wire             E_st_stall;
+wire             E_stall;
+wire             E_valid;
+reg              E_valid_from_R;
+wire    [ 71: 0] E_vinst;
+wire             E_wrctl_bstatus;
+wire             E_wrctl_estatus;
+wire             E_wrctl_ienable;
+wire             E_wrctl_status;
+wire    [ 31: 0] F_av_iw;
+wire    [  4: 0] F_av_iw_a;
+wire    [  4: 0] F_av_iw_b;
+wire    [  4: 0] F_av_iw_c;
+wire    [  4: 0] F_av_iw_control_regnum;
+wire    [  7: 0] F_av_iw_custom_n;
+wire             F_av_iw_custom_readra;
+wire             F_av_iw_custom_readrb;
+wire             F_av_iw_custom_writerc;
+wire    [ 15: 0] F_av_iw_imm16;
+wire    [ 25: 0] F_av_iw_imm26;
+wire    [  4: 0] F_av_iw_imm5;
+wire    [  1: 0] F_av_iw_memsz;
+wire    [  5: 0] F_av_iw_op;
+wire    [  5: 0] F_av_iw_opx;
+wire             F_av_mem16;
+wire             F_av_mem32;
+wire             F_av_mem8;
+wire    [ 55: 0] F_inst;
+wire             F_is_opx_inst;
+wire    [ 31: 0] F_iw;
+wire    [  4: 0] F_iw_a;
+wire    [  4: 0] F_iw_b;
+wire    [  4: 0] F_iw_c;
+wire    [  4: 0] F_iw_control_regnum;
+wire    [  7: 0] F_iw_custom_n;
+wire             F_iw_custom_readra;
+wire             F_iw_custom_readrb;
+wire             F_iw_custom_writerc;
+wire    [ 15: 0] F_iw_imm16;
+wire    [ 25: 0] F_iw_imm26;
+wire    [  4: 0] F_iw_imm5;
+wire    [  1: 0] F_iw_memsz;
+wire    [  5: 0] F_iw_op;
+wire    [  5: 0] F_iw_opx;
+wire             F_mem16;
+wire             F_mem32;
+wire             F_mem8;
+wire             F_op_add;
+wire             F_op_addi;
+wire             F_op_and;
+wire             F_op_andhi;
+wire             F_op_andi;
+wire             F_op_beq;
+wire             F_op_bge;
+wire             F_op_bgeu;
+wire             F_op_blt;
+wire             F_op_bltu;
+wire             F_op_bne;
+wire             F_op_br;
+wire             F_op_break;
+wire             F_op_bret;
+wire             F_op_call;
+wire             F_op_callr;
+wire             F_op_cmpeq;
+wire             F_op_cmpeqi;
+wire             F_op_cmpge;
+wire             F_op_cmpgei;
+wire             F_op_cmpgeu;
+wire             F_op_cmpgeui;
+wire             F_op_cmplt;
+wire             F_op_cmplti;
+wire             F_op_cmpltu;
+wire             F_op_cmpltui;
+wire             F_op_cmpne;
+wire             F_op_cmpnei;
+wire             F_op_crst;
+wire             F_op_custom;
+wire             F_op_div;
+wire             F_op_divu;
+wire             F_op_eret;
+wire             F_op_flushd;
+wire             F_op_flushda;
+wire             F_op_flushi;
+wire             F_op_flushp;
+wire             F_op_hbreak;
+wire             F_op_initd;
+wire             F_op_initda;
+wire             F_op_initi;
+wire             F_op_intr;
+wire             F_op_jmp;
+wire             F_op_jmpi;
+wire             F_op_ldb;
+wire             F_op_ldbio;
+wire             F_op_ldbu;
+wire             F_op_ldbuio;
+wire             F_op_ldh;
+wire             F_op_ldhio;
+wire             F_op_ldhu;
+wire             F_op_ldhuio;
+wire             F_op_ldl;
+wire             F_op_ldw;
+wire             F_op_ldwio;
+wire             F_op_mul;
+wire             F_op_muli;
+wire             F_op_mulxss;
+wire             F_op_mulxsu;
+wire             F_op_mulxuu;
+wire             F_op_nextpc;
+wire             F_op_nor;
+wire             F_op_op_rsv02;
+wire             F_op_op_rsv09;
+wire             F_op_op_rsv10;
+wire             F_op_op_rsv17;
+wire             F_op_op_rsv18;
+wire             F_op_op_rsv25;
+wire             F_op_op_rsv26;
+wire             F_op_op_rsv33;
+wire             F_op_op_rsv34;
+wire             F_op_op_rsv41;
+wire             F_op_op_rsv42;
+wire             F_op_op_rsv49;
+wire             F_op_op_rsv57;
+wire             F_op_op_rsv61;
+wire             F_op_op_rsv62;
+wire             F_op_op_rsv63;
+wire             F_op_opx_rsv00;
+wire             F_op_opx_rsv10;
+wire             F_op_opx_rsv15;
+wire             F_op_opx_rsv17;
+wire             F_op_opx_rsv21;
+wire             F_op_opx_rsv25;
+wire             F_op_opx_rsv33;
+wire             F_op_opx_rsv34;
+wire             F_op_opx_rsv35;
+wire             F_op_opx_rsv42;
+wire             F_op_opx_rsv43;
+wire             F_op_opx_rsv44;
+wire             F_op_opx_rsv47;
+wire             F_op_opx_rsv50;
+wire             F_op_opx_rsv51;
+wire             F_op_opx_rsv55;
+wire             F_op_opx_rsv56;
+wire             F_op_opx_rsv60;
+wire             F_op_opx_rsv63;
+wire             F_op_or;
+wire             F_op_orhi;
+wire             F_op_ori;
+wire             F_op_rdctl;
+wire             F_op_rdprs;
+wire             F_op_ret;
+wire             F_op_rol;
+wire             F_op_roli;
+wire             F_op_ror;
+wire             F_op_sll;
+wire             F_op_slli;
+wire             F_op_sra;
+wire             F_op_srai;
+wire             F_op_srl;
+wire             F_op_srli;
+wire             F_op_stb;
+wire             F_op_stbio;
+wire             F_op_stc;
+wire             F_op_sth;
+wire             F_op_sthio;
+wire             F_op_stw;
+wire             F_op_stwio;
+wire             F_op_sub;
+wire             F_op_sync;
+wire             F_op_trap;
+wire             F_op_wrctl;
+wire             F_op_wrprs;
+wire             F_op_xor;
+wire             F_op_xorhi;
+wire             F_op_xori;
+reg     [ 17: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
+wire             F_pc_en;
+wire    [ 17: 0] F_pc_no_crst_nxt;
+wire    [ 17: 0] F_pc_nxt;
+wire    [ 17: 0] F_pc_plus_one;
+wire    [  1: 0] F_pc_sel_nxt;
+wire    [ 19: 0] F_pcb;
+wire    [ 19: 0] F_pcb_nxt;
+wire    [ 19: 0] F_pcb_plus_four;
+wire             F_valid;
+wire    [ 71: 0] F_vinst;
+reg     [  1: 0] R_compare_op;
+reg              R_ctrl_alu_force_and;
+wire             R_ctrl_alu_force_and_nxt;
+reg              R_ctrl_alu_force_xor;
+wire             R_ctrl_alu_force_xor_nxt;
+reg              R_ctrl_alu_signed_comparison;
+wire             R_ctrl_alu_signed_comparison_nxt;
+reg              R_ctrl_alu_subtract;
+wire             R_ctrl_alu_subtract_nxt;
+reg              R_ctrl_b_is_dst;
+wire             R_ctrl_b_is_dst_nxt;
+reg              R_ctrl_br;
+reg              R_ctrl_br_cmp;
+wire             R_ctrl_br_cmp_nxt;
+wire             R_ctrl_br_nxt;
+reg              R_ctrl_br_uncond;
+wire             R_ctrl_br_uncond_nxt;
+reg              R_ctrl_break;
+wire             R_ctrl_break_nxt;
+reg              R_ctrl_crst;
+wire             R_ctrl_crst_nxt;
+reg              R_ctrl_custom;
+reg              R_ctrl_custom_multi;
+wire             R_ctrl_custom_multi_nxt;
+wire             R_ctrl_custom_nxt;
+reg              R_ctrl_exception;
+wire             R_ctrl_exception_nxt;
+reg              R_ctrl_force_src2_zero;
+wire             R_ctrl_force_src2_zero_nxt;
+reg              R_ctrl_hi_imm16;
+wire             R_ctrl_hi_imm16_nxt;
+reg              R_ctrl_ignore_dst;
+wire             R_ctrl_ignore_dst_nxt;
+reg              R_ctrl_implicit_dst_eretaddr;
+wire             R_ctrl_implicit_dst_eretaddr_nxt;
+reg              R_ctrl_implicit_dst_retaddr;
+wire             R_ctrl_implicit_dst_retaddr_nxt;
+reg              R_ctrl_intr_inst;
+wire             R_ctrl_intr_inst_nxt;
+reg              R_ctrl_jmp_direct;
+wire             R_ctrl_jmp_direct_nxt;
+reg              R_ctrl_jmp_indirect;
+wire             R_ctrl_jmp_indirect_nxt;
+reg              R_ctrl_ld;
+reg              R_ctrl_ld_ex;
+wire             R_ctrl_ld_ex_nxt;
+reg              R_ctrl_ld_io;
+wire             R_ctrl_ld_io_nxt;
+reg              R_ctrl_ld_non_io;
+wire             R_ctrl_ld_non_io_nxt;
+wire             R_ctrl_ld_nxt;
+reg              R_ctrl_ld_signed;
+wire             R_ctrl_ld_signed_nxt;
+reg              R_ctrl_ld_st_ex;
+wire             R_ctrl_ld_st_ex_nxt;
+reg              R_ctrl_logic;
+wire             R_ctrl_logic_nxt;
+reg              R_ctrl_mem16;
+wire             R_ctrl_mem16_nxt;
+reg              R_ctrl_mem32;
+wire             R_ctrl_mem32_nxt;
+reg              R_ctrl_mem8;
+wire             R_ctrl_mem8_nxt;
+reg              R_ctrl_rd_ctl_reg;
+wire             R_ctrl_rd_ctl_reg_nxt;
+reg              R_ctrl_retaddr;
+wire             R_ctrl_retaddr_nxt;
+reg              R_ctrl_rot_right;
+wire             R_ctrl_rot_right_nxt;
+reg              R_ctrl_set_src2_rem_imm;
+wire             R_ctrl_set_src2_rem_imm_nxt;
+reg              R_ctrl_shift_logical;
+wire             R_ctrl_shift_logical_nxt;
+reg              R_ctrl_shift_right_arith;
+wire             R_ctrl_shift_right_arith_nxt;
+reg              R_ctrl_shift_rot;
+wire             R_ctrl_shift_rot_nxt;
+reg              R_ctrl_shift_rot_right;
+wire             R_ctrl_shift_rot_right_nxt;
+reg              R_ctrl_signed_imm12;
+wire             R_ctrl_signed_imm12_nxt;
+reg              R_ctrl_src2_choose_imm;
+wire             R_ctrl_src2_choose_imm_nxt;
+reg              R_ctrl_src_imm5_shift_rot;
+wire             R_ctrl_src_imm5_shift_rot_nxt;
+reg              R_ctrl_st;
+reg              R_ctrl_st_ex;
+wire             R_ctrl_st_ex_nxt;
+wire             R_ctrl_st_nxt;
+reg              R_ctrl_uncond_cti_non_br;
+wire             R_ctrl_uncond_cti_non_br_nxt;
+reg              R_ctrl_unsigned_lo_imm16;
+wire             R_ctrl_unsigned_lo_imm16_nxt;
+reg              R_ctrl_wrctl_inst;
+wire             R_ctrl_wrctl_inst_nxt;
+reg     [  4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
+wire             R_en;
+reg     [  1: 0] R_logic_op;
+wire    [ 31: 0] R_rf_a;
+wire    [ 31: 0] R_rf_a_q;
+wire    [ 31: 0] R_rf_b;
+wire    [ 31: 0] R_rf_b_q;
+wire    [ 31: 0] R_src1;
+wire    [ 31: 0] R_src2;
+wire    [ 15: 0] R_src2_hi;
+wire    [ 15: 0] R_src2_lo;
+reg              R_src2_use_imm;
+wire    [  7: 0] R_stb_data;
+wire    [ 15: 0] R_sth_data;
+wire    [ 31: 0] R_stw_data;
+reg              R_valid;
+wire    [ 71: 0] R_vinst;
+reg              R_wr_dst_reg;
+reg              W1_rf_ecc_recoverable_valid;
+reg     [ 31: 0] W_alu_result;
+wire             W_br_taken;
+reg              W_bstatus_reg;
+wire             W_bstatus_reg_inst_nxt;
+wire             W_bstatus_reg_nxt;
+reg     [ 31: 0] W_cdsr_reg;
+reg              W_cmp_result;
+reg     [ 31: 0] W_control_rd_data;
+wire    [ 31: 0] W_cpuid_reg;
+wire    [  4: 0] W_dst_regnum;
+reg              W_estatus_reg;
+wire             W_estatus_reg_inst_nxt;
+wire             W_estatus_reg_nxt;
+reg     [ 31: 0] W_ienable_reg;
+wire    [ 31: 0] W_ienable_reg_nxt;
+reg     [ 31: 0] W_ipending_reg;
+wire    [ 31: 0] W_ipending_reg_nxt;
+wire    [ 19: 0] W_mem_baddr;
+reg              W_rf_ecc_recoverable_valid;
+reg              W_rf_ecc_unrecoverable_valid;
+wire             W_rf_ecc_valid_any;
+wire    [ 31: 0] W_rf_wr_data;
+wire             W_rf_wren;
+wire             W_status_reg;
+reg              W_status_reg_pie;
+wire             W_status_reg_pie_inst_nxt;
+wire             W_status_reg_pie_nxt;
+reg              W_up_ex_mon_state;
+reg              W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
+wire             W_valid_from_M;
+wire    [ 71: 0] W_vinst;
+wire    [ 31: 0] W_wr_data;
+wire    [ 31: 0] W_wr_data_non_zero;
+wire             av_fill_bit;
+reg     [  1: 0] av_ld_align_cycle;
+wire    [  1: 0] av_ld_align_cycle_nxt;
+wire             av_ld_align_one_more_cycle;
+reg              av_ld_aligning_data;
+wire             av_ld_aligning_data_nxt;
+reg     [  7: 0] av_ld_byte0_data;
+wire    [  7: 0] av_ld_byte0_data_nxt;
+reg     [  7: 0] av_ld_byte1_data;
+wire             av_ld_byte1_data_en;
+wire    [  7: 0] av_ld_byte1_data_nxt;
+reg     [  7: 0] av_ld_byte2_data;
+wire    [  7: 0] av_ld_byte2_data_nxt;
+reg     [  7: 0] av_ld_byte3_data;
+wire    [  7: 0] av_ld_byte3_data_nxt;
+wire    [ 31: 0] av_ld_data_aligned_filtered;
+wire    [ 31: 0] av_ld_data_aligned_unfiltered;
+wire             av_ld_done;
+wire             av_ld_extend;
+wire             av_ld_getting_data;
+wire             av_ld_rshift8;
+reg              av_ld_waiting_for_data;
+wire             av_ld_waiting_for_data_nxt;
+wire             av_sign_bit;
+wire    [ 19: 0] d_address;
+reg     [  3: 0] d_byteenable;
+reg              d_read;
+wire             d_read_nxt;
+reg              d_write;
+wire             d_write_nxt;
+reg     [ 31: 0] d_writedata;
+wire             debug_mem_slave_clk;
+wire             debug_mem_slave_debugaccess_to_roms;
+wire    [ 31: 0] debug_mem_slave_readdata;
+wire             debug_mem_slave_reset;
+wire             debug_mem_slave_waitrequest;
+wire             debug_reset_request;
+wire             dummy_ci_port;
+reg              hbreak_enabled;
+reg              hbreak_pending;
+wire             hbreak_pending_nxt;
+wire             hbreak_req;
+wire    [ 19: 0] i_address;
+reg              i_read;
+wire             i_read_nxt;
+wire    [ 31: 0] iactive;
+wire             intr_req;
+wire             oci_hbreak_req;
+wire    [ 31: 0] oci_ienable;
+wire             oci_single_step_mode;
+wire             oci_tb_hbreak_req;
+wire             test_has_ended;
+reg              wait_for_one_post_bret_inst;
+  //the_nios2_uc_nios2_cpu_test_bench, which is an e_instance
+  nios2_uc_nios2_cpu_test_bench the_nios2_uc_nios2_cpu_test_bench
+    (
+      .D_iw                          (D_iw),
+      .D_iw_op                       (D_iw_op),
+      .D_iw_opx                      (D_iw_opx),
+      .D_valid                       (D_valid),
+      .E_valid                       (E_valid),
+      .F_pcb                         (F_pcb),
+      .F_valid                       (F_valid),
+      .R_ctrl_ld                     (R_ctrl_ld),
+      .R_ctrl_ld_non_io              (R_ctrl_ld_non_io),
+      .R_dst_regnum                  (R_dst_regnum),
+      .R_wr_dst_reg                  (R_wr_dst_reg),
+      .W_valid                       (W_valid),
+      .W_vinst                       (W_vinst),
+      .W_wr_data                     (W_wr_data),
+      .av_ld_data_aligned_filtered   (av_ld_data_aligned_filtered),
+      .av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
+      .clk                           (clk),
+      .d_address                     (d_address),
+      .d_byteenable                  (d_byteenable),
+      .d_read                        (d_read),
+      .d_write                       (d_write),
+      .i_address                     (i_address),
+      .i_read                        (i_read),
+      .i_readdata                    (i_readdata),
+      .i_waitrequest                 (i_waitrequest),
+      .reset_n                       (reset_n),
+      .test_has_ended                (test_has_ended)
+    );
+
+  assign F_av_iw_a = F_av_iw[31 : 27];
+  assign F_av_iw_b = F_av_iw[26 : 22];
+  assign F_av_iw_c = F_av_iw[21 : 17];
+  assign F_av_iw_custom_n = F_av_iw[13 : 6];
+  assign F_av_iw_custom_readra = F_av_iw[16];
+  assign F_av_iw_custom_readrb = F_av_iw[15];
+  assign F_av_iw_custom_writerc = F_av_iw[14];
+  assign F_av_iw_opx = F_av_iw[16 : 11];
+  assign F_av_iw_op = F_av_iw[5 : 0];
+  assign F_av_iw_imm5 = F_av_iw[10 : 6];
+  assign F_av_iw_imm16 = F_av_iw[21 : 6];
+  assign F_av_iw_imm26 = F_av_iw[31 : 6];
+  assign F_av_iw_memsz = F_av_iw[4 : 3];
+  assign F_av_iw_control_regnum = F_av_iw[10 : 6];
+  assign F_av_mem8 = F_av_iw_memsz == 2'b00;
+  assign F_av_mem16 = F_av_iw_memsz == 2'b01;
+  assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
+  assign F_iw_a = F_iw[31 : 27];
+  assign F_iw_b = F_iw[26 : 22];
+  assign F_iw_c = F_iw[21 : 17];
+  assign F_iw_custom_n = F_iw[13 : 6];
+  assign F_iw_custom_readra = F_iw[16];
+  assign F_iw_custom_readrb = F_iw[15];
+  assign F_iw_custom_writerc = F_iw[14];
+  assign F_iw_opx = F_iw[16 : 11];
+  assign F_iw_op = F_iw[5 : 0];
+  assign F_iw_imm5 = F_iw[10 : 6];
+  assign F_iw_imm16 = F_iw[21 : 6];
+  assign F_iw_imm26 = F_iw[31 : 6];
+  assign F_iw_memsz = F_iw[4 : 3];
+  assign F_iw_control_regnum = F_iw[10 : 6];
+  assign F_mem8 = F_iw_memsz == 2'b00;
+  assign F_mem16 = F_iw_memsz == 2'b01;
+  assign F_mem32 = F_iw_memsz[1] == 1'b1;
+  assign D_iw_a = D_iw[31 : 27];
+  assign D_iw_b = D_iw[26 : 22];
+  assign D_iw_c = D_iw[21 : 17];
+  assign D_iw_custom_n = D_iw[13 : 6];
+  assign D_iw_custom_readra = D_iw[16];
+  assign D_iw_custom_readrb = D_iw[15];
+  assign D_iw_custom_writerc = D_iw[14];
+  assign D_iw_opx = D_iw[16 : 11];
+  assign D_iw_op = D_iw[5 : 0];
+  assign D_iw_imm5 = D_iw[10 : 6];
+  assign D_iw_imm16 = D_iw[21 : 6];
+  assign D_iw_imm26 = D_iw[31 : 6];
+  assign D_iw_memsz = D_iw[4 : 3];
+  assign D_iw_control_regnum = D_iw[10 : 6];
+  assign D_mem8 = D_iw_memsz == 2'b00;
+  assign D_mem16 = D_iw_memsz == 2'b01;
+  assign D_mem32 = D_iw_memsz[1] == 1'b1;
+  assign F_op_call = F_iw_op == 0;
+  assign F_op_jmpi = F_iw_op == 1;
+  assign F_op_op_rsv02 = F_iw_op == 2;
+  assign F_op_ldbu = F_iw_op == 3;
+  assign F_op_addi = F_iw_op == 4;
+  assign F_op_stb = F_iw_op == 5;
+  assign F_op_br = F_iw_op == 6;
+  assign F_op_ldb = F_iw_op == 7;
+  assign F_op_cmpgei = F_iw_op == 8;
+  assign F_op_op_rsv09 = F_iw_op == 9;
+  assign F_op_op_rsv10 = F_iw_op == 10;
+  assign F_op_ldhu = F_iw_op == 11;
+  assign F_op_andi = F_iw_op == 12;
+  assign F_op_sth = F_iw_op == 13;
+  assign F_op_bge = F_iw_op == 14;
+  assign F_op_ldh = F_iw_op == 15;
+  assign F_op_cmplti = F_iw_op == 16;
+  assign F_op_op_rsv17 = F_iw_op == 17;
+  assign F_op_op_rsv18 = F_iw_op == 18;
+  assign F_op_initda = F_iw_op == 19;
+  assign F_op_ori = F_iw_op == 20;
+  assign F_op_stw = F_iw_op == 21;
+  assign F_op_blt = F_iw_op == 22;
+  assign F_op_ldw = F_iw_op == 23;
+  assign F_op_cmpnei = F_iw_op == 24;
+  assign F_op_op_rsv25 = F_iw_op == 25;
+  assign F_op_op_rsv26 = F_iw_op == 26;
+  assign F_op_flushda = F_iw_op == 27;
+  assign F_op_xori = F_iw_op == 28;
+  assign F_op_stc = F_iw_op == 29;
+  assign F_op_bne = F_iw_op == 30;
+  assign F_op_ldl = F_iw_op == 31;
+  assign F_op_cmpeqi = F_iw_op == 32;
+  assign F_op_op_rsv33 = F_iw_op == 33;
+  assign F_op_op_rsv34 = F_iw_op == 34;
+  assign F_op_ldbuio = F_iw_op == 35;
+  assign F_op_muli = F_iw_op == 36;
+  assign F_op_stbio = F_iw_op == 37;
+  assign F_op_beq = F_iw_op == 38;
+  assign F_op_ldbio = F_iw_op == 39;
+  assign F_op_cmpgeui = F_iw_op == 40;
+  assign F_op_op_rsv41 = F_iw_op == 41;
+  assign F_op_op_rsv42 = F_iw_op == 42;
+  assign F_op_ldhuio = F_iw_op == 43;
+  assign F_op_andhi = F_iw_op == 44;
+  assign F_op_sthio = F_iw_op == 45;
+  assign F_op_bgeu = F_iw_op == 46;
+  assign F_op_ldhio = F_iw_op == 47;
+  assign F_op_cmpltui = F_iw_op == 48;
+  assign F_op_op_rsv49 = F_iw_op == 49;
+  assign F_op_custom = F_iw_op == 50;
+  assign F_op_initd = F_iw_op == 51;
+  assign F_op_orhi = F_iw_op == 52;
+  assign F_op_stwio = F_iw_op == 53;
+  assign F_op_bltu = F_iw_op == 54;
+  assign F_op_ldwio = F_iw_op == 55;
+  assign F_op_rdprs = F_iw_op == 56;
+  assign F_op_op_rsv57 = F_iw_op == 57;
+  assign F_op_flushd = F_iw_op == 59;
+  assign F_op_xorhi = F_iw_op == 60;
+  assign F_op_op_rsv61 = F_iw_op == 61;
+  assign F_op_op_rsv62 = F_iw_op == 62;
+  assign F_op_op_rsv63 = F_iw_op == 63;
+  assign F_op_opx_rsv00 = (F_iw_opx == 0) & F_is_opx_inst;
+  assign F_op_eret = (F_iw_opx == 1) & F_is_opx_inst;
+  assign F_op_roli = (F_iw_opx == 2) & F_is_opx_inst;
+  assign F_op_rol = (F_iw_opx == 3) & F_is_opx_inst;
+  assign F_op_flushp = (F_iw_opx == 4) & F_is_opx_inst;
+  assign F_op_ret = (F_iw_opx == 5) & F_is_opx_inst;
+  assign F_op_nor = (F_iw_opx == 6) & F_is_opx_inst;
+  assign F_op_mulxuu = (F_iw_opx == 7) & F_is_opx_inst;
+  assign F_op_cmpge = (F_iw_opx == 8) & F_is_opx_inst;
+  assign F_op_bret = (F_iw_opx == 9) & F_is_opx_inst;
+  assign F_op_opx_rsv10 = (F_iw_opx == 10) & F_is_opx_inst;
+  assign F_op_ror = (F_iw_opx == 11) & F_is_opx_inst;
+  assign F_op_flushi = (F_iw_opx == 12) & F_is_opx_inst;
+  assign F_op_jmp = (F_iw_opx == 13) & F_is_opx_inst;
+  assign F_op_and = (F_iw_opx == 14) & F_is_opx_inst;
+  assign F_op_opx_rsv15 = (F_iw_opx == 15) & F_is_opx_inst;
+  assign F_op_cmplt = (F_iw_opx == 16) & F_is_opx_inst;
+  assign F_op_opx_rsv17 = (F_iw_opx == 17) & F_is_opx_inst;
+  assign F_op_slli = (F_iw_opx == 18) & F_is_opx_inst;
+  assign F_op_sll = (F_iw_opx == 19) & F_is_opx_inst;
+  assign F_op_wrprs = (F_iw_opx == 20) & F_is_opx_inst;
+  assign F_op_opx_rsv21 = (F_iw_opx == 21) & F_is_opx_inst;
+  assign F_op_or = (F_iw_opx == 22) & F_is_opx_inst;
+  assign F_op_mulxsu = (F_iw_opx == 23) & F_is_opx_inst;
+  assign F_op_cmpne = (F_iw_opx == 24) & F_is_opx_inst;
+  assign F_op_opx_rsv25 = (F_iw_opx == 25) & F_is_opx_inst;
+  assign F_op_srli = (F_iw_opx == 26) & F_is_opx_inst;
+  assign F_op_srl = (F_iw_opx == 27) & F_is_opx_inst;
+  assign F_op_nextpc = (F_iw_opx == 28) & F_is_opx_inst;
+  assign F_op_callr = (F_iw_opx == 29) & F_is_opx_inst;
+  assign F_op_xor = (F_iw_opx == 30) & F_is_opx_inst;
+  assign F_op_mulxss = (F_iw_opx == 31) & F_is_opx_inst;
+  assign F_op_cmpeq = (F_iw_opx == 32) & F_is_opx_inst;
+  assign F_op_opx_rsv33 = (F_iw_opx == 33) & F_is_opx_inst;
+  assign F_op_opx_rsv34 = (F_iw_opx == 34) & F_is_opx_inst;
+  assign F_op_opx_rsv35 = (F_iw_opx == 35) & F_is_opx_inst;
+  assign F_op_divu = (F_iw_opx == 36) & F_is_opx_inst;
+  assign F_op_div = (F_iw_opx == 37) & F_is_opx_inst;
+  assign F_op_rdctl = (F_iw_opx == 38) & F_is_opx_inst;
+  assign F_op_mul = (F_iw_opx == 39) & F_is_opx_inst;
+  assign F_op_cmpgeu = (F_iw_opx == 40) & F_is_opx_inst;
+  assign F_op_initi = (F_iw_opx == 41) & F_is_opx_inst;
+  assign F_op_opx_rsv42 = (F_iw_opx == 42) & F_is_opx_inst;
+  assign F_op_opx_rsv43 = (F_iw_opx == 43) & F_is_opx_inst;
+  assign F_op_opx_rsv44 = (F_iw_opx == 44) & F_is_opx_inst;
+  assign F_op_trap = (F_iw_opx == 45) & F_is_opx_inst;
+  assign F_op_wrctl = (F_iw_opx == 46) & F_is_opx_inst;
+  assign F_op_opx_rsv47 = (F_iw_opx == 47) & F_is_opx_inst;
+  assign F_op_cmpltu = (F_iw_opx == 48) & F_is_opx_inst;
+  assign F_op_add = (F_iw_opx == 49) & F_is_opx_inst;
+  assign F_op_opx_rsv50 = (F_iw_opx == 50) & F_is_opx_inst;
+  assign F_op_opx_rsv51 = (F_iw_opx == 51) & F_is_opx_inst;
+  assign F_op_break = (F_iw_opx == 52) & F_is_opx_inst;
+  assign F_op_hbreak = (F_iw_opx == 53) & F_is_opx_inst;
+  assign F_op_sync = (F_iw_opx == 54) & F_is_opx_inst;
+  assign F_op_opx_rsv55 = (F_iw_opx == 55) & F_is_opx_inst;
+  assign F_op_opx_rsv56 = (F_iw_opx == 56) & F_is_opx_inst;
+  assign F_op_sub = (F_iw_opx == 57) & F_is_opx_inst;
+  assign F_op_srai = (F_iw_opx == 58) & F_is_opx_inst;
+  assign F_op_sra = (F_iw_opx == 59) & F_is_opx_inst;
+  assign F_op_opx_rsv60 = (F_iw_opx == 60) & F_is_opx_inst;
+  assign F_op_intr = (F_iw_opx == 61) & F_is_opx_inst;
+  assign F_op_crst = (F_iw_opx == 62) & F_is_opx_inst;
+  assign F_op_opx_rsv63 = (F_iw_opx == 63) & F_is_opx_inst;
+  assign F_is_opx_inst = F_iw_op == 58;
+  assign D_op_call = D_iw_op == 0;
+  assign D_op_jmpi = D_iw_op == 1;
+  assign D_op_op_rsv02 = D_iw_op == 2;
+  assign D_op_ldbu = D_iw_op == 3;
+  assign D_op_addi = D_iw_op == 4;
+  assign D_op_stb = D_iw_op == 5;
+  assign D_op_br = D_iw_op == 6;
+  assign D_op_ldb = D_iw_op == 7;
+  assign D_op_cmpgei = D_iw_op == 8;
+  assign D_op_op_rsv09 = D_iw_op == 9;
+  assign D_op_op_rsv10 = D_iw_op == 10;
+  assign D_op_ldhu = D_iw_op == 11;
+  assign D_op_andi = D_iw_op == 12;
+  assign D_op_sth = D_iw_op == 13;
+  assign D_op_bge = D_iw_op == 14;
+  assign D_op_ldh = D_iw_op == 15;
+  assign D_op_cmplti = D_iw_op == 16;
+  assign D_op_op_rsv17 = D_iw_op == 17;
+  assign D_op_op_rsv18 = D_iw_op == 18;
+  assign D_op_initda = D_iw_op == 19;
+  assign D_op_ori = D_iw_op == 20;
+  assign D_op_stw = D_iw_op == 21;
+  assign D_op_blt = D_iw_op == 22;
+  assign D_op_ldw = D_iw_op == 23;
+  assign D_op_cmpnei = D_iw_op == 24;
+  assign D_op_op_rsv25 = D_iw_op == 25;
+  assign D_op_op_rsv26 = D_iw_op == 26;
+  assign D_op_flushda = D_iw_op == 27;
+  assign D_op_xori = D_iw_op == 28;
+  assign D_op_stc = D_iw_op == 29;
+  assign D_op_bne = D_iw_op == 30;
+  assign D_op_ldl = D_iw_op == 31;
+  assign D_op_cmpeqi = D_iw_op == 32;
+  assign D_op_op_rsv33 = D_iw_op == 33;
+  assign D_op_op_rsv34 = D_iw_op == 34;
+  assign D_op_ldbuio = D_iw_op == 35;
+  assign D_op_muli = D_iw_op == 36;
+  assign D_op_stbio = D_iw_op == 37;
+  assign D_op_beq = D_iw_op == 38;
+  assign D_op_ldbio = D_iw_op == 39;
+  assign D_op_cmpgeui = D_iw_op == 40;
+  assign D_op_op_rsv41 = D_iw_op == 41;
+  assign D_op_op_rsv42 = D_iw_op == 42;
+  assign D_op_ldhuio = D_iw_op == 43;
+  assign D_op_andhi = D_iw_op == 44;
+  assign D_op_sthio = D_iw_op == 45;
+  assign D_op_bgeu = D_iw_op == 46;
+  assign D_op_ldhio = D_iw_op == 47;
+  assign D_op_cmpltui = D_iw_op == 48;
+  assign D_op_op_rsv49 = D_iw_op == 49;
+  assign D_op_custom = D_iw_op == 50;
+  assign D_op_initd = D_iw_op == 51;
+  assign D_op_orhi = D_iw_op == 52;
+  assign D_op_stwio = D_iw_op == 53;
+  assign D_op_bltu = D_iw_op == 54;
+  assign D_op_ldwio = D_iw_op == 55;
+  assign D_op_rdprs = D_iw_op == 56;
+  assign D_op_op_rsv57 = D_iw_op == 57;
+  assign D_op_flushd = D_iw_op == 59;
+  assign D_op_xorhi = D_iw_op == 60;
+  assign D_op_op_rsv61 = D_iw_op == 61;
+  assign D_op_op_rsv62 = D_iw_op == 62;
+  assign D_op_op_rsv63 = D_iw_op == 63;
+  assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
+  assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
+  assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
+  assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
+  assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
+  assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
+  assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
+  assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
+  assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
+  assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
+  assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
+  assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
+  assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
+  assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
+  assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
+  assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
+  assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
+  assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
+  assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
+  assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
+  assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
+  assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
+  assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
+  assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
+  assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
+  assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
+  assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
+  assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
+  assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
+  assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
+  assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
+  assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
+  assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
+  assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
+  assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
+  assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
+  assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
+  assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
+  assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
+  assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
+  assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
+  assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
+  assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
+  assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
+  assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
+  assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
+  assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
+  assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
+  assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
+  assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
+  assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
+  assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
+  assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
+  assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
+  assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
+  assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
+  assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
+  assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
+  assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
+  assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
+  assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
+  assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
+  assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
+  assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
+  assign D_is_opx_inst = D_iw_op == 58;
+  assign R_en = 1'b1;
+  assign E_ci_result = 0;
+  //custom_instruction_master, which is an e_custom_instruction_master
+  assign dummy_ci_port = 1'b0;
+  assign E_ci_multi_stall = 1'b0;
+  assign iactive = irq[31 : 0] & 32'b00000000000000000000000000000001;
+  assign F_pc_sel_nxt = (R_ctrl_exception | W_rf_ecc_unrecoverable_valid) ? 2'b00 :
+    R_ctrl_break                              ? 2'b01 :
+    (W_br_taken | R_ctrl_uncond_cti_non_br)   ? 2'b10 :
+    2'b11;
+
+  assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 65544 :
+    (F_pc_sel_nxt == 2'b01)? 131592 :
+    (F_pc_sel_nxt == 2'b10)? E_arith_result[19 : 2] :
+    F_pc_plus_one;
+
+  assign F_pc_nxt = F_pc_no_crst_nxt;
+  assign F_pcb_nxt = {F_pc_nxt, 2'b00};
+  assign F_pc_en = W_valid | W_rf_ecc_unrecoverable_valid;
+  assign F_pc_plus_one = F_pc + 1;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          F_pc <= 65536;
+      else if (F_pc_en)
+          F_pc <= F_pc_nxt;
+    end
+
+
+  assign F_pcb = {F_pc, 2'b00};
+  assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
+  assign F_valid = i_read & ~i_waitrequest;
+  assign i_read_nxt = W_valid | W_rf_ecc_unrecoverable_valid | (i_read & i_waitrequest);
+  assign i_address = {F_pc, 2'b00};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          i_read <= 1'b1;
+      else 
+        i_read <= i_read_nxt;
+    end
+
+
+  assign oci_tb_hbreak_req = oci_hbreak_req;
+  assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled &  ~(wait_for_one_post_bret_inst & ~W_valid);
+  assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled 
+    : hbreak_req;
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          wait_for_one_post_bret_inst <= 1'b0;
+      else 
+        wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1  : (F_valid | ~oci_single_step_mode) ? 1'b0  : wait_for_one_post_bret_inst;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          hbreak_pending <= 1'b0;
+      else 
+        hbreak_pending <= hbreak_pending_nxt;
+    end
+
+
+  assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
+  assign F_av_iw = i_readdata;
+  assign F_iw = hbreak_req     ? 4040762 :
+    1'b0   ? 127034 :
+    intr_req       ? 3926074 : 
+    F_av_iw;
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_iw <= 0;
+      else if (F_valid)
+          D_iw <= F_iw;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          D_valid <= 0;
+      else 
+        D_valid <= F_valid | W1_rf_ecc_recoverable_valid;
+    end
+
+
+  assign D_dst_regnum = D_ctrl_implicit_dst_retaddr    ? 5'd31 : 
+    D_ctrl_implicit_dst_eretaddr   ? 5'd29 : 
+    D_ctrl_b_is_dst                ? D_iw_b :
+    D_iw_c;
+
+  assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
+  assign D_logic_op_raw = D_is_opx_inst ? D_iw_opx[4 : 3] :
+    D_iw_op[4 : 3];
+
+  assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : 
+    D_ctrl_alu_force_and ? 2'b01 :
+    D_logic_op_raw;
+
+  assign D_compare_op = D_is_opx_inst ? D_iw_opx[4 : 3] : 
+    D_iw_op[4 : 3];
+
+  assign D_jmp_direct_target_waddr = D_iw[31 : 6];
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_valid <= 0;
+      else 
+        R_valid <= D_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_wr_dst_reg <= 0;
+      else 
+        R_wr_dst_reg <= D_wr_dst_reg;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_dst_regnum <= 0;
+      else 
+        R_dst_regnum <= D_dst_regnum;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_logic_op <= 0;
+      else 
+        R_logic_op <= D_logic_op;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_compare_op <= 0;
+      else 
+        R_compare_op <= D_compare_op;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_src2_use_imm <= 0;
+      else 
+        R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
+    end
+
+
+  assign E_rf_ecc_valid_any = E_rf_ecc_recoverable_valid|E_rf_ecc_unrecoverable_valid;
+  assign W_rf_ecc_valid_any = W_rf_ecc_recoverable_valid|W_rf_ecc_unrecoverable_valid;
+  assign E_rf_ecc_recoverable_valid = 1'b0;
+  assign E_rf_ecc_unrecoverable_valid = 1'b0;
+  assign W_dst_regnum = R_dst_regnum;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_rf_ecc_recoverable_valid <= 0;
+      else 
+        W_rf_ecc_recoverable_valid <= E_rf_ecc_recoverable_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W1_rf_ecc_recoverable_valid <= 0;
+      else 
+        W1_rf_ecc_recoverable_valid <= W_rf_ecc_recoverable_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_rf_ecc_unrecoverable_valid <= 0;
+      else 
+        W_rf_ecc_unrecoverable_valid <= E_rf_ecc_unrecoverable_valid & ~E_rf_ecc_recoverable_valid;
+    end
+
+
+  assign R_rf_a = R_rf_a_q;
+  assign R_rf_b = R_rf_b_q;
+  assign W_rf_wren = (R_wr_dst_reg & W_valid) | W_rf_ecc_valid_any | ~reset_n;
+  assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
+//nios2_uc_nios2_cpu_register_bank_a, which is an nios_sdp_ram
+nios2_uc_nios2_cpu_register_bank_a_module nios2_uc_nios2_cpu_register_bank_a
+  (
+    .clock     (clk),
+    .data      (W_rf_wr_data),
+    .q         (R_rf_a_q),
+    .rdaddress (D_iw_a),
+    .wraddress (W_dst_regnum),
+    .wren      (W_rf_wren)
+  );
+
+//synthesis translate_off
+`ifdef NO_PLI
+defparam nios2_uc_nios2_cpu_register_bank_a.lpm_file = "nios2_uc_nios2_cpu_rf_ram_a.dat";
+`else
+defparam nios2_uc_nios2_cpu_register_bank_a.lpm_file = "nios2_uc_nios2_cpu_rf_ram_a.hex";
+`endif
+//synthesis translate_on
+//nios2_uc_nios2_cpu_register_bank_b, which is an nios_sdp_ram
+nios2_uc_nios2_cpu_register_bank_b_module nios2_uc_nios2_cpu_register_bank_b
+  (
+    .clock     (clk),
+    .data      (W_rf_wr_data),
+    .q         (R_rf_b_q),
+    .rdaddress (D_iw_b),
+    .wraddress (W_dst_regnum),
+    .wren      (W_rf_wren)
+  );
+
+//synthesis translate_off
+`ifdef NO_PLI
+defparam nios2_uc_nios2_cpu_register_bank_b.lpm_file = "nios2_uc_nios2_cpu_rf_ram_b.dat";
+`else
+defparam nios2_uc_nios2_cpu_register_bank_b.lpm_file = "nios2_uc_nios2_cpu_rf_ram_b.hex";
+`endif
+//synthesis translate_on
+  assign R_src1 = (((R_ctrl_br & E_valid_from_R) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
+    ((R_ctrl_jmp_direct & E_valid_from_R))? {D_jmp_direct_target_waddr, 2'b00} :
+    R_rf_a;
+
+  assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? {16 {D_ctrl_set_src2_rem_imm}} :
+    (R_ctrl_src_imm5_shift_rot)? {{11 {1'b0}},D_iw_imm5} :
+    (R_src2_use_imm)? D_iw_imm16 :
+    R_rf_b[15 : 0];
+
+  assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? {16 {D_ctrl_set_src2_rem_imm}} :
+    (R_ctrl_hi_imm16)? D_iw_imm16 :
+    (R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
+    R_rf_b[31 : 16];
+
+  assign R_src2 = {R_src2_hi, R_src2_lo};
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_valid_from_R <= 0;
+      else 
+        E_valid_from_R <= R_valid | E_stall;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_new_inst <= 0;
+      else 
+        E_new_inst <= R_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_src1 <= 0;
+      else 
+        E_src1 <= R_src1;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_src2 <= 0;
+      else 
+        E_src2 <= R_src2;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_invert_arith_src_msb <= 0;
+      else 
+        E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_alu_sub <= 0;
+      else 
+        E_alu_sub <= D_ctrl_alu_subtract & R_valid;
+    end
+
+
+  assign E_valid = E_valid_from_R & ~E_rf_ecc_valid_any;
+  assign E_stall = (E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall) & ~(E_rf_ecc_valid_any|W_rf_ecc_valid_any|W1_rf_ecc_recoverable_valid);
+  assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb, 
+    E_src1[30 : 0]};
+
+  assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb, 
+    E_src2[30 : 0]};
+
+  assign E_arith_result = E_alu_sub ?
+    E_arith_src1 - E_arith_src2 :
+    E_arith_src1 + E_arith_src2;
+
+  assign E_mem_baddr = E_arith_result[19 : 0];
+  assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
+    (R_logic_op == 2'b01)? (E_src1 & E_src2) :
+    (R_logic_op == 2'b10)? (E_src1 | E_src2) :
+    (E_src1 ^ E_src2);
+
+  assign E_logic_result_is_0 = E_logic_result == 0;
+  assign E_eq = E_logic_result_is_0;
+  assign E_lt = E_arith_result[32];
+  assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
+    (R_compare_op == 2'b01)? ~E_lt :
+    (R_compare_op == 2'b10)? E_lt :
+    ~E_eq;
+
+  assign E_shift_rot_shfcnt = E_src2[4 : 0];
+  assign E_shift_rot_cnt_nxt = E_new_inst ? E_shift_rot_shfcnt : E_shift_rot_cnt-1;
+  assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
+  assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
+  assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
+    (R_ctrl_rot_right ? E_shift_rot_result[0] : 
+    E_shift_rot_result[31]);
+
+  assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
+    (R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
+    {E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_shift_rot_result <= 0;
+      else 
+        E_shift_rot_result <= E_shift_rot_result_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          E_shift_rot_cnt <= 0;
+      else 
+        E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
+    end
+
+
+  assign E_control_rd_data = (D_iw_control_regnum == 5'd0)? W_status_reg :
+    (D_iw_control_regnum == 5'd1)? W_estatus_reg :
+    (D_iw_control_regnum == 5'd2)? W_bstatus_reg :
+    (D_iw_control_regnum == 5'd3)? W_ienable_reg :
+    (D_iw_control_regnum == 5'd4)? W_ipending_reg :
+    (D_iw_control_regnum == 5'd5)? W_cpuid_reg :
+    W_cdsr_reg;
+
+  assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rd_ctl_reg))? 0 :
+    (R_ctrl_shift_rot)? E_shift_rot_result :
+    (R_ctrl_logic)? E_logic_result :
+    (R_ctrl_custom)? E_ci_result :
+    E_arith_result;
+
+  assign R_sth_data = R_rf_b[15 : 0];
+  assign R_stw_data = R_rf_b[31 : 0];
+  assign R_stb_data = R_rf_b[7 : 0];
+  assign E_st_data = (D_ctrl_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
+    (D_ctrl_mem16)? {R_sth_data, R_sth_data} :
+    R_stw_data;
+
+  assign E_mem_byte_en = ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0001 :
+    ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0010 :
+    ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b0100 :
+    ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1000 :
+    ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b00})? 4'b0011 :
+    ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b01})? 4'b0011 :
+    ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b10})? 4'b1100 :
+    ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b11})? 4'b1100 :
+    4'b1111;
+
+  assign d_read_nxt = (R_ctrl_ld & E_new_inst & ~E_rf_ecc_valid_any) | (d_read & d_waitrequest);
+  assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
+  assign d_write_nxt = ((R_ctrl_st & (~R_ctrl_st_ex | W_up_ex_mon_state)) & E_new_inst & ~E_rf_ecc_valid_any) | (d_write & d_waitrequest);
+  assign E_st_stall = d_write_nxt;
+  assign d_address = W_mem_baddr;
+  assign av_ld_getting_data = d_read & ~d_waitrequest;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d_read <= 0;
+      else 
+        d_read <= d_read_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d_writedata <= 0;
+      else 
+        d_writedata <= E_st_data;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d_byteenable <= 0;
+      else 
+        d_byteenable <= E_mem_byte_en;
+    end
+
+
+  assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
+  assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_ctrl_mem16 ? 2 : 3);
+  assign av_ld_aligning_data_nxt = av_ld_aligning_data ? 
+    ~av_ld_align_one_more_cycle : 
+    (~D_ctrl_mem32 & av_ld_getting_data);
+
+  assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ? 
+    ~av_ld_getting_data : 
+    (R_ctrl_ld & E_new_inst);
+
+  assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_ctrl_mem32 | ~av_ld_aligning_data_nxt);
+  assign av_ld_rshift8 = av_ld_aligning_data & 
+    (av_ld_align_cycle < (W_mem_baddr[1 : 0]));
+
+  assign av_ld_extend = av_ld_aligning_data;
+  assign av_ld_byte0_data_nxt = av_ld_rshift8      ? av_ld_byte1_data :
+    av_ld_extend       ? av_ld_byte0_data :d_readdata[7 : 0];
+
+  assign av_ld_byte1_data_nxt = av_ld_rshift8      ? av_ld_byte2_data :
+    av_ld_extend       ? {8 {av_fill_bit}} :d_readdata[15 : 8];
+
+  assign av_ld_byte2_data_nxt = av_ld_rshift8      ? av_ld_byte3_data :
+    av_ld_extend       ? {8 {av_fill_bit}} :d_readdata[23 : 16];
+
+  assign av_ld_byte3_data_nxt = av_ld_rshift8      ? av_ld_byte3_data :
+    av_ld_extend       ? {8 {av_fill_bit}} :d_readdata[31 : 24];
+
+  assign av_ld_byte1_data_en = ~(av_ld_extend & D_ctrl_mem16 & ~av_ld_rshift8);
+  assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data, 
+    av_ld_byte1_data, av_ld_byte0_data};
+
+  assign av_sign_bit = D_ctrl_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
+  assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          av_ld_align_cycle <= 0;
+      else 
+        av_ld_align_cycle <= av_ld_align_cycle_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          av_ld_waiting_for_data <= 0;
+      else 
+        av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          av_ld_aligning_data <= 0;
+      else 
+        av_ld_aligning_data <= av_ld_aligning_data_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          av_ld_byte0_data <= 0;
+      else 
+        av_ld_byte0_data <= av_ld_byte0_data_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          av_ld_byte1_data <= 0;
+      else if (av_ld_byte1_data_en)
+          av_ld_byte1_data <= av_ld_byte1_data_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          av_ld_byte2_data <= 0;
+      else 
+        av_ld_byte2_data <= av_ld_byte2_data_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          av_ld_byte3_data <= 0;
+      else 
+        av_ld_byte3_data <= av_ld_byte3_data_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_up_ex_mon_state <= 0;
+      else if (R_en)
+          W_up_ex_mon_state <= (R_ctrl_ld_ex & W_valid) ? 1'b1 :
+                    ((D_op_eret & W_valid) | (R_ctrl_st_ex & W_valid)) ? 1'b0 : 
+                    W_up_ex_mon_state;
+
+    end
+
+
+  assign W_valid_from_M = W_valid;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_valid <= 0;
+      else 
+        W_valid <= E_valid & ~E_stall;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          A_valid_from_M <= 0;
+      else 
+        A_valid_from_M <= E_valid & ~E_stall;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_control_rd_data <= 0;
+      else 
+        W_control_rd_data <= D_ctrl_intr_inst ? W_status_reg : E_control_rd_data;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_cmp_result <= 0;
+      else 
+        W_cmp_result <= E_cmp_result;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_alu_result <= 0;
+      else 
+        W_alu_result <= E_alu_result;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_status_reg_pie <= 0;
+      else 
+        W_status_reg_pie <= W_status_reg_pie_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_estatus_reg <= 0;
+      else 
+        W_estatus_reg <= W_estatus_reg_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_bstatus_reg <= 0;
+      else 
+        W_bstatus_reg <= W_bstatus_reg_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ienable_reg <= 0;
+      else 
+        W_ienable_reg <= W_ienable_reg_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_ipending_reg <= 0;
+      else 
+        W_ipending_reg <= W_ipending_reg_nxt;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          W_cdsr_reg <= 0;
+      else 
+        W_cdsr_reg <= 0;
+    end
+
+
+  assign W_cpuid_reg = 0;
+  assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
+    R_ctrl_rd_ctl_reg       ? W_control_rd_data :
+    W_alu_result[31 : 0];
+
+  assign W_wr_data = W_wr_data_non_zero;
+  assign W_br_taken = R_ctrl_br_uncond | (R_ctrl_br & W_cmp_result);
+  assign W_mem_baddr = W_alu_result[19 : 0];
+  assign W_status_reg = W_status_reg_pie;
+  assign E_wrctl_status = R_ctrl_wrctl_inst & 
+    (D_iw_control_regnum == 5'd0);
+
+  assign E_wrctl_estatus = R_ctrl_wrctl_inst & 
+    (D_iw_control_regnum == 5'd1);
+
+  assign E_wrctl_bstatus = R_ctrl_wrctl_inst & 
+    (D_iw_control_regnum == 5'd2);
+
+  assign E_wrctl_ienable = R_ctrl_wrctl_inst & 
+    (D_iw_control_regnum == 5'd3);
+
+  assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst | W_rf_ecc_unrecoverable_valid) ? 1'b0 :
+    (D_op_eret)                     ? W_estatus_reg :
+    (D_op_bret)                     ? W_bstatus_reg :
+    (E_wrctl_status)                ? E_src1[0] :
+    W_status_reg_pie;
+
+  assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
+  assign W_estatus_reg_inst_nxt = (R_ctrl_crst)        ? 0 :
+    (R_ctrl_exception|W_rf_ecc_unrecoverable_valid)   ? W_status_reg :
+    (E_wrctl_estatus)    ? E_src1[0] :
+    W_estatus_reg;
+
+  assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
+  assign W_bstatus_reg_inst_nxt = (R_ctrl_break)       ? W_status_reg :
+    (E_wrctl_bstatus)    ? E_src1[0] :
+    W_bstatus_reg;
+
+  assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
+  assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ? 
+    E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000000001;
+
+  assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000000001;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          hbreak_enabled <= 1'b1;
+      else if (E_valid)
+          hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          d_write <= 0;
+      else 
+        d_write <= d_write_nxt;
+    end
+
+
+  nios2_uc_nios2_cpu_nios2_oci the_nios2_uc_nios2_cpu_nios2_oci
+    (
+      .D_valid                             (D_valid),
+      .E_st_data                           (E_st_data),
+      .E_valid                             (E_valid),
+      .F_pc                                (F_pc),
+      .address_nxt                         (debug_mem_slave_address),
+      .av_ld_data_aligned_filtered         (av_ld_data_aligned_filtered),
+      .byteenable_nxt                      (debug_mem_slave_byteenable),
+      .clk                                 (debug_mem_slave_clk),
+      .d_address                           (d_address),
+      .d_read                              (d_read),
+      .d_waitrequest                       (d_waitrequest),
+      .d_write                             (d_write),
+      .debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms),
+      .debugaccess_nxt                     (debug_mem_slave_debugaccess),
+      .hbreak_enabled                      (hbreak_enabled),
+      .oci_hbreak_req                      (oci_hbreak_req),
+      .oci_ienable                         (oci_ienable),
+      .oci_single_step_mode                (oci_single_step_mode),
+      .read_nxt                            (debug_mem_slave_read),
+      .readdata                            (debug_mem_slave_readdata),
+      .reset                               (debug_mem_slave_reset),
+      .reset_n                             (reset_n),
+      .reset_req                           (reset_req),
+      .resetrequest                        (debug_reset_request),
+      .waitrequest                         (debug_mem_slave_waitrequest),
+      .write_nxt                           (debug_mem_slave_write),
+      .writedata_nxt                       (debug_mem_slave_writedata)
+    );
+
+  //debug_mem_slave, which is an e_avalon_slave
+  assign debug_mem_slave_clk = clk;
+  assign debug_mem_slave_reset = ~reset_n;
+  assign D_ctrl_custom = 1'b0;
+  assign R_ctrl_custom_nxt = D_ctrl_custom;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_custom <= 0;
+      else if (R_en)
+          R_ctrl_custom <= R_ctrl_custom_nxt;
+    end
+
+
+  assign D_ctrl_custom_multi = 1'b0;
+  assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_custom_multi <= 0;
+      else if (R_en)
+          R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
+    end
+
+
+  assign D_ctrl_jmp_indirect = D_op_eret|D_op_bret|D_op_ret|D_op_jmp|D_op_callr;
+  assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_jmp_indirect <= 0;
+      else if (R_en)
+          R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
+    end
+
+
+  assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
+  assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_jmp_direct <= 0;
+      else if (R_en)
+          R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
+    end
+
+
+  assign D_ctrl_implicit_dst_retaddr = D_op_call;
+  assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_implicit_dst_retaddr <= 0;
+      else if (R_en)
+          R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
+    end
+
+
+  assign D_ctrl_implicit_dst_eretaddr = D_op_div|
+    D_op_divu|
+    D_op_mul|
+    D_op_muli|
+    D_op_mulxss|
+    D_op_mulxsu|
+    D_op_mulxuu|
+    D_op_crst|
+    D_op_ldl|
+    D_op_op_rsv02|
+    D_op_op_rsv09|
+    D_op_op_rsv10|
+    D_op_op_rsv17|
+    D_op_op_rsv18|
+    D_op_op_rsv25|
+    D_op_op_rsv26|
+    D_op_op_rsv33|
+    D_op_op_rsv34|
+    D_op_op_rsv41|
+    D_op_op_rsv42|
+    D_op_op_rsv49|
+    D_op_op_rsv57|
+    D_op_op_rsv61|
+    D_op_op_rsv62|
+    D_op_op_rsv63|
+    D_op_opx_rsv00|
+    D_op_opx_rsv10|
+    D_op_opx_rsv15|
+    D_op_opx_rsv17|
+    D_op_opx_rsv21|
+    D_op_opx_rsv25|
+    D_op_opx_rsv33|
+    D_op_opx_rsv34|
+    D_op_opx_rsv35|
+    D_op_opx_rsv42|
+    D_op_opx_rsv43|
+    D_op_opx_rsv44|
+    D_op_opx_rsv47|
+    D_op_opx_rsv50|
+    D_op_opx_rsv51|
+    D_op_opx_rsv55|
+    D_op_opx_rsv56|
+    D_op_opx_rsv60|
+    D_op_opx_rsv63|
+    D_op_rdprs|
+    D_op_stc|
+    D_op_wrprs;
+
+  assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_implicit_dst_eretaddr <= 0;
+      else if (R_en)
+          R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
+    end
+
+
+  assign D_ctrl_exception = D_op_trap|
+    D_op_opx_rsv44|
+    D_op_div|
+    D_op_divu|
+    D_op_mul|
+    D_op_muli|
+    D_op_mulxss|
+    D_op_mulxsu|
+    D_op_mulxuu|
+    D_op_crst|
+    D_op_ldl|
+    D_op_op_rsv02|
+    D_op_op_rsv09|
+    D_op_op_rsv10|
+    D_op_op_rsv17|
+    D_op_op_rsv18|
+    D_op_op_rsv25|
+    D_op_op_rsv26|
+    D_op_op_rsv33|
+    D_op_op_rsv34|
+    D_op_op_rsv41|
+    D_op_op_rsv42|
+    D_op_op_rsv49|
+    D_op_op_rsv57|
+    D_op_op_rsv61|
+    D_op_op_rsv62|
+    D_op_op_rsv63|
+    D_op_opx_rsv00|
+    D_op_opx_rsv10|
+    D_op_opx_rsv15|
+    D_op_opx_rsv17|
+    D_op_opx_rsv21|
+    D_op_opx_rsv25|
+    D_op_opx_rsv33|
+    D_op_opx_rsv34|
+    D_op_opx_rsv35|
+    D_op_opx_rsv42|
+    D_op_opx_rsv43|
+    D_op_opx_rsv47|
+    D_op_opx_rsv50|
+    D_op_opx_rsv51|
+    D_op_opx_rsv55|
+    D_op_opx_rsv56|
+    D_op_opx_rsv60|
+    D_op_opx_rsv63|
+    D_op_rdprs|
+    D_op_stc|
+    D_op_wrprs|
+    D_op_intr;
+
+  assign R_ctrl_exception_nxt = D_ctrl_exception;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_exception <= 0;
+      else if (R_en)
+          R_ctrl_exception <= R_ctrl_exception_nxt;
+    end
+
+
+  assign D_ctrl_break = D_op_break|D_op_hbreak;
+  assign R_ctrl_break_nxt = D_ctrl_break;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_break <= 0;
+      else if (R_en)
+          R_ctrl_break <= R_ctrl_break_nxt;
+    end
+
+
+  assign D_ctrl_crst = 1'b0;
+  assign R_ctrl_crst_nxt = D_ctrl_crst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_crst <= 0;
+      else if (R_en)
+          R_ctrl_crst <= R_ctrl_crst_nxt;
+    end
+
+
+  assign D_ctrl_rd_ctl_reg = D_op_rdctl;
+  assign R_ctrl_rd_ctl_reg_nxt = D_ctrl_rd_ctl_reg;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_rd_ctl_reg <= 0;
+      else if (R_en)
+          R_ctrl_rd_ctl_reg <= R_ctrl_rd_ctl_reg_nxt;
+    end
+
+
+  assign D_ctrl_uncond_cti_non_br = D_op_call|D_op_jmpi|D_op_eret|D_op_bret|D_op_ret|D_op_jmp|D_op_callr;
+  assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_uncond_cti_non_br <= 0;
+      else if (R_en)
+          R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
+    end
+
+
+  assign D_ctrl_retaddr = D_op_call|
+    D_op_op_rsv02|
+    D_op_nextpc|
+    D_op_callr|
+    D_op_trap|
+    D_op_opx_rsv44|
+    D_op_div|
+    D_op_divu|
+    D_op_mul|
+    D_op_muli|
+    D_op_mulxss|
+    D_op_mulxsu|
+    D_op_mulxuu|
+    D_op_crst|
+    D_op_ldl|
+    D_op_op_rsv09|
+    D_op_op_rsv10|
+    D_op_op_rsv17|
+    D_op_op_rsv18|
+    D_op_op_rsv25|
+    D_op_op_rsv26|
+    D_op_op_rsv33|
+    D_op_op_rsv34|
+    D_op_op_rsv41|
+    D_op_op_rsv42|
+    D_op_op_rsv49|
+    D_op_op_rsv57|
+    D_op_op_rsv61|
+    D_op_op_rsv62|
+    D_op_op_rsv63|
+    D_op_opx_rsv00|
+    D_op_opx_rsv10|
+    D_op_opx_rsv15|
+    D_op_opx_rsv17|
+    D_op_opx_rsv21|
+    D_op_opx_rsv25|
+    D_op_opx_rsv33|
+    D_op_opx_rsv34|
+    D_op_opx_rsv35|
+    D_op_opx_rsv42|
+    D_op_opx_rsv43|
+    D_op_opx_rsv47|
+    D_op_opx_rsv50|
+    D_op_opx_rsv51|
+    D_op_opx_rsv55|
+    D_op_opx_rsv56|
+    D_op_opx_rsv60|
+    D_op_opx_rsv63|
+    D_op_rdprs|
+    D_op_stc|
+    D_op_wrprs|
+    D_op_intr|
+    D_op_break|
+    D_op_hbreak;
+
+  assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_retaddr <= 0;
+      else if (R_en)
+          R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
+    end
+
+
+  assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
+  assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_shift_logical <= 0;
+      else if (R_en)
+          R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
+    end
+
+
+  assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
+  assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_shift_right_arith <= 0;
+      else if (R_en)
+          R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
+    end
+
+
+  assign D_ctrl_rot_right = D_op_ror;
+  assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_rot_right <= 0;
+      else if (R_en)
+          R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
+    end
+
+
+  assign D_ctrl_shift_rot_right = D_op_srli|D_op_srl|D_op_srai|D_op_sra|D_op_ror;
+  assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_shift_rot_right <= 0;
+      else if (R_en)
+          R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
+    end
+
+
+  assign D_ctrl_shift_rot = D_op_slli|
+    D_op_sll|
+    D_op_roli|
+    D_op_rol|
+    D_op_srli|
+    D_op_srl|
+    D_op_srai|
+    D_op_sra|
+    D_op_ror;
+
+  assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_shift_rot <= 0;
+      else if (R_en)
+          R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
+    end
+
+
+  assign D_ctrl_logic = D_op_and|
+    D_op_or|
+    D_op_xor|
+    D_op_nor|
+    D_op_andhi|
+    D_op_orhi|
+    D_op_xorhi|
+    D_op_andi|
+    D_op_ori|
+    D_op_xori;
+
+  assign R_ctrl_logic_nxt = D_ctrl_logic;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_logic <= 0;
+      else if (R_en)
+          R_ctrl_logic <= R_ctrl_logic_nxt;
+    end
+
+
+  assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
+  assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_hi_imm16 <= 0;
+      else if (R_en)
+          R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
+    end
+
+
+  assign D_ctrl_set_src2_rem_imm = 1'b0;
+  assign R_ctrl_set_src2_rem_imm_nxt = D_ctrl_set_src2_rem_imm;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_set_src2_rem_imm <= 0;
+      else if (R_en)
+          R_ctrl_set_src2_rem_imm <= R_ctrl_set_src2_rem_imm_nxt;
+    end
+
+
+  assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
+    D_op_cmpltui|
+    D_op_andi|
+    D_op_ori|
+    D_op_xori|
+    D_op_roli|
+    D_op_slli|
+    D_op_srli|
+    D_op_srai;
+
+  assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_unsigned_lo_imm16 <= 0;
+      else if (R_en)
+          R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
+    end
+
+
+  assign D_ctrl_signed_imm12 = 1'b0;
+  assign R_ctrl_signed_imm12_nxt = D_ctrl_signed_imm12;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_signed_imm12 <= 0;
+      else if (R_en)
+          R_ctrl_signed_imm12 <= R_ctrl_signed_imm12_nxt;
+    end
+
+
+  assign D_ctrl_src_imm5_shift_rot = D_op_roli|D_op_slli|D_op_srli|D_op_srai;
+  assign R_ctrl_src_imm5_shift_rot_nxt = D_ctrl_src_imm5_shift_rot;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_src_imm5_shift_rot <= 0;
+      else if (R_en)
+          R_ctrl_src_imm5_shift_rot <= R_ctrl_src_imm5_shift_rot_nxt;
+    end
+
+
+  assign D_ctrl_br_uncond = D_op_br;
+  assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_br_uncond <= 0;
+      else if (R_en)
+          R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
+    end
+
+
+  assign D_ctrl_br = D_op_br|D_op_bge|D_op_blt|D_op_bne|D_op_beq|D_op_bgeu|D_op_bltu;
+  assign R_ctrl_br_nxt = D_ctrl_br;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_br <= 0;
+      else if (R_en)
+          R_ctrl_br <= R_ctrl_br_nxt;
+    end
+
+
+  assign D_ctrl_alu_subtract = D_op_sub|
+    D_op_cmplti|
+    D_op_cmpltui|
+    D_op_cmplt|
+    D_op_cmpltu|
+    D_op_blt|
+    D_op_bltu|
+    D_op_cmpgei|
+    D_op_cmpgeui|
+    D_op_cmpge|
+    D_op_cmpgeu|
+    D_op_bge|
+    D_op_bgeu;
+
+  assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_alu_subtract <= 0;
+      else if (R_en)
+          R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
+    end
+
+
+  assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
+  assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_alu_signed_comparison <= 0;
+      else if (R_en)
+          R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
+    end
+
+
+  assign D_ctrl_br_cmp = D_op_br|
+    D_op_bge|
+    D_op_blt|
+    D_op_bne|
+    D_op_beq|
+    D_op_bgeu|
+    D_op_bltu|
+    D_op_cmpgei|
+    D_op_cmplti|
+    D_op_cmpnei|
+    D_op_cmpgeui|
+    D_op_cmpltui|
+    D_op_cmpeqi|
+    D_op_cmpge|
+    D_op_cmplt|
+    D_op_cmpne|
+    D_op_cmpgeu|
+    D_op_cmpltu|
+    D_op_cmpeq;
+
+  assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_br_cmp <= 0;
+      else if (R_en)
+          R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
+    end
+
+
+  assign D_ctrl_ld_signed = D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldbio|D_op_ldhio|D_op_ldwio;
+  assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_ld_signed <= 0;
+      else if (R_en)
+          R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
+    end
+
+
+  assign D_ctrl_ld = D_op_ldb|
+    D_op_ldh|
+    D_op_ldw|
+    D_op_ldbio|
+    D_op_ldhio|
+    D_op_ldwio|
+    D_op_ldbu|
+    D_op_ldhu|
+    D_op_ldbuio|
+    D_op_ldhuio;
+
+  assign R_ctrl_ld_nxt = D_ctrl_ld;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_ld <= 0;
+      else if (R_en)
+          R_ctrl_ld <= R_ctrl_ld_nxt;
+    end
+
+
+  assign D_ctrl_ld_ex = 1'b0;
+  assign R_ctrl_ld_ex_nxt = D_ctrl_ld_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_ld_ex <= 0;
+      else if (R_en)
+          R_ctrl_ld_ex <= R_ctrl_ld_ex_nxt;
+    end
+
+
+  assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw;
+  assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_ld_non_io <= 0;
+      else if (R_en)
+          R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
+    end
+
+
+  assign D_ctrl_st_ex = 1'b0;
+  assign R_ctrl_st_ex_nxt = D_ctrl_st_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_st_ex <= 0;
+      else if (R_en)
+          R_ctrl_st_ex <= R_ctrl_st_ex_nxt;
+    end
+
+
+  assign D_ctrl_st = D_op_stb|D_op_sth|D_op_stw|D_op_stbio|D_op_sthio|D_op_stwio;
+  assign R_ctrl_st_nxt = D_ctrl_st;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_st <= 0;
+      else if (R_en)
+          R_ctrl_st <= R_ctrl_st_nxt;
+    end
+
+
+  assign D_ctrl_ld_st_ex = 1'b0;
+  assign R_ctrl_ld_st_ex_nxt = D_ctrl_ld_st_ex;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_ld_st_ex <= 0;
+      else if (R_en)
+          R_ctrl_ld_st_ex <= R_ctrl_ld_st_ex_nxt;
+    end
+
+
+  assign D_ctrl_mem8 = D_op_ldb|D_op_ldbu|D_op_ldbio|D_op_ldbuio|D_op_stb|D_op_stbio;
+  assign R_ctrl_mem8_nxt = D_ctrl_mem8;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_mem8 <= 0;
+      else if (R_en)
+          R_ctrl_mem8 <= R_ctrl_mem8_nxt;
+    end
+
+
+  assign D_ctrl_mem16 = D_op_ldhu|D_op_ldh|D_op_ldhio|D_op_ldhuio|D_op_sth|D_op_sthio;
+  assign R_ctrl_mem16_nxt = D_ctrl_mem16;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_mem16 <= 0;
+      else if (R_en)
+          R_ctrl_mem16 <= R_ctrl_mem16_nxt;
+    end
+
+
+  assign D_ctrl_mem32 = D_op_ldw|D_op_ldwio|D_op_stw|D_op_stwio;
+  assign R_ctrl_mem32_nxt = D_ctrl_mem32;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_mem32 <= 0;
+      else if (R_en)
+          R_ctrl_mem32 <= R_ctrl_mem32_nxt;
+    end
+
+
+  assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio;
+  assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_ld_io <= 0;
+      else if (R_en)
+          R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
+    end
+
+
+  assign D_ctrl_b_is_dst = D_op_addi|
+    D_op_andhi|
+    D_op_orhi|
+    D_op_xorhi|
+    D_op_andi|
+    D_op_ori|
+    D_op_xori|
+    D_op_call|
+    D_op_cmpgei|
+    D_op_cmplti|
+    D_op_cmpnei|
+    D_op_cmpgeui|
+    D_op_cmpltui|
+    D_op_cmpeqi|
+    D_op_jmpi|
+    D_op_ldb|
+    D_op_ldh|
+    D_op_ldw|
+    D_op_ldbio|
+    D_op_ldhio|
+    D_op_ldwio|
+    D_op_ldbu|
+    D_op_ldhu|
+    D_op_ldbuio|
+    D_op_ldhuio|
+    D_op_initd|
+    D_op_initda|
+    D_op_flushd|
+    D_op_flushda;
+
+  assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_b_is_dst <= 0;
+      else if (R_en)
+          R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
+    end
+
+
+  assign D_ctrl_ignore_dst = D_op_br|
+    D_op_bge|
+    D_op_blt|
+    D_op_bne|
+    D_op_beq|
+    D_op_bgeu|
+    D_op_bltu|
+    D_op_stb|
+    D_op_sth|
+    D_op_stw|
+    D_op_stbio|
+    D_op_sthio|
+    D_op_stwio|
+    D_op_jmpi;
+
+  assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_ignore_dst <= 0;
+      else if (R_en)
+          R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
+    end
+
+
+  assign D_ctrl_src2_choose_imm = D_op_addi|
+    D_op_andhi|
+    D_op_orhi|
+    D_op_xorhi|
+    D_op_andi|
+    D_op_ori|
+    D_op_xori|
+    D_op_call|
+    D_op_cmpgei|
+    D_op_cmplti|
+    D_op_cmpnei|
+    D_op_cmpgeui|
+    D_op_cmpltui|
+    D_op_cmpeqi|
+    D_op_jmpi|
+    D_op_ldb|
+    D_op_ldh|
+    D_op_ldw|
+    D_op_ldbio|
+    D_op_ldhio|
+    D_op_ldwio|
+    D_op_ldbu|
+    D_op_ldhu|
+    D_op_ldbuio|
+    D_op_ldhuio|
+    D_op_initd|
+    D_op_initda|
+    D_op_flushd|
+    D_op_flushda|
+    D_op_stb|
+    D_op_sth|
+    D_op_stw|
+    D_op_stbio|
+    D_op_sthio|
+    D_op_stwio|
+    D_op_roli|
+    D_op_slli|
+    D_op_srli|
+    D_op_srai;
+
+  assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_src2_choose_imm <= 0;
+      else if (R_en)
+          R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
+    end
+
+
+  assign D_ctrl_wrctl_inst = D_op_wrctl;
+  assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_wrctl_inst <= 0;
+      else if (R_en)
+          R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
+    end
+
+
+  assign D_ctrl_intr_inst = 1'b0;
+  assign R_ctrl_intr_inst_nxt = D_ctrl_intr_inst;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_intr_inst <= 0;
+      else if (R_en)
+          R_ctrl_intr_inst <= R_ctrl_intr_inst_nxt;
+    end
+
+
+  assign D_ctrl_force_src2_zero = D_op_call|
+    D_op_op_rsv02|
+    D_op_nextpc|
+    D_op_callr|
+    D_op_trap|
+    D_op_opx_rsv44|
+    D_op_crst|
+    D_op_ldl|
+    D_op_op_rsv09|
+    D_op_op_rsv10|
+    D_op_op_rsv17|
+    D_op_op_rsv18|
+    D_op_op_rsv25|
+    D_op_op_rsv26|
+    D_op_op_rsv33|
+    D_op_op_rsv34|
+    D_op_op_rsv41|
+    D_op_op_rsv42|
+    D_op_op_rsv49|
+    D_op_op_rsv57|
+    D_op_op_rsv61|
+    D_op_op_rsv62|
+    D_op_op_rsv63|
+    D_op_opx_rsv00|
+    D_op_opx_rsv10|
+    D_op_opx_rsv15|
+    D_op_opx_rsv17|
+    D_op_opx_rsv21|
+    D_op_opx_rsv25|
+    D_op_opx_rsv33|
+    D_op_opx_rsv34|
+    D_op_opx_rsv35|
+    D_op_opx_rsv42|
+    D_op_opx_rsv43|
+    D_op_opx_rsv47|
+    D_op_opx_rsv50|
+    D_op_opx_rsv51|
+    D_op_opx_rsv55|
+    D_op_opx_rsv56|
+    D_op_opx_rsv60|
+    D_op_opx_rsv63|
+    D_op_rdprs|
+    D_op_stc|
+    D_op_wrprs|
+    D_op_intr|
+    D_op_break|
+    D_op_hbreak|
+    D_op_eret|
+    D_op_bret|
+    D_op_ret|
+    D_op_jmp|
+    D_op_jmpi;
+
+  assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_force_src2_zero <= 0;
+      else if (R_en)
+          R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
+    end
+
+
+  assign D_ctrl_alu_force_xor = D_op_cmpgei|
+    D_op_cmpgeui|
+    D_op_cmpeqi|
+    D_op_cmpge|
+    D_op_cmpgeu|
+    D_op_cmpeq|
+    D_op_cmpnei|
+    D_op_cmpne|
+    D_op_bge|
+    D_op_bgeu|
+    D_op_beq|
+    D_op_bne|
+    D_op_br;
+
+  assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_alu_force_xor <= 0;
+      else if (R_en)
+          R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
+    end
+
+
+  assign D_ctrl_alu_force_and = 1'b0;
+  assign R_ctrl_alu_force_and_nxt = D_ctrl_alu_force_and;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          R_ctrl_alu_force_and <= 0;
+      else if (R_en)
+          R_ctrl_alu_force_and <= R_ctrl_alu_force_and_nxt;
+    end
+
+
+  //data_master, which is an e_avalon_master
+  //instruction_master, which is an e_avalon_master
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  assign F_inst = (F_op_call)? 56'h20202063616c6c :
+    (F_op_jmpi)? 56'h2020206a6d7069 :
+    (F_op_ldbu)? 56'h2020206c646275 :
+    (F_op_addi)? 56'h20202061646469 :
+    (F_op_stb)? 56'h20202020737462 :
+    (F_op_br)? 56'h20202020206272 :
+    (F_op_ldb)? 56'h202020206c6462 :
+    (F_op_cmpgei)? 56'h20636d70676569 :
+    (F_op_ldhu)? 56'h2020206c646875 :
+    (F_op_andi)? 56'h202020616e6469 :
+    (F_op_sth)? 56'h20202020737468 :
+    (F_op_bge)? 56'h20202020626765 :
+    (F_op_ldh)? 56'h202020206c6468 :
+    (F_op_cmplti)? 56'h20636d706c7469 :
+    (F_op_initda)? 56'h20696e69746461 :
+    (F_op_ori)? 56'h202020206f7269 :
+    (F_op_stw)? 56'h20202020737477 :
+    (F_op_blt)? 56'h20202020626c74 :
+    (F_op_ldw)? 56'h202020206c6477 :
+    (F_op_cmpnei)? 56'h20636d706e6569 :
+    (F_op_flushda)? 56'h666c7573686461 :
+    (F_op_xori)? 56'h202020786f7269 :
+    (F_op_bne)? 56'h20202020626e65 :
+    (F_op_cmpeqi)? 56'h20636d70657169 :
+    (F_op_ldbuio)? 56'h206c646275696f :
+    (F_op_muli)? 56'h2020206d756c69 :
+    (F_op_stbio)? 56'h2020737462696f :
+    (F_op_beq)? 56'h20202020626571 :
+    (F_op_ldbio)? 56'h20206c6462696f :
+    (F_op_cmpgeui)? 56'h636d7067657569 :
+    (F_op_ldhuio)? 56'h206c646875696f :
+    (F_op_andhi)? 56'h2020616e646869 :
+    (F_op_sthio)? 56'h2020737468696f :
+    (F_op_bgeu)? 56'h20202062676575 :
+    (F_op_ldhio)? 56'h20206c6468696f :
+    (F_op_cmpltui)? 56'h636d706c747569 :
+    (F_op_custom)? 56'h20637573746f6d :
+    (F_op_initd)? 56'h2020696e697464 :
+    (F_op_orhi)? 56'h2020206f726869 :
+    (F_op_stwio)? 56'h2020737477696f :
+    (F_op_bltu)? 56'h202020626c7475 :
+    (F_op_ldwio)? 56'h20206c6477696f :
+    (F_op_flushd)? 56'h20666c75736864 :
+    (F_op_xorhi)? 56'h2020786f726869 :
+    (F_op_eret)? 56'h20202065726574 :
+    (F_op_roli)? 56'h202020726f6c69 :
+    (F_op_rol)? 56'h20202020726f6c :
+    (F_op_flushp)? 56'h20666c75736870 :
+    (F_op_ret)? 56'h20202020726574 :
+    (F_op_nor)? 56'h202020206e6f72 :
+    (F_op_mulxuu)? 56'h206d756c787575 :
+    (F_op_cmpge)? 56'h2020636d706765 :
+    (F_op_bret)? 56'h20202062726574 :
+    (F_op_ror)? 56'h20202020726f72 :
+    (F_op_flushi)? 56'h20666c75736869 :
+    (F_op_jmp)? 56'h202020206a6d70 :
+    (F_op_and)? 56'h20202020616e64 :
+    (F_op_cmplt)? 56'h2020636d706c74 :
+    (F_op_slli)? 56'h202020736c6c69 :
+    (F_op_sll)? 56'h20202020736c6c :
+    (F_op_or)? 56'h20202020206f72 :
+    (F_op_mulxsu)? 56'h206d756c787375 :
+    (F_op_cmpne)? 56'h2020636d706e65 :
+    (F_op_srli)? 56'h20202073726c69 :
+    (F_op_srl)? 56'h2020202073726c :
+    (F_op_nextpc)? 56'h206e6578747063 :
+    (F_op_callr)? 56'h202063616c6c72 :
+    (F_op_xor)? 56'h20202020786f72 :
+    (F_op_mulxss)? 56'h206d756c787373 :
+    (F_op_cmpeq)? 56'h2020636d706571 :
+    (F_op_divu)? 56'h20202064697675 :
+    (F_op_div)? 56'h20202020646976 :
+    (F_op_rdctl)? 56'h2020726463746c :
+    (F_op_mul)? 56'h202020206d756c :
+    (F_op_cmpgeu)? 56'h20636d70676575 :
+    (F_op_initi)? 56'h2020696e697469 :
+    (F_op_trap)? 56'h20202074726170 :
+    (F_op_wrctl)? 56'h2020777263746c :
+    (F_op_cmpltu)? 56'h20636d706c7475 :
+    (F_op_add)? 56'h20202020616464 :
+    (F_op_break)? 56'h2020627265616b :
+    (F_op_hbreak)? 56'h2068627265616b :
+    (F_op_sync)? 56'h20202073796e63 :
+    (F_op_sub)? 56'h20202020737562 :
+    (F_op_srai)? 56'h20202073726169 :
+    (F_op_sra)? 56'h20202020737261 :
+    (F_op_intr)? 56'h202020696e7472 :
+    56'h20202020424144;
+
+  assign D_inst = (D_op_call)? 56'h20202063616c6c :
+    (D_op_jmpi)? 56'h2020206a6d7069 :
+    (D_op_ldbu)? 56'h2020206c646275 :
+    (D_op_addi)? 56'h20202061646469 :
+    (D_op_stb)? 56'h20202020737462 :
+    (D_op_br)? 56'h20202020206272 :
+    (D_op_ldb)? 56'h202020206c6462 :
+    (D_op_cmpgei)? 56'h20636d70676569 :
+    (D_op_ldhu)? 56'h2020206c646875 :
+    (D_op_andi)? 56'h202020616e6469 :
+    (D_op_sth)? 56'h20202020737468 :
+    (D_op_bge)? 56'h20202020626765 :
+    (D_op_ldh)? 56'h202020206c6468 :
+    (D_op_cmplti)? 56'h20636d706c7469 :
+    (D_op_initda)? 56'h20696e69746461 :
+    (D_op_ori)? 56'h202020206f7269 :
+    (D_op_stw)? 56'h20202020737477 :
+    (D_op_blt)? 56'h20202020626c74 :
+    (D_op_ldw)? 56'h202020206c6477 :
+    (D_op_cmpnei)? 56'h20636d706e6569 :
+    (D_op_flushda)? 56'h666c7573686461 :
+    (D_op_xori)? 56'h202020786f7269 :
+    (D_op_bne)? 56'h20202020626e65 :
+    (D_op_cmpeqi)? 56'h20636d70657169 :
+    (D_op_ldbuio)? 56'h206c646275696f :
+    (D_op_muli)? 56'h2020206d756c69 :
+    (D_op_stbio)? 56'h2020737462696f :
+    (D_op_beq)? 56'h20202020626571 :
+    (D_op_ldbio)? 56'h20206c6462696f :
+    (D_op_cmpgeui)? 56'h636d7067657569 :
+    (D_op_ldhuio)? 56'h206c646875696f :
+    (D_op_andhi)? 56'h2020616e646869 :
+    (D_op_sthio)? 56'h2020737468696f :
+    (D_op_bgeu)? 56'h20202062676575 :
+    (D_op_ldhio)? 56'h20206c6468696f :
+    (D_op_cmpltui)? 56'h636d706c747569 :
+    (D_op_custom)? 56'h20637573746f6d :
+    (D_op_initd)? 56'h2020696e697464 :
+    (D_op_orhi)? 56'h2020206f726869 :
+    (D_op_stwio)? 56'h2020737477696f :
+    (D_op_bltu)? 56'h202020626c7475 :
+    (D_op_ldwio)? 56'h20206c6477696f :
+    (D_op_flushd)? 56'h20666c75736864 :
+    (D_op_xorhi)? 56'h2020786f726869 :
+    (D_op_eret)? 56'h20202065726574 :
+    (D_op_roli)? 56'h202020726f6c69 :
+    (D_op_rol)? 56'h20202020726f6c :
+    (D_op_flushp)? 56'h20666c75736870 :
+    (D_op_ret)? 56'h20202020726574 :
+    (D_op_nor)? 56'h202020206e6f72 :
+    (D_op_mulxuu)? 56'h206d756c787575 :
+    (D_op_cmpge)? 56'h2020636d706765 :
+    (D_op_bret)? 56'h20202062726574 :
+    (D_op_ror)? 56'h20202020726f72 :
+    (D_op_flushi)? 56'h20666c75736869 :
+    (D_op_jmp)? 56'h202020206a6d70 :
+    (D_op_and)? 56'h20202020616e64 :
+    (D_op_cmplt)? 56'h2020636d706c74 :
+    (D_op_slli)? 56'h202020736c6c69 :
+    (D_op_sll)? 56'h20202020736c6c :
+    (D_op_or)? 56'h20202020206f72 :
+    (D_op_mulxsu)? 56'h206d756c787375 :
+    (D_op_cmpne)? 56'h2020636d706e65 :
+    (D_op_srli)? 56'h20202073726c69 :
+    (D_op_srl)? 56'h2020202073726c :
+    (D_op_nextpc)? 56'h206e6578747063 :
+    (D_op_callr)? 56'h202063616c6c72 :
+    (D_op_xor)? 56'h20202020786f72 :
+    (D_op_mulxss)? 56'h206d756c787373 :
+    (D_op_cmpeq)? 56'h2020636d706571 :
+    (D_op_divu)? 56'h20202064697675 :
+    (D_op_div)? 56'h20202020646976 :
+    (D_op_rdctl)? 56'h2020726463746c :
+    (D_op_mul)? 56'h202020206d756c :
+    (D_op_cmpgeu)? 56'h20636d70676575 :
+    (D_op_initi)? 56'h2020696e697469 :
+    (D_op_trap)? 56'h20202074726170 :
+    (D_op_wrctl)? 56'h2020777263746c :
+    (D_op_cmpltu)? 56'h20636d706c7475 :
+    (D_op_add)? 56'h20202020616464 :
+    (D_op_break)? 56'h2020627265616b :
+    (D_op_hbreak)? 56'h2068627265616b :
+    (D_op_sync)? 56'h20202073796e63 :
+    (D_op_sub)? 56'h20202020737562 :
+    (D_op_srai)? 56'h20202073726169 :
+    (D_op_sra)? 56'h20202020737261 :
+    (D_op_intr)? 56'h202020696e7472 :
+    56'h20202020424144;
+
+  assign F_vinst = F_valid ? F_inst : {9{8'h2d}};
+  assign D_vinst = D_valid ? D_inst : {9{8'h2d}};
+  assign R_vinst = R_valid ? D_inst : {9{8'h2d}};
+  assign E_vinst = E_valid ? D_inst : {9{8'h2d}};
+  assign W_vinst = W_valid ? D_inst : {9{8'h2d}};
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+
+endmodule
+

nios2_uc/synthesis/submodules/nios2_uc_nios2_cpu_debug_slave_sysclk.v

@@ -0,0 +1,162 @@
+//Legal Notice: (C)2020 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_debug_slave_sysclk (
+                                               // inputs:
+                                                clk,
+                                                ir_in,
+                                                sr,
+                                                vs_udr,
+                                                vs_uir,
+
+                                               // outputs:
+                                                jdo,
+                                                take_action_break_a,
+                                                take_action_break_b,
+                                                take_action_break_c,
+                                                take_action_ocimem_a,
+                                                take_action_ocimem_b,
+                                                take_action_tracectrl,
+                                                take_no_action_break_a,
+                                                take_no_action_break_b,
+                                                take_no_action_break_c,
+                                                take_no_action_ocimem_a
+                                             )
+;
+
+  output  [ 37: 0] jdo;
+  output           take_action_break_a;
+  output           take_action_break_b;
+  output           take_action_break_c;
+  output           take_action_ocimem_a;
+  output           take_action_ocimem_b;
+  output           take_action_tracectrl;
+  output           take_no_action_break_a;
+  output           take_no_action_break_b;
+  output           take_no_action_break_c;
+  output           take_no_action_ocimem_a;
+  input            clk;
+  input   [  1: 0] ir_in;
+  input   [ 37: 0] sr;
+  input            vs_udr;
+  input            vs_uir;
+
+
+reg              enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\""  */;
+reg     [  1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg     [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\""  */;
+reg              jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\""  */;
+reg              sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\""  */;
+reg              sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\""  */;
+wire             sync_udr;
+wire             sync_uir;
+wire             take_action_break_a;
+wire             take_action_break_b;
+wire             take_action_break_c;
+wire             take_action_ocimem_a;
+wire             take_action_ocimem_b;
+wire             take_action_tracectrl;
+wire             take_no_action_break_a;
+wire             take_no_action_break_b;
+wire             take_no_action_break_c;
+wire             take_no_action_ocimem_a;
+wire             unxunused_resetxx3;
+wire             unxunused_resetxx4;
+reg              update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\""  */;
+  assign unxunused_resetxx3 = 1'b1;
+  altera_std_synchronizer the_altera_std_synchronizer3
+    (
+      .clk (clk),
+      .din (vs_udr),
+      .dout (sync_udr),
+      .reset_n (unxunused_resetxx3)
+    );
+
+  defparam the_altera_std_synchronizer3.depth = 2;
+
+  assign unxunused_resetxx4 = 1'b1;
+  altera_std_synchronizer the_altera_std_synchronizer4
+    (
+      .clk (clk),
+      .din (vs_uir),
+      .dout (sync_uir),
+      .reset_n (unxunused_resetxx4)
+    );
+
+  defparam the_altera_std_synchronizer4.depth = 2;
+
+  always @(posedge clk)
+    begin
+      sync2_udr <= sync_udr;
+      update_jdo_strobe <= sync_udr & ~sync2_udr;
+      enable_action_strobe <= update_jdo_strobe;
+      sync2_uir <= sync_uir;
+      jxuir <= sync_uir & ~sync2_uir;
+    end
+
+
+  assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && 
+    ~jdo[35] && jdo[34];
+
+  assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && 
+    ~jdo[35] && ~jdo[34];
+
+  assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) && 
+    jdo[35];
+
+  assign take_action_break_a = enable_action_strobe && (ir == 2'b10) && 
+    ~jdo[36] && 
+    jdo[37];
+
+  assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) && 
+    ~jdo[36] && 
+    ~jdo[37];
+
+  assign take_action_break_b = enable_action_strobe && (ir == 2'b10) && 
+    jdo[36] && ~jdo[35] &&
+    jdo[37];
+
+  assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) && 
+    jdo[36] && ~jdo[35] &&
+    ~jdo[37];
+
+  assign take_action_break_c = enable_action_strobe && (ir == 2'b10) && 
+    jdo[36] &&  jdo[35] &&
+    jdo[37];
+
+  assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) && 
+    jdo[36] &&  jdo[35] &&
+    ~jdo[37];
+
+  assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&  
+    jdo[15];
+
+  always @(posedge clk)
+    begin
+      if (jxuir)
+          ir <= ir_in;
+      if (update_jdo_strobe)
+          jdo <= sr;
+    end
+
+
+
+endmodule
+

nios2_uc/synthesis/submodules/nios2_uc_nios2_cpu_debug_slave_tck.v

@@ -0,0 +1,239 @@
+//Legal Notice: (C)2020 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_debug_slave_tck (
+                                            // inputs:
+                                             MonDReg,
+                                             break_readreg,
+                                             dbrk_hit0_latch,
+                                             dbrk_hit1_latch,
+                                             dbrk_hit2_latch,
+                                             dbrk_hit3_latch,
+                                             debugack,
+                                             ir_in,
+                                             jtag_state_rti,
+                                             monitor_error,
+                                             monitor_ready,
+                                             reset_n,
+                                             resetlatch,
+                                             tck,
+                                             tdi,
+                                             tracemem_on,
+                                             tracemem_trcdata,
+                                             tracemem_tw,
+                                             trc_im_addr,
+                                             trc_on,
+                                             trc_wrap,
+                                             trigbrktype,
+                                             trigger_state_1,
+                                             vs_cdr,
+                                             vs_sdr,
+                                             vs_uir,
+
+                                            // outputs:
+                                             ir_out,
+                                             jrst_n,
+                                             sr,
+                                             st_ready_test_idle,
+                                             tdo
+                                          )
+;
+
+  output  [  1: 0] ir_out;
+  output           jrst_n;
+  output  [ 37: 0] sr;
+  output           st_ready_test_idle;
+  output           tdo;
+  input   [ 31: 0] MonDReg;
+  input   [ 31: 0] break_readreg;
+  input            dbrk_hit0_latch;
+  input            dbrk_hit1_latch;
+  input            dbrk_hit2_latch;
+  input            dbrk_hit3_latch;
+  input            debugack;
+  input   [  1: 0] ir_in;
+  input            jtag_state_rti;
+  input            monitor_error;
+  input            monitor_ready;
+  input            reset_n;
+  input            resetlatch;
+  input            tck;
+  input            tdi;
+  input            tracemem_on;
+  input   [ 35: 0] tracemem_trcdata;
+  input            tracemem_tw;
+  input   [  6: 0] trc_im_addr;
+  input            trc_on;
+  input            trc_wrap;
+  input            trigbrktype;
+  input            trigger_state_1;
+  input            vs_cdr;
+  input            vs_sdr;
+  input            vs_uir;
+
+
+reg     [  2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire             debugack_sync;
+reg     [  1: 0] ir_out;
+wire             jrst_n;
+wire             monitor_ready_sync;
+reg     [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\""  */;
+wire             st_ready_test_idle;
+wire             tdo;
+wire             unxcomplemented_resetxx1;
+wire             unxcomplemented_resetxx2;
+  always @(posedge tck)
+    begin
+      if (vs_cdr)
+          case (ir_in)
+          
+              2'b00: begin
+                  sr[35] <= debugack_sync;
+                  sr[34] <= monitor_error;
+                  sr[33] <= resetlatch;
+                  sr[32 : 1] <= MonDReg;
+                  sr[0] <= monitor_ready_sync;
+              end // 2'b00 
+          
+              2'b01: begin
+                  sr[35 : 0] <= tracemem_trcdata;
+                  sr[37] <= tracemem_tw;
+                  sr[36] <= tracemem_on;
+              end // 2'b01 
+          
+              2'b10: begin
+                  sr[37] <= trigger_state_1;
+                  sr[36] <= dbrk_hit3_latch;
+                  sr[35] <= dbrk_hit2_latch;
+                  sr[34] <= dbrk_hit1_latch;
+                  sr[33] <= dbrk_hit0_latch;
+                  sr[32 : 1] <= break_readreg;
+                  sr[0] <= trigbrktype;
+              end // 2'b10 
+          
+              2'b11: begin
+                  sr[15 : 2] <= trc_im_addr;
+                  sr[1] <= trc_wrap;
+                  sr[0] <= trc_on;
+              end // 2'b11 
+          
+          endcase // ir_in
+      if (vs_sdr)
+          case (DRsize)
+          
+              3'b000: begin
+                  sr <= {tdi, sr[37 : 2], tdi};
+              end // 3'b000 
+          
+              3'b001: begin
+                  sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
+              end // 3'b001 
+          
+              3'b010: begin
+                  sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
+              end // 3'b010 
+          
+              3'b011: begin
+                  sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
+              end // 3'b011 
+          
+              3'b100: begin
+                  sr <= {tdi, sr[37],         tdi, sr[35 : 1]};
+              end // 3'b100 
+          
+              3'b101: begin
+                  sr <= {tdi, sr[37 : 1]};
+              end // 3'b101 
+          
+              default: begin
+                  sr <= {tdi, sr[37 : 2], tdi};
+              end // default
+          
+          endcase // DRsize
+      if (vs_uir)
+          case (ir_in)
+          
+              2'b00: begin
+                  DRsize <= 3'b100;
+              end // 2'b00 
+          
+              2'b01: begin
+                  DRsize <= 3'b101;
+              end // 2'b01 
+          
+              2'b10: begin
+                  DRsize <= 3'b101;
+              end // 2'b10 
+          
+              2'b11: begin
+                  DRsize <= 3'b010;
+              end // 2'b11 
+          
+          endcase // ir_in
+    end
+
+
+  assign tdo = sr[0];
+  assign st_ready_test_idle = jtag_state_rti;
+  assign unxcomplemented_resetxx1 = jrst_n;
+  altera_std_synchronizer the_altera_std_synchronizer1
+    (
+      .clk (tck),
+      .din (debugack),
+      .dout (debugack_sync),
+      .reset_n (unxcomplemented_resetxx1)
+    );
+
+  defparam the_altera_std_synchronizer1.depth = 2;
+
+  assign unxcomplemented_resetxx2 = jrst_n;
+  altera_std_synchronizer the_altera_std_synchronizer2
+    (
+      .clk (tck),
+      .din (monitor_ready),
+      .dout (monitor_ready_sync),
+      .reset_n (unxcomplemented_resetxx2)
+    );
+
+  defparam the_altera_std_synchronizer2.depth = 2;
+
+  always @(posedge tck or negedge jrst_n)
+    begin
+      if (jrst_n == 0)
+          ir_out <= 2'b0;
+      else 
+        ir_out <= {debugack_sync, monitor_ready_sync};
+    end
+
+
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  assign jrst_n = reset_n;
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  assign jrst_n = 1;
+//synthesis read_comments_as_HDL off
+
+endmodule
+

nios2_uc/synthesis/submodules/nios2_uc_nios2_cpu_debug_slave_wrapper.v

@@ -0,0 +1,222 @@
+//Legal Notice: (C)2020 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_debug_slave_wrapper (
+                                                // inputs:
+                                                 MonDReg,
+                                                 break_readreg,
+                                                 clk,
+                                                 dbrk_hit0_latch,
+                                                 dbrk_hit1_latch,
+                                                 dbrk_hit2_latch,
+                                                 dbrk_hit3_latch,
+                                                 debugack,
+                                                 monitor_error,
+                                                 monitor_ready,
+                                                 reset_n,
+                                                 resetlatch,
+                                                 tracemem_on,
+                                                 tracemem_trcdata,
+                                                 tracemem_tw,
+                                                 trc_im_addr,
+                                                 trc_on,
+                                                 trc_wrap,
+                                                 trigbrktype,
+                                                 trigger_state_1,
+
+                                                // outputs:
+                                                 jdo,
+                                                 jrst_n,
+                                                 st_ready_test_idle,
+                                                 take_action_break_a,
+                                                 take_action_break_b,
+                                                 take_action_break_c,
+                                                 take_action_ocimem_a,
+                                                 take_action_ocimem_b,
+                                                 take_action_tracectrl,
+                                                 take_no_action_break_a,
+                                                 take_no_action_break_b,
+                                                 take_no_action_break_c,
+                                                 take_no_action_ocimem_a
+                                              )
+;
+
+  output  [ 37: 0] jdo;
+  output           jrst_n;
+  output           st_ready_test_idle;
+  output           take_action_break_a;
+  output           take_action_break_b;
+  output           take_action_break_c;
+  output           take_action_ocimem_a;
+  output           take_action_ocimem_b;
+  output           take_action_tracectrl;
+  output           take_no_action_break_a;
+  output           take_no_action_break_b;
+  output           take_no_action_break_c;
+  output           take_no_action_ocimem_a;
+  input   [ 31: 0] MonDReg;
+  input   [ 31: 0] break_readreg;
+  input            clk;
+  input            dbrk_hit0_latch;
+  input            dbrk_hit1_latch;
+  input            dbrk_hit2_latch;
+  input            dbrk_hit3_latch;
+  input            debugack;
+  input            monitor_error;
+  input            monitor_ready;
+  input            reset_n;
+  input            resetlatch;
+  input            tracemem_on;
+  input   [ 35: 0] tracemem_trcdata;
+  input            tracemem_tw;
+  input   [  6: 0] trc_im_addr;
+  input            trc_on;
+  input            trc_wrap;
+  input            trigbrktype;
+  input            trigger_state_1;
+
+
+wire    [ 37: 0] jdo;
+wire             jrst_n;
+wire    [ 37: 0] sr;
+wire             st_ready_test_idle;
+wire             take_action_break_a;
+wire             take_action_break_b;
+wire             take_action_break_c;
+wire             take_action_ocimem_a;
+wire             take_action_ocimem_b;
+wire             take_action_tracectrl;
+wire             take_no_action_break_a;
+wire             take_no_action_break_b;
+wire             take_no_action_break_c;
+wire             take_no_action_ocimem_a;
+wire             vji_cdr;
+wire    [  1: 0] vji_ir_in;
+wire    [  1: 0] vji_ir_out;
+wire             vji_rti;
+wire             vji_sdr;
+wire             vji_tck;
+wire             vji_tdi;
+wire             vji_tdo;
+wire             vji_udr;
+wire             vji_uir;
+  //Change the sld_virtual_jtag_basic's defparams to
+  //switch between a regular Nios II or an internally embedded Nios II.
+  //For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
+  //For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
+  nios2_uc_nios2_cpu_debug_slave_tck the_nios2_uc_nios2_cpu_debug_slave_tck
+    (
+      .MonDReg            (MonDReg),
+      .break_readreg      (break_readreg),
+      .dbrk_hit0_latch    (dbrk_hit0_latch),
+      .dbrk_hit1_latch    (dbrk_hit1_latch),
+      .dbrk_hit2_latch    (dbrk_hit2_latch),
+      .dbrk_hit3_latch    (dbrk_hit3_latch),
+      .debugack           (debugack),
+      .ir_in              (vji_ir_in),
+      .ir_out             (vji_ir_out),
+      .jrst_n             (jrst_n),
+      .jtag_state_rti     (vji_rti),
+      .monitor_error      (monitor_error),
+      .monitor_ready      (monitor_ready),
+      .reset_n            (reset_n),
+      .resetlatch         (resetlatch),
+      .sr                 (sr),
+      .st_ready_test_idle (st_ready_test_idle),
+      .tck                (vji_tck),
+      .tdi                (vji_tdi),
+      .tdo                (vji_tdo),
+      .tracemem_on        (tracemem_on),
+      .tracemem_trcdata   (tracemem_trcdata),
+      .tracemem_tw        (tracemem_tw),
+      .trc_im_addr        (trc_im_addr),
+      .trc_on             (trc_on),
+      .trc_wrap           (trc_wrap),
+      .trigbrktype        (trigbrktype),
+      .trigger_state_1    (trigger_state_1),
+      .vs_cdr             (vji_cdr),
+      .vs_sdr             (vji_sdr),
+      .vs_uir             (vji_uir)
+    );
+
+  nios2_uc_nios2_cpu_debug_slave_sysclk the_nios2_uc_nios2_cpu_debug_slave_sysclk
+    (
+      .clk                     (clk),
+      .ir_in                   (vji_ir_in),
+      .jdo                     (jdo),
+      .sr                      (sr),
+      .take_action_break_a     (take_action_break_a),
+      .take_action_break_b     (take_action_break_b),
+      .take_action_break_c     (take_action_break_c),
+      .take_action_ocimem_a    (take_action_ocimem_a),
+      .take_action_ocimem_b    (take_action_ocimem_b),
+      .take_action_tracectrl   (take_action_tracectrl),
+      .take_no_action_break_a  (take_no_action_break_a),
+      .take_no_action_break_b  (take_no_action_break_b),
+      .take_no_action_break_c  (take_no_action_break_c),
+      .take_no_action_ocimem_a (take_no_action_ocimem_a),
+      .vs_udr                  (vji_udr),
+      .vs_uir                  (vji_uir)
+    );
+
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  assign vji_tck = 1'b0;
+  assign vji_tdi = 1'b0;
+  assign vji_sdr = 1'b0;
+  assign vji_cdr = 1'b0;
+  assign vji_rti = 1'b0;
+  assign vji_uir = 1'b0;
+  assign vji_udr = 1'b0;
+  assign vji_ir_in = 2'b0;
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  sld_virtual_jtag_basic nios2_uc_nios2_cpu_debug_slave_phy
+//    (
+//      .ir_in (vji_ir_in),
+//      .ir_out (vji_ir_out),
+//      .jtag_state_rti (vji_rti),
+//      .tck (vji_tck),
+//      .tdi (vji_tdi),
+//      .tdo (vji_tdo),
+//      .virtual_state_cdr (vji_cdr),
+//      .virtual_state_sdr (vji_sdr),
+//      .virtual_state_udr (vji_udr),
+//      .virtual_state_uir (vji_uir)
+//    );
+//
+//  defparam nios2_uc_nios2_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
+//           nios2_uc_nios2_cpu_debug_slave_phy.sld_instance_index = 0,
+//           nios2_uc_nios2_cpu_debug_slave_phy.sld_ir_width = 2,
+//           nios2_uc_nios2_cpu_debug_slave_phy.sld_mfg_id = 70,
+//           nios2_uc_nios2_cpu_debug_slave_phy.sld_sim_action = "",
+//           nios2_uc_nios2_cpu_debug_slave_phy.sld_sim_n_scan = 0,
+//           nios2_uc_nios2_cpu_debug_slave_phy.sld_sim_total_length = 0,
+//           nios2_uc_nios2_cpu_debug_slave_phy.sld_type_id = 34,
+//           nios2_uc_nios2_cpu_debug_slave_phy.sld_version = 3;
+//
+//synthesis read_comments_as_HDL off
+
+endmodule
+

nios2_uc/synthesis/submodules/nios2_uc_nios2_cpu_test_bench.v

@@ -0,0 +1,656 @@
+//Legal Notice: (C)2020 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_nios2_cpu_test_bench (
+                                       // inputs:
+                                        D_iw,
+                                        D_iw_op,
+                                        D_iw_opx,
+                                        D_valid,
+                                        E_valid,
+                                        F_pcb,
+                                        F_valid,
+                                        R_ctrl_ld,
+                                        R_ctrl_ld_non_io,
+                                        R_dst_regnum,
+                                        R_wr_dst_reg,
+                                        W_valid,
+                                        W_vinst,
+                                        W_wr_data,
+                                        av_ld_data_aligned_unfiltered,
+                                        clk,
+                                        d_address,
+                                        d_byteenable,
+                                        d_read,
+                                        d_write,
+                                        i_address,
+                                        i_read,
+                                        i_readdata,
+                                        i_waitrequest,
+                                        reset_n,
+
+                                       // outputs:
+                                        av_ld_data_aligned_filtered,
+                                        test_has_ended
+                                     )
+;
+
+  output  [ 31: 0] av_ld_data_aligned_filtered;
+  output           test_has_ended;
+  input   [ 31: 0] D_iw;
+  input   [  5: 0] D_iw_op;
+  input   [  5: 0] D_iw_opx;
+  input            D_valid;
+  input            E_valid;
+  input   [ 19: 0] F_pcb;
+  input            F_valid;
+  input            R_ctrl_ld;
+  input            R_ctrl_ld_non_io;
+  input   [  4: 0] R_dst_regnum;
+  input            R_wr_dst_reg;
+  input            W_valid;
+  input   [ 71: 0] W_vinst;
+  input   [ 31: 0] W_wr_data;
+  input   [ 31: 0] av_ld_data_aligned_unfiltered;
+  input            clk;
+  input   [ 19: 0] d_address;
+  input   [  3: 0] d_byteenable;
+  input            d_read;
+  input            d_write;
+  input   [ 19: 0] i_address;
+  input            i_read;
+  input   [ 31: 0] i_readdata;
+  input            i_waitrequest;
+  input            reset_n;
+
+
+wire             D_is_opx_inst;
+wire             D_op_add;
+wire             D_op_addi;
+wire             D_op_and;
+wire             D_op_andhi;
+wire             D_op_andi;
+wire             D_op_beq;
+wire             D_op_bge;
+wire             D_op_bgeu;
+wire             D_op_blt;
+wire             D_op_bltu;
+wire             D_op_bne;
+wire             D_op_br;
+wire             D_op_break;
+wire             D_op_bret;
+wire             D_op_call;
+wire             D_op_callr;
+wire             D_op_cmpeq;
+wire             D_op_cmpeqi;
+wire             D_op_cmpge;
+wire             D_op_cmpgei;
+wire             D_op_cmpgeu;
+wire             D_op_cmpgeui;
+wire             D_op_cmplt;
+wire             D_op_cmplti;
+wire             D_op_cmpltu;
+wire             D_op_cmpltui;
+wire             D_op_cmpne;
+wire             D_op_cmpnei;
+wire             D_op_crst;
+wire             D_op_custom;
+wire             D_op_div;
+wire             D_op_divu;
+wire             D_op_eret;
+wire             D_op_flushd;
+wire             D_op_flushda;
+wire             D_op_flushi;
+wire             D_op_flushp;
+wire             D_op_hbreak;
+wire             D_op_initd;
+wire             D_op_initda;
+wire             D_op_initi;
+wire             D_op_intr;
+wire             D_op_jmp;
+wire             D_op_jmpi;
+wire             D_op_ldb;
+wire             D_op_ldbio;
+wire             D_op_ldbu;
+wire             D_op_ldbuio;
+wire             D_op_ldh;
+wire             D_op_ldhio;
+wire             D_op_ldhu;
+wire             D_op_ldhuio;
+wire             D_op_ldl;
+wire             D_op_ldw;
+wire             D_op_ldwio;
+wire             D_op_mul;
+wire             D_op_muli;
+wire             D_op_mulxss;
+wire             D_op_mulxsu;
+wire             D_op_mulxuu;
+wire             D_op_nextpc;
+wire             D_op_nor;
+wire             D_op_op_rsv02;
+wire             D_op_op_rsv09;
+wire             D_op_op_rsv10;
+wire             D_op_op_rsv17;
+wire             D_op_op_rsv18;
+wire             D_op_op_rsv25;
+wire             D_op_op_rsv26;
+wire             D_op_op_rsv33;
+wire             D_op_op_rsv34;
+wire             D_op_op_rsv41;
+wire             D_op_op_rsv42;
+wire             D_op_op_rsv49;
+wire             D_op_op_rsv57;
+wire             D_op_op_rsv61;
+wire             D_op_op_rsv62;
+wire             D_op_op_rsv63;
+wire             D_op_opx_rsv00;
+wire             D_op_opx_rsv10;
+wire             D_op_opx_rsv15;
+wire             D_op_opx_rsv17;
+wire             D_op_opx_rsv21;
+wire             D_op_opx_rsv25;
+wire             D_op_opx_rsv33;
+wire             D_op_opx_rsv34;
+wire             D_op_opx_rsv35;
+wire             D_op_opx_rsv42;
+wire             D_op_opx_rsv43;
+wire             D_op_opx_rsv44;
+wire             D_op_opx_rsv47;
+wire             D_op_opx_rsv50;
+wire             D_op_opx_rsv51;
+wire             D_op_opx_rsv55;
+wire             D_op_opx_rsv56;
+wire             D_op_opx_rsv60;
+wire             D_op_opx_rsv63;
+wire             D_op_or;
+wire             D_op_orhi;
+wire             D_op_ori;
+wire             D_op_rdctl;
+wire             D_op_rdprs;
+wire             D_op_ret;
+wire             D_op_rol;
+wire             D_op_roli;
+wire             D_op_ror;
+wire             D_op_sll;
+wire             D_op_slli;
+wire             D_op_sra;
+wire             D_op_srai;
+wire             D_op_srl;
+wire             D_op_srli;
+wire             D_op_stb;
+wire             D_op_stbio;
+wire             D_op_stc;
+wire             D_op_sth;
+wire             D_op_sthio;
+wire             D_op_stw;
+wire             D_op_stwio;
+wire             D_op_sub;
+wire             D_op_sync;
+wire             D_op_trap;
+wire             D_op_wrctl;
+wire             D_op_wrprs;
+wire             D_op_xor;
+wire             D_op_xorhi;
+wire             D_op_xori;
+wire    [ 31: 0] av_ld_data_aligned_filtered;
+wire             av_ld_data_aligned_unfiltered_0_is_x;
+wire             av_ld_data_aligned_unfiltered_10_is_x;
+wire             av_ld_data_aligned_unfiltered_11_is_x;
+wire             av_ld_data_aligned_unfiltered_12_is_x;
+wire             av_ld_data_aligned_unfiltered_13_is_x;
+wire             av_ld_data_aligned_unfiltered_14_is_x;
+wire             av_ld_data_aligned_unfiltered_15_is_x;
+wire             av_ld_data_aligned_unfiltered_16_is_x;
+wire             av_ld_data_aligned_unfiltered_17_is_x;
+wire             av_ld_data_aligned_unfiltered_18_is_x;
+wire             av_ld_data_aligned_unfiltered_19_is_x;
+wire             av_ld_data_aligned_unfiltered_1_is_x;
+wire             av_ld_data_aligned_unfiltered_20_is_x;
+wire             av_ld_data_aligned_unfiltered_21_is_x;
+wire             av_ld_data_aligned_unfiltered_22_is_x;
+wire             av_ld_data_aligned_unfiltered_23_is_x;
+wire             av_ld_data_aligned_unfiltered_24_is_x;
+wire             av_ld_data_aligned_unfiltered_25_is_x;
+wire             av_ld_data_aligned_unfiltered_26_is_x;
+wire             av_ld_data_aligned_unfiltered_27_is_x;
+wire             av_ld_data_aligned_unfiltered_28_is_x;
+wire             av_ld_data_aligned_unfiltered_29_is_x;
+wire             av_ld_data_aligned_unfiltered_2_is_x;
+wire             av_ld_data_aligned_unfiltered_30_is_x;
+wire             av_ld_data_aligned_unfiltered_31_is_x;
+wire             av_ld_data_aligned_unfiltered_3_is_x;
+wire             av_ld_data_aligned_unfiltered_4_is_x;
+wire             av_ld_data_aligned_unfiltered_5_is_x;
+wire             av_ld_data_aligned_unfiltered_6_is_x;
+wire             av_ld_data_aligned_unfiltered_7_is_x;
+wire             av_ld_data_aligned_unfiltered_8_is_x;
+wire             av_ld_data_aligned_unfiltered_9_is_x;
+wire             test_has_ended;
+  assign D_op_call = D_iw_op == 0;
+  assign D_op_jmpi = D_iw_op == 1;
+  assign D_op_op_rsv02 = D_iw_op == 2;
+  assign D_op_ldbu = D_iw_op == 3;
+  assign D_op_addi = D_iw_op == 4;
+  assign D_op_stb = D_iw_op == 5;
+  assign D_op_br = D_iw_op == 6;
+  assign D_op_ldb = D_iw_op == 7;
+  assign D_op_cmpgei = D_iw_op == 8;
+  assign D_op_op_rsv09 = D_iw_op == 9;
+  assign D_op_op_rsv10 = D_iw_op == 10;
+  assign D_op_ldhu = D_iw_op == 11;
+  assign D_op_andi = D_iw_op == 12;
+  assign D_op_sth = D_iw_op == 13;
+  assign D_op_bge = D_iw_op == 14;
+  assign D_op_ldh = D_iw_op == 15;
+  assign D_op_cmplti = D_iw_op == 16;
+  assign D_op_op_rsv17 = D_iw_op == 17;
+  assign D_op_op_rsv18 = D_iw_op == 18;
+  assign D_op_initda = D_iw_op == 19;
+  assign D_op_ori = D_iw_op == 20;
+  assign D_op_stw = D_iw_op == 21;
+  assign D_op_blt = D_iw_op == 22;
+  assign D_op_ldw = D_iw_op == 23;
+  assign D_op_cmpnei = D_iw_op == 24;
+  assign D_op_op_rsv25 = D_iw_op == 25;
+  assign D_op_op_rsv26 = D_iw_op == 26;
+  assign D_op_flushda = D_iw_op == 27;
+  assign D_op_xori = D_iw_op == 28;
+  assign D_op_stc = D_iw_op == 29;
+  assign D_op_bne = D_iw_op == 30;
+  assign D_op_ldl = D_iw_op == 31;
+  assign D_op_cmpeqi = D_iw_op == 32;
+  assign D_op_op_rsv33 = D_iw_op == 33;
+  assign D_op_op_rsv34 = D_iw_op == 34;
+  assign D_op_ldbuio = D_iw_op == 35;
+  assign D_op_muli = D_iw_op == 36;
+  assign D_op_stbio = D_iw_op == 37;
+  assign D_op_beq = D_iw_op == 38;
+  assign D_op_ldbio = D_iw_op == 39;
+  assign D_op_cmpgeui = D_iw_op == 40;
+  assign D_op_op_rsv41 = D_iw_op == 41;
+  assign D_op_op_rsv42 = D_iw_op == 42;
+  assign D_op_ldhuio = D_iw_op == 43;
+  assign D_op_andhi = D_iw_op == 44;
+  assign D_op_sthio = D_iw_op == 45;
+  assign D_op_bgeu = D_iw_op == 46;
+  assign D_op_ldhio = D_iw_op == 47;
+  assign D_op_cmpltui = D_iw_op == 48;
+  assign D_op_op_rsv49 = D_iw_op == 49;
+  assign D_op_custom = D_iw_op == 50;
+  assign D_op_initd = D_iw_op == 51;
+  assign D_op_orhi = D_iw_op == 52;
+  assign D_op_stwio = D_iw_op == 53;
+  assign D_op_bltu = D_iw_op == 54;
+  assign D_op_ldwio = D_iw_op == 55;
+  assign D_op_rdprs = D_iw_op == 56;
+  assign D_op_op_rsv57 = D_iw_op == 57;
+  assign D_op_flushd = D_iw_op == 59;
+  assign D_op_xorhi = D_iw_op == 60;
+  assign D_op_op_rsv61 = D_iw_op == 61;
+  assign D_op_op_rsv62 = D_iw_op == 62;
+  assign D_op_op_rsv63 = D_iw_op == 63;
+  assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
+  assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
+  assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
+  assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
+  assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
+  assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
+  assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
+  assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
+  assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
+  assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
+  assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
+  assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
+  assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
+  assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
+  assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
+  assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
+  assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
+  assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
+  assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
+  assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
+  assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
+  assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
+  assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
+  assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
+  assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
+  assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
+  assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
+  assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
+  assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
+  assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
+  assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
+  assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
+  assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
+  assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
+  assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
+  assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
+  assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
+  assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
+  assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
+  assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
+  assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
+  assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
+  assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
+  assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
+  assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
+  assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
+  assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
+  assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
+  assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
+  assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
+  assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
+  assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
+  assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
+  assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
+  assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
+  assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
+  assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
+  assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
+  assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
+  assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
+  assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
+  assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
+  assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
+  assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
+  assign D_is_opx_inst = D_iw_op == 58;
+  assign test_has_ended = 1'b0;
+
+//synthesis translate_off
+//////////////// SIMULATION-ONLY CONTENTS
+  //Clearing 'X' data bits
+  assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
+
+  assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
+  assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
+  assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
+  assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
+  assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
+  assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
+  assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
+  assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
+  assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
+  assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
+  assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
+  assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
+  assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
+  assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
+  assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
+  assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
+  assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
+  assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
+  assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
+  assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
+  assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
+  assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
+  assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
+  assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
+  assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
+  assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
+  assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
+  assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
+  assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
+  assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
+  assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
+  assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
+  assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
+  assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
+  assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
+  assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
+  assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
+  assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
+  assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
+  assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
+  assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
+  assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
+  assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
+  assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
+  assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
+  assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
+  assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
+  assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
+  assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
+  assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
+  assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
+  assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
+  assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
+  assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
+  assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
+  assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
+  assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
+  assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
+  assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
+  assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
+  assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
+  assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
+  assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(F_valid) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/F_valid is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(D_valid) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/D_valid is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(E_valid) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/E_valid is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(W_valid) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/W_valid is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (W_valid)
+          if (^(R_wr_dst_reg) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/R_wr_dst_reg is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (W_valid & R_wr_dst_reg)
+          if (^(W_wr_data) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/W_wr_data is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (W_valid & R_wr_dst_reg)
+          if (^(R_dst_regnum) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/R_dst_regnum is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(d_write) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/d_write is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (d_write)
+          if (^(d_byteenable) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/d_byteenable is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (d_write | d_read)
+          if (^(d_address) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/d_address is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(d_read) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/d_read is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk)
+    begin
+      if (reset_n)
+          if (^(i_read) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/i_read is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (i_read)
+          if (^(i_address) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/i_address is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (i_read & ~i_waitrequest)
+          if (^(i_readdata) === 1'bx)
+            begin
+              $write("%0d ns: ERROR: nios2_uc_nios2_cpu_test_bench/i_readdata is 'x'\n", $time);
+              $stop;
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (W_valid & R_ctrl_ld)
+          if (^(av_ld_data_aligned_unfiltered) === 1'bx)
+            begin
+              $write("%0d ns: WARNING: nios2_uc_nios2_cpu_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
+            end
+    end
+
+
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+        begin
+        end
+      else if (W_valid & R_wr_dst_reg)
+          if (^(W_wr_data) === 1'bx)
+            begin
+              $write("%0d ns: WARNING: nios2_uc_nios2_cpu_test_bench/W_wr_data is 'x'\n", $time);
+            end
+    end
+
+
+
+//////////////// END SIMULATION-ONLY CONTENTS
+
+//synthesis translate_on
+//synthesis read_comments_as_HDL on
+//  
+//  assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
+//
+//synthesis read_comments_as_HDL off
+
+endmodule
+

nios2_uc/synthesis/submodules/nios2_uc_onchip_memory2.v

@@ -0,0 +1,89 @@
+//Legal Notice: (C)2020 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_onchip_memory2 (
+                                 // inputs:
+                                  address,
+                                  byteenable,
+                                  chipselect,
+                                  clk,
+                                  clken,
+                                  freeze,
+                                  reset,
+                                  reset_req,
+                                  write,
+                                  writedata,
+
+                                 // outputs:
+                                  readdata
+                               )
+;
+
+  parameter INIT_FILE = "nios2_uc_onchip_memory2.hex";
+
+
+  output  [ 31: 0] readdata;
+  input   [ 15: 0] address;
+  input   [  3: 0] byteenable;
+  input            chipselect;
+  input            clk;
+  input            clken;
+  input            freeze;
+  input            reset;
+  input            reset_req;
+  input            write;
+  input   [ 31: 0] writedata;
+
+
+wire             clocken0;
+wire    [ 31: 0] readdata;
+wire             wren;
+  assign wren = chipselect & write;
+  assign clocken0 = clken & ~reset_req;
+  altsyncram the_altsyncram
+    (
+      .address_a (address),
+      .byteena_a (byteenable),
+      .clock0 (clk),
+      .clocken0 (clocken0),
+      .data_a (writedata),
+      .q_a (readdata),
+      .wren_a (wren)
+    );
+
+  defparam the_altsyncram.byte_size = 8,
+           the_altsyncram.init_file = INIT_FILE,
+           the_altsyncram.lpm_type = "altsyncram",
+           the_altsyncram.maximum_depth = 51200,
+           the_altsyncram.numwords_a = 51200,
+           the_altsyncram.operation_mode = "SINGLE_PORT",
+           the_altsyncram.outdata_reg_a = "UNREGISTERED",
+           the_altsyncram.ram_block_type = "AUTO",
+           the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
+           the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
+           the_altsyncram.width_a = 32,
+           the_altsyncram.width_byteena_a = 4,
+           the_altsyncram.widthad_a = 16;
+
+  //s1, which is an e_avalon_slave
+  //s2, which is an e_avalon_slave
+
+endmodule
+

nios2_uc/synthesis/submodules/nios2_uc_pio_LED.v

@@ -0,0 +1,67 @@
+//Legal Notice: (C)2020 Altera Corporation. All rights reserved.  Your
+//use of Altera Corporation's design tools, logic functions and other
+//software and tools, and its AMPP partner logic functions, and any
+//output files any of the foregoing (including device programming or
+//simulation files), and any associated documentation or information are
+//expressly subject to the terms and conditions of the Altera Program
+//License Subscription Agreement or other applicable license agreement,
+//including, without limitation, that your use is for the sole purpose
+//of programming logic devices manufactured by Altera and sold by Altera
+//or its authorized distributors.  Please refer to the applicable
+//agreement for further details.
+
+// synthesis translate_off
+`timescale 1ns / 1ps
+// synthesis translate_on
+
+// turn off superfluous verilog processor warnings 
+// altera message_level Level1 
+// altera message_off 10034 10035 10036 10037 10230 10240 10030 
+
+module nios2_uc_pio_LED (
+                          // inputs:
+                           address,
+                           chipselect,
+                           clk,
+                           reset_n,
+                           write_n,
+                           writedata,
+
+                          // outputs:
+                           out_port,
+                           readdata
+                        )
+;
+
+  output  [ 31: 0] out_port;
+  output  [ 31: 0] readdata;
+  input   [  1: 0] address;
+  input            chipselect;
+  input            clk;
+  input            reset_n;
+  input            write_n;
+  input   [ 31: 0] writedata;
+
+
+wire             clk_en;
+reg     [ 31: 0] data_out;
+wire    [ 31: 0] out_port;
+wire    [ 31: 0] read_mux_out;
+wire    [ 31: 0] readdata;
+  assign clk_en = 1;
+  //s1, which is an e_avalon_slave
+  assign read_mux_out = {32 {(address == 0)}} & data_out;
+  always @(posedge clk or negedge reset_n)
+    begin
+      if (reset_n == 0)
+          data_out <= 0;
+      else if (chipselect && ~write_n && (address == 0))
+          data_out <= writedata[31 : 0];
+    end
+
+
+  assign readdata = {32'b0 | read_mux_out};
+  assign out_port = data_out;
+
+endmodule
+

output_files/myfirst_niosii.cdf

@@ -0,0 +1,13 @@
+/* Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(EP4CE115F29) Path("/home/sstudent/HS-Codesign/HS-Codesign/niosii_20201119/output_files/") File("myfirst_niosii.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;

output_files/myfirst_niosii.sld

@@ -0,0 +1,14 @@
+<sld_project_info>
+  <sld_infos>
+    <sld_info hpath="nios2_uc:u0" name="u0">
+      <assignment_values>
+        <assignment_value text="QSYS_NAME nios2_uc HAS_SOPCINFO 1 GENERATION_ID 1605800269"/>
+      </assignment_values>
+    </sld_info>
+    <sld_info hpath="sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:instrumentation_fabric" library="alt_sld_fab" name="instrumentation_fabric">
+      <assignment_values>
+        <assignment_value text="QSYS_NAME alt_sld_fab HAS_SOPCINFO 1"/>
+      </assignment_values>
+    </sld_info>
+  </sld_infos>
+</sld_project_info>

software/.metadata/.plugins/org.eclipse.cdt.core/hello_world.language.settings.xml

@@ -0,0 +1,2505 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1616516038" name="Nios II">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider id="altera.tool.Nios2GCCBuiltinSpecsDetector">
+				<language id="org.eclipse.cdt.core.gcc">
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/lib/gcc/nios2-elf/5.3.0/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/lib/gcc/nios2-elf/5.3.0/include-fixed">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/nios2-elf/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="NIOS2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQUIRE" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQ_REL" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_CONSUME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELAXED" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELEASE" value="3">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_SEQ_CST" value="5">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BIGGEST_ALIGNMENT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BYTE_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR_BIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DECIMAL_DIG__" value="17">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DENORM_MIN__" value="((double)4.9406564584124654e-324L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DIG__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_EPSILON__" value="((double)2.2204460492503131e-16L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MANT_DIG__" value="53">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX_10_EXP__" value="308">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX_EXP__" value="1024">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX__" value="((double)1.7976931348623157e+308L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN_10_EXP__" value="(-307)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN_EXP__" value="(-1021)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN__" value="((double)2.2250738585072014e-308L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_EPSILON__" value="1E-33DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MANT_DIG__" value="34">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MAX_EXP__" value="6145">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MAX__" value="9.999999999999999999999999999999999E6144DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MIN_EXP__" value="(-6142)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MIN__" value="1E-6143DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_SUBNORMAL_MIN__" value="0.000000000000000000000000000000001E-6143DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_EPSILON__" value="1E-6DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MANT_DIG__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MAX_EXP__" value="97">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MAX__" value="9.999999E96DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MIN_EXP__" value="(-94)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MIN__" value="1E-95DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_SUBNORMAL_MIN__" value="0.000001E-95DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_EPSILON__" value="1E-15DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MANT_DIG__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MAX_EXP__" value="385">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MAX__" value="9.999999999999999E384DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MIN_EXP__" value="(-382)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MIN__" value="1E-383DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_SUBNORMAL_MIN__" value="0.000000000000001E-383DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DECIMAL_DIG__" value="17">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC_EVAL_METHOD__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ELF__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FINITE_MATH_ONLY__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLOAT_WORD_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DECIMAL_DIG__" value="9">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DENORM_MIN__" value="1.4012984643248171e-45F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DIG__" value="6">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_EPSILON__" value="1.1920928955078125e-7F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_EVAL_METHOD__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MANT_DIG__" value="24">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX_10_EXP__" value="38">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX_EXP__" value="128">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX__" value="3.4028234663852886e+38F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN_10_EXP__" value="(-37)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN_EXP__" value="(-125)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN__" value="1.1754943508222875e-38F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_RADIX__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_BOOL_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_CHAR16_T_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_CHAR32_T_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_CHAR_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_INT_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_LLONG_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_LONG_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_POINTER_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_SHORT_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_TEST_AND_SET_TRUEVAL" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_WCHAR_T_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_IEC_559" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_IEC_559_COMPLEX" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC_MINOR__" value="3">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC_PATCHLEVEL__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC_STDC_INLINE__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC__" value="5">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GXX_ABI_VERSION" value="1009">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT16_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT16_MAX__" value="0x7fff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT16_TYPE__" value="short int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT32_C(c)" value="c ## L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT32_MAX__" value="0x7fffffffL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT32_TYPE__" value="long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT64_C(c)" value="c ## LL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT64_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT64_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT8_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT8_MAX__" value="0x7f">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT8_TYPE__" value="signed char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTMAX_C(c)" value="c ## LL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTMAX_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTMAX_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTPTR_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTPTR_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST16_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST16_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST32_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST32_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST64_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST64_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST8_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST8_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST16_MAX__" value="0x7fff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST16_TYPE__" value="short int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST32_MAX__" value="0x7fffffffL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST32_TYPE__" value="long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST64_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST64_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST8_MAX__" value="0x7f">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST8_TYPE__" value="signed char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_DENORM_MIN__" value="4.9406564584124654e-324L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_DIG__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_EPSILON__" value="2.2204460492503131e-16L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MANT_DIG__" value="53">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX_10_EXP__" value="308">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX_EXP__" value="1024">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX__" value="1.7976931348623157e+308L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN_10_EXP__" value="(-307)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN_EXP__" value="(-1021)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN__" value="2.2250738585072014e-308L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LONG_LONG_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LONG_MAX__" value="0x7fffffffL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NIOS2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NIOS2__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NO_INLINE__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_BIG_ENDIAN__" value="4321">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_LITTLE_ENDIAN__" value="1234">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_PDP_ENDIAN__" value="3412">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PRAGMA_REDEFINE_EXTNAME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PTRDIFF_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PTRDIFF_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__REGISTER_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SCHAR_MAX__" value="0x7f">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SHRT_MAX__" value="0x7fff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_MIN__" value="(-__SIG_ATOMIC_MAX__ - 1)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_FLOAT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_INT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG_LONG__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_POINTER__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_PTRDIFF_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SHORT__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SIZE_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_WCHAR_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_WINT_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_HOSTED__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_UTF_16__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_UTF_32__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_VERSION__" value="201112L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_MAX__" value="0xffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_C(c)" value="c ## UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_MAX__" value="0xffffffffUL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_MAX__" value="0xff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_MAX__" value="0xffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_MAX__" value="0xffffffffUL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_MAX__" value="0xff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USER_LABEL_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USING_SJLJ_EXCEPTIONS__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VERSION__" value="&quot;5.3.0&quot;">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MIN__" value="(-__WCHAR_MAX__ - 1)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MIN__" value="0U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__has_include(STR)" value="__has_include__(STR)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__has_include_next(STR)" value="__has_include_next__(STR)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2_arch__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2_little_endian" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2_little_endian__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="nios2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="nios2_little_endian" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+				</language>
+				<language id="org.eclipse.cdt.core.g++">
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/nios2-elf/include/c++/5.3.0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/nios2-elf/include/c++/5.3.0/nios2-elf">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/nios2-elf/include/c++/5.3.0/backward">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/lib/gcc/nios2-elf/5.3.0/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/lib/gcc/nios2-elf/5.3.0/include-fixed">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/nios2-elf/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="NIOS2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQUIRE" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQ_REL" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_CONSUME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELAXED" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELEASE" value="3">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_SEQ_CST" value="5">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BIGGEST_ALIGNMENT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BYTE_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR_BIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DECIMAL_DIG__" value="17">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DENORM_MIN__" value="double(4.9406564584124654e-324L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DIG__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_EPSILON__" value="double(2.2204460492503131e-16L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MANT_DIG__" value="53">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX_10_EXP__" value="308">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX_EXP__" value="1024">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX__" value="double(1.7976931348623157e+308L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN_10_EXP__" value="(-307)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN_EXP__" value="(-1021)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN__" value="double(2.2250738585072014e-308L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_EPSILON__" value="1E-33DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MANT_DIG__" value="34">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MAX_EXP__" value="6145">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MAX__" value="9.999999999999999999999999999999999E6144DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MIN_EXP__" value="(-6142)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MIN__" value="1E-6143DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_SUBNORMAL_MIN__" value="0.000000000000000000000000000000001E-6143DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_EPSILON__" value="1E-6DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MANT_DIG__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MAX_EXP__" value="97">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MAX__" value="9.999999E96DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MIN_EXP__" value="(-94)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MIN__" value="1E-95DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_SUBNORMAL_MIN__" value="0.000001E-95DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_EPSILON__" value="1E-15DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MANT_DIG__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MAX_EXP__" value="385">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MAX__" value="9.999999999999999E384DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MIN_EXP__" value="(-382)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MIN__" value="1E-383DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_SUBNORMAL_MIN__" value="0.000000000000001E-383DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DECIMAL_DIG__" value="17">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC_EVAL_METHOD__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEPRECATED" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ELF__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__EXCEPTIONS" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FINITE_MATH_ONLY__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLOAT_WORD_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DECIMAL_DIG__" value="9">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DENORM_MIN__" value="1.4012984643248171e-45F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DIG__" value="6">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_EPSILON__" value="1.1920928955078125e-7F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_EVAL_METHOD__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MANT_DIG__" value="24">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX_10_EXP__" value="38">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX_EXP__" value="128">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX__" value="3.4028234663852886e+38F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN_10_EXP__" value="(-37)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN_EXP__" value="(-125)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN__" value="1.1754943508222875e-38F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_RADIX__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_BOOL_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_CHAR16_T_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_CHAR32_T_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_CHAR_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_INT_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_LLONG_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_LONG_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_POINTER_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_SHORT_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_TEST_AND_SET_TRUEVAL" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_WCHAR_T_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_IEC_559" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_IEC_559_COMPLEX" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC_GNU_INLINE__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC_MINOR__" value="3">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC_PATCHLEVEL__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC__" value="5">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUG__" value="5">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GXX_ABI_VERSION" value="1009">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GXX_RTTI" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GXX_WEAK__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT16_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT16_MAX__" value="0x7fff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT16_TYPE__" value="short int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT32_C(c)" value="c ## L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT32_MAX__" value="0x7fffffffL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT32_TYPE__" value="long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT64_C(c)" value="c ## LL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT64_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT64_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT8_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT8_MAX__" value="0x7f">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT8_TYPE__" value="signed char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTMAX_C(c)" value="c ## LL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTMAX_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTMAX_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTPTR_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTPTR_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST16_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST16_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST32_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST32_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST64_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST64_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST8_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST8_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST16_MAX__" value="0x7fff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST16_TYPE__" value="short int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST32_MAX__" value="0x7fffffffL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST32_TYPE__" value="long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST64_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST64_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST8_MAX__" value="0x7f">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST8_TYPE__" value="signed char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_DENORM_MIN__" value="4.9406564584124654e-324L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_DIG__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_EPSILON__" value="2.2204460492503131e-16L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MANT_DIG__" value="53">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX_10_EXP__" value="308">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX_EXP__" value="1024">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX__" value="1.7976931348623157e+308L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN_10_EXP__" value="(-307)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN_EXP__" value="(-1021)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN__" value="2.2250738585072014e-308L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LONG_LONG_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LONG_MAX__" value="0x7fffffffL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NIOS2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NIOS2__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NO_INLINE__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_BIG_ENDIAN__" value="4321">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_LITTLE_ENDIAN__" value="1234">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_PDP_ENDIAN__" value="3412">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PRAGMA_REDEFINE_EXTNAME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PTRDIFF_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PTRDIFF_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__REGISTER_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SCHAR_MAX__" value="0x7f">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SHRT_MAX__" value="0x7fff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_MIN__" value="(-__SIG_ATOMIC_MAX__ - 1)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_FLOAT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_INT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG_LONG__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_POINTER__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_PTRDIFF_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SHORT__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SIZE_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_WCHAR_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_WINT_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_HOSTED__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_MAX__" value="0xffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_C(c)" value="c ## UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_MAX__" value="0xffffffffUL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_MAX__" value="0xff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_MAX__" value="0xffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_MAX__" value="0xffffffffUL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_MAX__" value="0xff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USER_LABEL_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USING_SJLJ_EXCEPTIONS__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VERSION__" value="&quot;5.3.0&quot;">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MIN__" value="(-__WCHAR_MAX__ - 1)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MIN__" value="0U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cplusplus" value="199711L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cpp_binary_literals" value="201304">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cpp_exceptions" value="199711">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cpp_rtti" value="199711">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cpp_runtime_arrays" value="198712">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__has_include(STR)" value="__has_include__(STR)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__has_include_next(STR)" value="__has_include_next__(STR)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2_arch__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2_little_endian" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2_little_endian__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="nios2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="nios2_little_endian" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+				</language>
+			</provider>
+			<provider id="altera.tool.Nios2GCCBuildCommandParser">
+				<language id="org.eclipse.cdt.core.gcc">
+					<resource project-relative-path="HAL/src/alt_uncached_free.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_wait.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="alt_sys_init.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="drivers/src/altera_avalon_jtag_uart_ioctl.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_printf.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_ioctl.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_fcntl.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="drivers/src/altera_avalon_jtag_uart_read.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_instruction_exception_entry.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_irq_register.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_uncached_malloc.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_usleep.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_dev_llist_insert.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_fd_unlock.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_log_printf.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_environ.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_icache_flush.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_execve.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_remap_cached.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_remap_uncached.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_stat.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="drivers/src/altera_avalon_jtag_uart_fd.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_dcache_flush_all.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_errno.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_exit.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_icache_flush_all.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_alarm_start.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_dcache_flush_no_writeback.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_get_fd.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_dev.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_putchar.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_tick.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_close.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_link.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_io_redirect.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_irq_handler.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_write.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_iic.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_ecc_fatal_exception.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_fork.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_dma_rxchan_open.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_settod.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_find_file.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_dcache_flush.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_dma_txchan_open.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_read.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_busy_sleep.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_fstat.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_do_ctors.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_getchar.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_sbrk.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_fs_reg.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_malloc_lock.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_rename.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_flash_dev.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_instruction_exception_register.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_open.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_find_dev.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_gettod.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="drivers/src/altera_avalon_jtag_uart_write.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_isatty.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_lseek.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_putcharbuf.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_env_lock.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_fd_lock.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="drivers/src/altera_avalon_jtag_uart_init.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_release_fd.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_do_dtors.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_getpid.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_unlink.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_load.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_putstr.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_times.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_kill.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_main.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="hello_world.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/altera_nios2_gen2_irq.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_iic_isr_register.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_gmon.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+					<resource project-relative-path="HAL/src/alt_irq_vars.c">
+						<entry kind="includePath" name="/hello_world_bsp/HAL/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="includePath" name="/hello_world_bsp/drivers/inc">
+							<flag value="VALUE_WORKSPACE_PATH|RESOLVED"/>
+						</entry>
+						<entry kind="macro" name="ALT_NO_INSTRUCTION_EMULATION" value=""/>
+						<entry kind="macro" name="ALT_SINGLE_THREADED" value=""/>
+						<entry kind="macro" name="__hal__" value=""/>
+					</resource>
+				</language>
+			</provider>
+		</extension>
+	</configuration>
+</project>

software/.metadata/.plugins/org.eclipse.cdt.core/hello_world_bsp.language.settings.xml

@@ -0,0 +1,1381 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.603004973" name="Nios II">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider id="altera.tool.Nios2GCCBuiltinSpecsDetector">
+				<language id="org.eclipse.cdt.core.gcc">
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/lib/gcc/nios2-elf/5.3.0/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/lib/gcc/nios2-elf/5.3.0/include-fixed">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/nios2-elf/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="NIOS2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQUIRE" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQ_REL" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_CONSUME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELAXED" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELEASE" value="3">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_SEQ_CST" value="5">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BIGGEST_ALIGNMENT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BYTE_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR_BIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DECIMAL_DIG__" value="17">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DENORM_MIN__" value="((double)4.9406564584124654e-324L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DIG__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_EPSILON__" value="((double)2.2204460492503131e-16L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MANT_DIG__" value="53">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX_10_EXP__" value="308">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX_EXP__" value="1024">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX__" value="((double)1.7976931348623157e+308L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN_10_EXP__" value="(-307)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN_EXP__" value="(-1021)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN__" value="((double)2.2250738585072014e-308L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_EPSILON__" value="1E-33DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MANT_DIG__" value="34">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MAX_EXP__" value="6145">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MAX__" value="9.999999999999999999999999999999999E6144DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MIN_EXP__" value="(-6142)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MIN__" value="1E-6143DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_SUBNORMAL_MIN__" value="0.000000000000000000000000000000001E-6143DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_EPSILON__" value="1E-6DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MANT_DIG__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MAX_EXP__" value="97">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MAX__" value="9.999999E96DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MIN_EXP__" value="(-94)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MIN__" value="1E-95DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_SUBNORMAL_MIN__" value="0.000001E-95DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_EPSILON__" value="1E-15DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MANT_DIG__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MAX_EXP__" value="385">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MAX__" value="9.999999999999999E384DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MIN_EXP__" value="(-382)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MIN__" value="1E-383DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_SUBNORMAL_MIN__" value="0.000000000000001E-383DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DECIMAL_DIG__" value="17">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC_EVAL_METHOD__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ELF__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FINITE_MATH_ONLY__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLOAT_WORD_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DECIMAL_DIG__" value="9">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DENORM_MIN__" value="1.4012984643248171e-45F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DIG__" value="6">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_EPSILON__" value="1.1920928955078125e-7F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_EVAL_METHOD__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MANT_DIG__" value="24">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX_10_EXP__" value="38">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX_EXP__" value="128">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX__" value="3.4028234663852886e+38F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN_10_EXP__" value="(-37)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN_EXP__" value="(-125)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN__" value="1.1754943508222875e-38F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_RADIX__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_BOOL_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_CHAR16_T_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_CHAR32_T_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_CHAR_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_INT_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_LLONG_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_LONG_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_POINTER_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_SHORT_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_TEST_AND_SET_TRUEVAL" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_WCHAR_T_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_IEC_559" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_IEC_559_COMPLEX" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC_MINOR__" value="3">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC_PATCHLEVEL__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC_STDC_INLINE__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC__" value="5">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GXX_ABI_VERSION" value="1009">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT16_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT16_MAX__" value="0x7fff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT16_TYPE__" value="short int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT32_C(c)" value="c ## L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT32_MAX__" value="0x7fffffffL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT32_TYPE__" value="long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT64_C(c)" value="c ## LL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT64_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT64_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT8_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT8_MAX__" value="0x7f">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT8_TYPE__" value="signed char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTMAX_C(c)" value="c ## LL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTMAX_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTMAX_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTPTR_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTPTR_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST16_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST16_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST32_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST32_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST64_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST64_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST8_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST8_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST16_MAX__" value="0x7fff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST16_TYPE__" value="short int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST32_MAX__" value="0x7fffffffL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST32_TYPE__" value="long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST64_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST64_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST8_MAX__" value="0x7f">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST8_TYPE__" value="signed char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_DENORM_MIN__" value="4.9406564584124654e-324L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_DIG__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_EPSILON__" value="2.2204460492503131e-16L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MANT_DIG__" value="53">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX_10_EXP__" value="308">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX_EXP__" value="1024">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX__" value="1.7976931348623157e+308L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN_10_EXP__" value="(-307)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN_EXP__" value="(-1021)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN__" value="2.2250738585072014e-308L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LONG_LONG_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LONG_MAX__" value="0x7fffffffL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NIOS2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NIOS2__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NO_INLINE__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_BIG_ENDIAN__" value="4321">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_LITTLE_ENDIAN__" value="1234">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_PDP_ENDIAN__" value="3412">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PRAGMA_REDEFINE_EXTNAME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PTRDIFF_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PTRDIFF_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__REGISTER_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SCHAR_MAX__" value="0x7f">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SHRT_MAX__" value="0x7fff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_MIN__" value="(-__SIG_ATOMIC_MAX__ - 1)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_FLOAT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_INT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG_LONG__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_POINTER__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_PTRDIFF_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SHORT__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SIZE_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_WCHAR_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_WINT_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_HOSTED__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_UTF_16__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_UTF_32__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_VERSION__" value="201112L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_MAX__" value="0xffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_C(c)" value="c ## UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_MAX__" value="0xffffffffUL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_MAX__" value="0xff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_MAX__" value="0xffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_MAX__" value="0xffffffffUL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_MAX__" value="0xff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USER_LABEL_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USING_SJLJ_EXCEPTIONS__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VERSION__" value="&quot;5.3.0&quot;">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MIN__" value="(-__WCHAR_MAX__ - 1)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MIN__" value="0U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__has_include(STR)" value="__has_include__(STR)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__has_include_next(STR)" value="__has_include_next__(STR)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2_arch__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2_little_endian" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2_little_endian__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="nios2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="nios2_little_endian" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+				</language>
+				<language id="org.eclipse.cdt.core.g++">
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/nios2-elf/include/c++/5.3.0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/nios2-elf/include/c++/5.3.0/nios2-elf">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/nios2-elf/include/c++/5.3.0/backward">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/lib/gcc/nios2-elf/5.3.0/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/lib/gcc/nios2-elf/5.3.0/include-fixed">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="/opt/intelFPGA/18.1/nios2eds/bin/gnu/H-x86_64-pc-linux-gnu/nios2-elf/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="NIOS2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQUIRE" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQ_REL" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_CONSUME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELAXED" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELEASE" value="3">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_SEQ_CST" value="5">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BIGGEST_ALIGNMENT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BYTE_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR_BIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DECIMAL_DIG__" value="17">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DENORM_MIN__" value="double(4.9406564584124654e-324L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DIG__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_EPSILON__" value="double(2.2204460492503131e-16L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MANT_DIG__" value="53">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX_10_EXP__" value="308">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX_EXP__" value="1024">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX__" value="double(1.7976931348623157e+308L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN_10_EXP__" value="(-307)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN_EXP__" value="(-1021)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN__" value="double(2.2250738585072014e-308L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_EPSILON__" value="1E-33DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MANT_DIG__" value="34">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MAX_EXP__" value="6145">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MAX__" value="9.999999999999999999999999999999999E6144DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MIN_EXP__" value="(-6142)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MIN__" value="1E-6143DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_SUBNORMAL_MIN__" value="0.000000000000000000000000000000001E-6143DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_EPSILON__" value="1E-6DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MANT_DIG__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MAX_EXP__" value="97">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MAX__" value="9.999999E96DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MIN_EXP__" value="(-94)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MIN__" value="1E-95DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_SUBNORMAL_MIN__" value="0.000001E-95DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_EPSILON__" value="1E-15DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MANT_DIG__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MAX_EXP__" value="385">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MAX__" value="9.999999999999999E384DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MIN_EXP__" value="(-382)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MIN__" value="1E-383DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_SUBNORMAL_MIN__" value="0.000000000000001E-383DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DECIMAL_DIG__" value="17">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC_EVAL_METHOD__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEPRECATED" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ELF__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__EXCEPTIONS" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FINITE_MATH_ONLY__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLOAT_WORD_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DECIMAL_DIG__" value="9">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DENORM_MIN__" value="1.4012984643248171e-45F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DIG__" value="6">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_EPSILON__" value="1.1920928955078125e-7F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_EVAL_METHOD__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MANT_DIG__" value="24">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX_10_EXP__" value="38">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX_EXP__" value="128">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX__" value="3.4028234663852886e+38F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN_10_EXP__" value="(-37)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN_EXP__" value="(-125)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN__" value="1.1754943508222875e-38F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_RADIX__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_BOOL_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_CHAR16_T_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_CHAR32_T_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_CHAR_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_INT_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_LLONG_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_LONG_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_POINTER_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_SHORT_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_TEST_AND_SET_TRUEVAL" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_ATOMIC_WCHAR_T_LOCK_FREE" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_IEC_559" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GCC_IEC_559_COMPLEX" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC_GNU_INLINE__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC_MINOR__" value="3">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC_PATCHLEVEL__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUC__" value="5">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GNUG__" value="5">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GXX_ABI_VERSION" value="1009">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GXX_RTTI" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__GXX_WEAK__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT16_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT16_MAX__" value="0x7fff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT16_TYPE__" value="short int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT32_C(c)" value="c ## L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT32_MAX__" value="0x7fffffffL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT32_TYPE__" value="long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT64_C(c)" value="c ## LL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT64_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT64_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT8_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT8_MAX__" value="0x7f">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT8_TYPE__" value="signed char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTMAX_C(c)" value="c ## LL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTMAX_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTMAX_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTPTR_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTPTR_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST16_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST16_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST32_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST32_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST64_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST64_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST8_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_FAST8_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST16_MAX__" value="0x7fff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST16_TYPE__" value="short int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST32_MAX__" value="0x7fffffffL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST32_TYPE__" value="long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST64_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST64_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST8_MAX__" value="0x7f">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_LEAST8_TYPE__" value="signed char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INT_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_DENORM_MIN__" value="4.9406564584124654e-324L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_DIG__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_EPSILON__" value="2.2204460492503131e-16L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MANT_DIG__" value="53">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX_10_EXP__" value="308">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX_EXP__" value="1024">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX__" value="1.7976931348623157e+308L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN_10_EXP__" value="(-307)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN_EXP__" value="(-1021)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN__" value="2.2250738585072014e-308L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LONG_LONG_MAX__" value="0x7fffffffffffffffLL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LONG_MAX__" value="0x7fffffffL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NIOS2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NIOS2__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NO_INLINE__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_BIG_ENDIAN__" value="4321">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_LITTLE_ENDIAN__" value="1234">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_PDP_ENDIAN__" value="3412">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PRAGMA_REDEFINE_EXTNAME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PTRDIFF_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PTRDIFF_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__REGISTER_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SCHAR_MAX__" value="0x7f">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SHRT_MAX__" value="0x7fff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_MIN__" value="(-__SIG_ATOMIC_MAX__ - 1)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_FLOAT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_INT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG_LONG__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_POINTER__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_PTRDIFF_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SHORT__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SIZE_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_WCHAR_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_WINT_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_HOSTED__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_MAX__" value="0xffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_C(c)" value="c ## UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_MAX__" value="0xffffffffUL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_MAX__" value="0xff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_MAX__" value="0xffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_MAX__" value="0xffffffffUL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_MAX__" value="0xffffffffffffffffULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_MAX__" value="0xff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USER_LABEL_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USING_SJLJ_EXCEPTIONS__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VERSION__" value="&quot;5.3.0&quot;">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MAX__" value="0x7fffffff">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MIN__" value="(-__WCHAR_MAX__ - 1)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MAX__" value="0xffffffffU">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MIN__" value="0U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cplusplus" value="199711L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cpp_binary_literals" value="201304">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cpp_exceptions" value="199711">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cpp_rtti" value="199711">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cpp_runtime_arrays" value="198712">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__has_include(STR)" value="__has_include__(STR)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__has_include_next(STR)" value="__has_include_next__(STR)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2_arch__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2_little_endian" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__nios2_little_endian__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="nios2" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="nios2_little_endian" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+				</language>
+			</provider>
+		</extension>
+	</configuration>
+</project>

software/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c

@@ -0,0 +1 @@
+

software/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp

@@ -0,0 +1 @@
+

software/.metadata/.plugins/org.eclipse.core.resources/.history/32/202feef1ef2f001b1545ef0b5631d2e4

@@ -0,0 +1,34 @@
+/*
+ * "Hello World" example.
+ *
+ * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on
+ * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example
+ * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT
+ * device in your system's hardware.
+ * The memory footprint of this hosted application is ~69 kbytes by default
+ * using the standard reference design.
+ *
+ * For a reduced footprint version of this template, and an explanation of how
+ * to reduce the memory footprint for a given application, see the
+ * "small_hello_world" template.
+ *
+ */
+
+#include <stdio.h>
+#include "altera_avalon_pio_regs.h"
+
+int main()
+{
+  printf("Hello from Nios II!\n");
+  int count = 0;
+
+  while(true) {
+	  printf("%d\n", count);
+	  IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, count++);
+	  for(int i=0; i<2000000; i++) {
+
+	  }
+  }
+
+  return 0;
+}

software/.metadata/.plugins/org.eclipse.core.resources/.history/50/403241c7ef2f001b1545ef0b5631d2e4

@@ -0,0 +1,33 @@
+/*
+ * "Hello World" example.
+ *
+ * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on
+ * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example
+ * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT
+ * device in your system's hardware.
+ * The memory footprint of this hosted application is ~69 kbytes by default
+ * using the standard reference design.
+ *
+ * For a reduced footprint version of this template, and an explanation of how
+ * to reduce the memory footprint for a given application, see the
+ * "small_hello_world" template.
+ *
+ */
+
+#include <stdio.h>
+#include "altera_avalon_pio_regs.h"
+
+int main()
+{
+  printf("Hello from Nios II!\n");
+  int count = 0;
+
+  while(true) {
+	  IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, count++);
+	  for(int i=0; i<2000000; i++) {
+
+	  }
+  }
+
+  return 0;
+}

software/.metadata/.plugins/org.eclipse.core.resources/.history/8f/502e43e9f12f001b1545ef0b5631d2e4

@@ -0,0 +1,35 @@
+/*
+ * "Hello World" example.
+ *
+ * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on
+ * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example
+ * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT
+ * device in your system's hardware.
+ * The memory footprint of this hosted application is ~69 kbytes by default
+ * using the standard reference design.
+ *
+ * For a reduced footprint version of this template, and an explanation of how
+ * to reduce the memory footprint for a given application, see the
+ * "small_hello_world" template.
+ *
+ */
+
+#include <stdio.h>
+#include "altera_avalon_pio_regs.h"
+#include <system.h>
+
+int main()
+{
+  printf("Hello from Nios II!\n");
+  int count = 0;
+
+  while(1) {
+	  printf("%d\n", count);
+	  IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, count++);
+	  for(int i=0; i<100000; i++) {
+
+	  }
+  }
+
+  return 0;
+}

software/.metadata/.plugins/org.eclipse.core.resources/.history/a5/c0d6e426f02f001b1545ef0b5631d2e4

@@ -0,0 +1,35 @@
+/*
+ * "Hello World" example.
+ *
+ * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on
+ * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example
+ * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT
+ * device in your system's hardware.
+ * The memory footprint of this hosted application is ~69 kbytes by default
+ * using the standard reference design.
+ *
+ * For a reduced footprint version of this template, and an explanation of how
+ * to reduce the memory footprint for a given application, see the
+ * "small_hello_world" template.
+ *
+ */
+
+#include <stdio.h>
+#include "altera_avalon_pio_regs.h"
+#include <system.h>
+
+int main()
+{
+  printf("Hello from Nios II!\n");
+  int count = 0;
+
+  while(1) {
+	  printf("%d\n", count);
+	  IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, count++);
+	  for(int i=0; i<2000000; i++) {
+
+	  }
+  }
+
+  return 0;
+}

software/.metadata/.plugins/org.eclipse.core.resources/.history/b7/608b34f6ef2f001b1545ef0b5631d2e4

@@ -0,0 +1,34 @@
+/*
+ * "Hello World" example.
+ *
+ * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on
+ * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example
+ * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT
+ * device in your system's hardware.
+ * The memory footprint of this hosted application is ~69 kbytes by default
+ * using the standard reference design.
+ *
+ * For a reduced footprint version of this template, and an explanation of how
+ * to reduce the memory footprint for a given application, see the
+ * "small_hello_world" template.
+ *
+ */
+
+#include <stdio.h>
+#include "altera_avalon_pio_regs.h"
+
+int main()
+{
+  printf("Hello from Nios II!\n");
+  int count = 0;
+
+  while(1) {
+	  printf("%d\n", count);
+	  IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED, count++);
+	  for(int i=0; i<2000000; i++) {
+
+	  }
+  }
+
+  return 0;
+}

software/.metadata/.plugins/org.eclipse.core.resources/.history/d2/901d0554f02f001b1545ef0b5631d2e4

@@ -0,0 +1,35 @@
+/*
+ * "Hello World" example.
+ *
+ * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on
+ * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example
+ * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT
+ * device in your system's hardware.
+ * The memory footprint of this hosted application is ~69 kbytes by default
+ * using the standard reference design.
+ *
+ * For a reduced footprint version of this template, and an explanation of how
+ * to reduce the memory footprint for a given application, see the
+ * "small_hello_world" template.
+ *
+ */
+
+#include <stdio.h>
+#include "altera_avalon_pio_regs.h"
+#include <system.h>
+
+int main()
+{
+  printf("Hello from Nios II!\n");
+  int count = 0;
+
+  while(1) {
+	  printf("%d\n", count);
+	  IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, count++);
+	  for(int i=0; i<500000; i++) {
+
+	  }
+  }
+
+  return 0;
+}

software/.metadata/.plugins/org.eclipse.core.resources/.history/d4/80e2f03df22f001b1545ef0b5631d2e4

@@ -0,0 +1,34 @@
+/*
+ * "Hello World" example.
+ *
+ * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on
+ * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example
+ * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT
+ * device in your system's hardware.
+ * The memory footprint of this hosted application is ~69 kbytes by default
+ * using the standard reference design.
+ *
+ * For a reduced footprint version of this template, and an explanation of how
+ * to reduce the memory footprint for a given application, see the
+ * "small_hello_world" template.
+ *
+ */
+
+#include <stdio.h>
+#include "altera_avalon_pio_regs.h"
+#include <system.h>
+
+int main()
+{
+  printf("Hello from Nios II!\n");
+  int count = 0;
+
+  while(1) {
+	  printf("%d\n", count);
+	  IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, count++);
+	  //for(int i=0; i<100000; i++) {
+	  //}
+  }
+
+  return 0;
+}

software/.metadata/.plugins/org.eclipse.core.resources/.history/e0/b060dd18f02f001b1545ef0b5631d2e4

@@ -0,0 +1,34 @@
+/*
+ * "Hello World" example.
+ *
+ * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on
+ * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example
+ * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT
+ * device in your system's hardware.
+ * The memory footprint of this hosted application is ~69 kbytes by default
+ * using the standard reference design.
+ *
+ * For a reduced footprint version of this template, and an explanation of how
+ * to reduce the memory footprint for a given application, see the
+ * "small_hello_world" template.
+ *
+ */
+
+#include <stdio.h>
+#include "altera_avalon_pio_regs.h"
+
+int main()
+{
+  printf("Hello from Nios II!\n");
+  int count = 0;
+
+  while(1) {
+	  printf("%d\n", count);
+	  IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, count++);
+	  for(int i=0; i<2000000; i++) {
+
+	  }
+  }
+
+  return 0;
+}

software/.metadata/.plugins/org.eclipse.core.resources/.history/f5/30a9ceb9ef2f001b1545ef0b5631d2e4

@@ -0,0 +1,24 @@
+/*
+ * "Hello World" example.
+ *
+ * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on
+ * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example
+ * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT
+ * device in your system's hardware.
+ * The memory footprint of this hosted application is ~69 kbytes by default
+ * using the standard reference design.
+ *
+ * For a reduced footprint version of this template, and an explanation of how
+ * to reduce the memory footprint for a given application, see the
+ * "small_hello_world" template.
+ *
+ */
+
+#include <stdio.h>
+
+int main()
+{
+  printf("Hello from Nios II!\n");
+
+  return 0;
+}

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.altera.sbtgui.ui.prefs

@@ -0,0 +1,4 @@
+eclipse.preferences.version=1
+newSoftwareExampleWizardPage.defaultLocation=/home/sstudent/HS-Codesign/HS-Codesign/niosii_20201119/software/hello_world
+newSoftwareExampleWizardPage.sopcinfoFile=/home/sstudent/HS-Codesign/HS-Codesign/niosii_20201119/nios2_uc.sopcinfo
+newSoftwareExampleWizardPage2.newBspLocation=/home/sstudent/HS-Codesign/HS-Codesign/niosii_20201119/software/hello_world_bsp

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-hello_world.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+indexer/preferenceScope=0

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-hello_world_bsp.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+indexer/preferenceScope=0

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.debug.core.cDebug.default_source_containers=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\n<sourceLookupDirector>\n<sourceContainers duplicates\="false">\n<container memento\="AbsolutePath" typeId\="org.eclipse.cdt.debug.core.containerType.absolutePath"/>\n<container memento\="programRelativePath" typeId\="org.eclipse.cdt.debug.core.containerType.programRelativePath"/>\n<container memento\="&lt;?xml version\=&quot;1.0&quot; encoding\=&quot;UTF-8&quot; standalone\=&quot;no&quot;?&gt;&\#10;&lt;project referencedProjects\=&quot;true&quot;/&gt;&\#10;" typeId\="org.eclipse.cdt.debug.core.containerType.project"/>\n</sourceContainers>\n</sourceLookupDirector>\n

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs

@@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+properties/hello_world.null.1232663156/preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1616516038=org.eclipse.cdt.build.core.settings.holder.818126668\=rebuildState\\\=true\\n\naltera.tool.gnu.cpp.linker.681709555\=rebuildState\\\=false\\n\naltera.tool.gnu.c.compiler.145552834\=rebuildState\\\=false\\n\naltera.tool.gnu.c.linker.1169005074\=rebuildState\\\=false\\n\naltera.tool.gnu.cpp.compiler.973565031\=rebuildState\\\=false\\n\naltera.nios2.linux.gcc4.1005046772\=rebuildState\\\=false\\n\naltera.tool.gnu.assembler.655282811\=rebuildState\\\=false\\n\naltera.tool.gnu.archiver.394076629\=rebuildState\\\=false\\n\norg.eclipse.cdt.build.core.settings.holder.libs.672759760\=rebuildState\\\=true\\n\npreference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1616516038\=rcState\\\=0\\nrebuildState\\\=false\\n\norg.eclipse.cdt.build.core.settings.holder.272524829\=rebuildState\\\=true\\n\norg.eclipse.cdt.build.core.prefbase.toolchain.593482184\=rebuildState\\\=true\\n\norg.eclipse.cdt.build.core.settings.holder.665904697\=rebuildState\\\=true\\n\n
+properties/hello_world_bsp.null.511316921/preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.603004973=org.eclipse.cdt.build.core.settings.holder.719992989\=rebuildState\\\=true\\n\naltera.tool.gnu.c.compiler.2129840421\=rebuildState\\\=true\\n\naltera.tool.gnu.cpp.compiler.441080672\=rebuildState\\\=true\\n\norg.eclipse.cdt.build.core.prefbase.toolchain.2103009207\=rebuildState\\\=true\\n\naltera.nios2.linux.gcc4.392043177\=rebuildState\\\=true\\n\norg.eclipse.cdt.build.core.settings.holder.libs.203059311\=rebuildState\\\=true\\n\naltera.tool.gnu.cpp.linker.1449706149\=rebuildState\\\=true\\n\norg.eclipse.cdt.build.core.settings.holder.2048312676\=rebuildState\\\=true\\n\naltera.tool.gnu.assembler.313202763\=rebuildState\\\=true\\n\naltera.tool.gnu.c.linker.2022682903\=rebuildState\\\=true\\n\naltera.tool.gnu.archiver.1818722045\=rebuildState\\\=true\\n\norg.eclipse.cdt.build.core.settings.holder.765233782\=rebuildState\\\=true\\n\npreference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.603004973\=rebuildState\\\=true\\n\n

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+version=1

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs

@@ -0,0 +1,5 @@
+//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.applicationLaunchType=org.eclipse.cdt.dsf.gdb.launch.localCLaunch,debug,;org.eclipse.cdt.cdi.launch.localCLaunch,run,;
+//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.attachLaunchType=org.eclipse.cdt.dsf.gdb.launch.attachCLaunch,debug,;
+//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.postmortemLaunchType=org.eclipse.cdt.dsf.gdb.launch.coreCLaunch,debug,;
+//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.remoteApplicationLaunchType=org.eclipse.rse.remotecdt.dsf.debug,debug,;
+eclipse.preferences.version=1

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs

@@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\n<launchPerspectives/>\n
+preferredTargets=org.eclipse.cdt.debug.ui.toggleCBreakpointTarget,org.eclipse.cdt.debug.ui.toggleCDynamicPrintfTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget|

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.epp.logging.aeri.ide.prefs

@@ -0,0 +1,4 @@
+eclipse.preferences.version=1
+resetSendMode=KEEP
+resetSendModeOn=0
+sendMode=NOTIFY

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.context.core.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+mylyn.attention.migrated=true

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.monitor.ui.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.mylyn.monitor.activity.tracking.enabled.checked=true

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.tasks.ui.prefs

@@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+org.eclipse.mylyn.tasks.ui.filters.nonmatching=true
+org.eclipse.mylyn.tasks.ui.filters.nonmatching.encouraged=true

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.core.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.rse.systemtype.local.systemType.defaultUserId=sstudent

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.ui.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.rse.preferences.order.connections=emw-pc0122103.Local

software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.browser.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+internalWebBrowserHistory=file\:///home/sstudent/HS-Codesign/HS-Codesign/niosii_20201119/software/hello_world_bsp/summary.html|*|file\:/home/sstudent/HS-Codesign/HS-Codesign/niosii_20201119/software/hello_world_bsp/summary.html|*|

software/.metadata/.plugins/org.eclipse.debug.core/.launches/hello_world Nios II Hardware configuration.launch

@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchConfiguration">
+<stringAttribute key="byteStreamDeviceCableName" value="USB-Blaster on localhost [3-9]"/>
+<stringAttribute key="byteStreamDeviceDeviceID" value="1"/>
+<stringAttribute key="byteStreamDeviceInstanceID" value="0"/>
+<booleanAttribute key="downloadProgram" value="true"/>
+<stringAttribute key="elfFile" value="/home/sstudent/HS-Codesign/HS-Codesign/niosii_20201119/software/hello_world/hello_world.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.altera.debug.cdi.gdb.plugin.Nios2GdbCdiDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="hello_world.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="hello_world"/>
+<stringAttribute key="processorCableName" value="USB-Blaster on localhost [3-9]"/>
+<stringAttribute key="processorDeviceIndex" value="1"/>
+<stringAttribute key="processorInstanceId" value="0"/>
+<booleanAttribute key="runProgram" value="true"/>
+</launchConfiguration>

software/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml

@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchHistory>
+<launchGroup id="org.eclipse.debug.ui.launchGroup.profilee">
+<mruHistory/>
+<favorites/>
+</launchGroup>
+<launchGroup id="org.eclipse.debug.ui.launchGroup.debug">
+<mruHistory>
+<launch memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;launchConfiguration local=&quot;true&quot; path=&quot;hello_world Nios II Hardware configuration&quot;/&gt;&#10;"/>
+</mruHistory>
+<favorites/>
+</launchGroup>
+<launchGroup id="org.eclipse.debug.ui.launchGroup.profile">
+<mruHistory/>
+<favorites/>
+</launchGroup>
+<launchGroup id="org.eclipse.ui.externaltools.launchGroup">
+<mruHistory/>
+<favorites/>
+</launchGroup>
+<launchGroup id="org.eclipse.debug.ui.launchGroup.run">
+<mruHistory>
+<launch memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;launchConfiguration local=&quot;true&quot; path=&quot;hello_world Nios II Hardware configuration&quot;/&gt;&#10;"/>
+</mruHistory>
+<favorites/>
+</launchGroup>
+</launchHistory>