VHDL implementation of transceiver, job parser and hardware accelerator modules

subDesTagesMitExtraKaese 2addef71e5 test 5 years ago
ip_repo_sources b375af81d0 changed src paths 5 years ago
sources 2addef71e5 test 5 years ago
vivado-git @ 6fdeefa9c3 25f53b2c2a added vivado-git 5 years ago
.gitignore 0d85585f08 removed old project 5 years ago
.gitmodules 2c5882b1f0 init 5 years ago
README.md 2c5882b1f0 init 5 years ago
RepoVivadoVersion 2c5882b1f0 init 5 years ago
checkin.pl b375af81d0 changed src paths 5 years ago
checkout.pl b375af81d0 changed src paths 5 years ago
condor_build.pl b375af81d0 changed src paths 5 years ago
min_area_pfile.tmp 2addef71e5 test 5 years ago
projects.list 0d85585f08 removed old project 5 years ago

README.md

modules-vhdl-ip

VHDL implementation of job parser and hardware accelerator modules