moved ip to sources

.gitignore

@@ -7,4 +7,5 @@
 /workspace.bak/
 .Xil/
 .Xiltemp/
-/run-*
+/run-*
+*.code-workspace

ip_repo_sources/myip_1.0/bd/bd.tcl

@@ -1,86 +0,0 @@
-
-proc init { cellpath otherInfo } {                                                                   
-                                                                                                             
-	set cell_handle [get_bd_cells $cellpath]                                                                 
-	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
-	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-	set full_sbusif_list [list  ]
-			                                                                                                 
-	foreach busif $all_busif {                                                                               
-		if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {                            
-			set busif_param_list [list]                                                                      
-			set busif_name [get_property NAME $busif]					                                     
-			if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {					         
-			    continue                                                                                     
-			}                                                                                                
-			foreach tparam $axi_standard_param_list {                                                        
-				lappend busif_param_list "C_${busif_name}_${tparam}"                                       
-			}                                                                                                
-			bd::mark_propagate_only $cell_handle $busif_param_list			                                 
-		}		                                                                                             
-	}                                                                                                        
-}
-
-
-proc pre_propagate {cellpath otherInfo } {                                                           
-                                                                                                             
-	set cell_handle [get_bd_cells $cellpath]                                                                 
-	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
-	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-	                                                                                                         
-	foreach busif $all_busif {	                                                                             
-		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
-			continue                                                                                         
-		}                                                                                                    
-		if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {                           
-			continue                                                                                         
-		}			                                                                                         
-		                                                                                                     
-		set busif_name [get_property NAME $busif]			                                                 
-		foreach tparam $axi_standard_param_list {		                                                     
-			set busif_param_name "C_${busif_name}_${tparam}"			                                     
-			                                                                                                 
-			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
-			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
-			                                                                                                 
-			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
-				if { $val_on_cell != "" } {                                                                  
-					set_property CONFIG.${tparam} $val_on_cell $busif                                        
-				}                                                                                            
-			}			                                                                                     
-		}		                                                                                             
-	}                                                                                                        
-}
-
-
-proc propagate {cellpath otherInfo } {                                                               
-                                                                                                             
-	set cell_handle [get_bd_cells $cellpath]                                                                 
-	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
-	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-	                                                                                                         
-	foreach busif $all_busif {                                                                               
-		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
-			continue                                                                                         
-		}                                                                                                    
-		if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {                            
-			continue                                                                                         
-		}			                                                                                         
-	                                                                                                         
-		set busif_name [get_property NAME $busif]		                                                     
-		foreach tparam $axi_standard_param_list {			                                                 
-			set busif_param_name "C_${busif_name}_${tparam}"			                                     
-                                                                                                             
-			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
-			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
-			                                                                                                 
-			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
-				#override property of bd_interface_net to bd_cell -- only for slaves.  May check for supported values..
-				if { $val_on_cell_intf_pin != "" } {                                                         
-					set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle               
-				}                                                                                            
-			}                                                                                                
-		}		                                                                                             
-	}                                                                                                        
-}
-

ip_repo_sources/myip_1.0/component.xml

@@ -1,828 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-  <spirit:vendor>user.org</spirit:vendor>
-  <spirit:library>user</spirit:library>
-  <spirit:name>myip</spirit:name>
-  <spirit:version>1.0</spirit:version>
-  <spirit:busInterfaces>
-    <spirit:busInterface>
-      <spirit:name>S00_AXI</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
-      <spirit:slave>
-        <spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
-      </spirit:slave>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWADDR</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awaddr</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWPROT</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awprot</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WDATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wdata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WSTRB</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wstrb</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>BRESP</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_bresp</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>BVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_bvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>BREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_bready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARADDR</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_araddr</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARPROT</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_arprot</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_arvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_arready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RDATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rdata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RRESP</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rresp</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>WIZ_DATA_WIDTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>WIZ_NUM_REG</spirit:name>
-          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
-          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>S00_AXI_RST</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RST</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_aresetn</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>POLARITY</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_RST.POLARITY">ACTIVE_LOW</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>S00_AXI_CLK</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>CLK</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_aclk</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_BUSIF">S00_AXI</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>ASSOCIATED_RESET</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-  </spirit:busInterfaces>
-  <spirit:memoryMaps>
-    <spirit:memoryMap>
-      <spirit:name>S00_AXI</spirit:name>
-      <spirit:addressBlock>
-        <spirit:name>S00_AXI_reg</spirit:name>
-        <spirit:baseAddress spirit:format="long" spirit:resolve="user">0</spirit:baseAddress>
-        <spirit:range spirit:format="long">4096</spirit:range>
-        <spirit:width spirit:format="long">32</spirit:width>
-        <spirit:usage>register</spirit:usage>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
-            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_BASE_PARAM">C_S00_AXI_BASEADDR</spirit:value>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
-            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_HIGH_PARAM">C_S00_AXI_HIGHADDR</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:addressBlock>
-    </spirit:memoryMap>
-  </spirit:memoryMaps>
-  <spirit:model>
-    <spirit:views>
-      <spirit:view>
-        <spirit:name>xilinx_vhdlsynthesis</spirit:name>
-        <spirit:displayName>VHDL Synthesis</spirit:displayName>
-        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
-        <spirit:language>vhdl</spirit:language>
-        <spirit:modelName>myip_v1_0</spirit:modelName>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>68e2ce51</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
-        <spirit:displayName>VHDL Simulation</spirit:displayName>
-        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
-        <spirit:language>vhdl</spirit:language>
-        <spirit:modelName>myip_v1_0</spirit:modelName>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>68e2ce51</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_softwaredriver</spirit:name>
-        <spirit:displayName>Software Driver</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:sw.driver</spirit:envIdentifier>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_softwaredriver_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>3ccb2799</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_xpgui</spirit:name>
-        <spirit:displayName>UI Layout</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>fd592ead</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>bd_tcl</spirit:name>
-        <spirit:displayName>Block Diagram</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
-        <spirit:fileSetRef>
-          <spirit:localName>bd_tcl_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>45a2f450</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-    </spirit:views>
-    <spirit:ports>
-      <spirit:port>
-        <spirit:name>s00_axi_awaddr</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH&apos;))-1)">6</spirit:left>
-            <spirit:right spirit:format="long">0</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_awprot</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left spirit:format="long">2</spirit:left>
-            <spirit:right spirit:format="long">0</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_awvalid</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_awready</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_wdata</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH&apos;))-1)">31</spirit:left>
-            <spirit:right spirit:format="long">0</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_wstrb</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH&apos;))/8)-1)">3</spirit:left>
-            <spirit:right spirit:format="long">0</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_wvalid</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
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-          <spirit:direction>in</spirit:direction>
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-              <spirit:typeName>wire</spirit:typeName>
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-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
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-          <spirit:direction>out</spirit:direction>
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-          </spirit:vector>
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-              <spirit:typeName>wire</spirit:typeName>
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-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_aclk</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_aresetn</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-    </spirit:ports>
-    <spirit:modelParameters>
-      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
-        <spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
-        <spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
-        <spirit:description>Width of S_AXI data bus</spirit:description>
-        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:order="3" spirit:rangeType="long">32</spirit:value>
-      </spirit:modelParameter>
-      <spirit:modelParameter spirit:dataType="integer">
-        <spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
-        <spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
-        <spirit:description>Width of S_AXI address bus</spirit:description>
-        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">7</spirit:value>
-      </spirit:modelParameter>
-    </spirit:modelParameters>
-  </spirit:model>
-  <spirit:choices>
-    <spirit:choice>
-      <spirit:name>choice_list_6fc15197</spirit:name>
-      <spirit:enumeration>32</spirit:enumeration>
-    </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_ce1226b1</spirit:name>
-      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
-    </spirit:choice>
-  </spirit:choices>
-  <spirit:fileSets>
-    <spirit:fileSet>
-      <spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
-      <spirit:file>
-        <spirit:name>hdl/myip_v1_0_S00_AXI.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>hdl/myip_v1_0.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_7e1348a6</spirit:userFileType>
-      </spirit:file>
-    </spirit:fileSet>
-    <spirit:fileSet>
-      <spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
-      <spirit:file>
-        <spirit:name>hdl/myip_v1_0_S00_AXI.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
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-      <spirit:file>
-        <spirit:name>hdl/myip_v1_0.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-      </spirit:file>
-    </spirit:fileSet>
-    <spirit:fileSet>
-      <spirit:name>xilinx_softwaredriver_view_fileset</spirit:name>
-      <spirit:file>
-        <spirit:name>drivers/myip_v1_0/data/myip.mdd</spirit:name>
-        <spirit:userFileType>mdd</spirit:userFileType>
-        <spirit:userFileType>driver_mdd</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>drivers/myip_v1_0/data/myip.tcl</spirit:name>
-        <spirit:fileType>tclSource</spirit:fileType>
-        <spirit:userFileType>driver_tcl</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>drivers/myip_v1_0/src/Makefile</spirit:name>
-        <spirit:userFileType>driver_src</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>drivers/myip_v1_0/src/myip.h</spirit:name>
-        <spirit:fileType>cSource</spirit:fileType>
-        <spirit:userFileType>driver_src</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>drivers/myip_v1_0/src/myip.c</spirit:name>
-        <spirit:fileType>cSource</spirit:fileType>
-        <spirit:userFileType>driver_src</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>drivers/myip_v1_0/src/myip_selftest.c</spirit:name>
-        <spirit:fileType>cSource</spirit:fileType>
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-        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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-    </spirit:fileSet>
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-      <spirit:name>bd_tcl_view_fileset</spirit:name>
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-        <spirit:fileType>tclSource</spirit:fileType>
-      </spirit:file>
-    </spirit:fileSet>
-  </spirit:fileSets>
-  <spirit:description>My new AXI IP</spirit:description>
-  <spirit:parameters>
-    <spirit:parameter>
-      <spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
-      <spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
-      <spirit:description>Width of S_AXI data bus</spirit:description>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="3">32</spirit:value>
-      <spirit:vendorExtensions>
-        <xilinx:parameterInfo>
-          <xilinx:enablement>
-            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_DATA_WIDTH">false</xilinx:isEnabled>
-          </xilinx:enablement>
-        </xilinx:parameterInfo>
-      </spirit:vendorExtensions>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
-      <spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
-      <spirit:description>Width of S_AXI address bus</spirit:description>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">7</spirit:value>
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-        <xilinx:parameterInfo>
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-          </xilinx:enablement>
-        </xilinx:parameterInfo>
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-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>C_S00_AXI_BASEADDR</spirit:name>
-      <spirit:displayName>C S00 AXI BASEADDR</spirit:displayName>
-      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
-      <spirit:vendorExtensions>
-        <xilinx:parameterInfo>
-          <xilinx:enablement>
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-          </xilinx:enablement>
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-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
-      <spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
-      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
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-          </xilinx:enablement>
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-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>Component_Name</spirit:name>
-      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">myip_v1_0</spirit:value>
-    </spirit:parameter>
-  </spirit:parameters>
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-        <xilinx:family xilinx:lifeCycle="Pre-Production">artix7</xilinx:family>
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-        <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
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-        <xilinx:tag xilinx:name="ui.data.coregen.dd@25589aa_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/myip_1.0</xilinx:tag>
-        <xilinx:tag xilinx:name="ui.data.coregen.dd@789342e6_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/myip_1.0</xilinx:tag>
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-        <xilinx:tag xilinx:name="ui.data.coregen.dd@37d27b0d_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/myip_1.0</xilinx:tag>
-      </xilinx:tags>
-    </xilinx:coreExtensions>
-    <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
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-  </spirit:vendorExtensions>
-</spirit:component>

ip_repo_sources/myip_1.0/drivers/myip_v1_0/data/myip.mdd

@@ -1,10 +0,0 @@
-
-
-OPTION psf_version = 2.1;
-
-BEGIN DRIVER myip
-	OPTION supported_peripherals = (myip);
-	OPTION copyfiles = all;
-	OPTION VERSION = 1.0;
-	OPTION NAME = myip;
-END DRIVER

ip_repo_sources/myip_1.0/drivers/myip_v1_0/data/myip.tcl

@@ -1,5 +0,0 @@
-
-
-proc generate {drv_handle} {
-	xdefine_include_file $drv_handle "xparameters.h" "myip" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
-}

ip_repo_sources/myip_1.0/drivers/myip_v1_0/src/Makefile

@@ -1,26 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-LIBSOURCES=*.c
-OUTS = *.o
-
-libs:
-	echo "Compiling myip..."
-	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
-	make clean
-
-include:
-	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
-	rm -rf ${OUTS}

ip_repo_sources/myip_1.0/drivers/myip_v1_0/src/myip.c

@@ -1,6 +0,0 @@
-
-
-/***************************** Include Files *******************************/
-#include "myip.h"
-
-/************************** Function Definitions ***************************/

ip_repo_sources/myip_1.0/drivers/myip_v1_0/src/myip.h

@@ -1,107 +0,0 @@
-
-#ifndef MYIP_H
-#define MYIP_H
-
-
-/****************** Include Files ********************/
-#include "xil_types.h"
-#include "xstatus.h"
-
-#define MYIP_S00_AXI_SLV_REG0_OFFSET 0
-#define MYIP_S00_AXI_SLV_REG1_OFFSET 4
-#define MYIP_S00_AXI_SLV_REG2_OFFSET 8
-#define MYIP_S00_AXI_SLV_REG3_OFFSET 12
-#define MYIP_S00_AXI_SLV_REG4_OFFSET 16
-#define MYIP_S00_AXI_SLV_REG5_OFFSET 20
-#define MYIP_S00_AXI_SLV_REG6_OFFSET 24
-#define MYIP_S00_AXI_SLV_REG7_OFFSET 28
-#define MYIP_S00_AXI_SLV_REG8_OFFSET 32
-#define MYIP_S00_AXI_SLV_REG9_OFFSET 36
-#define MYIP_S00_AXI_SLV_REG10_OFFSET 40
-#define MYIP_S00_AXI_SLV_REG11_OFFSET 44
-#define MYIP_S00_AXI_SLV_REG12_OFFSET 48
-#define MYIP_S00_AXI_SLV_REG13_OFFSET 52
-#define MYIP_S00_AXI_SLV_REG14_OFFSET 56
-#define MYIP_S00_AXI_SLV_REG15_OFFSET 60
-#define MYIP_S00_AXI_SLV_REG16_OFFSET 64
-#define MYIP_S00_AXI_SLV_REG17_OFFSET 68
-#define MYIP_S00_AXI_SLV_REG18_OFFSET 72
-#define MYIP_S00_AXI_SLV_REG19_OFFSET 76
-#define MYIP_S00_AXI_SLV_REG20_OFFSET 80
-#define MYIP_S00_AXI_SLV_REG21_OFFSET 84
-#define MYIP_S00_AXI_SLV_REG22_OFFSET 88
-#define MYIP_S00_AXI_SLV_REG23_OFFSET 92
-#define MYIP_S00_AXI_SLV_REG24_OFFSET 96
-#define MYIP_S00_AXI_SLV_REG25_OFFSET 100
-#define MYIP_S00_AXI_SLV_REG26_OFFSET 104
-#define MYIP_S00_AXI_SLV_REG27_OFFSET 108
-#define MYIP_S00_AXI_SLV_REG28_OFFSET 112
-#define MYIP_S00_AXI_SLV_REG29_OFFSET 116
-#define MYIP_S00_AXI_SLV_REG30_OFFSET 120
-#define MYIP_S00_AXI_SLV_REG31_OFFSET 124
-
-
-/**************************** Type Definitions *****************************/
-/**
- *
- * Write a value to a MYIP register. A 32 bit write is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is written.
- *
- * @param   BaseAddress is the base address of the MYIPdevice.
- * @param   RegOffset is the register offset from the base to write to.
- * @param   Data is the data written to the register.
- *
- * @return  None.
- *
- * @note
- * C-style signature:
- * 	void MYIP_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
- *
- */
-#define MYIP_mWriteReg(BaseAddress, RegOffset, Data) \
-  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/**
- *
- * Read a value from a MYIP register. A 32 bit read is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is read from the register. The most significant data
- * will be read as 0.
- *
- * @param   BaseAddress is the base address of the MYIP device.
- * @param   RegOffset is the register offset from the base to write to.
- *
- * @return  Data is the data from the register.
- *
- * @note
- * C-style signature:
- * 	u32 MYIP_mReadReg(u32 BaseAddress, unsigned RegOffset)
- *
- */
-#define MYIP_mReadReg(BaseAddress, RegOffset) \
-    Xil_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ****************************/
-/**
- *
- * Run a self-test on the driver/device. Note this may be a destructive test if
- * resets of the device are performed.
- *
- * If the hardware system is not built correctly, this function may never
- * return to the caller.
- *
- * @param   baseaddr_p is the base address of the MYIP instance to be worked on.
- *
- * @return
- *
- *    - XST_SUCCESS   if all self-test code passed
- *    - XST_FAILURE   if any self-test code failed
- *
- * @note    Caching must be turned off for this function to work.
- * @note    Self test may fail if data memory and device are not on the same bus.
- *
- */
-XStatus MYIP_Reg_SelfTest(void * baseaddr_p);
-
-#endif // MYIP_H

ip_repo_sources/myip_1.0/drivers/myip_v1_0/src/myip_selftest.c

@@ -1,60 +0,0 @@
-
-/***************************** Include Files *******************************/
-#include "myip.h"
-#include "xparameters.h"
-#include "stdio.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ***************************/
-#define READ_WRITE_MUL_FACTOR 0x10
-
-/************************** Function Definitions ***************************/
-/**
- *
- * Run a self-test on the driver/device. Note this may be a destructive test if
- * resets of the device are performed.
- *
- * If the hardware system is not built correctly, this function may never
- * return to the caller.
- *
- * @param   baseaddr_p is the base address of the MYIPinstance to be worked on.
- *
- * @return
- *
- *    - XST_SUCCESS   if all self-test code passed
- *    - XST_FAILURE   if any self-test code failed
- *
- * @note    Caching must be turned off for this function to work.
- * @note    Self test may fail if data memory and device are not on the same bus.
- *
- */
-XStatus MYIP_Reg_SelfTest(void * baseaddr_p)
-{
-	u32 baseaddr;
-	int write_loop_index;
-	int read_loop_index;
-	int Index;
-
-	baseaddr = (u32) baseaddr_p;
-
-	xil_printf("******************************\n\r");
-	xil_printf("* User Peripheral Self Test\n\r");
-	xil_printf("******************************\n\n\r");
-
-	/*
-	 * Write to user logic slave module register(s) and read back
-	 */
-	xil_printf("User logic slave module test...\n\r");
-
-	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
-	  MYIP_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
-	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
-	  if ( MYIP_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
-	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
-	    return XST_FAILURE;
-	  }
-
-	xil_printf("   - slave register write/read passed\n\n\r");
-
-	return XST_SUCCESS;
-}

ip_repo_sources/myip_1.0/example_designs/bfm_design/design.tcl

@@ -1,88 +0,0 @@
-proc create_ipi_design { offsetfile design_name } {
-	create_bd_design $design_name
-	open_bd_design $design_name
-
-	# Create Clock and Reset Ports
-	set ACLK [ create_bd_port -dir I -type clk ACLK ]
-	set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
-	set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
-	set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $ARESETN
-	set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
-
-	# Create instance: myip_0, and set properties
-	set myip_0 [ create_bd_cell -type ip -vlnv user.org:user:myip:1.0 myip_0]
-
-	# Create instance: master_0, and set properties
-	set master_0 [ create_bd_cell -type ip -vlnv  xilinx.com:ip:axi_vip master_0]
-	set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
-
-	# Create interface connections
-	connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins myip_0/S00_AXI]
-
-	# Create port connections
-	connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins myip_0/S00_AXI_ACLK]
-	connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins myip_0/S00_AXI_ARESETN]
-set_property target_simulator XSim [current_project]
-set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
-
-	# Auto assign address
-	assign_bd_address
-
-	# Copy all address to interface_address.vh file
-	set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
-	upvar 1 $offsetfile offset_file
-	set offset_file "${bd_path}/myip_v1_0_tb_include.svh"
-	set fp [open $offset_file "w"]
-	puts $fp "`ifndef myip_v1_0_tb_include_vh_"
-	puts $fp "`define myip_v1_0_tb_include_vh_\n"
-	puts $fp "//Configuration current bd names"
-	puts $fp "`define BD_NAME ${design_name}"
-	puts $fp "`define BD_INST_NAME ${design_name}_i"
-	puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
-	puts $fp "//Configuration address parameters"
-
-	puts $fp "`endif"
-	close $fp
-}
-
-set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:myip:1.0]]]]
-set test_bench_file ${ip_path}/example_designs/bfm_design/myip_v1_0_tb.sv
-set interface_address_vh_file ""
-
-# Set IP Repository and Update IP Catalogue 
-set repo_paths [get_property ip_repo_paths [current_fileset]] 
-if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
-	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
-	update_ip_catalog
-}
-
-set design_name ""
-set all_bd {}
-set all_bd_files [get_files *.bd -quiet]
-foreach file $all_bd_files {
-set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
-set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
-lappend all_bd $bd_name
-}
-
-for { set i 1 } { 1 } { incr i } {
-	set design_name "myip_v1_0_bfm_${i}"
-	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
-		break
-	}
-}
-
-create_ipi_design interface_address_vh_file ${design_name}
-validate_bd_design
-
-set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
-import_files -force -norecurse $wrapper_file
-
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
-import_files -fileset sim_1 -norecurse -force $test_bench_file
-remove_files -quiet -fileset sim_1 myip_v1_0_tb_include.vh
-import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
-set_property top myip_v1_0_tb [get_filesets sim_1]
-set_property top_lib {} [get_filesets sim_1]
-set_property top_file {} [get_filesets sim_1]
-launch_simulation -simset sim_1 -mode behavioral

ip_repo_sources/myip_1.0/example_designs/bfm_design/myip_v1_0_tb.sv

@@ -1,197 +0,0 @@
-
-`timescale 1ns / 1ps
-`include "myip_v1_0_tb_include.svh"
-
-import axi_vip_pkg::*;
-import myip_v1_0_bfm_1_master_0_0_pkg::*;
-
-module myip_v1_0_tb();
-
-
-xil_axi_uint                            error_cnt = 0;
-xil_axi_uint                            comparison_cnt = 0;
-axi_transaction                         wr_transaction;   
-axi_transaction                         rd_transaction;   
-axi_monitor_transaction                 mst_monitor_transaction;  
-axi_monitor_transaction                 master_moniter_transaction_queue[$];  
-xil_axi_uint                            master_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 mst_scb_transaction;  
-axi_monitor_transaction                 passthrough_monitor_transaction;  
-axi_monitor_transaction                 passthrough_master_moniter_transaction_queue[$];  
-xil_axi_uint                            passthrough_master_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 passthrough_mst_scb_transaction;  
-axi_monitor_transaction                 passthrough_slave_moniter_transaction_queue[$];  
-xil_axi_uint                            passthrough_slave_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 passthrough_slv_scb_transaction;  
-axi_monitor_transaction                 slv_monitor_transaction;  
-axi_monitor_transaction                 slave_moniter_transaction_queue[$];  
-xil_axi_uint                            slave_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 slv_scb_transaction;  
-xil_axi_uint                           mst_agent_verbosity = 0;  
-xil_axi_uint                           slv_agent_verbosity = 0;  
-xil_axi_uint                           passthrough_agent_verbosity = 0;  
-bit                                     clock;
-bit                                     reset;
-integer result_slave;  
-bit [31:0] S00_AXI_test_data[3:0]; 
- localparam LC_AXI_BURST_LENGTH = 8; 
- localparam LC_AXI_DATA_WIDTH = 32; 
-task automatic COMPARE_DATA; 
-  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected; 
-  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual; 
-  begin 
-    if (expected === 'hx || actual === 'hx) begin 
-      $display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); 
- result_slave = 0;    $stop; 
-  end 
-  if (actual != expected) begin 
-    $display("TESTBENCH ERROR! Data expected is not equal to actual.",     " expected = 0x%h",expected,     " actual   = 0x%h",actual); 
-    result_slave = 0; 
-    $stop; 
-  end 
-  else  
-    begin 
-     $display("TESTBENCH Passed! Data expected is equal to actual.", 
-              " expected = 0x%h",expected,               " actual   = 0x%h",actual); 
-    end 
-  end 
-endtask 
-integer                                 i; 
-integer                                 j;  
-xil_axi_uint                            trans_cnt_before_switch = 48;  
-xil_axi_uint                            passthrough_cmd_switch_cnt = 0;  
-event                                   passthrough_mastermode_start_event;  
-event                                   passthrough_mastermode_end_event;  
-event                                   passthrough_slavemode_end_event;  
-xil_axi_uint                            mtestID;  
-xil_axi_ulong                           mtestADDR;  
-xil_axi_len_t                           mtestBurstLength;  
-xil_axi_size_t                          mtestDataSize;   
-xil_axi_burst_t                         mtestBurstType;   
-xil_axi_lock_t                          mtestLOCK;  
-xil_axi_cache_t                         mtestCacheType = 0;  
-xil_axi_prot_t                          mtestProtectionType = 3'b000;  
-xil_axi_region_t                        mtestRegion = 4'b000;  
-xil_axi_qos_t                           mtestQOS = 4'b000;  
-xil_axi_data_beat                       dbeat;  
-xil_axi_data_beat [255:0]               mtestWUSER;   
-xil_axi_data_beat                       mtestAWUSER = 'h0;  
-xil_axi_data_beat                       mtestARUSER = 0;  
-xil_axi_data_beat [255:0]               mtestRUSER;      
-xil_axi_uint                            mtestBUSER = 0;  
-xil_axi_resp_t                          mtestBresp;  
-xil_axi_resp_t[255:0]                   mtestRresp;  
-bit [63:0]                              mtestWDataL; 
-bit [63:0]                              mtestRDataL; 
-axi_transaction                         pss_wr_transaction;   
-axi_transaction                         pss_rd_transaction;   
-axi_transaction                         reactive_transaction;   
-axi_transaction                         rd_payload_transaction;  
-axi_transaction                         wr_rand;  
-axi_transaction                         rd_rand;  
-axi_transaction                         wr_reactive;  
-axi_transaction                         rd_reactive;  
-axi_transaction                         wr_reactive2;   
-axi_transaction                         rd_reactive2;  
-axi_ready_gen                           bready_gen;  
-axi_ready_gen                           rready_gen;  
-axi_ready_gen                           awready_gen;  
-axi_ready_gen                           wready_gen;  
-axi_ready_gen                           arready_gen;  
-axi_ready_gen                           bready_gen2;  
-axi_ready_gen                           rready_gen2;  
-axi_ready_gen                           awready_gen2;  
-axi_ready_gen                           wready_gen2;  
-axi_ready_gen                           arready_gen2;  
-xil_axi_payload_byte                    data_mem[xil_axi_ulong];  
-myip_v1_0_bfm_1_master_0_0_mst_t          mst_agent_0;
-
-  `BD_WRAPPER DUT(
-      .ARESETN(reset), 
-      .ACLK(clock) 
-    ); 
-  
-initial begin
-     mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms  
-   mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE); 
-   mst_agent_0.set_agent_tag("Master VIP"); 
-   mst_agent_0.set_verbosity(mst_agent_verbosity); 
-   mst_agent_0.start_master(); 
-     $timeformat (-12, 1, " ps", 1);
-  end
-  initial begin
-    reset <= 1'b0;
-    #200ns;
-    reset <= 1'b1;
-    repeat (5) @(negedge clock); 
-  end
-  always #5 clock <= ~clock;
-  initial begin
-      S_AXI_TEST ( );
-
-      #1ns;
-      $finish;
-  end
-task automatic S_AXI_TEST;  
-begin   
-#1; 
-   $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method starts"); 
-   mtestID = 0; 
-   mtestADDR = 64'h00000000; 
-   mtestBurstLength = 0; 
-   mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
-   mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
-   mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
-   mtestCacheType = 0;  
-   mtestProtectionType = 0;  
-   mtestRegion = 0; 
-   mtestQOS = 0; 
-   result_slave = 1; 
-  mtestWDataL[31:0] = 32'h00000001; 
-  for(int i = 0; i < 4;i++) begin 
-  S00_AXI_test_data[i] <= mtestWDataL[31:0];   
-  mst_agent_0.AXI4LITE_WRITE_BURST( 
-  mtestADDR, 
-  mtestProtectionType, 
-  mtestWDataL, 
-  mtestBresp 
-  );   
-  mtestWDataL[31:0] = mtestWDataL[31:0] + 1; 
-  mtestADDR = mtestADDR + 64'h4; 
-  end 
-     $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method completes"); 
-     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method starts"); 
-     mtestID = 0; 
-     mtestADDR = 64'h00000000; 
-     mtestBurstLength = 0; 
-     mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
-     mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
-     mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
-     mtestCacheType = 0;  
-     mtestProtectionType = 0;  
-     mtestRegion = 0; 
-     mtestQOS = 0; 
- for(int i = 0; i < 4;i++) begin 
-   mst_agent_0.AXI4LITE_READ_BURST( 
-        mtestADDR, 
-        mtestProtectionType, 
-        mtestRDataL, 
-        mtestRresp 
-      ); 
-   mtestADDR = mtestADDR + 64'h4; 
-   COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL); 
- end 
-     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method completes"); 
-     $display("Sequential read transfers example similar to  AXI VIP READ_BURST method completes"); 
-     $display("---------------------------------------------------------"); 
-     $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); 
-     if ( result_slave ) begin                    
-       $display("PTGEN_TEST: PASSED!");                  
-     end    else begin                                       
-       $display("PTGEN_TEST: FAILED!");                  
-     end                                
-     $display("---------------------------------------------------------"); 
-  end 
-endtask  
-
-endmodule

ip_repo_sources/myip_1.0/example_designs/debug_hw_design/design.tcl

@@ -1,118 +0,0 @@
-
-proc create_ipi_design { offsetfile design_name } {
-
-	create_bd_design $design_name
-	open_bd_design $design_name
-
-	# Create and configure Clock/Reset
-	create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
-	create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
-
-	#Constraints will be provided manually while pin planning.
-		create_bd_port -dir I -type rst reset_rtl
-		set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
-		connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
-		connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
-		set external_reset_port reset_rtl
-		create_bd_port -dir I -type clk clock_rtl
-		connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
-		set external_clock_port clock_rtl
-	
-	#Avoid IPI DRC, make clock port synchronous to reset
-	if { $external_clock_port ne "" && $external_reset_port ne "" } {
-		set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
-	}
-
-	# Connect other sys_reset pins
-	connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
-
-	# Create instance: myip_0, and set properties
-	set myip_0 [ create_bd_cell -type ip -vlnv user.org:user:myip:1.0 myip_0 ]
-
-	# Create instance: jtag_axi_0, and set properties
-	set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
-	set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
-	connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
-	# Create instance: axi_peri_interconnect, and set properties
-	set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
-	set_property -dict [ list CONFIG.NUM_SI {1}  ] $axi_peri_interconnect
-	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
-	connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
-
-	set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
-	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
-	# Connect all clock & reset of myip_0 slave interfaces..
-	connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins myip_0/S00_AXI]
-	connect_bd_net [get_bd_pins myip_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins myip_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
-
-	# Auto assign address
-	assign_bd_address
-
-	# Copy all address to myip_v1_0_include.tcl file
-	set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
-	upvar 1 $offsetfile offset_file
-	set offset_file "${bd_path}/myip_v1_0_include.tcl"
-	set fp [open $offset_file "w"]
-	puts $fp "# Configuration address parameters"
-
-	set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_myip_0_S00_AXI_* ]]
-	puts $fp "set s00_axi_addr ${offset}"
-
-	close $fp
-}
-
-# Set IP Repository and Update IP Catalogue 
-set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:myip:1.0]]]]
-set hw_test_file ${ip_path}/example_designs/debug_hw_design/myip_v1_0_hw_test.tcl
-
-set repo_paths [get_property ip_repo_paths [current_fileset]] 
-if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
-	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
-	update_ip_catalog
-}
-
-set design_name ""
-set all_bd {}
-set all_bd_files [get_files *.bd -quiet]
-foreach file $all_bd_files {
-set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
-set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
-lappend all_bd $bd_name
-}
-
-for { set i 1 } { 1 } { incr i } {
-	set design_name "myip_v1_0_hw_${i}"
-	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
-		break
-	}
-}
-
-set intf_address_include_file ""
-create_ipi_design intf_address_include_file ${design_name}
-save_bd_design
-validate_bd_design
-
-set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
-import_files -force -norecurse $wrapper_file
-
-puts "-------------------------------------------------------------------------------------------------"
-puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
-puts "   please perform following steps to test design in targeted board."
-puts "1. Generate bitstream"
-puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
-puts "3. Download generated bitstream"
-puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
-puts "   to every interface present in the peripheral : xilinx.com:user:myip:1.0"
-puts "   : source -notrace ${hw_test_file}"
-puts "-------------------------------------------------------------------------------------------------"
-

ip_repo_sources/myip_1.0/example_designs/debug_hw_design/myip_v1_0_hw_test.tcl

@@ -1,45 +0,0 @@
-# Runtime Tcl commands to interact with - myip_v1_0
-
-# Sourcing design address info tcl
-set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
-source ${bd_path}/myip_v1_0_include.tcl
-
-# jtag axi master interface hardware name, change as per your design.
-set jtag_axi_master hw_axi_1
-set ec 0
-
-# hw test script
-# Delete all previous axis transactions
-if { [llength [get_hw_axi_txns -quiet]] } {
-	delete_hw_axi_txn [get_hw_axi_txns -quiet]
-}
-
-
-# Test all lite slaves.
-set wdata_1 abcd1234
-
-# Test: S00_AXI
-# Create a write transaction at s00_axi_addr address
-create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
-# Create a read transaction at s00_axi_addr address
-create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
-# Initiate transactions
-run_hw_axi r_s00_axi_addr
-run_hw_axi w_s00_axi_addr
-run_hw_axi r_s00_axi_addr
-set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
-# Compare read data
-if { $rdata_tmp == $wdata_1 } {
-	puts "Data comparison test pass for - S00_AXI"
-} else {
-	puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
-	inc ec
-}
-
-# Check error flag
-if { $ec == 0 } {
-	 puts "PTGEN_TEST: PASSED!" 
-} else {
-	 puts "PTGEN_TEST: FAILED!" 
-}
-

ip_repo_sources/myip_1.0/hdl/myip_v1_0.vhd

@@ -1,118 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity myip_v1_0 is
-	generic (
-		-- Users to add parameters here
-
-		-- User parameters ends
-		-- Do not modify the parameters beyond this line
-
-
-		-- Parameters of Axi Slave Bus Interface S00_AXI
-		C_S00_AXI_DATA_WIDTH	: integer	:= 32;
-		C_S00_AXI_ADDR_WIDTH	: integer	:= 7
-	);
-	port (
-		-- Users to add ports here
-
-		-- User ports ends
-		-- Do not modify the ports beyond this line
-
-
-		-- Ports of Axi Slave Bus Interface S00_AXI
-		s00_axi_aclk	: in std_logic;
-		s00_axi_aresetn	: in std_logic;
-		s00_axi_awaddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
-		s00_axi_awprot	: in std_logic_vector(2 downto 0);
-		s00_axi_awvalid	: in std_logic;
-		s00_axi_awready	: out std_logic;
-		s00_axi_wdata	: in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
-		s00_axi_wstrb	: in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
-		s00_axi_wvalid	: in std_logic;
-		s00_axi_wready	: out std_logic;
-		s00_axi_bresp	: out std_logic_vector(1 downto 0);
-		s00_axi_bvalid	: out std_logic;
-		s00_axi_bready	: in std_logic;
-		s00_axi_araddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
-		s00_axi_arprot	: in std_logic_vector(2 downto 0);
-		s00_axi_arvalid	: in std_logic;
-		s00_axi_arready	: out std_logic;
-		s00_axi_rdata	: out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
-		s00_axi_rresp	: out std_logic_vector(1 downto 0);
-		s00_axi_rvalid	: out std_logic;
-		s00_axi_rready	: in std_logic
-	);
-end myip_v1_0;
-
-architecture arch_imp of myip_v1_0 is
-
-	-- component declaration
-	component myip_v1_0_S00_AXI is
-		generic (
-		C_S_AXI_DATA_WIDTH	: integer	:= 32;
-		C_S_AXI_ADDR_WIDTH	: integer	:= 7
-		);
-		port (
-		S_AXI_ACLK	: in std_logic;
-		S_AXI_ARESETN	: in std_logic;
-		S_AXI_AWADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		S_AXI_AWPROT	: in std_logic_vector(2 downto 0);
-		S_AXI_AWVALID	: in std_logic;
-		S_AXI_AWREADY	: out std_logic;
-		S_AXI_WDATA	: in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		S_AXI_WSTRB	: in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-		S_AXI_WVALID	: in std_logic;
-		S_AXI_WREADY	: out std_logic;
-		S_AXI_BRESP	: out std_logic_vector(1 downto 0);
-		S_AXI_BVALID	: out std_logic;
-		S_AXI_BREADY	: in std_logic;
-		S_AXI_ARADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		S_AXI_ARPROT	: in std_logic_vector(2 downto 0);
-		S_AXI_ARVALID	: in std_logic;
-		S_AXI_ARREADY	: out std_logic;
-		S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		S_AXI_RRESP	: out std_logic_vector(1 downto 0);
-		S_AXI_RVALID	: out std_logic;
-		S_AXI_RREADY	: in std_logic
-		);
-	end component myip_v1_0_S00_AXI;
-
-begin
-
--- Instantiation of Axi Bus Interface S00_AXI
-myip_v1_0_S00_AXI_inst : myip_v1_0_S00_AXI
-	generic map (
-		C_S_AXI_DATA_WIDTH	=> C_S00_AXI_DATA_WIDTH,
-		C_S_AXI_ADDR_WIDTH	=> C_S00_AXI_ADDR_WIDTH
-	)
-	port map (
-		S_AXI_ACLK	=> s00_axi_aclk,
-		S_AXI_ARESETN	=> s00_axi_aresetn,
-		S_AXI_AWADDR	=> s00_axi_awaddr,
-		S_AXI_AWPROT	=> s00_axi_awprot,
-		S_AXI_AWVALID	=> s00_axi_awvalid,
-		S_AXI_AWREADY	=> s00_axi_awready,
-		S_AXI_WDATA	=> s00_axi_wdata,
-		S_AXI_WSTRB	=> s00_axi_wstrb,
-		S_AXI_WVALID	=> s00_axi_wvalid,
-		S_AXI_WREADY	=> s00_axi_wready,
-		S_AXI_BRESP	=> s00_axi_bresp,
-		S_AXI_BVALID	=> s00_axi_bvalid,
-		S_AXI_BREADY	=> s00_axi_bready,
-		S_AXI_ARADDR	=> s00_axi_araddr,
-		S_AXI_ARPROT	=> s00_axi_arprot,
-		S_AXI_ARVALID	=> s00_axi_arvalid,
-		S_AXI_ARREADY	=> s00_axi_arready,
-		S_AXI_RDATA	=> s00_axi_rdata,
-		S_AXI_RRESP	=> s00_axi_rresp,
-		S_AXI_RVALID	=> s00_axi_rvalid,
-		S_AXI_RREADY	=> s00_axi_rready
-	);
-
-	-- Add user logic here
-
-	-- User logic ends
-
-end arch_imp;

ip_repo_sources/myip_1.0/hdl/myip_v1_0_S00_AXI.vhd

@@ -1,755 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity myip_v1_0_S00_AXI is
-	generic (
-		-- Users to add parameters here
-
-		-- User parameters ends
-		-- Do not modify the parameters beyond this line
-
-		-- Width of S_AXI data bus
-		C_S_AXI_DATA_WIDTH	: integer	:= 32;
-		-- Width of S_AXI address bus
-		C_S_AXI_ADDR_WIDTH	: integer	:= 7
-	);
-	port (
-		-- Users to add ports here
-
-		-- User ports ends
-		-- Do not modify the ports beyond this line
-
-		-- Global Clock Signal
-		S_AXI_ACLK	: in std_logic;
-		-- Global Reset Signal. This Signal is Active LOW
-		S_AXI_ARESETN	: in std_logic;
-		-- Write address (issued by master, acceped by Slave)
-		S_AXI_AWADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		-- Write channel Protection type. This signal indicates the
-    		-- privilege and security level of the transaction, and whether
-    		-- the transaction is a data access or an instruction access.
-		S_AXI_AWPROT	: in std_logic_vector(2 downto 0);
-		-- Write address valid. This signal indicates that the master signaling
-    		-- valid write address and control information.
-		S_AXI_AWVALID	: in std_logic;
-		-- Write address ready. This signal indicates that the slave is ready
-    		-- to accept an address and associated control signals.
-		S_AXI_AWREADY	: out std_logic;
-		-- Write data (issued by master, acceped by Slave) 
-		S_AXI_WDATA	: in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		-- Write strobes. This signal indicates which byte lanes hold
-    		-- valid data. There is one write strobe bit for each eight
-    		-- bits of the write data bus.    
-		S_AXI_WSTRB	: in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-		-- Write valid. This signal indicates that valid write
-    		-- data and strobes are available.
-		S_AXI_WVALID	: in std_logic;
-		-- Write ready. This signal indicates that the slave
-    		-- can accept the write data.
-		S_AXI_WREADY	: out std_logic;
-		-- Write response. This signal indicates the status
-    		-- of the write transaction.
-		S_AXI_BRESP	: out std_logic_vector(1 downto 0);
-		-- Write response valid. This signal indicates that the channel
-    		-- is signaling a valid write response.
-		S_AXI_BVALID	: out std_logic;
-		-- Response ready. This signal indicates that the master
-    		-- can accept a write response.
-		S_AXI_BREADY	: in std_logic;
-		-- Read address (issued by master, acceped by Slave)
-		S_AXI_ARADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		-- Protection type. This signal indicates the privilege
-    		-- and security level of the transaction, and whether the
-    		-- transaction is a data access or an instruction access.
-		S_AXI_ARPROT	: in std_logic_vector(2 downto 0);
-		-- Read address valid. This signal indicates that the channel
-    		-- is signaling valid read address and control information.
-		S_AXI_ARVALID	: in std_logic;
-		-- Read address ready. This signal indicates that the slave is
-    		-- ready to accept an address and associated control signals.
-		S_AXI_ARREADY	: out std_logic;
-		-- Read data (issued by slave)
-		S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		-- Read response. This signal indicates the status of the
-    		-- read transfer.
-		S_AXI_RRESP	: out std_logic_vector(1 downto 0);
-		-- Read valid. This signal indicates that the channel is
-    		-- signaling the required read data.
-		S_AXI_RVALID	: out std_logic;
-		-- Read ready. This signal indicates that the master can
-    		-- accept the read data and response information.
-		S_AXI_RREADY	: in std_logic
-	);
-end myip_v1_0_S00_AXI;
-
-architecture arch_imp of myip_v1_0_S00_AXI is
-
-	-- AXI4LITE signals
-	signal axi_awaddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-	signal axi_awready	: std_logic;
-	signal axi_wready	: std_logic;
-	signal axi_bresp	: std_logic_vector(1 downto 0);
-	signal axi_bvalid	: std_logic;
-	signal axi_araddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-	signal axi_arready	: std_logic;
-	signal axi_rdata	: std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal axi_rresp	: std_logic_vector(1 downto 0);
-	signal axi_rvalid	: std_logic;
-
-	-- Example-specific design signals
-	-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-	-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-	-- ADDR_LSB = 2 for 32 bits (n downto 2)
-	-- ADDR_LSB = 3 for 64 bits (n downto 3)
-	constant ADDR_LSB  : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
-	constant OPT_MEM_ADDR_BITS : integer := 4;
-	------------------------------------------------
-	---- Signals for user logic register space example
-	--------------------------------------------------
-	---- Number of Slave Registers 32
-	signal slv_reg0	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg1	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg2	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg3	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg4	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg5	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg6	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg7	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg8	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg9	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg10	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg11	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg12	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg13	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg14	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg15	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg16	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg17	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg18	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg19	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg20	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg21	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg22	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg23	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg24	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg25	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg26	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg27	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg28	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg29	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg30	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg31	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg_rden	: std_logic;
-	signal slv_reg_wren	: std_logic;
-	signal reg_data_out	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal byte_index	: integer;
-	signal aw_en	: std_logic;
-
-begin
-	-- I/O Connections assignments
-
-	S_AXI_AWREADY	<= axi_awready;
-	S_AXI_WREADY	<= axi_wready;
-	S_AXI_BRESP	<= axi_bresp;
-	S_AXI_BVALID	<= axi_bvalid;
-	S_AXI_ARREADY	<= axi_arready;
-	S_AXI_RDATA	<= axi_rdata;
-	S_AXI_RRESP	<= axi_rresp;
-	S_AXI_RVALID	<= axi_rvalid;
-	-- Implement axi_awready generation
-	-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-	-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-	-- de-asserted when reset is low.
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_awready <= '0';
-	      aw_en <= '1';
-	    else
-	      if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-	        -- slave is ready to accept write address when
-	        -- there is a valid write address and write data
-	        -- on the write address and data bus. This design 
-	        -- expects no outstanding transactions. 
-	           axi_awready <= '1';
-	           aw_en <= '0';
-	        elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
-	           aw_en <= '1';
-	           axi_awready <= '0';
-	      else
-	        axi_awready <= '0';
-	      end if;
-	    end if;
-	  end if;
-	end process;
-
-	-- Implement axi_awaddr latching
-	-- This process is used to latch the address when both 
-	-- S_AXI_AWVALID and S_AXI_WVALID are valid. 
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_awaddr <= (others => '0');
-	    else
-	      if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-	        -- Write Address latching
-	        axi_awaddr <= S_AXI_AWADDR;
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement axi_wready generation
-	-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-	-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
-	-- de-asserted when reset is low. 
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_wready <= '0';
-	    else
-	      if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
-	          -- slave is ready to accept write data when 
-	          -- there is a valid write address and write data
-	          -- on the write address and data bus. This design 
-	          -- expects no outstanding transactions.           
-	          axi_wready <= '1';
-	      else
-	        axi_wready <= '0';
-	      end if;
-	    end if;
-	  end if;
-	end process; 
-
-	-- Implement memory mapped register select and write logic generation
-	-- The write data is accepted and written to memory mapped registers when
-	-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-	-- select byte enables of slave registers while writing.
-	-- These registers are cleared when reset (active low) is applied.
-	-- Slave register write enable is asserted when valid address and data are available
-	-- and the slave is ready to accept the write address and write data.
-	slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
-
-	process (S_AXI_ACLK)
-	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); 
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      slv_reg0 <= (others => '0');
-	      slv_reg1 <= (others => '0');
-	      slv_reg2 <= (others => '0');
-	      slv_reg3 <= (others => '0');
-	      slv_reg4 <= (others => '0');
-	      slv_reg5 <= (others => '0');
-	      slv_reg6 <= (others => '0');
-	      slv_reg7 <= (others => '0');
-	      slv_reg8 <= (others => '0');
-	      slv_reg9 <= (others => '0');
-	      slv_reg10 <= (others => '0');
-	      slv_reg11 <= (others => '0');
-	      slv_reg12 <= (others => '0');
-	      slv_reg13 <= (others => '0');
-	      slv_reg14 <= (others => '0');
-	      slv_reg15 <= (others => '0');
-	      slv_reg16 <= (others => '0');
-	      slv_reg17 <= (others => '0');
-	      slv_reg18 <= (others => '0');
-	      slv_reg19 <= (others => '0');
-	      slv_reg20 <= (others => '0');
-	      slv_reg21 <= (others => '0');
-	      slv_reg22 <= (others => '0');
-	      slv_reg23 <= (others => '0');
-	      slv_reg24 <= (others => '0');
-	      slv_reg25 <= (others => '0');
-	      slv_reg26 <= (others => '0');
-	      slv_reg27 <= (others => '0');
-	      slv_reg28 <= (others => '0');
-	      slv_reg29 <= (others => '0');
-	      slv_reg30 <= (others => '0');
-	      slv_reg31 <= (others => '0');
-	    else
-	      loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
-	      if (slv_reg_wren = '1') then
-	        case loc_addr is
-	          when b"00000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 0
-	                slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 1
-	                slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 2
-	                slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 3
-	                slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 4
-	                slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 5
-	                slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 6
-	                slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 7
-	                slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 8
-	                slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 9
-	                slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 10
-	                slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 11
-	                slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 12
-	                slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 13
-	                slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 14
-	                slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 15
-	                slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 16
-	                slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 17
-	                slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 18
-	                slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 19
-	                slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 20
-	                slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 21
-	                slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 22
-	                slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 23
-	                slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 24
-	                slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 25
-	                slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 26
-	                slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 27
-	                slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 28
-	                slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 29
-	                slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 30
-	                slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 31
-	                slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when others =>
-	            slv_reg0 <= slv_reg0;
-	            slv_reg1 <= slv_reg1;
-	            slv_reg2 <= slv_reg2;
-	            slv_reg3 <= slv_reg3;
-	            slv_reg4 <= slv_reg4;
-	            slv_reg5 <= slv_reg5;
-	            slv_reg6 <= slv_reg6;
-	            slv_reg7 <= slv_reg7;
-	            slv_reg8 <= slv_reg8;
-	            slv_reg9 <= slv_reg9;
-	            slv_reg10 <= slv_reg10;
-	            slv_reg11 <= slv_reg11;
-	            slv_reg12 <= slv_reg12;
-	            slv_reg13 <= slv_reg13;
-	            slv_reg14 <= slv_reg14;
-	            slv_reg15 <= slv_reg15;
-	            slv_reg16 <= slv_reg16;
-	            slv_reg17 <= slv_reg17;
-	            slv_reg18 <= slv_reg18;
-	            slv_reg19 <= slv_reg19;
-	            slv_reg20 <= slv_reg20;
-	            slv_reg21 <= slv_reg21;
-	            slv_reg22 <= slv_reg22;
-	            slv_reg23 <= slv_reg23;
-	            slv_reg24 <= slv_reg24;
-	            slv_reg25 <= slv_reg25;
-	            slv_reg26 <= slv_reg26;
-	            slv_reg27 <= slv_reg27;
-	            slv_reg28 <= slv_reg28;
-	            slv_reg29 <= slv_reg29;
-	            slv_reg30 <= slv_reg30;
-	            slv_reg31 <= slv_reg31;
-	        end case;
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement write response logic generation
-	-- The write response and response valid signals are asserted by the slave 
-	-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
-	-- This marks the acceptance of address and indicates the status of 
-	-- write transaction.
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_bvalid  <= '0';
-	      axi_bresp   <= "00"; --need to work more on the responses
-	    else
-	      if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0'  ) then
-	        axi_bvalid <= '1';
-	        axi_bresp  <= "00"; 
-	      elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then   --check if bready is asserted while bvalid is high)
-	        axi_bvalid <= '0';                                 -- (there is a possibility that bready is always asserted high)
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement axi_arready generation
-	-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-	-- S_AXI_ARVALID is asserted. axi_awready is 
-	-- de-asserted when reset (active low) is asserted. 
-	-- The read address is also latched when S_AXI_ARVALID is 
-	-- asserted. axi_araddr is reset to zero on reset assertion.
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_arready <= '0';
-	      axi_araddr  <= (others => '1');
-	    else
-	      if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-	        -- indicates that the slave has acceped the valid read address
-	        axi_arready <= '1';
-	        -- Read Address latching 
-	        axi_araddr  <= S_AXI_ARADDR;           
-	      else
-	        axi_arready <= '0';
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement axi_arvalid generation
-	-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
-	-- S_AXI_ARVALID and axi_arready are asserted. The slave registers 
-	-- data are available on the axi_rdata bus at this instance. The 
-	-- assertion of axi_rvalid marks the validity of read data on the 
-	-- bus and axi_rresp indicates the status of read transaction.axi_rvalid 
-	-- is deasserted on reset (active low). axi_rresp and axi_rdata are 
-	-- cleared to zero on reset (active low).  
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then
-	    if S_AXI_ARESETN = '0' then
-	      axi_rvalid <= '0';
-	      axi_rresp  <= "00";
-	    else
-	      if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-	        -- Valid read data is available at the read data bus
-	        axi_rvalid <= '1';
-	        axi_rresp  <= "00"; -- 'OKAY' response
-	      elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-	        -- Read data is accepted by the master
-	        axi_rvalid <= '0';
-	      end if;            
-	    end if;
-	  end if;
-	end process;
-
-	-- Implement memory mapped register select and read logic generation
-	-- Slave register read enable is asserted when valid address is available
-	-- and the slave is ready to accept the read address.
-	slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
-
-	process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
-	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
-	begin
-	    -- Address decoding for reading registers
-	    loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
-	    case loc_addr is
-	      when b"00000" =>
-	        reg_data_out <= slv_reg0;
-	      when b"00001" =>
-	        reg_data_out <= slv_reg1;
-	      when b"00010" =>
-	        reg_data_out <= slv_reg2;
-	      when b"00011" =>
-	        reg_data_out <= slv_reg3;
-	      when b"00100" =>
-	        reg_data_out <= slv_reg4;
-	      when b"00101" =>
-	        reg_data_out <= slv_reg5;
-	      when b"00110" =>
-	        reg_data_out <= slv_reg6;
-	      when b"00111" =>
-	        reg_data_out <= slv_reg7;
-	      when b"01000" =>
-	        reg_data_out <= slv_reg8;
-	      when b"01001" =>
-	        reg_data_out <= slv_reg9;
-	      when b"01010" =>
-	        reg_data_out <= slv_reg10;
-	      when b"01011" =>
-	        reg_data_out <= slv_reg11;
-	      when b"01100" =>
-	        reg_data_out <= slv_reg12;
-	      when b"01101" =>
-	        reg_data_out <= slv_reg13;
-	      when b"01110" =>
-	        reg_data_out <= slv_reg14;
-	      when b"01111" =>
-	        reg_data_out <= slv_reg15;
-	      when b"10000" =>
-	        reg_data_out <= slv_reg16;
-	      when b"10001" =>
-	        reg_data_out <= slv_reg17;
-	      when b"10010" =>
-	        reg_data_out <= slv_reg18;
-	      when b"10011" =>
-	        reg_data_out <= slv_reg19;
-	      when b"10100" =>
-	        reg_data_out <= slv_reg20;
-	      when b"10101" =>
-	        reg_data_out <= slv_reg21;
-	      when b"10110" =>
-	        reg_data_out <= slv_reg22;
-	      when b"10111" =>
-	        reg_data_out <= slv_reg23;
-	      when b"11000" =>
-	        reg_data_out <= slv_reg24;
-	      when b"11001" =>
-	        reg_data_out <= slv_reg25;
-	      when b"11010" =>
-	        reg_data_out <= slv_reg26;
-	      when b"11011" =>
-	        reg_data_out <= slv_reg27;
-	      when b"11100" =>
-	        reg_data_out <= slv_reg28;
-	      when b"11101" =>
-	        reg_data_out <= slv_reg29;
-	      when b"11110" =>
-	        reg_data_out <= slv_reg30;
-	      when b"11111" =>
-	        reg_data_out <= slv_reg31;
-	      when others =>
-	        reg_data_out  <= (others => '0');
-	    end case;
-	end process; 
-
-	-- Output register or memory read data
-	process( S_AXI_ACLK ) is
-	begin
-	  if (rising_edge (S_AXI_ACLK)) then
-	    if ( S_AXI_ARESETN = '0' ) then
-	      axi_rdata  <= (others => '0');
-	    else
-	      if (slv_reg_rden = '1') then
-	        -- When there is a valid read address (S_AXI_ARVALID) with 
-	        -- acceptance of read address by the slave (axi_arready), 
-	        -- output the read dada 
-	        -- Read address mux
-	          axi_rdata <= reg_data_out;     -- register read data
-	      end if;   
-	    end if;
-	  end if;
-	end process;
-
-
-	-- Add user logic here
-
-	-- User logic ends
-
-end arch_imp;

ip_repo_sources/myip_1.0/xgui/myip_v1_0.tcl

@@ -1,62 +0,0 @@
-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
-  ipgui::add_param $IPINST -name "Component_Name"
-  #Adding Page
-  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
-  set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox]
-  set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH}
-  set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}]
-  set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH}
-  ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
-  ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
-
-
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
-	# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
-	# Procedure called to validate C_S00_AXI_DATA_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
-	# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
-	# Procedure called to validate C_S00_AXI_ADDR_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
-	# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
-	# Procedure called to validate C_S00_AXI_BASEADDR
-	return true
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
-	# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
-	# Procedure called to validate C_S00_AXI_HIGHADDR
-	return true
-}
-
-
-proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
-	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
-	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
-}
-

ip_repo_sources/neuron_1.0/bd/bd.tcl

@@ -1,86 +0,0 @@
-
-proc init { cellpath otherInfo } {                                                                   
-                                                                                                             
-	set cell_handle [get_bd_cells $cellpath]                                                                 
-	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
-	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-	set full_sbusif_list [list  ]
-			                                                                                                 
-	foreach busif $all_busif {                                                                               
-		if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {                            
-			set busif_param_list [list]                                                                      
-			set busif_name [get_property NAME $busif]					                                     
-			if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {					         
-			    continue                                                                                     
-			}                                                                                                
-			foreach tparam $axi_standard_param_list {                                                        
-				lappend busif_param_list "C_${busif_name}_${tparam}"                                       
-			}                                                                                                
-			bd::mark_propagate_only $cell_handle $busif_param_list			                                 
-		}		                                                                                             
-	}                                                                                                        
-}
-
-
-proc pre_propagate {cellpath otherInfo } {                                                           
-                                                                                                             
-	set cell_handle [get_bd_cells $cellpath]                                                                 
-	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
-	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-	                                                                                                         
-	foreach busif $all_busif {	                                                                             
-		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
-			continue                                                                                         
-		}                                                                                                    
-		if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {                           
-			continue                                                                                         
-		}			                                                                                         
-		                                                                                                     
-		set busif_name [get_property NAME $busif]			                                                 
-		foreach tparam $axi_standard_param_list {		                                                     
-			set busif_param_name "C_${busif_name}_${tparam}"			                                     
-			                                                                                                 
-			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
-			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
-			                                                                                                 
-			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
-				if { $val_on_cell != "" } {                                                                  
-					set_property CONFIG.${tparam} $val_on_cell $busif                                        
-				}                                                                                            
-			}			                                                                                     
-		}		                                                                                             
-	}                                                                                                        
-}
-
-
-proc propagate {cellpath otherInfo } {                                                               
-                                                                                                             
-	set cell_handle [get_bd_cells $cellpath]                                                                 
-	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
-	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-	                                                                                                         
-	foreach busif $all_busif {                                                                               
-		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
-			continue                                                                                         
-		}                                                                                                    
-		if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {                            
-			continue                                                                                         
-		}			                                                                                         
-	                                                                                                         
-		set busif_name [get_property NAME $busif]		                                                     
-		foreach tparam $axi_standard_param_list {			                                                 
-			set busif_param_name "C_${busif_name}_${tparam}"			                                     
-                                                                                                             
-			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
-			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
-			                                                                                                 
-			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
-				#override property of bd_interface_net to bd_cell -- only for slaves.  May check for supported values..
-				if { $val_on_cell_intf_pin != "" } {                                                         
-					set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle               
-				}                                                                                            
-			}                                                                                                
-		}		                                                                                             
-	}                                                                                                        
-}
-

ip_repo_sources/neuron_1.0/component.xml

@@ -1,945 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-  <spirit:vendor>user.org</spirit:vendor>
-  <spirit:library>user</spirit:library>
-  <spirit:name>neuron</spirit:name>
-  <spirit:version>1.0</spirit:version>
-  <spirit:busInterfaces>
-    <spirit:busInterface>
-      <spirit:name>S00_AXI</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
-      <spirit:slave>
-        <spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
-      </spirit:slave>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWADDR</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awaddr</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWPROT</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awprot</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WDATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wdata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WSTRB</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wstrb</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>BRESP</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_bresp</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>BVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_bvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>BREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_bready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARADDR</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_araddr</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARPROT</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_arprot</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_arvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_arready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RDATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rdata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RRESP</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rresp</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>WIZ_DATA_WIDTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>WIZ_NUM_REG</spirit:name>
-          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
-          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>S00_AXI_RST</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RST</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_aresetn</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>POLARITY</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_RST.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>S00_AXI_CLK</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>CLK</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_aclk</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_BUSIF">S00_AXI</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>ASSOCIATED_RESET</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-  </spirit:busInterfaces>
-  <spirit:memoryMaps>
-    <spirit:memoryMap>
-      <spirit:name>S00_AXI</spirit:name>
-      <spirit:addressBlock>
-        <spirit:name>S00_AXI_reg</spirit:name>
-        <spirit:baseAddress spirit:format="long" spirit:resolve="user">0</spirit:baseAddress>
-        <spirit:range spirit:format="long">4096</spirit:range>
-        <spirit:width spirit:format="long">32</spirit:width>
-        <spirit:usage>register</spirit:usage>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
-            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_BASE_PARAM">C_S00_AXI_BASEADDR</spirit:value>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
-            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_HIGH_PARAM">C_S00_AXI_HIGHADDR</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:addressBlock>
-    </spirit:memoryMap>
-  </spirit:memoryMaps>
-  <spirit:model>
-    <spirit:views>
-      <spirit:view>
-        <spirit:name>xilinx_vhdlsynthesis</spirit:name>
-        <spirit:displayName>VHDL Synthesis</spirit:displayName>
-        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
-        <spirit:language>vhdl</spirit:language>
-        <spirit:modelName>neuron_v1_0</spirit:modelName>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>11a4ae67</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
-        <spirit:displayName>VHDL Simulation</spirit:displayName>
-        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
-        <spirit:language>vhdl</spirit:language>
-        <spirit:modelName>neuron_v1_0</spirit:modelName>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>11a4ae67</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_softwaredriver</spirit:name>
-        <spirit:displayName>Software Driver</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:sw.driver</spirit:envIdentifier>
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-          </xilinx:enablement>
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-      </spirit:vendorExtensions>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
-      <spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
-      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
-      <spirit:vendorExtensions>
-        <xilinx:parameterInfo>
-          <xilinx:enablement>
-            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_HIGHADDR">false</xilinx:isEnabled>
-          </xilinx:enablement>
-        </xilinx:parameterInfo>
-      </spirit:vendorExtensions>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>Component_Name</spirit:name>
-      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">neuron_v1_0</spirit:value>
-    </spirit:parameter>
-  </spirit:parameters>
-  <spirit:vendorExtensions>
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-        <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
-      </xilinx:taxonomies>
-      <xilinx:displayName>neuron_v1.0</xilinx:displayName>
-      <xilinx:coreRevision>6</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2019-05-29T08:46:29Z</xilinx:coreCreationDateTime>
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-      </xilinx:tags>
-    </xilinx:coreExtensions>
-    <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="0312d308"/>
-      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ed1368d5"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0c1d33f5"/>
-      <xilinx:checksum xilinx:scope="ports" xilinx:value="48e360dd"/>
-      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="a0a6f17f"/>
-      <xilinx:checksum xilinx:scope="parameters" xilinx:value="ae442535"/>
-    </xilinx:packagingInfo>
-  </spirit:vendorExtensions>
-</spirit:component>

ip_repo_sources/neuron_1.0/drivers/neuron_v1_0/data/neuron.mdd

@@ -1,10 +0,0 @@
-
-
-OPTION psf_version = 2.1;
-
-BEGIN DRIVER neuron
-	OPTION supported_peripherals = (neuron);
-	OPTION copyfiles = all;
-	OPTION VERSION = 1.0;
-	OPTION NAME = neuron;
-END DRIVER

ip_repo_sources/neuron_1.0/drivers/neuron_v1_0/data/neuron.tcl

@@ -1,5 +0,0 @@
-
-
-proc generate {drv_handle} {
-	xdefine_include_file $drv_handle "xparameters.h" "neuron" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
-}

ip_repo_sources/neuron_1.0/drivers/neuron_v1_0/src/Makefile

@@ -1,26 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-LIBSOURCES=*.c
-OUTS = *.o
-
-libs:
-	echo "Compiling neuron..."
-	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
-	make clean
-
-include:
-	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
-	rm -rf ${OUTS}

ip_repo_sources/neuron_1.0/drivers/neuron_v1_0/src/neuron.c

@@ -1,6 +0,0 @@
-
-
-/***************************** Include Files *******************************/
-#include "neuron.h"
-
-/************************** Function Definitions ***************************/

ip_repo_sources/neuron_1.0/drivers/neuron_v1_0/src/neuron.h

@@ -1,107 +0,0 @@
-
-#ifndef NEURON_H
-#define NEURON_H
-
-
-/****************** Include Files ********************/
-#include "xil_types.h"
-#include "xstatus.h"
-
-#define NEURON_S00_AXI_SLV_REG0_OFFSET 0
-#define NEURON_S00_AXI_SLV_REG1_OFFSET 4
-#define NEURON_S00_AXI_SLV_REG2_OFFSET 8
-#define NEURON_S00_AXI_SLV_REG3_OFFSET 12
-#define NEURON_S00_AXI_SLV_REG4_OFFSET 16
-#define NEURON_S00_AXI_SLV_REG5_OFFSET 20
-#define NEURON_S00_AXI_SLV_REG6_OFFSET 24
-#define NEURON_S00_AXI_SLV_REG7_OFFSET 28
-#define NEURON_S00_AXI_SLV_REG8_OFFSET 32
-#define NEURON_S00_AXI_SLV_REG9_OFFSET 36
-#define NEURON_S00_AXI_SLV_REG10_OFFSET 40
-#define NEURON_S00_AXI_SLV_REG11_OFFSET 44
-#define NEURON_S00_AXI_SLV_REG12_OFFSET 48
-#define NEURON_S00_AXI_SLV_REG13_OFFSET 52
-#define NEURON_S00_AXI_SLV_REG14_OFFSET 56
-#define NEURON_S00_AXI_SLV_REG15_OFFSET 60
-#define NEURON_S00_AXI_SLV_REG16_OFFSET 64
-#define NEURON_S00_AXI_SLV_REG17_OFFSET 68
-#define NEURON_S00_AXI_SLV_REG18_OFFSET 72
-#define NEURON_S00_AXI_SLV_REG19_OFFSET 76
-#define NEURON_S00_AXI_SLV_REG20_OFFSET 80
-#define NEURON_S00_AXI_SLV_REG21_OFFSET 84
-#define NEURON_S00_AXI_SLV_REG22_OFFSET 88
-#define NEURON_S00_AXI_SLV_REG23_OFFSET 92
-#define NEURON_S00_AXI_SLV_REG24_OFFSET 96
-#define NEURON_S00_AXI_SLV_REG25_OFFSET 100
-#define NEURON_S00_AXI_SLV_REG26_OFFSET 104
-#define NEURON_S00_AXI_SLV_REG27_OFFSET 108
-#define NEURON_S00_AXI_SLV_REG28_OFFSET 112
-#define NEURON_S00_AXI_SLV_REG29_OFFSET 116
-#define NEURON_S00_AXI_SLV_REG30_OFFSET 120
-#define NEURON_S00_AXI_SLV_REG31_OFFSET 124
-
-
-/**************************** Type Definitions *****************************/
-/**
- *
- * Write a value to a NEURON register. A 32 bit write is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is written.
- *
- * @param   BaseAddress is the base address of the NEURONdevice.
- * @param   RegOffset is the register offset from the base to write to.
- * @param   Data is the data written to the register.
- *
- * @return  None.
- *
- * @note
- * C-style signature:
- * 	void NEURON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
- *
- */
-#define NEURON_mWriteReg(BaseAddress, RegOffset, Data) \
-  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/**
- *
- * Read a value from a NEURON register. A 32 bit read is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is read from the register. The most significant data
- * will be read as 0.
- *
- * @param   BaseAddress is the base address of the NEURON device.
- * @param   RegOffset is the register offset from the base to write to.
- *
- * @return  Data is the data from the register.
- *
- * @note
- * C-style signature:
- * 	u32 NEURON_mReadReg(u32 BaseAddress, unsigned RegOffset)
- *
- */
-#define NEURON_mReadReg(BaseAddress, RegOffset) \
-    Xil_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ****************************/
-/**
- *
- * Run a self-test on the driver/device. Note this may be a destructive test if
- * resets of the device are performed.
- *
- * If the hardware system is not built correctly, this function may never
- * return to the caller.
- *
- * @param   baseaddr_p is the base address of the NEURON instance to be worked on.
- *
- * @return
- *
- *    - XST_SUCCESS   if all self-test code passed
- *    - XST_FAILURE   if any self-test code failed
- *
- * @note    Caching must be turned off for this function to work.
- * @note    Self test may fail if data memory and device are not on the same bus.
- *
- */
-XStatus NEURON_Reg_SelfTest(void * baseaddr_p);
-
-#endif // NEURON_H

ip_repo_sources/neuron_1.0/drivers/neuron_v1_0/src/neuron_selftest.c

@@ -1,60 +0,0 @@
-
-/***************************** Include Files *******************************/
-#include "neuron.h"
-#include "xparameters.h"
-#include "stdio.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ***************************/
-#define READ_WRITE_MUL_FACTOR 0x10
-
-/************************** Function Definitions ***************************/
-/**
- *
- * Run a self-test on the driver/device. Note this may be a destructive test if
- * resets of the device are performed.
- *
- * If the hardware system is not built correctly, this function may never
- * return to the caller.
- *
- * @param   baseaddr_p is the base address of the NEURONinstance to be worked on.
- *
- * @return
- *
- *    - XST_SUCCESS   if all self-test code passed
- *    - XST_FAILURE   if any self-test code failed
- *
- * @note    Caching must be turned off for this function to work.
- * @note    Self test may fail if data memory and device are not on the same bus.
- *
- */
-XStatus NEURON_Reg_SelfTest(void * baseaddr_p)
-{
-	u32 baseaddr;
-	int write_loop_index;
-	int read_loop_index;
-	int Index;
-
-	baseaddr = (u32) baseaddr_p;
-
-	xil_printf("******************************\n\r");
-	xil_printf("* User Peripheral Self Test\n\r");
-	xil_printf("******************************\n\n\r");
-
-	/*
-	 * Write to user logic slave module register(s) and read back
-	 */
-	xil_printf("User logic slave module test...\n\r");
-
-	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
-	  NEURON_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
-	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
-	  if ( NEURON_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
-	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
-	    return XST_FAILURE;
-	  }
-
-	xil_printf("   - slave register write/read passed\n\n\r");
-
-	return XST_SUCCESS;
-}

ip_repo_sources/neuron_1.0/example_designs/bfm_design/design.tcl

@@ -1,88 +0,0 @@
-proc create_ipi_design { offsetfile design_name } {
-	create_bd_design $design_name
-	open_bd_design $design_name
-
-	# Create Clock and Reset Ports
-	set ACLK [ create_bd_port -dir I -type clk ACLK ]
-	set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
-	set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
-	set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $ARESETN
-	set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
-
-	# Create instance: neuron_0, and set properties
-	set neuron_0 [ create_bd_cell -type ip -vlnv user.org:user:neuron:1.0 neuron_0]
-
-	# Create instance: master_0, and set properties
-	set master_0 [ create_bd_cell -type ip -vlnv  xilinx.com:ip:axi_vip master_0]
-	set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
-
-	# Create interface connections
-	connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins neuron_0/S00_AXI]
-
-	# Create port connections
-	connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins neuron_0/S00_AXI_ACLK]
-	connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins neuron_0/S00_AXI_ARESETN]
-set_property target_simulator XSim [current_project]
-set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
-
-	# Auto assign address
-	assign_bd_address
-
-	# Copy all address to interface_address.vh file
-	set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
-	upvar 1 $offsetfile offset_file
-	set offset_file "${bd_path}/neuron_v1_0_tb_include.svh"
-	set fp [open $offset_file "w"]
-	puts $fp "`ifndef neuron_v1_0_tb_include_vh_"
-	puts $fp "`define neuron_v1_0_tb_include_vh_\n"
-	puts $fp "//Configuration current bd names"
-	puts $fp "`define BD_NAME ${design_name}"
-	puts $fp "`define BD_INST_NAME ${design_name}_i"
-	puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
-	puts $fp "//Configuration address parameters"
-
-	puts $fp "`endif"
-	close $fp
-}
-
-set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:neuron:1.0]]]]
-set test_bench_file ${ip_path}/example_designs/bfm_design/neuron_v1_0_tb.sv
-set interface_address_vh_file ""
-
-# Set IP Repository and Update IP Catalogue 
-set repo_paths [get_property ip_repo_paths [current_fileset]] 
-if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
-	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
-	update_ip_catalog
-}
-
-set design_name ""
-set all_bd {}
-set all_bd_files [get_files *.bd -quiet]
-foreach file $all_bd_files {
-set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
-set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
-lappend all_bd $bd_name
-}
-
-for { set i 1 } { 1 } { incr i } {
-	set design_name "neuron_v1_0_bfm_${i}"
-	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
-		break
-	}
-}
-
-create_ipi_design interface_address_vh_file ${design_name}
-validate_bd_design
-
-set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
-import_files -force -norecurse $wrapper_file
-
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
-import_files -fileset sim_1 -norecurse -force $test_bench_file
-remove_files -quiet -fileset sim_1 neuron_v1_0_tb_include.vh
-import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
-set_property top neuron_v1_0_tb [get_filesets sim_1]
-set_property top_lib {} [get_filesets sim_1]
-set_property top_file {} [get_filesets sim_1]
-launch_simulation -simset sim_1 -mode behavioral

ip_repo_sources/neuron_1.0/example_designs/bfm_design/neuron_v1_0_tb.sv

@@ -1,197 +0,0 @@
-
-`timescale 1ns / 1ps
-`include "neuron_v1_0_tb_include.svh"
-
-import axi_vip_pkg::*;
-import neuron_v1_0_bfm_1_master_0_0_pkg::*;
-
-module neuron_v1_0_tb();
-
-
-xil_axi_uint                            error_cnt = 0;
-xil_axi_uint                            comparison_cnt = 0;
-axi_transaction                         wr_transaction;   
-axi_transaction                         rd_transaction;   
-axi_monitor_transaction                 mst_monitor_transaction;  
-axi_monitor_transaction                 master_moniter_transaction_queue[$];  
-xil_axi_uint                            master_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 mst_scb_transaction;  
-axi_monitor_transaction                 passthrough_monitor_transaction;  
-axi_monitor_transaction                 passthrough_master_moniter_transaction_queue[$];  
-xil_axi_uint                            passthrough_master_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 passthrough_mst_scb_transaction;  
-axi_monitor_transaction                 passthrough_slave_moniter_transaction_queue[$];  
-xil_axi_uint                            passthrough_slave_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 passthrough_slv_scb_transaction;  
-axi_monitor_transaction                 slv_monitor_transaction;  
-axi_monitor_transaction                 slave_moniter_transaction_queue[$];  
-xil_axi_uint                            slave_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 slv_scb_transaction;  
-xil_axi_uint                           mst_agent_verbosity = 0;  
-xil_axi_uint                           slv_agent_verbosity = 0;  
-xil_axi_uint                           passthrough_agent_verbosity = 0;  
-bit                                     clock;
-bit                                     reset;
-integer result_slave;  
-bit [31:0] S00_AXI_test_data[3:0]; 
- localparam LC_AXI_BURST_LENGTH = 8; 
- localparam LC_AXI_DATA_WIDTH = 32; 
-task automatic COMPARE_DATA; 
-  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected; 
-  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual; 
-  begin 
-    if (expected === 'hx || actual === 'hx) begin 
-      $display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); 
- result_slave = 0;    $stop; 
-  end 
-  if (actual != expected) begin 
-    $display("TESTBENCH ERROR! Data expected is not equal to actual.",     " expected = 0x%h",expected,     " actual   = 0x%h",actual); 
-    result_slave = 0; 
-    $stop; 
-  end 
-  else  
-    begin 
-     $display("TESTBENCH Passed! Data expected is equal to actual.", 
-              " expected = 0x%h",expected,               " actual   = 0x%h",actual); 
-    end 
-  end 
-endtask 
-integer                                 i; 
-integer                                 j;  
-xil_axi_uint                            trans_cnt_before_switch = 48;  
-xil_axi_uint                            passthrough_cmd_switch_cnt = 0;  
-event                                   passthrough_mastermode_start_event;  
-event                                   passthrough_mastermode_end_event;  
-event                                   passthrough_slavemode_end_event;  
-xil_axi_uint                            mtestID;  
-xil_axi_ulong                           mtestADDR;  
-xil_axi_len_t                           mtestBurstLength;  
-xil_axi_size_t                          mtestDataSize;   
-xil_axi_burst_t                         mtestBurstType;   
-xil_axi_lock_t                          mtestLOCK;  
-xil_axi_cache_t                         mtestCacheType = 0;  
-xil_axi_prot_t                          mtestProtectionType = 3'b000;  
-xil_axi_region_t                        mtestRegion = 4'b000;  
-xil_axi_qos_t                           mtestQOS = 4'b000;  
-xil_axi_data_beat                       dbeat;  
-xil_axi_data_beat [255:0]               mtestWUSER;   
-xil_axi_data_beat                       mtestAWUSER = 'h0;  
-xil_axi_data_beat                       mtestARUSER = 0;  
-xil_axi_data_beat [255:0]               mtestRUSER;      
-xil_axi_uint                            mtestBUSER = 0;  
-xil_axi_resp_t                          mtestBresp;  
-xil_axi_resp_t[255:0]                   mtestRresp;  
-bit [63:0]                              mtestWDataL; 
-bit [63:0]                              mtestRDataL; 
-axi_transaction                         pss_wr_transaction;   
-axi_transaction                         pss_rd_transaction;   
-axi_transaction                         reactive_transaction;   
-axi_transaction                         rd_payload_transaction;  
-axi_transaction                         wr_rand;  
-axi_transaction                         rd_rand;  
-axi_transaction                         wr_reactive;  
-axi_transaction                         rd_reactive;  
-axi_transaction                         wr_reactive2;   
-axi_transaction                         rd_reactive2;  
-axi_ready_gen                           bready_gen;  
-axi_ready_gen                           rready_gen;  
-axi_ready_gen                           awready_gen;  
-axi_ready_gen                           wready_gen;  
-axi_ready_gen                           arready_gen;  
-axi_ready_gen                           bready_gen2;  
-axi_ready_gen                           rready_gen2;  
-axi_ready_gen                           awready_gen2;  
-axi_ready_gen                           wready_gen2;  
-axi_ready_gen                           arready_gen2;  
-xil_axi_payload_byte                    data_mem[xil_axi_ulong];  
-neuron_v1_0_bfm_1_master_0_0_mst_t          mst_agent_0;
-
-  `BD_WRAPPER DUT(
-      .ARESETN(reset), 
-      .ACLK(clock) 
-    ); 
-  
-initial begin
-     mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms  
-   mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE); 
-   mst_agent_0.set_agent_tag("Master VIP"); 
-   mst_agent_0.set_verbosity(mst_agent_verbosity); 
-   mst_agent_0.start_master(); 
-     $timeformat (-12, 1, " ps", 1);
-  end
-  initial begin
-    reset <= 1'b0;
-    #200ns;
-    reset <= 1'b1;
-    repeat (5) @(negedge clock); 
-  end
-  always #5 clock <= ~clock;
-  initial begin
-      S_AXI_TEST ( );
-
-      #1ns;
-      $finish;
-  end
-task automatic S_AXI_TEST;  
-begin   
-#1; 
-   $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method starts"); 
-   mtestID = 0; 
-   mtestADDR = 64'h00000000; 
-   mtestBurstLength = 0; 
-   mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
-   mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
-   mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
-   mtestCacheType = 0;  
-   mtestProtectionType = 0;  
-   mtestRegion = 0; 
-   mtestQOS = 0; 
-   result_slave = 1; 
-  mtestWDataL[31:0] = 32'h00000001; 
-  for(int i = 0; i < 4;i++) begin 
-  S00_AXI_test_data[i] <= mtestWDataL[31:0];   
-  mst_agent_0.AXI4LITE_WRITE_BURST( 
-  mtestADDR, 
-  mtestProtectionType, 
-  mtestWDataL, 
-  mtestBresp 
-  );   
-  mtestWDataL[31:0] = mtestWDataL[31:0] + 1; 
-  mtestADDR = mtestADDR + 64'h4; 
-  end 
-     $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method completes"); 
-     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method starts"); 
-     mtestID = 0; 
-     mtestADDR = 64'h00000000; 
-     mtestBurstLength = 0; 
-     mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
-     mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
-     mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
-     mtestCacheType = 0;  
-     mtestProtectionType = 0;  
-     mtestRegion = 0; 
-     mtestQOS = 0; 
- for(int i = 0; i < 4;i++) begin 
-   mst_agent_0.AXI4LITE_READ_BURST( 
-        mtestADDR, 
-        mtestProtectionType, 
-        mtestRDataL, 
-        mtestRresp 
-      ); 
-   mtestADDR = mtestADDR + 64'h4; 
-   COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL); 
- end 
-     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method completes"); 
-     $display("Sequential read transfers example similar to  AXI VIP READ_BURST method completes"); 
-     $display("---------------------------------------------------------"); 
-     $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); 
-     if ( result_slave ) begin                    
-       $display("PTGEN_TEST: PASSED!");                  
-     end    else begin                                       
-       $display("PTGEN_TEST: FAILED!");                  
-     end                                
-     $display("---------------------------------------------------------"); 
-  end 
-endtask  
-
-endmodule

ip_repo_sources/neuron_1.0/example_designs/debug_hw_design/design.tcl

@@ -1,118 +0,0 @@
-
-proc create_ipi_design { offsetfile design_name } {
-
-	create_bd_design $design_name
-	open_bd_design $design_name
-
-	# Create and configure Clock/Reset
-	create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
-	create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
-
-	#Constraints will be provided manually while pin planning.
-		create_bd_port -dir I -type rst reset_rtl
-		set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
-		connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
-		connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
-		set external_reset_port reset_rtl
-		create_bd_port -dir I -type clk clock_rtl
-		connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
-		set external_clock_port clock_rtl
-	
-	#Avoid IPI DRC, make clock port synchronous to reset
-	if { $external_clock_port ne "" && $external_reset_port ne "" } {
-		set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
-	}
-
-	# Connect other sys_reset pins
-	connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
-
-	# Create instance: neuron_0, and set properties
-	set neuron_0 [ create_bd_cell -type ip -vlnv user.org:user:neuron:1.0 neuron_0 ]
-
-	# Create instance: jtag_axi_0, and set properties
-	set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
-	set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
-	connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
-	# Create instance: axi_peri_interconnect, and set properties
-	set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
-	set_property -dict [ list CONFIG.NUM_SI {1}  ] $axi_peri_interconnect
-	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
-	connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
-
-	set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
-	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
-	# Connect all clock & reset of neuron_0 slave interfaces..
-	connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins neuron_0/S00_AXI]
-	connect_bd_net [get_bd_pins neuron_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins neuron_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
-
-	# Auto assign address
-	assign_bd_address
-
-	# Copy all address to neuron_v1_0_include.tcl file
-	set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
-	upvar 1 $offsetfile offset_file
-	set offset_file "${bd_path}/neuron_v1_0_include.tcl"
-	set fp [open $offset_file "w"]
-	puts $fp "# Configuration address parameters"
-
-	set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_neuron_0_S00_AXI_* ]]
-	puts $fp "set s00_axi_addr ${offset}"
-
-	close $fp
-}
-
-# Set IP Repository and Update IP Catalogue 
-set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:neuron:1.0]]]]
-set hw_test_file ${ip_path}/example_designs/debug_hw_design/neuron_v1_0_hw_test.tcl
-
-set repo_paths [get_property ip_repo_paths [current_fileset]] 
-if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
-	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
-	update_ip_catalog
-}
-
-set design_name ""
-set all_bd {}
-set all_bd_files [get_files *.bd -quiet]
-foreach file $all_bd_files {
-set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
-set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
-lappend all_bd $bd_name
-}
-
-for { set i 1 } { 1 } { incr i } {
-	set design_name "neuron_v1_0_hw_${i}"
-	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
-		break
-	}
-}
-
-set intf_address_include_file ""
-create_ipi_design intf_address_include_file ${design_name}
-save_bd_design
-validate_bd_design
-
-set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
-import_files -force -norecurse $wrapper_file
-
-puts "-------------------------------------------------------------------------------------------------"
-puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
-puts "   please perform following steps to test design in targeted board."
-puts "1. Generate bitstream"
-puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
-puts "3. Download generated bitstream"
-puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
-puts "   to every interface present in the peripheral : xilinx.com:user:myip:1.0"
-puts "   : source -notrace ${hw_test_file}"
-puts "-------------------------------------------------------------------------------------------------"
-

ip_repo_sources/neuron_1.0/example_designs/debug_hw_design/neuron_v1_0_hw_test.tcl

@@ -1,45 +0,0 @@
-# Runtime Tcl commands to interact with - neuron_v1_0
-
-# Sourcing design address info tcl
-set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
-source ${bd_path}/neuron_v1_0_include.tcl
-
-# jtag axi master interface hardware name, change as per your design.
-set jtag_axi_master hw_axi_1
-set ec 0
-
-# hw test script
-# Delete all previous axis transactions
-if { [llength [get_hw_axi_txns -quiet]] } {
-	delete_hw_axi_txn [get_hw_axi_txns -quiet]
-}
-
-
-# Test all lite slaves.
-set wdata_1 abcd1234
-
-# Test: S00_AXI
-# Create a write transaction at s00_axi_addr address
-create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
-# Create a read transaction at s00_axi_addr address
-create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
-# Initiate transactions
-run_hw_axi r_s00_axi_addr
-run_hw_axi w_s00_axi_addr
-run_hw_axi r_s00_axi_addr
-set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
-# Compare read data
-if { $rdata_tmp == $wdata_1 } {
-	puts "Data comparison test pass for - S00_AXI"
-} else {
-	puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
-	inc ec
-}
-
-# Check error flag
-if { $ec == 0 } {
-	 puts "PTGEN_TEST: PASSED!" 
-} else {
-	 puts "PTGEN_TEST: FAILED!" 
-}
-

ip_repo_sources/neuron_1.0/hdl/neuron_v1_0.vhd

@@ -1,117 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity neuron_v1_0 is
-	generic (
-		-- Users to add parameters here
-
-		-- User parameters ends
-		-- Do not modify the parameters beyond this line
-
-
-		-- Parameters of Axi Slave Bus Interface S00_AXI
-		C_S00_AXI_DATA_WIDTH	: integer	:= 32;
-		C_S00_AXI_ADDR_WIDTH	: integer	:= 7
-	);
-	port (
-		-- Users to add ports here
-
-		-- User ports ends
-		-- Do not modify the ports beyond this line
-
-
-		-- Ports of Axi Slave Bus Interface S00_AXI
-		s00_axi_aclk	: in std_logic;
-		s00_axi_aresetn	: in std_logic;
-		s00_axi_awaddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
-		s00_axi_awprot	: in std_logic_vector(2 downto 0);
-		s00_axi_awvalid	: in std_logic;
-		s00_axi_awready	: out std_logic;
-		s00_axi_wdata	: in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
-		s00_axi_wstrb	: in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
-		s00_axi_wvalid	: in std_logic;
-		s00_axi_wready	: out std_logic;
-		s00_axi_bresp	: out std_logic_vector(1 downto 0);
-		s00_axi_bvalid	: out std_logic;
-		s00_axi_bready	: in std_logic;
-		s00_axi_araddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
-		s00_axi_arprot	: in std_logic_vector(2 downto 0);
-		s00_axi_arvalid	: in std_logic;
-		s00_axi_arready	: out std_logic;
-		s00_axi_rdata	: out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
-		s00_axi_rresp	: out std_logic_vector(1 downto 0);
-		s00_axi_rvalid	: out std_logic;
-		s00_axi_rready	: in std_logic
-	);
-end neuron_v1_0;
-
-architecture arch_imp of neuron_v1_0 is
-
-	-- component declaration
-	component neuron_v1_0_S00_AXI is
-		generic (
-		C_S_AXI_DATA_WIDTH	: integer	:= 32;
-		C_S_AXI_ADDR_WIDTH	: integer	:= 7
-		);
-		port (
-		S_AXI_ACLK	: in std_logic;
-		S_AXI_ARESETN	: in std_logic;
-		S_AXI_AWADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		S_AXI_AWPROT	: in std_logic_vector(2 downto 0);
-		S_AXI_AWVALID	: in std_logic;
-		S_AXI_AWREADY	: out std_logic;
-		S_AXI_WDATA	: in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		S_AXI_WSTRB	: in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-		S_AXI_WVALID	: in std_logic;
-		S_AXI_WREADY	: out std_logic;
-		S_AXI_BRESP	: out std_logic_vector(1 downto 0);
-		S_AXI_BVALID	: out std_logic;
-		S_AXI_BREADY	: in std_logic;
-		S_AXI_ARADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		S_AXI_ARPROT	: in std_logic_vector(2 downto 0);
-		S_AXI_ARVALID	: in std_logic;
-		S_AXI_ARREADY	: out std_logic;
-		S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		S_AXI_RRESP	: out std_logic_vector(1 downto 0);
-		S_AXI_RVALID	: out std_logic;
-		S_AXI_RREADY	: in std_logic
-		);
-	end component neuron_v1_0_S00_AXI;
-
-begin
-
--- Instantiation of Axi Bus Interface S00_AXI
-neuron_v1_0_S00_AXI_inst : neuron_v1_0_S00_AXI
-	generic map (
-		C_S_AXI_DATA_WIDTH	=> C_S00_AXI_DATA_WIDTH,
-		C_S_AXI_ADDR_WIDTH	=> C_S00_AXI_ADDR_WIDTH
-	)
-	port map (
-		S_AXI_ACLK	=> s00_axi_aclk,
-		S_AXI_ARESETN	=> s00_axi_aresetn,
-		S_AXI_AWADDR	=> s00_axi_awaddr,
-		S_AXI_AWPROT	=> s00_axi_awprot,
-		S_AXI_AWVALID	=> s00_axi_awvalid,
-		S_AXI_AWREADY	=> s00_axi_awready,
-		S_AXI_WDATA	=> s00_axi_wdata,
-		S_AXI_WSTRB	=> s00_axi_wstrb,
-		S_AXI_WVALID	=> s00_axi_wvalid,
-		S_AXI_WREADY	=> s00_axi_wready,
-		S_AXI_BRESP	=> s00_axi_bresp,
-		S_AXI_BVALID	=> s00_axi_bvalid,
-		S_AXI_BREADY	=> s00_axi_bready,
-		S_AXI_ARADDR	=> s00_axi_araddr,
-		S_AXI_ARPROT	=> s00_axi_arprot,
-		S_AXI_ARVALID	=> s00_axi_arvalid,
-		S_AXI_ARREADY	=> s00_axi_arready,
-		S_AXI_RDATA	=> s00_axi_rdata,
-		S_AXI_RRESP	=> s00_axi_rresp,
-		S_AXI_RVALID	=> s00_axi_rvalid,
-		S_AXI_RREADY	=> s00_axi_rready
-	);
-
-	-- Add user logic here
-	-- User logic ends
-
-end arch_imp;

ip_repo_sources/neuron_1.0/hdl/neuron_v1_0_S00_AXI.vhd

@@ -1,812 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.myPackage.ALL;
-
-entity neuron_v1_0_S00_AXI is
-	generic (
-		-- Users to add parameters here
-
-		-- User parameters ends
-		-- Do not modify the parameters beyond this line
-
-		-- Width of S_AXI data bus
-		C_S_AXI_DATA_WIDTH	: integer	:= 32;
-		-- Width of S_AXI address bus
-		C_S_AXI_ADDR_WIDTH	: integer	:= 7
-	);
-	port (
-		-- Users to add ports here
-
-		-- User ports ends
-		-- Do not modify the ports beyond this line
-
-		-- Global Clock Signal
-		S_AXI_ACLK	: in std_logic;
-		-- Global Reset Signal. This Signal is Active LOW
-		S_AXI_ARESETN	: in std_logic;
-		-- Write address (issued by master, acceped by Slave)
-		S_AXI_AWADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		-- Write channel Protection type. This signal indicates the
-    		-- privilege and security level of the transaction, and whether
-    		-- the transaction is a data access or an instruction access.
-		S_AXI_AWPROT	: in std_logic_vector(2 downto 0);
-		-- Write address valid. This signal indicates that the master signaling
-    		-- valid write address and control information.
-		S_AXI_AWVALID	: in std_logic;
-		-- Write address ready. This signal indicates that the slave is ready
-    		-- to accept an address and associated control signals.
-		S_AXI_AWREADY	: out std_logic;
-		-- Write data (issued by master, acceped by Slave) 
-		S_AXI_WDATA	: in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		-- Write strobes. This signal indicates which byte lanes hold
-    		-- valid data. There is one write strobe bit for each eight
-    		-- bits of the write data bus.    
-		S_AXI_WSTRB	: in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-		-- Write valid. This signal indicates that valid write
-    		-- data and strobes are available.
-		S_AXI_WVALID	: in std_logic;
-		-- Write ready. This signal indicates that the slave
-    		-- can accept the write data.
-		S_AXI_WREADY	: out std_logic;
-		-- Write response. This signal indicates the status
-    		-- of the write transaction.
-		S_AXI_BRESP	: out std_logic_vector(1 downto 0);
-		-- Write response valid. This signal indicates that the channel
-    		-- is signaling a valid write response.
-		S_AXI_BVALID	: out std_logic;
-		-- Response ready. This signal indicates that the master
-    		-- can accept a write response.
-		S_AXI_BREADY	: in std_logic;
-		-- Read address (issued by master, acceped by Slave)
-		S_AXI_ARADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		-- Protection type. This signal indicates the privilege
-    		-- and security level of the transaction, and whether the
-    		-- transaction is a data access or an instruction access.
-		S_AXI_ARPROT	: in std_logic_vector(2 downto 0);
-		-- Read address valid. This signal indicates that the channel
-    		-- is signaling valid read address and control information.
-		S_AXI_ARVALID	: in std_logic;
-		-- Read address ready. This signal indicates that the slave is
-    		-- ready to accept an address and associated control signals.
-		S_AXI_ARREADY	: out std_logic;
-		-- Read data (issued by slave)
-		S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		-- Read response. This signal indicates the status of the
-    		-- read transfer.
-		S_AXI_RRESP	: out std_logic_vector(1 downto 0);
-		-- Read valid. This signal indicates that the channel is
-    		-- signaling the required read data.
-		S_AXI_RVALID	: out std_logic;
-		-- Read ready. This signal indicates that the master can
-    		-- accept the read data and response information.
-		S_AXI_RREADY	: in std_logic
-	);
-end neuron_v1_0_S00_AXI;
-
-architecture arch_imp of neuron_v1_0_S00_AXI is
-
-	-- AXI4LITE signals
-	signal axi_awaddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-	signal axi_awready	: std_logic;
-	signal axi_wready	: std_logic;
-	signal axi_bresp	: std_logic_vector(1 downto 0);
-	signal axi_bvalid	: std_logic;
-	signal axi_araddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-	signal axi_arready	: std_logic;
-	signal axi_rdata	: std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal axi_rresp	: std_logic_vector(1 downto 0);
-	signal axi_rvalid	: std_logic;
-
-	-- Example-specific design signals
-	-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-	-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-	-- ADDR_LSB = 2 for 32 bits (n downto 2)
-	-- ADDR_LSB = 3 for 64 bits (n downto 3)
-	constant ADDR_LSB  : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
-	constant OPT_MEM_ADDR_BITS : integer := 4;
-	------------------------------------------------
-	---- Signals for user logic register space example
-	--------------------------------------------------
-	---- Number of Slave Registers 32
-	signal slv_reg0	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg1	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg2	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg3	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg4	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg5	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg6	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg7	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg8	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg9	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg10	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg11	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg12	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg13	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg14	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg15	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg16	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg17	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg18	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg19	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg20	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg21	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg22	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg23	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg24	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg25	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg26	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg27	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg28	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg29	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg30	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg31	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg_rden	: std_logic;
-	signal slv_reg_wren	: std_logic;
-	signal reg_data_out	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal byte_index	: integer;
-	signal aw_en	: std_logic;
-	
-
-    component mac is
-     port ( 
-       inputs : in dataVector;
-       weights : in dataVector;
-       bias : in dataType;
-       outp : out dataType;
-       clk: in STD_LOGIC);
-    end component;
-    
-    component sigmoid is
-     port ( 
-       inp : in dataType;
-       clk : in std_logic;
-       outp : out dataType);
-    end component;
-    
-    signal var1 : dataType;
-    signal calc_outp: dataType;
-    signal inputs : dataVector;
-    signal weights : dataVector;
-
-begin
-	-- I/O Connections assignments
-
-	S_AXI_AWREADY	<= axi_awready;
-	S_AXI_WREADY	<= axi_wready;
-	S_AXI_BRESP	<= axi_bresp;
-	S_AXI_BVALID	<= axi_bvalid;
-	S_AXI_ARREADY	<= axi_arready;
-	S_AXI_RDATA	<= axi_rdata;
-	S_AXI_RRESP	<= axi_rresp;
-	S_AXI_RVALID	<= axi_rvalid;
-	-- Implement axi_awready generation
-	-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-	-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-	-- de-asserted when reset is low.
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_awready <= '0';
-	      aw_en <= '1';
-	    else
-	      if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-	        -- slave is ready to accept write address when
-	        -- there is a valid write address and write data
-	        -- on the write address and data bus. This design 
-	        -- expects no outstanding transactions. 
-	           axi_awready <= '1';
-	           aw_en <= '0';
-	        elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
-	           aw_en <= '1';
-	           axi_awready <= '0';
-	      else
-	        axi_awready <= '0';
-	      end if;
-	    end if;
-	  end if;
-	end process;
-
-	-- Implement axi_awaddr latching
-	-- This process is used to latch the address when both 
-	-- S_AXI_AWVALID and S_AXI_WVALID are valid. 
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_awaddr <= (others => '0');
-	    else
-	      if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-	        -- Write Address latching
-	        axi_awaddr <= S_AXI_AWADDR;
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement axi_wready generation
-	-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-	-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
-	-- de-asserted when reset is low. 
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_wready <= '0';
-	    else
-	      if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
-	          -- slave is ready to accept write data when 
-	          -- there is a valid write address and write data
-	          -- on the write address and data bus. This design 
-	          -- expects no outstanding transactions.           
-	          axi_wready <= '1';
-	      else
-	        axi_wready <= '0';
-	      end if;
-	    end if;
-	  end if;
-	end process; 
-
-	-- Implement memory mapped register select and write logic generation
-	-- The write data is accepted and written to memory mapped registers when
-	-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-	-- select byte enables of slave registers while writing.
-	-- These registers are cleared when reset (active low) is applied.
-	-- Slave register write enable is asserted when valid address and data are available
-	-- and the slave is ready to accept the write address and write data.
-	slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
-
-	process (S_AXI_ACLK)
-	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); 
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      slv_reg0 <= (others => '0');
-	      slv_reg1 <= (others => '0');
-	      slv_reg2 <= (others => '0');
-	      slv_reg3 <= (others => '0');
-	      slv_reg4 <= (others => '0');
-	      slv_reg5 <= (others => '0');
-	      slv_reg6 <= (others => '0');
-	      slv_reg7 <= (others => '0');
-	      slv_reg8 <= (others => '0');
-	      slv_reg9 <= (others => '0');
-	      slv_reg10 <= (others => '0');
-	      slv_reg11 <= (others => '0');
-	      slv_reg12 <= (others => '0');
-	      slv_reg13 <= (others => '0');
-	      slv_reg14 <= (others => '0');
-	      slv_reg15 <= (others => '0');
-	      slv_reg16 <= (others => '0');
-	      slv_reg17 <= (others => '0');
-	      slv_reg18 <= (others => '0');
-	      slv_reg19 <= (others => '0');
-	      slv_reg20 <= (others => '0');
-	      slv_reg21 <= (others => '0');
-	      slv_reg22 <= (others => '0');
-	      slv_reg23 <= (others => '0');
-	      slv_reg24 <= (others => '0');
-	      slv_reg25 <= (others => '0');
-	      slv_reg26 <= (others => '0');
-	      slv_reg27 <= (others => '0');
-	      slv_reg28 <= (others => '0');
-	      slv_reg29 <= (others => '0');
-	      slv_reg30 <= (others => '0');
-	      slv_reg31 <= (others => '0');
-	    else
-	      loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
-	      if (slv_reg_wren = '1') then
-	        case loc_addr is
-	          when b"00000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 0
-	                slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 1
-	                slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 2
-	                slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 3
-	                slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 4
-	                slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 5
-	                slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 6
-	                slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 7
-	                slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 8
-	                slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 9
-	                slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 10
-	                slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 11
-	                slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 12
-	                slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 13
-	                slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 14
-	                slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 15
-	                slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 16
-	                slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 17
-	                slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 18
-	                slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 19
-	                slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 20
-	                slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 21
-	                slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 22
-	                slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 23
-	                slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 24
-	                slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 25
-	                slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 26
-	                slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 27
-	                slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 28
-	                slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 29
-	                slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 30
-	                slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 31
-	                slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when others =>
-	            slv_reg0 <= slv_reg0;
-	            slv_reg1 <= slv_reg1;
-	            slv_reg2 <= slv_reg2;
-	            slv_reg3 <= slv_reg3;
-	            slv_reg4 <= slv_reg4;
-	            slv_reg5 <= slv_reg5;
-	            slv_reg6 <= slv_reg6;
-	            slv_reg7 <= slv_reg7;
-	            slv_reg8 <= slv_reg8;
-	            slv_reg9 <= slv_reg9;
-	            slv_reg10 <= slv_reg10;
-	            slv_reg11 <= slv_reg11;
-	            slv_reg12 <= slv_reg12;
-	            slv_reg13 <= slv_reg13;
-	            slv_reg14 <= slv_reg14;
-	            slv_reg15 <= slv_reg15;
-	            slv_reg16 <= slv_reg16;
-	            slv_reg17 <= slv_reg17;
-	            slv_reg18 <= slv_reg18;
-	            slv_reg19 <= slv_reg19;
-	            slv_reg20 <= slv_reg20;
-	            slv_reg21 <= slv_reg21;
-	            slv_reg22 <= slv_reg22;
-	            slv_reg23 <= slv_reg23;
-	            slv_reg24 <= slv_reg24;
-	            slv_reg25 <= slv_reg25;
-	            slv_reg26 <= slv_reg26;
-	            slv_reg27 <= slv_reg27;
-	            slv_reg28 <= slv_reg28;
-	            slv_reg29 <= slv_reg29;
-	            slv_reg30 <= slv_reg30;
-	            slv_reg31 <= slv_reg31;
-	        end case;
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement write response logic generation
-	-- The write response and response valid signals are asserted by the slave 
-	-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
-	-- This marks the acceptance of address and indicates the status of 
-	-- write transaction.
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_bvalid  <= '0';
-	      axi_bresp   <= "00"; --need to work more on the responses
-	    else
-	      if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0'  ) then
-	        axi_bvalid <= '1';
-	        axi_bresp  <= "00"; 
-	      elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then   --check if bready is asserted while bvalid is high)
-	        axi_bvalid <= '0';                                 -- (there is a possibility that bready is always asserted high)
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement axi_arready generation
-	-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-	-- S_AXI_ARVALID is asserted. axi_awready is 
-	-- de-asserted when reset (active low) is asserted. 
-	-- The read address is also latched when S_AXI_ARVALID is 
-	-- asserted. axi_araddr is reset to zero on reset assertion.
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_arready <= '0';
-	      axi_araddr  <= (others => '1');
-	    else
-	      if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-	        -- indicates that the slave has acceped the valid read address
-	        axi_arready <= '1';
-	        -- Read Address latching 
-	        axi_araddr  <= S_AXI_ARADDR;           
-	      else
-	        axi_arready <= '0';
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement axi_arvalid generation
-	-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
-	-- S_AXI_ARVALID and axi_arready are asserted. The slave registers 
-	-- data are available on the axi_rdata bus at this instance. The 
-	-- assertion of axi_rvalid marks the validity of read data on the 
-	-- bus and axi_rresp indicates the status of read transaction.axi_rvalid 
-	-- is deasserted on reset (active low). axi_rresp and axi_rdata are 
-	-- cleared to zero on reset (active low).  
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then
-	    if S_AXI_ARESETN = '0' then
-	      axi_rvalid <= '0';
-	      axi_rresp  <= "00";
-	    else
-	      if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-	        -- Valid read data is available at the read data bus
-	        axi_rvalid <= '1';
-	        axi_rresp  <= "00"; -- 'OKAY' response
-	      elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-	        -- Read data is accepted by the master
-	        axi_rvalid <= '0';
-	      end if;            
-	    end if;
-	  end if;
-	end process;
-
-	-- Implement memory mapped register select and read logic generation
-	-- Slave register read enable is asserted when valid address is available
-	-- and the slave is ready to accept the read address.
-	slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
-
-	process (calc_outp, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
-	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
-	begin
-	    -- Address decoding for reading registers
-	    loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
-	    case loc_addr is
-	      when b"00000" =>
-	        reg_data_out <= calc_outp;
-	      when b"00001" =>
-	        reg_data_out <= slv_reg1;
-	      when b"00010" =>
-	        reg_data_out <= slv_reg2;
-	      when b"00011" =>
-	        reg_data_out <= slv_reg3;
-	      when b"00100" =>
-	        reg_data_out <= slv_reg4;
-	      when b"00101" =>
-	        reg_data_out <= slv_reg5;
-	      when b"00110" =>
-	        reg_data_out <= slv_reg6;
-	      when b"00111" =>
-	        reg_data_out <= slv_reg7;
-	      when b"01000" =>
-	        reg_data_out <= slv_reg8;
-	      when b"01001" =>
-	        reg_data_out <= slv_reg9;
-	      when b"01010" =>
-	        reg_data_out <= slv_reg10;
-	      when b"01011" =>
-	        reg_data_out <= slv_reg11;
-	      when b"01100" =>
-	        reg_data_out <= slv_reg12;
-	      when b"01101" =>
-	        reg_data_out <= slv_reg13;
-	      when b"01110" =>
-	        reg_data_out <= slv_reg14;
-	      when b"01111" =>
-	        reg_data_out <= slv_reg15;
-	      when b"10000" =>
-	        reg_data_out <= slv_reg16;
-	      when b"10001" =>
-	        reg_data_out <= slv_reg17;
-	      when b"10010" =>
-	        reg_data_out <= slv_reg18;
-	      when b"10011" =>
-	        reg_data_out <= slv_reg19;
-	      when b"10100" =>
-	        reg_data_out <= slv_reg20;
-	      when b"10101" =>
-	        reg_data_out <= slv_reg21;
-	      when b"10110" =>
-	        reg_data_out <= slv_reg22;
-	      when b"10111" =>
-	        reg_data_out <= slv_reg23;
-	      when b"11000" =>
-	        reg_data_out <= slv_reg24;
-	      when b"11001" =>
-	        reg_data_out <= slv_reg25;
-	      when b"11010" =>
-	        reg_data_out <= slv_reg26;
-	      when b"11011" =>
-	        reg_data_out <= slv_reg27;
-	      when b"11100" =>
-	        reg_data_out <= slv_reg28;
-	      when b"11101" =>
-	        reg_data_out <= slv_reg29;
-	      when b"11110" =>
-	        reg_data_out <= slv_reg30;
-	      when b"11111" =>
-	        reg_data_out <= slv_reg31;
-	      when others =>
-	        reg_data_out  <= (others => '0');
-	    end case;
-	end process; 
-
-	-- Output register or memory read data
-	process( S_AXI_ACLK ) is
-	begin
-	  if (rising_edge (S_AXI_ACLK)) then
-	    if ( S_AXI_ARESETN = '0' ) then
-	      axi_rdata  <= (others => '0');
-	    else
-	      if (slv_reg_rden = '1') then
-	        -- When there is a valid read address (S_AXI_ARVALID) with 
-	        -- acceptance of read address by the slave (axi_arready), 
-	        -- output the read dada 
-	        -- Read address mux
-	          axi_rdata <= reg_data_out;     -- register read data
-	      end if;   
-	    end if;
-	  end if;
-	end process;
-
-
-	-- Add user logic here
-    mac1: mac port map (
-        inputs => inputs,
-        weights => weights,
-        bias => slv_reg20,
-        outp => var1,
-        clk => S_AXI_ACLK
-    );
-    
-    sig1: sigmoid port map (
-        inp => var1,
-        clk => S_AXI_ACLK,
-        outp => calc_outp
-    );
-    
-    inputs (0) <= slv_reg0;
-    weights(0) <= slv_reg1;
-    inputs (1) <= slv_reg2;
-    weights(1) <= slv_reg3;
-    inputs (2) <= slv_reg4;
-    weights(2) <= slv_reg5;
-    inputs (3) <= slv_reg6;
-    weights(3) <= slv_reg7;
-    inputs (4) <= slv_reg8;
-    weights(4) <= slv_reg9;
-    inputs (5) <= slv_reg10;
-    weights(5) <= slv_reg11;
-    inputs (6) <= slv_reg12;
-    weights(6) <= slv_reg13;
-    inputs (7) <= slv_reg14;
-    weights(7) <= slv_reg15;
-    inputs (8) <= slv_reg16;
-    weights(8) <= slv_reg17;
-    inputs (9) <= slv_reg18;
-    weights(9) <= slv_reg19;
-    
-	-- User logic ends
-
-end arch_imp;

ip_repo_sources/neuron_1.0/src/globals.vhd

@@ -1,28 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.math_real.all;
-
-package myPackage is
-    
-    constant nNodes : integer := 10;
-    constant nBits : integer := 32;
-    subtype dataType is std_logic_vector(nBits-1 downto 0);
-    subtype dataTypeAdder is std_logic_vector(integer(ceil(log2(real(nBits)))) downto 0);
-    type dataVector is array(0 to nNodes-1) of std_logic_vector(nBits-1 downto 0);
-end myPackage;
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity globals is
---  Port ( );
-end globals;
-
-architecture Behavioral of globals is
-
-begin
-
-
-end Behavioral;

ip_repo_sources/neuron_1.0/src/mac.vhd

@@ -1,42 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_arith.ALL;
-use IEEE.std_logic_textio.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.myPackage.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity mac is
-    Port ( inputs : in dataVector;
-           weights : in dataVector;
-           bias : in dataType;
-           outp : out dataType;
-           clk: in STD_LOGIC);
-end mac;
-
-architecture Behavioral of mac is
-
-begin
-
-MAIN: process(clk)
-    variable sum : dataType;
-begin
-    if rising_edge(clk) then
-        sum :=  bias;
-        for i in 0 to nNodes-1 loop
-            sum := sum + conv_integer(inputs(i)) * conv_integer(weights(i));
-        end loop;
-        
-        outp <= sum;
-    end if;
-end process;
-
-end Behavioral;

ip_repo_sources/neuron_1.0/src/neuron.vhd

@@ -1,47 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity neuron is
-    Port (
-        inputs : in dataVector;
-        weights : in dataVector;
-        bias : in dataType;
-        clk : in std_logic;
-        outp : out dataType);
-end neuron;
-
-architecture Behavioral of neuron is 
-
-component mac is
- port ( 
-   inputs : in dataVector;
-   weights : in dataVector;
-   bias : in dataType;
-   outp : out dataType);
-end component;
-
-component sigmoid is
- port ( 
-   inp : in dataType;
-   clk : in std_logic;
-   outp : out dataType);
-end component;
-
-signal var1 : dataType;
-
-begin
-mac1: mac port map (
-    inputs => inputs,
-    weights => weights,
-    bias => bias,
-    outp => var1
-);
-
-sig1: sigmoid port map (
-    inp => var1,
-    clk => clk,
-    outp => outp
-);
-
-end Behavioral;

ip_repo_sources/neuron_1.0/src/neuron4.vhd

@@ -1,61 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity neuron4 is
-    Port (
-        input0 : in std_logic_vector(nBits-1 downto 0);
-        input1 : in std_logic_vector(nBits-1 downto 0);
-        input2 : in std_logic_vector(nBits-1 downto 0);
-        input3 : in std_logic_vector(nBits-1 downto 0);
-        weight0 : in std_logic_vector(nBits-1 downto 0);
-        weight1 : in std_logic_vector(nBits-1 downto 0);
-        weight2 : in std_logic_vector(nBits-1 downto 0);
-        weight3 : in std_logic_vector(nBits-1 downto 0);
-        
-        bias : in std_logic_vector(nBits-1 downto 0);
-        clk : in std_logic;
-        outp : out std_logic_vector(nBits-1 downto 0));
-end neuron4;
-
-architecture Behavioral of neuron4 is 
-
-component mac is
- port ( 
-   inputs : in dataVector;
-   weights : in dataVector;
-   bias : in dataType;
-   outp : out dataType);
-end component;
-
-component sigmoid is
- port ( 
-   inp : in dataType;
-   clk : in std_logic;
-   outp : out dataType);
-end component;
-
-signal var1 : dataType;
-
-begin
-mac1: mac port map (
-    inputs(0) => input0,
-    inputs(1) => input1,
-    inputs(2) => input2,
-    inputs(3) => input3,
-    weights(0) => weight0,
-    weights(1) => weight1,
-    weights(2) => weight2,
-    weights(3) => weight3,
-    
-    bias => bias,
-    outp => var1
-);
-
-sig1: sigmoid port map (
-    inp => var1,
-    clk => clk,
-    outp => outp
-);
-
-end Behavioral;

ip_repo_sources/neuron_1.0/xgui/neuron_v1_0.tcl

@@ -1,62 +0,0 @@
-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
-  ipgui::add_param $IPINST -name "Component_Name"
-  #Adding Page
-  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
-  set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox]
-  set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH}
-  set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}]
-  set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH}
-  ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
-  ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
-
-
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
-	# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
-	# Procedure called to validate C_S00_AXI_DATA_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
-	# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
-	# Procedure called to validate C_S00_AXI_ADDR_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
-	# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
-	# Procedure called to validate C_S00_AXI_BASEADDR
-	return true
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
-	# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
-	# Procedure called to validate C_S00_AXI_HIGHADDR
-	return true
-}
-
-
-proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
-	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
-	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
-}
-

ip_repo_sources/neuron_packed/component.xml

@@ -1,1492 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-  <spirit:vendor>xilinx.com</spirit:vendor>
-  <spirit:library>user</spirit:library>
-  <spirit:name>packaging</spirit:name>
-  <spirit:version>2.0</spirit:version>
-  <spirit:busInterfaces>
-    <spirit:busInterface>
-      <spirit:name>rst</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RST</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>rst</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>clk</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>CLK</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>clk</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>ASSOCIATED_RESET</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">rst</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>fifo_read</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read_rtl" spirit:version="1.0"/>
-      <spirit:master/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RD_DATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>inputStream</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>EMPTY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>inputEmpty</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RD_EN</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>inpRdEn</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>fifo_write</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write_rtl" spirit:version="1.0"/>
-      <spirit:master/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ALMOST_FULL</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>outputFull</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WR_DATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>outData</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WR_EN</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>outWrEn</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-    </spirit:busInterface>
-  </spirit:busInterfaces>
-  <spirit:model>
-    <spirit:views>
-      <spirit:view>
-        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
-        <spirit:displayName>Synthesis</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
-        <spirit:language>VHDL</spirit:language>
-        <spirit:modelName>packaging</spirit:modelName>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>e0830e35</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
-        <spirit:displayName>Simulation</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
-        <spirit:language>VHDL</spirit:language>
-        <spirit:modelName>packaging</spirit:modelName>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>e0830e35</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_xpgui</spirit:name>
-        <spirit:displayName>UI Layout</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>b2335c60</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-    </spirit:views>
-    <spirit:ports>
-      <spirit:port>
-        <spirit:name>clk</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>rst</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>inputStream</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.busWidth&apos;)) - 1)">31</spirit:left>
-            <spirit:right spirit:format="long">0</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>inpRdEn</spirit:name>
-        <spirit:wire>
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ip_repo_sources/neuron_packed/src/dummyModule.vhd

@@ -1,188 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 12.06.2019 22:30:43
--- Design Name: 
--- Module Name: dummyModule - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity dummyModule is
-    generic(
-        busWidth : integer:=32;
-        regDepth : integer:=4);
-    Port ( clk : in STD_LOGIC;
-           rst_n : in STD_LOGIC;
-           start : in STD_LOGIC;
-           ready: out std_logic;
-           idle : out std_logic;
-           done : out std_logic;
-           
-           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           srcValid : in std_logic;
-           srcReady : out std_logic;
-           
-           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           dstValid : out std_logic;
-           dstReady : in std_logic);
-end dummyModule;
-
-architecture Behavioral of dummyModule is
-
-    constant regWidth : integer:= regDepth * busWidth;
-
-    component shiftIn is
-        generic(
-            inWidth : integer := busWidth;
-            outWidth : integer := regWidth);
-        Port ( clk : in STD_LOGIC;
-               ce : in std_logic;
-               sync_reset : in STD_LOGIC;
-               dataIn : in std_logic_vector(inWidth-1 downto 0);
-               dataOut : out std_logic_vector(outWidth-1 downto 0);
-               finished : out STD_LOGIC);
-    end component;
-    component dummyModuleLogic is
-        generic(
-            regWidth : integer:=regWidth);
-        Port (
-            inputs : in std_logic_vector(regWidth-1 downto 0);
-            start : in std_logic;
-            finished : out std_logic;
-            clk : in std_logic;
-            outputs : out std_logic_vector(regWidth-1 downto 0));
-    end component;
-    component shiftOut is
-        generic(
-            inWidth : integer := regWidth;
-            outWidth : integer := busWidth);
-        Port ( clk : in STD_LOGIC;
-               ce : in std_logic;
-               sync_reset : in STD_LOGIC;
-               dataIn : in std_logic_vector(inWidth-1 downto 0);
-               dataOut : out std_logic_vector(outWidth-1 downto 0);
-               valid : out std_logic;
-               finished : out STD_LOGIC);
-    end component;
-    
-    signal dataInStorage : std_logic_vector(regWidth-1 downto 0);
-    signal dataOutStorage : std_logic_vector(regWidth-1 downto 0);
-    signal startShiftIn : std_logic;
-    signal shiftInFinished : std_logic;
-    signal calcFinished : std_logic;
-    signal shiftOutFinished : std_logic;
-    
-    type state_t is (waiting, srcShift, calc, dstShift);
-    signal state : state_t := waiting;
-
-begin
-    shiftIn2: shiftIn port map (
-        clk         => clk,
-        ce          => srcValid,
-        sync_reset  => startShiftIn,
-        dataIn      => srcData,
-        dataOut     => dataInStorage,
-        finished    => shiftInFinished
-    );
-    
-    dummyModuleLogic1: dummyModuleLogic port map (
-        inputs  => dataInStorage,
-        clk     => clk,
-        outputs => dataOutStorage,
-        start   => shiftInFinished,
-        finished=> calcFinished
-    );
-    
-    shiftOut2 : shiftOut port map (
-        clk         => clk,
-        ce      => dstReady,
-        sync_reset  => calcFinished,
-        dataIn      => dataOutStorage,
-        dataOut     => dstData,
-        finished    => shiftOutFinished,
-        valid       => dstValid
-    );
-    
-    fsm : process(clk, rst_n)
-    
-    begin
-        if rst_n = '0' then
-            state <= waiting;
-            ready <= '0';
-        elsif rising_edge(clk) then
-            startShiftIn <= '1';
-            idle <= '0';
-            ready <= '1';
-            case state is
-                when waiting =>
-                    if start='1' and shiftOutFinished = '0'  then
-                        state <= srcShift;
-                    else
-                        startShiftIn <= '0';
-                        idle <= '1';
-                    end if;
-                    
-                    
-                when srcShift =>
-                    
-                    if shiftInFinished = '1' then
-                        state <= calc;
-                    end if;
-                when calc =>
-                    if calcFinished='1' then
-                        state <= dstShift;
-                    end if;
-                when dstShift =>
-                    if shiftOutFinished='1' then
-                        state <= waiting;
-                    end if;
-            end case;
-        end if;
-    end process;
-    process(startShiftIn, shiftInFinished, shiftOutFinished, start) begin
-        srcReady <= startShiftIn and not shiftInFinished;
-        done <= start and shiftOutFinished;
-    end process;
-end Behavioral;
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity dummyModuleLogic is
-    Generic (
-        regWidth : integer := 16
-    );
-    Port (
-        inputs : in std_logic_vector(regWidth-1 downto 0);
-        start : in std_logic;
-        finished : out std_logic;
-        clk : in std_logic;
-        outputs : out std_logic_vector(regWidth-1 downto 0));
-end dummyModuleLogic;
-
-architecture Behavioral of dummyModuleLogic is
-
-begin
-    process(clk)
-    begin
-        if(rising_edge(clk)) then
-            outputs <= inputs;
-            finished <= start;
-        end if;
-    end process;
-end Behavioral;

ip_repo_sources/neuron_packed/src/globals.vhd

@@ -1,40 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.math_real.all;
-
-package myPackage is
-    
-    constant nNodes : integer := 10;
-    constant nBits : integer := 32;
-    subtype dataType is std_logic_vector(nBits-1 downto 0);
-    type dataVector is array(nNodes-1 downto 0) of std_logic_vector(nBits-1 downto 0);
-    function to_dataVector(x : in std_logic_vector(nBits*nNodes-1 downto 0)) return dataVector;
-    
-end myPackage;
-
-package body myPackage is
-    function to_dataVector(x : in std_logic_vector(nBits*nNodes-1 downto 0)) return dataVector is
-    variable ret : dataVector;
-    begin
-        for i in integer range 0 to (x'length/nBits) - 1 loop
-            ret(i) := x(i * nBits + nBits - 1 downto i * nBits);
-        end loop;
-        return ret;
-    end function;
-
-end myPackage;
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity globals is
---Port ( );
-end globals;
-
-architecture Behavioral of globals is
-
-begin
-
-
-end Behavioral;

ip_repo_sources/neuron_packed/src/multiplex.vhd

@@ -1,228 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 03.06.2019 18:42:50
--- Design Name: 
--- Module Name: multiplex - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_arith.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.myPackage.ALL;
-
-entity multiplex is
-    generic(
-        busWidth : integer:=32);
-    Port ( clk : in STD_LOGIC;
-           start : in STD_LOGIC;
-           ready: out std_logic;
-           rst : in STD_LOGIC;
-           done : out STD_LOGIC;
-           idle : out STD_LOGIC;
-           
-           moduleId : in STD_LOGIC_VECTOR (31 downto 0);
-           
-           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           srcValid : in std_logic;
-           srcReady : out std_logic;
-           
-           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           dstValid : out std_logic;
-           dstReady : in std_logic
-    );
-end multiplex;
-
-architecture Behavioral of multiplex is
-
-component parallelize is
-    generic(
-        busWidth : integer:=busWidth);
-    Port ( clk : in STD_LOGIC;
-           rst : in STD_LOGIC;
-           start : in STD_LOGIC;
-           dataIn : in std_logic_vector(busWidth-1 downto 0);
-           ready: out std_logic;
-           dataOutReset : in std_logic;
-           dataOut : out std_logic_vector(busWidth-1 downto 0);
-           finished : out STD_LOGIC);
-end component;
-
-component dummyModule is
-    generic(
-        busWidth : integer:=busWidth;
-        regDepth : integer);
-    Port ( clk : in STD_LOGIC;
-           rst_n : in STD_LOGIC;
-           start : in STD_LOGIC;
-           ready: out std_logic;
-           idle : out std_logic;
-           done : out std_logic;
-           
-           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           srcValid : in std_logic;
-           srcReady : out std_logic;
-           
-           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           dstValid : out std_logic;
-           dstReady : in std_logic);
-end component;
-
-component filter11x11_strm is
-port (
-    width : IN STD_LOGIC_VECTOR (31 downto 0);
-    height : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt1 : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt2 : IN STD_LOGIC_VECTOR (31 downto 0);
-    src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
-    dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
-    ap_clk : IN STD_LOGIC;
-    ap_rst_n : IN STD_LOGIC;
-    ap_start : IN STD_LOGIC;
-    src_V_TVALID : IN STD_LOGIC;
-    src_V_TREADY : OUT STD_LOGIC;
-    dst_V_TVALID : OUT STD_LOGIC;
-    dst_V_TREADY : IN STD_LOGIC;
-    ap_done : OUT STD_LOGIC;
-    ap_ready : OUT STD_LOGIC;
-    ap_idle : OUT STD_LOGIC);
-end component;
-
-constant N : integer := 3;
-type muxBitVector is array(0 to N-1) of std_logic;
-type muxDataVector is array(0 to N-1) of std_logic_vector(busWidth-1 downto 0);
-subtype filter11_t is std_logic_vector(busWidth-1 downto 0);
-
-constant moduleIds : muxDataVector :=(
-    0 => x"2cb31e7c",
-    1 => x"f218e0a2",
-    2 => x"9323eb24"
-);
-
-signal imgWidth : std_logic_vector(busWidth-1 downto 0) := std_logic_vector(conv_unsigned(224, 32));
-signal imgHeight : std_logic_vector(busWidth-1 downto 0) := std_logic_vector(conv_unsigned(224, 32));
-
-signal filt1 : filter11_t := x"00000001";
-signal filt2 : filter11_t := x"00000001";
-
-signal muxSrcData : std_logic_vector(busWidth-1 downto 0);
-signal muxSrcValid : std_logic;
-signal muxSrcReady : muxBitVector := (others => '1');
-
-signal muxDstData : muxDataVector;
-signal muxDstValid : muxBitVector := (others => '0');
-signal muxDstReady : std_logic;
-
-signal muxReady : muxBitVector := (others => '1');
-signal muxIdle : muxBitVector := (others => '1');
-signal muxDone : muxBitVector := (others => '1');
-
-signal muxStart : muxBitVector := (others => '0');
-
-
-
-begin
-    dummyBig : dummyModule 
-    generic map (
-        regDepth => 1024
-    ) port map (
-        clk     => clk,
-        rst_n   => rst,
-        
-        srcData => muxSrcData,
-        srcValid=> muxSrcValid,
-        srcReady=> muxSrcReady(0),
-        
-        dstData => muxDstData(0),
-        dstValid => muxDstValid(0),
-        dstReady => muxDstReady,
-        
-        start   => muxStart(0),
-        ready   => muxReady(0),
-        idle    => muxIdle(0),
-        done    => muxDone(0)
-    );
-    
-    dummy : dummyModule 
-    generic map (
-        regDepth => 4
-    ) port map (
-        clk     => clk,
-        rst_n   => rst,
-        
-        srcData => muxSrcData,
-        srcValid=> muxSrcValid,
-        srcReady=> muxSrcReady(1),
-        
-        dstData => muxDstData(1),
-        dstValid => muxDstValid(1),
-        dstReady => muxDstReady,
-        
-        start   => muxStart(1),
-        ready   => muxReady(1),
-        idle    => muxIdle(1),
-        done    => muxDone(1)
-    );
-    f11 : filter11x11_strm port map (
-        ap_clk => clk,
-        ap_rst_n => rst,
-        ap_start => muxStart(2),
-        ap_done => muxDone(2),
-        ap_ready => muxReady(2),
-        ap_idle => muxIdle(2),
-        width => imgWidth,
-        height => imgHeight,
-        
-        src_V_TDATA => muxSrcData,
-        src_V_TVALID => muxSrcValid,
-        src_V_TREADY => muxSrcReady(2),
-        
-        dst_V_TDATA => muxDstData(2),
-        dst_V_TVALID => muxDstValid(2),
-        dst_V_TREADY => muxDstReady,
-        
-        filt1 => filt1,
-        filt2 => filt2
-        
-    );
-
-    process(moduleId, muxSrcReady, muxReady, muxDstData, muxDstValid, muxDone, muxIdle, start)
-        variable i : integer range 0 to N-1;
-    begin
-        i := 0;
-        for k in 0 to N-1 loop
-            if moduleIds(k) = moduleId then
-                i := k;
-            end if;
-        end loop;
-        
-        ready <= muxReady(i);
-        dstData <= muxDstData(i);
-        done <= muxDone(i);
-        idle <= muxIdle(i);
-        dstValid <= muxDstValid(i);
-        srcReady <= muxSrcReady(i);
-        
-        muxStart <= (others => '0');
-        muxStart(i) <= start;
-    end process;
-    
-    muxSrcValid <= srcValid;
-    muxSrcData <= srcData;
-    muxDstReady <= dstReady;
-    
-end Behavioral;

ip_repo_sources/neuron_packed/src/packaging.vhd

@@ -1,346 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 03.06.2019 20:10:59
--- Design Name: 
--- Module Name: packaging - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_arith.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.myPackage.ALL;
-
-entity packaging is
-    generic(
-        busWidth : integer:=32);
-    Port ( clk : in STD_LOGIC;
-           rst : in STD_LOGIC;
-           inputStream : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           inpRdEn : out std_logic;
-           --inputDataCount : in STD_LOGIC_VECTOR (15 downto 0);
-           inputEmpty : in std_logic;
-           
-           outData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           outWrEn : out std_logic;
-           outputFull : in std_logic;
-           errorCode : out STD_LOGIC_VECTOR(3 DOWNTO 0);
-           stateOut : out STD_LOGIC_VECTOR(3 downto 0));
-end packaging;
-
-architecture Behavioral of packaging is
-
-    constant PREAMBLE : std_logic_vector(31 downto 0) := x"E1E4C312";
-    type state_t is (
-        waitPreamble, 
-        checkPreamble,
-        waitDatasetId,
-        getDatasetId,
-        waitModuleId,
-        checkModuleId, 
-        writeHeader,
-        waitProcessing,
-        waitChecksum,
-        readChecksum,
-        writeChecksum);
-    
-
-    component multiplex is
-        generic(
-            busWidth : integer:=busWidth);
-        Port (
-           clk : in STD_LOGIC;
-           start : in STD_LOGIC;
-           ready: out std_logic;
-           rst : in STD_LOGIC;
-           done : out STD_LOGIC;
-           idle : out STD_LOGIC;
-           
-           moduleId : in STD_LOGIC_VECTOR (31 downto 0);
-           
-           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           srcValid : in std_logic;
-           srcReady : out std_logic;
-           
-           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           dstValid : out std_logic;
-           dstReady : in std_logic);
-    end component;
-    
-    component checksum is
-        Port ( clk : in STD_LOGIC;
-           reset : in STD_LOGIC;
-           enable : in STD_LOGIC;
-           dataIn : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           output : out STD_LOGIC_VECTOR (busWidth-1 downto 0));
-    end component;
-    
-    signal state : state_t;
-    signal moduleId : STD_LOGIC_VECTOR (31 downto 0);
-    signal datasetId : STD_LOGIC_VECTOR (31 downto 0);
-    signal inputReadReady : std_logic;
-    signal outputWriteEnable_s : std_logic;
-    signal outputStream_s : STD_LOGIC_VECTOR (busWidth-1 downto 0);
-    signal inputReadEnable : std_logic;
-    signal outputWriteEnable : std_logic;
-    signal outputStream : STD_LOGIC_VECTOR (busWidth-1 downto 0);
-    signal errorCode_s : std_logic_vector(3 downto 0);
-    
-    signal outHeaderCounter : integer range 0 to 3;
-    
-    signal muxSrcData : STD_LOGIC_VECTOR (busWidth-1 downto 0);
-    signal muxSrcValid : std_logic;
-    signal muxSrcReady : std_logic;
-    
-    signal muxDstData : STD_LOGIC_VECTOR (busWidth-1 downto 0);
-    signal muxDstValid : std_logic;
-    signal muxDstReady : std_logic;
-    
-    signal muxStart  : std_logic;
-    signal muxReady  : std_logic;
-    signal muxDone   : std_logic;
-    signal muxIdle   : std_logic;
-    
-    signal muxControlsFIFO : std_logic;
-    
-    signal csReset : std_logic;
-    signal csOutReset : std_logic;
-    signal csSum : STD_LOGIC_VECTOR (busWidth-1 downto 0);
-    
-    signal csOutSum : STD_LOGIC_VECTOR (busWidth-1 downto 0);
-    
-begin
-
-    mux1 : multiplex port map (
-        clk => clk,
-        rst => rst,
-        start => muxStart,
-        ready  => muxReady,
-        done => muxDone,
-        idle => muxIdle,
-        
-        moduleId => moduleId,
-        
-        srcData     => muxSrcData,
-        srcValid    => muxSrcValid,
-        srcReady    => muxSrcReady,
-        
-        dstData     => muxDstData,
-        dstValid    => muxDstValid,
-        dstReady    => muxDstReady
-        
-    );
-    checksum1 : checksum port map (
-        clk => clk,
-        reset => csReset,
-        enable => inputReadEnable,
-        dataIn => inputStream,
-        output => csSum
-    );
-    checksum2 : checksum port map (
-        clk => clk,
-        reset => csOutReset,
-        enable => outputWriteEnable,
-        dataIn => outputStream,
-        output => csOutSum
-    );
-
-    sm : process(rst, clk)
-    
-    begin
-        if(rst = '0') then
-            state <= waitPreamble;
-            inputReadReady <= '0';
-            csReset <= '0';
-            csOutReset <= '0';
-            outHeaderCounter <= 3;
-            muxStart <= '0';
-            muxControlsFIFO <= '0';
-        elsif(rising_edge(clk)) then
-            csReset <= '1';
-            csOutReset <= '1';
-            errorCode_s <= x"0";
-            muxStart <= '0';
-            muxControlsFIFO <= '0';
-
-            outputWriteEnable_s <= '0';
-            outHeaderCounter <= 0;
-            
-            outputStream_s <= (others=>'0');
-        
-            case state is
-                -- wait for header
-                when waitPreamble =>
-                    csReset <= '0';
-                    inputReadReady <= '1';
-                    if(inputEmpty = '1' or outputFull = '1') then
-                        state <= waitPreamble;
-                    else
-                        state <= checkPreamble;
-                    end if;
-                    
-                -- is preamble correct?
-                when checkPreamble =>
-                    if(inputStream = PREAMBLE and inputEmpty = '0') then
-                        state <= getDatasetId;
-                    elsif inputStream = PREAMBLE then
-                        state <= waitDatasetId;
-                    else
-                        state <= waitPreamble;
-                        errorCode_s <= x"1";
-                    end if;
-                when waitDatasetId =>
-                    if inputEmpty = '1' then
-                        errorCode_s <= x"F";
-                        state <= waitDatasetId;
-                    else
-                        state <= getDatasetId;
-                    end if;
-                    
-                when getDatasetId =>
-                    datasetId <= inputStream;
-                    if inputEmpty = '1' then
-                        state <= waitModuleId;
-                    else
-                        state <= checkModuleId;
-                    end if;
-                
-                when waitModuleId =>
-                    if inputEmpty = '1' then
-                        errorCode_s <= x"E";
-                        state <= waitModuleId;
-                    else
-                        state <= checkModuleId;
-                    end if;
-                -- is moduleId known?
-                when checkModuleId =>
-                    inputReadReady <= '0';
-                    if outputFull = '1' then
-                        state <= checkModuleId;
-                        errorCode_s <= x"D";
-                    elsif(inputStream = x"2cb31e7c" or inputStream = x"f218e0a2" or inputStream = x"9323eb24") then
-                        state <= writeHeader;
-                        moduleId <= inputStream;
-                        outputStream_s <= PREAMBLE;
-                        csOutReset <= '0';
-                        outputWriteEnable_s <= '1';
-                        
-                    else
-                        state <= waitPreamble;
-                        errorCode_s <= x"2";
-                    end if;
-                    
-                -- wait for data
-                when writeHeader =>
-                    if outputFull = '1' then
-                        state <= writeHeader;
-                        errorCode_s <= x"C";
-                        outHeaderCounter <= outHeaderCounter;
-                    elsif(outHeaderCounter < 2) then
-                        outputWriteEnable_s <= '1';
-                        case outHeaderCounter is
-                            when 0 =>  outputStream_s <= datasetId;
-                            when others => outputStream_s <= moduleId;
-                        end case;
-                        outHeaderCounter <= outHeaderCounter + 1;
-                        state <= writeHeader;
-                    else
-                        state <= waitProcessing;
-                        muxStart <= '1';
-                        muxControlsFIFO <= '1';
-                    end if;
-
-                when waitProcessing =>
-                    if(muxDone = '0') then
-                        state <= waitProcessing;
-                        muxControlsFIFO <= '1';
-                        errorCode_s <= x"B";
-                        muxStart <= '1';
-                    else
-                        state <= waitChecksum;
-                        inputReadReady <= '1';
-                    end if;
-                
-                when waitChecksum =>
-                    if inputEmpty = '1' then
-                        errorCode_s <= x"A";
-                        state <= waitChecksum;
-                        inputReadReady <= '1';
-                    else
-                        state <= readChecksum;
-                        inputReadReady <= '0';
-                    end if;
-                when readChecksum =>
-                    state <= writeChecksum;
-                    
-                when writeChecksum =>
-                    if outputFull = '0' then
-                        outputWriteEnable_s <= '1';
-                        state <= waitPreamble;
-                    else
-                        state <= writeChecksum;
-                    end if;
-                    
-                    if(unsigned(csSum) = 0) then
-                        outputStream_s <= 0 - unsigned(csOutSum);
-                    else
-                        errorCode_s <= x"3";
-                        outputStream_s <= 1 - unsigned(csOutSum);
-                    end if;
-                
-                when others =>
-                    state <= waitPreamble;
-                    inputReadReady <= '0';
-            end case;
-            
-            if signed(errorCode_s) > 0 and outputFull = '0' then
-                outputWriteEnable_s <= '1';
-                outputStream_s <= x"E330300" & errorCode_s;
-            end if;
-            muxSrcValid <= muxSrcReady and not inputEmpty;
-            
-        end if;
-    end process;
-    
-    muxCtrl : process(muxControlsFIFO, outputWriteEnable_s, inputReadReady, outputStream_s, muxDstValid, muxSrcReady, muxDstData, inputStream, outputFull, inputEmpty)
-    
-    begin
-        if muxControlsFIFO = '0' then
-            outputWriteEnable   <= outputWriteEnable_s;
-            inputReadEnable     <= inputReadReady and not inputEmpty;
-            outputStream        <= outputStream_s;
-            
-            muxSrcData <= (others => 'U');
-            muxDstReady <= '0';
-        else
-            outputWriteEnable   <= muxDstValid and not outputFull;
-            inputReadEnable     <= muxSrcReady and not inputEmpty;
-            outputStream        <= muxDstData;
-            
-            muxSrcData <= inputStream;
-            muxDstReady <= not outputFull;
-        end if;
-        
-    end process;
-    errorCode <= errorCode_s;
-    stateOut <= std_logic_vector(conv_unsigned(state_t'POS(state), 4));
-    
-    outWrEn <= outputWriteEnable;
-    inpRdEn <= inputReadEnable;
-    outData <= outputStream;
-    
-end Behavioral;

ip_repo_sources/neuron_packed/src/shiftIn.vhd

@@ -1,66 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 06/03/2019 01:56:01 PM
--- Design Name: 
--- Module Name: shiftOut - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity shiftIn is
-    generic(
-        inWidth : integer := 8;
-        outWidth : integer := 32);
-    Port ( clk : in STD_LOGIC;
-           ce : in std_logic;
-           sync_reset : in STD_LOGIC;
-           dataIn : in std_logic_vector(inWidth-1 downto 0);
-           dataOut : out std_logic_vector(outWidth-1 downto 0);
-           finished : out STD_LOGIC);
-end shiftIn;
-
-architecture Behavioral of shiftIn is
-    signal dataIndex : integer range 0 to (outWidth / inWidth) := 0;
-    signal dataOut_s : std_logic_vector(outWidth-1 downto 0);
-begin
-
-p_s2p : process(clk, sync_reset, dataIndex)
-begin
-    if(sync_reset = '0') then
-        dataIndex <= 0;
-        finished <= '0';
-        dataOut_s <= (others => '0');
-    elsif(rising_edge(clk)) then
-        if(dataIndex < outWidth/inWidth and ce = '1') then
-            --dataOut_s(outWidth - dataIndex * inWidth - 1 downto outWidth - dataIndex * inWidth - inWidth) <= dataIn;
-            dataOut_s <= dataOut_s(outWidth-1 - inWidth downto 0) & dataIn;
-            dataIndex <= dataIndex + 1;
-        else
-            dataIndex <= dataIndex;
-            dataOut_s <= dataOut_s;
-        end if;
-    end if;
-    if(dataIndex < outWidth/inWidth) then
-        finished <= '0';
-    else
-        finished <= '1';
-    end if;
-end process;
-
-dataOut <= dataOut_s;
-end Behavioral;

ip_repo_sources/neuron_packed/src/shiftOut.vhd

@@ -1,72 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 06/03/2019 01:56:01 PM
--- Design Name: 
--- Module Name: shiftOut - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity shiftOut is
-    generic(
-        inWidth : integer := 32*4;
-        outWidth : integer := 32);
-    Port ( clk : in STD_LOGIC;
-           ce : in std_logic;
-           sync_reset : in STD_LOGIC;
-           dataIn : in std_logic_vector(inWidth-1 downto 0);
-           dataOut : out std_logic_vector(outWidth-1 downto 0);
-           valid : out std_logic;
-           finished : out STD_LOGIC);
-end shiftOut;
-
-architecture Behavioral of shiftOut is
-    signal dataIndex : integer range -1 to (inWidth / outWidth)-1 := 0;
-begin
-
-p_s2p : process(clk, sync_reset)
-begin
-    if(sync_reset = '0') then
-        dataIndex <= -1;
-        finished <= '0';
-        valid <= '0';
-    elsif(rising_edge(clk)) then
-        if dataIndex < inWidth/outWidth-1 and ce='0' then
-            finished <= '0';
-            dataIndex <= dataIndex;
-            valid <= '0';
-        elsif(dataIndex < inWidth/outWidth-1) then
-            finished <= '0';
-            dataIndex <= dataIndex + 1;
-            valid <= '1';
-        else
-            finished <= '1';
-            dataIndex <= dataIndex;
-            valid <= '0';
-        end if;
-    end if;
-end process;
-
-process(dataIn, dataIndex) begin
-    if dataIndex >= 0 then
-        dataOut <= dataIn(inWidth - dataIndex * outWidth - 1 downto inWidth - dataIndex * outWidth - outWidth);
-    else
-        dataOut <= (others => 'U');
-    end if;
-end process;
-end Behavioral;

ip_repo_sources/neuron_packed/xgui/packaging_v1_0.tcl

@@ -1,25 +0,0 @@
-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
-  ipgui::add_param $IPINST -name "Component_Name"
-  #Adding Page
-  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
-  ipgui::add_param $IPINST -name "busWidth" -parent ${Page_0}
-
-
-}
-
-proc update_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
-	# Procedure called to update busWidth when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
-	# Procedure called to validate busWidth
-	return true
-}
-
-
-proc update_MODELPARAM_VALUE.busWidth { MODELPARAM_VALUE.busWidth PARAM_VALUE.busWidth } {
-	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.busWidth}] ${MODELPARAM_VALUE.busWidth}
-}
-

ip_repo_sources/neuron_packed/xgui/packaging_v2_0.tcl

@@ -1,25 +0,0 @@
-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
-  ipgui::add_param $IPINST -name "Component_Name"
-  #Adding Page
-  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
-  ipgui::add_param $IPINST -name "busWidth" -parent ${Page_0}
-
-
-}
-
-proc update_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
-	# Procedure called to update busWidth when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
-	# Procedure called to validate busWidth
-	return true
-}
-
-
-proc update_MODELPARAM_VALUE.busWidth { MODELPARAM_VALUE.busWidth PARAM_VALUE.busWidth } {
-	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.busWidth}] ${MODELPARAM_VALUE.busWidth}
-}
-

ip_repo_sources/packaging/component.xml

@@ -1,650 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-  <spirit:vendor>user.org</spirit:vendor>
-  <spirit:library>user</spirit:library>
-  <spirit:name>packaging</spirit:name>
-  <spirit:version>3.0</spirit:version>
-  <spirit:busInterfaces>
-    <spirit:busInterface>
-      <spirit:name>rst</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RST</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>rst</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>clk</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>CLK</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>clk</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>ASSOCIATED_RESET</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">rst</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>fifo_read</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read_rtl" spirit:version="1.0"/>
-      <spirit:master/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RD_DATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>inputStream</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RD_EN</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>inpRdEn</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>EMPTY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>inputEmpty</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>fifo_write</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write_rtl" spirit:version="1.0"/>
-      <spirit:master/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WR_DATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>outData</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WR_EN</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>outWrEn</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>FULL</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>outputFull</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-    </spirit:busInterface>
-  </spirit:busInterfaces>
-  <spirit:model>
-    <spirit:views>
-      <spirit:view>
-        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
-        <spirit:displayName>Synthesis</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
-        <spirit:language>VHDL</spirit:language>
-        <spirit:modelName>packaging</spirit:modelName>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>80fccf26</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
-        <spirit:displayName>Simulation</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
-        <spirit:language>VHDL</spirit:language>
-        <spirit:modelName>packaging</spirit:modelName>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>80fccf26</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_testbench</spirit:name>
-        <spirit:displayName>Test Bench</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:simulation.testbench</spirit:envIdentifier>
-        <spirit:modelName>tb</spirit:modelName>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_testbench_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>88e53ccc</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_xpgui</spirit:name>
-        <spirit:displayName>UI Layout</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>b2335c60</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-    </spirit:views>
-    <spirit:ports>
-      <spirit:port>
-        <spirit:name>clk</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>rst</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>inputStream</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.busWidth&apos;)) - 1)">31</spirit:left>
-            <spirit:right spirit:format="long">0</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>inpRdEn</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>inputEmpty</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>outData</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.busWidth&apos;)) - 1)">31</spirit:left>
-            <spirit:right spirit:format="long">0</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>outWrEn</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>outputFull</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>errorCode</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:vector>
-            <spirit:left spirit:format="long">3</spirit:left>
-            <spirit:right spirit:format="long">0</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>stateOut</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:vector>
-            <spirit:left spirit:format="long">3</spirit:left>
-            <spirit:right spirit:format="long">0</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-    </spirit:ports>
-    <spirit:modelParameters>
-      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
-        <spirit:name>busWidth</spirit:name>
-        <spirit:displayName>Buswidth</spirit:displayName>
-        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.busWidth">32</spirit:value>
-      </spirit:modelParameter>
-    </spirit:modelParameters>
-  </spirit:model>
-  <spirit:fileSets>
-    <spirit:fileSet>
-      <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
-      <spirit:file>
-        <spirit:name>src/Block_proc.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/Loop_Border_proc.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/Loop_Border_proc_borderbuf.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/Loop_HConvH_proc6.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/Loop_VConvH_proc.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/Loop_VConvH_proc_linebuf_0.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/globals.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/checksum.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/conv2d_5x5_224p.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/dummyModule.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/fifo_w32_d2_A.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/fifo_w32_d3_A.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/filter11x11_strm.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/filter11x11_strm_ent.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/kernel_5x5.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/multiplex.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/ram.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/shiftIn.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/start_for_Block_proc_U0.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/start_for_Loop_Border_proc_U0.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/start_for_Loop_VConvH_proc_U0.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/packaging.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_c867fa61</spirit:userFileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-    </spirit:fileSet>
-    <spirit:fileSet>
-      <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
-      <spirit:file>
-        <spirit:name>src/Block_proc.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/Loop_Border_proc.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/Loop_Border_proc_borderbuf.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/Loop_HConvH_proc6.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/Loop_VConvH_proc.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/Loop_VConvH_proc_linebuf_0.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/globals.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>src/checksum.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
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ip_repo_sources/packaging/src/Block_proc.vhd

@@ -1,321 +0,0 @@
--- ==============================================================
--- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
--- Version: 2018.3
--- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--- 
--- ===========================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity Block_proc is
-port (
-    ap_clk : IN STD_LOGIC;
-    ap_rst : IN STD_LOGIC;
-    ap_start : IN STD_LOGIC;
-    start_full_n : IN STD_LOGIC;
-    ap_done : OUT STD_LOGIC;
-    ap_continue : IN STD_LOGIC;
-    ap_idle : OUT STD_LOGIC;
-    ap_ready : OUT STD_LOGIC;
-    start_out : OUT STD_LOGIC;
-    start_write : OUT STD_LOGIC;
-    width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    width_empty_n : IN STD_LOGIC;
-    width_read : OUT STD_LOGIC;
-    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    height_empty_n : IN STD_LOGIC;
-    height_read : OUT STD_LOGIC;
-    width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    width_out_full_n : IN STD_LOGIC;
-    width_out_write : OUT STD_LOGIC;
-    height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    height_out_full_n : IN STD_LOGIC;
-    height_out_write : OUT STD_LOGIC;
-    vconv_xlim_out_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    vconv_xlim_out_out_full_n : IN STD_LOGIC;
-    vconv_xlim_out_out_write : OUT STD_LOGIC );
-end;
-
-
-architecture behav of Block_proc is 
-    constant ap_const_logic_1 : STD_LOGIC := '1';
-    constant ap_const_logic_0 : STD_LOGIC := '0';
-    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
-    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
-    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
-    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
-    constant ap_const_lv32_FFFFFFF6 : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111110110";
-    constant ap_const_boolean_1 : BOOLEAN := true;
-
-    signal real_start : STD_LOGIC;
-    signal start_once_reg : STD_LOGIC := '0';
-    signal ap_done_reg : STD_LOGIC := '0';
-    signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
-    attribute fsm_encoding : string;
-    attribute fsm_encoding of ap_CS_fsm : signal is "none";
-    signal ap_CS_fsm_state1 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
-    signal internal_ap_ready : STD_LOGIC;
-    signal width_blk_n : STD_LOGIC;
-    signal height_blk_n : STD_LOGIC;
-    signal width_out_blk_n : STD_LOGIC;
-    signal ap_CS_fsm_state2 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
-    signal height_out_blk_n : STD_LOGIC;
-    signal vconv_xlim_out_out_blk_n : STD_LOGIC;
-    signal width_read_reg_69 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_state1 : BOOLEAN;
-    signal height_read_reg_75 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_state2 : BOOLEAN;
-    signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
-
-
-begin
-
-
-
-
-    ap_CS_fsm_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_CS_fsm <= ap_ST_fsm_state1;
-            else
-                ap_CS_fsm <= ap_NS_fsm;
-            end if;
-        end if;
-    end process;
-
-
-    ap_done_reg_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_done_reg <= ap_const_logic_0;
-            else
-                if ((ap_continue = ap_const_logic_1)) then 
-                    ap_done_reg <= ap_const_logic_0;
-                elsif ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
-                    ap_done_reg <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    start_once_reg_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                start_once_reg <= ap_const_logic_0;
-            else
-                if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then 
-                    start_once_reg <= ap_const_logic_1;
-                elsif ((internal_ap_ready = ap_const_logic_1)) then 
-                    start_once_reg <= ap_const_logic_0;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                height_read_reg_75 <= height_dout;
-                width_read_reg_69 <= width_dout;
-            end if;
-        end if;
-    end process;
-
-    ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, width_empty_n, height_empty_n, width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
-    begin
-        case ap_CS_fsm is
-            when ap_ST_fsm_state1 => 
-                if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                    ap_NS_fsm <= ap_ST_fsm_state2;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_state1;
-                end if;
-            when ap_ST_fsm_state2 => 
-                if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
-                    ap_NS_fsm <= ap_ST_fsm_state1;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_state2;
-                end if;
-            when others =>  
-                ap_NS_fsm <= "XX";
-        end case;
-    end process;
-    ap_CS_fsm_state1 <= ap_CS_fsm(0);
-    ap_CS_fsm_state2 <= ap_CS_fsm(1);
-
-    ap_block_state1_assign_proc : process(real_start, ap_done_reg, width_empty_n, height_empty_n)
-    begin
-                ap_block_state1 <= ((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
-    end process;
-
-
-    ap_block_state2_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n)
-    begin
-                ap_block_state2 <= ((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0));
-    end process;
-
-
-    ap_done_assign_proc : process(ap_done_reg, width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
-            ap_done <= ap_const_logic_1;
-        else 
-            ap_done <= ap_done_reg;
-        end if; 
-    end process;
-
-
-    ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
-    begin
-        if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            ap_idle <= ap_const_logic_1;
-        else 
-            ap_idle <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    ap_ready <= internal_ap_ready;
-
-    height_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_blk_n <= height_empty_n;
-        else 
-            height_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    height_out_blk_n_assign_proc : process(height_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-            height_out_blk_n <= height_out_full_n;
-        else 
-            height_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    height_out_din <= height_read_reg_75;
-
-    height_out_write_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
-            height_out_write <= ap_const_logic_1;
-        else 
-            height_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    height_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_read <= ap_const_logic_1;
-        else 
-            height_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    internal_ap_ready_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
-            internal_ap_ready <= ap_const_logic_1;
-        else 
-            internal_ap_ready <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
-    begin
-        if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then 
-            real_start <= ap_const_logic_0;
-        else 
-            real_start <= ap_start;
-        end if; 
-    end process;
-
-    start_out <= real_start;
-
-    start_write_assign_proc : process(real_start, start_once_reg)
-    begin
-        if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then 
-            start_write <= ap_const_logic_1;
-        else 
-            start_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    vconv_xlim_out_out_blk_n_assign_proc : process(vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-            vconv_xlim_out_out_blk_n <= vconv_xlim_out_out_full_n;
-        else 
-            vconv_xlim_out_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    vconv_xlim_out_out_din <= std_logic_vector(unsigned(width_read_reg_69) + unsigned(ap_const_lv32_FFFFFFF6));
-
-    vconv_xlim_out_out_write_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
-            vconv_xlim_out_out_write <= ap_const_logic_1;
-        else 
-            vconv_xlim_out_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    width_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_blk_n <= width_empty_n;
-        else 
-            width_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    width_out_blk_n_assign_proc : process(width_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-            width_out_blk_n <= width_out_full_n;
-        else 
-            width_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    width_out_din <= width_read_reg_69;
-
-    width_out_write_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
-            width_out_write <= ap_const_logic_1;
-        else 
-            width_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    width_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_read <= ap_const_logic_1;
-        else 
-            width_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-end behav;

ip_repo_sources/packaging/src/Loop_Border_proc.vhd

@@ -1,896 +0,0 @@
--- ==============================================================
--- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
--- Version: 2018.3
--- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--- 
--- ===========================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity Loop_Border_proc is
-port (
-    ap_clk : IN STD_LOGIC;
-    ap_rst : IN STD_LOGIC;
-    ap_start : IN STD_LOGIC;
-    ap_done : OUT STD_LOGIC;
-    ap_continue : IN STD_LOGIC;
-    ap_idle : OUT STD_LOGIC;
-    ap_ready : OUT STD_LOGIC;
-    width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    width_empty_n : IN STD_LOGIC;
-    width_read : OUT STD_LOGIC;
-    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    height_empty_n : IN STD_LOGIC;
-    height_read : OUT STD_LOGIC;
-    dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
-    dst_V_TVALID : OUT STD_LOGIC;
-    dst_V_TREADY : IN STD_LOGIC;
-    vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    vconv_xlim_loc_empty_n : IN STD_LOGIC;
-    vconv_xlim_loc_read : OUT STD_LOGIC;
-    vconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    vconv_V_empty_n : IN STD_LOGIC;
-    vconv_V_read : OUT STD_LOGIC );
-end;
-
-
-architecture behav of Loop_Border_proc is 
-    constant ap_const_logic_1 : STD_LOGIC := '1';
-    constant ap_const_logic_0 : STD_LOGIC := '0';
-    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
-    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
-    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
-    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
-    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
-    constant ap_const_boolean_1 : BOOLEAN := true;
-    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
-    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
-    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
-    constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
-    constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
-    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
-    constant ap_const_boolean_0 : BOOLEAN := false;
-    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
-    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
-    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
-    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
-    constant ap_const_lv32_FFFFFFF5 : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111110101";
-    constant ap_const_lv32_FFFFFFFA : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111010";
-    constant ap_const_lv32_FFFFFFFB : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111011";
-    constant ap_const_lv10_5 : STD_LOGIC_VECTOR (9 downto 0) := "0000000101";
-    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
-    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
-    constant ap_const_lv10_6 : STD_LOGIC_VECTOR (9 downto 0) := "0000000110";
-    constant ap_const_lv10_3FB : STD_LOGIC_VECTOR (9 downto 0) := "1111111011";
-    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
-
-    signal ap_done_reg : STD_LOGIC := '0';
-    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
-    attribute fsm_encoding : string;
-    attribute fsm_encoding of ap_CS_fsm : signal is "none";
-    signal ap_CS_fsm_state1 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
-    signal dst_V_1_data_out : STD_LOGIC_VECTOR (31 downto 0);
-    signal dst_V_1_vld_in : STD_LOGIC;
-    signal dst_V_1_vld_out : STD_LOGIC;
-    signal dst_V_1_ack_in : STD_LOGIC;
-    signal dst_V_1_ack_out : STD_LOGIC;
-    signal dst_V_1_payload_A : STD_LOGIC_VECTOR (31 downto 0);
-    signal dst_V_1_payload_B : STD_LOGIC_VECTOR (31 downto 0);
-    signal dst_V_1_sel_rd : STD_LOGIC := '0';
-    signal dst_V_1_sel_wr : STD_LOGIC := '0';
-    signal dst_V_1_sel : STD_LOGIC;
-    signal dst_V_1_load_A : STD_LOGIC;
-    signal dst_V_1_load_B : STD_LOGIC;
-    signal dst_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
-    signal dst_V_1_state_cmp_full : STD_LOGIC;
-    signal width_blk_n : STD_LOGIC;
-    signal height_blk_n : STD_LOGIC;
-    signal dst_V_TDATA_blk_n : STD_LOGIC;
-    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
-    signal ap_block_pp0_stage0 : BOOLEAN;
-    signal exitcond_flatten_reg_499 : STD_LOGIC_VECTOR (0 downto 0);
-    signal exitcond_flatten_reg_499_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
-    signal exitcond_flatten_reg_499_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal vconv_xlim_loc_blk_n : STD_LOGIC;
-    signal vconv_V_blk_n : STD_LOGIC;
-    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
-    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
-    signal brmerge_mid2_reg_516 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_24_i_i_reg_525 : STD_LOGIC_VECTOR (0 downto 0);
-    signal indvar_flatten_reg_145 : STD_LOGIC_VECTOR (63 downto 0);
-    signal i6_0_i_i_i_reg_156 : STD_LOGIC_VECTOR (9 downto 0);
-    signal j_0_i_i_i_reg_167 : STD_LOGIC_VECTOR (9 downto 0);
-    signal width_read_reg_459 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_state1 : BOOLEAN;
-    signal height_read_reg_467 : STD_LOGIC_VECTOR (31 downto 0);
-    signal vconv_xlim_loc_read_reg_473 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_9_i_i_fu_178_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_9_i_i_reg_478 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_CS_fsm_state2 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
-    signal tmp_i_i_fu_183_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_i_i_reg_483 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_7_i_i_fu_188_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_7_i_i_reg_488 : STD_LOGIC_VECTOR (31 downto 0);
-    signal bound_fu_199_p2 : STD_LOGIC_VECTOR (63 downto 0);
-    signal bound_reg_494 : STD_LOGIC_VECTOR (63 downto 0);
-    signal exitcond_flatten_fu_247_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
-    signal ap_predicate_op59_read_state4 : BOOLEAN;
-    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
-    signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
-    signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
-    signal ap_block_state6_io : BOOLEAN;
-    signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
-    signal ap_block_state7_io : BOOLEAN;
-    signal ap_block_pp0_stage0_11001 : BOOLEAN;
-    signal exitcond_flatten_reg_499_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal indvar_flatten_next_fu_252_p2 : STD_LOGIC_VECTOR (63 downto 0);
-    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
-    signal j_0_i_i_i_mid2_fu_268_p3 : STD_LOGIC_VECTOR (9 downto 0);
-    signal j_0_i_i_i_mid2_reg_508 : STD_LOGIC_VECTOR (9 downto 0);
-    signal brmerge_mid2_fu_305_p3 : STD_LOGIC_VECTOR (0 downto 0);
-    signal brmerge_mid2_reg_516_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal i6_0_i_i_i_mid2_fu_317_p3 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp_24_i_i_fu_325_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_28_i_i_fu_330_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_28_i_i_reg_529 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_28_i_i_reg_529_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_30_i_i_fu_335_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_30_i_i_reg_534 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_30_i_i_reg_534_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_30_i_i_reg_534_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal j_fu_340_p2 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp_27_i_i_fu_355_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_27_i_i_reg_544 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_29_i_i_fu_360_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_29_i_i_reg_549 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_29_i_i_reg_549_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal borderbuf_q1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal pix_out_7_reg_560 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
-    signal pix_out_8_fu_431_p3 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_pp0_stage0_subdone : BOOLEAN;
-    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
-    signal borderbuf_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal borderbuf_ce0 : STD_LOGIC;
-    signal borderbuf_we0 : STD_LOGIC;
-    signal borderbuf_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal borderbuf_ce1 : STD_LOGIC;
-    signal tmp_26_i_i_fu_346_p1 : STD_LOGIC_VECTOR (63 downto 0);
-    signal tmp_32_i_i_fu_370_p1 : STD_LOGIC_VECTOR (63 downto 0);
-    signal r_edge_pix_fu_74 : STD_LOGIC_VECTOR (31 downto 0);
-    signal pix_out_fu_78 : STD_LOGIC_VECTOR (31 downto 0);
-    signal l_edge_pix_fu_391_p3 : STD_LOGIC_VECTOR (31 downto 0);
-    signal pix_out_1_fu_82 : STD_LOGIC_VECTOR (31 downto 0);
-    signal pix_in_2_l_edge_pix_s_fu_384_p3 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_pp0_stage0_01001 : BOOLEAN;
-    signal bound_fu_199_p0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal bound_fu_199_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal i6_0_i_cast_i_i_mid1_fu_205_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal notrhs_fu_221_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal notlhs_fu_215_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_17_i_i_fu_209_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal brmerge_i_i_i_not_fu_226_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal j_0_i_cast_i_i_fu_238_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal i_fu_258_p2 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp_22_i_i_fu_242_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal i6_0_i_cast_i_i_fu_264_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal notrhs_mid1_fu_288_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal notlhs_mid1_fu_282_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_17_i_i_mid1_fu_276_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal brmerge_i_i_i_not_mi_fu_293_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal brmerge_fu_232_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal brmerge_mid1_fu_299_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal j_0_i_cast_i_i_mid2_s_fu_313_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_31_i_i_fu_365_p2 : STD_LOGIC_VECTOR (9 downto 0);
-    signal sel_tmp_fu_414_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal sel_tmp1_fu_419_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal pix_out_3_fu_424_p3 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_CS_fsm_state8 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
-    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
-    signal ap_idle_pp0 : STD_LOGIC;
-    signal ap_enable_pp0 : STD_LOGIC;
-    signal bound_fu_199_p00 : STD_LOGIC_VECTOR (63 downto 0);
-    signal bound_fu_199_p10 : STD_LOGIC_VECTOR (63 downto 0);
-
-    component Loop_Border_proc_borderbuf IS
-    generic (
-        DataWidth : INTEGER;
-        AddressRange : INTEGER;
-        AddressWidth : INTEGER );
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        address0 : IN STD_LOGIC_VECTOR (9 downto 0);
-        ce0 : IN STD_LOGIC;
-        we0 : IN STD_LOGIC;
-        d0 : IN STD_LOGIC_VECTOR (31 downto 0);
-        address1 : IN STD_LOGIC_VECTOR (9 downto 0);
-        ce1 : IN STD_LOGIC;
-        q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
-    end component;
-
-
-
-begin
-    borderbuf_U : component Loop_Border_proc_borderbuf
-    generic map (
-        DataWidth => 32,
-        AddressRange => 662,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => borderbuf_address0,
-        ce0 => borderbuf_ce0,
-        we0 => borderbuf_we0,
-        d0 => vconv_V_dout,
-        address1 => borderbuf_address1,
-        ce1 => borderbuf_ce1,
-        q1 => borderbuf_q1);
-
-
-
-
-
-    ap_CS_fsm_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_CS_fsm <= ap_ST_fsm_state1;
-            else
-                ap_CS_fsm <= ap_NS_fsm;
-            end if;
-        end if;
-    end process;
-
-
-    ap_done_reg_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_done_reg <= ap_const_logic_0;
-            else
-                if ((ap_continue = ap_const_logic_1)) then 
-                    ap_done_reg <= ap_const_logic_0;
-                elsif (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
-                    ap_done_reg <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
-            else
-                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
-                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then 
-                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
-                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
-                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
-                    end if;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                    ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    dst_V_1_sel_rd_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                dst_V_1_sel_rd <= ap_const_logic_0;
-            else
-                if (((dst_V_1_ack_out = ap_const_logic_1) and (dst_V_1_vld_out = ap_const_logic_1))) then 
-                                        dst_V_1_sel_rd <= not(dst_V_1_sel_rd);
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    dst_V_1_sel_wr_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                dst_V_1_sel_wr <= ap_const_logic_0;
-            else
-                if (((dst_V_1_ack_in = ap_const_logic_1) and (dst_V_1_vld_in = ap_const_logic_1))) then 
-                                        dst_V_1_sel_wr <= not(dst_V_1_sel_wr);
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    dst_V_1_state_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                dst_V_1_state <= ap_const_lv2_0;
-            else
-                if ((((dst_V_1_state = ap_const_lv2_2) and (dst_V_1_vld_in = ap_const_logic_0)) or ((dst_V_1_state = ap_const_lv2_3) and (dst_V_1_vld_in = ap_const_logic_0) and (dst_V_1_ack_out = ap_const_logic_1)))) then 
-                    dst_V_1_state <= ap_const_lv2_2;
-                elsif ((((dst_V_1_state = ap_const_lv2_1) and (dst_V_1_ack_out = ap_const_logic_0)) or ((dst_V_1_state = ap_const_lv2_3) and (dst_V_1_ack_out = ap_const_logic_0) and (dst_V_1_vld_in = ap_const_logic_1)))) then 
-                    dst_V_1_state <= ap_const_lv2_1;
-                elsif (((not(((dst_V_1_vld_in = ap_const_logic_0) and (dst_V_1_ack_out = ap_const_logic_1))) and not(((dst_V_1_ack_out = ap_const_logic_0) and (dst_V_1_vld_in = ap_const_logic_1))) and (dst_V_1_state = ap_const_lv2_3)) or ((dst_V_1_state = ap_const_lv2_1) and (dst_V_1_ack_out = ap_const_logic_1)) or ((dst_V_1_state = ap_const_lv2_2) and (dst_V_1_vld_in = ap_const_logic_1)))) then 
-                    dst_V_1_state <= ap_const_lv2_3;
-                else 
-                    dst_V_1_state <= ap_const_lv2_2;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    i6_0_i_i_i_reg_156_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-                i6_0_i_i_i_reg_156 <= i6_0_i_i_i_mid2_fu_317_p3;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                i6_0_i_i_i_reg_156 <= ap_const_lv10_0;
-            end if; 
-        end if;
-    end process;
-
-    indvar_flatten_reg_145_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-                indvar_flatten_reg_145 <= indvar_flatten_next_fu_252_p2;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                indvar_flatten_reg_145 <= ap_const_lv64_0;
-            end if; 
-        end if;
-    end process;
-
-    j_0_i_i_i_reg_167_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-                j_0_i_i_i_reg_167 <= j_fu_340_p2;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                j_0_i_i_i_reg_167 <= ap_const_lv10_0;
-            end if; 
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
-                bound_reg_494 <= bound_fu_199_p2;
-                tmp_7_i_i_reg_488 <= tmp_7_i_i_fu_188_p2;
-                tmp_9_i_i_reg_478 <= tmp_9_i_i_fu_178_p2;
-                tmp_i_i_reg_483 <= tmp_i_i_fu_183_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
-                brmerge_mid2_reg_516 <= brmerge_mid2_fu_305_p3;
-                j_0_i_i_i_mid2_reg_508 <= j_0_i_i_i_mid2_fu_268_p3;
-                tmp_30_i_i_reg_534 <= tmp_30_i_i_fu_335_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
-                brmerge_mid2_reg_516_pp0_iter1_reg <= brmerge_mid2_reg_516;
-                exitcond_flatten_reg_499 <= exitcond_flatten_fu_247_p2;
-                exitcond_flatten_reg_499_pp0_iter1_reg <= exitcond_flatten_reg_499;
-                tmp_28_i_i_reg_529_pp0_iter1_reg <= tmp_28_i_i_reg_529;
-                tmp_30_i_i_reg_534_pp0_iter1_reg <= tmp_30_i_i_reg_534;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((dst_V_1_load_A = ap_const_logic_1)) then
-                dst_V_1_payload_A <= pix_out_8_fu_431_p3;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((dst_V_1_load_B = ap_const_logic_1)) then
-                dst_V_1_payload_B <= pix_out_8_fu_431_p3;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
-                exitcond_flatten_reg_499_pp0_iter2_reg <= exitcond_flatten_reg_499_pp0_iter1_reg;
-                exitcond_flatten_reg_499_pp0_iter3_reg <= exitcond_flatten_reg_499_pp0_iter2_reg;
-                tmp_29_i_i_reg_549_pp0_iter2_reg <= tmp_29_i_i_reg_549;
-                tmp_30_i_i_reg_534_pp0_iter2_reg <= tmp_30_i_i_reg_534_pp0_iter1_reg;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                height_read_reg_467 <= height_dout;
-                vconv_xlim_loc_read_reg_473 <= vconv_xlim_loc_dout;
-                width_read_reg_459 <= width_dout;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((brmerge_mid2_reg_516_pp0_iter1_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
-                pix_out_1_fu_82 <= pix_in_2_l_edge_pix_s_fu_384_p3;
-                pix_out_fu_78 <= l_edge_pix_fu_391_p3;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_reg_499_pp0_iter1_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
-                pix_out_7_reg_560 <= borderbuf_q1;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
-                r_edge_pix_fu_74 <= vconv_V_dout;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((brmerge_mid2_fu_305_p3 = ap_const_lv1_1) and (exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
-                tmp_24_i_i_reg_525 <= tmp_24_i_i_fu_325_p2;
-                tmp_28_i_i_reg_529 <= tmp_28_i_i_fu_330_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
-                tmp_27_i_i_reg_544 <= tmp_27_i_i_fu_355_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_reg_499 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
-                tmp_29_i_i_reg_549 <= tmp_29_i_i_fu_360_p2;
-            end if;
-        end if;
-    end process;
-
-    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, width_empty_n, height_empty_n, dst_V_1_ack_in, vconv_xlim_loc_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, exitcond_flatten_fu_247_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_CS_fsm_state8)
-    begin
-        case ap_CS_fsm is
-            when ap_ST_fsm_state1 => 
-                if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                    ap_NS_fsm <= ap_ST_fsm_state2;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_state1;
-                end if;
-            when ap_ST_fsm_state2 => 
-                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-            when ap_ST_fsm_pp0_stage0 => 
-                if ((not(((exitcond_flatten_fu_247_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) and not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0))))) then
-                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-                elsif ((((exitcond_flatten_fu_247_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0)))) then
-                    ap_NS_fsm <= ap_ST_fsm_state8;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-                end if;
-            when ap_ST_fsm_state8 => 
-                if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then
-                    ap_NS_fsm <= ap_ST_fsm_state1;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_state8;
-                end if;
-            when others =>  
-                ap_NS_fsm <= "XXXX";
-        end case;
-    end process;
-    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
-    ap_CS_fsm_state1 <= ap_CS_fsm(0);
-    ap_CS_fsm_state2 <= ap_CS_fsm(1);
-    ap_CS_fsm_state8 <= ap_CS_fsm(3);
-        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_pp0_stage0_01001_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4)
-    begin
-                ap_block_pp0_stage0_01001 <= ((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
-    end process;
-
-
-    ap_block_pp0_stage0_11001_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_state6_io, ap_block_state7_io)
-    begin
-                ap_block_pp0_stage0_11001 <= (((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state7_io) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state6_io) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)));
-    end process;
-
-
-    ap_block_pp0_stage0_subdone_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_state6_io, ap_block_state7_io)
-    begin
-                ap_block_pp0_stage0_subdone <= (((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state7_io) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state6_io) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)));
-    end process;
-
-
-    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
-    begin
-                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
-    end process;
-
-        ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_state4_pp0_stage0_iter1_assign_proc : process(vconv_V_empty_n, ap_predicate_op59_read_state4)
-    begin
-                ap_block_state4_pp0_stage0_iter1 <= ((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1));
-    end process;
-
-        ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_state6_io_assign_proc : process(dst_V_1_ack_in, exitcond_flatten_reg_499_pp0_iter2_reg)
-    begin
-                ap_block_state6_io <= ((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (dst_V_1_ack_in = ap_const_logic_0));
-    end process;
-
-        ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_state7_io_assign_proc : process(dst_V_1_ack_in, exitcond_flatten_reg_499_pp0_iter3_reg)
-    begin
-                ap_block_state7_io <= ((exitcond_flatten_reg_499_pp0_iter3_reg = ap_const_lv1_0) and (dst_V_1_ack_in = ap_const_logic_0));
-    end process;
-
-        ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_flatten_fu_247_p2)
-    begin
-        if ((exitcond_flatten_fu_247_p2 = ap_const_lv1_1)) then 
-            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
-        else 
-            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_done_assign_proc : process(ap_done_reg, dst_V_1_ack_in, ap_CS_fsm_state8)
-    begin
-        if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
-            ap_done <= ap_const_logic_1;
-        else 
-            ap_done <= ap_done_reg;
-        end if; 
-    end process;
-
-    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
-
-    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
-    begin
-        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            ap_idle <= ap_const_logic_1;
-        else 
-            ap_idle <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2)
-    begin
-        if (((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0))) then 
-            ap_idle_pp0 <= ap_const_logic_1;
-        else 
-            ap_idle_pp0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_predicate_op59_read_state4_assign_proc : process(brmerge_mid2_reg_516, tmp_24_i_i_reg_525)
-    begin
-                ap_predicate_op59_read_state4 <= ((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1));
-    end process;
-
-
-    ap_ready_assign_proc : process(dst_V_1_ack_in, ap_CS_fsm_state8)
-    begin
-        if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
-            ap_ready <= ap_const_logic_1;
-        else 
-            ap_ready <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    borderbuf_address0 <= tmp_26_i_i_fu_346_p1(10 - 1 downto 0);
-    borderbuf_address1 <= tmp_32_i_i_fu_370_p1(10 - 1 downto 0);
-
-    borderbuf_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            borderbuf_ce0 <= ap_const_logic_1;
-        else 
-            borderbuf_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    borderbuf_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            borderbuf_ce1 <= ap_const_logic_1;
-        else 
-            borderbuf_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    borderbuf_we0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, brmerge_mid2_reg_516, tmp_24_i_i_reg_525, ap_block_pp0_stage0_11001)
-    begin
-        if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            borderbuf_we0 <= ap_const_logic_1;
-        else 
-            borderbuf_we0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    bound_fu_199_p0 <= bound_fu_199_p00(32 - 1 downto 0);
-    bound_fu_199_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(width_read_reg_459),64));
-    bound_fu_199_p1 <= bound_fu_199_p10(32 - 1 downto 0);
-    bound_fu_199_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(height_read_reg_467),64));
-    bound_fu_199_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_199_p0) * unsigned(bound_fu_199_p1), 64));
-    brmerge_fu_232_p2 <= (tmp_17_i_i_fu_209_p2 or brmerge_i_i_i_not_fu_226_p2);
-    brmerge_i_i_i_not_fu_226_p2 <= (notrhs_fu_221_p2 and notlhs_fu_215_p2);
-    brmerge_i_i_i_not_mi_fu_293_p2 <= (notrhs_mid1_fu_288_p2 and notlhs_mid1_fu_282_p2);
-    brmerge_mid1_fu_299_p2 <= (tmp_17_i_i_mid1_fu_276_p2 or brmerge_i_i_i_not_mi_fu_293_p2);
-    brmerge_mid2_fu_305_p3 <= 
-        brmerge_fu_232_p2 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
-        brmerge_mid1_fu_299_p2;
-    dst_V_1_ack_in <= dst_V_1_state(1);
-    dst_V_1_ack_out <= dst_V_TREADY;
-
-    dst_V_1_data_out_assign_proc : process(dst_V_1_payload_A, dst_V_1_payload_B, dst_V_1_sel)
-    begin
-        if ((dst_V_1_sel = ap_const_logic_1)) then 
-            dst_V_1_data_out <= dst_V_1_payload_B;
-        else 
-            dst_V_1_data_out <= dst_V_1_payload_A;
-        end if; 
-    end process;
-
-    dst_V_1_load_A <= (not(dst_V_1_sel_wr) and dst_V_1_state_cmp_full);
-    dst_V_1_load_B <= (dst_V_1_state_cmp_full and dst_V_1_sel_wr);
-    dst_V_1_sel <= dst_V_1_sel_rd;
-    dst_V_1_state_cmp_full <= '0' when (dst_V_1_state = ap_const_lv2_1) else '1';
-
-    dst_V_1_vld_in_assign_proc : process(ap_enable_reg_pp0_iter3, exitcond_flatten_reg_499_pp0_iter2_reg, ap_block_pp0_stage0_11001)
-    begin
-        if (((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1))) then 
-            dst_V_1_vld_in <= ap_const_logic_1;
-        else 
-            dst_V_1_vld_in <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    dst_V_1_vld_out <= dst_V_1_state(0);
-    dst_V_TDATA <= dst_V_1_data_out;
-
-    dst_V_TDATA_blk_n_assign_proc : process(dst_V_1_state, ap_enable_reg_pp0_iter3, ap_block_pp0_stage0, exitcond_flatten_reg_499_pp0_iter2_reg, ap_enable_reg_pp0_iter4, exitcond_flatten_reg_499_pp0_iter3_reg)
-    begin
-        if ((((exitcond_flatten_reg_499_pp0_iter3_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)))) then 
-            dst_V_TDATA_blk_n <= dst_V_1_state(1);
-        else 
-            dst_V_TDATA_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    dst_V_TVALID <= dst_V_1_state(0);
-    exitcond_flatten_fu_247_p2 <= "1" when (indvar_flatten_reg_145 = bound_reg_494) else "0";
-
-    height_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_blk_n <= height_empty_n;
-        else 
-            height_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    height_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_read <= ap_const_logic_1;
-        else 
-            height_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    i6_0_i_cast_i_i_fu_264_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_fu_258_p2),32));
-    i6_0_i_cast_i_i_mid1_fu_205_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i6_0_i_i_i_reg_156),32));
-    i6_0_i_i_i_mid2_fu_317_p3 <= 
-        i6_0_i_i_i_reg_156 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
-        i_fu_258_p2;
-    i_fu_258_p2 <= std_logic_vector(unsigned(i6_0_i_i_i_reg_156) + unsigned(ap_const_lv10_1));
-    indvar_flatten_next_fu_252_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_145) + unsigned(ap_const_lv64_1));
-    j_0_i_cast_i_i_fu_238_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_reg_167),32));
-    j_0_i_cast_i_i_mid2_s_fu_313_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_mid2_fu_268_p3),32));
-    j_0_i_i_i_mid2_fu_268_p3 <= 
-        j_0_i_i_i_reg_167 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
-        ap_const_lv10_0;
-    j_fu_340_p2 <= std_logic_vector(unsigned(j_0_i_i_i_mid2_fu_268_p3) + unsigned(ap_const_lv10_1));
-    l_edge_pix_fu_391_p3 <= 
-        r_edge_pix_fu_74 when (tmp_28_i_i_reg_529_pp0_iter1_reg(0) = '1') else 
-        pix_out_fu_78;
-    notlhs_fu_215_p2 <= "1" when (unsigned(i6_0_i_i_i_reg_156) > unsigned(ap_const_lv10_5)) else "0";
-    notlhs_mid1_fu_282_p2 <= "1" when (unsigned(i_fu_258_p2) > unsigned(ap_const_lv10_5)) else "0";
-    notrhs_fu_221_p2 <= "1" when (signed(i6_0_i_cast_i_i_mid1_fu_205_p1) < signed(tmp_7_i_i_reg_488)) else "0";
-    notrhs_mid1_fu_288_p2 <= "1" when (signed(i6_0_i_cast_i_i_fu_264_p1) < signed(tmp_7_i_i_reg_488)) else "0";
-    pix_in_2_l_edge_pix_s_fu_384_p3 <= 
-        r_edge_pix_fu_74 when (tmp_27_i_i_reg_544(0) = '1') else 
-        pix_out_1_fu_82;
-    pix_out_3_fu_424_p3 <= 
-        pix_out_7_reg_560 when (sel_tmp1_fu_419_p2(0) = '1') else 
-        pix_out_fu_78;
-    pix_out_8_fu_431_p3 <= 
-        pix_out_1_fu_82 when (tmp_29_i_i_reg_549_pp0_iter2_reg(0) = '1') else 
-        pix_out_3_fu_424_p3;
-    sel_tmp1_fu_419_p2 <= (tmp_30_i_i_reg_534_pp0_iter2_reg and sel_tmp_fu_414_p2);
-    sel_tmp_fu_414_p2 <= (tmp_29_i_i_reg_549_pp0_iter2_reg xor ap_const_lv1_1);
-    tmp_17_i_i_fu_209_p2 <= "1" when (i6_0_i_i_i_reg_156 = ap_const_lv10_0) else "0";
-    tmp_17_i_i_mid1_fu_276_p2 <= "1" when (i_fu_258_p2 = ap_const_lv10_0) else "0";
-    tmp_22_i_i_fu_242_p2 <= "1" when (signed(j_0_i_cast_i_i_fu_238_p1) < signed(width_read_reg_459)) else "0";
-    tmp_24_i_i_fu_325_p2 <= "1" when (signed(j_0_i_cast_i_i_mid2_s_fu_313_p1) < signed(vconv_xlim_loc_read_reg_473)) else "0";
-    tmp_26_i_i_fu_346_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_mid2_reg_508),64));
-    tmp_27_i_i_fu_355_p2 <= "1" when (j_0_i_i_i_mid2_reg_508 = ap_const_lv10_0) else "0";
-    tmp_28_i_i_fu_330_p2 <= "1" when (j_0_i_cast_i_i_mid2_s_fu_313_p1 = tmp_9_i_i_reg_478) else "0";
-    tmp_29_i_i_fu_360_p2 <= "1" when (unsigned(j_0_i_i_i_mid2_reg_508) < unsigned(ap_const_lv10_6)) else "0";
-    tmp_30_i_i_fu_335_p2 <= "1" when (signed(j_0_i_cast_i_i_mid2_s_fu_313_p1) < signed(tmp_i_i_reg_483)) else "0";
-    tmp_31_i_i_fu_365_p2 <= std_logic_vector(unsigned(j_0_i_i_i_mid2_reg_508) + unsigned(ap_const_lv10_3FB));
-    tmp_32_i_i_fu_370_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_31_i_i_fu_365_p2),64));
-    tmp_7_i_i_fu_188_p2 <= std_logic_vector(unsigned(height_read_reg_467) + unsigned(ap_const_lv32_FFFFFFFB));
-    tmp_9_i_i_fu_178_p2 <= std_logic_vector(unsigned(width_read_reg_459) + unsigned(ap_const_lv32_FFFFFFF5));
-    tmp_i_i_fu_183_p2 <= std_logic_vector(unsigned(width_read_reg_459) + unsigned(ap_const_lv32_FFFFFFFA));
-
-    vconv_V_blk_n_assign_proc : process(vconv_V_empty_n, ap_block_pp0_stage0, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, brmerge_mid2_reg_516, tmp_24_i_i_reg_525)
-    begin
-        if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
-            vconv_V_blk_n <= vconv_V_empty_n;
-        else 
-            vconv_V_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    vconv_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            vconv_V_read <= ap_const_logic_1;
-        else 
-            vconv_V_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    vconv_xlim_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            vconv_xlim_loc_blk_n <= vconv_xlim_loc_empty_n;
-        else 
-            vconv_xlim_loc_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    vconv_xlim_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            vconv_xlim_loc_read <= ap_const_logic_1;
-        else 
-            vconv_xlim_loc_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    width_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_blk_n <= width_empty_n;
-        else 
-            width_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    width_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_read <= ap_const_logic_1;
-        else 
-            width_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-end behav;

ip_repo_sources/packaging/src/Loop_Border_proc_borderbuf.vhd

@@ -1,132 +0,0 @@
--- ==============================================================
--- File generated on Wed Jun 26 16:53:30 CEST 2019
--- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
--- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
--- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--- ==============================================================
---
-library ieee; 
-use ieee.std_logic_1164.all; 
-use ieee.std_logic_unsigned.all;
-
-entity Loop_Border_proc_borderbuf_ram is 
-    generic(
-            MEM_TYPE    : string := "block"; 
-            DWIDTH     : integer := 32; 
-            AWIDTH     : integer := 10; 
-            MEM_SIZE    : integer := 662
-    ); 
-    port (
-          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
-          ce0       : in std_logic; 
-          d0        : in std_logic_vector(DWIDTH-1 downto 0); 
-          we0       : in std_logic; 
-          addr1     : in std_logic_vector(AWIDTH-1 downto 0); 
-          ce1       : in std_logic; 
-          q1        : out std_logic_vector(DWIDTH-1 downto 0);
-          clk        : in std_logic 
-    ); 
-end entity; 
-
-
-architecture rtl of Loop_Border_proc_borderbuf_ram is 
-
-signal addr1_tmp : std_logic_vector(AWIDTH-1 downto 0); 
-type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
-shared variable ram : mem_array;
-
-attribute syn_ramstyle : string; 
-attribute syn_ramstyle of ram : variable is "block_ram";
-attribute ram_style : string;
-attribute ram_style of ram : variable is MEM_TYPE;
-
-begin 
-
-
-
-p_memory_access_0: process (clk)  
-begin 
-    if (clk'event and clk = '1') then
-        if (ce0 = '1') then 
-            if (we0 = '1') then 
-                ram(CONV_INTEGER(addr0)) := d0; 
-            end if;
-        end if;
-    end if;
-end process;
-
-memory_access_guard_1: process (addr1) 
-begin
-      addr1_tmp <= addr1;
---synthesis translate_off
-      if (CONV_INTEGER(addr1) > mem_size-1) then
-           addr1_tmp <= (others => '0');
-      else 
-           addr1_tmp <= addr1;
-      end if;
---synthesis translate_on
-end process;
-
-p_memory_access_1: process (clk)  
-begin 
-    if (clk'event and clk = '1') then
-        if (ce1 = '1') then 
-            q1 <= ram(CONV_INTEGER(addr1_tmp)); 
-        end if;
-    end if;
-end process;
-
-
-end rtl;
-
-Library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity Loop_Border_proc_borderbuf is
-    generic (
-        DataWidth : INTEGER := 32;
-        AddressRange : INTEGER := 662;
-        AddressWidth : INTEGER := 10);
-    port (
-        reset : IN STD_LOGIC;
-        clk : IN STD_LOGIC;
-        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
-        ce0 : IN STD_LOGIC;
-        we0 : IN STD_LOGIC;
-        d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
-        address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
-        ce1 : IN STD_LOGIC;
-        q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
-end entity;
-
-architecture arch of Loop_Border_proc_borderbuf is
-    component Loop_Border_proc_borderbuf_ram is
-        port (
-            clk : IN STD_LOGIC;
-            addr0 : IN STD_LOGIC_VECTOR;
-            ce0 : IN STD_LOGIC;
-            we0 : IN STD_LOGIC;
-            d0 : IN STD_LOGIC_VECTOR;
-            addr1 : IN STD_LOGIC_VECTOR;
-            ce1 : IN STD_LOGIC;
-            q1 : OUT STD_LOGIC_VECTOR);
-    end component;
-
-
-
-begin
-    Loop_Border_proc_borderbuf_ram_U :  component Loop_Border_proc_borderbuf_ram
-    port map (
-        clk => clk,
-        addr0 => address0,
-        ce0 => ce0,
-        we0 => we0,
-        d0 => d0,
-        addr1 => address1,
-        ce1 => ce1,
-        q1 => q1);
-
-end architecture;
-
-

ip_repo_sources/packaging/src/Loop_HConvH_proc6.vhd

@@ -1,746 +0,0 @@
--- ==============================================================
--- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
--- Version: 2018.3
--- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--- 
--- ===========================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity Loop_HConvH_proc6 is
-port (
-    ap_clk : IN STD_LOGIC;
-    ap_rst : IN STD_LOGIC;
-    ap_start : IN STD_LOGIC;
-    ap_done : OUT STD_LOGIC;
-    ap_continue : IN STD_LOGIC;
-    ap_idle : OUT STD_LOGIC;
-    ap_ready : OUT STD_LOGIC;
-    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    height_empty_n : IN STD_LOGIC;
-    height_read : OUT STD_LOGIC;
-    width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    width_empty_n : IN STD_LOGIC;
-    width_read : OUT STD_LOGIC;
-    src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
-    src_V_TVALID : IN STD_LOGIC;
-    src_V_TREADY : OUT STD_LOGIC;
-    filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt1_empty_n : IN STD_LOGIC;
-    filt1_read : OUT STD_LOGIC;
-    filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt2_empty_n : IN STD_LOGIC;
-    filt2_read : OUT STD_LOGIC;
-    hconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    hconv_V_full_n : IN STD_LOGIC;
-    hconv_V_write : OUT STD_LOGIC );
-end;
-
-
-architecture behav of Loop_HConvH_proc6 is 
-    constant ap_const_logic_1 : STD_LOGIC := '1';
-    constant ap_const_logic_0 : STD_LOGIC := '0';
-    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
-    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
-    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
-    constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
-    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
-    constant ap_const_boolean_1 : BOOLEAN := true;
-    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
-    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
-    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
-    constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
-    constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
-    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
-    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
-    constant ap_const_boolean_0 : BOOLEAN := false;
-    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
-    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
-    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
-    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
-    constant ap_const_lv10_9 : STD_LOGIC_VECTOR (9 downto 0) := "0000001001";
-    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
-    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
-
-    signal ap_done_reg : STD_LOGIC := '0';
-    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
-    attribute fsm_encoding : string;
-    attribute fsm_encoding of ap_CS_fsm : signal is "none";
-    signal ap_CS_fsm_state1 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
-    signal src_V_0_data_out : STD_LOGIC_VECTOR (31 downto 0);
-    signal src_V_0_vld_in : STD_LOGIC;
-    signal src_V_0_vld_out : STD_LOGIC;
-    signal src_V_0_ack_in : STD_LOGIC;
-    signal src_V_0_ack_out : STD_LOGIC;
-    signal src_V_0_payload_A : STD_LOGIC_VECTOR (31 downto 0);
-    signal src_V_0_payload_B : STD_LOGIC_VECTOR (31 downto 0);
-    signal src_V_0_sel_rd : STD_LOGIC := '0';
-    signal src_V_0_sel_wr : STD_LOGIC := '0';
-    signal src_V_0_sel : STD_LOGIC;
-    signal src_V_0_load_A : STD_LOGIC;
-    signal src_V_0_load_B : STD_LOGIC;
-    signal src_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
-    signal src_V_0_state_cmp_full : STD_LOGIC;
-    signal height_blk_n : STD_LOGIC;
-    signal width_blk_n : STD_LOGIC;
-    signal src_V_TDATA_blk_n : STD_LOGIC;
-    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
-    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
-    signal ap_block_pp0_stage0 : BOOLEAN;
-    signal exitcond_flatten_fu_214_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal filt1_blk_n : STD_LOGIC;
-    signal filt2_blk_n : STD_LOGIC;
-    signal hconv_V_blk_n : STD_LOGIC;
-    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
-    signal tmp_10_i_reg_491 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_10_i_reg_491_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal indvar_flatten_reg_141 : STD_LOGIC_VECTOR (63 downto 0);
-    signal row_0_i_i_reg_152 : STD_LOGIC_VECTOR (9 downto 0);
-    signal height_read_reg_421 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_state1 : BOOLEAN;
-    signal width_read_reg_426 : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt1_read_reg_432 : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt2_read_reg_437 : STD_LOGIC_VECTOR (31 downto 0);
-    signal bound_fu_169_p2 : STD_LOGIC_VECTOR (63 downto 0);
-    signal bound_reg_442 : STD_LOGIC_VECTOR (63 downto 0);
-    signal ap_CS_fsm_state2 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
-    signal hwin_5_load_reg_447 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
-    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
-    signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
-    signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
-    signal ap_block_pp0_stage0_11001 : BOOLEAN;
-    signal hwin_5_load_reg_447_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_8_load_reg_452 : STD_LOGIC_VECTOR (31 downto 0);
-    signal exitcond_flatten_reg_457 : STD_LOGIC_VECTOR (0 downto 0);
-    signal exitcond_flatten_reg_457_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal indvar_flatten_next_fu_219_p2 : STD_LOGIC_VECTOR (63 downto 0);
-    signal tmp_23_9_i_fu_281_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_23_9_i_reg_466 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_23_i_fu_286_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_23_i_reg_471 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_fu_291_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_reg_476 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_reg_476_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_reg_476_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_fu_303_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_reg_481 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_reg_481_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_reg_481_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp7_fu_309_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp7_reg_486 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp7_reg_486_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_10_i_fu_315_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_10_i_reg_491_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal row_fu_326_p2 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp8_fu_336_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp8_reg_500 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp5_fu_345_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp5_reg_505 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_pp0_stage0_subdone : BOOLEAN;
-    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
-    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
-    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
-    signal ap_block_pp0_stage0_01001 : BOOLEAN;
-    signal hwin_1_1_i_fu_64 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_1_fu_68 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_2_fu_72 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_3_fu_76 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_4_fu_80 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_5_fu_84 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_6_fu_88 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_7_fu_92 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_8_fu_96 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_9_fu_100 : STD_LOGIC_VECTOR (31 downto 0);
-    signal bound_fu_169_p0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal bound_fu_169_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal row_0_i_cast_i_fu_205_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_4_i_fu_209_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_23_9_i_fu_281_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_23_i_fu_286_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp4_fu_297_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal row_0_i_i_mid2_fu_273_p3 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp9_fu_332_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp6_fu_341_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp1_fu_350_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_CS_fsm_state7 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
-    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
-    signal ap_idle_pp0 : STD_LOGIC;
-    signal ap_enable_pp0 : STD_LOGIC;
-    signal bound_fu_169_p00 : STD_LOGIC_VECTOR (63 downto 0);
-    signal bound_fu_169_p10 : STD_LOGIC_VECTOR (63 downto 0);
-
-
-begin
-
-
-
-
-    ap_CS_fsm_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_CS_fsm <= ap_ST_fsm_state1;
-            else
-                ap_CS_fsm <= ap_NS_fsm;
-            end if;
-        end if;
-    end process;
-
-
-    ap_done_reg_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_done_reg <= ap_const_logic_0;
-            else
-                if ((ap_continue = ap_const_logic_1)) then 
-                    ap_done_reg <= ap_const_logic_0;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
-                    ap_done_reg <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
-            else
-                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
-                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then 
-                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
-                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
-                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
-                    end if;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                    ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    src_V_0_sel_rd_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                src_V_0_sel_rd <= ap_const_logic_0;
-            else
-                if (((src_V_0_ack_out = ap_const_logic_1) and (src_V_0_vld_out = ap_const_logic_1))) then 
-                                        src_V_0_sel_rd <= not(src_V_0_sel_rd);
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    src_V_0_sel_wr_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                src_V_0_sel_wr <= ap_const_logic_0;
-            else
-                if (((src_V_0_ack_in = ap_const_logic_1) and (src_V_0_vld_in = ap_const_logic_1))) then 
-                                        src_V_0_sel_wr <= not(src_V_0_sel_wr);
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    src_V_0_state_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                src_V_0_state <= ap_const_lv2_0;
-            else
-                if ((((src_V_0_state = ap_const_lv2_2) and (src_V_0_vld_in = ap_const_logic_0)) or ((src_V_0_state = ap_const_lv2_3) and (src_V_0_vld_in = ap_const_logic_0) and (src_V_0_ack_out = ap_const_logic_1)))) then 
-                    src_V_0_state <= ap_const_lv2_2;
-                elsif ((((src_V_0_state = ap_const_lv2_1) and (src_V_0_ack_out = ap_const_logic_0)) or ((src_V_0_state = ap_const_lv2_3) and (src_V_0_ack_out = ap_const_logic_0) and (src_V_0_vld_in = ap_const_logic_1)))) then 
-                    src_V_0_state <= ap_const_lv2_1;
-                elsif (((not(((src_V_0_vld_in = ap_const_logic_0) and (src_V_0_ack_out = ap_const_logic_1))) and not(((src_V_0_ack_out = ap_const_logic_0) and (src_V_0_vld_in = ap_const_logic_1))) and (src_V_0_state = ap_const_lv2_3)) or ((src_V_0_state = ap_const_lv2_1) and (src_V_0_ack_out = ap_const_logic_1)) or ((src_V_0_state = ap_const_lv2_2) and (src_V_0_vld_in = ap_const_logic_1)))) then 
-                    src_V_0_state <= ap_const_lv2_3;
-                else 
-                    src_V_0_state <= ap_const_lv2_2;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    indvar_flatten_reg_141_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
-                indvar_flatten_reg_141 <= indvar_flatten_next_fu_219_p2;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                indvar_flatten_reg_141 <= ap_const_lv64_0;
-            end if; 
-        end if;
-    end process;
-
-    row_0_i_i_reg_152_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
-                row_0_i_i_reg_152 <= row_fu_326_p2;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                row_0_i_i_reg_152 <= ap_const_lv10_0;
-            end if; 
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
-                bound_reg_442 <= bound_fu_169_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
-                exitcond_flatten_reg_457 <= exitcond_flatten_fu_214_p2;
-                exitcond_flatten_reg_457_pp0_iter1_reg <= exitcond_flatten_reg_457;
-                hwin_5_load_reg_447 <= hwin_5_fu_84;
-                hwin_5_load_reg_447_pp0_iter1_reg <= hwin_5_load_reg_447;
-                hwin_8_load_reg_452 <= hwin_8_fu_96;
-                tmp2_reg_476_pp0_iter1_reg <= tmp2_reg_476;
-                tmp3_reg_481_pp0_iter1_reg <= tmp3_reg_481;
-                tmp7_reg_486_pp0_iter1_reg <= tmp7_reg_486;
-                tmp_10_i_reg_491_pp0_iter1_reg <= tmp_10_i_reg_491;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                filt1_read_reg_432 <= filt1_dout;
-                filt2_read_reg_437 <= filt2_dout;
-                height_read_reg_421 <= height_dout;
-                width_read_reg_426 <= width_dout;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
-                hwin_1_1_i_fu_64 <= hwin_1_fu_68;
-                hwin_1_fu_68 <= hwin_2_fu_72;
-                hwin_2_fu_72 <= hwin_3_fu_76;
-                hwin_3_fu_76 <= hwin_4_fu_80;
-                hwin_4_fu_80 <= hwin_5_fu_84;
-                hwin_5_fu_84 <= hwin_6_fu_88;
-                hwin_6_fu_88 <= hwin_7_fu_92;
-                hwin_7_fu_92 <= hwin_8_fu_96;
-                hwin_8_fu_96 <= hwin_9_fu_100;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
-                hwin_9_fu_100 <= src_V_0_data_out;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((src_V_0_load_A = ap_const_logic_1)) then
-                src_V_0_payload_A <= src_V_TDATA;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((src_V_0_load_B = ap_const_logic_1)) then
-                src_V_0_payload_B <= src_V_TDATA;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
-                tmp2_reg_476 <= tmp2_fu_291_p2;
-                tmp3_reg_481 <= tmp3_fu_303_p2;
-                tmp7_reg_486 <= tmp7_fu_309_p2;
-                tmp_10_i_reg_491 <= tmp_10_i_fu_315_p2;
-                tmp_23_9_i_reg_466 <= tmp_23_9_i_fu_281_p2;
-                tmp_23_i_reg_471 <= tmp_23_i_fu_286_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
-                tmp2_reg_476_pp0_iter2_reg <= tmp2_reg_476_pp0_iter1_reg;
-                tmp3_reg_481_pp0_iter2_reg <= tmp3_reg_481_pp0_iter1_reg;
-                tmp_10_i_reg_491_pp0_iter2_reg <= tmp_10_i_reg_491_pp0_iter1_reg;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_reg_457_pp0_iter1_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
-                tmp5_reg_505 <= tmp5_fu_345_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_reg_457 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
-                tmp8_reg_500 <= tmp8_fu_336_p2;
-            end if;
-        end if;
-    end process;
-
-    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
-    begin
-        case ap_CS_fsm is
-            when ap_ST_fsm_state1 => 
-                if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                    ap_NS_fsm <= ap_ST_fsm_state2;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_state1;
-                end if;
-            when ap_ST_fsm_state2 => 
-                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-            when ap_ST_fsm_pp0_stage0 => 
-                if ((not(((exitcond_flatten_fu_214_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) and not(((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1))))) then
-                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-                elsif ((((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)))) then
-                    ap_NS_fsm <= ap_ST_fsm_state7;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-                end if;
-            when ap_ST_fsm_state7 => 
-                ap_NS_fsm <= ap_ST_fsm_state1;
-            when others =>  
-                ap_NS_fsm <= "XXXX";
-        end case;
-    end process;
-    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
-    ap_CS_fsm_state1 <= ap_CS_fsm(0);
-    ap_CS_fsm_state2 <= ap_CS_fsm(1);
-    ap_CS_fsm_state7 <= ap_CS_fsm(3);
-        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_pp0_stage0_01001_assign_proc : process(src_V_0_vld_out, hconv_V_full_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
-    begin
-                ap_block_pp0_stage0_01001 <= (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)));
-    end process;
-
-
-    ap_block_pp0_stage0_11001_assign_proc : process(src_V_0_vld_out, hconv_V_full_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
-    begin
-                ap_block_pp0_stage0_11001 <= (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)));
-    end process;
-
-
-    ap_block_pp0_stage0_subdone_assign_proc : process(src_V_0_vld_out, hconv_V_full_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
-    begin
-                ap_block_pp0_stage0_subdone <= (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)));
-    end process;
-
-
-    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
-    begin
-                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
-    end process;
-
-
-    ap_block_state3_pp0_stage0_iter0_assign_proc : process(src_V_0_vld_out, exitcond_flatten_fu_214_p2)
-    begin
-                ap_block_state3_pp0_stage0_iter0 <= ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0));
-    end process;
-
-        ap_block_state4_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-        ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_state6_pp0_stage0_iter3_assign_proc : process(hconv_V_full_n, tmp_10_i_reg_491_pp0_iter2_reg)
-    begin
-                ap_block_state6_pp0_stage0_iter3 <= ((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0));
-    end process;
-
-
-    ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_flatten_fu_214_p2)
-    begin
-        if ((exitcond_flatten_fu_214_p2 = ap_const_lv1_1)) then 
-            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
-        else 
-            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state7)
-    begin
-        if ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
-            ap_done <= ap_const_logic_1;
-        else 
-            ap_done <= ap_done_reg;
-        end if; 
-    end process;
-
-    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
-
-    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
-    begin
-        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            ap_idle <= ap_const_logic_1;
-        else 
-            ap_idle <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
-    begin
-        if (((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then 
-            ap_idle_pp0 <= ap_const_logic_1;
-        else 
-            ap_idle_pp0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_ready_assign_proc : process(ap_CS_fsm_state7)
-    begin
-        if ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
-            ap_ready <= ap_const_logic_1;
-        else 
-            ap_ready <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    bound_fu_169_p0 <= bound_fu_169_p00(32 - 1 downto 0);
-    bound_fu_169_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(width_read_reg_426),64));
-    bound_fu_169_p1 <= bound_fu_169_p10(32 - 1 downto 0);
-    bound_fu_169_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(height_read_reg_421),64));
-    bound_fu_169_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_169_p0) * unsigned(bound_fu_169_p1), 64));
-    exitcond_flatten_fu_214_p2 <= "1" when (indvar_flatten_reg_141 = bound_reg_442) else "0";
-
-    filt1_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt1_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_blk_n <= filt1_empty_n;
-        else 
-            filt1_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    filt1_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_read <= ap_const_logic_1;
-        else 
-            filt1_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    filt2_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt2_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_blk_n <= filt2_empty_n;
-        else 
-            filt2_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    filt2_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_read <= ap_const_logic_1;
-        else 
-            filt2_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    hconv_V_blk_n_assign_proc : process(hconv_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
-    begin
-        if (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
-            hconv_V_blk_n <= hconv_V_full_n;
-        else 
-            hconv_V_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    hconv_V_din <= std_logic_vector(unsigned(tmp5_reg_505) + unsigned(tmp1_fu_350_p2));
-
-    hconv_V_write_assign_proc : process(ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg, ap_block_pp0_stage0_11001)
-    begin
-        if (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
-            hconv_V_write <= ap_const_logic_1;
-        else 
-            hconv_V_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    height_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_blk_n <= height_empty_n;
-        else 
-            height_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    height_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_read <= ap_const_logic_1;
-        else 
-            height_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    indvar_flatten_next_fu_219_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_141) + unsigned(ap_const_lv64_1));
-    row_0_i_cast_i_fu_205_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_0_i_i_reg_152),32));
-    row_0_i_i_mid2_fu_273_p3 <= 
-        row_0_i_i_reg_152 when (tmp_4_i_fu_209_p2(0) = '1') else 
-        ap_const_lv10_0;
-    row_fu_326_p2 <= std_logic_vector(unsigned(row_0_i_i_mid2_fu_273_p3) + unsigned(ap_const_lv10_1));
-    src_V_0_ack_in <= src_V_0_state(1);
-
-    src_V_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_block_pp0_stage0_11001)
-    begin
-        if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
-            src_V_0_ack_out <= ap_const_logic_1;
-        else 
-            src_V_0_ack_out <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    src_V_0_data_out_assign_proc : process(src_V_0_payload_A, src_V_0_payload_B, src_V_0_sel)
-    begin
-        if ((src_V_0_sel = ap_const_logic_1)) then 
-            src_V_0_data_out <= src_V_0_payload_B;
-        else 
-            src_V_0_data_out <= src_V_0_payload_A;
-        end if; 
-    end process;
-
-    src_V_0_load_A <= (src_V_0_state_cmp_full and not(src_V_0_sel_wr));
-    src_V_0_load_B <= (src_V_0_state_cmp_full and src_V_0_sel_wr);
-    src_V_0_sel <= src_V_0_sel_rd;
-    src_V_0_state_cmp_full <= '0' when (src_V_0_state = ap_const_lv2_1) else '1';
-    src_V_0_vld_in <= src_V_TVALID;
-    src_V_0_vld_out <= src_V_0_state(0);
-
-    src_V_TDATA_blk_n_assign_proc : process(src_V_0_state, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0, exitcond_flatten_fu_214_p2)
-    begin
-        if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
-            src_V_TDATA_blk_n <= src_V_0_state(0);
-        else 
-            src_V_TDATA_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    src_V_TREADY <= src_V_0_state(1);
-    tmp1_fu_350_p2 <= std_logic_vector(unsigned(tmp3_reg_481_pp0_iter2_reg) + unsigned(tmp2_reg_476_pp0_iter2_reg));
-    tmp2_fu_291_p2 <= std_logic_vector(unsigned(hwin_1_1_i_fu_64) + unsigned(hwin_1_fu_68));
-    tmp3_fu_303_p2 <= std_logic_vector(unsigned(tmp4_fu_297_p2) + unsigned(hwin_2_fu_72));
-    tmp4_fu_297_p2 <= std_logic_vector(unsigned(hwin_3_fu_76) + unsigned(hwin_4_fu_80));
-    tmp5_fu_345_p2 <= std_logic_vector(unsigned(tmp8_reg_500) + unsigned(tmp6_fu_341_p2));
-    tmp6_fu_341_p2 <= std_logic_vector(unsigned(tmp7_reg_486_pp0_iter1_reg) + unsigned(hwin_5_load_reg_447_pp0_iter1_reg));
-    tmp7_fu_309_p2 <= std_logic_vector(unsigned(hwin_6_fu_88) + unsigned(hwin_7_fu_92));
-    tmp8_fu_336_p2 <= std_logic_vector(unsigned(tmp9_fu_332_p2) + unsigned(hwin_8_load_reg_452));
-    tmp9_fu_332_p2 <= std_logic_vector(unsigned(tmp_23_9_i_reg_466) + unsigned(tmp_23_i_reg_471));
-    tmp_10_i_fu_315_p2 <= "1" when (unsigned(row_0_i_i_mid2_fu_273_p3) > unsigned(ap_const_lv10_9)) else "0";
-    tmp_23_9_i_fu_281_p1 <= hwin_9_fu_100;
-    tmp_23_9_i_fu_281_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt1_read_reg_432) * signed(tmp_23_9_i_fu_281_p1))), 32));
-    tmp_23_i_fu_286_p1 <= src_V_0_data_out;
-    tmp_23_i_fu_286_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt2_read_reg_437) * signed(tmp_23_i_fu_286_p1))), 32));
-    tmp_4_i_fu_209_p2 <= "1" when (signed(row_0_i_cast_i_fu_205_p1) < signed(width_read_reg_426)) else "0";
-
-    width_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_blk_n <= width_empty_n;
-        else 
-            width_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    width_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_read <= ap_const_logic_1;
-        else 
-            width_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-end behav;

ip_repo_sources/packaging/src/Loop_VConvH_proc.vhd

@@ -1,1570 +0,0 @@
--- ==============================================================
--- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
--- Version: 2018.3
--- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--- 
--- ===========================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity Loop_VConvH_proc is
-port (
-    ap_clk : IN STD_LOGIC;
-    ap_rst : IN STD_LOGIC;
-    ap_start : IN STD_LOGIC;
-    ap_done : OUT STD_LOGIC;
-    ap_continue : IN STD_LOGIC;
-    ap_idle : OUT STD_LOGIC;
-    ap_ready : OUT STD_LOGIC;
-    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    height_empty_n : IN STD_LOGIC;
-    height_read : OUT STD_LOGIC;
-    vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    vconv_xlim_loc_empty_n : IN STD_LOGIC;
-    vconv_xlim_loc_read : OUT STD_LOGIC;
-    hconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    hconv_V_empty_n : IN STD_LOGIC;
-    hconv_V_read : OUT STD_LOGIC;
-    vconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    vconv_V_full_n : IN STD_LOGIC;
-    vconv_V_write : OUT STD_LOGIC;
-    filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt1_empty_n : IN STD_LOGIC;
-    filt1_read : OUT STD_LOGIC;
-    filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt2_empty_n : IN STD_LOGIC;
-    filt2_read : OUT STD_LOGIC;
-    height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    height_out_full_n : IN STD_LOGIC;
-    height_out_write : OUT STD_LOGIC;
-    vconv_xlim_loc_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    vconv_xlim_loc_out_full_n : IN STD_LOGIC;
-    vconv_xlim_loc_out_write : OUT STD_LOGIC );
-end;
-
-
-architecture behav of Loop_VConvH_proc is 
-    constant ap_const_logic_1 : STD_LOGIC := '1';
-    constant ap_const_logic_0 : STD_LOGIC := '0';
-    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
-    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
-    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
-    constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
-    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
-    constant ap_const_boolean_1 : BOOLEAN := true;
-    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
-    constant ap_const_boolean_0 : BOOLEAN := false;
-    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
-    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
-    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
-    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
-    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
-    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
-    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
-    constant ap_const_lv10_9 : STD_LOGIC_VECTOR (9 downto 0) := "0000001001";
-    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
-
-    signal ap_done_reg : STD_LOGIC := '0';
-    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
-    attribute fsm_encoding : string;
-    attribute fsm_encoding of ap_CS_fsm : signal is "none";
-    signal ap_CS_fsm_state1 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
-    signal linebuf_0_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_0_ce0 : STD_LOGIC;
-    signal linebuf_0_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_0_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_0_ce1 : STD_LOGIC;
-    signal linebuf_0_we1 : STD_LOGIC;
-    signal linebuf_1_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_1_ce0 : STD_LOGIC;
-    signal linebuf_1_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_1_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_1_ce1 : STD_LOGIC;
-    signal linebuf_1_we1 : STD_LOGIC;
-    signal linebuf_2_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_2_ce0 : STD_LOGIC;
-    signal linebuf_2_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_2_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_2_ce1 : STD_LOGIC;
-    signal linebuf_2_we1 : STD_LOGIC;
-    signal linebuf_3_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_3_ce0 : STD_LOGIC;
-    signal linebuf_3_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_3_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_3_ce1 : STD_LOGIC;
-    signal linebuf_3_we1 : STD_LOGIC;
-    signal linebuf_4_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_4_ce0 : STD_LOGIC;
-    signal linebuf_4_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_4_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_4_ce1 : STD_LOGIC;
-    signal linebuf_4_we1 : STD_LOGIC;
-    signal linebuf_5_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_5_ce0 : STD_LOGIC;
-    signal linebuf_5_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_5_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_5_ce1 : STD_LOGIC;
-    signal linebuf_5_we1 : STD_LOGIC;
-    signal linebuf_6_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_6_ce0 : STD_LOGIC;
-    signal linebuf_6_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_6_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_6_ce1 : STD_LOGIC;
-    signal linebuf_6_we1 : STD_LOGIC;
-    signal linebuf_7_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_7_ce0 : STD_LOGIC;
-    signal linebuf_7_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_7_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_7_ce1 : STD_LOGIC;
-    signal linebuf_7_we1 : STD_LOGIC;
-    signal linebuf_8_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_8_ce0 : STD_LOGIC;
-    signal linebuf_8_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_8_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_8_ce1 : STD_LOGIC;
-    signal linebuf_8_we1 : STD_LOGIC;
-    signal linebuf_9_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_9_ce0 : STD_LOGIC;
-    signal linebuf_9_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_9_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_9_ce1 : STD_LOGIC;
-    signal linebuf_9_we1 : STD_LOGIC;
-    signal height_blk_n : STD_LOGIC;
-    signal vconv_xlim_loc_blk_n : STD_LOGIC;
-    signal hconv_V_blk_n : STD_LOGIC;
-    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
-    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
-    signal ap_block_pp0_stage0 : BOOLEAN;
-    signal exitcond_flatten_reg_532 : STD_LOGIC_VECTOR (0 downto 0);
-    signal vconv_V_blk_n : STD_LOGIC;
-    signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
-    signal tmp_8_i_i_mid2_reg_541 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_8_i_i_mid2_reg_541_pp0_iter4_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal filt1_blk_n : STD_LOGIC;
-    signal filt2_blk_n : STD_LOGIC;
-    signal height_out_blk_n : STD_LOGIC;
-    signal vconv_xlim_loc_out_blk_n : STD_LOGIC;
-    signal indvar_flatten_reg_319 : STD_LOGIC_VECTOR (63 downto 0);
-    signal col1_0_i_i_i_reg_330 : STD_LOGIC_VECTOR (9 downto 0);
-    signal row2_0_i_i_i_reg_341 : STD_LOGIC_VECTOR (9 downto 0);
-    signal height_read_reg_506 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_state1 : BOOLEAN;
-    signal vconv_xlim_loc_read_reg_511 : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt1_read_reg_517 : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt2_read_reg_522 : STD_LOGIC_VECTOR (31 downto 0);
-    signal bound_fu_358_p2 : STD_LOGIC_VECTOR (63 downto 0);
-    signal bound_reg_527 : STD_LOGIC_VECTOR (63 downto 0);
-    signal ap_CS_fsm_state2 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
-    signal exitcond_flatten_fu_373_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
-    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
-    signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
-    signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
-    signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
-    signal ap_block_state8_pp0_stage0_iter5 : BOOLEAN;
-    signal ap_block_pp0_stage0_11001 : BOOLEAN;
-    signal exitcond_flatten_reg_532_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal exitcond_flatten_reg_532_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal exitcond_flatten_reg_532_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal indvar_flatten_next_fu_378_p2 : STD_LOGIC_VECTOR (63 downto 0);
-    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
-    signal tmp_8_i_i_mid2_fu_410_p3 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_8_i_i_mid2_reg_541_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_8_i_i_mid2_reg_541_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_8_i_i_mid2_reg_541_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal col1_0_i_i_i_mid2_fu_418_p3 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_0_addr_reg_550 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_1_addr_reg_556 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_2_addr_reg_562 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_3_addr_reg_568 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_4_addr_reg_574 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_5_addr_reg_580 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_6_addr_reg_586 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_7_addr_reg_592 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_8_addr_reg_598 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_9_addr_reg_604 : STD_LOGIC_VECTOR (9 downto 0);
-    signal row_fu_440_p2 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp_1_reg_615 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_5_load_reg_620 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_5_load_reg_620_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_5_load_reg_620_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_8_load_reg_625 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_8_load_reg_625_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_9_load_reg_630 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_fu_446_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_reg_635 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_reg_635_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_reg_635_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_reg_635_pp0_iter4_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_fu_458_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_reg_640 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_reg_640_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_reg_640_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_reg_640_pp0_iter4_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp7_fu_464_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp7_reg_645 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp7_reg_645_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp7_reg_645_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_30_9_i_i_fu_470_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_30_9_i_i_reg_650 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_30_i_i_fu_474_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_30_i_i_reg_655 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp8_fu_482_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp8_reg_660 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp5_fu_491_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp5_reg_665 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_pp0_stage0_subdone : BOOLEAN;
-    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
-    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
-    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
-    signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
-    signal tmp_16_i_i_fu_426_p1 : STD_LOGIC_VECTOR (63 downto 0);
-    signal ap_block_pp0_stage0_01001 : BOOLEAN;
-    signal bound_fu_358_p0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal bound_fu_358_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal row2_0_i_cast_i_i_fu_364_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_11_i_i_fu_368_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal col_fu_392_p2 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp_8_i_i_fu_404_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_8_i_i_mid1_fu_398_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal row2_0_i_i_i_mid2_fu_384_p3 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp4_fu_452_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp9_fu_478_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp6_fu_487_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp1_fu_496_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_CS_fsm_state9 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
-    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
-    signal ap_block_pp0 : BOOLEAN;
-    signal ap_enable_operation_44 : BOOLEAN;
-    signal ap_enable_state3_pp0_iter0_stage0 : BOOLEAN;
-    signal ap_enable_operation_66 : BOOLEAN;
-    signal ap_enable_state4_pp0_iter1_stage0 : BOOLEAN;
-    signal ap_enable_operation_68 : BOOLEAN;
-    signal ap_enable_operation_46 : BOOLEAN;
-    signal ap_enable_operation_67 : BOOLEAN;
-    signal ap_enable_operation_70 : BOOLEAN;
-    signal ap_enable_operation_48 : BOOLEAN;
-    signal ap_enable_operation_69 : BOOLEAN;
-    signal ap_enable_operation_72 : BOOLEAN;
-    signal ap_enable_operation_50 : BOOLEAN;
-    signal ap_enable_operation_71 : BOOLEAN;
-    signal ap_enable_operation_74 : BOOLEAN;
-    signal ap_enable_operation_52 : BOOLEAN;
-    signal ap_enable_operation_73 : BOOLEAN;
-    signal ap_enable_operation_76 : BOOLEAN;
-    signal ap_enable_operation_54 : BOOLEAN;
-    signal ap_enable_operation_75 : BOOLEAN;
-    signal ap_enable_operation_78 : BOOLEAN;
-    signal ap_enable_operation_56 : BOOLEAN;
-    signal ap_enable_operation_77 : BOOLEAN;
-    signal ap_enable_operation_80 : BOOLEAN;
-    signal ap_enable_operation_58 : BOOLEAN;
-    signal ap_enable_operation_79 : BOOLEAN;
-    signal ap_enable_operation_82 : BOOLEAN;
-    signal ap_enable_operation_60 : BOOLEAN;
-    signal ap_enable_operation_81 : BOOLEAN;
-    signal ap_enable_operation_84 : BOOLEAN;
-    signal ap_enable_operation_62 : BOOLEAN;
-    signal ap_enable_operation_83 : BOOLEAN;
-    signal ap_enable_operation_89 : BOOLEAN;
-    signal ap_idle_pp0 : STD_LOGIC;
-    signal ap_enable_pp0 : STD_LOGIC;
-    signal bound_fu_358_p00 : STD_LOGIC_VECTOR (63 downto 0);
-    signal bound_fu_358_p10 : STD_LOGIC_VECTOR (63 downto 0);
-
-    component Loop_VConvH_proc_linebuf_0 IS
-    generic (
-        DataWidth : INTEGER;
-        AddressRange : INTEGER;
-        AddressWidth : INTEGER );
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        address0 : IN STD_LOGIC_VECTOR (9 downto 0);
-        ce0 : IN STD_LOGIC;
-        q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
-        address1 : IN STD_LOGIC_VECTOR (9 downto 0);
-        ce1 : IN STD_LOGIC;
-        we1 : IN STD_LOGIC;
-        d1 : IN STD_LOGIC_VECTOR (31 downto 0) );
-    end component;
-
-
-
-begin
-    linebuf_0_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_0_address0,
-        ce0 => linebuf_0_ce0,
-        q0 => linebuf_0_q0,
-        address1 => linebuf_0_address1,
-        ce1 => linebuf_0_ce1,
-        we1 => linebuf_0_we1,
-        d1 => linebuf_1_q0);
-
-    linebuf_1_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_1_address0,
-        ce0 => linebuf_1_ce0,
-        q0 => linebuf_1_q0,
-        address1 => linebuf_1_address1,
-        ce1 => linebuf_1_ce1,
-        we1 => linebuf_1_we1,
-        d1 => linebuf_2_q0);
-
-    linebuf_2_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_2_address0,
-        ce0 => linebuf_2_ce0,
-        q0 => linebuf_2_q0,
-        address1 => linebuf_2_address1,
-        ce1 => linebuf_2_ce1,
-        we1 => linebuf_2_we1,
-        d1 => linebuf_3_q0);
-
-    linebuf_3_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_3_address0,
-        ce0 => linebuf_3_ce0,
-        q0 => linebuf_3_q0,
-        address1 => linebuf_3_address1,
-        ce1 => linebuf_3_ce1,
-        we1 => linebuf_3_we1,
-        d1 => linebuf_4_q0);
-
-    linebuf_4_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_4_address0,
-        ce0 => linebuf_4_ce0,
-        q0 => linebuf_4_q0,
-        address1 => linebuf_4_address1,
-        ce1 => linebuf_4_ce1,
-        we1 => linebuf_4_we1,
-        d1 => linebuf_5_q0);
-
-    linebuf_5_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_5_address0,
-        ce0 => linebuf_5_ce0,
-        q0 => linebuf_5_q0,
-        address1 => linebuf_5_address1,
-        ce1 => linebuf_5_ce1,
-        we1 => linebuf_5_we1,
-        d1 => linebuf_6_q0);
-
-    linebuf_6_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_6_address0,
-        ce0 => linebuf_6_ce0,
-        q0 => linebuf_6_q0,
-        address1 => linebuf_6_address1,
-        ce1 => linebuf_6_ce1,
-        we1 => linebuf_6_we1,
-        d1 => linebuf_7_q0);
-
-    linebuf_7_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_7_address0,
-        ce0 => linebuf_7_ce0,
-        q0 => linebuf_7_q0,
-        address1 => linebuf_7_address1,
-        ce1 => linebuf_7_ce1,
-        we1 => linebuf_7_we1,
-        d1 => linebuf_8_q0);
-
-    linebuf_8_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_8_address0,
-        ce0 => linebuf_8_ce0,
-        q0 => linebuf_8_q0,
-        address1 => linebuf_8_address1,
-        ce1 => linebuf_8_ce1,
-        we1 => linebuf_8_we1,
-        d1 => linebuf_9_q0);
-
-    linebuf_9_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_9_address0,
-        ce0 => linebuf_9_ce0,
-        q0 => linebuf_9_q0,
-        address1 => linebuf_9_address1,
-        ce1 => linebuf_9_ce1,
-        we1 => linebuf_9_we1,
-        d1 => hconv_V_dout);
-
-
-
-
-
-    ap_CS_fsm_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_CS_fsm <= ap_ST_fsm_state1;
-            else
-                ap_CS_fsm <= ap_NS_fsm;
-            end if;
-        end if;
-    end process;
-
-
-    ap_done_reg_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_done_reg <= ap_const_logic_0;
-            else
-                if ((ap_continue = ap_const_logic_1)) then 
-                    ap_done_reg <= ap_const_logic_0;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
-                    ap_done_reg <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
-            else
-                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
-                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then 
-                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
-                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
-                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
-                    end if;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                    ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    col1_0_i_i_i_reg_330_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
-                col1_0_i_i_i_reg_330 <= col1_0_i_i_i_mid2_fu_418_p3;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                col1_0_i_i_i_reg_330 <= ap_const_lv10_0;
-            end if; 
-        end if;
-    end process;
-
-    indvar_flatten_reg_319_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
-                indvar_flatten_reg_319 <= indvar_flatten_next_fu_378_p2;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                indvar_flatten_reg_319 <= ap_const_lv64_0;
-            end if; 
-        end if;
-    end process;
-
-    row2_0_i_i_i_reg_341_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
-                row2_0_i_i_i_reg_341 <= row_fu_440_p2;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                row2_0_i_i_i_reg_341 <= ap_const_lv10_0;
-            end if; 
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
-                bound_reg_527 <= bound_fu_358_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
-                exitcond_flatten_reg_532 <= exitcond_flatten_fu_373_p2;
-                exitcond_flatten_reg_532_pp0_iter1_reg <= exitcond_flatten_reg_532;
-                tmp_8_i_i_mid2_reg_541_pp0_iter1_reg <= tmp_8_i_i_mid2_reg_541;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
-                exitcond_flatten_reg_532_pp0_iter2_reg <= exitcond_flatten_reg_532_pp0_iter1_reg;
-                exitcond_flatten_reg_532_pp0_iter3_reg <= exitcond_flatten_reg_532_pp0_iter2_reg;
-                linebuf_5_load_reg_620_pp0_iter2_reg <= linebuf_5_load_reg_620;
-                linebuf_5_load_reg_620_pp0_iter3_reg <= linebuf_5_load_reg_620_pp0_iter2_reg;
-                linebuf_8_load_reg_625_pp0_iter2_reg <= linebuf_8_load_reg_625;
-                tmp2_reg_635_pp0_iter2_reg <= tmp2_reg_635;
-                tmp2_reg_635_pp0_iter3_reg <= tmp2_reg_635_pp0_iter2_reg;
-                tmp2_reg_635_pp0_iter4_reg <= tmp2_reg_635_pp0_iter3_reg;
-                tmp3_reg_640_pp0_iter2_reg <= tmp3_reg_640;
-                tmp3_reg_640_pp0_iter3_reg <= tmp3_reg_640_pp0_iter2_reg;
-                tmp3_reg_640_pp0_iter4_reg <= tmp3_reg_640_pp0_iter3_reg;
-                tmp7_reg_645_pp0_iter2_reg <= tmp7_reg_645;
-                tmp7_reg_645_pp0_iter3_reg <= tmp7_reg_645_pp0_iter2_reg;
-                tmp_8_i_i_mid2_reg_541_pp0_iter2_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter1_reg;
-                tmp_8_i_i_mid2_reg_541_pp0_iter3_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter2_reg;
-                tmp_8_i_i_mid2_reg_541_pp0_iter4_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter3_reg;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                filt1_read_reg_517 <= filt1_dout;
-                filt2_read_reg_522 <= filt2_dout;
-                height_read_reg_506 <= height_dout;
-                vconv_xlim_loc_read_reg_511 <= vconv_xlim_loc_dout;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then
-                linebuf_0_addr_reg_550 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_1_addr_reg_556 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_2_addr_reg_562 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_3_addr_reg_568 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_4_addr_reg_574 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_5_addr_reg_580 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_6_addr_reg_586 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_7_addr_reg_592 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_8_addr_reg_598 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_9_addr_reg_604 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                tmp_8_i_i_mid2_reg_541 <= tmp_8_i_i_mid2_fu_410_p3;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then
-                linebuf_5_load_reg_620 <= linebuf_5_q0;
-                linebuf_8_load_reg_625 <= linebuf_8_q0;
-                linebuf_9_load_reg_630 <= linebuf_9_q0;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then
-                tmp2_reg_635 <= tmp2_fu_446_p2;
-                tmp3_reg_640 <= tmp3_fu_458_p2;
-                tmp7_reg_645 <= tmp7_fu_464_p2;
-                tmp_1_reg_615 <= hconv_V_dout;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter3_reg = ap_const_lv1_0))) then
-                tmp5_reg_665 <= tmp5_fu_491_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter2_reg = ap_const_lv1_0))) then
-                tmp8_reg_660 <= tmp8_fu_482_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter1_reg = ap_const_lv1_0))) then
-                tmp_30_9_i_i_reg_650 <= tmp_30_9_i_i_fu_470_p2;
-                tmp_30_i_i_reg_655 <= tmp_30_i_i_fu_474_p2;
-            end if;
-        end if;
-    end process;
-
-    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter5, exitcond_flatten_fu_373_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter4)
-    begin
-        case ap_CS_fsm is
-            when ap_ST_fsm_state1 => 
-                if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                    ap_NS_fsm <= ap_ST_fsm_state2;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_state1;
-                end if;
-            when ap_ST_fsm_state2 => 
-                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-            when ap_ST_fsm_pp0_stage0 => 
-                if ((not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) and not(((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1))))) then
-                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-                elsif ((((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)) or ((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1)))) then
-                    ap_NS_fsm <= ap_ST_fsm_state9;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-                end if;
-            when ap_ST_fsm_state9 => 
-                ap_NS_fsm <= ap_ST_fsm_state1;
-            when others =>  
-                ap_NS_fsm <= "XXXX";
-        end case;
-    end process;
-    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
-    ap_CS_fsm_state1 <= ap_CS_fsm(0);
-    ap_CS_fsm_state2 <= ap_CS_fsm(1);
-    ap_CS_fsm_state9 <= ap_CS_fsm(3);
-
-    ap_block_pp0_assign_proc : process(ap_CS_fsm, ap_block_pp0_stage0_subdone)
-    begin
-                ap_block_pp0 <= ((ap_ST_fsm_pp0_stage0 = ap_CS_fsm) and (ap_const_boolean_1 = ap_block_pp0_stage0_subdone));
-    end process;
-
-        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_pp0_stage0_01001_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
-    begin
-                ap_block_pp0_stage0_01001 <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
-    end process;
-
-
-    ap_block_pp0_stage0_11001_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
-    begin
-                ap_block_pp0_stage0_11001 <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
-    end process;
-
-
-    ap_block_pp0_stage0_subdone_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
-    begin
-                ap_block_pp0_stage0_subdone <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
-    end process;
-
-
-    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
-    begin
-                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
-    end process;
-
-        ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_state4_pp0_stage0_iter1_assign_proc : process(hconv_V_empty_n, exitcond_flatten_reg_532)
-    begin
-                ap_block_state4_pp0_stage0_iter1 <= ((hconv_V_empty_n = ap_const_logic_0) and (exitcond_flatten_reg_532 = ap_const_lv1_0));
-    end process;
-
-        ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-        ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-        ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_state8_pp0_stage0_iter5_assign_proc : process(vconv_V_full_n, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
-    begin
-                ap_block_state8_pp0_stage0_iter5 <= ((vconv_V_full_n = ap_const_logic_0) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1));
-    end process;
-
-
-    ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-        if ((exitcond_flatten_fu_373_p2 = ap_const_lv1_1)) then 
-            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
-        else 
-            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state9)
-    begin
-        if ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
-            ap_done <= ap_const_logic_1;
-        else 
-            ap_done <= ap_done_reg;
-        end if; 
-    end process;
-
-
-    ap_enable_operation_44_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_44 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_46_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_46 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_48_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_48 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_50_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_50 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_52_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_52 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_54_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_54 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_56_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_56 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_58_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_58 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_60_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_60 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_62_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_62 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_66_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_66 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_67_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_67 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_68_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_68 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_69_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_69 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_70_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_70 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_71_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_71 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_72_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_72 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_73_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_73 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_74_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_74 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_75_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_75 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_76_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_76 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_77_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_77 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_78_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_78 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_79_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_79 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_80_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_80 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_81_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_81 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_82_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_82 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_83_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_83 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_84_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_84 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_89_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_89 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
-
-    ap_enable_state3_pp0_iter0_stage0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0)
-    begin
-                ap_enable_state3_pp0_iter0_stage0 <= ((ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0));
-    end process;
-
-
-    ap_enable_state4_pp0_iter1_stage0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
-    begin
-                ap_enable_state4_pp0_iter1_stage0 <= ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0));
-    end process;
-
-
-    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
-    begin
-        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            ap_idle <= ap_const_logic_1;
-        else 
-            ap_idle <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4)
-    begin
-        if (((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then 
-            ap_idle_pp0 <= ap_const_logic_1;
-        else 
-            ap_idle_pp0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_ready_assign_proc : process(ap_CS_fsm_state9)
-    begin
-        if ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
-            ap_ready <= ap_const_logic_1;
-        else 
-            ap_ready <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    bound_fu_358_p0 <= bound_fu_358_p00(32 - 1 downto 0);
-    bound_fu_358_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(vconv_xlim_loc_read_reg_511),64));
-    bound_fu_358_p1 <= bound_fu_358_p10(32 - 1 downto 0);
-    bound_fu_358_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(height_read_reg_506),64));
-    bound_fu_358_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_358_p0) * unsigned(bound_fu_358_p1), 64));
-    col1_0_i_i_i_mid2_fu_418_p3 <= 
-        col1_0_i_i_i_reg_330 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
-        col_fu_392_p2;
-    col_fu_392_p2 <= std_logic_vector(unsigned(col1_0_i_i_i_reg_330) + unsigned(ap_const_lv10_1));
-    exitcond_flatten_fu_373_p2 <= "1" when (indvar_flatten_reg_319 = bound_reg_527) else "0";
-
-    filt1_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt1_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_blk_n <= filt1_empty_n;
-        else 
-            filt1_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    filt1_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_read <= ap_const_logic_1;
-        else 
-            filt1_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    filt2_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt2_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_blk_n <= filt2_empty_n;
-        else 
-            filt2_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    filt2_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_read <= ap_const_logic_1;
-        else 
-            filt2_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    hconv_V_blk_n_assign_proc : process(hconv_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_flatten_reg_532)
-    begin
-        if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
-            hconv_V_blk_n <= hconv_V_empty_n;
-        else 
-            hconv_V_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    hconv_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            hconv_V_read <= ap_const_logic_1;
-        else 
-            hconv_V_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    height_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_blk_n <= height_empty_n;
-        else 
-            height_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    height_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_out_blk_n <= height_out_full_n;
-        else 
-            height_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    height_out_din <= height_dout;
-
-    height_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_out_write <= ap_const_logic_1;
-        else 
-            height_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    height_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_read <= ap_const_logic_1;
-        else 
-            height_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    indvar_flatten_next_fu_378_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_319) + unsigned(ap_const_lv64_1));
-    linebuf_0_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_0_address1 <= linebuf_0_addr_reg_550;
-
-    linebuf_0_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_0_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_0_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_0_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_0_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_0_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_0_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_0_we1 <= ap_const_logic_1;
-        else 
-            linebuf_0_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_1_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_1_address1 <= linebuf_1_addr_reg_556;
-
-    linebuf_1_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_1_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_1_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_1_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_1_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_1_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_1_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_1_we1 <= ap_const_logic_1;
-        else 
-            linebuf_1_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_2_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_2_address1 <= linebuf_2_addr_reg_562;
-
-    linebuf_2_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_2_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_2_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_2_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_2_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_2_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_2_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_2_we1 <= ap_const_logic_1;
-        else 
-            linebuf_2_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_3_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_3_address1 <= linebuf_3_addr_reg_568;
-
-    linebuf_3_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_3_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_3_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_3_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_3_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_3_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_3_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_3_we1 <= ap_const_logic_1;
-        else 
-            linebuf_3_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_4_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_4_address1 <= linebuf_4_addr_reg_574;
-
-    linebuf_4_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_4_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_4_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_4_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_4_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_4_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_4_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_4_we1 <= ap_const_logic_1;
-        else 
-            linebuf_4_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_5_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_5_address1 <= linebuf_5_addr_reg_580;
-
-    linebuf_5_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_5_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_5_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_5_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_5_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_5_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_5_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_5_we1 <= ap_const_logic_1;
-        else 
-            linebuf_5_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_6_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_6_address1 <= linebuf_6_addr_reg_586;
-
-    linebuf_6_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_6_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_6_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_6_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_6_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_6_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_6_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_6_we1 <= ap_const_logic_1;
-        else 
-            linebuf_6_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_7_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_7_address1 <= linebuf_7_addr_reg_592;
-
-    linebuf_7_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_7_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_7_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_7_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_7_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_7_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_7_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_7_we1 <= ap_const_logic_1;
-        else 
-            linebuf_7_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_8_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_8_address1 <= linebuf_8_addr_reg_598;
-
-    linebuf_8_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_8_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_8_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_8_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_8_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_8_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_8_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_8_we1 <= ap_const_logic_1;
-        else 
-            linebuf_8_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_9_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_9_address1 <= linebuf_9_addr_reg_604;
-
-    linebuf_9_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_9_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_9_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_9_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_9_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_9_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_9_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_9_we1 <= ap_const_logic_1;
-        else 
-            linebuf_9_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    row2_0_i_cast_i_i_fu_364_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row2_0_i_i_i_reg_341),32));
-    row2_0_i_i_i_mid2_fu_384_p3 <= 
-        row2_0_i_i_i_reg_341 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
-        ap_const_lv10_0;
-    row_fu_440_p2 <= std_logic_vector(unsigned(row2_0_i_i_i_mid2_fu_384_p3) + unsigned(ap_const_lv10_1));
-    tmp1_fu_496_p2 <= std_logic_vector(unsigned(tmp3_reg_640_pp0_iter4_reg) + unsigned(tmp2_reg_635_pp0_iter4_reg));
-    tmp2_fu_446_p2 <= std_logic_vector(unsigned(linebuf_0_q0) + unsigned(linebuf_1_q0));
-    tmp3_fu_458_p2 <= std_logic_vector(unsigned(tmp4_fu_452_p2) + unsigned(linebuf_2_q0));
-    tmp4_fu_452_p2 <= std_logic_vector(unsigned(linebuf_3_q0) + unsigned(linebuf_4_q0));
-    tmp5_fu_491_p2 <= std_logic_vector(unsigned(tmp8_reg_660) + unsigned(tmp6_fu_487_p2));
-    tmp6_fu_487_p2 <= std_logic_vector(unsigned(tmp7_reg_645_pp0_iter3_reg) + unsigned(linebuf_5_load_reg_620_pp0_iter3_reg));
-    tmp7_fu_464_p2 <= std_logic_vector(unsigned(linebuf_6_q0) + unsigned(linebuf_7_q0));
-    tmp8_fu_482_p2 <= std_logic_vector(unsigned(tmp9_fu_478_p2) + unsigned(linebuf_8_load_reg_625_pp0_iter2_reg));
-    tmp9_fu_478_p2 <= std_logic_vector(unsigned(tmp_30_9_i_i_reg_650) + unsigned(tmp_30_i_i_reg_655));
-    tmp_11_i_i_fu_368_p2 <= "1" when (signed(row2_0_i_cast_i_i_fu_364_p1) < signed(vconv_xlim_loc_read_reg_511)) else "0";
-    tmp_16_i_i_fu_426_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row2_0_i_i_i_mid2_fu_384_p3),64));
-    tmp_30_9_i_i_fu_470_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt1_read_reg_517) * signed(linebuf_9_load_reg_630))), 32));
-    tmp_30_i_i_fu_474_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt2_read_reg_522) * signed(tmp_1_reg_615))), 32));
-    tmp_8_i_i_fu_404_p2 <= "1" when (unsigned(col1_0_i_i_i_reg_330) > unsigned(ap_const_lv10_9)) else "0";
-    tmp_8_i_i_mid1_fu_398_p2 <= "1" when (unsigned(col_fu_392_p2) > unsigned(ap_const_lv10_9)) else "0";
-    tmp_8_i_i_mid2_fu_410_p3 <= 
-        tmp_8_i_i_fu_404_p2 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
-        tmp_8_i_i_mid1_fu_398_p2;
-
-    vconv_V_blk_n_assign_proc : process(vconv_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
-    begin
-        if (((ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
-            vconv_V_blk_n <= vconv_V_full_n;
-        else 
-            vconv_V_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    vconv_V_din <= std_logic_vector(unsigned(tmp5_reg_665) + unsigned(tmp1_fu_496_p2));
-
-    vconv_V_write_assign_proc : process(ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1))) then 
-            vconv_V_write <= ap_const_logic_1;
-        else 
-            vconv_V_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    vconv_xlim_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            vconv_xlim_loc_blk_n <= vconv_xlim_loc_empty_n;
-        else 
-            vconv_xlim_loc_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    vconv_xlim_loc_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            vconv_xlim_loc_out_blk_n <= vconv_xlim_loc_out_full_n;
-        else 
-            vconv_xlim_loc_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    vconv_xlim_loc_out_din <= vconv_xlim_loc_dout;
-
-    vconv_xlim_loc_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            vconv_xlim_loc_out_write <= ap_const_logic_1;
-        else 
-            vconv_xlim_loc_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    vconv_xlim_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            vconv_xlim_loc_read <= ap_const_logic_1;
-        else 
-            vconv_xlim_loc_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-end behav;

ip_repo_sources/packaging/src/Loop_VConvH_proc_linebuf_0.vhd

@@ -1,132 +0,0 @@
--- ==============================================================
--- File generated on Wed Jun 26 16:53:30 CEST 2019
--- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
--- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
--- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--- ==============================================================
---
-library ieee; 
-use ieee.std_logic_1164.all; 
-use ieee.std_logic_unsigned.all;
-
-entity Loop_VConvH_proc_linebuf_0_ram is 
-    generic(
-            MEM_TYPE    : string := "block"; 
-            DWIDTH     : integer := 32; 
-            AWIDTH     : integer := 10; 
-            MEM_SIZE    : integer := 672
-    ); 
-    port (
-          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
-          ce0       : in std_logic; 
-          q0        : out std_logic_vector(DWIDTH-1 downto 0);
-          addr1     : in std_logic_vector(AWIDTH-1 downto 0); 
-          ce1       : in std_logic; 
-          d1        : in std_logic_vector(DWIDTH-1 downto 0); 
-          we1       : in std_logic; 
-          clk        : in std_logic 
-    ); 
-end entity; 
-
-
-architecture rtl of Loop_VConvH_proc_linebuf_0_ram is 
-
-signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
-type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
-shared variable ram : mem_array := (others=>(others=>'0'));
-
-attribute syn_ramstyle : string; 
-attribute syn_ramstyle of ram : variable is "block_ram";
-attribute ram_style : string;
-attribute ram_style of ram : variable is MEM_TYPE;
-
-begin 
-
-
-memory_access_guard_0: process (addr0) 
-begin
-      addr0_tmp <= addr0;
---synthesis translate_off
-      if (CONV_INTEGER(addr0) > mem_size-1) then
-           addr0_tmp <= (others => '0');
-      else 
-           addr0_tmp <= addr0;
-      end if;
---synthesis translate_on
-end process;
-
-p_memory_access_0: process (clk)  
-begin 
-    if (clk'event and clk = '1') then
-        if (ce0 = '1') then 
-            q0 <= ram(CONV_INTEGER(addr0_tmp)); 
-        end if;
-    end if;
-end process;
-
-
-p_memory_access_1: process (clk)  
-begin 
-    if (clk'event and clk = '1') then
-        if (ce1 = '1') then 
-            if (we1 = '1') then 
-                ram(CONV_INTEGER(addr1)) := d1; 
-            end if;
-        end if;
-    end if;
-end process;
-
-
-end rtl;
-
-Library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity Loop_VConvH_proc_linebuf_0 is
-    generic (
-        DataWidth : INTEGER := 32;
-        AddressRange : INTEGER := 672;
-        AddressWidth : INTEGER := 10);
-    port (
-        reset : IN STD_LOGIC;
-        clk : IN STD_LOGIC;
-        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
-        ce0 : IN STD_LOGIC;
-        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
-        address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
-        ce1 : IN STD_LOGIC;
-        we1 : IN STD_LOGIC;
-        d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
-end entity;
-
-architecture arch of Loop_VConvH_proc_linebuf_0 is
-    component Loop_VConvH_proc_linebuf_0_ram is
-        port (
-            clk : IN STD_LOGIC;
-            addr0 : IN STD_LOGIC_VECTOR;
-            ce0 : IN STD_LOGIC;
-            q0 : OUT STD_LOGIC_VECTOR;
-            addr1 : IN STD_LOGIC_VECTOR;
-            ce1 : IN STD_LOGIC;
-            we1 : IN STD_LOGIC;
-            d1 : IN STD_LOGIC_VECTOR);
-    end component;
-
-
-
-begin
-    Loop_VConvH_proc_linebuf_0_ram_U :  component Loop_VConvH_proc_linebuf_0_ram
-    port map (
-        clk => clk,
-        addr0 => address0,
-        ce0 => ce0,
-        q0 => q0,
-        addr1 => address1,
-        ce1 => ce1,
-        we1 => we1,
-        d1 => d1);
-
-end architecture;
-
-

ip_repo_sources/packaging/src/checksum.vhd

@@ -1,34 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_arith.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.myPackage.ALL;
-
-
-entity checksum is
-    generic(
-        busWidth : integer:=32);
-    Port ( clk : in STD_LOGIC;
-           reset : in STD_LOGIC;
-           enable : in STD_LOGIC;
-           dataIn : in std_logic_vector(busWidth-1 downto 0);
-           output : out std_logic_vector(busWidth-1 downto 0));
-end checksum;
-
-architecture Behavioral of checksum is
-    signal sum : unsigned(busWidth-1 downto 0);
-begin
-    main : process(clk, reset)
-        
-    begin
-        if(reset = '0') then
-            sum <= (others => '0');
-        elsif(rising_edge(clk)) then
-            if(enable = '1') then
-                sum <= sum + unsigned(dataIn);
-            end if;
-        end if;
-    end process;
-
-    output <= std_logic_vector(sum);
-end Behavioral;

ip_repo_sources/packaging/src/fifo_w32_d2_A.vhd

@@ -1,140 +0,0 @@
--- ==============================================================
--- File generated on Wed Jun 26 16:53:30 CEST 2019
--- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
--- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
--- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--- ==============================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity fifo_w32_d2_A_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 32;
-        ADDR_WIDTH : integer := 1;
-        DEPTH : integer := 2);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-end fifo_w32_d2_A_shiftReg;
-
-architecture rtl of fifo_w32_d2_A_shiftReg is
---constant DEPTH_WIDTH: integer := 16;
-type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-signal SRL_SIG : SRL_ARRAY;
-
-begin
-p_shift: process (clk)
-begin
-    if (clk'event and clk = '1') then
-        if (ce = '1') then
-            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
-        end if;
-    end if;
-end process;
-
-q <= SRL_SIG(conv_integer(a));
-
-end rtl;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-entity fifo_w32_d2_A is 
-    generic (
-        MEM_STYLE  : string := "shiftreg"; 
-        DATA_WIDTH : integer := 32;
-        ADDR_WIDTH : integer := 1;
-        DEPTH : integer := 2);
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_empty_n : OUT STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_read : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
-end entity;
-
-architecture rtl of fifo_w32_d2_A is
-
-    component fifo_w32_d2_A_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 32;
-        ADDR_WIDTH : integer := 1;
-        DEPTH : integer := 2);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-    end component;
-
-    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
-    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-    signal shiftReg_ce : STD_LOGIC;
-    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
-    signal internal_empty_n : STD_LOGIC := '0';
-    signal internal_full_n  : STD_LOGIC := '1';
-
-begin
-    if_empty_n <= internal_empty_n;
-    if_full_n <= internal_full_n;
-    shiftReg_data <= if_din;
-    if_dout <= shiftReg_q;
-
-    process (clk)
-    begin
-        if clk'event and clk = '1' then
-            if reset = '1' then
-                mOutPtr <= (others => '1');
-                internal_empty_n <= '0';
-                internal_full_n <= '1';
-            else
-                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
-                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
-                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2);
-                    if (mOutPtr = conv_std_logic_vector(0, 2)) then 
-                        internal_empty_n <= '0';
-                    end if;
-                    internal_full_n <= '1';
-                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
-                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
-                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2);
-                    internal_empty_n <= '1';
-                    if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then 
-                        internal_full_n <= '0';
-                    end if;
-                end if;
-            end if;
-        end if;
-    end process;
-
-    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
-    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
-
-    U_fifo_w32_d2_A_shiftReg : fifo_w32_d2_A_shiftReg
-    generic map (
-        DATA_WIDTH => DATA_WIDTH,
-        ADDR_WIDTH => ADDR_WIDTH,
-        DEPTH => DEPTH)
-    port map (
-        clk => clk,
-        data => shiftReg_data,
-        ce => shiftReg_ce,
-        a => shiftReg_addr,
-        q => shiftReg_q);
-
-end rtl;
-

ip_repo_sources/packaging/src/fifo_w32_d3_A.vhd

@@ -1,140 +0,0 @@
--- ==============================================================
--- File generated on Wed Jun 26 16:53:30 CEST 2019
--- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
--- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
--- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--- ==============================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity fifo_w32_d3_A_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 32;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-end fifo_w32_d3_A_shiftReg;
-
-architecture rtl of fifo_w32_d3_A_shiftReg is
---constant DEPTH_WIDTH: integer := 16;
-type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-signal SRL_SIG : SRL_ARRAY;
-
-begin
-p_shift: process (clk)
-begin
-    if (clk'event and clk = '1') then
-        if (ce = '1') then
-            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
-        end if;
-    end if;
-end process;
-
-q <= SRL_SIG(conv_integer(a));
-
-end rtl;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-entity fifo_w32_d3_A is 
-    generic (
-        MEM_STYLE  : string := "shiftreg"; 
-        DATA_WIDTH : integer := 32;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_empty_n : OUT STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_read : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
-end entity;
-
-architecture rtl of fifo_w32_d3_A is
-
-    component fifo_w32_d3_A_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 32;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-    end component;
-
-    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
-    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-    signal shiftReg_ce : STD_LOGIC;
-    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
-    signal internal_empty_n : STD_LOGIC := '0';
-    signal internal_full_n  : STD_LOGIC := '1';
-
-begin
-    if_empty_n <= internal_empty_n;
-    if_full_n <= internal_full_n;
-    shiftReg_data <= if_din;
-    if_dout <= shiftReg_q;
-
-    process (clk)
-    begin
-        if clk'event and clk = '1' then
-            if reset = '1' then
-                mOutPtr <= (others => '1');
-                internal_empty_n <= '0';
-                internal_full_n <= '1';
-            else
-                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
-                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
-                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
-                    if (mOutPtr = conv_std_logic_vector(0, 3)) then 
-                        internal_empty_n <= '0';
-                    end if;
-                    internal_full_n <= '1';
-                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
-                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
-                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
-                    internal_empty_n <= '1';
-                    if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then 
-                        internal_full_n <= '0';
-                    end if;
-                end if;
-            end if;
-        end if;
-    end process;
-
-    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
-    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
-
-    U_fifo_w32_d3_A_shiftReg : fifo_w32_d3_A_shiftReg
-    generic map (
-        DATA_WIDTH => DATA_WIDTH,
-        ADDR_WIDTH => ADDR_WIDTH,
-        DEPTH => DEPTH)
-    port map (
-        clk => clk,
-        data => shiftReg_data,
-        ce => shiftReg_ce,
-        a => shiftReg_addr,
-        q => shiftReg_q);
-
-end rtl;
-

ip_repo_sources/packaging/src/filter11x11_strm.vhd

@@ -1,923 +0,0 @@
--- ==============================================================
--- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
--- Version: 2018.3
--- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--- 
--- ===========================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity filter11x11_strm is
-port (
-    width : IN STD_LOGIC_VECTOR (31 downto 0);
-    height : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt1 : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt2 : IN STD_LOGIC_VECTOR (31 downto 0);
-    src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
-    dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
-    ap_clk : IN STD_LOGIC;
-    ap_rst_n : IN STD_LOGIC;
-    ap_start : IN STD_LOGIC;
-    src_V_TVALID : IN STD_LOGIC;
-    src_V_TREADY : OUT STD_LOGIC;
-    dst_V_TVALID : OUT STD_LOGIC;
-    dst_V_TREADY : IN STD_LOGIC;
-    ap_done : OUT STD_LOGIC;
-    ap_ready : OUT STD_LOGIC;
-    ap_idle : OUT STD_LOGIC );
-end;
-
-
-architecture behav of filter11x11_strm is 
-    attribute CORE_GENERATION_INFO : STRING;
-    attribute CORE_GENERATION_INFO of behav : architecture is
-    "filter11x11_strm,hls_ip_2018_3,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7a100tcsg324-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.470000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=22,HLS_SYN_DSP=28,HLS_SYN_FF=3339,HLS_SYN_LUT=3643,HLS_VERSION=2018_3}";
-    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
-    constant ap_const_logic_1 : STD_LOGIC := '1';
-    constant ap_const_logic_0 : STD_LOGIC := '0';
-    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
-    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
-    constant ap_const_boolean_1 : BOOLEAN := true;
-
-    signal ap_rst_n_inv : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_ap_start : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_start_full_n : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_ap_done : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_ap_continue : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_ap_idle : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_ap_ready : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_start_out : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_start_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_width_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_width_out_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_width_out1_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_width_out1_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_height_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_height_out_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_height_out2_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_height_out2_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_filt1_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_filt1_out_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_filt1_out3_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_filt1_out3_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_filt2_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_filt2_out_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_filt2_out4_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_filt2_out4_write : STD_LOGIC;
-    signal Block_proc_U0_ap_start : STD_LOGIC;
-    signal Block_proc_U0_ap_done : STD_LOGIC;
-    signal Block_proc_U0_ap_continue : STD_LOGIC;
-    signal Block_proc_U0_ap_idle : STD_LOGIC;
-    signal Block_proc_U0_ap_ready : STD_LOGIC;
-    signal Block_proc_U0_start_out : STD_LOGIC;
-    signal Block_proc_U0_start_write : STD_LOGIC;
-    signal Block_proc_U0_width_read : STD_LOGIC;
-    signal Block_proc_U0_height_read : STD_LOGIC;
-    signal Block_proc_U0_width_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal Block_proc_U0_width_out_write : STD_LOGIC;
-    signal Block_proc_U0_height_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal Block_proc_U0_height_out_write : STD_LOGIC;
-    signal Block_proc_U0_vconv_xlim_out_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal Block_proc_U0_vconv_xlim_out_out_write : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_ap_start : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_ap_done : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_ap_continue : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_ap_idle : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_ap_ready : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_height_read : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_width_read : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_src_V_TREADY : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_filt1_read : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_filt2_read : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_hconv_V_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal Loop_HConvH_proc6_U0_hconv_V_write : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_ap_start : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_ap_done : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_ap_continue : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_ap_idle : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_ap_ready : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_height_read : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_vconv_xlim_loc_read : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_hconv_V_read : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_vconv_V_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal Loop_VConvH_proc_U0_vconv_V_write : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_filt1_read : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_filt2_read : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_height_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal Loop_VConvH_proc_U0_height_out_write : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_vconv_xlim_loc_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal Loop_VConvH_proc_U0_vconv_xlim_loc_out_write : STD_LOGIC;
-    signal Loop_Border_proc_U0_ap_start : STD_LOGIC;
-    signal Loop_Border_proc_U0_ap_done : STD_LOGIC;
-    signal Loop_Border_proc_U0_ap_continue : STD_LOGIC;
-    signal Loop_Border_proc_U0_ap_idle : STD_LOGIC;
-    signal Loop_Border_proc_U0_ap_ready : STD_LOGIC;
-    signal Loop_Border_proc_U0_width_read : STD_LOGIC;
-    signal Loop_Border_proc_U0_height_read : STD_LOGIC;
-    signal Loop_Border_proc_U0_dst_V_TDATA : STD_LOGIC_VECTOR (31 downto 0);
-    signal Loop_Border_proc_U0_dst_V_TVALID : STD_LOGIC;
-    signal Loop_Border_proc_U0_vconv_xlim_loc_read : STD_LOGIC;
-    signal Loop_Border_proc_U0_vconv_V_read : STD_LOGIC;
-    signal ap_sync_continue : STD_LOGIC;
-    signal width_c_full_n : STD_LOGIC;
-    signal width_c_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal width_c_empty_n : STD_LOGIC;
-    signal width_c155_full_n : STD_LOGIC;
-    signal width_c155_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal width_c155_empty_n : STD_LOGIC;
-    signal height_c_full_n : STD_LOGIC;
-    signal height_c_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal height_c_empty_n : STD_LOGIC;
-    signal height_c156_full_n : STD_LOGIC;
-    signal height_c156_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal height_c156_empty_n : STD_LOGIC;
-    signal filt1_c_full_n : STD_LOGIC;
-    signal filt1_c_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt1_c_empty_n : STD_LOGIC;
-    signal filt1_c157_full_n : STD_LOGIC;
-    signal filt1_c157_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt1_c157_empty_n : STD_LOGIC;
-    signal filt2_c_full_n : STD_LOGIC;
-    signal filt2_c_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt2_c_empty_n : STD_LOGIC;
-    signal filt2_c158_full_n : STD_LOGIC;
-    signal filt2_c158_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt2_c158_empty_n : STD_LOGIC;
-    signal width_c159_full_n : STD_LOGIC;
-    signal width_c159_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal width_c159_empty_n : STD_LOGIC;
-    signal height_c160_full_n : STD_LOGIC;
-    signal height_c160_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal height_c160_empty_n : STD_LOGIC;
-    signal vconv_xlim_loc_c_full_n : STD_LOGIC;
-    signal vconv_xlim_loc_c_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal vconv_xlim_loc_c_empty_n : STD_LOGIC;
-    signal hconv_V_full_n : STD_LOGIC;
-    signal hconv_V_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal hconv_V_empty_n : STD_LOGIC;
-    signal vconv_V_full_n : STD_LOGIC;
-    signal vconv_V_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal vconv_V_empty_n : STD_LOGIC;
-    signal height_c161_full_n : STD_LOGIC;
-    signal height_c161_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal height_c161_empty_n : STD_LOGIC;
-    signal vconv_xlim_loc_c162_full_n : STD_LOGIC;
-    signal vconv_xlim_loc_c162_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal vconv_xlim_loc_c162_empty_n : STD_LOGIC;
-    signal ap_sync_done : STD_LOGIC;
-    signal ap_sync_ready : STD_LOGIC;
-    signal ap_sync_reg_filter11x11_strm_ent_U0_ap_ready : STD_LOGIC := '0';
-    signal ap_sync_filter11x11_strm_ent_U0_ap_ready : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_ap_ready_count : STD_LOGIC_VECTOR (1 downto 0) := "00";
-    signal ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready : STD_LOGIC := '0';
-    signal ap_sync_Loop_HConvH_proc6_U0_ap_ready : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_ap_ready_count : STD_LOGIC_VECTOR (1 downto 0) := "00";
-    signal start_for_Block_proc_U0_din : STD_LOGIC_VECTOR (0 downto 0);
-    signal start_for_Block_proc_U0_full_n : STD_LOGIC;
-    signal start_for_Block_proc_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
-    signal start_for_Block_proc_U0_empty_n : STD_LOGIC;
-    signal start_for_Loop_VConvH_proc_U0_din : STD_LOGIC_VECTOR (0 downto 0);
-    signal start_for_Loop_VConvH_proc_U0_full_n : STD_LOGIC;
-    signal start_for_Loop_VConvH_proc_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
-    signal start_for_Loop_VConvH_proc_U0_empty_n : STD_LOGIC;
-    signal start_for_Loop_Border_proc_U0_din : STD_LOGIC_VECTOR (0 downto 0);
-    signal start_for_Loop_Border_proc_U0_full_n : STD_LOGIC;
-    signal start_for_Loop_Border_proc_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
-    signal start_for_Loop_Border_proc_U0_empty_n : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_start_full_n : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_start_write : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_start_full_n : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_start_write : STD_LOGIC;
-    signal Loop_Border_proc_U0_start_full_n : STD_LOGIC;
-    signal Loop_Border_proc_U0_start_write : STD_LOGIC;
-
-    component filter11x11_strm_ent IS
-    port (
-        ap_clk : IN STD_LOGIC;
-        ap_rst : IN STD_LOGIC;
-        ap_start : IN STD_LOGIC;
-        start_full_n : IN STD_LOGIC;
-        ap_done : OUT STD_LOGIC;
-        ap_continue : IN STD_LOGIC;
-        ap_idle : OUT STD_LOGIC;
-        ap_ready : OUT STD_LOGIC;
-        start_out : OUT STD_LOGIC;
-        start_write : OUT STD_LOGIC;
-        width : IN STD_LOGIC_VECTOR (31 downto 0);
-        height : IN STD_LOGIC_VECTOR (31 downto 0);
-        filt1 : IN STD_LOGIC_VECTOR (31 downto 0);
-        filt2 : IN STD_LOGIC_VECTOR (31 downto 0);
-        width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        width_out_full_n : IN STD_LOGIC;
-        width_out_write : OUT STD_LOGIC;
-        width_out1_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        width_out1_full_n : IN STD_LOGIC;
-        width_out1_write : OUT STD_LOGIC;
-        height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        height_out_full_n : IN STD_LOGIC;
-        height_out_write : OUT STD_LOGIC;
-        height_out2_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        height_out2_full_n : IN STD_LOGIC;
-        height_out2_write : OUT STD_LOGIC;
-        filt1_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        filt1_out_full_n : IN STD_LOGIC;
-        filt1_out_write : OUT STD_LOGIC;
-        filt1_out3_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        filt1_out3_full_n : IN STD_LOGIC;
-        filt1_out3_write : OUT STD_LOGIC;
-        filt2_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        filt2_out_full_n : IN STD_LOGIC;
-        filt2_out_write : OUT STD_LOGIC;
-        filt2_out4_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        filt2_out4_full_n : IN STD_LOGIC;
-        filt2_out4_write : OUT STD_LOGIC );
-    end component;
-
-
-    component Block_proc IS
-    port (
-        ap_clk : IN STD_LOGIC;
-        ap_rst : IN STD_LOGIC;
-        ap_start : IN STD_LOGIC;
-        start_full_n : IN STD_LOGIC;
-        ap_done : OUT STD_LOGIC;
-        ap_continue : IN STD_LOGIC;
-        ap_idle : OUT STD_LOGIC;
-        ap_ready : OUT STD_LOGIC;
-        start_out : OUT STD_LOGIC;
-        start_write : OUT STD_LOGIC;
-        width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        width_empty_n : IN STD_LOGIC;
-        width_read : OUT STD_LOGIC;
-        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        height_empty_n : IN STD_LOGIC;
-        height_read : OUT STD_LOGIC;
-        width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        width_out_full_n : IN STD_LOGIC;
-        width_out_write : OUT STD_LOGIC;
-        height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        height_out_full_n : IN STD_LOGIC;
-        height_out_write : OUT STD_LOGIC;
-        vconv_xlim_out_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        vconv_xlim_out_out_full_n : IN STD_LOGIC;
-        vconv_xlim_out_out_write : OUT STD_LOGIC );
-    end component;
-
-
-    component Loop_HConvH_proc6 IS
-    port (
-        ap_clk : IN STD_LOGIC;
-        ap_rst : IN STD_LOGIC;
-        ap_start : IN STD_LOGIC;
-        ap_done : OUT STD_LOGIC;
-        ap_continue : IN STD_LOGIC;
-        ap_idle : OUT STD_LOGIC;
-        ap_ready : OUT STD_LOGIC;
-        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        height_empty_n : IN STD_LOGIC;
-        height_read : OUT STD_LOGIC;
-        width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        width_empty_n : IN STD_LOGIC;
-        width_read : OUT STD_LOGIC;
-        src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
-        src_V_TVALID : IN STD_LOGIC;
-        src_V_TREADY : OUT STD_LOGIC;
-        filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        filt1_empty_n : IN STD_LOGIC;
-        filt1_read : OUT STD_LOGIC;
-        filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        filt2_empty_n : IN STD_LOGIC;
-        filt2_read : OUT STD_LOGIC;
-        hconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        hconv_V_full_n : IN STD_LOGIC;
-        hconv_V_write : OUT STD_LOGIC );
-    end component;
-
-
-    component Loop_VConvH_proc IS
-    port (
-        ap_clk : IN STD_LOGIC;
-        ap_rst : IN STD_LOGIC;
-        ap_start : IN STD_LOGIC;
-        ap_done : OUT STD_LOGIC;
-        ap_continue : IN STD_LOGIC;
-        ap_idle : OUT STD_LOGIC;
-        ap_ready : OUT STD_LOGIC;
-        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        height_empty_n : IN STD_LOGIC;
-        height_read : OUT STD_LOGIC;
-        vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        vconv_xlim_loc_empty_n : IN STD_LOGIC;
-        vconv_xlim_loc_read : OUT STD_LOGIC;
-        hconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        hconv_V_empty_n : IN STD_LOGIC;
-        hconv_V_read : OUT STD_LOGIC;
-        vconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        vconv_V_full_n : IN STD_LOGIC;
-        vconv_V_write : OUT STD_LOGIC;
-        filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        filt1_empty_n : IN STD_LOGIC;
-        filt1_read : OUT STD_LOGIC;
-        filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        filt2_empty_n : IN STD_LOGIC;
-        filt2_read : OUT STD_LOGIC;
-        height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        height_out_full_n : IN STD_LOGIC;
-        height_out_write : OUT STD_LOGIC;
-        vconv_xlim_loc_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        vconv_xlim_loc_out_full_n : IN STD_LOGIC;
-        vconv_xlim_loc_out_write : OUT STD_LOGIC );
-    end component;
-
-
-    component Loop_Border_proc IS
-    port (
-        ap_clk : IN STD_LOGIC;
-        ap_rst : IN STD_LOGIC;
-        ap_start : IN STD_LOGIC;
-        ap_done : OUT STD_LOGIC;
-        ap_continue : IN STD_LOGIC;
-        ap_idle : OUT STD_LOGIC;
-        ap_ready : OUT STD_LOGIC;
-        width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        width_empty_n : IN STD_LOGIC;
-        width_read : OUT STD_LOGIC;
-        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        height_empty_n : IN STD_LOGIC;
-        height_read : OUT STD_LOGIC;
-        dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
-        dst_V_TVALID : OUT STD_LOGIC;
-        dst_V_TREADY : IN STD_LOGIC;
-        vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        vconv_xlim_loc_empty_n : IN STD_LOGIC;
-        vconv_xlim_loc_read : OUT STD_LOGIC;
-        vconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        vconv_V_empty_n : IN STD_LOGIC;
-        vconv_V_read : OUT STD_LOGIC );
-    end component;
-
-
-    component fifo_w32_d2_A IS
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR (31 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR (31 downto 0);
-        if_empty_n : OUT STD_LOGIC;
-        if_read : IN STD_LOGIC );
-    end component;
-
-
-    component fifo_w32_d3_A IS
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR (31 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR (31 downto 0);
-        if_empty_n : OUT STD_LOGIC;
-        if_read : IN STD_LOGIC );
-    end component;
-
-
-    component start_for_Block_proc_U0 IS
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR (0 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
-        if_empty_n : OUT STD_LOGIC;
-        if_read : IN STD_LOGIC );
-    end component;
-
-
-    component start_for_Loop_VConvH_proc_U0 IS
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR (0 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
-        if_empty_n : OUT STD_LOGIC;
-        if_read : IN STD_LOGIC );
-    end component;
-
-
-    component start_for_Loop_Border_proc_U0 IS
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR (0 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
-        if_empty_n : OUT STD_LOGIC;
-        if_read : IN STD_LOGIC );
-    end component;
-
-
-
-begin
-    filter11x11_strm_ent_U0 : component filter11x11_strm_ent
-    port map (
-        ap_clk => ap_clk,
-        ap_rst => ap_rst_n_inv,
-        ap_start => filter11x11_strm_ent_U0_ap_start,
-        start_full_n => filter11x11_strm_ent_U0_start_full_n,
-        ap_done => filter11x11_strm_ent_U0_ap_done,
-        ap_continue => filter11x11_strm_ent_U0_ap_continue,
-        ap_idle => filter11x11_strm_ent_U0_ap_idle,
-        ap_ready => filter11x11_strm_ent_U0_ap_ready,
-        start_out => filter11x11_strm_ent_U0_start_out,
-        start_write => filter11x11_strm_ent_U0_start_write,
-        width => width,
-        height => height,
-        filt1 => filt1,
-        filt2 => filt2,
-        width_out_din => filter11x11_strm_ent_U0_width_out_din,
-        width_out_full_n => width_c_full_n,
-        width_out_write => filter11x11_strm_ent_U0_width_out_write,
-        width_out1_din => filter11x11_strm_ent_U0_width_out1_din,
-        width_out1_full_n => width_c155_full_n,
-        width_out1_write => filter11x11_strm_ent_U0_width_out1_write,
-        height_out_din => filter11x11_strm_ent_U0_height_out_din,
-        height_out_full_n => height_c_full_n,
-        height_out_write => filter11x11_strm_ent_U0_height_out_write,
-        height_out2_din => filter11x11_strm_ent_U0_height_out2_din,
-        height_out2_full_n => height_c156_full_n,
-        height_out2_write => filter11x11_strm_ent_U0_height_out2_write,
-        filt1_out_din => filter11x11_strm_ent_U0_filt1_out_din,
-        filt1_out_full_n => filt1_c_full_n,
-        filt1_out_write => filter11x11_strm_ent_U0_filt1_out_write,
-        filt1_out3_din => filter11x11_strm_ent_U0_filt1_out3_din,
-        filt1_out3_full_n => filt1_c157_full_n,
-        filt1_out3_write => filter11x11_strm_ent_U0_filt1_out3_write,
-        filt2_out_din => filter11x11_strm_ent_U0_filt2_out_din,
-        filt2_out_full_n => filt2_c_full_n,
-        filt2_out_write => filter11x11_strm_ent_U0_filt2_out_write,
-        filt2_out4_din => filter11x11_strm_ent_U0_filt2_out4_din,
-        filt2_out4_full_n => filt2_c158_full_n,
-        filt2_out4_write => filter11x11_strm_ent_U0_filt2_out4_write);
-
-    Block_proc_U0 : component Block_proc
-    port map (
-        ap_clk => ap_clk,
-        ap_rst => ap_rst_n_inv,
-        ap_start => Block_proc_U0_ap_start,
-        start_full_n => start_for_Loop_Border_proc_U0_full_n,
-        ap_done => Block_proc_U0_ap_done,
-        ap_continue => Block_proc_U0_ap_continue,
-        ap_idle => Block_proc_U0_ap_idle,
-        ap_ready => Block_proc_U0_ap_ready,
-        start_out => Block_proc_U0_start_out,
-        start_write => Block_proc_U0_start_write,
-        width_dout => width_c_dout,
-        width_empty_n => width_c_empty_n,
-        width_read => Block_proc_U0_width_read,
-        height_dout => height_c_dout,
-        height_empty_n => height_c_empty_n,
-        height_read => Block_proc_U0_height_read,
-        width_out_din => Block_proc_U0_width_out_din,
-        width_out_full_n => width_c159_full_n,
-        width_out_write => Block_proc_U0_width_out_write,
-        height_out_din => Block_proc_U0_height_out_din,
-        height_out_full_n => height_c160_full_n,
-        height_out_write => Block_proc_U0_height_out_write,
-        vconv_xlim_out_out_din => Block_proc_U0_vconv_xlim_out_out_din,
-        vconv_xlim_out_out_full_n => vconv_xlim_loc_c_full_n,
-        vconv_xlim_out_out_write => Block_proc_U0_vconv_xlim_out_out_write);
-
-    Loop_HConvH_proc6_U0 : component Loop_HConvH_proc6
-    port map (
-        ap_clk => ap_clk,
-        ap_rst => ap_rst_n_inv,
-        ap_start => Loop_HConvH_proc6_U0_ap_start,
-        ap_done => Loop_HConvH_proc6_U0_ap_done,
-        ap_continue => Loop_HConvH_proc6_U0_ap_continue,
-        ap_idle => Loop_HConvH_proc6_U0_ap_idle,
-        ap_ready => Loop_HConvH_proc6_U0_ap_ready,
-        height_dout => height_c156_dout,
-        height_empty_n => height_c156_empty_n,
-        height_read => Loop_HConvH_proc6_U0_height_read,
-        width_dout => width_c155_dout,
-        width_empty_n => width_c155_empty_n,
-        width_read => Loop_HConvH_proc6_U0_width_read,
-        src_V_TDATA => src_V_TDATA,
-        src_V_TVALID => src_V_TVALID,
-        src_V_TREADY => Loop_HConvH_proc6_U0_src_V_TREADY,
-        filt1_dout => filt1_c_dout,
-        filt1_empty_n => filt1_c_empty_n,
-        filt1_read => Loop_HConvH_proc6_U0_filt1_read,
-        filt2_dout => filt2_c_dout,
-        filt2_empty_n => filt2_c_empty_n,
-        filt2_read => Loop_HConvH_proc6_U0_filt2_read,
-        hconv_V_din => Loop_HConvH_proc6_U0_hconv_V_din,
-        hconv_V_full_n => hconv_V_full_n,
-        hconv_V_write => Loop_HConvH_proc6_U0_hconv_V_write);
-
-    Loop_VConvH_proc_U0 : component Loop_VConvH_proc
-    port map (
-        ap_clk => ap_clk,
-        ap_rst => ap_rst_n_inv,
-        ap_start => Loop_VConvH_proc_U0_ap_start,
-        ap_done => Loop_VConvH_proc_U0_ap_done,
-        ap_continue => Loop_VConvH_proc_U0_ap_continue,
-        ap_idle => Loop_VConvH_proc_U0_ap_idle,
-        ap_ready => Loop_VConvH_proc_U0_ap_ready,
-        height_dout => height_c160_dout,
-        height_empty_n => height_c160_empty_n,
-        height_read => Loop_VConvH_proc_U0_height_read,
-        vconv_xlim_loc_dout => vconv_xlim_loc_c_dout,
-        vconv_xlim_loc_empty_n => vconv_xlim_loc_c_empty_n,
-        vconv_xlim_loc_read => Loop_VConvH_proc_U0_vconv_xlim_loc_read,
-        hconv_V_dout => hconv_V_dout,
-        hconv_V_empty_n => hconv_V_empty_n,
-        hconv_V_read => Loop_VConvH_proc_U0_hconv_V_read,
-        vconv_V_din => Loop_VConvH_proc_U0_vconv_V_din,
-        vconv_V_full_n => vconv_V_full_n,
-        vconv_V_write => Loop_VConvH_proc_U0_vconv_V_write,
-        filt1_dout => filt1_c157_dout,
-        filt1_empty_n => filt1_c157_empty_n,
-        filt1_read => Loop_VConvH_proc_U0_filt1_read,
-        filt2_dout => filt2_c158_dout,
-        filt2_empty_n => filt2_c158_empty_n,
-        filt2_read => Loop_VConvH_proc_U0_filt2_read,
-        height_out_din => Loop_VConvH_proc_U0_height_out_din,
-        height_out_full_n => height_c161_full_n,
-        height_out_write => Loop_VConvH_proc_U0_height_out_write,
-        vconv_xlim_loc_out_din => Loop_VConvH_proc_U0_vconv_xlim_loc_out_din,
-        vconv_xlim_loc_out_full_n => vconv_xlim_loc_c162_full_n,
-        vconv_xlim_loc_out_write => Loop_VConvH_proc_U0_vconv_xlim_loc_out_write);
-
-    Loop_Border_proc_U0 : component Loop_Border_proc
-    port map (
-        ap_clk => ap_clk,
-        ap_rst => ap_rst_n_inv,
-        ap_start => Loop_Border_proc_U0_ap_start,
-        ap_done => Loop_Border_proc_U0_ap_done,
-        ap_continue => Loop_Border_proc_U0_ap_continue,
-        ap_idle => Loop_Border_proc_U0_ap_idle,
-        ap_ready => Loop_Border_proc_U0_ap_ready,
-        width_dout => width_c159_dout,
-        width_empty_n => width_c159_empty_n,
-        width_read => Loop_Border_proc_U0_width_read,
-        height_dout => height_c161_dout,
-        height_empty_n => height_c161_empty_n,
-        height_read => Loop_Border_proc_U0_height_read,
-        dst_V_TDATA => Loop_Border_proc_U0_dst_V_TDATA,
-        dst_V_TVALID => Loop_Border_proc_U0_dst_V_TVALID,
-        dst_V_TREADY => dst_V_TREADY,
-        vconv_xlim_loc_dout => vconv_xlim_loc_c162_dout,
-        vconv_xlim_loc_empty_n => vconv_xlim_loc_c162_empty_n,
-        vconv_xlim_loc_read => Loop_Border_proc_U0_vconv_xlim_loc_read,
-        vconv_V_dout => vconv_V_dout,
-        vconv_V_empty_n => vconv_V_empty_n,
-        vconv_V_read => Loop_Border_proc_U0_vconv_V_read);
-
-    width_c_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_width_out_din,
-        if_full_n => width_c_full_n,
-        if_write => filter11x11_strm_ent_U0_width_out_write,
-        if_dout => width_c_dout,
-        if_empty_n => width_c_empty_n,
-        if_read => Block_proc_U0_width_read);
-
-    width_c155_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_width_out1_din,
-        if_full_n => width_c155_full_n,
-        if_write => filter11x11_strm_ent_U0_width_out1_write,
-        if_dout => width_c155_dout,
-        if_empty_n => width_c155_empty_n,
-        if_read => Loop_HConvH_proc6_U0_width_read);
-
-    height_c_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_height_out_din,
-        if_full_n => height_c_full_n,
-        if_write => filter11x11_strm_ent_U0_height_out_write,
-        if_dout => height_c_dout,
-        if_empty_n => height_c_empty_n,
-        if_read => Block_proc_U0_height_read);
-
-    height_c156_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_height_out2_din,
-        if_full_n => height_c156_full_n,
-        if_write => filter11x11_strm_ent_U0_height_out2_write,
-        if_dout => height_c156_dout,
-        if_empty_n => height_c156_empty_n,
-        if_read => Loop_HConvH_proc6_U0_height_read);
-
-    filt1_c_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_filt1_out_din,
-        if_full_n => filt1_c_full_n,
-        if_write => filter11x11_strm_ent_U0_filt1_out_write,
-        if_dout => filt1_c_dout,
-        if_empty_n => filt1_c_empty_n,
-        if_read => Loop_HConvH_proc6_U0_filt1_read);
-
-    filt1_c157_U : component fifo_w32_d3_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_filt1_out3_din,
-        if_full_n => filt1_c157_full_n,
-        if_write => filter11x11_strm_ent_U0_filt1_out3_write,
-        if_dout => filt1_c157_dout,
-        if_empty_n => filt1_c157_empty_n,
-        if_read => Loop_VConvH_proc_U0_filt1_read);
-
-    filt2_c_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_filt2_out_din,
-        if_full_n => filt2_c_full_n,
-        if_write => filter11x11_strm_ent_U0_filt2_out_write,
-        if_dout => filt2_c_dout,
-        if_empty_n => filt2_c_empty_n,
-        if_read => Loop_HConvH_proc6_U0_filt2_read);
-
-    filt2_c158_U : component fifo_w32_d3_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_filt2_out4_din,
-        if_full_n => filt2_c158_full_n,
-        if_write => filter11x11_strm_ent_U0_filt2_out4_write,
-        if_dout => filt2_c158_dout,
-        if_empty_n => filt2_c158_empty_n,
-        if_read => Loop_VConvH_proc_U0_filt2_read);
-
-    width_c159_U : component fifo_w32_d3_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => Block_proc_U0_width_out_din,
-        if_full_n => width_c159_full_n,
-        if_write => Block_proc_U0_width_out_write,
-        if_dout => width_c159_dout,
-        if_empty_n => width_c159_empty_n,
-        if_read => Loop_Border_proc_U0_width_read);
-
-    height_c160_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => Block_proc_U0_height_out_din,
-        if_full_n => height_c160_full_n,
-        if_write => Block_proc_U0_height_out_write,
-        if_dout => height_c160_dout,
-        if_empty_n => height_c160_empty_n,
-        if_read => Loop_VConvH_proc_U0_height_read);
-
-    vconv_xlim_loc_c_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => Block_proc_U0_vconv_xlim_out_out_din,
-        if_full_n => vconv_xlim_loc_c_full_n,
-        if_write => Block_proc_U0_vconv_xlim_out_out_write,
-        if_dout => vconv_xlim_loc_c_dout,
-        if_empty_n => vconv_xlim_loc_c_empty_n,
-        if_read => Loop_VConvH_proc_U0_vconv_xlim_loc_read);
-
-    hconv_V_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => Loop_HConvH_proc6_U0_hconv_V_din,
-        if_full_n => hconv_V_full_n,
-        if_write => Loop_HConvH_proc6_U0_hconv_V_write,
-        if_dout => hconv_V_dout,
-        if_empty_n => hconv_V_empty_n,
-        if_read => Loop_VConvH_proc_U0_hconv_V_read);
-
-    vconv_V_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => Loop_VConvH_proc_U0_vconv_V_din,
-        if_full_n => vconv_V_full_n,
-        if_write => Loop_VConvH_proc_U0_vconv_V_write,
-        if_dout => vconv_V_dout,
-        if_empty_n => vconv_V_empty_n,
-        if_read => Loop_Border_proc_U0_vconv_V_read);
-
-    height_c161_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => Loop_VConvH_proc_U0_height_out_din,
-        if_full_n => height_c161_full_n,
-        if_write => Loop_VConvH_proc_U0_height_out_write,
-        if_dout => height_c161_dout,
-        if_empty_n => height_c161_empty_n,
-        if_read => Loop_Border_proc_U0_height_read);
-
-    vconv_xlim_loc_c162_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => Loop_VConvH_proc_U0_vconv_xlim_loc_out_din,
-        if_full_n => vconv_xlim_loc_c162_full_n,
-        if_write => Loop_VConvH_proc_U0_vconv_xlim_loc_out_write,
-        if_dout => vconv_xlim_loc_c162_dout,
-        if_empty_n => vconv_xlim_loc_c162_empty_n,
-        if_read => Loop_Border_proc_U0_vconv_xlim_loc_read);
-
-    start_for_Block_proc_U0_U : component start_for_Block_proc_U0
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => start_for_Block_proc_U0_din,
-        if_full_n => start_for_Block_proc_U0_full_n,
-        if_write => filter11x11_strm_ent_U0_start_write,
-        if_dout => start_for_Block_proc_U0_dout,
-        if_empty_n => start_for_Block_proc_U0_empty_n,
-        if_read => Block_proc_U0_ap_ready);
-
-    start_for_Loop_VConvH_proc_U0_U : component start_for_Loop_VConvH_proc_U0
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => start_for_Loop_VConvH_proc_U0_din,
-        if_full_n => start_for_Loop_VConvH_proc_U0_full_n,
-        if_write => filter11x11_strm_ent_U0_start_write,
-        if_dout => start_for_Loop_VConvH_proc_U0_dout,
-        if_empty_n => start_for_Loop_VConvH_proc_U0_empty_n,
-        if_read => Loop_VConvH_proc_U0_ap_ready);
-
-    start_for_Loop_Border_proc_U0_U : component start_for_Loop_Border_proc_U0
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => start_for_Loop_Border_proc_U0_din,
-        if_full_n => start_for_Loop_Border_proc_U0_full_n,
-        if_write => Block_proc_U0_start_write,
-        if_dout => start_for_Loop_Border_proc_U0_dout,
-        if_empty_n => start_for_Loop_Border_proc_U0_empty_n,
-        if_read => Loop_Border_proc_U0_ap_ready);
-
-
-
-
-
-    ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst_n_inv = '1') then
-                ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready <= ap_const_logic_0;
-            else
-                if (((ap_sync_ready and ap_start) = ap_const_logic_1)) then 
-                    ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready <= ap_const_logic_0;
-                else 
-                    ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready <= ap_sync_Loop_HConvH_proc6_U0_ap_ready;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_sync_reg_filter11x11_strm_ent_U0_ap_ready_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst_n_inv = '1') then
-                ap_sync_reg_filter11x11_strm_ent_U0_ap_ready <= ap_const_logic_0;
-            else
-                if (((ap_sync_ready and ap_start) = ap_const_logic_1)) then 
-                    ap_sync_reg_filter11x11_strm_ent_U0_ap_ready <= ap_const_logic_0;
-                else 
-                    ap_sync_reg_filter11x11_strm_ent_U0_ap_ready <= ap_sync_filter11x11_strm_ent_U0_ap_ready;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    Loop_HConvH_proc6_U0_ap_ready_count_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_logic_0 = Loop_HConvH_proc6_U0_ap_ready) and (ap_sync_ready = ap_const_logic_1))) then 
-                Loop_HConvH_proc6_U0_ap_ready_count <= std_logic_vector(unsigned(Loop_HConvH_proc6_U0_ap_ready_count) - unsigned(ap_const_lv2_1));
-            elsif (((ap_const_logic_1 = Loop_HConvH_proc6_U0_ap_ready) and (ap_sync_ready = ap_const_logic_0))) then 
-                Loop_HConvH_proc6_U0_ap_ready_count <= std_logic_vector(unsigned(Loop_HConvH_proc6_U0_ap_ready_count) + unsigned(ap_const_lv2_1));
-            end if; 
-        end if;
-    end process;
-
-    filter11x11_strm_ent_U0_ap_ready_count_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_sync_ready = ap_const_logic_1) and (filter11x11_strm_ent_U0_ap_ready = ap_const_logic_0))) then 
-                filter11x11_strm_ent_U0_ap_ready_count <= std_logic_vector(unsigned(filter11x11_strm_ent_U0_ap_ready_count) - unsigned(ap_const_lv2_1));
-            elsif (((ap_sync_ready = ap_const_logic_0) and (filter11x11_strm_ent_U0_ap_ready = ap_const_logic_1))) then 
-                filter11x11_strm_ent_U0_ap_ready_count <= std_logic_vector(unsigned(filter11x11_strm_ent_U0_ap_ready_count) + unsigned(ap_const_lv2_1));
-            end if; 
-        end if;
-    end process;
-    Block_proc_U0_ap_continue <= ap_const_logic_1;
-    Block_proc_U0_ap_start <= start_for_Block_proc_U0_empty_n;
-    Loop_Border_proc_U0_ap_continue <= ap_const_logic_1;
-    Loop_Border_proc_U0_ap_start <= start_for_Loop_Border_proc_U0_empty_n;
-    Loop_Border_proc_U0_start_full_n <= ap_const_logic_1;
-    Loop_Border_proc_U0_start_write <= ap_const_logic_0;
-    Loop_HConvH_proc6_U0_ap_continue <= ap_const_logic_1;
-    Loop_HConvH_proc6_U0_ap_start <= ((ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready xor ap_const_logic_1) and ap_start);
-    Loop_HConvH_proc6_U0_start_full_n <= ap_const_logic_1;
-    Loop_HConvH_proc6_U0_start_write <= ap_const_logic_0;
-    Loop_VConvH_proc_U0_ap_continue <= ap_const_logic_1;
-    Loop_VConvH_proc_U0_ap_start <= start_for_Loop_VConvH_proc_U0_empty_n;
-    Loop_VConvH_proc_U0_start_full_n <= ap_const_logic_1;
-    Loop_VConvH_proc_U0_start_write <= ap_const_logic_0;
-    ap_done <= Loop_Border_proc_U0_ap_done;
-    ap_idle <= (filter11x11_strm_ent_U0_ap_idle and Loop_VConvH_proc_U0_ap_idle and Loop_HConvH_proc6_U0_ap_idle and Loop_Border_proc_U0_ap_idle and Block_proc_U0_ap_idle);
-    ap_ready <= ap_sync_ready;
-
-    ap_rst_n_inv_assign_proc : process(ap_rst_n)
-    begin
-                ap_rst_n_inv <= not(ap_rst_n);
-    end process;
-
-    ap_sync_Loop_HConvH_proc6_U0_ap_ready <= (ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready or Loop_HConvH_proc6_U0_ap_ready);
-    ap_sync_continue <= ap_const_logic_1;
-    ap_sync_done <= Loop_Border_proc_U0_ap_done;
-    ap_sync_filter11x11_strm_ent_U0_ap_ready <= (filter11x11_strm_ent_U0_ap_ready or ap_sync_reg_filter11x11_strm_ent_U0_ap_ready);
-    ap_sync_ready <= (ap_sync_filter11x11_strm_ent_U0_ap_ready and ap_sync_Loop_HConvH_proc6_U0_ap_ready);
-    dst_V_TDATA <= Loop_Border_proc_U0_dst_V_TDATA;
-    dst_V_TVALID <= Loop_Border_proc_U0_dst_V_TVALID;
-    filter11x11_strm_ent_U0_ap_continue <= ap_const_logic_1;
-    filter11x11_strm_ent_U0_ap_start <= ((ap_sync_reg_filter11x11_strm_ent_U0_ap_ready xor ap_const_logic_1) and ap_start);
-    filter11x11_strm_ent_U0_start_full_n <= (start_for_Loop_VConvH_proc_U0_full_n and start_for_Block_proc_U0_full_n);
-    src_V_TREADY <= Loop_HConvH_proc6_U0_src_V_TREADY;
-    start_for_Block_proc_U0_din <= (0=>ap_const_logic_1, others=>'-');
-    start_for_Loop_Border_proc_U0_din <= (0=>ap_const_logic_1, others=>'-');
-    start_for_Loop_VConvH_proc_U0_din <= (0=>ap_const_logic_1, others=>'-');
-end behav;

ip_repo_sources/packaging/src/filter11x11_strm_ent.vhd

@@ -1,368 +0,0 @@
--- ==============================================================
--- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
--- Version: 2018.3
--- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--- 
--- ===========================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity filter11x11_strm_ent is
-port (
-    ap_clk : IN STD_LOGIC;
-    ap_rst : IN STD_LOGIC;
-    ap_start : IN STD_LOGIC;
-    start_full_n : IN STD_LOGIC;
-    ap_done : OUT STD_LOGIC;
-    ap_continue : IN STD_LOGIC;
-    ap_idle : OUT STD_LOGIC;
-    ap_ready : OUT STD_LOGIC;
-    start_out : OUT STD_LOGIC;
-    start_write : OUT STD_LOGIC;
-    width : IN STD_LOGIC_VECTOR (31 downto 0);
-    height : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt1 : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt2 : IN STD_LOGIC_VECTOR (31 downto 0);
-    width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    width_out_full_n : IN STD_LOGIC;
-    width_out_write : OUT STD_LOGIC;
-    width_out1_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    width_out1_full_n : IN STD_LOGIC;
-    width_out1_write : OUT STD_LOGIC;
-    height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    height_out_full_n : IN STD_LOGIC;
-    height_out_write : OUT STD_LOGIC;
-    height_out2_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    height_out2_full_n : IN STD_LOGIC;
-    height_out2_write : OUT STD_LOGIC;
-    filt1_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    filt1_out_full_n : IN STD_LOGIC;
-    filt1_out_write : OUT STD_LOGIC;
-    filt1_out3_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    filt1_out3_full_n : IN STD_LOGIC;
-    filt1_out3_write : OUT STD_LOGIC;
-    filt2_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    filt2_out_full_n : IN STD_LOGIC;
-    filt2_out_write : OUT STD_LOGIC;
-    filt2_out4_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    filt2_out4_full_n : IN STD_LOGIC;
-    filt2_out4_write : OUT STD_LOGIC );
-end;
-
-
-architecture behav of filter11x11_strm_ent is 
-    constant ap_const_logic_1 : STD_LOGIC := '1';
-    constant ap_const_logic_0 : STD_LOGIC := '0';
-    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
-    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
-    constant ap_const_boolean_1 : BOOLEAN := true;
-
-    signal real_start : STD_LOGIC;
-    signal start_once_reg : STD_LOGIC := '0';
-    signal ap_done_reg : STD_LOGIC := '0';
-    signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
-    attribute fsm_encoding : string;
-    attribute fsm_encoding of ap_CS_fsm : signal is "none";
-    signal ap_CS_fsm_state1 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
-    signal internal_ap_ready : STD_LOGIC;
-    signal width_out_blk_n : STD_LOGIC;
-    signal width_out1_blk_n : STD_LOGIC;
-    signal height_out_blk_n : STD_LOGIC;
-    signal height_out2_blk_n : STD_LOGIC;
-    signal filt1_out_blk_n : STD_LOGIC;
-    signal filt1_out3_blk_n : STD_LOGIC;
-    signal filt2_out_blk_n : STD_LOGIC;
-    signal filt2_out4_blk_n : STD_LOGIC;
-    signal ap_block_state1 : BOOLEAN;
-    signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
-
-
-begin
-
-
-
-
-    ap_CS_fsm_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_CS_fsm <= ap_ST_fsm_state1;
-            else
-                ap_CS_fsm <= ap_NS_fsm;
-            end if;
-        end if;
-    end process;
-
-
-    ap_done_reg_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_done_reg <= ap_const_logic_0;
-            else
-                if ((ap_continue = ap_const_logic_1)) then 
-                    ap_done_reg <= ap_const_logic_0;
-                elsif ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-                    ap_done_reg <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    start_once_reg_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                start_once_reg <= ap_const_logic_0;
-            else
-                if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then 
-                    start_once_reg <= ap_const_logic_1;
-                elsif ((internal_ap_ready = ap_const_logic_1)) then 
-                    start_once_reg <= ap_const_logic_0;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        case ap_CS_fsm is
-            when ap_ST_fsm_state1 => 
-                ap_NS_fsm <= ap_ST_fsm_state1;
-            when others =>  
-                ap_NS_fsm <= "X";
-        end case;
-    end process;
-    ap_CS_fsm_state1 <= ap_CS_fsm(0);
-
-    ap_block_state1_assign_proc : process(real_start, ap_done_reg, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-                ap_block_state1 <= ((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
-    end process;
-
-
-    ap_done_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            ap_done <= ap_const_logic_1;
-        else 
-            ap_done <= ap_done_reg;
-        end if; 
-    end process;
-
-
-    ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
-    begin
-        if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            ap_idle <= ap_const_logic_1;
-        else 
-            ap_idle <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    ap_ready <= internal_ap_ready;
-
-    filt1_out3_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, filt1_out3_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_out3_blk_n <= filt1_out3_full_n;
-        else 
-            filt1_out3_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    filt1_out3_din <= filt1;
-
-    filt1_out3_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_out3_write <= ap_const_logic_1;
-        else 
-            filt1_out3_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    filt1_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, filt1_out_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_out_blk_n <= filt1_out_full_n;
-        else 
-            filt1_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    filt1_out_din <= filt1;
-
-    filt1_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_out_write <= ap_const_logic_1;
-        else 
-            filt1_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    filt2_out4_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, filt2_out4_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_out4_blk_n <= filt2_out4_full_n;
-        else 
-            filt2_out4_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    filt2_out4_din <= filt2;
-
-    filt2_out4_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_out4_write <= ap_const_logic_1;
-        else 
-            filt2_out4_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    filt2_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, filt2_out_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_out_blk_n <= filt2_out_full_n;
-        else 
-            filt2_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    filt2_out_din <= filt2;
-
-    filt2_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_out_write <= ap_const_logic_1;
-        else 
-            filt2_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    height_out2_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, height_out2_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_out2_blk_n <= height_out2_full_n;
-        else 
-            height_out2_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    height_out2_din <= height;
-
-    height_out2_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_out2_write <= ap_const_logic_1;
-        else 
-            height_out2_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    height_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, height_out_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_out_blk_n <= height_out_full_n;
-        else 
-            height_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    height_out_din <= height;
-
-    height_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_out_write <= ap_const_logic_1;
-        else 
-            height_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    internal_ap_ready_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            internal_ap_ready <= ap_const_logic_1;
-        else 
-            internal_ap_ready <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
-    begin
-        if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then 
-            real_start <= ap_const_logic_0;
-        else 
-            real_start <= ap_start;
-        end if; 
-    end process;
-
-    start_out <= real_start;
-
-    start_write_assign_proc : process(real_start, start_once_reg)
-    begin
-        if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then 
-            start_write <= ap_const_logic_1;
-        else 
-            start_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    width_out1_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out1_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_out1_blk_n <= width_out1_full_n;
-        else 
-            width_out1_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    width_out1_din <= width;
-
-    width_out1_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_out1_write <= ap_const_logic_1;
-        else 
-            width_out1_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    width_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_out_blk_n <= width_out_full_n;
-        else 
-            width_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    width_out_din <= width;
-
-    width_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_out_write <= ap_const_logic_1;
-        else 
-            width_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-end behav;

ip_repo_sources/packaging/src/mac.vhd

@@ -1,42 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_arith.ALL;
-use IEEE.std_logic_textio.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.myPackage.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity mac is
-    Port ( inputs : in dataVector;
-           weights : in dataVector;
-           bias : in dataType;
-           outp : out dataType;
-           clk: in STD_LOGIC);
-end mac;
-
-architecture Behavioral of mac is
-
-begin
-
-MAIN: process(clk)
-    variable sum : dataType;
-begin
-    if rising_edge(clk) then
-        sum :=  bias;
-        for i in 0 to nNodes-1 loop
-            sum := signed(sum) + conv_integer(signed(inputs(i))) * conv_integer(signed(weights(i)));
-        end loop;
-        
-        outp <= sum;
-    end if;
-end process;
-
-end Behavioral;

ip_repo_sources/packaging/src/neuron.vhd

@@ -1,61 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity neuron is
-    Port (
-        inputs : in dataVector;
-        weights : in dataVector;
-        bias : in dataType;
-        start : in std_logic;
-        finished : out std_logic;
-        clk : in std_logic;
-        outp : out dataType);
-end neuron;
-
-architecture Behavioral of neuron is 
-
-component mac is
- port ( 
-   inputs : in dataVector;
-   weights : in dataVector;
-   bias : in dataType;
-   outp : out dataType;
-   clk : in std_logic);
-end component;
-
-component relu is
- port ( 
-   inp : in dataType;
-   clk : in std_logic;
-   outp : out dataType);
-end component;
-
-signal var1 : dataType;
-
-signal macFinished: std_logic;
-
-begin
-mac1: mac port map (
-    inputs => inputs,
-    weights => weights,
-    bias => bias,
-    outp => var1,
-    clk => clk
-);
-
-relu1: relu port map (
-    inp => var1,
-    clk => clk,
-    outp => outp
-);
-
-timing : process(clk)
-begin
-    if(rising_edge(clk)) then
-        macFinished <= start;
-        finished <= macFinished;
-    end if;
-end process;
-
-end Behavioral;

ip_repo_sources/packaging/src/parallelize.vhd

@@ -1,86 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity parallelize is
-    generic(
-        busWidth : integer:=8);
-    Port ( clk : in STD_LOGIC;
-           rst : in STD_LOGIC;
-           start : in STD_LOGIC;
-           dataIn : in std_logic_vector(busWidth-1 downto 0);
-           ready: out std_logic;
-           dataOutReset : in std_logic;
-           dataOut : out std_logic_vector(busWidth-1 downto 0);
-           finished : out STD_LOGIC);
-end parallelize;
-
-architecture Behavioral of parallelize is
-
-constant parallelInWidth : integer := (2*nNodes+1) * nBits;
-constant parallelOutWidth : integer := nBits;
-
-component shiftIn is
-    generic(
-        inWidth : integer := busWidth;
-        outWidth : integer := parallelInWidth);
-    Port ( clk : in STD_LOGIC;
-           sync_reset : in STD_LOGIC;
-           dataIn : in std_logic_vector(inWidth-1 downto 0);
-           dataOut : out std_logic_vector(outWidth-1 downto 0);
-           finished : out STD_LOGIC);
-end component;
-component neuron is
-    Port (
-        inputs : in dataVector;
-        weights : in dataVector;
-        bias : in dataType;
-        start : in std_logic;
-        finished : out std_logic;
-        clk : in std_logic;
-        outp : out dataType);
-end component;
-component shiftOut is
-    generic(
-        inWidth : integer := parallelOutWidth;
-        outWidth : integer := busWidth);
-    Port ( clk : in STD_LOGIC;
-           sync_reset : in STD_LOGIC;
-           dataIn : in std_logic_vector(inWidth-1 downto 0);
-           dataOut : out std_logic_vector(outWidth-1 downto 0);
-           finished : out STD_LOGIC);
-end component;
-
-signal dataInStorage : std_logic_vector(parallelInWidth-1 downto 0);
-signal dataOutStorage : std_logic_vector(parallelOutWidth-1 downto 0);
-signal shiftInFinished : std_logic;
-
-begin
-
-shiftIn1: shiftIn port map (
-    clk         => clk,
-    sync_reset  => start,
-    dataIn      => dataIn,
-    dataOut     => dataInStorage,
-    finished    => shiftInFinished
-);
-
-neuron1: neuron port map (
-    inputs  => to_dataVector(dataInStorage(parallelInWidth-1 downto (nNodes+1) * nBits)),
-    weights => to_dataVector(dataInStorage((nNodes+1) * nBits-1 downto nBits)),
-    bias    => dataInStorage(nBits-1 downto 0),
-    clk     => clk,
-    outp    => dataOutStorage,
-    start   => shiftInFinished,
-    finished=> ready
-);
-
-shiftOut1 : shiftOut port map (
-    clk         => clk,
-    sync_reset  => dataOutReset,
-    dataIn      => dataOutStorage,
-    dataOut     => dataOut,
-    finished    => finished
-);
-
-end Behavioral;

ip_repo_sources/packaging/src/relu.vhd

@@ -1,30 +0,0 @@
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_signed.all;
-use IEEE.std_logic_arith.all;
-use IEEE.math_real.all;
-use work.myPackage.ALL;
-
-entity relu is
-    Port ( inp : in dataType;
-           outp : out dataType;
-           clk: in STD_LOGIC );
-end relu;
-
-architecture Behavioral of relu is
-
-begin
-    calc : process(clk)
-    begin
-        if(rising_edge(clk)) then
-            if(signed(inp) > 0) then
-                outp <= inp;
-            else
-                outp <= (others => '0');
-            end if;
-            
-        end if;
-    end process;
-end Behavioral;

ip_repo_sources/packaging/src/start_for_Block_proc_U0.vhd

@@ -1,140 +0,0 @@
--- ==============================================================
--- File generated on Wed Jun 26 16:53:30 CEST 2019
--- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
--- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
--- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--- ==============================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity start_for_Block_proc_U0_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 1;
-        DEPTH : integer := 2);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-end start_for_Block_proc_U0_shiftReg;
-
-architecture rtl of start_for_Block_proc_U0_shiftReg is
---constant DEPTH_WIDTH: integer := 16;
-type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-signal SRL_SIG : SRL_ARRAY;
-
-begin
-p_shift: process (clk)
-begin
-    if (clk'event and clk = '1') then
-        if (ce = '1') then
-            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
-        end if;
-    end if;
-end process;
-
-q <= SRL_SIG(conv_integer(a));
-
-end rtl;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-entity start_for_Block_proc_U0 is 
-    generic (
-        MEM_STYLE  : string := "shiftreg"; 
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 1;
-        DEPTH : integer := 2);
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_empty_n : OUT STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_read : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
-end entity;
-
-architecture rtl of start_for_Block_proc_U0 is
-
-    component start_for_Block_proc_U0_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 1;
-        DEPTH : integer := 2);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-    end component;
-
-    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
-    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-    signal shiftReg_ce : STD_LOGIC;
-    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
-    signal internal_empty_n : STD_LOGIC := '0';
-    signal internal_full_n  : STD_LOGIC := '1';
-
-begin
-    if_empty_n <= internal_empty_n;
-    if_full_n <= internal_full_n;
-    shiftReg_data <= if_din;
-    if_dout <= shiftReg_q;
-
-    process (clk)
-    begin
-        if clk'event and clk = '1' then
-            if reset = '1' then
-                mOutPtr <= (others => '1');
-                internal_empty_n <= '0';
-                internal_full_n <= '1';
-            else
-                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
-                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
-                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2);
-                    if (mOutPtr = conv_std_logic_vector(0, 2)) then 
-                        internal_empty_n <= '0';
-                    end if;
-                    internal_full_n <= '1';
-                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
-                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
-                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2);
-                    internal_empty_n <= '1';
-                    if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then 
-                        internal_full_n <= '0';
-                    end if;
-                end if;
-            end if;
-        end if;
-    end process;
-
-    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
-    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
-
-    U_start_for_Block_proc_U0_shiftReg : start_for_Block_proc_U0_shiftReg
-    generic map (
-        DATA_WIDTH => DATA_WIDTH,
-        ADDR_WIDTH => ADDR_WIDTH,
-        DEPTH => DEPTH)
-    port map (
-        clk => clk,
-        data => shiftReg_data,
-        ce => shiftReg_ce,
-        a => shiftReg_addr,
-        q => shiftReg_q);
-
-end rtl;
-

ip_repo_sources/packaging/src/start_for_Loop_Border_proc_U0.vhd

@@ -1,140 +0,0 @@
--- ==============================================================
--- File generated on Wed Jun 26 16:53:30 CEST 2019
--- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
--- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
--- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--- ==============================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity start_for_Loop_Border_proc_U0_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-end start_for_Loop_Border_proc_U0_shiftReg;
-
-architecture rtl of start_for_Loop_Border_proc_U0_shiftReg is
---constant DEPTH_WIDTH: integer := 16;
-type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-signal SRL_SIG : SRL_ARRAY;
-
-begin
-p_shift: process (clk)
-begin
-    if (clk'event and clk = '1') then
-        if (ce = '1') then
-            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
-        end if;
-    end if;
-end process;
-
-q <= SRL_SIG(conv_integer(a));
-
-end rtl;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-entity start_for_Loop_Border_proc_U0 is 
-    generic (
-        MEM_STYLE  : string := "shiftreg"; 
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_empty_n : OUT STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_read : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
-end entity;
-
-architecture rtl of start_for_Loop_Border_proc_U0 is
-
-    component start_for_Loop_Border_proc_U0_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-    end component;
-
-    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
-    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-    signal shiftReg_ce : STD_LOGIC;
-    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
-    signal internal_empty_n : STD_LOGIC := '0';
-    signal internal_full_n  : STD_LOGIC := '1';
-
-begin
-    if_empty_n <= internal_empty_n;
-    if_full_n <= internal_full_n;
-    shiftReg_data <= if_din;
-    if_dout <= shiftReg_q;
-
-    process (clk)
-    begin
-        if clk'event and clk = '1' then
-            if reset = '1' then
-                mOutPtr <= (others => '1');
-                internal_empty_n <= '0';
-                internal_full_n <= '1';
-            else
-                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
-                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
-                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
-                    if (mOutPtr = conv_std_logic_vector(0, 3)) then 
-                        internal_empty_n <= '0';
-                    end if;
-                    internal_full_n <= '1';
-                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
-                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
-                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
-                    internal_empty_n <= '1';
-                    if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then 
-                        internal_full_n <= '0';
-                    end if;
-                end if;
-            end if;
-        end if;
-    end process;
-
-    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
-    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
-
-    U_start_for_Loop_Border_proc_U0_shiftReg : start_for_Loop_Border_proc_U0_shiftReg
-    generic map (
-        DATA_WIDTH => DATA_WIDTH,
-        ADDR_WIDTH => ADDR_WIDTH,
-        DEPTH => DEPTH)
-    port map (
-        clk => clk,
-        data => shiftReg_data,
-        ce => shiftReg_ce,
-        a => shiftReg_addr,
-        q => shiftReg_q);
-
-end rtl;
-

ip_repo_sources/packaging/src/start_for_Loop_VConvH_proc_U0.vhd

@@ -1,140 +0,0 @@
--- ==============================================================
--- File generated on Wed Jun 26 16:53:30 CEST 2019
--- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
--- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
--- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--- ==============================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity start_for_Loop_VConvH_proc_U0_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-end start_for_Loop_VConvH_proc_U0_shiftReg;
-
-architecture rtl of start_for_Loop_VConvH_proc_U0_shiftReg is
---constant DEPTH_WIDTH: integer := 16;
-type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-signal SRL_SIG : SRL_ARRAY;
-
-begin
-p_shift: process (clk)
-begin
-    if (clk'event and clk = '1') then
-        if (ce = '1') then
-            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
-        end if;
-    end if;
-end process;
-
-q <= SRL_SIG(conv_integer(a));
-
-end rtl;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-entity start_for_Loop_VConvH_proc_U0 is 
-    generic (
-        MEM_STYLE  : string := "shiftreg"; 
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_empty_n : OUT STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_read : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
-end entity;
-
-architecture rtl of start_for_Loop_VConvH_proc_U0 is
-
-    component start_for_Loop_VConvH_proc_U0_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-    end component;
-
-    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
-    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-    signal shiftReg_ce : STD_LOGIC;
-    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
-    signal internal_empty_n : STD_LOGIC := '0';
-    signal internal_full_n  : STD_LOGIC := '1';
-
-begin
-    if_empty_n <= internal_empty_n;
-    if_full_n <= internal_full_n;
-    shiftReg_data <= if_din;
-    if_dout <= shiftReg_q;
-
-    process (clk)
-    begin
-        if clk'event and clk = '1' then
-            if reset = '1' then
-                mOutPtr <= (others => '1');
-                internal_empty_n <= '0';
-                internal_full_n <= '1';
-            else
-                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
-                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
-                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
-                    if (mOutPtr = conv_std_logic_vector(0, 3)) then 
-                        internal_empty_n <= '0';
-                    end if;
-                    internal_full_n <= '1';
-                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
-                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
-                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
-                    internal_empty_n <= '1';
-                    if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then 
-                        internal_full_n <= '0';
-                    end if;
-                end if;
-            end if;
-        end if;
-    end process;
-
-    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
-    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
-
-    U_start_for_Loop_VConvH_proc_U0_shiftReg : start_for_Loop_VConvH_proc_U0_shiftReg
-    generic map (
-        DATA_WIDTH => DATA_WIDTH,
-        ADDR_WIDTH => ADDR_WIDTH,
-        DEPTH => DEPTH)
-    port map (
-        clk => clk,
-        data => shiftReg_data,
-        ce => shiftReg_ce,
-        a => shiftReg_addr,
-        q => shiftReg_q);
-
-end rtl;
-

ip_repo_sources/packaging/src/tb_behav.wcfg

@@ -1,128 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<wave_config>
-   <wave_state>
-   </wave_state>
-   <db_ref_list>
-      <db_ref path="tb_behav.wdb" id="1">
-         <top_modules>
-            <top_module name="mypackage" />
-            <top_module name="tb" />
-         </top_modules>
-      </db_ref>
-   </db_ref_list>
-   <zoom_setting>
-      <ZoomStartTime time="325423333333fs"></ZoomStartTime>
-      <ZoomEndTime time="559023333334fs"></ZoomEndTime>
-      <Cursor1Time time="520090000000fs"></Cursor1Time>
-   </zoom_setting>
-   <column_width_setting>
-      <NameColumnWidth column_width="201"></NameColumnWidth>
-      <ValueColumnWidth column_width="72"></ValueColumnWidth>
-   </column_width_setting>
-   <WVObjectSize size="19" />
-   <wvobject fp_name="/tb/dut/clk" type="logic">
-      <obj_property name="ElementShortName">clk</obj_property>
-      <obj_property name="ObjectShortName">clk</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/rst" type="logic">
-      <obj_property name="ElementShortName">rst</obj_property>
-      <obj_property name="ObjectShortName">rst</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/inputStream" type="array">
-      <obj_property name="ElementShortName">inputStream[31:0]</obj_property>
-      <obj_property name="ObjectShortName">inputStream[31:0]</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/inputReadEnable" type="logic">
-      <obj_property name="ElementShortName">inputReadEnable</obj_property>
-      <obj_property name="ObjectShortName">inputReadEnable</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/inputReadReady" type="logic">
-      <obj_property name="ElementShortName">inputReadReady</obj_property>
-      <obj_property name="ObjectShortName">inputReadReady</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/inputEmpty" type="logic">
-      <obj_property name="ElementShortName">inputEmpty</obj_property>
-      <obj_property name="ObjectShortName">inputEmpty</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/outputStream" type="array">
-      <obj_property name="ElementShortName">outputStream[31:0]</obj_property>
-      <obj_property name="ObjectShortName">outputStream[31:0]</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/outputWriteEnable" type="logic">
-      <obj_property name="ElementShortName">outputWriteEnable</obj_property>
-      <obj_property name="ObjectShortName">outputWriteEnable</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/outputWriteReady" type="logic">
-      <obj_property name="ElementShortName">outputWriteReady</obj_property>
-      <obj_property name="ObjectShortName">outputWriteReady</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/outputFull" type="logic">
-      <obj_property name="ElementShortName">outputFull</obj_property>
-      <obj_property name="ObjectShortName">outputFull</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/outHeaderCounter" type="other">
-      <obj_property name="ElementShortName">outHeaderCounter</obj_property>
-      <obj_property name="ObjectShortName">outHeaderCounter</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/state" type="other">
-      <obj_property name="ElementShortName">state</obj_property>
-      <obj_property name="ObjectShortName">state</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/errorCode" type="array">
-      <obj_property name="ElementShortName">errorCode[3:0]</obj_property>
-      <obj_property name="ObjectShortName">errorCode[3:0]</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/mux1/done" type="logic">
-      <obj_property name="ElementShortName">done</obj_property>
-      <obj_property name="ObjectShortName">done</obj_property>
-   </wvobject>
-   <wvobject fp_name="group61" type="group">
-      <obj_property name="label">dummy</obj_property>
-      <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="isExpanded"></obj_property>
-      <wvobject fp_name="/tb/dut/mux1/dummy/start" type="logic">
-         <obj_property name="ElementShortName">start</obj_property>
-         <obj_property name="ObjectShortName">start</obj_property>
-      </wvobject>
-      <wvobject fp_name="/tb/dut/mux1/dummy/ready" type="logic">
-         <obj_property name="ElementShortName">ready</obj_property>
-         <obj_property name="ObjectShortName">ready</obj_property>
-      </wvobject>
-      <wvobject fp_name="/tb/dut/mux1/dummy/idle" type="logic">
-         <obj_property name="ElementShortName">idle</obj_property>
-         <obj_property name="ObjectShortName">idle</obj_property>
-      </wvobject>
-      <wvobject fp_name="/tb/dut/mux1/dummy/srcValid" type="logic">
-         <obj_property name="ElementShortName">srcValid</obj_property>
-         <obj_property name="ObjectShortName">srcValid</obj_property>
-      </wvobject>
-      <wvobject fp_name="/tb/dut/mux1/dummy/srcReady" type="logic">
-         <obj_property name="ElementShortName">srcReady</obj_property>
-         <obj_property name="ObjectShortName">srcReady</obj_property>
-      </wvobject>
-      <wvobject fp_name="/tb/dut/mux1/dummy/dstValid" type="logic">
-         <obj_property name="ElementShortName">dstValid</obj_property>
-         <obj_property name="ObjectShortName">dstValid</obj_property>
-      </wvobject>
-      <wvobject fp_name="/tb/dut/mux1/dummy/dstReady" type="logic">
-         <obj_property name="ElementShortName">dstReady</obj_property>
-         <obj_property name="ObjectShortName">dstReady</obj_property>
-      </wvobject>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/csSum" type="array">
-      <obj_property name="ElementShortName">csSum[31:0]</obj_property>
-      <obj_property name="ObjectShortName">csSum[31:0]</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/csEnable" type="logic">
-      <obj_property name="ElementShortName">csEnable</obj_property>
-      <obj_property name="ObjectShortName">csEnable</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/csOutSum" type="array">
-      <obj_property name="ElementShortName">csOutSum[31:0]</obj_property>
-      <obj_property name="ObjectShortName">csOutSum[31:0]</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb/dut/csOutReset" type="logic">
-      <obj_property name="ElementShortName">csOutReset</obj_property>
-      <obj_property name="ObjectShortName">csOutReset</obj_property>
-   </wvobject>
-</wave_config>

ip_repo_sources/xgui/packaging_v1_0.tcl

@@ -1,25 +0,0 @@
-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
-  ipgui::add_param $IPINST -name "Component_Name"
-  #Adding Page
-  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
-  ipgui::add_param $IPINST -name "busWidth" -parent ${Page_0}
-
-
-}
-
-proc update_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
-	# Procedure called to update busWidth when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
-	# Procedure called to validate busWidth
-	return true
-}
-
-
-proc update_MODELPARAM_VALUE.busWidth { MODELPARAM_VALUE.busWidth PARAM_VALUE.busWidth } {
-	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.busWidth}] ${MODELPARAM_VALUE.busWidth}
-}
-

ip_repo_sources/xgui/packaging_v3_0.tcl

@@ -1,25 +0,0 @@
-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
-  ipgui::add_param $IPINST -name "Component_Name"
-  #Adding Page
-  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
-  ipgui::add_param $IPINST -name "busWidth" -parent ${Page_0}
-
-
-}
-
-proc update_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
-	# Procedure called to update busWidth when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
-	# Procedure called to validate busWidth
-	return true
-}
-
-
-proc update_MODELPARAM_VALUE.busWidth { MODELPARAM_VALUE.busWidth PARAM_VALUE.busWidth } {
-	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.busWidth}] ${MODELPARAM_VALUE.busWidth}
-}
-

min_area_pfile.tmp

@@ -1,21 +0,0 @@
-10000
-1
-3
-4
-1
-0
-0
-9
-8
-8
-8
-8
-256
-256
-256
-256
-0
-0
-0
-0
-0

sources/complete-bd.bd/design_1.tcl

@@ -37,6 +37,13 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
 # To test this script, run the following commands from Vivado Tcl console:
 # source design_1_script.tcl
 
+
+# The design that will be created by this Tcl script contains the following 
+# module references:
+# packaging
+
+# Please add the sources of those modules before sourcing this Tcl script.
+
 # If there is no project opened, this script will create a
 # project, but make sure you do not have an existing project
 # <./myproj/project_1.xpr> in the current working folder.
@@ -127,7 +134,6 @@ xilinx.com:ip:c_counter_binary:12.0\
 xilinx.com:user:ethernet_transceiver2:1.0\
 xilinx.com:ip:fifo_generator:13.2\
 xilinx.com:ip:c_addsub:12.0\
-user.org:user:packaging:3.0\
 xilinx.com:user:segment:1.0\
 xilinx.com:ip:xlconcat:2.1\
 xilinx.com:ip:xlconstant:1.1\
@@ -151,6 +157,31 @@ xilinx.com:ip:xlslice:1.0\
 
 }
 
+##################################################################
+# CHECK Modules
+##################################################################
+set bCheckModules 1
+if { $bCheckModules == 1 } {
+   set list_check_mods "\ 
+packaging\
+"
+
+   set list_mods_missing ""
+   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
+
+   foreach mod_vlnv $list_check_mods {
+      if { [can_resolve_reference $mod_vlnv] == 0 } {
+         lappend list_mods_missing $mod_vlnv
+      }
+   }
+
+   if { $list_mods_missing ne "" } {
+      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
+      common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
+      set bCheckIPsPassed 0
+   }
+}
+
 if { $bCheckIPsPassed != 1 } {
   common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
   return 3
@@ -359,9 +390,17 @@ proc create_root_design { parentCell } {
    CONFIG.Out_Width {1} \
  ] $negate_0
 
-  # Create instance: packaging_1, and set properties
-  set packaging_1 [ create_bd_cell -type ip -vlnv user.org:user:packaging:3.0 packaging_1 ]
-
+  # Create instance: packaging_0, and set properties
+  set block_name packaging
+  set block_cell_name packaging_0
+  if { [catch {set packaging_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $packaging_0 eq "" } {
+     catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
   # Create instance: segment_0, and set properties
   set segment_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:segment:1.0 segment_0 ]
 
@@ -413,8 +452,6 @@ proc create_root_design { parentCell } {
   # Create interface connections
   connect_bd_intf_net -intf_net ethernet_transceiver2_0_fifo_read [get_bd_intf_pins ethernet_transceiver2_0/fifo_read] [get_bd_intf_pins fifo_output/FIFO_READ]
   connect_bd_intf_net -intf_net ethernet_transceiver2_0_fifo_write [get_bd_intf_pins ethernet_transceiver2_0/fifo_write] [get_bd_intf_pins fifo_input/FIFO_WRITE]
-  connect_bd_intf_net -intf_net packaging_1_fifo_read [get_bd_intf_pins fifo_input/FIFO_READ] [get_bd_intf_pins packaging_1/fifo_read]
-  connect_bd_intf_net -intf_net packaging_1_fifo_write [get_bd_intf_pins fifo_output/FIFO_WRITE] [get_bd_intf_pins packaging_1/fifo_write]
 
   # Create port connections
   connect_bd_net -net Net [get_bd_ports eth_rxd_0] [get_bd_pins ethernet_transceiver2_0/eth_rxd]
@@ -426,7 +463,7 @@ proc create_root_design { parentCell } {
   connect_bd_net -net Net6 [get_bd_ports eth_rstn_0] [get_bd_pins ethernet_transceiver2_0/eth_rstn]
   connect_bd_net -net c_counter_binary_0_Q [get_bd_pins c_counter_binary_0/Q] [get_bd_pins segment_0/num2]
   connect_bd_net -net c_counter_binary_1_Q [get_bd_pins c_counter_binary_1/Q] [get_bd_pins segment_0/num1]
-  connect_bd_net -net clk_wiz_clk_out1 [get_bd_ports clk_100MHz] [get_bd_pins c_counter_binary_0/CLK] [get_bd_pins c_counter_binary_1/CLK] [get_bd_pins ethernet_transceiver2_0/clk100mhz] [get_bd_pins fifo_input/clk] [get_bd_pins fifo_output/wr_clk] [get_bd_pins negate_0/CLK] [get_bd_pins packaging_1/clk] [get_bd_pins segment_0/clk]
+  connect_bd_net -net clk_wiz_clk_out1 [get_bd_ports clk_100MHz] [get_bd_pins c_counter_binary_0/CLK] [get_bd_pins c_counter_binary_1/CLK] [get_bd_pins ethernet_transceiver2_0/clk100mhz] [get_bd_pins fifo_input/clk] [get_bd_pins fifo_output/wr_clk] [get_bd_pins negate_0/CLK] [get_bd_pins packaging_0/clk] [get_bd_pins segment_0/clk]
   connect_bd_net -net ethernet_transceiver2_0_eth_mdc [get_bd_ports eth_mdc_0] [get_bd_pins ethernet_transceiver2_0/eth_mdc]
   connect_bd_net -net ethernet_transceiver2_0_eth_refclk [get_bd_ports eth_refclk_0] [get_bd_pins ethernet_transceiver2_0/eth_refclk] [get_bd_pins fifo_output/rd_clk]
   connect_bd_net -net ethernet_transceiver2_0_led16_b [get_bd_ports led16_b_0] [get_bd_pins ethernet_transceiver2_0/led16_b]
@@ -435,12 +472,18 @@ proc create_root_design { parentCell } {
   connect_bd_net -net ethernet_transceiver2_0_led17_b [get_bd_ports led17_b_0] [get_bd_pins ethernet_transceiver2_0/led17_b]
   connect_bd_net -net ethernet_transceiver2_0_led17_g [get_bd_ports led17_g_0] [get_bd_pins ethernet_transceiver2_0/led17_g]
   connect_bd_net -net ethernet_transceiver2_0_led17_r [get_bd_ports led17_r_0] [get_bd_pins ethernet_transceiver2_0/led17_r]
+  connect_bd_net -net fifo_input_dout [get_bd_pins fifo_input/dout] [get_bd_pins packaging_0/inputStream]
+  connect_bd_net -net fifo_input_empty [get_bd_pins fifo_input/empty] [get_bd_pins packaging_0/inputEmpty]
   connect_bd_net -net fifo_input_overflow [get_bd_pins c_counter_binary_1/CE] [get_bd_pins fifo_input/overflow]
+  connect_bd_net -net fifo_output_full [get_bd_pins fifo_output/full] [get_bd_pins packaging_0/outputFull]
   connect_bd_net -net fifo_output_overflow [get_bd_pins c_counter_binary_0/CE] [get_bd_pins fifo_output/overflow]
   connect_bd_net -net fifo_output_rd_data_count [get_bd_pins fifo_output/rd_data_count] [get_bd_pins xlconcat_5/In0]
-  connect_bd_net -net packaging_1_errorCode [get_bd_pins packaging_1/errorCode] [get_bd_pins xlconcat_4/In0]
-  connect_bd_net -net packaging_1_stateOut [get_bd_pins packaging_1/stateOut] [get_bd_pins xlconcat_4/In1]
-  connect_bd_net -net rst_clk_wiz_100M_peripheral_aresetn [get_bd_ports reset_rtl_0] [get_bd_pins ethernet_transceiver2_0/btn_reset] [get_bd_pins negate_0/A] [get_bd_pins packaging_1/rst]
+  connect_bd_net -net packaging_0_errorCode [get_bd_pins packaging_0/errorCode] [get_bd_pins xlconcat_4/In0]
+  connect_bd_net -net packaging_0_inpRdEn [get_bd_pins fifo_input/rd_en] [get_bd_pins packaging_0/inpRdEn]
+  connect_bd_net -net packaging_0_outData [get_bd_pins fifo_output/din] [get_bd_pins packaging_0/outData]
+  connect_bd_net -net packaging_0_outWrEn [get_bd_pins fifo_output/wr_en] [get_bd_pins packaging_0/outWrEn]
+  connect_bd_net -net packaging_0_stateOut [get_bd_pins packaging_0/stateOut] [get_bd_pins xlconcat_4/In1]
+  connect_bd_net -net rst_clk_wiz_100M_peripheral_aresetn [get_bd_ports reset_rtl_0] [get_bd_pins ethernet_transceiver2_0/btn_reset] [get_bd_pins negate_0/A] [get_bd_pins packaging_0/rst]
   connect_bd_net -net segment_0_anodes [get_bd_ports anodes_0] [get_bd_pins segment_0/anodes]
   connect_bd_net -net segment_0_cathodes [get_bd_ports cathodes_0] [get_bd_pins segment_0/cathodes]
   connect_bd_net -net sw_0_1 [get_bd_ports sw_0] [get_bd_pins ethernet_transceiver2_0/ip]

sources/complete-bd.tcl

@@ -104,6 +104,7 @@ set_property -name "webtalk.questa_export_sim" -value "1" -objects $obj
 set_property -name "webtalk.riviera_export_sim" -value "1" -objects $obj
 set_property -name "webtalk.vcs_export_sim" -value "1" -objects $obj
 set_property -name "webtalk.xsim_export_sim" -value "1" -objects $obj
+set_property -name "webtalk.xsim_launch_sim" -value "3" -objects $obj
 set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
 
 # Create 'sources_1' fileset (if not found)
@@ -127,14 +128,162 @@ puts "*** FINISHED RECONSTRUCTING BLOCK DESIGNS"
 
 # Set 'sources_1' fileset object
 set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/Block_proc.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/Loop_Border_proc.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/Loop_Border_proc_borderbuf.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/Loop_HConvH_proc6.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/Loop_VConvH_proc.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/Loop_VConvH_proc_linebuf_0.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/globals.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/checksum.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/conv2d.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/conv2d_5x5_224p.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/dummyModule.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/fifo_w32_d2_A.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/fifo_w32_d3_A.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/filter11x11_strm.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/filter11x11_strm_ent.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/kernel_5x5.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/multiplex.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/ram.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/shiftIn.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/start_for_Block_proc_U0.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/start_for_Loop_Border_proc_U0.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/start_for_Loop_VConvH_proc_U0.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/packaging.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/shiftOut.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/neuron.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/mac.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/parallelize.vhd"]\
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/relu.vhd"]\
+]
+# set imported_files [import_files -fileset sources_1 $files]
+
 # Set 'sources_1' fileset file properties for remote files
 # None
 
 # Set 'sources_1' fileset file properties for local files
-# None
+set file "src/Block_proc.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/Loop_Border_proc.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/Loop_Border_proc_borderbuf.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/Loop_HConvH_proc6.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/Loop_VConvH_proc.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/Loop_VConvH_proc_linebuf_0.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/globals.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/checksum.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/conv2d.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/conv2d_5x5_224p.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/dummyModule.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/fifo_w32_d2_A.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/fifo_w32_d3_A.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/filter11x11_strm.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/filter11x11_strm_ent.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/kernel_5x5.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/multiplex.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/ram.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/shiftIn.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/start_for_Block_proc_U0.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/start_for_Loop_Border_proc_U0.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/start_for_Loop_VConvH_proc_U0.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/packaging.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/shiftOut.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/neuron.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/mac.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/parallelize.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
+set file "src/relu.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
 
 # Set 'sources_1' fileset properties
 set obj [get_filesets sources_1]
+set_property -name "top" -value "packaging" -objects $obj
+set_property -name "top_arch" -value "Behavioral" -objects $obj
+set_property -name "top_file" -value "sources/complete-bd/complete-bd.srcs/sources_1/imports/src/packaging.vhd" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
 
 # Create 'constrs_1' fileset (if not found)
 if {[string equal [get_filesets -quiet constrs_1] ""]} {
@@ -144,12 +293,7 @@ if {[string equal [get_filesets -quiet constrs_1] ""]} {
 # Set 'constrs_1' fileset object
 set obj [get_filesets constrs_1]
 
-# Add/Import constrs file and set constrs file properties
-# set file "[file normalize ${origin_dir}/workspace/complete-bd/complete-bd.srcs/constrs_1/imports/new/nexys_4_ddr.xdc]"
-# set file_imported [import_files -fileset constrs_1 [list $file]]
-# set file "new/nexys_4_ddr.xdc"
-# set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
-# set_property -name "file_type" -value "XDC" -objects $file_obj
+# Empty (no sources present)
 
 # Set 'constrs_1' fileset properties
 set obj [get_filesets constrs_1]
@@ -162,10 +306,26 @@ if {[string equal [get_filesets -quiet sim_1] ""]} {
 
 # Set 'sim_1' fileset object
 set obj [get_filesets sim_1]
-# Empty (no sources present)
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/tb.vhd"]\
+]
+# set imported_files [import_files -fileset sim_1 $files]
+
+# Set 'sim_1' fileset file properties for remote files
+# None
+
+# Set 'sim_1' fileset file properties for local files
+set file "src/tb.vhd"
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
 
 # Set 'sim_1' fileset properties
 set obj [get_filesets sim_1]
+set_property -name "top" -value "tb_module" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
 
 # Set 'utils_1' fileset object
 set obj [get_filesets utils_1]
@@ -176,10 +336,84 @@ set obj [get_filesets utils_1]
 
 
 # Adding sources referenced in BDs, if not already added
+if { [get_files Block_proc.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/Block_proc.vhd
+}
+if { [get_files Loop_Border_proc.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/Loop_Border_proc.vhd
+}
+if { [get_files Loop_Border_proc_borderbuf.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/Loop_Border_proc_borderbuf.vhd
+}
+if { [get_files Loop_HConvH_proc6.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/Loop_HConvH_proc6.vhd
+}
+if { [get_files Loop_VConvH_proc.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/Loop_VConvH_proc.vhd
+}
+if { [get_files Loop_VConvH_proc_linebuf_0.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/Loop_VConvH_proc_linebuf_0.vhd
+}
+if { [get_files globals.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/globals.vhd
+}
+if { [get_files checksum.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/checksum.vhd
+}
+if { [get_files conv2d.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/conv2d.vhd
+}
+if { [get_files conv2d_5x5_224p.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/conv2d_5x5_224p.vhd
+}
+if { [get_files dummyModule.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/dummyModule.vhd
+}
+if { [get_files fifo_w32_d2_A.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/fifo_w32_d2_A.vhd
+}
+if { [get_files fifo_w32_d3_A.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/fifo_w32_d3_A.vhd
+}
+if { [get_files filter11x11_strm.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/filter11x11_strm.vhd
+}
+if { [get_files filter11x11_strm_ent.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/filter11x11_strm_ent.vhd
+}
+if { [get_files kernel_5x5.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/kernel_5x5.vhd
+}
+if { [get_files multiplex.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/multiplex.vhd
+}
+if { [get_files ram.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/ram.vhd
+}
+if { [get_files shiftIn.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/shiftIn.vhd
+}
+if { [get_files start_for_Block_proc_U0.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/start_for_Block_proc_U0.vhd
+}
+if { [get_files start_for_Loop_Border_proc_U0.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/start_for_Loop_Border_proc_U0.vhd
+}
+if { [get_files start_for_Loop_VConvH_proc_U0.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/start_for_Loop_VConvH_proc_U0.vhd
+}
+if { [get_files packaging.vhd] == "" } {
+  import_files -quiet -fileset sources_1 /home/windows/repos/vhdl-modules/workspace/complete-bd/complete-bd.srcs/sources_1/imports/src/packaging.vhd
+}
 
 
 # Proc to create BD design_1
 proc cr_bd_design_1 { parentCell } {
+# The design that will be created by this Tcl proc contains the following 
+# module references:
+# packaging
+
+
 
   # CHANGE DESIGN NAME HERE
   set design_name design_1
@@ -199,7 +433,6 @@ proc cr_bd_design_1 { parentCell } {
   xilinx.com:user:ethernet_transceiver2:1.0\
   xilinx.com:ip:fifo_generator:13.2\
   xilinx.com:ip:c_addsub:12.0\
-  user.org:user:packaging:3.0\
   xilinx.com:user:segment:1.0\
   xilinx.com:ip:xlconcat:2.1\
   xilinx.com:ip:xlconstant:1.1\
@@ -223,6 +456,31 @@ proc cr_bd_design_1 { parentCell } {
 
   }
 
+  ##################################################################
+  # CHECK Modules
+  ##################################################################
+  set bCheckModules 1
+  if { $bCheckModules == 1 } {
+     set list_check_mods "\ 
+  packaging\
+  "
+
+   set list_mods_missing ""
+   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
+
+   foreach mod_vlnv $list_check_mods {
+      if { [can_resolve_reference $mod_vlnv] == 0 } {
+         lappend list_mods_missing $mod_vlnv
+      }
+   }
+
+   if { $list_mods_missing ne "" } {
+      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
+      common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
+      set bCheckIPsPassed 0
+   }
+}
+
   if { $bCheckIPsPassed != 1 } {
     common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
     return 3
@@ -420,9 +678,17 @@ proc cr_bd_design_1 { parentCell } {
    CONFIG.Out_Width {1} \
  ] $negate_0
 
-  # Create instance: packaging_1, and set properties
-  set packaging_1 [ create_bd_cell -type ip -vlnv user.org:user:packaging:3.0 packaging_1 ]
-
+  # Create instance: packaging_0, and set properties
+  set block_name packaging
+  set block_cell_name packaging_0
+  if { [catch {set packaging_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $packaging_0 eq "" } {
+     catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
   # Create instance: segment_0, and set properties
   set segment_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:segment:1.0 segment_0 ]
 
@@ -474,8 +740,6 @@ proc cr_bd_design_1 { parentCell } {
   # Create interface connections
   connect_bd_intf_net -intf_net ethernet_transceiver2_0_fifo_read [get_bd_intf_pins ethernet_transceiver2_0/fifo_read] [get_bd_intf_pins fifo_output/FIFO_READ]
   connect_bd_intf_net -intf_net ethernet_transceiver2_0_fifo_write [get_bd_intf_pins ethernet_transceiver2_0/fifo_write] [get_bd_intf_pins fifo_input/FIFO_WRITE]
-  connect_bd_intf_net -intf_net packaging_1_fifo_read [get_bd_intf_pins fifo_input/FIFO_READ] [get_bd_intf_pins packaging_1/fifo_read]
-  connect_bd_intf_net -intf_net packaging_1_fifo_write [get_bd_intf_pins fifo_output/FIFO_WRITE] [get_bd_intf_pins packaging_1/fifo_write]
 
   # Create port connections
   connect_bd_net -net Net [get_bd_ports eth_rxd_0] [get_bd_pins ethernet_transceiver2_0/eth_rxd]
@@ -487,7 +751,7 @@ proc cr_bd_design_1 { parentCell } {
   connect_bd_net -net Net6 [get_bd_ports eth_rstn_0] [get_bd_pins ethernet_transceiver2_0/eth_rstn]
   connect_bd_net -net c_counter_binary_0_Q [get_bd_pins c_counter_binary_0/Q] [get_bd_pins segment_0/num2]
   connect_bd_net -net c_counter_binary_1_Q [get_bd_pins c_counter_binary_1/Q] [get_bd_pins segment_0/num1]
-  connect_bd_net -net clk_wiz_clk_out1 [get_bd_ports clk_100MHz] [get_bd_pins c_counter_binary_0/CLK] [get_bd_pins c_counter_binary_1/CLK] [get_bd_pins ethernet_transceiver2_0/clk100mhz] [get_bd_pins fifo_input/clk] [get_bd_pins fifo_output/wr_clk] [get_bd_pins negate_0/CLK] [get_bd_pins packaging_1/clk] [get_bd_pins segment_0/clk]
+  connect_bd_net -net clk_wiz_clk_out1 [get_bd_ports clk_100MHz] [get_bd_pins c_counter_binary_0/CLK] [get_bd_pins c_counter_binary_1/CLK] [get_bd_pins ethernet_transceiver2_0/clk100mhz] [get_bd_pins fifo_input/clk] [get_bd_pins fifo_output/wr_clk] [get_bd_pins negate_0/CLK] [get_bd_pins packaging_0/clk] [get_bd_pins segment_0/clk]
   connect_bd_net -net ethernet_transceiver2_0_eth_mdc [get_bd_ports eth_mdc_0] [get_bd_pins ethernet_transceiver2_0/eth_mdc]
   connect_bd_net -net ethernet_transceiver2_0_eth_refclk [get_bd_ports eth_refclk_0] [get_bd_pins ethernet_transceiver2_0/eth_refclk] [get_bd_pins fifo_output/rd_clk]
   connect_bd_net -net ethernet_transceiver2_0_led16_b [get_bd_ports led16_b_0] [get_bd_pins ethernet_transceiver2_0/led16_b]
@@ -496,12 +760,18 @@ proc cr_bd_design_1 { parentCell } {
   connect_bd_net -net ethernet_transceiver2_0_led17_b [get_bd_ports led17_b_0] [get_bd_pins ethernet_transceiver2_0/led17_b]
   connect_bd_net -net ethernet_transceiver2_0_led17_g [get_bd_ports led17_g_0] [get_bd_pins ethernet_transceiver2_0/led17_g]
   connect_bd_net -net ethernet_transceiver2_0_led17_r [get_bd_ports led17_r_0] [get_bd_pins ethernet_transceiver2_0/led17_r]
+  connect_bd_net -net fifo_input_dout [get_bd_pins fifo_input/dout] [get_bd_pins packaging_0/inputStream]
+  connect_bd_net -net fifo_input_empty [get_bd_pins fifo_input/empty] [get_bd_pins packaging_0/inputEmpty]
   connect_bd_net -net fifo_input_overflow [get_bd_pins c_counter_binary_1/CE] [get_bd_pins fifo_input/overflow]
+  connect_bd_net -net fifo_output_full [get_bd_pins fifo_output/full] [get_bd_pins packaging_0/outputFull]
   connect_bd_net -net fifo_output_overflow [get_bd_pins c_counter_binary_0/CE] [get_bd_pins fifo_output/overflow]
   connect_bd_net -net fifo_output_rd_data_count [get_bd_pins fifo_output/rd_data_count] [get_bd_pins xlconcat_5/In0]
-  connect_bd_net -net packaging_1_errorCode [get_bd_pins packaging_1/errorCode] [get_bd_pins xlconcat_4/In0]
-  connect_bd_net -net packaging_1_stateOut [get_bd_pins packaging_1/stateOut] [get_bd_pins xlconcat_4/In1]
-  connect_bd_net -net rst_clk_wiz_100M_peripheral_aresetn [get_bd_ports reset_rtl_0] [get_bd_pins ethernet_transceiver2_0/btn_reset] [get_bd_pins negate_0/A] [get_bd_pins packaging_1/rst]
+  connect_bd_net -net packaging_0_errorCode [get_bd_pins packaging_0/errorCode] [get_bd_pins xlconcat_4/In0]
+  connect_bd_net -net packaging_0_inpRdEn [get_bd_pins fifo_input/rd_en] [get_bd_pins packaging_0/inpRdEn]
+  connect_bd_net -net packaging_0_outData [get_bd_pins fifo_output/din] [get_bd_pins packaging_0/outData]
+  connect_bd_net -net packaging_0_outWrEn [get_bd_pins fifo_output/wr_en] [get_bd_pins packaging_0/outWrEn]
+  connect_bd_net -net packaging_0_stateOut [get_bd_pins packaging_0/stateOut] [get_bd_pins xlconcat_4/In1]
+  connect_bd_net -net rst_clk_wiz_100M_peripheral_aresetn [get_bd_ports reset_rtl_0] [get_bd_pins ethernet_transceiver2_0/btn_reset] [get_bd_pins negate_0/A] [get_bd_pins packaging_0/rst]
   connect_bd_net -net segment_0_anodes [get_bd_ports anodes_0] [get_bd_pins segment_0/anodes]
   connect_bd_net -net segment_0_cathodes [get_bd_ports cathodes_0] [get_bd_pins segment_0/cathodes]
   connect_bd_net -net sw_0_1 [get_bd_ports sw_0] [get_bd_pins ethernet_transceiver2_0/ip]

sources/complete-bd/complete-bd.srcs/constrs_1/imports/new/nexys_4_ddr.xdc

@@ -1,78 +0,0 @@
-#clock
-
-set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk_100MHz]
-#create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk_100MHz]
-set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports reset_rtl_0]
-
-
-# ethernet phy
-
-set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS33} [get_ports eth_mdc_0]
-set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports eth_mdio_0]
-set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports eth_rstn_0]
-set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports eth_crsdv_0]
-set_property -dict {PACKAGE_PIN C10 IOSTANDARD LVCMOS33} [get_ports eth_rxerr_0]
-set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports {eth_rxd_0[0]}]
-set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports {eth_rxd_0[1]}]
-set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS33} [get_ports eth_txen_0]
-set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS33} [get_ports {eth_txd_0[0]}]
-set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports {eth_txd_0[1]}]
-set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports eth_refclk_0]
-#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }];
-
-# rgb led
-
-set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { led16_r_0 }]; #IO_L5P_T0_D06_14 Sch=led16_b
-set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { led16_g_0 }]; #IO_L10P_T1_D14_14 Sch=led16_g
-set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { led16_b_0 }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
-set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led17_r_0 }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
-set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { led17_g_0 }]; #IO_0_14 Sch=led17_g
-set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { led17_b_0 }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
-
-## LEDs
-
-set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { led_0[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
-set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { led_0[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
-set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { led_0[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
-set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { led_0[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
-set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { led_0[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
-set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { led_0[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
-set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { led_0[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
-set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { led_0[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
-set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { led_0[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
-set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { led_0[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
-set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { led_0[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
-set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { led_0[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
-set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { led_0[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
-set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { led_0[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
-set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { led_0[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
-set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { led_0[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
-
-##Switches
-
-set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { sw_0[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
-set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { sw_0[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
-set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { sw_0[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
-set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { sw_0[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
-set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { sw_0[4] }];
-
-##7 segment display
-
-set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { cathodes_0[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
-set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { cathodes_0[1] }]; #IO_25_14 Sch=cb
-set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { cathodes_0[2] }]; #IO_25_15 Sch=cc
-set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { cathodes_0[3] }]; #IO_L7P_T2_A26_15 Sch=cd
-set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { cathodes_0[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce
-set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { cathodes_0[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
-set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { cathodes_0[6] }]; #IO_L4P_T0_D04_14 Sch=cg
-set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { cathodes_0[7] }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
-
-set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { anodes_0[7] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
-set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { anodes_0[6] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
-set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { anodes_0[5] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
-set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { anodes_0[4] }]; #IO_L19P_T3_A22_15 Sch=an[3]
-set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { anodes_0[3] }]; #IO_L8N_T1_D12_14 Sch=an[4]
-set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { anodes_0[2] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
-set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { anodes_0[1] }]; #IO_L23P_T3_35 Sch=an[6]
-set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { anodes_0[0] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
-

ip_repo_sources/packaging/src/conv2d_5x5_224p.vhd → sources/complete-bd/complete-bd.srcs/sources_1/imports/src/conv2d.vhd

@@ -4,11 +4,11 @@ use IEEE.STD_LOGIC_1164.ALL;
 use work.myPackage.ALL;
 
 
-entity conv2d_5x5_224p is
+entity conv2d is
     generic(
         busWidth : integer := 32;
-        kernelSize : integer := 5;
-        imageWidth : integer := 224 + 4);
+        kernelSize : integer;
+        imageWidth : integer);
     Port ( clk : in STD_LOGIC;
            rst_n : in std_logic;
            start : in STD_LOGIC;
@@ -23,10 +23,11 @@ entity conv2d_5x5_224p is
            dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
            dstValid : out std_logic;
            dstReady : in std_logic);
-end conv2d_5x5_224p;
+end conv2d;
 
-architecture Behavioral of conv2d_5x5_224p is
+architecture Behavioral of conv2d is
     constant regDepth : integer := ((kernelSize-1) * imageWidth + kernelSize);
+    constant wordCount : integer := kernelSize*kernelSize + imageWidth*imageWidth;
     component shiftIn is
         generic(
             busWidth : integer := busWidth;
@@ -52,7 +53,7 @@ architecture Behavioral of conv2d_5x5_224p is
     );
     end component;
     
-    function buffer_to_kernel(inp : in register_file(0 to regDepth-1)) return register_file is
+    function buffer_to_activations(inp : in register_file(0 to regDepth-1)) return register_file is
         variable ret : register_file(0 to kernelSize*kernelSize-1);
     begin
         for x in integer range 0 to kernelSize - 1 loop
@@ -66,20 +67,21 @@ architecture Behavioral of conv2d_5x5_224p is
     signal kernelOutput : std_logic_vector(busWidth-1 downto 0);
     signal inputBuffer : register_file(0 to regDepth-1);
     signal kernelValues : register_file(0 to kernelSize*kernelSize-1);
-    signal dataIndex : integer range 0 to imageWidth*imageWidth;
+    signal dataIndex : integer range 0 to wordCount;
     
     signal working : std_logic := '0';
     signal dstStalled_s : std_logic := '0';
     signal dstValid_s : std_logic := '0';
+    signal kernelComplete : std_logic := '0';
     
 begin
     kernel_5x5 : kernel_NxN port map (
         kernelValues => kernelValues,
-        inputValues => buffer_to_kernel(inputBuffer),
+        inputValues => buffer_to_activations(inputBuffer),
         outputValue => kernelOutput
     );
     dstData <= kernelOutput;
-    shiftIn2: shiftIn port map (
+    shiftInPixels: shiftIn port map (
         clk         => clk,
         ce          => dstValid_s,
         sync_reset  => working,
@@ -88,27 +90,18 @@ begin
         dataIndex    => dataIndex
     );
     
-    setKernel : process(rst_n) begin
-        kernelValues <= (others => (others => '0'));
-        
-        -- 0  0  0  0  0
-        -- 0 -1 -1 -1  0
-        -- 0 -1  8 -1  0
-        -- 0 -1 -1 -1  0
-        -- 0  0  0  0  0
-        
-        kernelValues(6) <= x"FFFFFFFF";
-        kernelValues(7) <= x"FFFFFFFF";
-        kernelValues(8) <= x"FFFFFFFF";
-        
-        kernelValues(11) <= x"FFFFFFFF";
-        kernelValues(12) <= x"00000008";
-        kernelValues(13) <= x"FFFFFFFF";
-        
-        kernelValues(16) <= x"FFFFFFFF";
-        kernelValues(17) <= x"FFFFFFFF";
-        kernelValues(18) <= x"FFFFFFFF";
-        
+    setKernel : process(rst_n, clk) begin
+        if rst_n = '0' then
+            kernelComplete <= '0';
+        elsif rising_edge(clk) then
+            kernelValues <= kernelValues;
+            if dataIndex < kernelSize * kernelSize then
+                kernelValues(dataIndex) <= srcData;
+                kernelComplete <= '0';
+            else
+                kernelComplete <= '1';
+            end if;        
+        end if;
     end process;
     
     dataPathStall : process(rst_n, clk)
@@ -125,11 +118,11 @@ begin
         end if;
     end process;
     
-    dstValid_s <= working and dstReady and (srcValid or dstStalled_s);
+    dstValid_s <= working and dstReady and (srcValid or dstStalled_s) and kernelComplete;
     dstValid <= dstValid_s;
     
     srcRdy : process(dataIndex, working, dstReady, srcValid, start) begin
-        if (dataIndex = imageWidth*imageWidth - 1 and srcValid = '1') or dataIndex = imageWidth*imageWidth then
+        if (dataIndex = wordCount - 1 and srcValid = '1') or dataIndex = wordCount then
             srcReady <= '0';
         else
             srcReady <= working and dstReady and not dstStalled_s and start;
@@ -145,10 +138,10 @@ begin
             done <= '0';
             working <= '0';
            
-            if dataIndex = imageWidth*imageWidth - 1 and dstValid_s = '1' then
+            if dataIndex = wordCount - 1 and dstValid_s = '1' then
                 done <= '1';
                 working <= '1';
-            elsif dataIndex = imageWidth*imageWidth then
+            elsif dataIndex = wordCount then
                 working <= '0';
             elsif start = '1' then
                 working <= '1';

sources/complete-bd/complete-bd.srcs/sources_1/imports/src/conv2d_5x5_224p.vhd

@@ -0,0 +1,68 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.myPackage.ALL;
+
+
+entity conv2d_5x5_224p is
+    generic(
+        busWidth : integer := 32);
+    Port ( clk : in STD_LOGIC;
+           rst_n : in std_logic;
+           start : in STD_LOGIC;
+           ready: out std_logic;
+           idle : out std_logic := '0';
+           done : out std_logic := '0';
+           
+           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           srcValid : in std_logic;
+           srcReady : out std_logic;
+           
+           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           dstValid : out std_logic;
+           dstReady : in std_logic);
+end conv2d_5x5_224p;
+
+architecture Behavioral of conv2d_5x5_224p is
+    component conv2d is
+    generic(
+        busWidth : integer := 32;
+        kernelSize : integer;
+        imageWidth : integer);
+    Port ( clk : in STD_LOGIC;
+           rst_n : in std_logic;
+           start : in STD_LOGIC;
+           ready: out std_logic;
+           idle : out std_logic := '0';
+           done : out std_logic := '0';
+           
+           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           srcValid : in std_logic;
+           srcReady : out std_logic;
+           
+           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           dstValid : out std_logic;
+           dstReady : in std_logic);
+    end component;
+begin
+    conv2d_0: conv2d generic map (
+        kernelSize => 5,
+        imageWidth => 224 + 4
+    ) port map (
+        clk => clk,
+        rst_n => rst_n,
+
+        srcData => srcData,
+        srcValid=> srcValid,
+        srcReady=> srcReady,
+        
+        dstData => dstData,
+        dstValid => dstValid,
+        dstReady => dstReady,
+        
+        start   => start,
+        ready   => ready,
+        idle    => idle,
+        done    => done
+    );
+end Behavioral;

ip_repo_sources/packaging/src/multiplex.vhd → sources/complete-bd/complete-bd.srcs/sources_1/imports/src/multiplex.vhd

@@ -92,9 +92,7 @@ end component;
 
 component conv2d_5x5_224p is
     generic(
-        busWidth : integer := 32;
-        kernelSize : integer := 5;
-        imageWidth : integer := 224 + 4);
+        busWidth : integer := 32);
     Port ( clk : in STD_LOGIC;
            rst_n : in std_logic;
            start : in STD_LOGIC;

ip_repo_sources/packaging/src/tb.vhd → sources/complete-bd/complete-bd.srcs/sources_1/imports/src/tb.vhd

@@ -5,11 +5,11 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
 use STD.textio.all;
 use ieee.std_logic_textio.all;
 
-entity tb is
+entity tb_module is
         
-end tb;
+end tb_module;
 
-architecture Behavioral of tb is
+architecture Behavioral of tb_module is
 
 constant busWidth : integer:=32;