added sources

ip_repo_sources/7segment/component.xml

@@ -0,0 +1,264 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>segment</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>segment</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>3ba0b575</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>segment</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>7ad6a897</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>f64a5dae</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>num1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">15</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="16">0x00E2</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>num2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">15</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="16">0x00E2</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>anodes</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">7</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>cathodes</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long">7</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>src/segment.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/segment.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_7ad6a897</spirit:userFileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>src/segment.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/segment_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>segment_v1_0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">segment_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>segment_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>package_project</xilinx:definitionSource>
+      <xilinx:coreRevision>4</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2019-06-27T22:30:48Z</xilinx:coreCreationDateTime>
+      <xilinx:tags>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@749e80d8_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@4d5a2e26_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@615029f0_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@1c465cf6_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@6da5ca59_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@39d7574a_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@63bf7914_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@7fc16fb0_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@4d9b7294_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@a1723ac_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@4d20d57f_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@629b5dff_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@79beb46b_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@489b6fd8_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@3074f5bc_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@71800c02_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@49a569bc_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@74ae251d_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@3f41d065_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@28681b2d_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@1d3564c5_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@8bfd351_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@6c402823_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@d7dc8ac_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@4ba251e4_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@5d55046_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
+      </xilinx:tags>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="a88d4390"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d53f92ad"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="6842c7da"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="9f959d71"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>

ip_repo_sources/7segment/src/segment.vhd

@@ -0,0 +1,68 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_arith.ALL;
+use IEEE.std_logic_textio.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity segment is Port (
+    num1 : in std_logic_vector(15 downto 0) := x"00e2";
+    num2 : in std_logic_vector(15 downto 0) := x"00e2";
+    clk: in std_logic;
+    anodes: out std_logic_vector(0 to 7);
+    cathodes: out std_logic_vector(0 to 7)
+);
+end segment;
+
+architecture Behavioral of segment is
+    
+    type inputs is array(7 downto 0) of integer range 0 to 15;
+    signal counter: std_logic_vector(18 downto 0);
+begin
+
+    process(clk)
+        variable tmp1 : integer range 0 to 2**15-1;
+        variable tmp2 : integer range 0 to 2**15-1;
+        variable data : integer range 0 to 15;
+        variable index: integer range 0 to 7;
+    begin
+        if(rising_edge(clk)) then
+            counter <= counter + 1;
+        end if;
+        index := conv_integer(unsigned(counter(18 downto 16)));
+        
+        tmp1 := conv_integer(unsigned(num1));
+        tmp2 := conv_integer(unsigned(num2));
+        anodes <= (others => '1');
+        anodes(index) <= '0';
+        
+        data := 10;
+        
+        case index is
+            when 0 => if(tmp1 / 1000 > 0) then data := tmp1 / 1000 mod 10; end if;
+            when 1 => if(tmp1 / 100  > 0) then data := tmp1 / 100  mod 10; end if;
+            when 2 => if(tmp1 / 10   > 0) then data := tmp1 / 10   mod 10; end if;
+            when 3 => data := tmp1 mod 10;
+            when 4 => if(tmp2 / 1000 > 0) then data := tmp2 / 1000 mod 10; end if;
+            when 5 => if(tmp2 / 100  > 0) then data := tmp2 / 100  mod 10; end if;
+            when 6 => if(tmp2 / 10   > 0) then data := tmp2 / 10   mod 10; end if;
+            when 7 => data := tmp2 mod 10;
+        end case;
+        case data is
+            when 0 => cathodes <= "00000011"; -- "0"     
+            when 1 => cathodes <= "10011111"; -- "1" 
+            when 2 => cathodes <= "00100101"; -- "2" 
+            when 3 => cathodes <= "00001101"; -- "3" 
+            when 4 => cathodes <= "10011001"; -- "4" 
+            when 5 => cathodes <= "01001001"; -- "5" 
+            when 6 => cathodes <= "01000001"; -- "6" 
+            when 7 => cathodes <= "00011111"; -- "7" 
+            when 8 => cathodes <= "00000001"; -- "8"     
+            when 9 => cathodes <= "00001001"; -- "9" 
+            when others => cathodes <= "11111111"; -- " "
+        end case;
+    end process;
+end Behavioral;

ip_repo_sources/7segment/src/segment.xdc

@@ -0,0 +1,40 @@
+#set_property PACKAGE_PIN U13 [get_ports {anodes[0]}]
+#set_property PACKAGE_PIN K2  [get_ports {anodes[1]}]
+#set_property PACKAGE_PIN T14 [get_ports {anodes[2]}]
+#set_property PACKAGE_PIN P14 [get_ports {anodes[3]}]
+#set_property PACKAGE_PIN J14 [get_ports {anodes[4]}]
+#set_property PACKAGE_PIN T9  [get_ports {anodes[5]}]
+#set_property PACKAGE_PIN J18 [get_ports {anodes[6]}]
+#set_property PACKAGE_PIN J17 [get_ports {anodes[7]}]
+
+#set_property IOSTANDARD LVCMOS33 [get_ports {anodes[0]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {anodes[1]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {anodes[2]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {anodes[3]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {anodes[4]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {anodes[5]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {anodes[6]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {anodes[7]}]
+
+
+#set_property PACKAGE_PIN T10 [get_ports {cathodes[0]}]
+#set_property PACKAGE_PIN R10 [get_ports {cathodes[1]}]
+#set_property PACKAGE_PIN K16 [get_ports {cathodes[2]}]
+#set_property PACKAGE_PIN K13 [get_ports {cathodes[3]}]
+#set_property PACKAGE_PIN P15 [get_ports {cathodes[4]}]
+#set_property PACKAGE_PIN T11 [get_ports {cathodes[5]}]
+#set_property PACKAGE_PIN L18 [get_ports {cathodes[6]}]
+#set_property PACKAGE_PIN H15 [get_ports {cathodes[7]}]
+
+#set_property IOSTANDARD LVCMOS33 [get_ports {cathodes[0]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {cathodes[1]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {cathodes[2]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {cathodes[3]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {cathodes[4]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {cathodes[5]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {cathodes[6]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {cathodes[7]}]
+
+
+#set_property PACKAGE_PIN E3 [get_ports {clk}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {clk}]

ip_repo_sources/7segment/xgui/segment_v1_0.tcl

@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+

ip_repo_sources/UDP-server/component.xml

@@ -0,0 +1,911 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>user.org</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>ethernet_transceiver</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>btn_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>btn_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>eth_rstn</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>eth_rstn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ETH_RSTN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
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+  </spirit:vendorExtensions>
+</spirit:component>

ip_repo_sources/UDP-server/src/clock_mod.vhd

@@ -0,0 +1,68 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov 
+-- 
+-- Create Date:    14:56:38 02/16/2017 
+-- Design Name: 
+-- Module Name:    clock_mod - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- This module provides Transceiver design with 2 clocks:
+-- - 50mhz clock, which is reference clock for the ethernet chip and
+-- - 50mhz_shifted clock, which is used for write Tx operations.
+-- 50mhz_shift clock is shifted by -pi/2 with respect to 50mhz clock
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_mod is
+--    Generic ( M_clk : integer);
+	 Port ( clk100mhz : in  STD_LOGIC;
+           clk_out : out  STD_LOGIC;
+			  clk_out_shift: out STD_LOGIC);
+end clock_mod;
+
+architecture Behavioral of clock_mod is
+
+signal temp_clk : std_logic := '0';
+signal temp_clk_shift : std_logic := '1';
+--signal count : integer range 0 to M_clk-1 :=0;
+
+begin
+	
+	clock: process (clk100mhz)
+	begin
+		if (rising_edge(clk100mhz)) then
+		temp_clk <= not(temp_clk);
+		end if;
+	end process clock;
+	
+	shift_clock: process (clk100mhz)
+	begin
+		if (falling_edge(clk100mhz)) then
+			temp_clk_shift <= not(temp_clk_shift);
+		end if;
+	end process shift_clock;
+	
+	clk_out <= temp_clk;
+	clk_out_shift <= temp_clk_shift;
+
+end Behavioral;
+

ip_repo_sources/UDP-server/src/clock_mod2.vhd

@@ -0,0 +1,88 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov
+-- 
+-- Create Date:    14:56:38 02/16/2017 
+-- Design Name: 
+-- Module Name:    clock_mod - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- This module generates 2.5mhz clocks for the SMI interface.
+-- 2.5mhz clock is the MDC clock and 2.5mhz_shift clock is used for read/write
+-- MDIO operations and it's shifted by -pi/2 with respect to 2.5mhz clock
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_mod2 is
+    Generic ( M_clk1 : integer;
+				  M_clk2 : integer);
+	 Port ( clk100mhz : in  STD_LOGIC;
+           clk_out1 : out  STD_LOGIC;
+			  clk_out2 : out STD_LOGIC);
+end clock_mod2;
+
+architecture Behavioral of clock_mod2 is
+
+signal temp_clk1 : std_logic := '0';
+signal temp_clk2 : std_logic := '0';
+signal count1 : integer range 0 to M_clk1-1 :=0;
+signal count2 : integer range 0 to M_clk1+M_clk1-1 :=0;
+
+begin
+	
+	clock1: process (clk100mhz)
+	begin
+		if (rising_edge(clk100mhz)) then
+			if (count1 < M_clk1-1) then
+				count1 <= count1+1;
+			elsif (count1 = M_clk1-1) then
+				count1 <= 0;
+				temp_clk1 <= not (temp_clk1);
+			end if;
+		end if;
+	end process clock1;
+	
+	clock2: process (clk100mhz)
+	begin
+		if (rising_edge(clk100mhz)) then
+			if (count2 < M_clk1-1 and count2 <= M_clk2-1) then
+				count2 <= count2+1;
+			elsif (count2 < M_clk1-1 and count2 = M_clk2) then
+				count2 <= count2+1;
+				temp_clk2 <= not (temp_clk2);
+			elsif (count2 <= (M_clk1+M_clk2-1)) then
+				count2 <= count2+1;
+			elsif (count2 = (M_clk1+M_clk2)) then
+				count2 <= count2+1;
+				temp_clk2 <= not (temp_clk2);
+			elsif (count2 < (M_clk1+M_clk1-1)) then
+				count2 <= count2+1;
+			elsif (count2 = (M_clk1+M_clk1-1))then
+				count2 <= 0;
+			end if;
+		end if;
+	end process clock2;
+	
+	clk_out1 <= temp_clk1;
+	clk_out2 <= temp_clk2;
+
+end Behavioral;
+

ip_repo_sources/UDP-server/src/crc32_parallel.vhd

@@ -0,0 +1,184 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov
+-- 
+-- Create Date:    15:13:21 03/26/2017 
+-- Design Name: 
+-- Module Name:    crc32_parallel - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- Cyclic Redundancy Check (CRC) module calculates the packet's crc and supplies 
+-- it back to the higher-level module. It performs calculations in parallel (2-bit
+-- wide) and uses 100mhz clock, whereas the rest of the server makes use of 50mhz clock.
+-- This allows to do crc calculations in parallel with reception and transmission of data
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity crc32_parallel is
+    Port ( clk100mhz : in  STD_LOGIC;
+           data_valid : in  STD_LOGIC; -- crc_start
+           rstn : in  STD_LOGIC;		   -- crc_stop
+           data_in : in  STD_LOGIC_VECTOR (1 downto 0); -- connected to rxd bus
+           crc : inout  STD_LOGIC_VECTOR (31 downto 0)); -- output for crc results
+end crc32_parallel;
+
+architecture Behavioral of crc32_parallel is
+type state_type is (idle, calc);
+signal state : state_type := idle;
+signal crc32_temp : std_logic_vector (31 downto 0);
+signal edge_count : std_logic;
+
+begin
+	-- because crc block works on 100mhz clock and processes the whole data nibble
+	-- during the single 100mhz clock period it uses edge_count to keep track of whether
+	-- the data on the bus has been processed already or not
+	-- crc made this way to make sure that crc block can calculate the crc value for the
+	-- packet being transmitted as this packed is actually being transmitted
+	-- and the results of crc calculations are available before transmitter starts
+	-- sending the crc results out
+	-- so, in fact, crc calculations are done in parallel with packet transmission
+	crc_32_2bit: process (clk100mhz,rstn)
+	begin
+		-- during reset state set all registers and flags to initial state
+		if (rstn = '1') then
+			crc32_temp <= (others => '1'); -- initial state of crc register
+			edge_count <= '0'; 				 -- keeps track of incoming data
+			state <= idle;
+		elsif (rising_edge(clk100mhz)) then
+			case state is
+			
+			-- in idle state crc block waits for the data_valid flag to be asserted 
+			when idle =>
+			crc32_temp <= (others => '1');
+			edge_count <= '0';
+			if (data_valid = '0') then
+				state <= idle;
+			-- once data_valid is asserted, calculate crc for the current data nibble
+			-- and invert edge_count
+			-- crc processes data nibbles on edge_count='0' only
+			elsif(data_valid = '1') then
+				crc32_temp(0) <= crc32_temp(30) xor data_in(1);
+				crc32_temp(1) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0));
+				crc32_temp(2) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(0);
+				crc32_temp(3) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(1);
+				crc32_temp(4) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(2);
+				crc32_temp(5) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(3);
+				crc32_temp(6) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(4);
+				crc32_temp(7) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(5);
+				crc32_temp(8) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(6);
+				crc32_temp(9) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(7);
+				crc32_temp(10) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(8);
+				crc32_temp(11) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(9);
+				crc32_temp(12) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(10);
+				crc32_temp(13) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(11);
+				crc32_temp(14) <= crc32_temp(12);
+				crc32_temp(15) <= crc32_temp(13);
+				crc32_temp(16) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(14);
+				crc32_temp(17) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(15);
+				crc32_temp(18) <= crc32_temp(16);
+				crc32_temp(19) <= crc32_temp(17);
+				crc32_temp(20) <= crc32_temp(18);
+				crc32_temp(21) <= crc32_temp(19);
+				crc32_temp(22) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(20);
+				crc32_temp(23) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(21);
+				crc32_temp(24) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(22);
+				crc32_temp(25) <= crc32_temp(23);
+				crc32_temp(26) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(24);
+				crc32_temp(27) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(25);
+				crc32_temp(28) <= crc32_temp(26);
+				crc32_temp(29) <= crc32_temp(27);
+				crc32_temp(30) <= crc32_temp(28);
+				crc32_temp(31) <= crc32_temp(29);
+				edge_count <= not(edge_count);
+				state <= calc;
+			end if;
+		
+			when calc => 
+			-- if valid data present on the bus
+			if (data_valid = '1') then
+				-- do nothing if edge_count = '1', just keep current crc result = to past crc result
+				if (edge_count = '1') then
+					edge_count <= not(edge_count);
+					crc32_temp <= crc32_temp;
+					state <= calc;
+				-- if edge_count = '0' calculate crc result for the new data nibble
+				elsif (edge_count = '0') then
+					edge_count <= not(edge_count);
+					---
+					crc32_temp(0) <= crc32_temp(30) xor data_in(1);
+					crc32_temp(1) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0));
+					crc32_temp(2) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(0);
+					crc32_temp(3) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(1);
+					crc32_temp(4) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(2);
+					crc32_temp(5) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(3);
+					crc32_temp(6) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(4);
+					crc32_temp(7) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(5);
+					crc32_temp(8) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(6);
+					crc32_temp(9) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(7);
+					crc32_temp(10) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(8);
+					crc32_temp(11) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(9);
+					crc32_temp(12) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(10);
+					crc32_temp(13) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(11);
+					crc32_temp(14) <= crc32_temp(12);
+					crc32_temp(15) <= crc32_temp(13);
+					crc32_temp(16) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(14);
+					crc32_temp(17) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(15);
+					crc32_temp(18) <= crc32_temp(16);
+					crc32_temp(19) <= crc32_temp(17);
+					crc32_temp(20) <= crc32_temp(18);
+					crc32_temp(21) <= crc32_temp(19);
+					crc32_temp(22) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(20);
+					crc32_temp(23) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(21);
+					crc32_temp(24) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(22);
+					crc32_temp(25) <= crc32_temp(23);
+					crc32_temp(26) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(24);
+					crc32_temp(27) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(25);
+					crc32_temp(28) <= crc32_temp(26);
+					crc32_temp(29) <= crc32_temp(27);
+					crc32_temp(30) <= crc32_temp(28);
+					crc32_temp(31) <= crc32_temp(29);
+					state <= calc;
+				end if;
+			-- if data valid is deasserted, that means that the last valid data nibble, protected by crc,
+			-- has been already loaded to the Tx bus and the current crc result is the valid crc value for the
+			-- packet being transmitted
+			elsif (data_valid <= '0') then
+				edge_count <= '0';
+				state <= idle;
+			end if;
+		
+		end case;
+		end if;
+	end process crc_32_2bit;
+	
+	-- this process outputs calculated crc value to the upper level module on every
+	-- edge_count = '1' (i.e. on every 2nd 100mhz clock period)
+	crc_out: process (clk100mhz,crc,crc32_temp,edge_count)
+	begin
+		if (rising_edge(clk100mhz) and edge_count = '1') then
+			crc <= not(crc32_temp);
+		else
+			crc <= crc;
+		end if;
+	end process crc_out;
+
+end Behavioral;
+

ip_repo_sources/UDP-server/src/debounce_switch.vhd

@@ -0,0 +1,109 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov
+-- 
+-- Create Date:    14:58:05 02/19/2017 
+-- Design Name: 
+-- Module Name:    debounce_switch - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- This module is responsible for debouncing Hardware Reset button
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity debounce_switch is
+	 Generic (N : integer);
+    Port ( clk100mhz : in  STD_LOGIC;
+           btn : in  STD_LOGIC;
+           db_sw : out  STD_LOGIC);
+end debounce_switch;
+
+architecture Behavioral of debounce_switch is
+
+	type state_type is (zero, one, wait0, wait1, init);
+	signal state : state_type := init;
+	signal timer : unsigned (N-1 downto 0) := (others => '0');
+	signal sw : std_logic;
+
+begin
+	
+	debouncer: process (clk100mhz,btn)
+	begin
+		if (rising_edge(clk100mhz)) then
+			case state is
+			
+				when init =>
+					timer <= (others => '1');
+					db_sw <= btn;
+					sw <= btn;
+					if (btn = '0') then
+						state <= zero;
+					elsif (btn = '1') then
+						state <= one;
+					end if;
+				
+				when zero =>
+					sw <= btn;
+					db_sw <= '0';
+					if (sw /= btn) then
+						state <= wait1;
+					elsif (sw = btn) then
+						state <= zero;
+					end if;
+				
+				when wait1 =>
+					sw <= btn;
+					if (timer > 0) then
+						timer <= timer-1;
+						db_sw <= '0';
+						state <= wait1;
+					elsif (timer = 0) then
+						db_sw <= btn;
+						state <= init;
+					end if;
+				
+				when one =>
+					sw <= btn;
+					db_sw <= '1';
+					if (sw /= btn) then
+						state <= wait0;
+					elsif (sw = btn) then
+						state <= one;
+					end if;
+				
+				when wait0 =>
+					sw <= btn;
+					if (timer > 0) then
+						timer <= timer-1;
+						db_sw <= '1';
+						state <= wait0;
+					elsif (timer = 0) then
+						db_sw <= btn;
+						state <= init;
+					end if;
+						
+					
+			end case;
+		end if;
+	end process debouncer;
+
+end Behavioral;
+

ip_repo_sources/UDP-server/src/eth_receiver.vhd

@@ -0,0 +1,1160 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov
+-- 
+-- Create Date:    11:16:51 02/24/2017 
+-- Design Name: 
+-- Module Name:    eth_rexeiver - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- Ethernet receiver module handles reception of data packets from the data server.
+-- Only 2 sorts of packets are accepted: ARP requests and UDP packets.
+-- This module doesn't use any elasticity buffer to store incoming packets. The data is 
+-- being parsed in parallel with read operation. ARP and UDP packets designated to
+-- this echo-server are accepted and the rest is rejected.
+-- Receiver module includs 7 processes and 1 sub-module:
+-- - process to read data in;
+-- - process to parse Ethernet headers of the incoming packets;
+-- - process to parse headers of the higher-level protocols (ARP, IP4, UDP);
+-- - process to do IP header checksum check;
+-- - process to do UDP header checksum check;
+-- - process to handle data write operation to RAM block;
+-- - process to handle data pass to Transmitter block for echo-reply;
+-- - lower-level module, performing crc check of the incoming packets.
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity eth_receiver is
+	 Generic (ADDR_WIDTH : integer;
+				 DATA_WIDTH : integer);
+    Port ( clk100mhz : in STD_LOGIC; -- clock for crc checker
+			  clk50mhz : in  STD_LOGIC; -- reference clock, read rx bus on falling edge
+           rxd : in  STD_LOGIC_VECTOR (1 downto 0);
+           crsdv : in  STD_LOGIC;
+           rstn : in  STD_LOGIC;
+			  rxerr : in STD_LOGIC;
+			  -- RAM signals
+			  wrt_data_ram : inout STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
+			  wrt_addr_ram : inout STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
+			  wrt_enable_ram : out STD_LOGIC;
+			  -- Addresses
+           fpga_mac : in STD_LOGIC_VECTOR (47 downto 0);
+			  fpga_ip : in STD_LOGIC_VECTOR (31 downto 0);
+			  fpga_port : in STD_LOGIC_VECTOR (15 downto 0);
+			  pc_mac : out STD_LOGIC_VECTOR (47 downto 0);
+			  pc_ip : out  STD_LOGIC_VECTOR (31 downto 0);
+			  pc_port : out STD_LOGIC_VECTOR (15 downto 0);
+			  -- Data to Tx
+			  datacm : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0);
+			  udpl : out STD_LOGIC_VECTOR (15 downto 0);
+			  udpc : out STD_LOGIC_VECTOR (15 downto 0);
+			  send_arp_reply : out STD_LOGIC;
+			  send_ethernet_protocol: out STD_LOGIC;
+			  data_out_valid : out STD_LOGIC);
+end eth_receiver;
+
+architecture Behavioral of eth_receiver is
+-- SIGNALS
+-- ******* process receive (responsible for handling Rx) ********--
+type state_type is (idle,wait_rx,read_eth_header,read_protocol_header,read_extra_ip_header,read_data,read_zero_padding,read_crc,check_crc);
+signal state : state_type := idle;
+signal bit_count : integer range 0 to 3 := 0;    							     -- counts number of nibbles read
+signal byte_count : integer range 0 to 1499 := 0;							     -- counts number of bytes read
+signal dest_mac : std_logic_vector (47 downto 0) := (others => '0');      -- register to store destination MAC address (from Ethernet header)
+signal source_mac : std_logic_vector (47 downto 0) := (others => '0');    -- register to store source MAC address (from Ethernet header)
+signal eth_prot_type : std_logic_vector (15 downto 0) := (others => '0'); -- register to store Ethernet Protocol Type
+signal bytes00, bytes01, bytes02, bytes03, bytes04, bytes05, bytes06, bytes07,
+bytes08, bytes09, bytes10, bytes11, bytes12, bytes13 : std_logic_vector (15 downto 0) := (others => '0'); -- registers to store IP/UDP headers
+signal byte_read_done : std_logic_vector (13 downto 0) := (others => '0'); -- flags for IP/UDP registers 
+signal read_eth_header_done : std_logic := '0';                            -- flag to indicate end of the Ethernet Header
+signal start_crc : std_logic := '0';       -- enable crc checking
+signal stop_crc : std_logic := '0';  		 -- disable crc checking
+signal unknown_request : std_logic := '0'; -- other unknown requests ORed
+-- ******* process eth_packet_type (responsible for parsing Ethernet header) ********--
+signal arp_request_expected : std_logic := '0';  -- flag set if Ethernet header matches ARP protocol
+signal eth_protocol_expected : std_logic := '0'; -- flag set if Ethernet header matches UDP protocol
+signal unknown_request1 : std_logic := '0';      -- Ethernet header matches neither ARP nor UDP protocols
+-- ******* process headers_parse (responsible for parsing ARP/UDP header) ********--
+signal ip_header_length : std_logic_vector (3 downto 0) := (others => '0');-- length in bytes of IP header (for UDP packet)
+signal ip_options_count_max : integer range 0 to 40 := 0;                  -- counter for UDP header's extra options (from 21 to 40 bytes)
+signal ip_extra_options : std_logic := '0'; 											-- set if UDP header has extra options
+signal ip_total_length : std_logic_vector (15 downto 0) := (others => '0');-- total length of datagram in bytes (IP header+payload (payload=UDP header+data)))
+signal data_counter_max : integer range 0 to 1471 := 0;							-- defines length of data field in bytes (without zero padding)
+signal zero_counter : integer range 0 to 18 := 0; 									-- defines length in bytes of zero padding
+signal identification : std_logic_vector (15 downto 0) := (others => '0'); -- ID number of the incoming packet
+signal flags_offset : std_logic_vector (15 downto 0) := (others => '0');   -- flags and fragmentation offset
+signal ip_header_checksum : std_logic_vector (15 downto 0) := (others => '0'); -- IP header's checksum
+signal ip_header_options : std_logic_vector (319 downto 0) := (others => '0'); -- vector to store IP header's optional fields
+signal byte_count_extra : integer range 0 to 39 := 0; 							-- byte counter for IP header's optional fields
+signal source_ip : std_logic_vector (31 downto 0) := (others => '0'); 		-- IP address of the sender
+signal source_port : std_logic_vector (15 downto 0) := (others => '0'); 	-- port number of the sender
+signal udp_length :std_logic_vector (15 downto 0) := (others => '0'); 		-- total length of UDP datagram (UDP header+data)
+signal udp_checksum :std_logic_vector (15 downto 0) := (others => '0'); 	-- UDP header's checksum
+signal temp_data : std_logic_vector (DATA_WIDTH-1 downto 0) := x"00"; 		-- register to temporarily save received data byte
+signal valid_data_byte_read : std_logic := '0'; -- flag indicateing that another data byte was read
+signal read_frame_done : std_logic := '0'; 		-- flag set when valid frame was read, cleared in idle state
+signal unknown_request2 : std_logic := '0'; 		-- set in case of any mismatch between incoming data and expected headers' structures
+-- ******* process ip_header_checksum_check (responsible for checking IP header's checksum) ********--
+signal ip_hcs_calc_temp1 : unsigned (23 downto 0) := (others => '0');   -- sum of all header's fields
+signal ip_hcs_calc_temp2 : unsigned (15 downto 0) := (others => '0');   -- sum of the carry-out with main checksum body
+signal ip_hcs_calc_extra : unsigned (23 downto 0) := (others => '0');   -- sum of IP header's extra options field
+signal edge_count_header : std_logic := '0'; 							      -- used to set correct format of the extra header field in checksum calculations 
+signal ip_hcs_calc : std_logic_vector (15 downto 0) := (others => '1'); -- calculated IP header's checksum
+signal ip_hcs_done : std_logic := '0';      -- flag set when checksum calculation completed
+type sip_type is (sip1,sip2,sip3);          -- states of the IP header's checksum FSM
+signal sip : sip_type := sip1;
+signal unknown_request3 : std_logic := '0'; -- flag set when calculated IP header's checksum is not equal to zero
+-- ******* process udp_header_checksum_check (responsible for checking UDP header's checksum) ********--
+signal udp_presum : unsigned (23 downto 0) := (others => '0');   -- sum of the UDP header's fields
+signal udp_presum_done : std_logic := '0'; 							  -- flag set when sum of the UDP header's fields calculated
+signal udp_data_sum : unsigned (23 downto 0) := (others => '0'); -- sum of all data fields
+signal udp_datasum_done : std_logic := '0'; 							  -- flag set when sum of all data fields calculated
+signal edge_count_data : std_logic := '0'; 							  -- used to set correct format of the current data field in checksum calculations 
+signal udp_hcs_calc_temp1 : unsigned (23 downto 0) := (others => '0');   -- sum of the sums of UDP header's fields and all data fields
+signal udp_hcs_calc_temp2 : unsigned (15 downto 0) := (others => '0');   -- sum of the carry-out with main checksum body
+signal udp_hcs_calc : std_logic_vector (15 downto 0) := (others => '1'); -- calculated UDP header's checksum
+signal udp_hcs_done : std_logic := '0';     -- flag set when UDP header's checksum calculated
+type sudp_type is (sudp1,sudp2,sudp3);      -- states of the UDP header's checksum FSM
+signal sudp : sudp_type := sudp1;
+signal unknown_request4 : std_logic := '0'; -- flag set when calculated UDP header's checksum is not equal to zero
+-- ******* process data_out_ram (responsible for saving valid data into RAM) ********--
+type s_ram_type is (s_ram1, s_ram2, s_ram3, s_ram4);                              -- states of the write RAM FSM
+signal s_ram : s_ram_type := s_ram1;
+signal addr_count : unsigned (ADDR_WIDTH-1 downto 0) := (others => '0'); 			 -- address to write RAM counter
+signal data_to_ram : std_logic_vector (DATA_WIDTH-1 downto 0) := (others => '0'); -- data to write to RAM register
+signal we_ram : std_logic := '0';  -- enable write RAM
+signal rst_ram : std_logic := '0'; -- reset input signals to RAM
+-- ******* crc checker's signals ********--
+signal crc_rx : std_logic_vector (31 downto 0) := (others => '0');         -- received crc value
+signal crc_calculated : std_logic_vector (31 downto 0) := (others => '0'); -- calculated crc value
+signal crc_pass : std_logic := '0';                                        -- flag set if read crc = calculated crc
+--*************** constants ********************--
+constant arp_request : std_logic_vector (15 downto 0) := x"0001";       -- code of ARP request operation
+constant arp_hw_type : std_logic_vector (15 downto 0) := x"0001";       -- code of ARP hardware type
+constant arp_protocol_type : std_logic_vector (15 downto 0) := x"0800"; -- code of ARP protocol type
+constant arp_hw_length : std_logic_vector (7 downto 0) := x"06";        -- code of ARP hardware length for Ethernet
+constant arp_protocol_length : std_logic_vector (7 downto 0) := x"04";  -- code of ARP protocol length for IP4
+constant ip_protocol : std_logic_vector (7 downto 0) := x"11";          -- code of transport layer protocol for UDP
+constant arp : std_logic_vector (15 downto 0) := x"0806";               -- code for the upper layer protocol that uses service of Internet (ARP)
+constant ethernet : std_logic_vector (15 downto 0) := x"0800";          -- code for the upper layer protocol that uses service of Internet (IP4)
+--***********************************--
+
+-- CRC checker declaration
+component crc32_parallel
+			 port (clk100mhz : in  STD_LOGIC;
+					 data_valid : in  STD_LOGIC;
+					 data_in : in  STD_LOGIC_VECTOR (1 downto 0);
+					 rstn : in STD_LOGIC;
+					 crc : inout  STD_LOGIC_VECTOR (31 downto 0));
+end component;
+
+begin
+-- CRC checker instantiation
+	crc_checker: crc32_parallel
+					 port map (clk100mhz => clk100mhz,
+								  data_valid => start_crc,
+								  data_in => rxd,
+								  rstn => stop_crc,
+								  crc => crc_calculated);
+								  
+
+	receive: process (clk50mhz,rstn)
+	begin
+		if (rstn = '0') then -- if transciever is being reset receiver becomes idle
+			state <= idle;
+		elsif (falling_edge(clk50mhz)) then
+			case state is
+			
+			-- Idle state all Rx flags and registers reset and Rx waits until
+			-- crsdv signal is and Preamble's nibbles appear on rxd bus
+			when idle =>
+				---flags
+				byte_read_done <= (others => '0');
+				crc_pass <= '0';
+				read_frame_done <= '0';
+				rst_ram <= '0';
+				start_crc <= '0';
+				stop_crc <= '1';
+				read_eth_header_done <= '0';
+				--- header registers
+				dest_mac <= (others => '0');
+				source_mac <= (others => '0');
+				eth_prot_type <= (others => '0');
+				--- counters
+				byte_count <= 0;
+				bit_count <= 0;
+				--- data registers
+				temp_data <= (others => '0');
+				crc_rx <= (others => '0');
+				--crc_calculated <= (others => '0');
+				bytes00 <= (others => '0');
+				bytes01 <= (others => '0');
+				bytes02 <= (others => '0');
+				bytes03 <= (others => '0');
+				bytes04 <= (others => '0');
+				bytes05 <= (others => '0');
+				bytes06 <= (others => '0');
+				bytes07 <= (others => '0');
+				bytes08 <= (others => '0');
+				bytes09 <= (others => '0');
+				bytes10 <= (others => '0');
+				bytes11 <= (others => '0');
+				bytes12 <= (others => '0');
+				bytes13 <= (others => '0');
+				-- if data valid signal is asserted, no error symbol is detected and
+				-- the first Preamble's nibbles appear on rxd bus receiver goes into the next state
+				if (crsdv = '1' and rxerr = '0' and rxd = "01") then 
+					state <= wait_rx;
+				else -- else it remains idle
+					state <= idle;
+				end if;
+			
+			-- in this state receiver waits for the last nibble of SFD
+			-- and goes into the next state where it reads Ethernet header
+			when wait_rx =>
+				-- if data valid signal deasserted or error symbol detected
+				-- receiver becomes idle
+				if (crsdv = '0' or rxerr = '1') then 
+					bit_count <= 0;
+					byte_count <= 0;
+					stop_crc <= '1';
+					start_crc <= '0';
+					rst_ram <= '1';
+					state <= idle;
+				else -- else wait for the "11" nibble - last nibble of SFD
+					rst_ram <= '0';
+					if (crsdv = '1' and rxd = "01") then
+						state <= wait_rx;
+					elsif (crsdv = '1' and rxd = "11") then
+						start_crc <= '1'; -- start crc check immediately after SFD
+						stop_crc <= '0';
+						state <= read_eth_header;
+					end if;
+				end if;
+			
+			-- read first 14 bytes (destination mac,source mac and protocol type) in this state
+			when read_eth_header => 
+				-- if data valid signal deasserted or error symbol detected
+				-- receiver becomes idle and stops crc check
+				if (crsdv = '0' or rxerr = '1') then
+					bit_count <= 0;
+					byte_count <= 0;
+					stop_crc <= '1'; 
+					start_crc <= '0';
+					rst_ram <= '1';
+					state <= idle;
+				else
+					rst_ram <= '0';
+					-- read destination MAC address
+					if (byte_count <= 5 and bit_count < 3) then
+						dest_mac((5-byte_count)*8+2*bit_count+1 downto (5-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_eth_header;
+					elsif (byte_count <= 5 and bit_count = 3) then
+						dest_mac((5-byte_count)*8+2*bit_count+1 downto (5-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						state <= read_eth_header;
+					-- read source MAC address
+					elsif (byte_count > 5 and byte_count <= 11 and bit_count < 3) then
+						source_mac((11-byte_count)*8+2*bit_count+1 downto (11-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_eth_header;
+					elsif (byte_count > 5 and byte_count <= 11 and bit_count = 3) then
+						source_mac((11-byte_count)*8+2*bit_count+1 downto (11-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						state <= read_eth_header;
+					-- read upper layer protocol type
+					elsif (byte_count > 11 and byte_count <= 13 and bit_count < 3) then
+						eth_prot_type((13-byte_count)*8+2*bit_count+1 downto (13-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_eth_header;
+					elsif (byte_count > 11 and byte_count <= 13 and bit_count = 3) then
+						eth_prot_type((13-byte_count)*8+2*bit_count+1 downto (13-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 13) then
+							byte_count <= 0;
+							read_eth_header_done <= '1'; -- set flag indicating end of read Ethernet header operation
+							-- this flag also starts eth_packet_type process
+							state <= read_protocol_header; -- go to next state and read Payload fields
+						else
+							state <= read_eth_header;
+						end if;
+					end if;
+				end if;
+			
+			-- read next 28 bytes here (both ARP and IP4 have 28-byte long headers (when there are no extra fields in IP header))
+			when read_protocol_header => 
+				-- if data valid signal deasserted or error symbol detected
+				-- receiver becomes idle and stops crc check
+				if (crsdv = '0' or rxerr = '1' or unknown_request = '1') then
+					bit_count <= 0;
+					byte_count <= 0;
+					byte_read_done <= (others => '0');
+					stop_crc <= '1';
+					start_crc <= '0';
+					rst_ram <= '1';
+					state <= idle;
+				-- bytes 00 to 13 store the headers' data; 
+				-- byte_read_done flags register is being set as receiver keeps reading the header's fields
+				-- every individual flag triggers separate header parse operations in headers_parse process
+				else 
+					rst_ram <= '0';
+					-- bytes 0 and 1
+					if (byte_count <= 1 and bit_count < 3) then
+						bytes00((1-byte_count)*8+2*bit_count+1 downto (1-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count <= 1 and bit_count = 3) then
+						bytes00((1-byte_count)*8+2*bit_count+1 downto (1-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 1) then
+							byte_read_done(0) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 2 and 3	
+					elsif (byte_count > 1 and byte_count <= 3 and bit_count < 3) then
+						bytes01((3-byte_count)*8+2*bit_count+1 downto (3-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 1 and byte_count <= 3 and bit_count = 3) then
+						bytes01((3-byte_count)*8+2*bit_count+1 downto (3-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 3) then
+							byte_read_done(1) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 4 and 5	
+					elsif (byte_count > 3 and byte_count <= 5 and bit_count < 3) then
+						bytes02((5-byte_count)*8+2*bit_count+1 downto (5-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 3 and byte_count <= 5 and bit_count = 3) then
+						bytes02((5-byte_count)*8+2*bit_count+1 downto (5-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 5) then
+							byte_read_done(2) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 6 and 7
+					elsif (byte_count > 5 and byte_count <= 7 and bit_count < 3) then
+						bytes03((7-byte_count)*8+2*bit_count+1 downto (7-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 5 and byte_count <= 7 and bit_count = 3) then
+						bytes03((7-byte_count)*8+2*bit_count+1 downto (7-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 7) then
+							byte_read_done(3) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 8 and 9
+					elsif (byte_count > 7 and byte_count <= 9 and bit_count < 3) then
+						bytes04((9-byte_count)*8+2*bit_count+1 downto (9-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 7 and byte_count <= 9 and bit_count = 3) then
+						bytes04((9-byte_count)*8+2*bit_count+1 downto (9-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 9) then
+							byte_read_done(4) <= '1';
+							-- if this is IP4 packet and its header contain extra field
+							-- go and read them and come back to this state to finish
+							-- reading the regular fields
+							if (ip_extra_options = '1') then 
+								byte_count_extra <= 0;
+								state <= read_extra_ip_header;
+							else -- keep reading the header
+								state <= read_protocol_header;
+							end if;
+						end if;
+					-- bytes 10 and 11
+					elsif (byte_count > 9 and byte_count <= 11 and bit_count < 3) then
+						bytes05((11-byte_count)*8+2*bit_count+1 downto (11-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 9 and byte_count <= 11 and bit_count = 3) then
+						bytes05((11-byte_count)*8+2*bit_count+1 downto (11-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 11) then
+							byte_read_done(5) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 12 and 13
+					elsif (byte_count > 11 and byte_count <= 13 and bit_count < 3) then
+						bytes06((13-byte_count)*8+2*bit_count+1 downto (13-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 11 and byte_count <= 13 and bit_count = 3) then
+						bytes06((13-byte_count)*8+2*bit_count+1 downto (13-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 13) then
+							byte_read_done(6) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 14 and 15
+					elsif (byte_count > 13 and byte_count <= 15 and bit_count < 3) then
+						bytes07((15-byte_count)*8+2*bit_count+1 downto (15-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 13 and byte_count <= 15 and bit_count = 3) then
+						bytes07((15-byte_count)*8+2*bit_count+1 downto (15-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 15) then
+							byte_read_done(7) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 16 and 17
+					elsif (byte_count > 15 and byte_count <= 17 and bit_count < 3) then
+						bytes08((17-byte_count)*8+2*bit_count+1 downto (17-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 15 and byte_count <= 17 and bit_count = 3) then
+						bytes08((17-byte_count)*8+2*bit_count+1 downto (17-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 17) then
+							byte_read_done(8) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 18 and 19
+					elsif (byte_count > 17 and byte_count <= 19 and bit_count < 3) then
+						bytes09((19-byte_count)*8+2*bit_count+1 downto (19-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 17 and byte_count <= 19 and bit_count = 3) then
+						bytes09((19-byte_count)*8+2*bit_count+1 downto (19-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 19) then
+							byte_read_done(9) <= '1'; -- this flag starts ip_header_checksum_check process
+						end if;
+						state <= read_protocol_header;
+					-- bytes 20 and 21
+					elsif (byte_count > 19 and byte_count <= 21 and bit_count < 3) then
+						bytes10((21-byte_count)*8+2*bit_count+1 downto (21-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 19 and byte_count <= 21 and bit_count = 3) then
+						bytes10((21-byte_count)*8+2*bit_count+1 downto (21-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 21) then
+							byte_read_done(10) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 22 and 23
+					elsif (byte_count > 21 and byte_count <= 23 and bit_count < 3) then
+						bytes11((23-byte_count)*8+2*bit_count+1 downto (23-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 21 and byte_count <= 23 and bit_count = 3) then
+						bytes11((23-byte_count)*8+2*bit_count+1 downto (23-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 23) then
+							byte_read_done(11) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 24 and 25
+					elsif (byte_count > 23 and byte_count <= 25 and bit_count < 3) then
+						bytes12((25-byte_count)*8+2*bit_count+1 downto (25-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 23 and byte_count <= 25 and bit_count = 3) then
+						bytes12((25-byte_count)*8+2*bit_count+1 downto (25-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 25) then
+							byte_read_done(12) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 26 and 27
+					elsif (byte_count > 25 and byte_count <= 27 and bit_count < 3) then
+						bytes13((27-byte_count)*8+2*bit_count+1 downto (27-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 25 and byte_count <= 27 and bit_count = 3) then
+						bytes13((27-byte_count)*8+2*bit_count+1 downto (27-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 27) then
+							byte_read_done(13) <= '1';-- this flag starts udp_header_checksum_check process
+							byte_count <= 0;
+							-- if data field is empty in this packet go and read zero-padded fields
+							if(data_counter_max = 0) then
+								state <= read_zero_padding;
+							else -- else read valid data
+								state <= read_data;
+							end if;
+						else 
+							state <= read_protocol_header;
+						end if;
+					end if;
+				end if;
+				
+				-- read extra ip_options_count_max-1 bytes of ip header
+				-- this design makes no use of extra fields, but they are important
+				-- for correct packet parsing and checksum calculations!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+				when read_extra_ip_header => 
+					-- if data valid signal deasserted or error symbol detected
+					-- receiver becomes idle and stops crc check
+					if (crsdv = '0' or rxerr = '1' or unknown_request = '1') then
+						bit_count <= 0;
+						byte_count <= 0;
+						byte_read_done <= (others => '0');
+						stop_crc <= '1';
+						start_crc <= '0';
+						rst_ram <= '1';
+						state <= idle;
+					else
+						rst_ram <= '0';
+						if (byte_count_extra <= ip_options_count_max-1 and bit_count < 3) then
+							ip_header_options((ip_options_count_max-1-byte_count_extra)*8+2*bit_count+1 downto (ip_options_count_max-1-byte_count_extra)*8+2*bit_count) <= rxd;
+							bit_count <= bit_count+1;
+							state <= read_extra_ip_header;
+						elsif (byte_count_extra <= ip_options_count_max-1 and bit_count = 3) then
+							ip_header_options((ip_options_count_max-1-byte_count_extra)*8+2*bit_count+1 downto (ip_options_count_max-1-byte_count_extra)*8+2*bit_count) <= rxd;
+							bit_count <= 0;
+							if (byte_count_extra < ip_options_count_max-1) then
+								byte_count_extra <= byte_count_extra+1;
+								state <= read_extra_ip_header;
+							elsif (byte_count_extra = ip_options_count_max-1) then
+								byte_count_extra <= 0;
+								state <= read_protocol_header; -- when done reading extra header's fields 
+								-- go back and finish reading the regular ones
+							end if;
+						end if;
+					end if;
+				
+				-- when packet contains valid data, read it here
+				when read_data =>
+					-- if data valid signal deasserted or error symbol detected
+					-- receiver becomes idle and stops crc check
+					if (crsdv = '0' or rxerr = '1' or unknown_request = '1') then
+						bit_count <= 0;
+						byte_count <= 0;
+						byte_read_done <= (others => '0');
+						stop_crc <= '1';
+						start_crc <= '0';
+						rst_ram <= '1';
+						state <= idle;
+					else 
+					-- every data byte is stored into temporary register from where it is transfered to RAM
+						rst_ram <= '0';
+						if (byte_count <= data_counter_max-1 and bit_count < 3) then
+							temp_data(2*bit_count+1 downto 2*bit_count) <= rxd;
+							bit_count <= bit_count+1;
+							valid_data_byte_read <= '0';
+							state <= read_data;
+						elsif (byte_count <= data_counter_max-1 and bit_count = 3) then
+							temp_data(2*bit_count+1 downto 2*bit_count) <= rxd;
+							bit_count <= 0;
+							byte_count <= byte_count+1;
+							valid_data_byte_read <= '1'; -- this flad triggers data transfer to RAM (process data_out_ram)
+							if (byte_count = data_counter_max-1) then
+								byte_count <= 0;
+								if (zero_counter /= 0) then -- if packet contains any zero-padded data fields go and read them
+									state <= read_zero_padding;
+								else -- else if there is no zero-padding stop crc checker and read incoming crc 
+									start_crc <= '0';
+									state <= read_crc;
+								end if;
+							else
+								state <= read_data;
+							end if;
+						end if;
+					end if;
+					
+				-- when packet contains zero-padded data fields, read it here
+				when read_zero_padding =>
+					valid_data_byte_read <= '0'; -- clear the flag set when the last data byte was read
+					-- if data valid signal deasserted or error symbol detected
+					-- receiver becomes idle and stops crc check
+					if (crsdv = '0' or rxerr = '1' or unknown_request = '1') then
+						bit_count <= 0;
+						byte_count <= 0;
+						byte_read_done <= (others => '0');
+						stop_crc <= '1'; --------------------------------------------crc
+						start_crc <= '0';--------------------------------------------crc
+						rst_ram <= '1';
+						state <= idle;
+					else -- zero-padding simply discarded, not stored
+						rst_ram <= '0';
+						if (byte_count <= zero_counter-1 and bit_count < 3) then
+							bit_count <= bit_count+1;
+							state <= read_zero_padding;
+						elsif (byte_count <= zero_counter-1 and bit_count = 3) then
+							bit_count <= 0;
+							byte_count <= byte_count+1;
+							if (byte_count+1 > zero_counter-1) then
+								byte_count <= 0;
+								start_crc <= '0';-- stop crc checker here
+								state <= read_crc;
+							else
+								state <= read_zero_padding;
+							end if;
+						end if;
+					end if;
+				
+				-- read crc field
+				-- validity of Rx data isn't checked, since any problems on the bus/lines
+				-- will be reflected on the crc field content and the packet will not pass crc check
+				when read_crc =>
+					valid_data_byte_read <= '0';-- clear the flag set when the last data byte was read
+					if (byte_count <= 3 and bit_count < 3) then
+						crc_rx((3-byte_count)*8+2*(3-bit_count)+1) <= rxd(0);
+						crc_rx((3-byte_count)*8+2*(3-bit_count)) <= rxd(1);
+						bit_count <= bit_count+1;
+						state <= read_crc;
+					elsif (byte_count <= 3 and bit_count = 3) then
+						crc_rx((3-byte_count)*8+2*(3-bit_count)+1) <= rxd(0);
+						crc_rx((3-byte_count)*8+2*(3-bit_count)) <= rxd(1);
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 3) then
+							byte_count <= 0;
+							read_frame_done <= '1';-- flag indicating the end of frame; resets RAM's signals
+							state <= check_crc; --
+						else
+							state <= read_crc;
+						end if;
+					end if;
+				
+				-- here calculated and received crc values are compared
+				when check_crc =>
+					if (crc_rx = crc_calculated) then
+						crc_pass <= '1'; -- if they are the same - packet is valid
+						rst_ram <= '0';
+					else
+						crc_pass <= '0'; -- else reject packet
+						rst_ram <= '1';
+					end if;
+					-- clear flags here
+					read_eth_header_done <= '0';
+					read_frame_done <= '0';
+					state <= idle;
+						
+			   end case;
+		end if;		
+	end process receive;
+	
+	-- this process start after Ethernet header is read and it decides whether to accept or
+	-- reject packet (when it's not addressed to FPGA, for example) and determines
+	-- the type of the upper layer protocol
+	eth_packet_type: process (read_eth_header_done,dest_mac,eth_prot_type,
+	fpga_mac,clk50mhz)
+		begin
+		if(rising_edge(clk50mhz)) then
+				if (read_eth_header_done = '1') then -- decision is made immediately after Ethernet header
+				-- has been read and it is maintained until the whole packet is read or any error is encountered
+					if ((dest_mac = x"ffffffffffff" or dest_mac = fpga_mac) and eth_prot_type = arp) then -- ARP request
+						arp_request_expected <= '1';
+						eth_protocol_expected <= '0';
+						unknown_request1 <= '0';
+					elsif ((dest_mac = x"ffffffffffff" or dest_mac = fpga_mac) and eth_prot_type = ethernet) then -- IP4 protocol
+						arp_request_expected <= '0';
+						eth_protocol_expected <= '1';
+						unknown_request1 <= '0';
+					else -- none of the above - reject packet
+						arp_request_expected <= '0';
+						eth_protocol_expected <= '0';
+						unknown_request1 <= '1'; -- flag indicating invalid packet set
+					end if;
+				else -- refresh protocol type registers
+					arp_request_expected <= '0';
+					eth_protocol_expected <= '0';
+					unknown_request1 <= '0';
+				end if;
+		end if;
+	end process eth_packet_type;
+	
+	-- this process parses headers based on the type of protocol detected by the process eth_packet_type
+	-- in case of any mismatch between expected and actual headers' fields the packets are rejected
+	headers_parse : process (byte_read_done,arp_request_expected,eth_protocol_expected,data_counter_max,source_mac,
+	fpga_ip,fpga_port,ip_header_length,bytes00,bytes01,bytes02,bytes03,
+	bytes04,bytes05,bytes06,bytes07,bytes08,bytes09,bytes10,bytes11,bytes12,bytes13,clk50mhz)
+	begin
+	if (rising_edge(clk50mhz)) then
+			-- if Ethernet header corresponds to ARP request
+			if (arp_request_expected = '1' and eth_protocol_expected = '0') then
+				-- the following registers are set to zero, since they are for the IP4/UDP protocols, not for ARP
+				ip_extra_options <= '0';
+				source_ip <= (others => '0');
+				source_port <= (others => '0');
+				ip_options_count_max <= 0;
+				udp_length <= (others => '0');
+				udp_checksum <= (others => '0');
+				ip_header_length <= (others => '0');
+				ip_total_length <= (others => '0');
+				ip_header_checksum <= (others => '0');
+				-- bytes00
+				if (byte_read_done(0)='1') then
+					if (arp_hw_type = bytes00) then -- if ARP hardware type read matches expected value
+						unknown_request2 <= '0'; 	  -- let packet pass
+					else
+						unknown_request2 <= '1';     -- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes01
+				if (byte_read_done(1)='1') then
+					if (arp_protocol_type = bytes01) then -- if ARP hardware type read matches expected value
+						unknown_request2 <= '0';           -- let packet pass
+					else
+						unknown_request2 <= '1';           -- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes02
+				if (byte_read_done(2)='1') then
+					-- if ARP hardware length and protocol length read match expected values
+					if (arp_hw_length = bytes02(15 downto 8) and arp_protocol_length = bytes02(7 downto 0)) then
+						unknown_request2 <= '0';           -- let packet pass
+					else
+						unknown_request2 <= '1';			  -- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes03
+				if (byte_read_done(3)='1') then
+					if (arp_request = bytes03) then -- if ARP request received
+						data_counter_max <= 0;  	  -- arp request has no data
+						zero_counter <= 18;			  -- arp request has 18 bytes of zero padding
+						unknown_request2 <= '0';	  -- let packet pass
+					else
+						data_counter_max <= 0; 
+						zero_counter <= 0;
+						unknown_request2 <= '1';	  -- else reject it
+					end if;
+				else 								        -- refresh data and zero count registers
+					data_counter_max <= 0; 
+					zero_counter <= 0;
+					unknown_request2 <= '0';
+				end if;
+				-- bytes04, bytes05, bytes06
+				if (byte_read_done(4)='1' and byte_read_done(5)='1' and byte_read_done(6)='1') then
+					if (source_mac = bytes04&bytes05&bytes06) then -- if source MAC matches the one read in Ethernet header
+						unknown_request2 <= '0';						  -- let packet pass
+					else
+						unknown_request2 <= '1';						  -- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes07, bytes08
+				if (byte_read_done(7)='1' and byte_read_done(8)='1') then
+					source_ip <= bytes07&bytes08; -- read source IP4 address
+				else
+					source_ip <= (others =>'0');  -- refresh source IP4 address register
+				end if;
+				-- bytes09, bytes10, bytes11
+				if (byte_read_done(9)='1' and byte_read_done(10)='1' and byte_read_done(11)='1') then
+					if (bytes09&bytes10&bytes11 = x"000000000000" or bytes09&bytes10&bytes11 = fpga_mac) then -- if target MAC address is zeros
+						unknown_request2 <= '0';								 -- let packet pass
+					else
+						unknown_request2 <= '1';								 -- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes12, bytes13
+				if (byte_read_done(12)='1' and byte_read_done(13)='1') then
+					if (fpga_ip = bytes12&bytes13) then -- if destination IP4 address = FPGA IP4 address
+						unknown_request2 <= '0';			-- let packet pass
+					else
+						unknown_request2 <= '1';			-- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+			-- if Ethernet header corresponds to IP4/UDP protocol
+			elsif (arp_request_expected = '0' and eth_protocol_expected = '1') then
+				-- bytes00
+				if (byte_read_done(0)='1') then
+					if (bytes00(15 downto 12) = "0100") then -- if IP version = 4 
+						unknown_request2 <= '0';				  -- let packet pass
+					else
+						unknown_request2 <= '1';				  -- else reject it
+					end if;
+					ip_header_length <= bytes00(11 downto 8);-- read IP header's length
+					if (4*to_integer(unsigned(ip_header_length)) > 20)then 						-- if it's greater than 20 bytes
+						ip_options_count_max <= 4*to_integer(unsigned(ip_header_length))-20; -- set extra header's field counter
+						ip_extra_options <= '1'; 															-- set flag indicating presence of extra header's fields
+					else
+						ip_options_count_max <= 0;                                           -- else thre are no extra header's fields
+						ip_extra_options <= '0';
+					end if;
+					-- differentiated services are ignored (bits 7 to 0 of bytes00)
+				else -- refresh registers
+					unknown_request2 <= '0';
+					ip_header_length <= x"0";
+					ip_options_count_max <= 0;
+					ip_extra_options <= '0';
+				end if;
+				-- bytes01
+				if (byte_read_done(1)='1') then
+					ip_total_length <= bytes01; -- read total length of IP datagram (header+data) in bytes
+					data_counter_max <= to_integer(unsigned(bytes01))- 4*to_integer(unsigned(bytes00(11 downto 8)))-8;-- set counter for data here
+					--example: 25(=37)-4*5-8=9 (from 0 to 8) = 9 bytes of data; 8 - is the UDP header length in bytes; 4*5 - is IP header length
+					if (data_counter_max < 18) then -- 8<17 - true; if less than 18 there are zero-padded data fields
+						zero_counter <= 18-data_counter_max; -- 18-9-1=8 (from 0 to 8) = 9 bytes of zeros
+					else
+						zero_counter <= 0;
+					end if;
+				else
+					ip_total_length <= (others => '0');
+					data_counter_max <= 0;
+					zero_counter <= 0;
+				end if;
+				-- bytes02
+				if (byte_read_done(2)='1') then
+					identification <= bytes02; -- read Identification field
+				else 
+					identification <= (others => '0');
+				end if;
+				-- bytes03
+				if (byte_read_done(3)='1') then
+					flags_offset <= bytes03;   -- read Flags and Fragmentation offsets (not used in the design)
+				else 
+					flags_offset <= (others => '0');
+				end if;
+				-- bytes04
+				if (byte_read_done(4)='1') then
+					if (ip_protocol = bytes04(7 downto 0)) then -- if higher level protocol is UDP 
+						unknown_request2 <= '0';					  -- let packet pass
+					else
+						unknown_request2 <= '1';					  -- else reject it
+					end if;
+				-- Time to Live parameter is ignored (bits 15 to 8 of bytes04)
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes05
+				if (byte_read_done(5)='1') then
+					ip_header_checksum <= bytes05; -- read IP header's checksum
+				else
+					ip_header_checksum <= (others => '0');
+				end if;
+				-- bytes06, bytes07
+				if (byte_read_done(6)='1' and byte_read_done(7)='1') then
+					source_ip <= bytes06&bytes07;  -- read source IP4 address
+				else
+					source_ip <= (others => '0');
+				end if;
+				-- bytes08, bytes09
+				if (byte_read_done(8)='1' and byte_read_done(9)='1') then
+					if (fpga_ip = bytes08&bytes09) then -- if destination IP4 address = FPGA IP4 address
+						unknown_request2 <= '0';         -- let packet pass
+					else
+						unknown_request2 <= '1';			-- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes10
+				if (byte_read_done(10)='1') then
+					source_port <= bytes10; 				-- read source port number
+				else
+					source_port <= (others => '0');
+				end if;
+				-- bytes11
+				if (byte_read_done(11)='1') then
+					if (fpga_port = bytes11) then      -- if destination port number = FPGA port number
+						unknown_request2 <= '0';		  -- let packet pass
+					else
+						unknown_request2 <= '1';        -- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes12
+				if (byte_read_done(12)='1') then
+					udp_length <= bytes12;				 -- read UDP protocol length
+				else
+					udp_length <= (others => '0');
+				end if;
+				-- bytes13
+				if (byte_read_done(13)='1') then
+					udp_checksum <= bytes13;		    -- read UDP checksum
+				else
+					udp_checksum <= (others => '0');
+				end if;
+			-- refresh headers' registers
+			else
+				unknown_request2 <= '0';
+				ip_extra_options <= '0';
+				source_ip <= (others => '0');
+				source_port <= (others => '0');
+				data_counter_max <= 0;
+				zero_counter <= 0;
+				ip_options_count_max <= 0;
+				udp_length <= (others => '0');
+				udp_checksum <= (others => '0');
+				ip_header_length <= (others => '0');
+				ip_total_length <= (others => '0');
+				ip_header_checksum <= (others => '0');
+			end if;
+	end if;
+	end process headers_parse;
+	
+	-- this process handles IP header checksum calculations, note checksum is not calculated for ARP protocol
+	ip_header_checksum_check: process (clk50mhz,byte_read_done(9),ip_header_checksum,arp_request_expected,eth_protocol_expected,
+	ip_extra_options,ip_options_count_max,ip_header_options)
+	begin
+	if (rising_edge(clk50mhz)) then
+		-- if IP4 protocol received and IP header is read and checksum hasn't been calculated, calculate it here
+		if (arp_request_expected = '0' and eth_protocol_expected = '1' and byte_read_done(9)='1' and ip_hcs_done = '0') then
+			case sip is
+				when sip1 =>
+					if (ip_extra_options = '1') then                   -- take into account IP header extra field
+						for j in 39 downto 0 loop                       -- 40-1=39 - max length of extra field in bytes
+							edge_count_header <= not(edge_count_header); -- keeps track of senior/junior byte
+							if (ip_header_options(j*8+7 downto j*8+0) = x"00") then
+								ip_hcs_calc_extra <= ip_hcs_calc_extra; 	-- find first non-zero byte here
+							else
+								if (edge_count_header = '0') then            -- senior byte was received first
+									ip_hcs_calc_extra <= ip_hcs_calc_extra+unsigned(ip_header_options(j*8+7 downto j*8+0)&x"00");
+								elsif (edge_count_header = '1') then         -- junior byte was received second
+									ip_hcs_calc_extra <= ip_hcs_calc_extra+unsigned(x"00"&ip_header_options(j*8+7 downto j*8+0));
+								end if;
+							end if;
+						end loop;
+					elsif (ip_extra_options = '0') then -- if no IP header extra options - it's just zero
+						edge_count_header <= '0';
+						ip_hcs_calc_extra <= (others => '0');
+					end if;
+					ip_hcs_calc_temp1 <= ip_hcs_calc_temp1+unsigned(bytes00)+unsigned(ip_total_length)+unsigned(identification)+
+					unsigned(flags_offset)+unsigned(bytes04)+unsigned(ip_header_checksum)+unsigned(bytes06)+
+					unsigned(bytes07)+unsigned(bytes08)+unsigned(bytes09)+ip_hcs_calc_extra; -- sum all the IP header's fields here
+					sip <= sip2;
+				when sip2 =>
+					ip_hcs_calc_temp2 <= not(ip_hcs_calc_temp2+ip_hcs_calc_temp1(15 downto 0)+ip_hcs_calc_temp1(23 downto 16)); -- add carry-out to checksum
+					sip <= sip3;
+				when sip3 =>
+					ip_hcs_calc <= std_logic_vector(ip_hcs_calc_temp2); -- complement the result
+					ip_hcs_done <= '1';											 -- set flag indicating completion of IP header checksum calculations
+					sip <= sip3;
+			end case;
+		-- if IP headers checksum has already been calculated keep the result
+		elsif (arp_request_expected = '0' and eth_protocol_expected = '1' and byte_read_done(9)='1' and ip_hcs_done = '1') then
+			ip_hcs_calc <= ip_hcs_calc;
+			ip_hcs_done <= ip_hcs_done;
+			ip_hcs_calc_temp1 <= ip_hcs_calc_temp1;
+			ip_hcs_calc_temp2 <= ip_hcs_calc_temp2;
+		else -- refresh IP headers checksum registers
+			ip_hcs_calc <= (others => '1');
+			ip_hcs_calc_temp1 <= (others => '0');
+			ip_hcs_calc_temp2 <= (others => '0');
+			ip_hcs_done <= '0';
+			sip <= sip1;
+		end if;
+		-- verify ip header checksum
+		if (ip_hcs_done = '1') then
+			if (ip_hcs_calc = x"0000") then -- if calculated checksum = 0
+				unknown_request3 <= '0';     -- let packet pass
+			else
+				unknown_request3 <= '1';     -- else reject it
+			end if;
+		else
+			unknown_request3 <= '0';
+		end if;
+	end if;
+	end process ip_header_checksum_check;
+	
+	-- this process handles UDP header checksum calculations, note checksum is not calculated for ARP protocol
+	udp_header_checksum_check: process (clk50mhz,byte_read_done(13),bytes13,arp_request_expected,eth_protocol_expected,
+	source_port,source_ip,fpga_ip,fpga_port,udp_length,temp_data,valid_data_byte_read,start_crc,stop_crc)
+	begin
+		if (rising_edge(clk50mhz)) then
+		-- if IP4 protocol received and UDP header is read and checksum hasn't been calculated, calculate it here
+			if (arp_request_expected = '0' and eth_protocol_expected = '1' and byte_read_done(13)='1' and udp_presum_done = '0') then
+				udp_presum <= udp_presum+unsigned(source_ip(31 downto 16))+unsigned(source_ip(15 downto 0))+unsigned(fpga_ip(31 downto 16))+
+				unsigned(fpga_ip(15 downto 0))+unsigned(x"00"&ip_protocol)+unsigned(udp_length)+unsigned(source_port)+unsigned(fpga_port)+
+				unsigned(udp_length)+unsigned(bytes13); -- presum calculates the first summand of UDP checksum comprising only header's fields
+				udp_presum_done <= '1';						 -- flag indicating the presum was calculated
+			-- maintain presum value once it was calculated
+			elsif (arp_request_expected = '0' and eth_protocol_expected = '1' and byte_read_done(13)='1' and udp_presum_done = '1') then
+				udp_presum <= udp_presum;
+				udp_presum_done <= udp_presum_done;
+			else -- reset presum here
+				udp_presum <= (others => '0');
+				udp_presum_done <= '0';
+			end if;
+			-- the second summand of UDP checksum, conmprising data fields, is calculated here 
+			if (valid_data_byte_read='1' and start_crc ='1' and stop_crc ='0') then -- once valid data byte was read and this is not the last data byte
+				edge_count_data <= not(edge_count_data); 										-- add it to the second checksum summand
+				if (edge_count_data = '0') then                                      -- edge count controls format of addition
+					udp_data_sum <= udp_data_sum+unsigned(temp_data&x"00");
+				elsif (edge_count_data = '1') then
+					udp_data_sum <= udp_data_sum+unsigned(x"00"&temp_data);
+				end if;
+			elsif (valid_data_byte_read='0' and start_crc ='1' and stop_crc ='0') then
+				edge_count_data <= edge_count_data;
+				udp_data_sum <= udp_data_sum;
+			elsif (start_crc ='0' and stop_crc ='0') then -- these flags defines the start of crc field on receive
+				edge_count_data <= '0';
+				udp_data_sum <= udp_data_sum;
+				udp_datasum_done <= '1';						 -- calculation of the second summand is over
+			elsif (stop_crc ='1') then							 -- refresh the second summand's register
+				edge_count_data <= '0';
+				udp_data_sum <= (others => '0');
+				udp_datasum_done <= '0';
+			end if;
+			if (udp_presum_done = '1' and udp_datasum_done = '1' and udp_hcs_done = '0') then -- if both summands are calculated find checksum
+				case sudp is
+					when sudp1 =>
+						udp_hcs_calc_temp1 <= udp_presum+udp_data_sum; 									 -- add 2 summand together
+						sudp <= sudp2;
+					when sudp2 =>
+						udp_hcs_calc_temp2 <= not(udp_hcs_calc_temp2+udp_hcs_calc_temp1(15 downto 0)+udp_hcs_calc_temp1(23 downto 16)); -- add carry-out
+						sudp <= sudp3;
+					when sudp3 =>
+						udp_hcs_calc <= std_logic_vector(udp_hcs_calc_temp2);							 -- find checksum
+						udp_hcs_done <= '1';																		 -- set flag
+						sudp <= sudp3;
+				end case;
+			elsif (udp_presum_done = '1' and udp_datasum_done = '1' and udp_hcs_done = '1') then -- maintain calculated checksum value
+				udp_hcs_calc_temp1 <= udp_hcs_calc_temp1;
+				udp_hcs_calc_temp2 <= udp_hcs_calc_temp2;
+				udp_hcs_calc <= udp_hcs_calc;
+				udp_hcs_done <= udp_hcs_done;
+			else -- refresh UDP checksum registers
+				udp_hcs_calc_temp1 <= (others => '0');
+				udp_hcs_calc_temp2 <= (others => '0');
+				udp_hcs_calc <= (others => '1');
+				udp_hcs_done <= '0';
+				sudp <= sudp1;
+			end if;
+			if (udp_hcs_done = '1') then
+				if (udp_hcs_calc = x"0000") then -- if calculated checksum = 0
+					unknown_request4 <= '0';		-- let packet pass
+				else
+					unknown_request4 <= '1';		-- else reject it
+				end if;
+			else
+				unknown_request4 <= '0';
+			end if;
+		end if;
+	end process udp_header_checksum_check;
+	
+	-- this process transfers data to transmitter for reply
+	data_out: process (crc_pass,read_frame_done,source_mac,source_ip,source_port,arp_request_expected,eth_protocol_expected,clk50mhz)
+	begin
+	if(rising_edge(clk50mhz)) then
+		if (crc_pass = '1') then -- if data packet passed crc check and it's a valid packet
+			-- pass data required to assemble Tx packet to transmitter
+			pc_mac <= source_mac;   			 -- PC's MAC address
+			pc_ip <= source_ip;     			 -- PC's IP4 address
+			pc_port <= source_port; 			 -- PC's port number
+			datacm <= std_logic_vector(to_signed(data_counter_max, ADDR_WIDTH+1)); -- length of the data field
+			udpl <= udp_length;    				 -- UDP header+data length
+			udpc <= udp_checksum;   			 -- UDP checksum (same for Rx and Tx, since it's an echo server)
+			data_out_valid <= '1';
+			if (arp_request_expected = '1') then
+				send_arp_reply <= '1';			 -- tell Tx to send ARP reply if ARP request was received
+				send_ethernet_protocol <= '0';
+			elsif (eth_protocol_expected = '1') then
+				send_arp_reply <= '0';
+				send_ethernet_protocol <= '1'; -- tell Tx to send UDP packet if UDP packet was received
+			else 										 -- no valid packet has been received, no reply will be sent
+				send_arp_reply <= '0';
+				send_ethernet_protocol <= '0';
+			end if;
+		else -- until the received packet passes crc check no data transferred to transmitter
+			pc_mac <= (others => '0');
+			pc_ip <= (others => '0');
+			pc_port <= (others => '0');
+			datacm <= (others => '0');
+			udpl <= (others => '0');
+			udpc <= (others => '0');
+			data_out_valid <= '0';
+			send_arp_reply <= '0';
+			send_ethernet_protocol <= '0';
+		end if;
+	end if;
+	end process data_out;
+	
+	-- this process takes care of saving received data to RAM
+	data_out_ram: process (clk50mhz,temp_data,valid_data_byte_read,addr_count,read_frame_done,data_to_ram,we_ram,rst_ram)
+	begin -- don't forget to reset ram if invalid signal
+		if(rising_edge(clk50mhz)) then
+			case s_ram is
+				when s_ram1 =>
+					if (valid_data_byte_read = '1') then -- if valid data byte was read write it to RAM
+						data_to_ram <= temp_data;
+						we_ram <= '1';
+						s_ram <= s_ram2;
+					elsif (read_frame_done = '1' or rst_ram = '1') then -- at the end of the frame or in case of error reset RAM's signals
+						data_to_ram <= (others => '0');
+						addr_count <= (others => '0');
+						we_ram <= '0';
+						s_ram <= s_ram4;
+					else
+						data_to_ram <= data_to_ram;
+						addr_count <= addr_count;
+						we_ram <= '0';
+						s_ram <= s_ram1;
+					end if;
+				when s_ram2 =>
+					data_to_ram <= data_to_ram;
+					we_ram <= '1';
+					addr_count <= addr_count;
+					s_ram <= s_ram3;
+				when s_ram3 =>
+					data_to_ram <= data_to_ram;
+					we_ram <= '0';
+					if (addr_count+1 > 2**ADDR_WIDTH-1) then
+						addr_count <= (others => '0');
+					else
+						addr_count <= addr_count+1;
+					end if;
+					s_ram <= s_ram1;
+				when s_ram4 =>
+					data_to_ram <= (others => '0');
+					addr_count <= (others => '0');
+					we_ram <= '0';
+					s_ram <= s_ram1;
+				end case;
+		end if;
+		-- attach RAM signals to RAM ports
+		wrt_data_ram <= data_to_ram;
+		wrt_addr_ram <= std_logic_vector(addr_count);
+		wrt_enable_ram <= we_ram;
+	end process data_out_ram;
+
+unknown_request <= unknown_request1 or unknown_request2 or unknown_request3 or unknown_request4; -- all flags indicating invalid packet formats are ORed here
+
+end Behavioral;
+

ip_repo_sources/UDP-server/src/eth_transmitter.vhd

@@ -0,0 +1,675 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov 
+-- 
+-- Create Date:    15:13:44 02/24/2017 
+-- Design Name: 
+-- Module Name:    eth_transmitter - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- Ethernet transmitter module hadles transmission of data packets back to the data
+-- server and performs all necessary operations, related to packet assembly, based
+-- on the data passed from receiver. It includes 4 processes and 1 sub-module:
+-- - process to write data out;
+-- - process to receive data from Receiver module;
+-- - process to create protocol headers (Ethernet, ARP, IP4, UDP) for the packet to be transmitted;
+-- - process for IP header checksum calculations;
+-- - sub-module for crc calculations;
+-- Data to be trasnmitted is retrieved from RAM block by the main Transmit process.
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_unsigned.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity eth_transmitter is
+	 Generic (ADDR_WIDTH : integer;
+				 DATA_WIDTH : integer);
+    Port ( clk100mhz : in  STD_LOGIC;     -- clock for crc calculator
+			  clk50mhz_shift : in STD_LOGIC; -- provides required set-up and hold time for TX signals with respect to reference clock
+			  rstn : in STD_LOGIC;
+           txd : inout  STD_LOGIC_VECTOR (1 downto 0);
+           txen : out  STD_LOGIC;
+			  -- RAM signals
+			  rd_data_ram : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
+			  rd_addr_ram : out STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
+			  rd_enable_ram : out STD_LOGIC;
+			  -- Addresses
+			  fpga_mac : in STD_LOGIC_VECTOR (47 downto 0);
+			  fpga_ip : in STD_LOGIC_VECTOR (31 downto 0);
+			  fpga_port : in STD_LOGIC_VECTOR (15 downto 0);
+			  pc_mac : in STD_LOGIC_VECTOR (47 downto 0);
+			  pc_ip : in  STD_LOGIC_VECTOR (31 downto 0);
+			  pc_port : in STD_LOGIC_VECTOR (15 downto 0);
+			  -- Data from Rx
+			  datacm : in STD_LOGIC_VECTOR (ADDR_WIDTH downto 0);
+			  udpl : in STD_LOGIC_VECTOR (15 downto 0);
+			  udpc : in STD_LOGIC_VECTOR (15 downto 0);
+			  send_arp_reply : in STD_LOGIC;
+			  send_ethernet_protocol: in STD_LOGIC;
+			  data_in_valid : in STD_LOGIC);
+end eth_transmitter;
+
+architecture Behavioral of eth_transmitter is
+-- SIGNALS
+-- ******* process transmit (responsible for handling Tx) ********--
+type state_type is (idle, tx_preamble, tx_sfd, tx_eth_frame_header, tx_protocol_header, tx_data, tx_zero_padding, tx_crc);
+signal state : state_type := idle;
+signal bit_count : integer range 0 to 3 := 0;								-- counts number of nibbles transmitted
+signal byte_count : integer range 0 to 1499 := 0;							-- counts number of bytes transmitted
+constant preamble : std_logic_vector (7 downto 0) := x"55";          -- preamble
+constant sfd : std_logic_vector (7 downto 0) := x"d5";               -- SFD
+signal dest_mac : std_logic_vector (47 downto 0) := (others => '0'); -- destination MAC address
+signal dest_ip : std_logic_vector (31 downto 0) := (others => '0');  -- destination IP4 address
+signal dest_port : std_logic_vector (15 downto 0) := (others => '0');-- destination Mport number
+signal eth_type : std_logic_vector(15 downto 0) := (others => '0');  -- upper layer type of protocol
+signal byte0, byte1, byte2, byte3, byte4, byte5, byte6, byte7, byte8,
+byte9, byte10, byte11, byte12, byte13, byte14, byte15, byte16, byte17, byte18,
+byte19, byte20, byte21, byte22, byte23, byte24, byte25, byte26, byte27 : std_logic_vector (7 downto 0);-- registers to store parsed headers
+signal data_counter_max : integer range 0 to 1471 := 0; -- defines length of data field in bytes without zero padding
+signal zero_counter : integer range 0 to 18 := 0;       -- defines length of zero-padded data field
+signal temp_data : std_logic_vector (DATA_WIDTH-1 downto 0) := x"00"; -- register to store data read from RAM before transmission
+signal start_crc : std_logic := '0'; -- enable crc calculator 
+signal stop_crc : std_logic := '0';  -- reset crc calculator
+signal tx_ready : std_logic := '0';  -- flag indicating that packet is ready for transmission
+signal tx_done : std_logic := '0';   -- flag indicating completion of packet transmission 
+signal crc_calculated : std_logic_vector (31 downto 0) := (others => '0'); -- calculated crc value for packet being transmitted
+-- ******* process set_tx_format (responsible for setting format of the packet to be transmitted) ********--
+signal arp_reply : std_logic := '0';    -- sets ARP as higher layer protocol
+signal eth_protocol : std_logic := '0'; -- flag sets IP as higher layer protocol       
+signal ip_total_length : std_logic_vector (15 downto 0) := (others => '0'); -- stores IP header+data length in bytes (from receiver)
+signal udp_length :std_logic_vector (15 downto 0) := (others => '0');       -- stores UDP header+data length in bytes (from receiver)
+signal udp_checksum : std_logic_vector (15 downto 0) := (others => '0');    -- stores UDP checksum value (from receiver)
+signal id_counter : unsigned (15 downto 0) := (others => '0');              -- Identification parameter for the outgoing packet
+-- ******* process ip_header_checksum_calc (responsible for IP header checksum calculation) ********--
+signal ip_header_checksum : std_logic_vector (15 downto 0) := (others => '0'); -- calculated IP header checksum
+signal temp_iphc1 : unsigned (23 downto 0) := (others => '0');	-- sum of all header's fields
+signal temp_iphc2 : unsigned (15 downto 0) := (others => '0');	-- sum of the carry-out with main checksum body
+signal ip_header_calc_done : std_logic := '0';						-- flag set when checksum calculation completed
+type s_type is (s1,s2,s3);													-- states of the IP header's checksum FSM
+signal s : s_type := s1;
+-- ******* constants for process set_tx_data (responsible for setting registers storing parsed headers) ********--
+constant ip_version : std_logic_vector (3 downto 0) := "0100";       -- code for IP version = 4 
+constant ip_header_length : std_logic_vector (3 downto 0) := "0101"; -- code for IP header length = 5 -> 20 bytes 
+constant ipl : unsigned (15 downto 0) := x"0014";                      -- IP header length - fixed = 20 bytes
+constant flags_offset : std_logic_vector (15 downto 0) := x"0000";   -- flags, offsets and fragmentation
+constant ttl : std_logic_vector (7 downto 0) := x"80";               -- time to live for the datagram
+constant ds : std_logic_vector (7 downto 0) := x"00";                -- differentiated services
+constant ip_protocol : std_logic_vector (7 downto 0) := x"11";       -- code of UDP protocol type
+constant arp_operation : std_logic_vector(15 downto 0) := x"0002";   -- code of ARP reply operation
+constant arp_hw_type : std_logic_vector (15 downto 0) := x"0001";    -- code of ARP hardware type
+constant arp_protocol_type : std_logic_vector (15 downto 0) := x"0800"; -- code of protocol type (IP4)
+constant arp_hw_length : std_logic_vector (7 downto 0) := x"06"; 			-- code of ARP hardware length
+constant arp_protocol_length : std_logic_vector (7 downto 0) := x"04";  -- code of ARP protocol length
+constant arp : std_logic_vector (15 downto 0) := x"0806"; 					-- code of ARP protocol type
+constant ethernet : std_logic_vector (15 downto 0) := x"0800";				-- code of IP4 protocol type
+
+-- CRC checker declaration
+component crc32_parallel
+			 port (clk100mhz : in  STD_LOGIC;
+					 data_valid : in  STD_LOGIC;
+					 data_in : in  STD_LOGIC_VECTOR (1 downto 0);
+					 rstn : in STD_LOGIC;
+					 crc : inout  STD_LOGIC_VECTOR (31 downto 0));
+end component;
+
+begin
+-- CRC checker instantiation
+crc_calculator: crc32_parallel
+					 port map (clk100mhz => clk100mhz,
+								  data_valid => start_crc,
+								  data_in => txd,
+								  rstn => stop_crc,
+								  crc => crc_calculated);
+
+	transmit: process (clk50mhz_shift,rstn)
+	begin
+		if (rstn = '0') then -- if transciever is being reset transmitter becomes idle
+			id_counter <= (others => '0'); -- reset ID counter on hardware reset
+			state <= idle;
+		elsif (rising_edge(clk50mhz_shift)) then
+			case state is
+			
+			-- Idle state all Tx flags and registers reset and Tx waits until 
+			-- tx_ready signal is asserted 
+			when idle =>
+				bit_count <= 0;
+				byte_count <= 0;
+				tx_done <= '0';
+				start_crc <= '0';
+				stop_crc <= '1';
+				txen <= '0';
+				txd <= "00";
+				if (tx_ready = '0') then
+					txen <= '0';
+					rd_enable_ram <= '0';
+					rd_addr_ram <= (others => '0');
+					state <= idle;
+				elsif (tx_ready = '1') then -- if tx_ready flag is set start transmission
+					txen <= '1';
+					txd <= preamble(2*bit_count+1 downto 2*bit_count);
+					-- if IP/UDP protocol is to be transmitted pre-read the first data byte from RAM
+					if (eth_protocol = '1') then
+						rd_enable_ram <= '1'; -- enable read
+						rd_addr_ram <= std_logic_vector(to_unsigned(byte_count,ADDR_WIDTH)); -- set address of RAM register to read from
+					else -- if ARP protocol, there is no data to be transmtted 
+						rd_enable_ram <= '0';
+						rd_addr_ram <= (others => '0');
+					end if;
+					--
+					byte_count <= 0;
+					bit_count <= bit_count+1;
+					state <= tx_preamble;
+				end if;
+			
+			-- this state transmits preamble
+			when tx_preamble =>
+				txen <= '1';
+				-- if IP/UDP protocol is to be transmitted pre-read the first data byte from RAM
+				if (eth_protocol = '1') then
+					temp_data <= rd_data_ram; 		  -- read data byte from RAM
+					rd_enable_ram <= '0';           -- disable read operation from RAM
+					rd_addr_ram <= (others => '0'); -- clear address bus
+				else -- if ARP protocol, there is no data to be transmtted 
+					temp_data <= (others => '0');
+					rd_enable_ram <= '0';
+					rd_addr_ram <= (others => '0');
+				end if;
+				--
+				tx_done <= '0';
+				if (byte_count <= 6 and bit_count < 3) then
+					txd <= preamble(2*bit_count+1 downto 2*bit_count);
+					bit_count <= bit_count+1;
+					state <= tx_preamble;
+				elsif (byte_count <= 6 and bit_count = 3) then
+					txd <= preamble(2*bit_count+1 downto 2*bit_count);
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_preamble;
+				elsif (byte_count = 7) then
+						txd <= sfd(2*bit_count+1 downto 2*bit_count);
+						bit_count <= bit_count+1;
+						byte_count <= 0;
+						state <= tx_sfd;
+				end if;
+			
+			-- this state transmits SFD
+			when tx_sfd =>
+				txen <= '1';
+				tx_done <= '0';
+				-- if IP/UDP protocol is to be transmitted pre-read the first data byte from RAM
+				if (eth_protocol = '1') then
+					temp_data <= rd_data_ram;
+					rd_enable_ram <= '0';
+					rd_addr_ram <= (others => '0');
+				else -- if ARP protocol, there is no data to be transmtted 
+					temp_data <= (others => '0');
+					rd_enable_ram <= '0';
+					rd_addr_ram <= (others => '0');
+				end if;
+				--
+				if (byte_count = 0 and bit_count < 3) then
+					txd <= sfd(2*bit_count+1 downto 2*bit_count);
+					bit_count <= bit_count+1;
+					state <= tx_sfd;
+				elsif (byte_count = 0 and bit_count = 3) then
+					txd <= sfd(2*bit_count+1 downto 2*bit_count);
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_sfd;
+				elsif (byte_count = 1) then
+					byte_count <= 0;
+					txd <= dest_mac((5-0)*8+2*bit_count+1 downto (5-0)*8+2*bit_count);
+					bit_count <= bit_count+1;
+					start_crc <= '1';
+					stop_crc <= '0';
+					state <= tx_eth_frame_header;
+				end if;
+			
+			-- this state transmits Ethernet frame header (destination and source MAC addresses and upper layer protocol type)
+			when tx_eth_frame_header =>
+				txen <= '1';
+				tx_done <= '0';
+				-- if IP/UDP protocol is to be transmitted pre-read the first data byte from RAM
+				if (eth_protocol = '1') then
+					temp_data <= rd_data_ram;
+					rd_enable_ram <= '0';
+					rd_addr_ram <= (others => '0');
+				else -- if ARP protocol, there is no data to be transmtted 
+					temp_data <= (others => '0');
+					rd_enable_ram <= '0';
+					rd_addr_ram <= (others => '0');
+				end if;
+				-- destination MAC transmitted
+				if (byte_count <= 5 and bit_count < 3) then
+					txd <= dest_mac((5-byte_count)*8+2*bit_count+1 downto (5-byte_count)*8+2*bit_count);
+					bit_count <= bit_count+1;
+					state <= tx_eth_frame_header;
+				elsif (byte_count <= 5 and bit_count = 3) then
+					txd <= dest_mac((5-byte_count)*8+2*bit_count+1 downto (5-byte_count)*8+2*bit_count);
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_eth_frame_header;
+				-- source MAC transmitted
+				elsif (byte_count > 5 and byte_count <= 11 and bit_count < 3) then
+					txd <= fpga_mac((11-byte_count)*8+2*bit_count+1 downto (11-byte_count)*8+2*bit_count);
+					bit_count <= bit_count+1;
+					state <= tx_eth_frame_header;
+				elsif (byte_count > 5 and byte_count <= 11 and bit_count = 3) then
+					txd <= fpga_mac((11-byte_count)*8+2*bit_count+1 downto (11-byte_count)*8+2*bit_count);
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_eth_frame_header;
+				-- upper layer protocol type transmitted
+				elsif (byte_count > 11 and byte_count <= 13 and bit_count < 3) then
+					txd <= eth_type((13-byte_count)*8+2*bit_count+1 downto (13-byte_count)*8+2*bit_count);
+					bit_count <= bit_count+1;
+					state <= tx_eth_frame_header;
+				elsif (byte_count > 11 and byte_count <= 13 and bit_count = 3) then
+					txd <= eth_type((13-byte_count)*8+2*bit_count+1 downto (13-byte_count)*8+2*bit_count);
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_eth_frame_header;
+				elsif (byte_count = 14) then
+						txd <= byte0(2*bit_count+1 downto 2*bit_count);
+						bit_count <= bit_count+1;
+						byte_count <= 0;
+						state <= tx_protocol_header;
+				end if;
+			
+			-- this state transmits ARP or IP/UDP protocol headers
+			when tx_protocol_header =>
+				txen <= '1';
+				tx_done <= '0';
+				-- if IP/UDP protocol is to be transmitted pre-read the first data byte from RAM
+				if (eth_protocol = '1') then
+					temp_data <= rd_data_ram;
+					rd_enable_ram <= '0';
+					rd_addr_ram <= (others => '0');
+				else -- if ARP protocol, there is no data to be transmtted
+					temp_data <= (others => '0');
+					rd_enable_ram <= '0';
+					rd_addr_ram <= (others => '0');
+				end if;
+				--
+				if (byte_count <= 27 and bit_count < 3) then
+					bit_count <= bit_count+1;
+					state <= tx_protocol_header;
+				elsif (byte_count <= 27 and bit_count = 3) then
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_protocol_header;
+				elsif (byte_count = 28 and data_counter_max = 0) then -- if there is no data to transmit, transmit zero-padding
+						bit_count <= bit_count+1;
+						byte_count <= 0;
+						state <= tx_zero_padding;
+				elsif (byte_count = 28 and data_counter_max > 0) then -- if there is data to transmit, transmit data
+						byte_count <= 0;
+						bit_count <= bit_count+1;
+						state <= tx_data;
+				end if;
+				case byte_count is
+					when 0 => txd <= byte0(2*bit_count+1 downto 2*bit_count);
+					when 1 => txd <= byte1(2*bit_count+1 downto 2*bit_count);
+					when 2 => txd <= byte2(2*bit_count+1 downto 2*bit_count);
+					when 3 => txd <= byte3(2*bit_count+1 downto 2*bit_count);
+					when 4 => txd <= byte4(2*bit_count+1 downto 2*bit_count);
+					when 5 => txd <= byte5(2*bit_count+1 downto 2*bit_count);
+					when 6 => txd <= byte6(2*bit_count+1 downto 2*bit_count);
+					when 7 => txd <= byte7(2*bit_count+1 downto 2*bit_count);
+					when 8 => txd <= byte8(2*bit_count+1 downto 2*bit_count);
+					when 9 => txd <= byte9(2*bit_count+1 downto 2*bit_count);
+					when 10 => txd <= byte10(2*bit_count+1 downto 2*bit_count);
+					when 11 => txd <= byte11(2*bit_count+1 downto 2*bit_count);
+					when 12 => txd <= byte12(2*bit_count+1 downto 2*bit_count);
+					when 13 => txd <= byte13(2*bit_count+1 downto 2*bit_count);
+					when 14 => txd <= byte14(2*bit_count+1 downto 2*bit_count);
+					when 15 => txd <= byte15(2*bit_count+1 downto 2*bit_count);
+					when 16 => txd <= byte16(2*bit_count+1 downto 2*bit_count);
+					when 17 => txd <= byte17(2*bit_count+1 downto 2*bit_count);
+					when 18 => txd <= byte18(2*bit_count+1 downto 2*bit_count);
+					when 19 => txd <= byte19(2*bit_count+1 downto 2*bit_count);
+					when 20 => txd <= byte20(2*bit_count+1 downto 2*bit_count);
+					when 21 => txd <= byte21(2*bit_count+1 downto 2*bit_count);
+					when 22 => txd <= byte22(2*bit_count+1 downto 2*bit_count);
+					when 23 => txd <= byte23(2*bit_count+1 downto 2*bit_count);
+					when 24 => txd <= byte24(2*bit_count+1 downto 2*bit_count);
+					when 25 => txd <= byte25(2*bit_count+1 downto 2*bit_count);
+					when 26 => txd <= byte26(2*bit_count+1 downto 2*bit_count);
+					when 27 => txd <= byte27(2*bit_count+1 downto 2*bit_count);
+					when others => 
+						if (data_counter_max = 0) then
+							txd <= "00"; -- preload zeros to Tx bus for zero-padding transmission
+						elsif (data_counter_max > 0) then
+							txd <= temp_data(2*bit_count+1 downto 2*bit_count); -- preload data to Tx bus for data transmission
+						end if;
+				end case;
+			
+			-- this state transmits data
+			when tx_data =>
+				txen <= '1';
+				tx_done <= '0';
+				if (byte_count <= data_counter_max-1 and bit_count < 3) then
+					txd <= temp_data(2*bit_count+1 downto 2*bit_count);
+					bit_count <= bit_count+1;
+					-- keep read RAM enabled and have the address to read on the bus
+					rd_enable_ram <= '1';
+					rd_addr_ram <= std_logic_vector(to_unsigned(byte_count+1,ADDR_WIDTH));
+					--
+					state <= tx_data;
+				elsif (byte_count <= data_counter_max-1 and bit_count = 3) then
+					txd <= temp_data(2*bit_count+1 downto 2*bit_count);
+					-- read the next data byte from RAM when the previous is transmitted
+					temp_data <= rd_data_ram;
+					rd_enable_ram <= '1';
+					--
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_data;
+				elsif (byte_count > data_counter_max-1 and zero_counter = 0) then -- if no zero-padding required
+					txd(0) <= crc_calculated((3-0)*8+(3-bit_count)*2+1); -- preload crc values on Tx bus
+					txd(1) <= crc_calculated((3-0)*8+(3-bit_count)*2);   -- and start crc transmission
+					-- when all the data was transmitted disable read from RAM operation and clear the RAM signals
+					temp_data <= (others => '0');
+					rd_enable_ram <= '0';
+					rd_addr_ram <= (others => '0');
+					--
+					start_crc <= '0'; -- stop crc calculation 
+					stop_crc <= '0';
+					bit_count <= bit_count+1;
+					byte_count <= 0;
+					state <= tx_crc;
+				elsif (byte_count > data_counter_max-1 and zero_counter > 0) then -- if zero-padding required
+					txd <= "00"; -- preload zeros to Tx bus
+					-- disable read from RAM operation and clear the RAM signals
+					temp_data <= (others => '0');
+					rd_enable_ram <= '0';
+					rd_addr_ram <= (others => '0');
+					--
+					byte_count <= 0;
+					bit_count <= bit_count+1;
+					state <= tx_zero_padding;
+				end if;
+			
+			-- this state transmits zero-padded data field
+			when tx_zero_padding =>
+				txen <= '1';
+				tx_done <= '0';
+				if (byte_count <= zero_counter-1 and bit_count < 3) then
+					txd <= "00";
+					bit_count <= bit_count+1;
+					state <= tx_zero_padding;
+				elsif (byte_count <= zero_counter-1 and bit_count = 3) then
+					txd <= "00";
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_zero_padding;
+				elsif (byte_count+1 > zero_counter-1) then -- when required amount of zero-padding was transmitted
+					txd(0) <= crc_calculated((3-0)*8+(3-bit_count)*2+1); -- preload crc values on Tx bus
+					txd(1) <= crc_calculated((3-0)*8+(3-bit_count)*2);   -- and start crc transmission
+					byte_count <= 0;
+					bit_count <= bit_count+1;
+					start_crc <= '0'; -- stop crc calculation
+					stop_crc <= '0';
+					state <= tx_crc;
+				end if;
+			
+			-- this state transmits calculated crc value
+			when tx_crc =>
+				txen <= '1';
+				tx_done <= '0';
+				if (byte_count <= 3 and bit_count < 3) then
+					txd(0) <= crc_calculated((3-byte_count)*8+(3-bit_count)*2+1);
+					txd(1) <= crc_calculated((3-byte_count)*8+(3-bit_count)*2);
+					bit_count <= bit_count+1;
+					state <= tx_crc;
+				elsif (byte_count <= 3 and bit_count = 3) then
+					txd(0) <= crc_calculated((3-byte_count)*8+(3-bit_count)*2+1);
+					txd(1) <= crc_calculated((3-byte_count)*8+(3-bit_count)*2);
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_crc;
+				elsif (byte_count > 3) then
+					byte_count <= 0;
+					tx_done <= '1'; -- if crc was transmitted - this is the end of the packet, go back to idle state
+					txen <= '0';
+					txd <= "00";
+					-- make sure that no overflow of the ID parameter happens
+					if (eth_protocol = '1' and id_counter+1 <= 65536) then
+						id_counter <= id_counter+1;
+					elsif (eth_protocol = '1' and id_counter+1 > 65536) then
+						id_counter <= (others => '0');
+					else 
+						id_counter <= id_counter;
+					end if;
+					state <= idle;
+				end if;
+			
+			
+			end case;
+		end if;
+	end process transmit;
+	
+	-- this process receives data from Rx module and determines protocol type of the next packet to be transmitted
+	set_tx_format: process (send_arp_reply,send_ethernet_protocol,data_in_valid,pc_mac,pc_ip,pc_port,tx_done,clk50mhz_shift,datacm,udpc)
+	begin
+		if (falling_edge(clk50mhz_shift)) then
+			-- set registers when there is valid data from Receiver
+			if (data_in_valid = '1' and tx_done = '0') then
+				if (send_arp_reply = '1') then
+					arp_reply <= '1';
+				elsif (send_ethernet_protocol = '1') then
+					eth_protocol <= '1';
+				end if;
+				dest_mac <= pc_mac;
+				dest_ip <= pc_ip;
+				dest_port <= pc_port;
+				data_counter_max <= to_integer(unsigned(datacm));
+				ip_total_length <= std_logic_vector(ipl+unsigned(udpl));
+				udp_length <= udpl;
+				udp_checksum <= udpc;
+			-- keep value of these registers until packet is transmitted 
+			elsif (data_in_valid = '0' and tx_done = '0') then
+				arp_reply <= arp_reply;
+				eth_protocol <= eth_protocol;
+				dest_mac <= dest_mac;
+				dest_ip <= dest_ip;
+				dest_port <= dest_port;
+				data_counter_max <= data_counter_max;
+				ip_total_length <= ip_total_length;
+				udp_length <= udp_length;
+				udp_checksum <= udp_checksum;
+			-- when the packet is transmitted, clear registers
+			elsif (tx_done = '1') then
+				arp_reply <= '0';
+				eth_protocol <= '0';
+				dest_mac <= (others => '0');
+				dest_ip <= (others => '0');
+				dest_port <= (others => '0');
+				data_counter_max <= 0;
+				ip_total_length <= (others => '0');
+				udp_length <= (others => '0');
+				udp_checksum <= (others => '0');
+			end if;
+		end if;
+	end process set_tx_format;
+	
+	-- this process assembles headers of the data packet to be transmitted
+	set_tx_data: process (arp_reply,eth_protocol,tx_done,clk50mhz_shift,ip_header_checksum)
+	begin
+		if (falling_edge(clk50mhz_shift)) then
+			-- if ARP reply required load headers registers and set data and zero counters accordingly
+			if (arp_reply = '1' and tx_done = '0') then
+				eth_type <= arp;
+				byte0 <= arp_hw_type(15 downto 8);
+				byte1 <= arp_hw_type(7 downto 0);
+				byte2 <= arp_protocol_type(15 downto 8);
+				byte3 <= arp_protocol_type(7 downto 0);
+				byte4 <= arp_hw_length;
+				byte5 <= arp_protocol_length;
+				byte6 <= arp_operation(15 downto 8);
+				byte7 <= arp_operation(7 downto 0);
+				byte8 <= fpga_mac(47 downto 40);
+				byte9 <= fpga_mac(39 downto 32);
+				byte10 <= fpga_mac(31 downto 24);
+				byte11 <= fpga_mac(23 downto 16);
+				byte12 <= fpga_mac(15 downto 8);
+				byte13 <= fpga_mac(7 downto 0);
+				byte14 <= fpga_ip(31 downto 24);
+				byte15 <= fpga_ip(23 downto 16);
+				byte16 <= fpga_ip(15 downto 8);
+				byte17 <= fpga_ip(7 downto 0);
+				byte18 <= dest_mac(47 downto 40);
+				byte19 <= dest_mac(39 downto 32);
+				byte20 <= dest_mac(31 downto 24);
+				byte21 <= dest_mac(23 downto 16);
+				byte22 <= dest_mac(15 downto 8);
+				byte23 <= dest_mac(7 downto 0);
+				byte24 <= dest_ip(31 downto 24);
+				byte25 <= dest_ip(23 downto 16);
+				byte26 <= dest_ip(15 downto 8);
+				byte27 <= dest_ip(7 downto 0);
+				--data_counter_max <= 0; -- arp request has 18 bytes of zero padding
+				zero_counter <= 18;
+				tx_ready <= '1';-- set flag indicating start of transmission
+			-- if IP/UDP reply required load headers registers and set data and zero counters accordingly
+			elsif (eth_protocol = '1' and tx_done = '0') then
+				eth_type <= ethernet;
+				byte0 <= ip_version&ip_header_length;
+				byte1 <= ds; -- differentiated services
+				-- total length of protocol in bytes
+				byte2 <= ip_total_length(15 downto 8);
+				byte3 <= ip_total_length(7 downto 0);
+				-- identification: number of package
+				byte4 <= std_logic_vector(id_counter(15 downto 8));
+				byte5 <= std_logic_vector(id_counter(7 downto 0));
+				byte6 <= flags_offset(15 downto 8); -- flags and 5 seniour bits from fragmentation offset
+				byte7 <= flags_offset(7 downto 0); -- 8 juniour bits from fragmentation offset
+				byte8 <= ttl; -- Time To Live
+				byte9 <= ip_protocol; -- x"11" - for UDP
+				-- header checksum (from process )
+				byte10 <= ip_header_checksum(15 downto 8);
+				byte11 <= ip_header_checksum(7 downto 0);
+				-- source ip
+				byte12 <= fpga_ip(31 downto 24);
+				byte13 <= fpga_ip(23 downto 16);
+				byte14 <= fpga_ip(15 downto 8);
+				byte15 <= fpga_ip(7 downto 0);
+				-- destination ip
+				byte16 <= dest_ip(31 downto 24);
+				byte17 <= dest_ip(23 downto 16);
+				byte18 <= dest_ip(15 downto 8);
+				byte19 <= dest_ip(7 downto 0);
+				-- source port
+				byte20 <= fpga_port(15 downto 8);
+				byte21 <= fpga_port(7 downto 0);
+				-- destination port
+				byte22 <= dest_port(15 downto 8);
+				byte23 <= dest_port(7 downto 0);
+				-- udp length
+				byte24 <= udp_length(15 downto 8);
+				byte25 <= udp_length(7 downto 0);
+				-- udp_checksum
+				byte26 <= udp_checksum(15 downto 8);
+				byte27 <= udp_checksum(7 downto 0);
+				-- counters and flags
+				--data_counter_max <= to_integer(unsigned(datacm));
+				if (data_counter_max < 18) then -- 4<=18 - true
+					zero_counter <= 18-data_counter_max; -- 18-4-1=13 (from 0 to 13) = 14 bytes of zeros
+				else
+					zero_counter <= 0;-- if data_counter_max=20 -> data_counter=19 (from 0 to 19) = 20 bytes of data
+				end if;
+				tx_ready <= '1'; -- set flag indicating start of transmission
+			else -- if there is nothing to transmit keep all registers and counters clear
+				tx_ready <= '0';
+				eth_type <= (others => '0');
+				byte0 <= (others => '0');
+				byte1 <= (others => '0');
+				byte2 <= (others => '0');
+				byte3 <= (others => '0');
+				byte4 <= (others => '0');
+				byte5 <= (others => '0');
+				byte6 <= (others => '0');
+				byte7 <= (others => '0');
+				byte8 <= (others => '0');
+				byte9 <= (others => '0');
+				byte10 <= (others => '0');
+				byte11 <= (others => '0');
+				byte12 <= (others => '0');
+				byte13 <= (others => '0');
+				byte14 <= (others => '0');
+				byte15 <= (others => '0');
+				byte16 <= (others => '0');
+				byte17 <= (others => '0');
+				byte18 <= (others => '0');
+				byte19 <= (others => '0');
+				byte20 <= (others => '0');
+				byte21 <= (others => '0');
+				byte22 <= (others => '0');
+				byte23 <= (others => '0');
+				byte24 <= (others => '0');
+				byte25 <= (others => '0');
+				byte26 <= (others => '0');
+				byte27 <= (others => '0');
+				--data_counter_max <= 0;
+				zero_counter <= 0;
+			end if;
+		end if;
+	end process set_tx_data;
+	
+	-- this process calculates IP header checksum
+	ip_header_checksum_calc: process (clk50mhz_shift,tx_ready,id_counter,dest_ip)
+	begin
+		if (falling_edge(clk50mhz_shift)) then
+			-- only for IP/UDP packets
+			if (eth_protocol = '1' and tx_ready = '1') then
+				-- if checksum hasn't been calculated yet, calculate it
+				if (ip_header_calc_done = '0') then
+					case s is
+						when s1 =>
+							temp_iphc1 <= temp_iphc1+unsigned(ip_version&ip_header_length&ds)+unsigned(ip_total_length)+id_counter+
+							unsigned(flags_offset)+unsigned(ttl&ip_protocol)+unsigned(fpga_ip(31 downto 16))+
+							unsigned(fpga_ip(15 downto 0))+unsigned(dest_ip(31 downto 16))+unsigned(dest_ip(15 downto 0)); -- sum of all header fields
+							s <= s2;
+						when s2 =>
+							temp_iphc2 <= not(temp_iphc2+temp_iphc1(15 downto 0)+temp_iphc1(23 downto 16)); -- sum of the main checksum body with carry-out
+							s <= s3;
+						when s3 =>
+							ip_header_checksum <= std_logic_vector(temp_iphc2); -- calculated checksum
+							ip_header_calc_done <= '1';                         -- checksum calculation done
+							s <= s3;
+					end case;
+				else -- if checksum hasn been calculated, keep it
+					temp_iphc1 <= temp_iphc1;
+					temp_iphc2 <= temp_iphc2;
+					ip_header_checksum <= ip_header_checksum;
+					ip_header_calc_done <= ip_header_calc_done;
+				end if;
+			else -- keep checksum registers clear when they are not used
+				temp_iphc1 <= (others => '0');
+				temp_iphc2 <= (others => '0');
+				ip_header_checksum <= (others => '0');
+				ip_header_calc_done <= '0';
+				s <= s1;
+			end if;
+		end if;
+	end process ip_header_checksum_calc;
+	
+end Behavioral;
+

ip_repo_sources/UDP-server/src/ethernet_transceiver.vhd

@@ -0,0 +1,508 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov
+-- 
+-- Create Date:    16:19:30 02/20/2017 
+-- Design Name: 
+-- Module Name:    ethernet_transceiver - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+
+-- UDP echo-server design uses on-board Ethernet port to create a data-link between FPGA board
+-- Nexys 4 DDR and MatLAB. Echo-server is capable of reception and transmission data packets
+-- using ARP and UDP protocols.
+-- MAC address of FPGA board: 00:18:3e:01:ff:71
+-- IP4 address of FPGA board: 192.168.1.10
+-- Port number used in the design: 58210
+-- The echo server will reply back to any data server, which uses correct IP4 address and Port number.
+-- MAC address of the board is made discoverable for the data server via ARP protocol
+-- This Echo-server design doesn't use any input or output FIFO's as elesticity buffers,
+-- both in- and outgoing data packets are parsed/assembled in parallel with Rx/Tx processes,
+-- which allows better resource utilisation at the price of more complex design architecture. 
+
+-- Additional Comments: 
+-- Transceiver block is the Top-level block of the Ethernet transceiver design, implementing 
+-- the VHDL UDP echo-server.
+-- Transceiver block itself handles the Power-On Reset operation along with subsequent Hardware Resets
+-- on request from the user.
+-- Apart from that it incorporates lower-level modules handling different functions required for the echo-server
+-- operations: Receiver, Transmitter, Serial Management Interface, Memory and Clock Modules
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity ethernet_transceiver2 is
+	 Generic (M_clk2_5mhz1: integer := 20; -- divisor for 2.5MHz clock
+				 M_clk2_5mhz2: integer := 10; -- divisor for shifted 2.5MHz clock 
+				 N : integer := 22;           -- divisor for debouncing circuit 
+				 ADDR_WIDTH : integer := 10;  -- RAM's address width
+				 DATA_WIDTH : integer := 8);  -- RAM's data width (1024x1byte)
+    Port ( clk100mhz : in  STD_LOGIC;
+           eth_rxd : inout  STD_LOGIC_VECTOR (1 downto 0);
+           eth_txd : inout  STD_LOGIC_VECTOR (1 downto 0);
+           eth_crsdv : inout  STD_LOGIC;
+			  eth_txen : inout  STD_LOGIC;
+           eth_rxerr : inout  STD_LOGIC;
+			  eth_mdc : out  STD_LOGIC;
+           eth_mdio : inout  STD_LOGIC;
+           eth_refclk : out  STD_LOGIC;
+           eth_rstn : inout  STD_LOGIC;
+			  -- display signals for ARP and UDP packets
+			  led16_b : out  STD_LOGIC;
+			  led16_g : out  STD_LOGIC;
+			  led16_r : out  STD_LOGIC;
+			  led17_b : out  STD_LOGIC;
+			  led17_g : out  STD_LOGIC;
+			  led17_r : out  STD_LOGIC;
+			  -- outputs for debugging
+--			  mode0 : out std_logic;
+--			  mode1 : out std_logic;
+--			  mode2 : out std_logic;
+--			  refclk : out std_logic;
+--			  rxerr : out std_logic;
+--			  txd : out  STD_LOGIC_VECTOR (1 downto 0);
+--			  txen : out  STD_LOGIC;
+			  -- Reset and SMI inputs/outputs
+			  btn_reset : in std_logic;
+			  led : out std_logic_vector (15 downto 0);
+			  sw : in std_logic_vector (4 downto 0);
+			  
+			  fifoWriteEnable : out std_logic;
+			  fifoWriteData   : out std_logic_vector(31 downto 0);
+			  fifoWriteAlmostFull  : in std_logic;
+			  fifoWriteFull  : in std_logic;
+			  
+			  fifoReadEnable : out std_logic;
+			  fifoReadData   : in std_logic_vector(DATA_WIDTH-1 downto 0);
+			  fifoReadAlmostEmpty  : in std_logic;
+			  fifoReadEmpty  : in std_logic;
+			  sendPacketLength : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- length of IP datagram data field in bytes
+			  sendPacketChecksum : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0') -- UDP checksum
+			  );
+end ethernet_transceiver2;
+
+architecture Behavioral of ethernet_transceiver2 is
+-- CLOCKS
+	-- main clock
+signal b_clk100mhz : std_logic;
+signal clk50mhz : std_logic; 		  -- inner signal for ETH_REFCLK (read Rx on falling edge)
+signal b_clk50mhz : std_logic; 		  -- inner signal for ETH_REFCLK (read Rx on falling edge)
+signal clk50mhz_shift : std_logic; -- shifted 50mhz clock signal for write Tx operation
+signal b_clk50mhz_shift : std_logic; -- shifted 50mhz clock signal for write Tx operation
+	-- mdio clock
+signal clk2_5mhz : std_logic;       -- MDC clock
+signal b_clk2_5mhz : std_logic;       -- MDC clock
+signal clk2_5mhz_shift : std_logic; -- shifted mdio clock for read and write MDIO
+signal b_clk2_5mhz_shift : std_logic; -- shifted mdio clock for read and write MDIO
+
+-- SIGNALS
+-- ******* process transceiver (only responsible for Hardware Reset) ********--
+type state_type is (idle, power_on, reset);
+signal state : state_type := idle;
+constant MODE : std_logic_vector (2 downto 0) := "111"; -- all capable; auto-negotiation enabled
+constant PHYAD : std_logic := '1'; 							  -- physical address of the transciever
+signal rstn_counter : integer range 0 to 5010 := 0;     -- count 100us+220ns (5000+11 50mhz clock cycles)
+signal po_counter : integer range 0 to 2499999:= 0;     -- count 50ms - power supply turn on time (2,500,000 50mhz clock cycles)
+signal hw_reset : std_logic;         -- button attached to this signal via debouncing circuit: hardware reset
+signal init_proc : std_logic := '0'; -- flag indicating wether power-on reset was done or not
+
+-- ******** Ethernet Signals ********--
+--*^*^*^*^*^*^* PC's and FPGA's MAC, IP4 addresses and Port numbers *^*^*^*^*^*^*--
+signal pc_mac : std_logic_vector (47 downto 0); -- PC's MAC address (configured on PC's side)
+signal pc_ip : std_logic_vector (31 downto 0);  -- PC's IP4 address (configured on PC's side)
+signal pc_port : std_logic_vector (15 downto 0);-- PC's port (configured on PC's side)
+constant fpga_mac : std_logic_vector (47 downto 0) := x"00183e01ff71";-- FPGA's MAC address
+constant fpga_ip : std_logic_vector (31 downto 0) := x"C0A8010A";     -- FPGA's IP4 address 192.168.1.10
+constant fpga_port : std_logic_vector (15 downto 0) := x"E362";       -- FPGA's port 58210
+-- data transfer between Rx and Tx
+signal send_arp_reply : std_logic := '0';        -- ARP protocol flag
+signal send_ethernet_protocol : std_logic := '0';-- Ethernet protocol flag
+signal data_out_valid : std_logic := '0';        -- data valid flag
+signal datacm : STD_LOGIC_VECTOR (ADDR_WIDTH downto 0) := (others => '0'); -- length of data in UDP datagram
+signal udpl : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- length of IP datagram data field in bytes
+signal udpc : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- UDP checksum
+-- data to and from RAM
+signal rx_data : std_logic_vector (DATA_WIDTH-1 downto 0) := (others => '0'); -- data from Rx to RAM
+signal fifo_data : std_logic_vector (31 downto 0) := (others => '0'); -- data from RAM to Tx
+signal wrt_addr_ram : std_logic_vector (ADDR_WIDTH-1 downto 0) := (others => '0'); -- address to write data to RAM
+signal rd_addr_ram  : std_logic_vector (ADDR_WIDTH-1 downto 0) := (others => '0');  -- address to read data from RAM
+
+signal we_ram  : std_logic := '0'; -- enable write RAM operation  
+signal re_ram  : std_logic := '0'; -- enable read RAM operation 
+ 
+signal data_counter : integer range 0 to 1472 := 0; -- index of data field in bytes without zero padding
+signal data_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- length of IP datagram data field in bytes
+
+-- data to rx
+signal tx_data : std_logic_vector (DATA_WIDTH-1 downto 0) := (others => '0'); -- data from RAM to Tx
+signal rd_addr_send : std_logic_vector (ADDR_WIDTH-1 downto 0) := (others => '0');  -- address to read data from RAM
+signal re_send : std_logic := '0'; -- enable read RAM operation
+signal sendPacketStart : std_logic := '0';
+
+--signal refclk: std_logic;
+
+-- ******** COMPONENTS DECLARATION ********--
+component debounce_switch -- for Hardware Reset switch debouncing
+		    generic (N : integer);
+			 port (clk100mhz : in std_logic;
+					 btn : in std_logic;
+					 db_sw : out std_logic);
+end component;
+
+component clock_mod -- RMII clocks
+			 --generic (M_clk : integer);
+			 port (clk100mhz : in std_logic;
+					 clk_out : out std_logic;
+					 clk_out_shift : out std_logic);
+end component;
+
+component clock_mod2 -- MDC clocks
+			 generic (M_clk1 : integer;
+						 M_clk2 : integer);
+			 port (clk100mhz : in std_logic;
+					 clk_out1 : out std_logic; 
+					 clk_out2 : out std_logic);
+end component;
+
+component md_interface -- MDIO interface
+			 port (mdc_shift : in STD_LOGIC;
+					 mdio : inout  STD_LOGIC;
+					 eth_rstn : in  STD_LOGIC;
+					 led : out  STD_LOGIC_VECTOR (15 downto 0);
+					 sw : in  STD_LOGIC_VECTOR (4 downto 0));
+end component;
+
+component eth_receiver -- RMII Rx Interface
+			 Generic (ADDR_WIDTH : integer;
+						 DATA_WIDTH : integer);
+			 port (clk100mhz : in STD_LOGIC;
+					 clk50mhz : in  STD_LOGIC;
+					 rxd : in  STD_LOGIC_VECTOR (1 downto 0);
+					 crsdv : in  STD_LOGIC;
+					 rstn : in  STD_LOGIC;
+					 rxerr : in STD_LOGIC;
+					 -- RAM signals
+					 wrt_data_ram : inout STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
+					 wrt_addr_ram : inout STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
+					 wrt_enable_ram : out STD_LOGIC;
+					 -- Addresses 
+					 fpga_mac : in STD_LOGIC_VECTOR (47 downto 0);
+					 fpga_ip : in STD_LOGIC_VECTOR (31 downto 0);
+					 fpga_port : in STD_LOGIC_VECTOR (15 downto 0);
+					 pc_mac : out STD_LOGIC_VECTOR (47 downto 0);
+				 	 pc_ip : out  STD_LOGIC_VECTOR (31 downto 0);
+					 pc_port : out STD_LOGIC_VECTOR (15 downto 0);
+					 -- Data to Tx
+					 datacm : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0);
+					 udpl : out STD_LOGIC_VECTOR (15 downto 0);
+					 udpc : out STD_LOGIC_VECTOR (15 downto 0);
+					 send_arp_reply : out STD_LOGIC;
+					 send_ethernet_protocol: out STD_LOGIC;
+					 data_out_valid : out STD_LOGIC);
+end component;
+
+component eth_transmitter -- RMII Tx Interface
+			 Generic (ADDR_WIDTH : integer;
+				       DATA_WIDTH : integer);
+			 port (clk100mhz : in  STD_LOGIC;
+					 clk50mhz_shift : in STD_LOGIC;
+					 rstn : in STD_LOGIC;
+					 txd : inout  STD_LOGIC_VECTOR (1 downto 0);
+					 txen : out  STD_LOGIC;
+				    -- Data from RAM
+					 rd_data_ram : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
+					 rd_addr_ram : out STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
+					 rd_enable_ram : out STD_LOGIC;
+					 -- Addresses
+				    fpga_mac : in STD_LOGIC_VECTOR (47 downto 0);
+				    fpga_ip : in STD_LOGIC_VECTOR (31 downto 0);
+				    fpga_port : in STD_LOGIC_VECTOR (15 downto 0);
+				    pc_mac : in STD_LOGIC_VECTOR (47 downto 0);
+				    pc_ip : in  STD_LOGIC_VECTOR (31 downto 0);
+				    pc_port : in STD_LOGIC_VECTOR (15 downto 0);
+				    -- Data from Rx
+					 datacm : in STD_LOGIC_VECTOR (ADDR_WIDTH downto 0);
+					 udpl : in STD_LOGIC_VECTOR (15 downto 0);
+					 udpc : in STD_LOGIC_VECTOR (15 downto 0);
+				    send_arp_reply : in STD_LOGIC;
+				    send_ethernet_protocol: in STD_LOGIC;
+				    data_in_valid : in STD_LOGIC);
+end component;
+
+component single_port_RAM -- RAM block to store data from Ethernet packets
+			 generic (ADDR_WIDTH : integer;
+						 DATA_WIDTH : integer);
+			 port (clk50mhz : in  STD_LOGIC;
+					 we : in  STD_LOGIC;
+					 re : in STD_LOGIC;
+					 addr_r : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
+					 addr_w : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
+					 din : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
+					 dout : out  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0));
+end component;
+
+component led1 -- Display module for incoming ARP and UDP packets
+			 Port ( clk50mhz : in  STD_LOGIC;
+					  rstn : in STD_LOGIC;
+					  dv_arp : in  STD_LOGIC;
+					  dv_eth : in  STD_LOGIC;
+					  led16_b : out  STD_LOGIC;
+					  led16_g : out  STD_LOGIC;
+					  led16_r : out  STD_LOGIC;
+					  led17_b : out  STD_LOGIC;
+					  led17_g : out  STD_LOGIC;
+					  led17_r : out  STD_LOGIC);
+end component;
+
+begin
+
+-- ******** COMPONENTS INSTANTIATION ********--
+-- clock buffers
+	U1: BUFG port map (I=>clk100mhz,O=>b_clk100mhz);
+	U2: BUFG port map (I=> clk2_5mhz, O=>b_clk2_5mhz);
+	U3: BUFG port map (I=>clk2_5mhz_shift,O=>b_clk2_5mhz_shift);
+	U4: BUFG port map (I=> clk50mhz,O=>b_clk50mhz);
+	U5: BUFG port map (I=> clk50mhz_shift,O=>b_clk50mhz_shift);
+--	pull-ups on multiplexed MODE pins
+	PULLUP_MODE0: PULLUP PORT MAP (O => eth_rxd(0));
+	PULLUP_MODE1: PULLUP PORT MAP (O => eth_rxd(1));
+	PULLUP_MODE2: PULLUP PORT MAP (O => eth_crsdv);
+-- pull-up on multiplexed PHYAD pin
+	PULLUP_PHYAD0: PULLUP PORT MAP (O => eth_rxerr);
+	
+-- pull-up on I2C MDIO pin is implemented in md_interface module
+
+-- MDIO interface
+	MDIO_Interface: md_interface
+						 port map (mdc_shift => b_clk2_5mhz_shift,--clk2_5mhz_shift,
+									  mdio => eth_mdio,
+									  eth_rstn => eth_rstn,
+									  led => led,
+									  sw => sw);
+									  
+--Ethernet receiver
+	Ethernet_receiver: eth_receiver
+							 generic map (ADDR_WIDTH => ADDR_WIDTH,
+											  DATA_WIDTH => DATA_WIDTH)
+						    port map (clk100mhz => b_clk100mhz,
+										  clk50mhz => b_clk50mhz,
+										  rxd => eth_rxd,
+										  crsdv => eth_crsdv,
+										  rstn => eth_rstn,
+										  rxerr => eth_rxerr,
+										  ---
+										  wrt_data_ram => rx_data,
+										  wrt_addr_ram => wrt_addr_ram,
+										  wrt_enable_ram => we_ram,
+										  ---
+										  fpga_mac => fpga_mac,
+										  fpga_ip => fpga_ip,
+										  fpga_port => fpga_port,
+										  pc_mac => pc_mac,
+										  pc_ip => pc_ip,
+										  pc_port => pc_port,
+										  ---
+										  datacm => datacm,
+										  udpl => udpl,
+										  udpc => udpc,
+										  send_arp_reply => send_arp_reply,
+										  send_ethernet_protocol => send_ethernet_protocol,
+										  data_out_valid => data_out_valid);
+
+--Ethernet transmitter
+	Ethernet_transmitter: eth_transmitter
+								 generic map (ADDR_WIDTH => ADDR_WIDTH,
+												  DATA_WIDTH => DATA_WIDTH)
+								 port map (clk100mhz => b_clk100mhz,
+											  clk50mhz_shift => b_clk50mhz_shift,
+											  rstn => eth_rstn,
+											  txd => eth_txd,
+											  txen => eth_txen,
+											  ---
+											  rd_data_ram => fifoReadData,
+											  rd_addr_ram => rd_addr_send,
+											  rd_enable_ram => fifoReadEnable,
+											  ---
+											  fpga_mac => fpga_mac,
+											  fpga_ip => fpga_ip,
+											  fpga_port => fpga_port,
+											  pc_mac => pc_mac,
+											  pc_ip => pc_ip,
+											  pc_port => pc_port,
+											  ---
+											  datacm => datacm,
+											  udpl => sendPacketLength,
+											  udpc => sendPacketChecksum,
+											  send_arp_reply => send_arp_reply,
+											  send_ethernet_protocol => sendPacketStart,
+											  data_in_valid => data_out_valid);
+
+-- Block RAM
+	RAM1: single_port_RAM
+			generic map (ADDR_WIDTH => ADDR_WIDTH,
+							 DATA_WIDTH => DATA_WIDTH)
+			port map (clk50mhz => b_clk50mhz,
+						 we => we_ram,
+						 re => re_ram,
+						 addr_w => wrt_addr_ram,
+						 addr_r => rd_addr_ram,
+						 din => rx_data,
+						 dout => tx_data);
+
+-- ARP and UDP LED's
+LED_count : led1 -- Display module for incoming ARP and UDP packets
+			 port map (clk50mhz => b_clk50mhz,
+						  rstn => eth_rstn,
+						  dv_arp => send_arp_reply,
+						  dv_eth => send_ethernet_protocol,
+						  led16_b => led16_b,
+						  led16_g => led16_g,
+						  led16_r => led16_r,
+						  led17_b => led17_b,
+						  led17_g => led17_g,
+						  led17_r => led17_r);
+
+-- Debouncing circuit
+	Switch: debounce_switch
+			  generic map (N => N)
+			  port map (clk100mhz => b_clk100mhz,
+							btn => btn_reset,
+							db_sw => hw_reset);
+
+-- RMII clocks	
+	CLOCK_50MHz: clock_mod
+					 --generic map (M_clk => M_clk50mhz)
+					 port map (clk100mhz => b_clk100mhz,
+								  clk_out => clk50mhz,
+								  clk_out_shift => clk50mhz_shift); 
+-- MDIO clocks
+	CLOCK_2_5MHz: clock_mod2
+					  generic map (M_clk1 => M_clk2_5mhz1,
+										M_clk2 => M_clk2_5mhz2)
+					  port map (clk100mhz => b_clk100mhz,
+								   clk_out1 => clk2_5mhz,
+									clk_out2 => clk2_5mhz_shift);
+	
+	transceiver: process (b_clk50mhz, hw_reset)
+	begin
+		if (hw_reset = '0') then
+			eth_rstn <= '0';
+			--MODE <= "111"; -- configure MODES here (if MODE is other than 1's)
+			--PHYAD <= '1';  -- configure PHYAD here (if PHYAD is other than 1's)
+			rstn_counter <= 0;
+			state <= reset;
+		elsif (rising_edge(b_clk50mhz)) then
+			case state is
+			
+			when idle =>
+				if (init_proc = '0') then -- if Power-ON Reset (POR) hasn't been completed
+					eth_rstn <= '1';
+					--MODE <= "111"; -- configure MODES here (if MODES is other than 1's)
+					--PHYAD <= '1';  -- configure PHYAD here (if PHYAD is other than 1's)
+					state <= power_on;
+				else	
+					eth_rstn <= '1';
+					--MODE <= "111"; -- release (set to 1's) MODES here (if configure them)
+					--PHYAD <= '1';  -- release (set to 1) PHYAD here (if configure it)
+					state <= idle;
+				end if;
+			
+			when power_on => -- wait for 50 ms before POR
+				--MODE <= "111"; -- configure MODES here (if MODES is other than 1's)
+				--PHYAD <= '1';  -- configure PHYAD here (if PHYAD is other than 1's)
+				if (po_counter < 2499999) then  
+					eth_rstn <= '1';
+					po_counter <= po_counter+1;
+					state <= power_on;
+				elsif (po_counter = 2499999) then
+					eth_rstn <= '0';
+					init_proc <= '1';
+					po_counter <= 0;
+					state <= reset;
+				end if;
+			
+			when reset => -- POR
+				if (rstn_counter <= 4999) then -- 100 us before releasing eth_rstn
+					--MODE <= "111"; -- configure MODES here (if MODES is other than 1's)
+					--PHYAD <= '1';  -- configure PHYAD here (if PHYAD is other than 1's)
+					rstn_counter <= rstn_counter+1;
+					eth_rstn <= '0';
+					state <= reset;
+				elsif (rstn_counter > 4999 and rstn_counter <= 5009) then -- 220 ns hold on time after releasing eth_rstn
+					--MODE <= "111"; -- configure MODES here (if MODES is other than 1's)
+					--PHYAD <= '1';  -- configure PHYAD here (if PHYAD is other than 1's)
+					rstn_counter <= rstn_counter+1;
+					eth_rstn <= '1';
+					state <= reset;
+				elsif (rstn_counter = 5010) then -- POR done, go back to idle state
+					--MODE <= "111"; -- release (set to 1's) MODES here (if configure them)
+					--PHYAD <= '1';  -- release (set to 1) PHYAD here (if configure it)
+					rstn_counter <= 0;
+					eth_rstn <= '1';
+					state <= idle;
+				end if;
+					
+			end case;
+		end if;
+	end process transceiver;
+
+    fifo_write : process(clk100mhz)
+    
+    begin
+        if(hw_reset = '0') then
+            data_counter <= 0;
+        elsif(rising_edge(clk100mhz)) then
+            fifoWriteEnable <= '0';
+            if(send_ethernet_protocol = '1') then
+                data_counter <= 0;
+                data_length <= udpl;
+                fifo_data <= (others=>'0');
+            elsif(unsigned(data_length) < 1471 and data_counter < unsigned(data_length)) then
+                fifo_data <= rx_data & fifo_data(31 downto DATA_WIDTH);
+                if(data_counter /= 0 and (data_counter mod 4 = 0)) then
+                    fifoWriteEnable <= '1';
+                end if;
+                data_counter <= data_counter + 1;
+            end if;
+        end if;
+    end process;
+
+-- tri-state buffers
+eth_rxd(0) <= '0' when MODE(0) = '0' else 'Z';
+eth_rxd(1) <= '0' when MODE(1) = '0' else 'Z';
+eth_crsdv <= '0' when MODE(2) = '0' else 'Z';
+eth_rxerr <= '0' when PHYAD = '0' else 'Z';
+-- RMII and MDC clocks
+eth_refclk <= b_clk50mhz;
+eth_mdc <= b_clk2_5mhz;--clk2_5mhz;
+
+-- outputs for debugging
+--mode0 <= eth_rxd(0);
+--mode1 <= eth_rxd(1);
+--mode2 <= eth_crsdv;
+--refclk <= b_clk50mhz;
+--rxerr <= eth_rxerr;
+--txd <= eth_txd;
+--txen <= eth_txen;
+
+fifoWriteData <= fifo_data;
+sendPacketStart <= not fifoReadEmpty;
+
+end Behavioral;
+

ip_repo_sources/UDP-server/src/led1.vhd

@@ -0,0 +1,94 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov 
+-- 
+-- Create Date:    14:15:42 03/30/2017 
+-- Design Name: 
+-- Module Name:    led1 - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- LED module visualise inflow of the valid data packets changing the colour of the 
+-- tri-colour LED's every time when valid ARP or UDP packet arrives
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity led1 is
+    Port ( clk50mhz : in  STD_LOGIC;
+			  rstn : in STD_LOGIC;
+           dv_arp : in  STD_LOGIC;
+			  dv_eth : in  STD_LOGIC;
+           led16_b : out  STD_LOGIC;
+			  led16_g : out  STD_LOGIC;
+			  led16_r : out  STD_LOGIC;
+			  led17_b : out  STD_LOGIC;
+			  led17_g : out  STD_LOGIC;
+			  led17_r : out  STD_LOGIC);
+end led1;
+
+architecture Behavioral of led1 is
+type state_type is (idle,arp_signal,eth_signal);
+signal state : state_type := idle;
+signal count_arp : integer range 0 to 3 := 0;
+signal count_eth : integer range 0 to 3 := 0;
+
+begin
+	led: process (clk50mhz,rstn,dv_arp,dv_eth)
+	begin
+		if (rstn = '0') then -- if Hardware Reset refresh counters and turn off led's
+			led16_b <= '0'; led16_g <= '0'; led16_r <= '0';
+			led17_b <= '0'; led17_g <= '0'; led17_r <= '0';
+			count_arp <= 0;
+			count_eth <= 0;
+		elsif (rising_edge(clk50mhz)) then
+			if (dv_arp ='1') then 			-- if valid ARP packet received
+				count_arp <= count_arp+1;  -- increment ARP counter 
+				if(count_arp+1 > 3) then
+					count_arp <= 1;
+				end if;
+			else
+				count_arp <= count_arp;
+			end if;
+				case count_arp is -- change ARP's led colour depending on the packet number 
+					when 0 => led16_b <= '0'; led16_g <= '0'; led16_r <= '0';
+					when 1 => led16_b <= '1'; led16_g <= '0'; led16_r <= '0';
+					when 2 => led16_b <= '0'; led16_g <= '1'; led16_r <= '0';
+					when 3 => led16_b <= '0'; led16_g <= '0'; led16_r <= '1';
+				end case;
+			
+			if (dv_eth ='1') then       -- if valid UDP packet received
+				count_eth <= count_eth+1;-- increment UDP counter 
+				if(count_eth+1 > 3) then
+					count_eth <= 1;
+				end if;
+			else
+				count_eth <= count_eth;
+			end if;
+				case count_eth is -- change UDP's led colour depending on the packet number 
+					when 0 => led17_b <= '0'; led17_g <= '0'; led17_r <= '0';
+					when 1 => led17_b <= '1'; led17_g <= '0'; led17_r <= '0';
+					when 2 => led17_b <= '0'; led17_g <= '1'; led17_r <= '0';
+					when 3 => led17_b <= '0'; led17_g <= '0'; led17_r <= '1';
+				end case;
+		end if;
+	end process led;
+
+end Behavioral;
+

ip_repo_sources/UDP-server/src/md_interface.vhd

@@ -0,0 +1,162 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov 
+-- 
+-- Create Date:    10:34:00 02/22/2017 
+-- Design Name: 
+-- Module Name:    md_interface - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- MDIO interface reads content of the SMI registers selected by input sw<4:0> and displays 
+-- their content using 16 on-board LED's
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity md_interface is
+    Port ( mdc_shift : in STD_LOGIC; -- clock for read/write SMI
+           mdio : inout  STD_LOGIC;  -- SMI data in/out line
+           eth_rstn : in  STD_LOGIC; -- reset
+           led : out  STD_LOGIC_VECTOR (15 downto 0); -- display for SMI registers
+           sw : in  STD_LOGIC_VECTOR (4 downto 0));   -- SMI register address
+end md_interface;
+
+architecture Behavioral of md_interface is
+
+signal mdio_prime : std_logic;
+constant preamble : std_logic_vector (31 downto 0) := x"FFFFFFFF"; -- preamble 32 1's
+constant start : std_logic_vector (1 downto 0) := "01";            -- start-of-frame
+constant wrt_mdio : std_logic_vector (1 downto 0) := "01";         -- code of write operation
+constant phy_addr : std_logic_vector (4 downto 0) := "00001";      -- physical address of chip
+signal reg_addr : std_logic_vector (4 downto 0);                   -- SMI register's address
+signal reg_data : std_logic_vector (15 downto 0);                  -- content of the SMI register
+type state_type is (idle, read_mdio);--, write_mdio);
+signal state : state_type := idle;
+signal counter : integer range  0 to 63 := 0;
+
+begin
+-- pull-up on I2C MDIO pin
+	PULLUP_MDIO: PULLUP PORT MAP (O => mdio);
+
+	mdio_interface: process (mdc_shift, eth_rstn)
+	begin
+		if (eth_rstn = '0') then
+			counter <= 0;
+			state <= idle;
+		elsif (rising_edge(mdc_shift)) then
+			case state is
+			
+			-- SMI module remains idle during reset
+			when idle =>
+				counter <= 0;
+				state <= read_mdio;
+			
+			-- in this state the SMI register, selected by sw<4:0> is read
+			when read_mdio =>
+				-- write preamble
+				if (counter <= 31) then
+					mdio_prime <= preamble(counter);
+					counter <= counter+1;
+					state <= read_mdio;
+				-- write start-of-frame bits
+				elsif (counter > 31 and counter <= 33)then
+					mdio_prime <= start(33-counter);
+					counter <= counter+1;
+					state <= read_mdio;
+				-- write operation code (read)
+				elsif (counter > 33 and counter <= 35) then
+					mdio_prime <= not(wrt_mdio(35-counter)); -- not(write) is read
+					counter <= counter+1;
+					state <= read_mdio;
+				-- write physical address of the device
+				elsif (counter > 35 and counter <=40) then
+					mdio_prime <= phy_addr(40-counter);
+					counter <= counter+1;
+					state <= read_mdio;
+				-- write register address to be read (sw<4:0>)
+				elsif (counter > 40 and counter <= 45) then
+					mdio_prime <= reg_addr(45-counter);
+					counter <= counter+1;
+					state <= read_mdio;
+				-- release line for turnaround bits
+				elsif (counter = 46 or counter = 47) then
+					mdio_prime <= '1'; --
+					counter <= counter+1;
+					state <= read_mdio;
+				-- read register's content
+				elsif (counter > 47 and counter < 63) then
+					reg_data(63-counter) <= mdio;
+					counter <= counter+1;
+					state <= read_mdio;
+				elsif (counter = 63) then
+					reg_data(63-counter) <= mdio;
+					counter <= 0;
+					state <= idle; -- go back to idle
+				end if;
+			
+			-- this state handles write SMI operation (not used in this design)
+--			when write_mdio =>
+--				read_done <= '0';
+--				if (counter <= 31) then
+--					mdio_prime <= preamble(counter);
+--					counter <= counter+1;
+--					state <= write_mdio;
+--				elsif (counter > 31 and counter <= 33)then
+--					mdio_prime <= start(33-counter);
+--					counter <= counter+1;
+--					state <= write_mdio;
+--				elsif (counter > 33 and counter <= 35) then
+--					mdio_prime <= wrt_mdio(35-counter);
+--					counter <= counter+1;
+--					state <= write_mdio;
+--				elsif (counter > 35 and counter <=40) then
+--					mdio_prime <= phy_addr(40-counter);
+--					counter <= counter+1;
+--					state <= write_mdio;
+--				elsif (counter > 40 and counter <= 45) then
+--					mdio_prime <= reg_addr_wrt(45-counter);
+--					counter <= counter+1;
+--					state <= write_mdio;
+--				elsif (counter = 46 or counter = 47) then -- turnaround bits
+--					mdio_prime <= '1';--
+--					counter <= counter+1;
+--					state <= write_mdio;
+--				elsif (counter > 47 and counter < 63) then
+--					mdio_prime <= reg_data_wrt(63-counter);
+--					counter <= counter+1;
+--					state <= write_mdio;
+--				elsif (counter = 63) then
+--					mdio_prime <= reg_data_wrt(63-counter);
+--					counter <= 0;
+--					write_done <= '1';
+--					state <= idle;
+--				end if;
+			
+			end case;
+		end if;
+	end process mdio_interface;
+	
+
+led <= reg_data; -- display content of the SMI register
+reg_addr <= sw;  -- read this register's content
+mdio <= '0' when mdio_prime = '0' else 'Z';
+
+end Behavioral;
+

ip_repo_sources/UDP-server/src/single_port_RAM.vhd

@@ -0,0 +1,66 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov 
+-- 
+-- Create Date:    17:24:25 02/19/2017 
+-- Design Name: 
+-- Module Name:    single_port_RAM - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- RAM module stores the data received with incoming packets and supplies it back to 
+-- Transmitter module for outgoing packets
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity single_port_RAM is
+	 Generic ( ADDR_WIDTH : integer;
+				  DATA_WIDTH : integer);
+    Port ( clk50mhz : in  STD_LOGIC; -- reference clock
+           we : in  STD_LOGIC;       -- write enable
+			  re : in STD_LOGIC;        -- read enable
+           addr_r : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0); -- address to write
+			  addr_w : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0); -- address to read
+           din : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);    -- data-in bus
+           dout : out  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)); -- data-out bus
+end single_port_RAM;
+
+architecture Behavioral of single_port_RAM is
+
+type ram_type is array (2**ADDR_WIDTH-1 downto 0) of 
+	std_logic_vector (DATA_WIDTH-1 downto 0);
+signal ram: ram_type := (others =>(others => '0'));
+
+begin
+	
+	memory: process (clk50mhz)
+	begin
+		if (rising_edge(clk50mhz)) then
+			if (we = '1') then -- when write is enabled
+				ram(to_integer(unsigned(addr_w))) <= din; -- write data on data-in bus into specified in addr_w register
+			end if;
+			if (re = '1') then -- when read is enabled
+				dout <= ram(to_integer(unsigned(addr_r)));-- read data from specified in addr_r register and place it on data-out bus
+			end if;
+		end if;
+	end process memory;
+
+end Behavioral;
+

ip_repo_sources/UDP-server/src/tb_eth_rxtx_arp_udp_ram.vhd

@@ -0,0 +1,258 @@
+--------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov
+--
+-- Create Date:   14:39:20 04/06/2017
+-- Design Name:   
+-- Module Name:   C:/Users/AM/Documents/ISE_projects/Nexyx4DDR/Ethernet/Ethernet_arp_udp_ram/eth_transceiver/tb_eth_rxtx_arp_udp_ram.vhd
+-- Project Name:  eth_transceiver
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: ethernet_transciever
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- This testbench file is used to test functionality of the UDP echo-server.
+-- First packet is ARP request being sent to echo-server from external
+-- data server to resolve the board's MAC address.
+-- 2nd and 4th packets are valid UDP messages of diffrent length and
+-- 3rd packet is invalid UDP message designated to the wrong port number.
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ 
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+ 
+ENTITY tb_eth_rxtx_arp_udp_ram IS
+END tb_eth_rxtx_arp_udp_ram;
+ 
+ARCHITECTURE behavior OF tb_eth_rxtx_arp_udp_ram IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT ethernet_transceiver2
+    Generic (M_clk2_5mhz1: integer := 20; -- divisor for 2.5MHz clock
+				 M_clk2_5mhz2: integer := 10; -- divisor for shifted 2.5MHz clock 
+				 N : integer := 22;           -- divisor for debouncing circuit 
+				 ADDR_WIDTH : integer := 10;  -- RAM's address width
+				 DATA_WIDTH : integer := 8);  -- RAM's data width (1024x1byte)
+    Port ( clk100mhz : in  STD_LOGIC;
+           eth_rxd : inout  STD_LOGIC_VECTOR (1 downto 0);
+           eth_txd : inout  STD_LOGIC_VECTOR (1 downto 0);
+           eth_crsdv : inout  STD_LOGIC;
+			  eth_txen : inout  STD_LOGIC;
+           eth_rxerr : inout  STD_LOGIC;
+			  eth_mdc : out  STD_LOGIC;
+           eth_mdio : inout  STD_LOGIC;
+           eth_refclk : out  STD_LOGIC;
+           eth_rstn : inout  STD_LOGIC;
+			  -- display signals for ARP and UDP packets
+			  led16_b : out  STD_LOGIC;
+			  led16_g : out  STD_LOGIC;
+			  led16_r : out  STD_LOGIC;
+			  led17_b : out  STD_LOGIC;
+			  led17_g : out  STD_LOGIC;
+			  led17_r : out  STD_LOGIC;
+			  -- outputs for debugging
+--			  mode0 : out std_logic;
+--			  mode1 : out std_logic;
+--			  mode2 : out std_logic;
+--			  refclk : out std_logic;
+--			  rxerr : out std_logic;
+--			  txd : out  STD_LOGIC_VECTOR (1 downto 0);
+--			  txen : out  STD_LOGIC;
+			  -- Reset and SMI inputs/outputs
+			  btn_reset : in std_logic;
+			  led : out std_logic_vector (15 downto 0);
+			  sw : in std_logic_vector (4 downto 0);
+			  
+			  fifoWriteEnable : out std_logic;
+			  fifoWriteData   : out std_logic_vector(31 downto 0);
+			  fifoWriteAlmostFull  : in std_logic;
+			  fifoWriteFull  : in std_logic;
+			  
+			  fifoReadEnable : out std_logic;
+			  fifoReadData   : in std_logic_vector(DATA_WIDTH-1 downto 0);
+			  fifoReadAlmostEmpty  : in std_logic;
+			  fifoReadEmpty  : in std_logic;
+			  sendPacketLength : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- length of IP datagram data field in bytes
+			  sendPacketChecksum : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0') -- UDP checksum
+			  );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal clk100mhz : std_logic := '0';
+   signal btn_reset : std_logic := '0';
+   signal sw : std_logic_vector(4 downto 0) := (others => '0');
+
+	--BiDirs
+   signal eth_rxd : std_logic_vector(1 downto 0);
+   signal eth_txd : std_logic_vector(1 downto 0);
+   signal eth_crsdv : std_logic;
+   signal eth_mdio : std_logic;
+   signal eth_rstn : std_logic;
+   signal eth_rxerr : std_logic;
+
+ 	--Outputs
+   signal led16_b : std_logic;
+   signal led16_g : std_logic;
+   signal led16_r : std_logic;
+   signal led17_b : std_logic;
+   signal led17_g : std_logic;
+   signal led17_r : std_logic;
+   signal eth_mdc : std_logic;
+   signal eth_refclk : std_logic;
+--   signal mode0 : std_logic;
+--   signal mode1 : std_logic;
+--   signal mode2 : std_logic;
+--   signal refclk : std_logic;
+--   signal rxerr : std_logic;
+   signal led : std_logic_vector(15 downto 0);
+   signal eth_txen : std_logic;
+
+   -- Clock period definitions
+   constant clk100mhz_period : time := 10 ns;
+   constant eth_refclk_period : time := 20 ns;
+   ---
+	signal data_arp : std_logic_vector(591 downto 0);
+	signal data_udp1 : std_logic_vector(591 downto 0);
+	signal data_udp2 : std_logic_vector(591 downto 0);
+	signal data_udp_err : std_logic_vector(591 downto 0);
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: ethernet_transceiver2 PORT MAP (
+          clk100mhz => clk100mhz,
+          eth_rxd => eth_rxd,
+          eth_txd => eth_txd,
+          eth_crsdv => eth_crsdv,
+          led16_b => led16_b,
+          led16_g => led16_g,
+          led16_r => led16_r,
+          led17_b => led17_b,
+          led17_g => led17_g,
+          led17_r => led17_r,
+          eth_mdc => eth_mdc,
+          eth_mdio => eth_mdio,
+          eth_refclk => eth_refclk,
+          eth_rstn => eth_rstn,
+--          mode0 => mode0,
+--          mode1 => mode1,
+--          mode2 => mode2,
+--          refclk => refclk,
+--          rxerr => rxerr,
+          btn_reset => btn_reset,
+          led => led,
+          sw => sw,
+          eth_txen => eth_txen,
+          eth_rxerr => eth_rxerr,
+          fifowritealmostfull => '0',
+          fifowritefull => '0',
+          fiforeaddata => (others=>'0'),
+          fiforeadalmostempty => '0',
+          fiforeadempty => '0'
+          
+        );
+
+   -- Clock process definitions
+   clk100mhz_process :process
+   begin
+		clk100mhz <= '0';
+		wait for clk100mhz_period/2;
+		clk100mhz <= '1';
+		wait for clk100mhz_period/2;
+   end process;
+ 
+   -- Stimulus process
+   stim_proc: process
+   begin		
+      eth_crsdv <= '0';
+		eth_rxd <= "00";
+		eth_rxerr <= '0';
+		data_arp <= x"0000aaaaaaaaaaaaaaabffffffffffff0007326ce4a6106000801000602000800007326ce4a6031580e00000000000000315805000000000000000000000000000000000000076052b35";
+		data_udp1 <= x"0000aaaaaaaaaaaaaaab00187c80ff8e0007326ce4a61000a20000a4e87e00000188f917031580e0031580506344c74600889d0b8040c020a060e0109000000000000000000014045003";
+		data_udp2 <= x"0000aaaaaaaaaaaaaaab00187c80ff8e0007326ce4a61000a20000b44c2b000001882151031580e0031580506344c74600983828f70f8f4fcf2faf6fef1f9f5fdf3fbf7fff009e1a4c3a";
+      data_udp_err <= x"0000aaaaaaaaaaaaaaab00187c80ff8e0007326ce4a61000a20000b44c2b000001882151031580e0031580506344c74500983829f60e8c3fce21af2def7f1a57df01b67bee009e1a4c3a";
+		
+		wait for 51 ms;
+		wait for 5 ns;
+
+		eth_crsdv <= '1';
+		for j in 295 downto 0 loop
+			eth_rxd(0) <= data_arp (2*j+1);
+			eth_rxd(1) <= data_arp (2*j);
+			if (j > 0) then
+				wait for eth_refclk_period;
+			elsif (j = 0) then
+				wait for eth_refclk_period;
+				eth_crsdv <= '0';
+			end if;
+		end loop;
+		eth_crsdv <= '0';
+      eth_rxd <= "00"; 
+		
+		wait for 200 us;
+		eth_crsdv <= '1';
+		for j in 295 downto 0 loop
+			eth_rxd(0) <= data_udp1 (2*j+1);
+			eth_rxd(1) <= data_udp1 (2*j);
+			if (j > 0) then
+				wait for eth_refclk_period;
+			elsif (j = 0) then
+				wait for eth_refclk_period;
+				eth_crsdv <= '0';
+			end if;
+		end loop;
+		eth_crsdv <= '0';
+		eth_rxd <= "00";
+		
+		wait for 200 us;
+		eth_crsdv <= '1';
+		for j in 295 downto 0 loop
+			eth_rxd(0) <= data_udp_err (2*j+1);
+			eth_rxd(1) <= data_udp_err (2*j);
+			if (j > 0) then
+				wait for eth_refclk_period;
+			elsif (j = 0) then
+				wait for eth_refclk_period;
+				eth_crsdv <= '0';
+			end if;
+		end loop;
+		eth_crsdv <= '0';
+		eth_rxd <= "00";
+		
+		wait for 200 us;
+		eth_crsdv <= '1';
+		for j in 295 downto 0 loop
+			eth_rxd(0) <= data_udp2 (2*j+1);
+			eth_rxd(1) <= data_udp2 (2*j);
+			if (j > 0) then
+				wait for eth_refclk_period;
+			elsif (j = 0) then
+				wait for eth_refclk_period;
+				eth_crsdv <= '0';
+			end if;
+		end loop;
+		eth_crsdv <= '0';
+		eth_rxd <= "00";
+
+      wait;
+   end process;
+
+END;

ip_repo_sources/UDP-server/xgui/ethernet_transceiver_v1_0.tcl

@@ -0,0 +1,85 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "ADDR_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "M_clk2_5mhz1" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "M_clk2_5mhz2" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "N" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.ADDR_WIDTH { PARAM_VALUE.ADDR_WIDTH } {
+	# Procedure called to update ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ADDR_WIDTH { PARAM_VALUE.ADDR_WIDTH } {
+	# Procedure called to validate ADDR_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
+	# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
+	# Procedure called to validate DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.M_clk2_5mhz1 { PARAM_VALUE.M_clk2_5mhz1 } {
+	# Procedure called to update M_clk2_5mhz1 when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.M_clk2_5mhz1 { PARAM_VALUE.M_clk2_5mhz1 } {
+	# Procedure called to validate M_clk2_5mhz1
+	return true
+}
+
+proc update_PARAM_VALUE.M_clk2_5mhz2 { PARAM_VALUE.M_clk2_5mhz2 } {
+	# Procedure called to update M_clk2_5mhz2 when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.M_clk2_5mhz2 { PARAM_VALUE.M_clk2_5mhz2 } {
+	# Procedure called to validate M_clk2_5mhz2
+	return true
+}
+
+proc update_PARAM_VALUE.N { PARAM_VALUE.N } {
+	# Procedure called to update N when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.N { PARAM_VALUE.N } {
+	# Procedure called to validate N
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.M_clk2_5mhz1 { MODELPARAM_VALUE.M_clk2_5mhz1 PARAM_VALUE.M_clk2_5mhz1 } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.M_clk2_5mhz1}] ${MODELPARAM_VALUE.M_clk2_5mhz1}
+}
+
+proc update_MODELPARAM_VALUE.M_clk2_5mhz2 { MODELPARAM_VALUE.M_clk2_5mhz2 PARAM_VALUE.M_clk2_5mhz2 } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.M_clk2_5mhz2}] ${MODELPARAM_VALUE.M_clk2_5mhz2}
+}
+
+proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N}
+}
+
+proc update_MODELPARAM_VALUE.ADDR_WIDTH { MODELPARAM_VALUE.ADDR_WIDTH PARAM_VALUE.ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ADDR_WIDTH}] ${MODELPARAM_VALUE.ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
+}
+

ip_repo_sources/UDP_echo-server/component.xml

@@ -0,0 +1,1462 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>ethernet_transceiver2</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>btn_reset</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>btn_reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>eth_rstn</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>eth_rstn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.ETH_RSTN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>fifo_read</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RD_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>fifo_read_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RD_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>fifo_read_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EMPTY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>fifo_read_empty</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>fifo_write</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WR_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>fifo_write_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WR_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>fifo_write_enable</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>FULL</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>fifo_write_full</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>ethernet_transceiver2</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>4218cab6</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>ethernet_transceiver2</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>f5e29829</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_testbench</spirit:name>
+        <spirit:displayName>Test Bench</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation.testbench</spirit:envIdentifier>
+        <spirit:modelName>ethernet_transceiver2</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_testbench_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>dd12fe65</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>4aa324c9</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk100mhz</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>eth_rxd</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>eth_txd</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>eth_crsdv</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>eth_txen</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>eth_rxerr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>eth_mdc</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>eth_mdio</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>eth_refclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>eth_rstn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>led16_b</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>led16_g</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>led16_r</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>led17_b</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>led17_g</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>led17_r</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>btn_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>led</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">15</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>udp_packet_checksum</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">15</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>udp_packet_recieved</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>udp_packet_sending</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>fifo_write_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.FIFO_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>fifo_write_enable</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>fifo_write_full</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>fifo_read_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.FIFO_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
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+</spirit:component>

ip_repo_sources/UDP_echo-server/src/clock_mod.vhd

@@ -0,0 +1,68 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov 
+-- 
+-- Create Date:    14:56:38 02/16/2017 
+-- Design Name: 
+-- Module Name:    clock_mod - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- This module provides Transceiver design with 2 clocks:
+-- - 50mhz clock, which is reference clock for the ethernet chip and
+-- - 50mhz_shifted clock, which is used for write Tx operations.
+-- 50mhz_shift clock is shifted by -pi/2 with respect to 50mhz clock
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_mod is
+--    Generic ( M_clk : integer);
+	 Port ( clk100mhz : in  STD_LOGIC;
+           clk_out : out  STD_LOGIC;
+			  clk_out_shift: out STD_LOGIC);
+end clock_mod;
+
+architecture Behavioral of clock_mod is
+
+signal temp_clk : std_logic := '0';
+signal temp_clk_shift : std_logic := '1';
+--signal count : integer range 0 to M_clk-1 :=0;
+
+begin
+	
+	clock: process (clk100mhz)
+	begin
+		if (rising_edge(clk100mhz)) then
+		temp_clk <= not(temp_clk);
+		end if;
+	end process clock;
+	
+	shift_clock: process (clk100mhz)
+	begin
+		if (falling_edge(clk100mhz)) then
+			temp_clk_shift <= not(temp_clk_shift);
+		end if;
+	end process shift_clock;
+	
+	clk_out <= temp_clk;
+	clk_out_shift <= temp_clk_shift;
+
+end Behavioral;
+

ip_repo_sources/UDP_echo-server/src/clock_mod2.vhd

@@ -0,0 +1,88 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov
+-- 
+-- Create Date:    14:56:38 02/16/2017 
+-- Design Name: 
+-- Module Name:    clock_mod - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- This module generates 2.5mhz clocks for the SMI interface.
+-- 2.5mhz clock is the MDC clock and 2.5mhz_shift clock is used for read/write
+-- MDIO operations and it's shifted by -pi/2 with respect to 2.5mhz clock
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_mod2 is
+    Generic ( M_clk1 : integer;
+				  M_clk2 : integer);
+	 Port ( clk100mhz : in  STD_LOGIC;
+           clk_out1 : out  STD_LOGIC;
+			  clk_out2 : out STD_LOGIC);
+end clock_mod2;
+
+architecture Behavioral of clock_mod2 is
+
+signal temp_clk1 : std_logic := '0';
+signal temp_clk2 : std_logic := '0';
+signal count1 : integer range 0 to M_clk1-1 :=0;
+signal count2 : integer range 0 to M_clk1+M_clk1-1 :=0;
+
+begin
+	
+	clock1: process (clk100mhz)
+	begin
+		if (rising_edge(clk100mhz)) then
+			if (count1 < M_clk1-1) then
+				count1 <= count1+1;
+			elsif (count1 = M_clk1-1) then
+				count1 <= 0;
+				temp_clk1 <= not (temp_clk1);
+			end if;
+		end if;
+	end process clock1;
+	
+	clock2: process (clk100mhz)
+	begin
+		if (rising_edge(clk100mhz)) then
+			if (count2 < M_clk1-1 and count2 <= M_clk2-1) then
+				count2 <= count2+1;
+			elsif (count2 < M_clk1-1 and count2 = M_clk2) then
+				count2 <= count2+1;
+				temp_clk2 <= not (temp_clk2);
+			elsif (count2 <= (M_clk1+M_clk2-1)) then
+				count2 <= count2+1;
+			elsif (count2 = (M_clk1+M_clk2)) then
+				count2 <= count2+1;
+				temp_clk2 <= not (temp_clk2);
+			elsif (count2 < (M_clk1+M_clk1-1)) then
+				count2 <= count2+1;
+			elsif (count2 = (M_clk1+M_clk1-1))then
+				count2 <= 0;
+			end if;
+		end if;
+	end process clock2;
+	
+	clk_out1 <= temp_clk1;
+	clk_out2 <= temp_clk2;
+
+end Behavioral;
+

ip_repo_sources/UDP_echo-server/src/crc32_parallel.vhd

@@ -0,0 +1,184 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov
+-- 
+-- Create Date:    15:13:21 03/26/2017 
+-- Design Name: 
+-- Module Name:    crc32_parallel - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- Cyclic Redundancy Check (CRC) module calculates the packet's crc and supplies 
+-- it back to the higher-level module. It performs calculations in parallel (2-bit
+-- wide) and uses 100mhz clock, whereas the rest of the server makes use of 50mhz clock.
+-- This allows to do crc calculations in parallel with reception and transmission of data
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity crc32_parallel is
+    Port ( clk100mhz : in  STD_LOGIC;
+           data_valid : in  STD_LOGIC; -- crc_start
+           rstn : in  STD_LOGIC;		   -- crc_stop
+           data_in : in  STD_LOGIC_VECTOR (1 downto 0); -- connected to rxd bus
+           crc : inout  STD_LOGIC_VECTOR (31 downto 0)); -- output for crc results
+end crc32_parallel;
+
+architecture Behavioral of crc32_parallel is
+type state_type is (idle, calc);
+signal state : state_type := idle;
+signal crc32_temp : std_logic_vector (31 downto 0);
+signal edge_count : std_logic;
+
+begin
+	-- because crc block works on 100mhz clock and processes the whole data nibble
+	-- during the single 100mhz clock period it uses edge_count to keep track of whether
+	-- the data on the bus has been processed already or not
+	-- crc made this way to make sure that crc block can calculate the crc value for the
+	-- packet being transmitted as this packed is actually being transmitted
+	-- and the results of crc calculations are available before transmitter starts
+	-- sending the crc results out
+	-- so, in fact, crc calculations are done in parallel with packet transmission
+	crc_32_2bit: process (clk100mhz,rstn)
+	begin
+		-- during reset state set all registers and flags to initial state
+		if (rstn = '1') then
+			crc32_temp <= (others => '1'); -- initial state of crc register
+			edge_count <= '0'; 				 -- keeps track of incoming data
+			state <= idle;
+		elsif (rising_edge(clk100mhz)) then
+			case state is
+			
+			-- in idle state crc block waits for the data_valid flag to be asserted 
+			when idle =>
+			crc32_temp <= (others => '1');
+			edge_count <= '0';
+			if (data_valid = '0') then
+				state <= idle;
+			-- once data_valid is asserted, calculate crc for the current data nibble
+			-- and invert edge_count
+			-- crc processes data nibbles on edge_count='0' only
+			elsif(data_valid = '1') then
+				crc32_temp(0) <= crc32_temp(30) xor data_in(1);
+				crc32_temp(1) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0));
+				crc32_temp(2) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(0);
+				crc32_temp(3) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(1);
+				crc32_temp(4) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(2);
+				crc32_temp(5) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(3);
+				crc32_temp(6) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(4);
+				crc32_temp(7) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(5);
+				crc32_temp(8) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(6);
+				crc32_temp(9) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(7);
+				crc32_temp(10) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(8);
+				crc32_temp(11) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(9);
+				crc32_temp(12) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(10);
+				crc32_temp(13) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(11);
+				crc32_temp(14) <= crc32_temp(12);
+				crc32_temp(15) <= crc32_temp(13);
+				crc32_temp(16) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(14);
+				crc32_temp(17) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(15);
+				crc32_temp(18) <= crc32_temp(16);
+				crc32_temp(19) <= crc32_temp(17);
+				crc32_temp(20) <= crc32_temp(18);
+				crc32_temp(21) <= crc32_temp(19);
+				crc32_temp(22) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(20);
+				crc32_temp(23) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(21);
+				crc32_temp(24) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(22);
+				crc32_temp(25) <= crc32_temp(23);
+				crc32_temp(26) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(24);
+				crc32_temp(27) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(25);
+				crc32_temp(28) <= crc32_temp(26);
+				crc32_temp(29) <= crc32_temp(27);
+				crc32_temp(30) <= crc32_temp(28);
+				crc32_temp(31) <= crc32_temp(29);
+				edge_count <= not(edge_count);
+				state <= calc;
+			end if;
+		
+			when calc => 
+			-- if valid data present on the bus
+			if (data_valid = '1') then
+				-- do nothing if edge_count = '1', just keep current crc result = to past crc result
+				if (edge_count = '1') then
+					edge_count <= not(edge_count);
+					crc32_temp <= crc32_temp;
+					state <= calc;
+				-- if edge_count = '0' calculate crc result for the new data nibble
+				elsif (edge_count = '0') then
+					edge_count <= not(edge_count);
+					---
+					crc32_temp(0) <= crc32_temp(30) xor data_in(1);
+					crc32_temp(1) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0));
+					crc32_temp(2) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(0);
+					crc32_temp(3) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(1);
+					crc32_temp(4) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(2);
+					crc32_temp(5) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(3);
+					crc32_temp(6) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(4);
+					crc32_temp(7) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(5);
+					crc32_temp(8) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(6);
+					crc32_temp(9) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(7);
+					crc32_temp(10) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(8);
+					crc32_temp(11) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(9);
+					crc32_temp(12) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(10);
+					crc32_temp(13) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(11);
+					crc32_temp(14) <= crc32_temp(12);
+					crc32_temp(15) <= crc32_temp(13);
+					crc32_temp(16) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(14);
+					crc32_temp(17) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(15);
+					crc32_temp(18) <= crc32_temp(16);
+					crc32_temp(19) <= crc32_temp(17);
+					crc32_temp(20) <= crc32_temp(18);
+					crc32_temp(21) <= crc32_temp(19);
+					crc32_temp(22) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(20);
+					crc32_temp(23) <= (crc32_temp(30) xor data_in(1)) xor (crc32_temp(31) xor data_in(0)) xor crc32_temp(21);
+					crc32_temp(24) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(22);
+					crc32_temp(25) <= crc32_temp(23);
+					crc32_temp(26) <= (crc32_temp(30) xor data_in(1)) xor crc32_temp(24);
+					crc32_temp(27) <= (crc32_temp(31) xor data_in(0)) xor crc32_temp(25);
+					crc32_temp(28) <= crc32_temp(26);
+					crc32_temp(29) <= crc32_temp(27);
+					crc32_temp(30) <= crc32_temp(28);
+					crc32_temp(31) <= crc32_temp(29);
+					state <= calc;
+				end if;
+			-- if data valid is deasserted, that means that the last valid data nibble, protected by crc,
+			-- has been already loaded to the Tx bus and the current crc result is the valid crc value for the
+			-- packet being transmitted
+			elsif (data_valid <= '0') then
+				edge_count <= '0';
+				state <= idle;
+			end if;
+		
+		end case;
+		end if;
+	end process crc_32_2bit;
+	
+	-- this process outputs calculated crc value to the upper level module on every
+	-- edge_count = '1' (i.e. on every 2nd 100mhz clock period)
+	crc_out: process (clk100mhz,crc,crc32_temp,edge_count)
+	begin
+		if (rising_edge(clk100mhz) and edge_count = '1') then
+			crc <= not(crc32_temp);
+		else
+			crc <= crc;
+		end if;
+	end process crc_out;
+
+end Behavioral;
+

ip_repo_sources/UDP_echo-server/src/debounce_switch.vhd

@@ -0,0 +1,109 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov
+-- 
+-- Create Date:    14:58:05 02/19/2017 
+-- Design Name: 
+-- Module Name:    debounce_switch - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- This module is responsible for debouncing Hardware Reset button
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity debounce_switch is
+	 Generic (N : integer);
+    Port ( clk100mhz : in  STD_LOGIC;
+           btn : in  STD_LOGIC;
+           db_sw : out  STD_LOGIC);
+end debounce_switch;
+
+architecture Behavioral of debounce_switch is
+
+	type state_type is (zero, one, wait0, wait1, init);
+	signal state : state_type := init;
+	signal timer : unsigned (N-1 downto 0) := (others => '0');
+	signal sw : std_logic;
+
+begin
+	
+	debouncer: process (clk100mhz,btn)
+	begin
+		if (rising_edge(clk100mhz)) then
+			case state is
+			
+				when init =>
+					timer <= (others => '1');
+					db_sw <= btn;
+					sw <= btn;
+					if (btn = '0') then
+						state <= zero;
+					elsif (btn = '1') then
+						state <= one;
+					end if;
+				
+				when zero =>
+					sw <= btn;
+					db_sw <= '0';
+					if (sw /= btn) then
+						state <= wait1;
+					elsif (sw = btn) then
+						state <= zero;
+					end if;
+				
+				when wait1 =>
+					sw <= btn;
+					if (timer > 0) then
+						timer <= timer-1;
+						db_sw <= '0';
+						state <= wait1;
+					elsif (timer = 0) then
+						db_sw <= btn;
+						state <= init;
+					end if;
+				
+				when one =>
+					sw <= btn;
+					db_sw <= '1';
+					if (sw /= btn) then
+						state <= wait0;
+					elsif (sw = btn) then
+						state <= one;
+					end if;
+				
+				when wait0 =>
+					sw <= btn;
+					if (timer > 0) then
+						timer <= timer-1;
+						db_sw <= '1';
+						state <= wait0;
+					elsif (timer = 0) then
+						db_sw <= btn;
+						state <= init;
+					end if;
+						
+					
+			end case;
+		end if;
+	end process debouncer;
+
+end Behavioral;
+

ip_repo_sources/UDP_echo-server/src/eth_receiver.vhd

@@ -0,0 +1,1167 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov
+-- 
+-- Create Date:    11:16:51 02/24/2017 
+-- Design Name: 
+-- Module Name:    eth_rexeiver - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- Ethernet receiver module handles reception of data packets from the data server.
+-- Only 2 sorts of packets are accepted: ARP requests and UDP packets.
+-- This module doesn't use any elasticity buffer to store incoming packets. The data is 
+-- being parsed in parallel with read operation. ARP and UDP packets designated to
+-- this echo-server are accepted and the rest is rejected.
+-- Receiver module includs 7 processes and 1 sub-module:
+-- - process to read data in;
+-- - process to parse Ethernet headers of the incoming packets;
+-- - process to parse headers of the higher-level protocols (ARP, IP4, UDP);
+-- - process to do IP header checksum check;
+-- - process to do UDP header checksum check;
+-- - process to handle data write operation to RAM block;
+-- - process to handle data pass to Transmitter block for echo-reply;
+-- - lower-level module, performing crc check of the incoming packets.
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity eth_receiver is
+	 Generic (ADDR_WIDTH : integer;
+				 DATA_WIDTH : integer);
+    Port ( clk100mhz : in STD_LOGIC; -- clock for crc checker
+			  clk50mhz : in  STD_LOGIC; -- reference clock, read rx bus on falling edge
+           rxd : in  STD_LOGIC_VECTOR (1 downto 0);
+           crsdv : in  STD_LOGIC;
+           rstn : in  STD_LOGIC;
+			  rxerr : in STD_LOGIC;
+			  -- RAM signals
+			  wrt_data_ram : inout STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
+			  wrt_addr_ram : inout STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
+			  wrt_enable_ram : out STD_LOGIC;
+			  -- Addresses
+           fpga_mac : in STD_LOGIC_VECTOR (47 downto 0);
+			  fpga_ip : in STD_LOGIC_VECTOR (31 downto 0);
+			  fpga_port : in STD_LOGIC_VECTOR (15 downto 0);
+			  pc_mac : out STD_LOGIC_VECTOR (47 downto 0);
+			  pc_ip : out  STD_LOGIC_VECTOR (31 downto 0);
+			  pc_port : out STD_LOGIC_VECTOR (15 downto 0);
+			  -- Data to Tx
+			  datacm : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0);
+			  udpl : out STD_LOGIC_VECTOR (15 downto 0);
+			  udpc : out STD_LOGIC_VECTOR (15 downto 0);
+			  send_arp_reply : out STD_LOGIC;
+			  send_ethernet_protocol: out STD_LOGIC;
+			  data_out_valid : out STD_LOGIC;
+			  is_idle : out std_logic);
+end eth_receiver;
+
+architecture Behavioral of eth_receiver is
+-- SIGNALS
+-- ******* process receive (responsible for handling Rx) ********--
+type state_type is (idle,wait_rx,read_eth_header,read_protocol_header,read_extra_ip_header,read_data,read_zero_padding,read_crc,check_crc);
+signal state : state_type := idle;
+signal bit_count : integer range 0 to 3 := 0;    							     -- counts number of nibbles read
+signal byte_count : integer range 0 to 1499 := 0;							     -- counts number of bytes read
+signal dest_mac : std_logic_vector (47 downto 0) := (others => '0');      -- register to store destination MAC address (from Ethernet header)
+signal source_mac : std_logic_vector (47 downto 0) := (others => '0');    -- register to store source MAC address (from Ethernet header)
+signal eth_prot_type : std_logic_vector (15 downto 0) := (others => '0'); -- register to store Ethernet Protocol Type
+signal bytes00, bytes01, bytes02, bytes03, bytes04, bytes05, bytes06, bytes07,
+bytes08, bytes09, bytes10, bytes11, bytes12, bytes13 : std_logic_vector (15 downto 0) := (others => '0'); -- registers to store IP/UDP headers
+signal byte_read_done : std_logic_vector (13 downto 0) := (others => '0'); -- flags for IP/UDP registers 
+signal read_eth_header_done : std_logic := '0';                            -- flag to indicate end of the Ethernet Header
+signal start_crc : std_logic := '0';       -- enable crc checking
+signal stop_crc : std_logic := '0';  		 -- disable crc checking
+signal unknown_request : std_logic := '0'; -- other unknown requests ORed
+-- ******* process eth_packet_type (responsible for parsing Ethernet header) ********--
+signal arp_request_expected : std_logic := '0';  -- flag set if Ethernet header matches ARP protocol
+signal eth_protocol_expected : std_logic := '0'; -- flag set if Ethernet header matches UDP protocol
+signal unknown_request1 : std_logic := '0';      -- Ethernet header matches neither ARP nor UDP protocols
+-- ******* process headers_parse (responsible for parsing ARP/UDP header) ********--
+signal ip_header_length : std_logic_vector (3 downto 0) := (others => '0');-- length in bytes of IP header (for UDP packet)
+signal ip_options_count_max : integer range 0 to 40 := 0;                  -- counter for UDP header's extra options (from 21 to 40 bytes)
+signal ip_extra_options : std_logic := '0'; 											-- set if UDP header has extra options
+signal ip_total_length : std_logic_vector (15 downto 0) := (others => '0');-- total length of datagram in bytes (IP header+payload (payload=UDP header+data)))
+signal data_counter_max : integer range 0 to 1471 := 0;							-- defines length of data field in bytes (without zero padding)
+signal zero_counter : integer range 0 to 18 := 0; 									-- defines length in bytes of zero padding
+signal identification : std_logic_vector (15 downto 0) := (others => '0'); -- ID number of the incoming packet
+signal flags_offset : std_logic_vector (15 downto 0) := (others => '0');   -- flags and fragmentation offset
+signal ip_header_checksum : std_logic_vector (15 downto 0) := (others => '0'); -- IP header's checksum
+signal ip_header_options : std_logic_vector (319 downto 0) := (others => '0'); -- vector to store IP header's optional fields
+signal byte_count_extra : integer range 0 to 39 := 0; 							-- byte counter for IP header's optional fields
+signal source_ip : std_logic_vector (31 downto 0) := (others => '0'); 		-- IP address of the sender
+signal source_port : std_logic_vector (15 downto 0) := (others => '0'); 	-- port number of the sender
+signal udp_length :std_logic_vector (15 downto 0) := (others => '0'); 		-- total length of UDP datagram (UDP header+data)
+signal udp_checksum :std_logic_vector (15 downto 0) := (others => '0'); 	-- UDP header's checksum
+signal temp_data : std_logic_vector (DATA_WIDTH-1 downto 0) := x"00"; 		-- register to temporarily save received data byte
+signal valid_data_byte_read : std_logic := '0'; -- flag indicateing that another data byte was read
+signal read_frame_done : std_logic := '0'; 		-- flag set when valid frame was read, cleared in idle state
+signal unknown_request2 : std_logic := '0'; 		-- set in case of any mismatch between incoming data and expected headers' structures
+-- ******* process ip_header_checksum_check (responsible for checking IP header's checksum) ********--
+signal ip_hcs_calc_temp1 : unsigned (23 downto 0) := (others => '0');   -- sum of all header's fields
+signal ip_hcs_calc_temp2 : unsigned (15 downto 0) := (others => '0');   -- sum of the carry-out with main checksum body
+signal ip_hcs_calc_extra : unsigned (23 downto 0) := (others => '0');   -- sum of IP header's extra options field
+signal edge_count_header : std_logic := '0'; 							      -- used to set correct format of the extra header field in checksum calculations 
+signal ip_hcs_calc : std_logic_vector (15 downto 0) := (others => '1'); -- calculated IP header's checksum
+signal ip_hcs_done : std_logic := '0';      -- flag set when checksum calculation completed
+type sip_type is (sip1,sip2,sip3);          -- states of the IP header's checksum FSM
+signal sip : sip_type := sip1;
+signal unknown_request3 : std_logic := '0'; -- flag set when calculated IP header's checksum is not equal to zero
+-- ******* process udp_header_checksum_check (responsible for checking UDP header's checksum) ********--
+signal udp_presum : unsigned (23 downto 0) := (others => '0');   -- sum of the UDP header's fields
+signal udp_presum_done : std_logic := '0'; 							  -- flag set when sum of the UDP header's fields calculated
+signal udp_data_sum : unsigned (23 downto 0) := (others => '0'); -- sum of all data fields
+signal udp_datasum_done : std_logic := '0'; 							  -- flag set when sum of all data fields calculated
+signal edge_count_data : std_logic := '0'; 							  -- used to set correct format of the current data field in checksum calculations 
+signal udp_hcs_calc_temp1 : unsigned (23 downto 0) := (others => '0');   -- sum of the sums of UDP header's fields and all data fields
+signal udp_hcs_calc_temp2 : unsigned (15 downto 0) := (others => '0');   -- sum of the carry-out with main checksum body
+signal udp_hcs_calc : std_logic_vector (15 downto 0) := (others => '1'); -- calculated UDP header's checksum
+signal udp_hcs_done : std_logic := '0';     -- flag set when UDP header's checksum calculated
+type sudp_type is (sudp1,sudp2,sudp3);      -- states of the UDP header's checksum FSM
+signal sudp : sudp_type := sudp1;
+signal unknown_request4 : std_logic := '0'; -- flag set when calculated UDP header's checksum is not equal to zero
+-- ******* process data_out_ram (responsible for saving valid data into RAM) ********--
+type s_ram_type is (s_ram1, s_ram2, s_ram3, s_ram4);                              -- states of the write RAM FSM
+signal s_ram : s_ram_type := s_ram1;
+signal addr_count : unsigned (ADDR_WIDTH-1 downto 0) := (others => '0'); 			 -- address to write RAM counter
+signal data_to_ram : std_logic_vector (DATA_WIDTH-1 downto 0) := (others => '0'); -- data to write to RAM register
+signal we_ram : std_logic := '0';  -- enable write RAM
+signal rst_ram : std_logic := '0'; -- reset input signals to RAM
+-- ******* crc checker's signals ********--
+signal crc_rx : std_logic_vector (31 downto 0) := (others => '0');         -- received crc value
+signal crc_calculated : std_logic_vector (31 downto 0) := (others => '0'); -- calculated crc value
+signal crc_pass : std_logic := '0';                                        -- flag set if read crc = calculated crc
+--*************** constants ********************--
+constant arp_request : std_logic_vector (15 downto 0) := x"0001";       -- code of ARP request operation
+constant arp_hw_type : std_logic_vector (15 downto 0) := x"0001";       -- code of ARP hardware type
+constant arp_protocol_type : std_logic_vector (15 downto 0) := x"0800"; -- code of ARP protocol type
+constant arp_hw_length : std_logic_vector (7 downto 0) := x"06";        -- code of ARP hardware length for Ethernet
+constant arp_protocol_length : std_logic_vector (7 downto 0) := x"04";  -- code of ARP protocol length for IP4
+constant ip_protocol : std_logic_vector (7 downto 0) := x"11";          -- code of transport layer protocol for UDP
+constant arp : std_logic_vector (15 downto 0) := x"0806";               -- code for the upper layer protocol that uses service of Internet (ARP)
+constant ethernet : std_logic_vector (15 downto 0) := x"0800";          -- code for the upper layer protocol that uses service of Internet (IP4)
+--***********************************--
+
+-- CRC checker declaration
+component crc32_parallel
+			 port (clk100mhz : in  STD_LOGIC;
+					 data_valid : in  STD_LOGIC;
+					 data_in : in  STD_LOGIC_VECTOR (1 downto 0);
+					 rstn : in STD_LOGIC;
+					 crc : inout  STD_LOGIC_VECTOR (31 downto 0));
+end component;
+
+begin
+-- CRC checker instantiation
+	crc_checker: crc32_parallel
+					 port map (clk100mhz => clk100mhz,
+								  data_valid => start_crc,
+								  data_in => rxd,
+								  rstn => stop_crc,
+								  crc => crc_calculated);
+								  
+
+	receive: process (clk50mhz,rstn)
+	begin
+		if (rstn = '0') then -- if transciever is being reset receiver becomes idle
+			state <= idle;
+		elsif (falling_edge(clk50mhz)) then
+			case state is
+			
+			-- Idle state all Rx flags and registers reset and Rx waits until
+			-- crsdv signal is and Preamble's nibbles appear on rxd bus
+			when idle =>
+				---flags
+				byte_read_done <= (others => '0');
+				crc_pass <= '0';
+				read_frame_done <= '0';
+				rst_ram <= '0';
+				start_crc <= '0';
+				stop_crc <= '1';
+				read_eth_header_done <= '0';
+				--- header registers
+				dest_mac <= (others => '0');
+				source_mac <= (others => '0');
+				eth_prot_type <= (others => '0');
+				--- counters
+				byte_count <= 0;
+				bit_count <= 0;
+				--- data registers
+				temp_data <= (others => '0');
+				crc_rx <= (others => '0');
+				--crc_calculated <= (others => '0');
+				bytes00 <= (others => '0');
+				bytes01 <= (others => '0');
+				bytes02 <= (others => '0');
+				bytes03 <= (others => '0');
+				bytes04 <= (others => '0');
+				bytes05 <= (others => '0');
+				bytes06 <= (others => '0');
+				bytes07 <= (others => '0');
+				bytes08 <= (others => '0');
+				bytes09 <= (others => '0');
+				bytes10 <= (others => '0');
+				bytes11 <= (others => '0');
+				bytes12 <= (others => '0');
+				bytes13 <= (others => '0');
+				-- if data valid signal is asserted, no error symbol is detected and
+				-- the first Preamble's nibbles appear on rxd bus receiver goes into the next state
+				if (crsdv = '1' and rxerr = '0' and rxd = "01") then 
+					state <= wait_rx;
+				else -- else it remains idle
+					state <= idle;
+				end if;
+			
+			-- in this state receiver waits for the last nibble of SFD
+			-- and goes into the next state where it reads Ethernet header
+			when wait_rx =>
+				-- if data valid signal deasserted or error symbol detected
+				-- receiver becomes idle
+				if (crsdv = '0' or rxerr = '1') then 
+					bit_count <= 0;
+					byte_count <= 0;
+					stop_crc <= '1';
+					start_crc <= '0';
+					rst_ram <= '1';
+					state <= idle;
+				else -- else wait for the "11" nibble - last nibble of SFD
+					rst_ram <= '0';
+					if (crsdv = '1' and rxd = "01") then
+						state <= wait_rx;
+					elsif (crsdv = '1' and rxd = "11") then
+						start_crc <= '1'; -- start crc check immediately after SFD
+						stop_crc <= '0';
+						state <= read_eth_header;
+					end if;
+				end if;
+			
+			-- read first 14 bytes (destination mac,source mac and protocol type) in this state
+			when read_eth_header => 
+				-- if data valid signal deasserted or error symbol detected
+				-- receiver becomes idle and stops crc check
+				if (crsdv = '0' or rxerr = '1') then
+					bit_count <= 0;
+					byte_count <= 0;
+					stop_crc <= '1'; 
+					start_crc <= '0';
+					rst_ram <= '1';
+					state <= idle;
+				else
+					rst_ram <= '0';
+					-- read destination MAC address
+					if (byte_count <= 5 and bit_count < 3) then
+						dest_mac((5-byte_count)*8+2*bit_count+1 downto (5-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_eth_header;
+					elsif (byte_count <= 5 and bit_count = 3) then
+						dest_mac((5-byte_count)*8+2*bit_count+1 downto (5-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						state <= read_eth_header;
+					-- read source MAC address
+					elsif (byte_count > 5 and byte_count <= 11 and bit_count < 3) then
+						source_mac((11-byte_count)*8+2*bit_count+1 downto (11-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_eth_header;
+					elsif (byte_count > 5 and byte_count <= 11 and bit_count = 3) then
+						source_mac((11-byte_count)*8+2*bit_count+1 downto (11-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						state <= read_eth_header;
+					-- read upper layer protocol type
+					elsif (byte_count > 11 and byte_count <= 13 and bit_count < 3) then
+						eth_prot_type((13-byte_count)*8+2*bit_count+1 downto (13-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_eth_header;
+					elsif (byte_count > 11 and byte_count <= 13 and bit_count = 3) then
+						eth_prot_type((13-byte_count)*8+2*bit_count+1 downto (13-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 13) then
+							byte_count <= 0;
+							read_eth_header_done <= '1'; -- set flag indicating end of read Ethernet header operation
+							-- this flag also starts eth_packet_type process
+							state <= read_protocol_header; -- go to next state and read Payload fields
+						else
+							state <= read_eth_header;
+						end if;
+					end if;
+				end if;
+			
+			-- read next 28 bytes here (both ARP and IP4 have 28-byte long headers (when there are no extra fields in IP header))
+			when read_protocol_header => 
+				-- if data valid signal deasserted or error symbol detected
+				-- receiver becomes idle and stops crc check
+				if (crsdv = '0' or rxerr = '1' or unknown_request = '1') then
+					bit_count <= 0;
+					byte_count <= 0;
+					byte_read_done <= (others => '0');
+					stop_crc <= '1';
+					start_crc <= '0';
+					rst_ram <= '1';
+					state <= idle;
+				-- bytes 00 to 13 store the headers' data; 
+				-- byte_read_done flags register is being set as receiver keeps reading the header's fields
+				-- every individual flag triggers separate header parse operations in headers_parse process
+				else 
+					rst_ram <= '0';
+					-- bytes 0 and 1
+					if (byte_count <= 1 and bit_count < 3) then
+						bytes00((1-byte_count)*8+2*bit_count+1 downto (1-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count <= 1 and bit_count = 3) then
+						bytes00((1-byte_count)*8+2*bit_count+1 downto (1-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 1) then
+							byte_read_done(0) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 2 and 3	
+					elsif (byte_count > 1 and byte_count <= 3 and bit_count < 3) then
+						bytes01((3-byte_count)*8+2*bit_count+1 downto (3-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 1 and byte_count <= 3 and bit_count = 3) then
+						bytes01((3-byte_count)*8+2*bit_count+1 downto (3-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 3) then
+							byte_read_done(1) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 4 and 5	
+					elsif (byte_count > 3 and byte_count <= 5 and bit_count < 3) then
+						bytes02((5-byte_count)*8+2*bit_count+1 downto (5-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 3 and byte_count <= 5 and bit_count = 3) then
+						bytes02((5-byte_count)*8+2*bit_count+1 downto (5-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 5) then
+							byte_read_done(2) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 6 and 7
+					elsif (byte_count > 5 and byte_count <= 7 and bit_count < 3) then
+						bytes03((7-byte_count)*8+2*bit_count+1 downto (7-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 5 and byte_count <= 7 and bit_count = 3) then
+						bytes03((7-byte_count)*8+2*bit_count+1 downto (7-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 7) then
+							byte_read_done(3) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 8 and 9
+					elsif (byte_count > 7 and byte_count <= 9 and bit_count < 3) then
+						bytes04((9-byte_count)*8+2*bit_count+1 downto (9-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 7 and byte_count <= 9 and bit_count = 3) then
+						bytes04((9-byte_count)*8+2*bit_count+1 downto (9-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 9) then
+							byte_read_done(4) <= '1';
+							-- if this is IP4 packet and its header contain extra field
+							-- go and read them and come back to this state to finish
+							-- reading the regular fields
+							if (ip_extra_options = '1') then 
+								byte_count_extra <= 0;
+								state <= read_extra_ip_header;
+							else -- keep reading the header
+								state <= read_protocol_header;
+							end if;
+						end if;
+					-- bytes 10 and 11
+					elsif (byte_count > 9 and byte_count <= 11 and bit_count < 3) then
+						bytes05((11-byte_count)*8+2*bit_count+1 downto (11-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 9 and byte_count <= 11 and bit_count = 3) then
+						bytes05((11-byte_count)*8+2*bit_count+1 downto (11-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 11) then
+							byte_read_done(5) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 12 and 13
+					elsif (byte_count > 11 and byte_count <= 13 and bit_count < 3) then
+						bytes06((13-byte_count)*8+2*bit_count+1 downto (13-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 11 and byte_count <= 13 and bit_count = 3) then
+						bytes06((13-byte_count)*8+2*bit_count+1 downto (13-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 13) then
+							byte_read_done(6) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 14 and 15
+					elsif (byte_count > 13 and byte_count <= 15 and bit_count < 3) then
+						bytes07((15-byte_count)*8+2*bit_count+1 downto (15-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 13 and byte_count <= 15 and bit_count = 3) then
+						bytes07((15-byte_count)*8+2*bit_count+1 downto (15-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 15) then
+							byte_read_done(7) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 16 and 17
+					elsif (byte_count > 15 and byte_count <= 17 and bit_count < 3) then
+						bytes08((17-byte_count)*8+2*bit_count+1 downto (17-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 15 and byte_count <= 17 and bit_count = 3) then
+						bytes08((17-byte_count)*8+2*bit_count+1 downto (17-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 17) then
+							byte_read_done(8) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 18 and 19
+					elsif (byte_count > 17 and byte_count <= 19 and bit_count < 3) then
+						bytes09((19-byte_count)*8+2*bit_count+1 downto (19-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 17 and byte_count <= 19 and bit_count = 3) then
+						bytes09((19-byte_count)*8+2*bit_count+1 downto (19-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 19) then
+							byte_read_done(9) <= '1'; -- this flag starts ip_header_checksum_check process
+						end if;
+						state <= read_protocol_header;
+					-- bytes 20 and 21
+					elsif (byte_count > 19 and byte_count <= 21 and bit_count < 3) then
+						bytes10((21-byte_count)*8+2*bit_count+1 downto (21-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 19 and byte_count <= 21 and bit_count = 3) then
+						bytes10((21-byte_count)*8+2*bit_count+1 downto (21-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 21) then
+							byte_read_done(10) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 22 and 23
+					elsif (byte_count > 21 and byte_count <= 23 and bit_count < 3) then
+						bytes11((23-byte_count)*8+2*bit_count+1 downto (23-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 21 and byte_count <= 23 and bit_count = 3) then
+						bytes11((23-byte_count)*8+2*bit_count+1 downto (23-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 23) then
+							byte_read_done(11) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 24 and 25
+					elsif (byte_count > 23 and byte_count <= 25 and bit_count < 3) then
+						bytes12((25-byte_count)*8+2*bit_count+1 downto (25-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 23 and byte_count <= 25 and bit_count = 3) then
+						bytes12((25-byte_count)*8+2*bit_count+1 downto (25-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 25) then
+							byte_read_done(12) <= '1';
+						end if;
+						state <= read_protocol_header;
+					-- bytes 26 and 27
+					elsif (byte_count > 25 and byte_count <= 27 and bit_count < 3) then
+						bytes13((27-byte_count)*8+2*bit_count+1 downto (27-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= bit_count+1;
+						state <= read_protocol_header;
+					elsif (byte_count > 25 and byte_count <= 27 and bit_count = 3) then
+						bytes13((27-byte_count)*8+2*bit_count+1 downto (27-byte_count)*8+2*bit_count) <= rxd;
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 27) then
+							byte_read_done(13) <= '1';-- this flag starts udp_header_checksum_check process
+							byte_count <= 0;
+							-- if data field is empty in this packet go and read zero-padded fields
+							if(data_counter_max = 0) then
+								state <= read_zero_padding;
+							else -- else read valid data
+								state <= read_data;
+							end if;
+						else 
+							state <= read_protocol_header;
+						end if;
+					end if;
+				end if;
+				
+				-- read extra ip_options_count_max-1 bytes of ip header
+				-- this design makes no use of extra fields, but they are important
+				-- for correct packet parsing and checksum calculations!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+				when read_extra_ip_header => 
+					-- if data valid signal deasserted or error symbol detected
+					-- receiver becomes idle and stops crc check
+					if (crsdv = '0' or rxerr = '1' or unknown_request = '1') then
+						bit_count <= 0;
+						byte_count <= 0;
+						byte_read_done <= (others => '0');
+						stop_crc <= '1';
+						start_crc <= '0';
+						rst_ram <= '1';
+						state <= idle;
+					else
+						rst_ram <= '0';
+						if (byte_count_extra <= ip_options_count_max-1 and bit_count < 3) then
+							ip_header_options((ip_options_count_max-1-byte_count_extra)*8+2*bit_count+1 downto (ip_options_count_max-1-byte_count_extra)*8+2*bit_count) <= rxd;
+							bit_count <= bit_count+1;
+							state <= read_extra_ip_header;
+						elsif (byte_count_extra <= ip_options_count_max-1 and bit_count = 3) then
+							ip_header_options((ip_options_count_max-1-byte_count_extra)*8+2*bit_count+1 downto (ip_options_count_max-1-byte_count_extra)*8+2*bit_count) <= rxd;
+							bit_count <= 0;
+							if (byte_count_extra < ip_options_count_max-1) then
+								byte_count_extra <= byte_count_extra+1;
+								state <= read_extra_ip_header;
+							elsif (byte_count_extra = ip_options_count_max-1) then
+								byte_count_extra <= 0;
+								state <= read_protocol_header; -- when done reading extra header's fields 
+								-- go back and finish reading the regular ones
+							end if;
+						end if;
+					end if;
+				
+				-- when packet contains valid data, read it here
+				when read_data =>
+					-- if data valid signal deasserted or error symbol detected
+					-- receiver becomes idle and stops crc check
+					if (crsdv = '0' or rxerr = '1' or unknown_request = '1') then
+						bit_count <= 0;
+						byte_count <= 0;
+						byte_read_done <= (others => '0');
+						stop_crc <= '1';
+						start_crc <= '0';
+						rst_ram <= '1';
+						state <= idle;
+					else 
+					-- every data byte is stored into temporary register from where it is transfered to RAM
+						rst_ram <= '0';
+						if (byte_count <= data_counter_max-1 and bit_count < 3) then
+							temp_data(2*bit_count+1 downto 2*bit_count) <= rxd;
+							bit_count <= bit_count+1;
+							valid_data_byte_read <= '0';
+							state <= read_data;
+						elsif (byte_count <= data_counter_max-1 and bit_count = 3) then
+							temp_data(2*bit_count+1 downto 2*bit_count) <= rxd;
+							bit_count <= 0;
+							byte_count <= byte_count+1;
+							valid_data_byte_read <= '1'; -- this flad triggers data transfer to RAM (process data_out_ram)
+							if (byte_count = data_counter_max-1) then
+								byte_count <= 0;
+								if (zero_counter /= 0) then -- if packet contains any zero-padded data fields go and read them
+									state <= read_zero_padding;
+								else -- else if there is no zero-padding stop crc checker and read incoming crc 
+									start_crc <= '0';
+									state <= read_crc;
+								end if;
+							else
+								state <= read_data;
+							end if;
+						end if;
+					end if;
+					
+				-- when packet contains zero-padded data fields, read it here
+				when read_zero_padding =>
+					valid_data_byte_read <= '0'; -- clear the flag set when the last data byte was read
+					-- if data valid signal deasserted or error symbol detected
+					-- receiver becomes idle and stops crc check
+					if (crsdv = '0' or rxerr = '1' or unknown_request = '1') then
+						bit_count <= 0;
+						byte_count <= 0;
+						byte_read_done <= (others => '0');
+						stop_crc <= '1'; --------------------------------------------crc
+						start_crc <= '0';--------------------------------------------crc
+						rst_ram <= '1';
+						state <= idle;
+					else -- zero-padding simply discarded, not stored
+						rst_ram <= '0';
+						if (byte_count <= zero_counter-1 and bit_count < 3) then
+							bit_count <= bit_count+1;
+							state <= read_zero_padding;
+						elsif (byte_count <= zero_counter-1 and bit_count = 3) then
+							bit_count <= 0;
+							byte_count <= byte_count+1;
+							if (byte_count+1 > zero_counter-1) then
+								byte_count <= 0;
+								start_crc <= '0';-- stop crc checker here
+								state <= read_crc;
+							else
+								state <= read_zero_padding;
+							end if;
+						end if;
+					end if;
+				
+				-- read crc field
+				-- validity of Rx data isn't checked, since any problems on the bus/lines
+				-- will be reflected on the crc field content and the packet will not pass crc check
+				when read_crc =>
+					valid_data_byte_read <= '0';-- clear the flag set when the last data byte was read
+					if (byte_count <= 3 and bit_count < 3) then
+						crc_rx((3-byte_count)*8+2*(3-bit_count)+1) <= rxd(0);
+						crc_rx((3-byte_count)*8+2*(3-bit_count)) <= rxd(1);
+						bit_count <= bit_count+1;
+						state <= read_crc;
+					elsif (byte_count <= 3 and bit_count = 3) then
+						crc_rx((3-byte_count)*8+2*(3-bit_count)+1) <= rxd(0);
+						crc_rx((3-byte_count)*8+2*(3-bit_count)) <= rxd(1);
+						bit_count <= 0;
+						byte_count <= byte_count+1;
+						if (byte_count = 3) then
+							byte_count <= 0;
+							read_frame_done <= '1';-- flag indicating the end of frame; resets RAM's signals
+							state <= check_crc; --
+						else
+							state <= read_crc;
+						end if;
+					end if;
+				
+				-- here calculated and received crc values are compared
+				when check_crc =>
+					if (crc_rx = crc_calculated) then
+						crc_pass <= '1'; -- if they are the same - packet is valid
+						rst_ram <= '0';
+					else
+						crc_pass <= '0'; -- else reject packet
+						rst_ram <= '1';
+					end if;
+					-- clear flags here
+					read_eth_header_done <= '0';
+					read_frame_done <= '0';
+					state <= idle;
+						
+			   end case;
+		end if;		
+	end process receive;
+	
+	-- this process start after Ethernet header is read and it decides whether to accept or
+	-- reject packet (when it's not addressed to FPGA, for example) and determines
+	-- the type of the upper layer protocol
+	eth_packet_type: process (read_eth_header_done,dest_mac,eth_prot_type,
+	fpga_mac,clk50mhz)
+		begin
+		if(rising_edge(clk50mhz)) then
+				if (read_eth_header_done = '1') then -- decision is made immediately after Ethernet header
+				-- has been read and it is maintained until the whole packet is read or any error is encountered
+					if ((dest_mac = x"ffffffffffff" or dest_mac = fpga_mac) and eth_prot_type = arp) then -- ARP request
+						arp_request_expected <= '1';
+						eth_protocol_expected <= '0';
+						unknown_request1 <= '0';
+					elsif ((dest_mac = x"ffffffffffff" or dest_mac = fpga_mac) and eth_prot_type = ethernet) then -- IP4 protocol
+						arp_request_expected <= '0';
+						eth_protocol_expected <= '1';
+						unknown_request1 <= '0';
+					else -- none of the above - reject packet
+						arp_request_expected <= '0';
+						eth_protocol_expected <= '0';
+						unknown_request1 <= '1'; -- flag indicating invalid packet set
+					end if;
+				else -- refresh protocol type registers
+					arp_request_expected <= '0';
+					eth_protocol_expected <= '0';
+					unknown_request1 <= '0';
+				end if;
+		end if;
+	end process eth_packet_type;
+	
+	-- this process parses headers based on the type of protocol detected by the process eth_packet_type
+	-- in case of any mismatch between expected and actual headers' fields the packets are rejected
+	headers_parse : process (byte_read_done,arp_request_expected,eth_protocol_expected,data_counter_max,source_mac,
+	fpga_ip,fpga_port,ip_header_length,bytes00,bytes01,bytes02,bytes03,
+	bytes04,bytes05,bytes06,bytes07,bytes08,bytes09,bytes10,bytes11,bytes12,bytes13,clk50mhz)
+	begin
+	if (rising_edge(clk50mhz)) then
+			-- if Ethernet header corresponds to ARP request
+			if (arp_request_expected = '1' and eth_protocol_expected = '0') then
+				-- the following registers are set to zero, since they are for the IP4/UDP protocols, not for ARP
+				ip_extra_options <= '0';
+				source_ip <= (others => '0');
+				source_port <= (others => '0');
+				ip_options_count_max <= 0;
+				udp_length <= (others => '0');
+				udp_checksum <= (others => '0');
+				ip_header_length <= (others => '0');
+				ip_total_length <= (others => '0');
+				ip_header_checksum <= (others => '0');
+				-- bytes00
+				if (byte_read_done(0)='1') then
+					if (arp_hw_type = bytes00) then -- if ARP hardware type read matches expected value
+						unknown_request2 <= '0'; 	  -- let packet pass
+					else
+						unknown_request2 <= '1';     -- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes01
+				if (byte_read_done(1)='1') then
+					if (arp_protocol_type = bytes01) then -- if ARP hardware type read matches expected value
+						unknown_request2 <= '0';           -- let packet pass
+					else
+						unknown_request2 <= '1';           -- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes02
+				if (byte_read_done(2)='1') then
+					-- if ARP hardware length and protocol length read match expected values
+					if (arp_hw_length = bytes02(15 downto 8) and arp_protocol_length = bytes02(7 downto 0)) then
+						unknown_request2 <= '0';           -- let packet pass
+					else
+						unknown_request2 <= '1';			  -- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes03
+				if (byte_read_done(3)='1') then
+					if (arp_request = bytes03) then -- if ARP request received
+						data_counter_max <= 0;  	  -- arp request has no data
+						zero_counter <= 18;			  -- arp request has 18 bytes of zero padding
+						unknown_request2 <= '0';	  -- let packet pass
+					else
+						data_counter_max <= 0; 
+						zero_counter <= 0;
+						unknown_request2 <= '1';	  -- else reject it
+					end if;
+				else 								        -- refresh data and zero count registers
+					data_counter_max <= 0; 
+					zero_counter <= 0;
+					unknown_request2 <= '0';
+				end if;
+				-- bytes04, bytes05, bytes06
+				if (byte_read_done(4)='1' and byte_read_done(5)='1' and byte_read_done(6)='1') then
+					if (source_mac = bytes04&bytes05&bytes06) then -- if source MAC matches the one read in Ethernet header
+						unknown_request2 <= '0';						  -- let packet pass
+					else
+						unknown_request2 <= '1';						  -- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes07, bytes08
+				if (byte_read_done(7)='1' and byte_read_done(8)='1') then
+					source_ip <= bytes07&bytes08; -- read source IP4 address
+				else
+					source_ip <= (others =>'0');  -- refresh source IP4 address register
+				end if;
+				-- bytes09, bytes10, bytes11
+				if (byte_read_done(9)='1' and byte_read_done(10)='1' and byte_read_done(11)='1') then
+					if (bytes09&bytes10&bytes11 = x"000000000000" or bytes09&bytes10&bytes11 = fpga_mac) then -- if target MAC address is zeros
+						unknown_request2 <= '0';								 -- let packet pass
+					else
+						unknown_request2 <= '1';								 -- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes12, bytes13
+				if (byte_read_done(12)='1' and byte_read_done(13)='1') then
+					if (fpga_ip = bytes12&bytes13) then -- if destination IP4 address = FPGA IP4 address
+						unknown_request2 <= '0';			-- let packet pass
+					else
+						unknown_request2 <= '1';			-- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+			-- if Ethernet header corresponds to IP4/UDP protocol
+			elsif (arp_request_expected = '0' and eth_protocol_expected = '1') then
+				-- bytes00
+				if (byte_read_done(0)='1') then
+					if (bytes00(15 downto 12) = "0100") then -- if IP version = 4 
+						unknown_request2 <= '0';				  -- let packet pass
+					else
+						unknown_request2 <= '1';				  -- else reject it
+					end if;
+					ip_header_length <= bytes00(11 downto 8);-- read IP header's length
+					if (4*to_integer(unsigned(ip_header_length)) > 20)then 						-- if it's greater than 20 bytes
+						ip_options_count_max <= 4*to_integer(unsigned(ip_header_length))-20; -- set extra header's field counter
+						ip_extra_options <= '1'; 															-- set flag indicating presence of extra header's fields
+					else
+						ip_options_count_max <= 0;                                           -- else thre are no extra header's fields
+						ip_extra_options <= '0';
+					end if;
+					-- differentiated services are ignored (bits 7 to 0 of bytes00)
+				else -- refresh registers
+					unknown_request2 <= '0';
+					ip_header_length <= x"0";
+					ip_options_count_max <= 0;
+					ip_extra_options <= '0';
+				end if;
+				-- bytes01
+				if (byte_read_done(1)='1') then
+					ip_total_length <= bytes01; -- read total length of IP datagram (header+data) in bytes
+					data_counter_max <= to_integer(unsigned(bytes01))- 4*to_integer(unsigned(bytes00(11 downto 8)))-8;-- set counter for data here
+					--example: 25(=37)-4*5-8=9 (from 0 to 8) = 9 bytes of data; 8 - is the UDP header length in bytes; 4*5 - is IP header length
+					if (data_counter_max < 18) then -- 8<17 - true; if less than 18 there are zero-padded data fields
+						zero_counter <= 18-data_counter_max; -- 18-9-1=8 (from 0 to 8) = 9 bytes of zeros
+					else
+						zero_counter <= 0;
+					end if;
+				else
+					ip_total_length <= (others => '0');
+					data_counter_max <= 0;
+					zero_counter <= 0;
+				end if;
+				-- bytes02
+				if (byte_read_done(2)='1') then
+					identification <= bytes02; -- read Identification field
+				else 
+					identification <= (others => '0');
+				end if;
+				-- bytes03
+				if (byte_read_done(3)='1') then
+					flags_offset <= bytes03;   -- read Flags and Fragmentation offsets (not used in the design)
+				else 
+					flags_offset <= (others => '0');
+				end if;
+				-- bytes04
+				if (byte_read_done(4)='1') then
+					if (ip_protocol = bytes04(7 downto 0)) then -- if higher level protocol is UDP 
+						unknown_request2 <= '0';					  -- let packet pass
+					else
+						unknown_request2 <= '1';					  -- else reject it
+					end if;
+				-- Time to Live parameter is ignored (bits 15 to 8 of bytes04)
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes05
+				if (byte_read_done(5)='1') then
+					ip_header_checksum <= bytes05; -- read IP header's checksum
+				else
+					ip_header_checksum <= (others => '0');
+				end if;
+				-- bytes06, bytes07
+				if (byte_read_done(6)='1' and byte_read_done(7)='1') then
+					source_ip <= bytes06&bytes07;  -- read source IP4 address
+				else
+					source_ip <= (others => '0');
+				end if;
+				-- bytes08, bytes09
+				if (byte_read_done(8)='1' and byte_read_done(9)='1') then
+					if (fpga_ip = bytes08&bytes09) then -- if destination IP4 address = FPGA IP4 address
+						unknown_request2 <= '0';         -- let packet pass
+					else
+						unknown_request2 <= '1';			-- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes10
+				if (byte_read_done(10)='1') then
+					source_port <= bytes10; 				-- read source port number
+				else
+					source_port <= (others => '0');
+				end if;
+				-- bytes11
+				if (byte_read_done(11)='1') then
+					if (fpga_port = bytes11) then      -- if destination port number = FPGA port number
+						unknown_request2 <= '0';		  -- let packet pass
+					else
+						unknown_request2 <= '1';        -- else reject it
+					end if;
+				else
+					unknown_request2 <= '0';
+				end if;
+				-- bytes12
+				if (byte_read_done(12)='1') then
+					udp_length <= bytes12;				 -- read UDP protocol length
+				else
+					udp_length <= (others => '0');
+				end if;
+				-- bytes13
+				if (byte_read_done(13)='1') then
+					udp_checksum <= bytes13;		    -- read UDP checksum
+				else
+					udp_checksum <= (others => '0');
+				end if;
+			-- refresh headers' registers
+			else
+				unknown_request2 <= '0';
+				ip_extra_options <= '0';
+				source_ip <= (others => '0');
+				source_port <= (others => '0');
+				data_counter_max <= 0;
+				zero_counter <= 0;
+				ip_options_count_max <= 0;
+				udp_length <= (others => '0');
+				udp_checksum <= (others => '0');
+				ip_header_length <= (others => '0');
+				ip_total_length <= (others => '0');
+				ip_header_checksum <= (others => '0');
+			end if;
+	end if;
+	end process headers_parse;
+	
+	-- this process handles IP header checksum calculations, note checksum is not calculated for ARP protocol
+	ip_header_checksum_check: process (clk50mhz,byte_read_done(9),ip_header_checksum,arp_request_expected,eth_protocol_expected,
+	ip_extra_options,ip_options_count_max,ip_header_options)
+	begin
+	if (rising_edge(clk50mhz)) then
+		-- if IP4 protocol received and IP header is read and checksum hasn't been calculated, calculate it here
+		if (arp_request_expected = '0' and eth_protocol_expected = '1' and byte_read_done(9)='1' and ip_hcs_done = '0') then
+			case sip is
+				when sip1 =>
+					if (ip_extra_options = '1') then                   -- take into account IP header extra field
+						for j in 39 downto 0 loop                       -- 40-1=39 - max length of extra field in bytes
+							edge_count_header <= not(edge_count_header); -- keeps track of senior/junior byte
+							if (ip_header_options(j*8+7 downto j*8+0) = x"00") then
+								ip_hcs_calc_extra <= ip_hcs_calc_extra; 	-- find first non-zero byte here
+							else
+								if (edge_count_header = '0') then            -- senior byte was received first
+									ip_hcs_calc_extra <= ip_hcs_calc_extra+unsigned(ip_header_options(j*8+7 downto j*8+0)&x"00");
+								elsif (edge_count_header = '1') then         -- junior byte was received second
+									ip_hcs_calc_extra <= ip_hcs_calc_extra+unsigned(x"00"&ip_header_options(j*8+7 downto j*8+0));
+								end if;
+							end if;
+						end loop;
+					elsif (ip_extra_options = '0') then -- if no IP header extra options - it's just zero
+						edge_count_header <= '0';
+						ip_hcs_calc_extra <= (others => '0');
+					end if;
+					ip_hcs_calc_temp1 <= ip_hcs_calc_temp1+unsigned(bytes00)+unsigned(ip_total_length)+unsigned(identification)+
+					unsigned(flags_offset)+unsigned(bytes04)+unsigned(ip_header_checksum)+unsigned(bytes06)+
+					unsigned(bytes07)+unsigned(bytes08)+unsigned(bytes09)+ip_hcs_calc_extra; -- sum all the IP header's fields here
+					sip <= sip2;
+				when sip2 =>
+					ip_hcs_calc_temp2 <= not(ip_hcs_calc_temp2+ip_hcs_calc_temp1(15 downto 0)+ip_hcs_calc_temp1(23 downto 16)); -- add carry-out to checksum
+					sip <= sip3;
+				when sip3 =>
+					ip_hcs_calc <= std_logic_vector(ip_hcs_calc_temp2); -- complement the result
+					ip_hcs_done <= '1';											 -- set flag indicating completion of IP header checksum calculations
+					sip <= sip3;
+			end case;
+		-- if IP headers checksum has already been calculated keep the result
+		elsif (arp_request_expected = '0' and eth_protocol_expected = '1' and byte_read_done(9)='1' and ip_hcs_done = '1') then
+			ip_hcs_calc <= ip_hcs_calc;
+			ip_hcs_done <= ip_hcs_done;
+			ip_hcs_calc_temp1 <= ip_hcs_calc_temp1;
+			ip_hcs_calc_temp2 <= ip_hcs_calc_temp2;
+		else -- refresh IP headers checksum registers
+			ip_hcs_calc <= (others => '1');
+			ip_hcs_calc_temp1 <= (others => '0');
+			ip_hcs_calc_temp2 <= (others => '0');
+			ip_hcs_done <= '0';
+			sip <= sip1;
+		end if;
+		-- verify ip header checksum
+		if (ip_hcs_done = '1') then
+			if (ip_hcs_calc = x"0000") then -- if calculated checksum = 0
+				unknown_request3 <= '0';     -- let packet pass
+			else
+				unknown_request3 <= '1';     -- else reject it
+			end if;
+		else
+			unknown_request3 <= '0';
+		end if;
+	end if;
+	end process ip_header_checksum_check;
+	
+	-- this process handles UDP header checksum calculations, note checksum is not calculated for ARP protocol
+	udp_header_checksum_check: process (clk50mhz,byte_read_done(13),bytes13,arp_request_expected,eth_protocol_expected,
+	source_port,source_ip,fpga_ip,fpga_port,udp_length,temp_data,valid_data_byte_read,start_crc,stop_crc)
+	begin
+		if (rising_edge(clk50mhz)) then
+		-- if IP4 protocol received and UDP header is read and checksum hasn't been calculated, calculate it here
+			if (arp_request_expected = '0' and eth_protocol_expected = '1' and byte_read_done(13)='1' and udp_presum_done = '0') then
+				udp_presum <= udp_presum+unsigned(source_ip(31 downto 16))+unsigned(source_ip(15 downto 0))+unsigned(fpga_ip(31 downto 16))+
+				unsigned(fpga_ip(15 downto 0))+unsigned(x"00"&ip_protocol)+unsigned(udp_length)+unsigned(source_port)+unsigned(fpga_port)+
+				unsigned(udp_length)+unsigned(bytes13); -- presum calculates the first summand of UDP checksum comprising only header's fields
+				udp_presum_done <= '1';						 -- flag indicating the presum was calculated
+			-- maintain presum value once it was calculated
+			elsif (arp_request_expected = '0' and eth_protocol_expected = '1' and byte_read_done(13)='1' and udp_presum_done = '1') then
+				udp_presum <= udp_presum;
+				udp_presum_done <= udp_presum_done;
+			else -- reset presum here
+				udp_presum <= (others => '0');
+				udp_presum_done <= '0';
+			end if;
+			-- the second summand of UDP checksum, conmprising data fields, is calculated here 
+			if (valid_data_byte_read='1' and start_crc ='1' and stop_crc ='0') then -- once valid data byte was read and this is not the last data byte
+				edge_count_data <= not(edge_count_data); 										-- add it to the second checksum summand
+				if (edge_count_data = '0') then                                      -- edge count controls format of addition
+					udp_data_sum <= udp_data_sum+unsigned(temp_data&x"00");
+				elsif (edge_count_data = '1') then
+					udp_data_sum <= udp_data_sum+unsigned(x"00"&temp_data);
+				end if;
+			elsif (valid_data_byte_read='0' and start_crc ='1' and stop_crc ='0') then
+				edge_count_data <= edge_count_data;
+				udp_data_sum <= udp_data_sum;
+			elsif (start_crc ='0' and stop_crc ='0') then -- these flags defines the start of crc field on receive
+				edge_count_data <= '0';
+				udp_data_sum <= udp_data_sum;
+				udp_datasum_done <= '1';						 -- calculation of the second summand is over
+			elsif (stop_crc ='1') then							 -- refresh the second summand's register
+				edge_count_data <= '0';
+				udp_data_sum <= (others => '0');
+				udp_datasum_done <= '0';
+			end if;
+			if (udp_presum_done = '1' and udp_datasum_done = '1' and udp_hcs_done = '0') then -- if both summands are calculated find checksum
+				case sudp is
+					when sudp1 =>
+						udp_hcs_calc_temp1 <= udp_presum+udp_data_sum; 									 -- add 2 summand together
+						sudp <= sudp2;
+					when sudp2 =>
+						udp_hcs_calc_temp2 <= not(udp_hcs_calc_temp2+udp_hcs_calc_temp1(15 downto 0)+udp_hcs_calc_temp1(23 downto 16)); -- add carry-out
+						sudp <= sudp3;
+					when sudp3 =>
+						udp_hcs_calc <= std_logic_vector(udp_hcs_calc_temp2);							 -- find checksum
+						udp_hcs_done <= '1';																		 -- set flag
+						sudp <= sudp3;
+				end case;
+			elsif (udp_presum_done = '1' and udp_datasum_done = '1' and udp_hcs_done = '1') then -- maintain calculated checksum value
+				udp_hcs_calc_temp1 <= udp_hcs_calc_temp1;
+				udp_hcs_calc_temp2 <= udp_hcs_calc_temp2;
+				udp_hcs_calc <= udp_hcs_calc;
+				udp_hcs_done <= udp_hcs_done;
+			else -- refresh UDP checksum registers
+				udp_hcs_calc_temp1 <= (others => '0');
+				udp_hcs_calc_temp2 <= (others => '0');
+				udp_hcs_calc <= (others => '1');
+				udp_hcs_done <= '0';
+				sudp <= sudp1;
+			end if;
+			if (udp_hcs_done = '1') then
+				if (udp_hcs_calc = x"0000") then -- if calculated checksum = 0
+					unknown_request4 <= '0';		-- let packet pass
+				else
+					unknown_request4 <= '1';		-- else reject it
+				end if;
+			else
+				unknown_request4 <= '0';
+			end if;
+		end if;
+	end process udp_header_checksum_check;
+	
+	-- this process transfers data to transmitter for reply
+	data_out: process (crc_pass,read_frame_done,source_mac,source_ip,source_port,arp_request_expected,eth_protocol_expected,clk50mhz)
+	begin
+	if(rising_edge(clk50mhz)) then
+		if (crc_pass = '1') then -- if data packet passed crc check and it's a valid packet
+			-- pass data required to assemble Tx packet to transmitter
+			pc_mac <= source_mac;   			 -- PC's MAC address
+			pc_ip <= source_ip;     			 -- PC's IP4 address
+			
+			datacm <= std_logic_vector(to_signed(data_counter_max, ADDR_WIDTH+1)); -- length of the data field
+			udpl <= udp_length;    				 -- UDP header+data length
+			udpc <= udp_checksum;   			 -- UDP checksum (same for Rx and Tx, since it's an echo server)
+			data_out_valid <= '1';
+			if (arp_request_expected = '1') then
+				send_arp_reply <= '1';			 -- tell Tx to send ARP reply if ARP request was received
+				send_ethernet_protocol <= '0';
+			elsif (eth_protocol_expected = '1') then
+				send_arp_reply <= '0';
+				send_ethernet_protocol <= '1'; -- tell Tx to send UDP packet if UDP packet was received
+				pc_port <= source_port; 			 -- PC's port number
+			else 										 -- no valid packet has been received, no reply will be sent
+				send_arp_reply <= '0';
+				send_ethernet_protocol <= '0';
+			end if;
+		else -- until the received packet passes crc check no data transferred to transmitter
+			--pc_mac <= (others => '0');
+			--pc_ip <= (others => '0');
+			--pc_port <= (others => '0');
+			datacm <= (others => '0');
+			udpl <= (others => '0');
+			udpc <= (others => '0');
+			data_out_valid <= '0';
+			send_arp_reply <= '0';
+			send_ethernet_protocol <= '0';
+		end if;
+	end if;
+	end process data_out;
+	
+	-- this process takes care of saving received data to RAM
+	data_out_ram: process (clk50mhz,temp_data,valid_data_byte_read,addr_count,read_frame_done,data_to_ram,we_ram,rst_ram)
+	begin -- don't forget to reset ram if invalid signal
+		if(rising_edge(clk50mhz)) then
+		    if(state = idle) then
+		      is_idle <= '1';
+		    else
+		      is_idle <= '0';
+		    end if;
+			case s_ram is
+				when s_ram1 =>
+					if (valid_data_byte_read = '1') then -- if valid data byte was read write it to RAM
+						data_to_ram <= temp_data;
+						we_ram <= '1';
+						s_ram <= s_ram3;
+					elsif (read_frame_done = '1' or rst_ram = '1') then -- at the end of the frame or in case of error reset RAM's signals
+						data_to_ram <= (others => '0');
+						addr_count <= (others => '0');
+						we_ram <= '0';
+						s_ram <= s_ram4;
+					else
+						data_to_ram <= data_to_ram;
+						addr_count <= addr_count;
+						we_ram <= '0';
+						s_ram <= s_ram1;
+					end if;
+				when s_ram2 =>
+					data_to_ram <= data_to_ram;
+					we_ram <= '1';
+					addr_count <= addr_count;
+					s_ram <= s_ram3;
+				when s_ram3 =>
+					data_to_ram <= data_to_ram;
+					we_ram <= '0';
+					if (addr_count+1 > 2**ADDR_WIDTH-1) then
+						addr_count <= (others => '0');
+					else
+						addr_count <= addr_count+1;
+					end if;
+					s_ram <= s_ram1;
+				when s_ram4 =>
+					data_to_ram <= (others => '0');
+					addr_count <= (others => '0');
+					we_ram <= '0';
+					s_ram <= s_ram1;
+				end case;
+		end if;
+		-- attach RAM signals to RAM ports
+		wrt_data_ram <= data_to_ram;
+		wrt_addr_ram <= std_logic_vector(addr_count);
+		wrt_enable_ram <= we_ram;
+	end process data_out_ram;
+
+unknown_request <= unknown_request1 or unknown_request2 or unknown_request3 or unknown_request4; -- all flags indicating invalid packet formats are ORed here
+
+end Behavioral;
+

ip_repo_sources/UDP_echo-server/src/eth_transmitter.vhd

@@ -0,0 +1,678 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov 
+-- 
+-- Create Date:    15:13:44 02/24/2017 
+-- Design Name: 
+-- Module Name:    eth_transmitter - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- Ethernet transmitter module hadles transmission of data packets back to the data
+-- server and performs all necessary operations, related to packet assembly, based
+-- on the data passed from receiver. It includes 4 processes and 1 sub-module:
+-- - process to write data out;
+-- - process to receive data from Receiver module;
+-- - process to create protocol headers (Ethernet, ARP, IP4, UDP) for the packet to be transmitted;
+-- - process for IP header checksum calculations;
+-- - sub-module for crc calculations;
+-- Data to be trasnmitted is retrieved from RAM block by the main Transmit process.
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_unsigned.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity eth_transmitter is
+	 Generic (ADDR_WIDTH : integer;
+				 DATA_WIDTH : integer);
+    Port ( clk100mhz : in  STD_LOGIC;     -- clock for crc calculator
+			  clk50mhz_shift : in STD_LOGIC; -- provides required set-up and hold time for TX signals with respect to reference clock
+			  rstn : in STD_LOGIC;
+           txd : inout  STD_LOGIC_VECTOR (1 downto 0);
+           txen : out  STD_LOGIC;
+			  -- RAM signals
+			  rd_data_fifo : in STD_LOGIC_VECTOR (31 downto 0);
+			  rd_enable_fifo : out STD_LOGIC;
+			  -- Addresses
+			  fpga_mac : in STD_LOGIC_VECTOR (47 downto 0);
+			  fpga_ip : in STD_LOGIC_VECTOR (31 downto 0);
+			  fpga_port : in STD_LOGIC_VECTOR (15 downto 0);
+			  pc_mac : in STD_LOGIC_VECTOR (47 downto 0);
+			  pc_ip : in  STD_LOGIC_VECTOR (31 downto 0);
+			  pc_port : in STD_LOGIC_VECTOR (15 downto 0);
+			  -- Data from Rx
+			  datacm : in STD_LOGIC_VECTOR (ADDR_WIDTH downto 0);
+			  udpl : in STD_LOGIC_VECTOR (15 downto 0);
+			  udpc : in STD_LOGIC_VECTOR (15 downto 0);
+			  send_arp_reply : in STD_LOGIC;
+			  send_ethernet_protocol: in STD_LOGIC;
+			  data_in_valid : in STD_LOGIC;
+			  
+			  datacm_r :out integer range 0 to 1472 := 0;
+			  sent_arp_response : out std_logic;
+			  is_idle : out std_logic);
+end eth_transmitter;
+
+architecture Behavioral of eth_transmitter is
+-- SIGNALS
+-- ******* process transmit (responsible for handling Tx) ********--
+type state_type is (idle, tx_preamble, tx_sfd, tx_eth_frame_header, tx_protocol_header, tx_data, tx_zero_padding, tx_crc);
+signal state : state_type := idle;
+signal bit_count : integer range 0 to 15 := 0;								-- counts number of nibbles transmitted
+signal byte_count : integer range 0 to 1499 := 0;							-- counts number of bytes transmitted
+constant preamble : std_logic_vector (7 downto 0) := x"55";          -- preamble
+constant sfd : std_logic_vector (7 downto 0) := x"d5";               -- SFD
+signal dest_mac : std_logic_vector (47 downto 0) := (others => '0'); -- destination MAC address
+signal dest_ip : std_logic_vector (31 downto 0) := (others => '0');  -- destination IP4 address
+signal dest_port : std_logic_vector (15 downto 0) := (others => '0');-- destination Mport number
+signal eth_type : std_logic_vector(15 downto 0) := (others => '0');  -- upper layer type of protocol
+signal byte0, byte1, byte2, byte3, byte4, byte5, byte6, byte7, byte8,
+byte9, byte10, byte11, byte12, byte13, byte14, byte15, byte16, byte17, byte18,
+byte19, byte20, byte21, byte22, byte23, byte24, byte25, byte26, byte27 : std_logic_vector (7 downto 0);-- registers to store parsed headers
+signal data_counter_max : integer range 0 to 1472 := 0; -- defines length of data field in bytes without zero padding
+signal zero_counter : integer range 0 to 18 := 0;       -- defines length of zero-padded data field
+signal start_crc : std_logic := '0'; -- enable crc calculator 
+signal stop_crc : std_logic := '0';  -- reset crc calculator
+signal tx_ready : std_logic := '0';  -- flag indicating that packet is ready for transmission
+signal temp_data : std_logic_vector(31 downto 0) := (others => '0');
+signal tx_done : std_logic := '0';   -- flag indicating completion of packet transmission 
+signal crc_calculated : std_logic_vector (31 downto 0) := (others => '0'); -- calculated crc value for packet being transmitted
+-- ******* process set_tx_format (responsible for setting format of the packet to be transmitted) ********--
+signal arp_reply : std_logic := '0';    -- sets ARP as higher layer protocol
+signal eth_protocol : std_logic := '0'; -- flag sets IP as higher layer protocol       
+signal ip_total_length : std_logic_vector (15 downto 0) := (others => '0'); -- stores IP header+data length in bytes (from receiver)
+signal udp_length :std_logic_vector (15 downto 0) := (others => '0');       -- stores UDP header+data length in bytes (from receiver)
+signal udp_checksum : std_logic_vector (15 downto 0) := (others => '0');    -- stores UDP checksum value (from receiver)
+signal id_counter : unsigned (15 downto 0) := (others => '0');              -- Identification parameter for the outgoing packet
+-- ******* process ip_header_checksum_calc (responsible for IP header checksum calculation) ********--
+signal ip_header_checksum : std_logic_vector (15 downto 0) := (others => '0'); -- calculated IP header checksum
+signal temp_iphc1 : unsigned (23 downto 0) := (others => '0');	-- sum of all header's fields
+signal temp_iphc2 : unsigned (15 downto 0) := (others => '0');	-- sum of the carry-out with main checksum body
+signal ip_header_calc_done : std_logic := '0';						-- flag set when checksum calculation completed
+type s_type is (s1,s2,s3);													-- states of the IP header's checksum FSM
+signal s : s_type := s1;
+-- ******* constants for process set_tx_data (responsible for setting registers storing parsed headers) ********--
+constant ip_version : std_logic_vector (3 downto 0) := "0100";       -- code for IP version = 4 
+constant ip_header_length : std_logic_vector (3 downto 0) := "0101"; -- code for IP header length = 5 -> 20 bytes 
+constant ipl : unsigned (15 downto 0) := x"0014";                      -- IP header length - fixed = 20 bytes
+constant flags_offset : std_logic_vector (15 downto 0) := x"0000";   -- flags, offsets and fragmentation
+constant ttl : std_logic_vector (7 downto 0) := x"80";               -- time to live for the datagram
+constant ds : std_logic_vector (7 downto 0) := x"00";                -- differentiated services
+constant ip_protocol : std_logic_vector (7 downto 0) := x"11";       -- code of UDP protocol type
+constant arp_operation : std_logic_vector(15 downto 0) := x"0002";   -- code of ARP reply operation
+constant arp_hw_type : std_logic_vector (15 downto 0) := x"0001";    -- code of ARP hardware type
+constant arp_protocol_type : std_logic_vector (15 downto 0) := x"0800"; -- code of protocol type (IP4)
+constant arp_hw_length : std_logic_vector (7 downto 0) := x"06"; 			-- code of ARP hardware length
+constant arp_protocol_length : std_logic_vector (7 downto 0) := x"04";  -- code of ARP protocol length
+constant arp : std_logic_vector (15 downto 0) := x"0806"; 					-- code of ARP protocol type
+constant ethernet : std_logic_vector (15 downto 0) := x"0800";				-- code of IP4 protocol type
+
+-- CRC checker declaration
+component crc32_parallel
+			 port (clk100mhz : in  STD_LOGIC;
+					 data_valid : in  STD_LOGIC;
+					 data_in : in  STD_LOGIC_VECTOR (1 downto 0);
+					 rstn : in STD_LOGIC;
+					 crc : inout  STD_LOGIC_VECTOR (31 downto 0));
+end component;
+
+begin
+-- CRC checker instantiation
+crc_calculator: crc32_parallel
+					 port map (clk100mhz => clk100mhz,
+								  data_valid => start_crc,
+								  data_in => txd,
+								  rstn => stop_crc,
+								  crc => crc_calculated);
+
+	transmit: process (clk50mhz_shift,rstn)
+	begin
+		if (rstn = '0') then -- if transciever is being reset transmitter becomes idle
+			id_counter <= (others => '0'); -- reset ID counter on hardware reset
+			state <= idle;
+		elsif (rising_edge(clk50mhz_shift)) then
+			case state is
+			
+			-- Idle state all Tx flags and registers reset and Tx waits until 
+			-- tx_ready signal is asserted 
+			when idle =>
+				bit_count <= 0;
+				byte_count <= 0;
+				tx_done <= '0';
+				start_crc <= '0';
+				stop_crc <= '1';
+				txen <= '0';
+				txd <= "00";
+				if (tx_ready = '0') then
+					txen <= '0';
+					rd_enable_fifo <= '0';
+					state <= idle;
+				elsif (tx_ready = '1') then -- if tx_ready flag is set start transmission
+					txen <= '1';
+					txd <= preamble(2*bit_count+1 downto 2*bit_count);
+					-- if IP/UDP protocol is to be transmitted pre-read the first data byte from RAM
+					if (eth_protocol = '1') then
+						rd_enable_fifo <= '1'; -- enable read
+					else -- if ARP protocol, there is no data to be transmtted 
+						rd_enable_fifo <= '0';
+					end if;
+					--
+					byte_count <= 0;
+					bit_count <= bit_count+1;
+					state <= tx_preamble;
+				end if;
+			
+			-- this state transmits preamble
+			when tx_preamble =>
+				txen <= '1';
+				-- if IP/UDP protocol is to be transmitted pre-read the first data byte from RAM
+				if (eth_protocol = '1') then
+					--temp_data <= rd_data_fifo; 		  -- read data byte from RAM
+					rd_enable_fifo <= '0';           -- disable read operation from RAM
+				else -- if ARP protocol, there is no data to be transmtted 
+					--temp_data <= (others => '0');
+					rd_enable_fifo <= '0';
+				end if;
+				--
+				tx_done <= '0';
+				if (byte_count <= 6 and bit_count < 3) then
+					txd <= preamble(2*bit_count+1 downto 2*bit_count);
+					bit_count <= bit_count+1;
+					state <= tx_preamble;
+				elsif (byte_count <= 6 and bit_count = 3) then
+					txd <= preamble(2*bit_count+1 downto 2*bit_count);
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_preamble;
+				elsif (byte_count = 7) then
+						txd <= sfd(2*bit_count+1 downto 2*bit_count);
+						bit_count <= bit_count+1;
+						byte_count <= 0;
+						state <= tx_sfd;
+				end if;
+			
+			-- this state transmits SFD
+			when tx_sfd =>
+				txen <= '1';
+				tx_done <= '0';
+				-- if IP/UDP protocol is to be transmitted pre-read the first data byte from RAM
+				if (eth_protocol = '1') then
+					--temp_data <= rd_data_fifo;
+					rd_enable_fifo <= '0';
+				else -- if ARP protocol, there is no data to be transmtted 
+					--temp_data <= (others => '0');
+					rd_enable_fifo <= '0';
+				end if;
+				--
+				if (byte_count = 0 and bit_count < 3) then
+					txd <= sfd(2*bit_count+1 downto 2*bit_count);
+					bit_count <= bit_count+1;
+					state <= tx_sfd;
+				elsif (byte_count = 0 and bit_count = 3) then
+					txd <= sfd(2*bit_count+1 downto 2*bit_count);
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_sfd;
+				elsif (byte_count = 1) then
+					byte_count <= 0;
+					txd <= dest_mac((5-0)*8+2*bit_count+1 downto (5-0)*8+2*bit_count);
+					bit_count <= bit_count+1;
+					start_crc <= '1';
+					stop_crc <= '0';
+					state <= tx_eth_frame_header;
+				end if;
+			
+			-- this state transmits Ethernet frame header (destination and source MAC addresses and upper layer protocol type)
+			when tx_eth_frame_header =>
+				txen <= '1';
+				tx_done <= '0';
+				-- if IP/UDP protocol is to be transmitted pre-read the first data byte from RAM
+				if (eth_protocol = '1') then
+					--temp_data <= rd_data_fifo;
+					rd_enable_fifo <= '0';
+				else -- if ARP protocol, there is no data to be transmtted 
+					--temp_data <= (others => '0');
+					rd_enable_fifo <= '0';
+				end if;
+				-- destination MAC transmitted
+				if (byte_count <= 5 and bit_count < 3) then
+					txd <= dest_mac((5-byte_count)*8+2*bit_count+1 downto (5-byte_count)*8+2*bit_count);
+					bit_count <= bit_count+1;
+					state <= tx_eth_frame_header;
+				elsif (byte_count <= 5 and bit_count = 3) then
+					txd <= dest_mac((5-byte_count)*8+2*bit_count+1 downto (5-byte_count)*8+2*bit_count);
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_eth_frame_header;
+				-- source MAC transmitted
+				elsif (byte_count > 5 and byte_count <= 11 and bit_count < 3) then
+					txd <= fpga_mac((11-byte_count)*8+2*bit_count+1 downto (11-byte_count)*8+2*bit_count);
+					bit_count <= bit_count+1;
+					state <= tx_eth_frame_header;
+				elsif (byte_count > 5 and byte_count <= 11 and bit_count = 3) then
+					txd <= fpga_mac((11-byte_count)*8+2*bit_count+1 downto (11-byte_count)*8+2*bit_count);
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_eth_frame_header;
+				-- upper layer protocol type transmitted
+				elsif (byte_count > 11 and byte_count <= 13 and bit_count < 3) then
+					txd <= eth_type((13-byte_count)*8+2*bit_count+1 downto (13-byte_count)*8+2*bit_count);
+					bit_count <= bit_count+1;
+					state <= tx_eth_frame_header;
+				elsif (byte_count > 11 and byte_count <= 13 and bit_count = 3) then
+					txd <= eth_type((13-byte_count)*8+2*bit_count+1 downto (13-byte_count)*8+2*bit_count);
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_eth_frame_header;
+				elsif (byte_count = 14) then
+						txd <= byte0(2*bit_count+1 downto 2*bit_count);
+						bit_count <= bit_count+1;
+						byte_count <= 0;
+						state <= tx_protocol_header;
+				end if;
+			
+			-- this state transmits ARP or IP/UDP protocol headers
+			when tx_protocol_header =>
+				txen <= '1';
+				tx_done <= '0';
+				-- if IP/UDP protocol is to be transmitted pre-read the first data byte from RAM
+				if (eth_protocol = '1') then
+					--temp_data <= rd_data_fifo;
+					rd_enable_fifo <= '0';
+				else -- if ARP protocol, there is no data to be transmtted
+					--temp_data <= (others => '0');
+					rd_enable_fifo <= '0';
+				end if;
+				--
+				if (byte_count <= 27 and bit_count < 3) then
+					bit_count <= bit_count+1;
+					state <= tx_protocol_header;
+				elsif (byte_count <= 27 and bit_count = 3) then
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_protocol_header;
+				elsif (byte_count = 28 and data_counter_max = 0) then -- if there is no data to transmit, transmit zero-padding
+						bit_count <= bit_count+1;
+						byte_count <= 0;
+						state <= tx_zero_padding;
+				elsif (byte_count = 28 and data_counter_max > 0) then -- if there is data to transmit, transmit data
+						byte_count <= 0;
+						bit_count <= bit_count+1;
+						state <= tx_data;
+				end if;
+				case byte_count is
+					when 0 => txd <= byte0(2*bit_count+1 downto 2*bit_count);
+					when 1 => txd <= byte1(2*bit_count+1 downto 2*bit_count);
+					when 2 => txd <= byte2(2*bit_count+1 downto 2*bit_count);
+					when 3 => txd <= byte3(2*bit_count+1 downto 2*bit_count);
+					when 4 => txd <= byte4(2*bit_count+1 downto 2*bit_count);
+					when 5 => txd <= byte5(2*bit_count+1 downto 2*bit_count);
+					when 6 => txd <= byte6(2*bit_count+1 downto 2*bit_count);
+					when 7 => txd <= byte7(2*bit_count+1 downto 2*bit_count);
+					when 8 => txd <= byte8(2*bit_count+1 downto 2*bit_count);
+					when 9 => txd <= byte9(2*bit_count+1 downto 2*bit_count);
+					when 10 => txd <= byte10(2*bit_count+1 downto 2*bit_count);
+					when 11 => txd <= byte11(2*bit_count+1 downto 2*bit_count);
+					when 12 => txd <= byte12(2*bit_count+1 downto 2*bit_count);
+					when 13 => txd <= byte13(2*bit_count+1 downto 2*bit_count);
+					when 14 => txd <= byte14(2*bit_count+1 downto 2*bit_count);
+					when 15 => txd <= byte15(2*bit_count+1 downto 2*bit_count);
+					when 16 => txd <= byte16(2*bit_count+1 downto 2*bit_count);
+					when 17 => txd <= byte17(2*bit_count+1 downto 2*bit_count);
+					when 18 => txd <= byte18(2*bit_count+1 downto 2*bit_count);
+					when 19 => txd <= byte19(2*bit_count+1 downto 2*bit_count);
+					when 20 => txd <= byte20(2*bit_count+1 downto 2*bit_count);
+					when 21 => txd <= byte21(2*bit_count+1 downto 2*bit_count);
+					when 22 => txd <= byte22(2*bit_count+1 downto 2*bit_count);
+					when 23 => txd <= byte23(2*bit_count+1 downto 2*bit_count);
+					when 24 => txd <= byte24(2*bit_count+1 downto 2*bit_count);
+					when 25 => txd <= byte25(2*bit_count+1 downto 2*bit_count);
+					when 26 => txd <= byte26(2*bit_count+1 downto 2*bit_count);
+					when 27 => txd <= byte27(2*bit_count+1 downto 2*bit_count);
+					when others => 
+						if (data_counter_max = 0) then
+							txd <= "00"; -- preload zeros to Tx bus for zero-padding transmission
+						elsif (data_counter_max > 0) then
+							txd <= temp_data(2*bit_count+1 downto 2*bit_count); -- preload data to Tx bus for data transmission
+						end if;
+				end case;
+			
+			-- this state transmits data
+			when tx_data =>
+				txen <= '1';
+				tx_done <= '0';
+				if (byte_count <= data_counter_max-1 and bit_count < 15) then
+					txd <= temp_data(2*bit_count+1 downto 2*bit_count);
+					bit_count <= bit_count+1;
+					-- keep read RAM enabled and have the address to read on the bus
+					rd_enable_fifo <= '0';
+					--
+					state <= tx_data;
+				elsif (byte_count <= data_counter_max-1 and bit_count = 15) then
+					txd <= temp_data(2*bit_count+1 downto 2*bit_count);
+					-- read the next data byte from RAM when the previous is transmitted
+					if(byte_count+4 <= data_counter_max-1) then
+					   rd_enable_fifo <= '1';
+					else
+					   rd_enable_fifo <= '0';
+					end if;
+					--
+					bit_count <= 0;
+					byte_count <= byte_count+4;
+					state <= tx_data;
+				elsif (byte_count > data_counter_max-1 and zero_counter = 0) then -- if no zero-padding required
+					txd(0) <= crc_calculated((3-0)*8+(3-bit_count)*2+1); -- preload crc values on Tx bus
+					txd(1) <= crc_calculated((3-0)*8+(3-bit_count)*2);   -- and start crc transmission
+					-- when all the data was transmitted disable read from RAM operation and clear the RAM signals
+					--temp_data <= (others => '0');
+					rd_enable_fifo <= '0';
+					--
+					start_crc <= '0'; -- stop crc calculation 
+					stop_crc <= '0';
+					bit_count <= bit_count+1;
+					byte_count <= 0;
+					state <= tx_crc;
+				elsif (byte_count > data_counter_max-1 and zero_counter > 0) then -- if zero-padding required
+					txd <= "00"; -- preload zeros to Tx bus
+					-- disable read from RAM operation and clear the RAM signals
+					--temp_data <= (others => '0');
+					rd_enable_fifo <= '0';
+					--
+					byte_count <= 0;
+					bit_count <= bit_count+1;
+					state <= tx_zero_padding;
+				end if;
+			
+			-- this state transmits zero-padded data field
+			when tx_zero_padding =>
+				txen <= '1';
+				tx_done <= '0';
+				if (byte_count <= zero_counter-1 and bit_count < 3) then
+					txd <= "00";
+					bit_count <= bit_count+1;
+					state <= tx_zero_padding;
+				elsif (byte_count <= zero_counter-1 and bit_count = 3) then
+					txd <= "00";
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_zero_padding;
+				elsif (byte_count+1 > zero_counter-1) then -- when required amount of zero-padding was transmitted
+					txd(0) <= crc_calculated((3-0)*8+(3-bit_count)*2+1); -- preload crc values on Tx bus
+					txd(1) <= crc_calculated((3-0)*8+(3-bit_count)*2);   -- and start crc transmission
+					byte_count <= 0;
+					bit_count <= bit_count+1;
+					start_crc <= '0'; -- stop crc calculation
+					stop_crc <= '0';
+					state <= tx_crc;
+				end if;
+			
+			-- this state transmits calculated crc value
+			when tx_crc =>
+				txen <= '1';
+				tx_done <= '0';
+				if (byte_count <= 3 and bit_count < 3) then
+					txd(0) <= crc_calculated((3-byte_count)*8+(3-bit_count)*2+1);
+					txd(1) <= crc_calculated((3-byte_count)*8+(3-bit_count)*2);
+					bit_count <= bit_count+1;
+					state <= tx_crc;
+				elsif (byte_count <= 3 and bit_count = 3) then
+					txd(0) <= crc_calculated((3-byte_count)*8+(3-bit_count)*2+1);
+					txd(1) <= crc_calculated((3-byte_count)*8+(3-bit_count)*2);
+					bit_count <= 0;
+					byte_count <= byte_count+1;
+					state <= tx_crc;
+				elsif (byte_count > 3) then
+					byte_count <= 0;
+					tx_done <= '1'; -- if crc was transmitted - this is the end of the packet, go back to idle state
+					txen <= '0';
+					txd <= "00";
+					-- make sure that no overflow of the ID parameter happens
+					if (eth_protocol = '1' and id_counter+1 <= 65536) then
+						id_counter <= id_counter+1;
+					elsif (eth_protocol = '1' and id_counter+1 > 65536) then
+						id_counter <= (others => '0');
+					else 
+						id_counter <= id_counter;
+					end if;
+					state <= idle;
+				end if;
+			
+			
+			end case;
+		end if;
+	end process transmit;
+	
+	-- this process receives data from Rx module and determines protocol type of the next packet to be transmitted
+	set_tx_format: process (send_arp_reply,send_ethernet_protocol,data_in_valid,pc_mac,pc_ip,pc_port,tx_done,clk50mhz_shift,datacm,udpc)
+	begin
+		if (falling_edge(clk50mhz_shift)) then
+			-- set registers when there is valid data from Receiver
+			sent_arp_response <= '0';
+			if (data_in_valid = '1' and tx_done = '0') then
+				if (send_arp_reply = '1') then
+					arp_reply <= '1';
+				elsif (send_ethernet_protocol = '1') then
+					eth_protocol <= '1';
+				end if;
+				dest_mac <= pc_mac;
+				dest_ip <= pc_ip;
+				dest_port <= pc_port;
+				data_counter_max <= to_integer(unsigned(datacm));
+				ip_total_length <= std_logic_vector(ipl+unsigned(udpl));
+				udp_length <= udpl;
+				udp_checksum <= udpc;
+			-- keep value of these registers until packet is transmitted 
+			elsif (data_in_valid = '0' and tx_done = '0') then
+				arp_reply <= arp_reply;
+				eth_protocol <= eth_protocol;
+				dest_mac <= dest_mac;
+				dest_ip <= dest_ip;
+				dest_port <= dest_port;
+				data_counter_max <= data_counter_max;
+				ip_total_length <= ip_total_length;
+				udp_length <= udp_length;
+				udp_checksum <= udp_checksum;
+			-- when the packet is transmitted, clear registers
+			elsif (tx_done = '1') then
+			    sent_arp_response <= arp_reply;
+				arp_reply <= '0';
+				eth_protocol <= '0';
+				dest_mac <= (others => '0');
+				dest_ip <= (others => '0');
+				dest_port <= (others => '0');
+				data_counter_max <= 0;
+				ip_total_length <= (others => '0');
+				udp_length <= (others => '0');
+				udp_checksum <= (others => '0');
+			end if;
+		end if;
+	end process set_tx_format;
+	
+	-- this process assembles headers of the data packet to be transmitted
+	set_tx_data: process (arp_reply,eth_protocol,tx_done,clk50mhz_shift,ip_header_checksum)
+	begin
+		if (falling_edge(clk50mhz_shift)) then
+		    if(state = idle) then
+		      is_idle <= '1';
+		    else
+		      is_idle <= '0';
+		    end if;
+		    
+			-- if ARP reply required load headers registers and set data and zero counters accordingly
+			if (arp_reply = '1' and tx_done = '0') then
+				eth_type <= arp;
+				byte0 <= arp_hw_type(15 downto 8);
+				byte1 <= arp_hw_type(7 downto 0);
+				byte2 <= arp_protocol_type(15 downto 8);
+				byte3 <= arp_protocol_type(7 downto 0);
+				byte4 <= arp_hw_length;
+				byte5 <= arp_protocol_length;
+				byte6 <= arp_operation(15 downto 8);
+				byte7 <= arp_operation(7 downto 0);
+				byte8 <= fpga_mac(47 downto 40);
+				byte9 <= fpga_mac(39 downto 32);
+				byte10 <= fpga_mac(31 downto 24);
+				byte11 <= fpga_mac(23 downto 16);
+				byte12 <= fpga_mac(15 downto 8);
+				byte13 <= fpga_mac(7 downto 0);
+				byte14 <= fpga_ip(31 downto 24);
+				byte15 <= fpga_ip(23 downto 16);
+				byte16 <= fpga_ip(15 downto 8);
+				byte17 <= fpga_ip(7 downto 0);
+				byte18 <= dest_mac(47 downto 40);
+				byte19 <= dest_mac(39 downto 32);
+				byte20 <= dest_mac(31 downto 24);
+				byte21 <= dest_mac(23 downto 16);
+				byte22 <= dest_mac(15 downto 8);
+				byte23 <= dest_mac(7 downto 0);
+				byte24 <= dest_ip(31 downto 24);
+				byte25 <= dest_ip(23 downto 16);
+				byte26 <= dest_ip(15 downto 8);
+				byte27 <= dest_ip(7 downto 0);
+				--data_counter_max <= 0; -- arp request has 18 bytes of zero padding
+				zero_counter <= 18;
+				tx_ready <= '1';-- set flag indicating start of transmission
+			-- if IP/UDP reply required load headers registers and set data and zero counters accordingly
+			elsif (eth_protocol = '1' and tx_done = '0') then
+				eth_type <= ethernet;
+				byte0 <= ip_version&ip_header_length;
+				byte1 <= ds; -- differentiated services
+				-- total length of protocol in bytes
+				byte2 <= ip_total_length(15 downto 8);
+				byte3 <= ip_total_length(7 downto 0);
+				-- identification: number of package
+				byte4 <= std_logic_vector(id_counter(15 downto 8));
+				byte5 <= std_logic_vector(id_counter(7 downto 0));
+				byte6 <= flags_offset(15 downto 8); -- flags and 5 seniour bits from fragmentation offset
+				byte7 <= flags_offset(7 downto 0); -- 8 juniour bits from fragmentation offset
+				byte8 <= ttl; -- Time To Live
+				byte9 <= ip_protocol; -- x"11" - for UDP
+				-- header checksum (from process )
+				byte10 <= ip_header_checksum(15 downto 8);
+				byte11 <= ip_header_checksum(7 downto 0);
+				-- source ip
+				byte12 <= fpga_ip(31 downto 24);
+				byte13 <= fpga_ip(23 downto 16);
+				byte14 <= fpga_ip(15 downto 8);
+				byte15 <= fpga_ip(7 downto 0);
+				-- destination ip
+				byte16 <= dest_ip(31 downto 24);
+				byte17 <= dest_ip(23 downto 16);
+				byte18 <= dest_ip(15 downto 8);
+				byte19 <= dest_ip(7 downto 0);
+				-- source port
+				byte20 <= fpga_port(15 downto 8);
+				byte21 <= fpga_port(7 downto 0);
+				-- destination port
+				byte22 <= dest_port(15 downto 8);
+				byte23 <= dest_port(7 downto 0);
+				-- udp length
+				byte24 <= udp_length(15 downto 8);
+				byte25 <= udp_length(7 downto 0);
+				-- udp_checksum
+				byte26 <= udp_checksum(15 downto 8);
+				byte27 <= udp_checksum(7 downto 0);
+				-- counters and flags
+				--data_counter_max <= to_integer(unsigned(datacm));
+				if (data_counter_max < 18) then -- 4<=18 - true
+					zero_counter <= 18-data_counter_max; -- 18-4-1=13 (from 0 to 13) = 14 bytes of zeros
+				else
+					zero_counter <= 0;-- if data_counter_max=20 -> data_counter=19 (from 0 to 19) = 20 bytes of data
+				end if;
+				tx_ready <= '1'; -- set flag indicating start of transmission
+			else -- if there is nothing to transmit keep all registers and counters clear
+				tx_ready <= '0';
+				eth_type <= (others => '0');
+				byte0 <= (others => '0');
+				byte1 <= (others => '0');
+				byte2 <= (others => '0');
+				byte3 <= (others => '0');
+				byte4 <= (others => '0');
+				byte5 <= (others => '0');
+				byte6 <= (others => '0');
+				byte7 <= (others => '0');
+				byte8 <= (others => '0');
+				byte9 <= (others => '0');
+				byte10 <= (others => '0');
+				byte11 <= (others => '0');
+				byte12 <= (others => '0');
+				byte13 <= (others => '0');
+				byte14 <= (others => '0');
+				byte15 <= (others => '0');
+				byte16 <= (others => '0');
+				byte17 <= (others => '0');
+				byte18 <= (others => '0');
+				byte19 <= (others => '0');
+				byte20 <= (others => '0');
+				byte21 <= (others => '0');
+				byte22 <= (others => '0');
+				byte23 <= (others => '0');
+				byte24 <= (others => '0');
+				byte25 <= (others => '0');
+				byte26 <= (others => '0');
+				byte27 <= (others => '0');
+				--data_counter_max <= 0;
+				zero_counter <= 0;
+			end if;
+		end if;
+	end process set_tx_data;
+	
+	-- this process calculates IP header checksum
+	ip_header_checksum_calc: process (clk50mhz_shift,tx_ready,id_counter,dest_ip)
+	begin
+		if (falling_edge(clk50mhz_shift)) then
+			-- only for IP/UDP packets
+			if (eth_protocol = '1' and tx_ready = '1') then
+				-- if checksum hasn't been calculated yet, calculate it
+				if (ip_header_calc_done = '0') then
+					case s is
+						when s1 =>
+							temp_iphc1 <= temp_iphc1+unsigned(ip_version&ip_header_length&ds)+unsigned(ip_total_length)+id_counter+
+							unsigned(flags_offset)+unsigned(ttl&ip_protocol)+unsigned(fpga_ip(31 downto 16))+
+							unsigned(fpga_ip(15 downto 0))+unsigned(dest_ip(31 downto 16))+unsigned(dest_ip(15 downto 0)); -- sum of all header fields
+							s <= s2;
+						when s2 =>
+							temp_iphc2 <= not(temp_iphc2+temp_iphc1(15 downto 0)+temp_iphc1(23 downto 16)); -- sum of the main checksum body with carry-out
+							s <= s3;
+						when s3 =>
+							ip_header_checksum <= std_logic_vector(temp_iphc2); -- calculated checksum
+							ip_header_calc_done <= '1';                         -- checksum calculation done
+							s <= s3;
+					end case;
+				else -- if checksum hasn been calculated, keep it
+					temp_iphc1 <= temp_iphc1;
+					temp_iphc2 <= temp_iphc2;
+					ip_header_checksum <= ip_header_checksum;
+					ip_header_calc_done <= ip_header_calc_done;
+				end if;
+			else -- keep checksum registers clear when they are not used
+				temp_iphc1 <= (others => '0');
+				temp_iphc2 <= (others => '0');
+				ip_header_checksum <= (others => '0');
+				ip_header_calc_done <= '0';
+				s <= s1;
+			end if;
+		end if;
+	end process ip_header_checksum_calc;
+	
+datacm_r <= data_counter_max;
+temp_data <= rd_data_fifo(7 downto 0) & rd_data_fifo(15 downto 8) & rd_data_fifo(23 downto 16) & rd_data_fifo(31 downto 24);
+	
+end Behavioral;
+

ip_repo_sources/UDP_echo-server/src/ethernet_transceiver.vhd

@@ -0,0 +1,565 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov
+-- 
+-- Create Date:    16:19:30 02/20/2017 
+-- Design Name: 
+-- Module Name:    ethernet_transceiver - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+
+-- UDP echo-server design uses on-board Ethernet port to create a data-link between FPGA board
+-- Nexys 4 DDR and MatLAB. Echo-server is capable of reception and transmission data packets
+-- using ARP and UDP protocols.
+-- MAC address of FPGA board: 00:18:3e:01:ff:71
+-- IP4 address of FPGA board: 192.168.1.10
+-- Port number used in the design: 58210
+-- The echo server will reply back to any data server, which uses correct IP4 address and Port number.
+-- MAC address of the board is made discoverable for the data server via ARP protocol
+-- This Echo-server design doesn't use any input or output FIFO's as elesticity buffers,
+-- both in- and outgoing data packets are parsed/assembled in parallel with Rx/Tx processes,
+-- which allows better resource utilisation at the price of more complex design architecture. 
+
+-- Additional Comments: 
+-- Transceiver block is the Top-level block of the Ethernet transceiver design, implementing 
+-- the VHDL UDP echo-server.
+-- Transceiver block itself handles the Power-On Reset operation along with subsequent Hardware Resets
+-- on request from the user.
+-- Apart from that it incorporates lower-level modules handling different functions required for the echo-server
+-- operations: Receiver, Transmitter, Serial Management Interface, Memory and Clock Modules
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.std_logic_unsigned.all;
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity ethernet_transceiver2 is
+	 Generic (M_clk2_5mhz1: integer := 20; -- divisor for 2.5MHz clock
+				 M_clk2_5mhz2: integer := 10; -- divisor for shifted 2.5MHz clock 
+				 N : integer := 22;           -- divisor for debouncing circuit 
+				 ADDR_WIDTH : integer := 10;  -- RAM's address width
+				 DATA_WIDTH : integer := 8;  -- RAM's data width (1024x1byte)
+				 FIFO_WIDTH : integer := 32);
+    Port ( clk100mhz : in  STD_LOGIC;
+           eth_rxd : inout  STD_LOGIC_VECTOR (1 downto 0);
+           eth_txd : inout  STD_LOGIC_VECTOR (1 downto 0);
+           eth_crsdv : inout  STD_LOGIC;
+			  eth_txen : inout  STD_LOGIC;
+           eth_rxerr : inout  STD_LOGIC;
+			  eth_mdc : out  STD_LOGIC;
+           eth_mdio : inout  STD_LOGIC;
+           eth_refclk : out  STD_LOGIC;
+           eth_rstn : inout  STD_LOGIC;
+			  -- display signals for ARP and UDP packets
+			  led16_b : out  STD_LOGIC;
+			  led16_g : out  STD_LOGIC;
+			  led16_r : out  STD_LOGIC;
+			  led17_b : out  STD_LOGIC;
+			  led17_g : out  STD_LOGIC;
+			  led17_r : out  STD_LOGIC;
+			  -- outputs for debugging
+--			  mode0 : out std_logic;
+--			  mode1 : out std_logic;
+--			  mode2 : out std_logic;
+--			  refclk : out std_logic;
+--			  rxerr : out std_logic;
+--			  txd : out  STD_LOGIC_VECTOR (1 downto 0);
+--			  txen : out  STD_LOGIC;
+			  -- Reset and SMI inputs/outputs
+			  btn_reset : in std_logic;
+			  led : out std_logic_vector (15 downto 0);
+			  --sw : in std_logic_vector (4 downto 0);
+			  
+			  
+			  udp_packet_checksum : in STD_LOGIC_VECTOR (15 downto 0);
+			  
+			  udp_packet_recieved : out std_logic;
+			  udp_packet_sending : out std_logic;
+			  fifo_write_data : out std_logic_vector(FIFO_WIDTH-1 downto 0);
+			  fifo_write_enable : out std_logic;
+			  fifo_write_full : in std_logic;
+			  
+			  fifo_read_data : in std_logic_vector(FIFO_WIDTH-1 downto 0);
+			  fifo_read_enable : out std_logic;
+			  fifo_read_length : in STD_LOGIC_VECTOR (15 downto 0); -- max. 1472
+			  fifo_read_empty : in std_logic;
+			  
+			  ip : in std_logic_vector(4 downto 0)
+			  
+			  );
+end ethernet_transceiver2;
+
+architecture Behavioral of ethernet_transceiver2 is
+-- CLOCKS
+	-- main clock
+signal b_clk100mhz : std_logic;
+signal clk50mhz : std_logic; 		  -- inner signal for ETH_REFCLK (read Rx on falling edge)
+signal b_clk50mhz : std_logic; 		  -- inner signal for ETH_REFCLK (read Rx on falling edge)
+signal clk50mhz_shift : std_logic; -- shifted 50mhz clock signal for write Tx operation
+signal b_clk50mhz_shift : std_logic; -- shifted 50mhz clock signal for write Tx operation
+	-- mdio clock
+signal clk2_5mhz : std_logic;       -- MDC clock
+signal b_clk2_5mhz : std_logic;       -- MDC clock
+signal clk2_5mhz_shift : std_logic; -- shifted mdio clock for read and write MDIO
+signal b_clk2_5mhz_shift : std_logic; -- shifted mdio clock for read and write MDIO
+
+-- SIGNALS
+-- ******* process transceiver (only responsible for Hardware Reset) ********--
+type state_type is (idle, power_on, reset);
+signal state : state_type := idle;
+constant MODE : std_logic_vector (2 downto 0) := "111"; -- all capable; auto-negotiation enabled
+constant PHYAD : std_logic := '1'; 							  -- physical address of the transciever
+signal rstn_counter : integer range 0 to 5010 := 0;     -- count 100us+220ns (5000+11 50mhz clock cycles)
+signal po_counter : integer range 0 to 2499999:= 0;     -- count 50ms - power supply turn on time (2,500,000 50mhz clock cycles)
+signal hw_reset : std_logic;         -- button attached to this signal via debouncing circuit: hardware reset
+signal init_proc : std_logic := '0'; -- flag indicating wether power-on reset was done or not
+
+-- ******** Ethernet Signals ********--
+--*^*^*^*^*^*^* PC's and FPGA's MAC, IP4 addresses and Port numbers *^*^*^*^*^*^*--
+signal pc_mac : std_logic_vector (47 downto 0); -- PC's MAC address (configured on PC's side)
+signal pc_ip : std_logic_vector (31 downto 0);  -- PC's IP4 address (configured on PC's side)
+signal pc_port : std_logic_vector (15 downto 0);-- PC's port (configured on PC's side)
+constant fpga_mac : std_logic_vector (47 downto 0) := x"00183e01ff" & "010" & ip;-- FPGA's MAC address
+constant fpga_ip : std_logic_vector (31 downto 0) := x"C0A801" & "001" & ip;     -- FPGA's IP4 address 192.168.1.32 - 192.168.1.63
+constant fpga_port : std_logic_vector (15 downto 0) := x"04D2";       -- FPGA's port 1234
+-- data transfer between Rx and Tx
+signal send_arp_reply : std_logic := '0';        -- ARP protocol flag
+signal send_ethernet_protocol : std_logic := '0';-- Ethernet protocol flag
+signal data_out_valid : std_logic := '0';        -- data valid flag
+signal datacm : STD_LOGIC_VECTOR (ADDR_WIDTH downto 0) := (others => '0'); -- length of data in UDP datagram
+signal udpl : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- length of IP datagram data field in bytes
+signal udpc : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- UDP checksum
+-- data to and from RAM
+signal rx_data : std_logic_vector (DATA_WIDTH-1 downto 0) := (others => '0'); -- data from Rx to RAM
+signal wrt_addr_ram : std_logic_vector (ADDR_WIDTH-1 downto 0) := (others => '0'); -- address to write data to RAM
+signal we_ram : std_logic := '0'; -- enable write RAM operation  
+signal re_ram : std_logic := '0'; -- enable read RAM operation 
+
+signal datacm_send : STD_LOGIC_VECTOR (ADDR_WIDTH downto 0) := (others => '0');
+signal datacm_r : integer range 0 to 1471 := 0;
+signal udp_packet_length : STD_LOGIC_VECTOR (15 downto 0);
+signal fifo_write : std_logic_vector(FIFO_WIDTH-1 downto 0);
+signal fifo_we : std_logic;
+signal fifo_read : std_logic_vector(FIFO_WIDTH-1 downto 0);
+signal fifo_re : std_logic;
+
+signal arp_response_pending : std_logic;
+signal arp_send_valid : std_logic;
+signal udp_send_data_valid : std_logic;
+signal tx_sent_arp : std_logic;
+signal tx_is_idle : std_logic;
+signal rx_is_idle : std_logic;
+signal tx_data_valid : std_logic;
+
+signal send_countdown : integer range 0 to 6000; -- 8333 packets/s
+
+--signal refclk: std_logic;
+
+-- ******** COMPONENTS DECLARATION ********--
+component debounce_switch -- for Hardware Reset switch debouncing
+		    generic (N : integer);
+			 port (clk100mhz : in std_logic;
+					 btn : in std_logic;
+					 db_sw : out std_logic);
+end component;
+
+component clock_mod -- RMII clocks
+			 --generic (M_clk : integer);
+			 port (clk100mhz : in std_logic;
+					 clk_out : out std_logic;
+					 clk_out_shift : out std_logic);
+end component;
+
+component clock_mod2 -- MDC clocks
+			 generic (M_clk1 : integer;
+						 M_clk2 : integer);
+			 port (clk100mhz : in std_logic;
+					 clk_out1 : out std_logic; 
+					 clk_out2 : out std_logic);
+end component;
+
+component md_interface -- MDIO interface
+			 port (mdc_shift : in STD_LOGIC;
+					 mdio : inout  STD_LOGIC;
+					 eth_rstn : in  STD_LOGIC;
+					 led : out  STD_LOGIC_VECTOR (15 downto 0);
+					 sw : in  STD_LOGIC_VECTOR (4 downto 0));
+end component;
+
+component eth_receiver -- RMII Rx Interface
+			 Generic (ADDR_WIDTH : integer;
+						 DATA_WIDTH : integer);
+			 port (clk100mhz : in STD_LOGIC;
+					 clk50mhz : in  STD_LOGIC;
+					 rxd : in  STD_LOGIC_VECTOR (1 downto 0);
+					 crsdv : in  STD_LOGIC;
+					 rstn : in  STD_LOGIC;
+					 rxerr : in STD_LOGIC;
+					 -- RAM signals
+					 wrt_data_ram : inout STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
+					 wrt_addr_ram : inout STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
+					 wrt_enable_ram : out STD_LOGIC;
+					 -- Addresses 
+					 fpga_mac : in STD_LOGIC_VECTOR (47 downto 0);
+					 fpga_ip : in STD_LOGIC_VECTOR (31 downto 0);
+					 fpga_port : in STD_LOGIC_VECTOR (15 downto 0);
+					 pc_mac : out STD_LOGIC_VECTOR (47 downto 0);
+				 	 pc_ip : out  STD_LOGIC_VECTOR (31 downto 0);
+					 pc_port : out STD_LOGIC_VECTOR (15 downto 0);
+					 -- Data to Tx
+					 datacm : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0);
+					 udpl : out STD_LOGIC_VECTOR (15 downto 0);
+					 udpc : out STD_LOGIC_VECTOR (15 downto 0);
+					 send_arp_reply : out STD_LOGIC;
+					 send_ethernet_protocol: out STD_LOGIC;
+					 data_out_valid : out STD_LOGIC;
+					 is_idle : out std_logic);
+end component;
+
+component eth_transmitter -- RMII Tx Interface
+			 Generic (ADDR_WIDTH : integer;
+				       DATA_WIDTH : integer);
+			 port (clk100mhz : in  STD_LOGIC;
+					 clk50mhz_shift : in STD_LOGIC;
+					 rstn : in STD_LOGIC;
+					 txd : inout  STD_LOGIC_VECTOR (1 downto 0);
+					 txen : out  STD_LOGIC;
+				    -- Data from RAM
+                    rd_data_fifo : in STD_LOGIC_VECTOR (31 downto 0);
+                    rd_enable_fifo : out STD_LOGIC;
+					 -- Addresses
+				    fpga_mac : in STD_LOGIC_VECTOR (47 downto 0);
+				    fpga_ip : in STD_LOGIC_VECTOR (31 downto 0);
+				    fpga_port : in STD_LOGIC_VECTOR (15 downto 0);
+				    pc_mac : in STD_LOGIC_VECTOR (47 downto 0);
+				    pc_ip : in  STD_LOGIC_VECTOR (31 downto 0);
+				    pc_port : in STD_LOGIC_VECTOR (15 downto 0);
+				    -- Data from Rx
+					 datacm : in STD_LOGIC_VECTOR (ADDR_WIDTH downto 0);
+					 udpl : in STD_LOGIC_VECTOR (15 downto 0);
+					 udpc : in STD_LOGIC_VECTOR (15 downto 0);
+				    send_arp_reply : in STD_LOGIC;
+				    send_ethernet_protocol: in STD_LOGIC;
+				    data_in_valid : in STD_LOGIC;
+				    datacm_r : out integer range 0 to 1471 := 0;
+				    sent_arp_response : out std_logic;
+			        is_idle : out std_logic);
+end component;
+
+component led1 -- Display module for incoming ARP and UDP packets
+			 Port ( clk50mhz : in  STD_LOGIC;
+					  rstn : in STD_LOGIC;
+					  dv_arp : in  STD_LOGIC;
+					  dv_eth : in  STD_LOGIC;
+					  led16_b : out  STD_LOGIC;
+					  led16_g : out  STD_LOGIC;
+					  led16_r : out  STD_LOGIC;
+					  led17_b : out  STD_LOGIC;
+					  led17_g : out  STD_LOGIC;
+					  led17_r : out  STD_LOGIC);
+end component;
+
+begin
+
+-- ******** COMPONENTS INSTANTIATION ********--
+-- clock buffers
+	U1: BUFG port map (I=>clk100mhz,O=>b_clk100mhz);
+	U2: BUFG port map (I=> clk2_5mhz, O=>b_clk2_5mhz);
+	U3: BUFG port map (I=>clk2_5mhz_shift,O=>b_clk2_5mhz_shift);
+	U4: BUFG port map (I=> clk50mhz,O=>b_clk50mhz);
+	U5: BUFG port map (I=> clk50mhz_shift,O=>b_clk50mhz_shift);
+--	pull-ups on multiplexed MODE pins
+	PULLUP_MODE0: PULLUP PORT MAP (O => eth_rxd(0));
+	PULLUP_MODE1: PULLUP PORT MAP (O => eth_rxd(1));
+	PULLUP_MODE2: PULLUP PORT MAP (O => eth_crsdv);
+-- pull-up on multiplexed PHYAD pin
+	PULLUP_PHYAD0: PULLUP PORT MAP (O => eth_rxerr);
+	
+-- pull-up on I2C MDIO pin is implemented in md_interface module
+
+-- MDIO interface
+	MDIO_Interface: md_interface
+						 port map (mdc_shift => b_clk2_5mhz_shift,--clk2_5mhz_shift,
+									  mdio => eth_mdio,
+									  eth_rstn => eth_rstn,
+									  led => led,
+									  sw => "11101");
+									  
+--Ethernet receiver
+	Ethernet_receiver: eth_receiver
+							 generic map (ADDR_WIDTH => ADDR_WIDTH,
+											  DATA_WIDTH => DATA_WIDTH)
+						    port map (clk100mhz => b_clk100mhz,
+										  clk50mhz => b_clk50mhz,
+										  rxd => eth_rxd,
+										  crsdv => eth_crsdv,
+										  rstn => eth_rstn,
+										  rxerr => eth_rxerr,
+										  ---
+										  wrt_data_ram => rx_data,
+										  wrt_addr_ram => wrt_addr_ram,
+										  wrt_enable_ram => we_ram,
+										  ---
+										  fpga_mac => fpga_mac,
+										  fpga_ip => fpga_ip,
+										  fpga_port => fpga_port,
+										  pc_mac => pc_mac,
+										  pc_ip => pc_ip,
+										  pc_port => pc_port,
+										  ---
+										  datacm => datacm,
+										  udpl => udpl,
+										  udpc => udpc,
+										  send_arp_reply => send_arp_reply,
+										  send_ethernet_protocol => send_ethernet_protocol,
+										  data_out_valid => data_out_valid);
+
+--Ethernet transmitter
+	Ethernet_transmitter: eth_transmitter
+								 generic map (ADDR_WIDTH => ADDR_WIDTH,
+												  DATA_WIDTH => DATA_WIDTH)
+								 port map (clk100mhz => b_clk100mhz,
+											  clk50mhz_shift => b_clk50mhz_shift,
+											  rstn => eth_rstn,
+											  txd => eth_txd,
+											  txen => eth_txen,
+											  ---
+											  rd_data_fifo => fifo_read_data,
+											  rd_enable_fifo => re_ram,
+											  ---
+											  fpga_mac => fpga_mac,
+											  fpga_ip => fpga_ip,
+											  fpga_port => fpga_port,
+											  pc_mac => pc_mac,
+											  pc_ip => pc_ip,
+											  pc_port => pc_port,
+											  ---
+											  datacm => datacm_send,
+											  udpl => udp_packet_length,
+											  udpc => udp_packet_checksum,
+											  send_arp_reply => arp_send_valid,
+											  send_ethernet_protocol => udp_send_data_valid,
+											  data_in_valid => tx_data_valid,
+											  datacm_r => datacm_r,
+											  sent_arp_response => tx_sent_arp,
+			                                  is_idle => tx_is_idle);
+
+-- ARP and UDP LED's
+LED_count : led1 -- Display module for incoming ARP and UDP packets
+			 port map (clk50mhz => b_clk50mhz,
+						  rstn => eth_rstn,
+						  dv_arp => send_arp_reply,
+						  dv_eth => send_ethernet_protocol,
+						  led16_b => led16_b,
+						  led16_g => led16_g,
+						  led16_r => led16_r,
+						  led17_b => led17_b,
+						  led17_g => led17_g,
+						  led17_r => led17_r);
+
+-- Debouncing circuit
+	Switch: debounce_switch
+			  generic map (N => N)
+			  port map (clk100mhz => b_clk100mhz,
+							btn => btn_reset,
+							db_sw => hw_reset);
+
+-- RMII clocks	
+	CLOCK_50MHz: clock_mod
+					 --generic map (M_clk => M_clk50mhz)
+					 port map (clk100mhz => b_clk100mhz,
+								  clk_out => clk50mhz,
+								  clk_out_shift => clk50mhz_shift); 
+-- MDIO clocks
+	CLOCK_2_5MHz: clock_mod2
+					  generic map (M_clk1 => M_clk2_5mhz1,
+										M_clk2 => M_clk2_5mhz2)
+					  port map (clk100mhz => b_clk100mhz,
+								   clk_out1 => clk2_5mhz,
+									clk_out2 => clk2_5mhz_shift);
+	
+	transceiver: process (b_clk50mhz, hw_reset)
+	begin
+		if (hw_reset = '0') then
+			eth_rstn <= '0';
+			--MODE <= "111"; -- configure MODES here (if MODE is other than 1's)
+			--PHYAD <= '1';  -- configure PHYAD here (if PHYAD is other than 1's)
+			rstn_counter <= 0;
+			state <= reset;
+		elsif (rising_edge(b_clk50mhz)) then
+			case state is
+			
+			when idle =>
+				if (init_proc = '0') then -- if Power-ON Reset (POR) hasn't been completed
+					eth_rstn <= '1';
+					--MODE <= "111"; -- configure MODES here (if MODES is other than 1's)
+					--PHYAD <= '1';  -- configure PHYAD here (if PHYAD is other than 1's)
+					state <= power_on;
+				else	
+					eth_rstn <= '1';
+					--MODE <= "111"; -- release (set to 1's) MODES here (if configure them)
+					--PHYAD <= '1';  -- release (set to 1) PHYAD here (if configure it)
+					state <= idle;
+				end if;
+			
+			when power_on => -- wait for 50 ms before POR
+				--MODE <= "111"; -- configure MODES here (if MODES is other than 1's)
+				--PHYAD <= '1';  -- configure PHYAD here (if PHYAD is other than 1's)
+				if (po_counter < 2499999) then  
+					eth_rstn <= '1';
+					po_counter <= po_counter+1;
+					state <= power_on;
+				elsif (po_counter = 2499999) then
+					eth_rstn <= '0';
+					init_proc <= '1';
+					po_counter <= 0;
+					state <= reset;
+				end if;
+			
+			when reset => -- POR
+				if (rstn_counter <= 4999) then -- 100 us before releasing eth_rstn
+					--MODE <= "111"; -- configure MODES here (if MODES is other than 1's)
+					--PHYAD <= '1';  -- configure PHYAD here (if PHYAD is other than 1's)
+					rstn_counter <= rstn_counter+1;
+					eth_rstn <= '0';
+					state <= reset;
+				elsif (rstn_counter > 4999 and rstn_counter <= 5009) then -- 220 ns hold on time after releasing eth_rstn
+					--MODE <= "111"; -- configure MODES here (if MODES is other than 1's)
+					--PHYAD <= '1';  -- configure PHYAD here (if PHYAD is other than 1's)
+					rstn_counter <= rstn_counter+1;
+					eth_rstn <= '1';
+					state <= reset;
+				elsif (rstn_counter = 5010) then -- POR done, go back to idle state
+					--MODE <= "111"; -- release (set to 1's) MODES here (if configure them)
+					--PHYAD <= '1';  -- release (set to 1) PHYAD here (if configure it)
+					rstn_counter <= 0;
+					eth_rstn <= '1';
+					state <= idle;
+				end if;
+					
+			end case;
+		end if;
+	end process transceiver;
+	
+	s2p : process(clk100mhz)
+	variable byte_index : integer range 0 to 3;
+	begin
+	   if(falling_edge(clk100mhz)) then
+	       fifo_we <= '0';
+	       if(we_ram = '1') then
+	           byte_index := to_integer(unsigned(wrt_addr_ram(1 downto 0)));
+               --fifo_write <= fifo_write(FIFO_WIDTH-1-DATA_WIDTH downto 0) & rx_data;
+               --fifo_write(FIFO_WIDTH-1-DATA_WIDTH*byte_index downto FIFO_WIDTH-(DATA_WIDTH+1)*byte_index) <= rx_data;
+               case byte_index is
+                    when 0 => fifo_write(31 downto 24) <= rx_data;
+                    when 1 => fifo_write(23 downto 16) <= rx_data;
+                    when 2 => fifo_write(15 downto  8) <= rx_data;
+                    when 3 => fifo_write( 7 downto  0) <= rx_data;
+               end case;
+               if(byte_index = 3 and fifo_we = '0') then
+                   fifo_we <= '1';
+               end if;
+	       end if;
+	   end if;
+	end process;
+	
+	p2s : process(clk100mhz, re_ram)
+	begin
+	   if(rising_edge(clk100mhz)) then
+	       --fifo_re <= '0';
+	       --if(re_ram = '1' and b_clk50mhz = '0') then
+	       --    fifo_re <= '1';
+           --end if;
+	   end if;
+	   fifo_re <= re_ram;
+	end process;
+	
+	send : process(b_clk50mhz)
+	   variable data_length : integer;
+	begin
+	   if(hw_reset = '0') then
+	       arp_response_pending <= '0';
+	       udp_send_data_valid <= '0';
+	       arp_send_valid <= '0';
+	   elsif(rising_edge(b_clk50mhz)) then
+           data_length := to_integer(unsigned(fifo_read_length))*(FIFO_WIDTH/DATA_WIDTH);
+           udp_send_data_valid <= '0';
+           arp_send_valid <= '0';
+           
+           if(data_length > 1472) then
+                udp_packet_length <= std_logic_vector(to_unsigned(1472+8, 16));
+                datacm_send <= std_logic_vector(to_unsigned(1472, ADDR_WIDTH+1));
+           else
+                udp_packet_length <= std_logic_vector(to_unsigned(data_length+8, 16));
+                datacm_send <= std_logic_vector(to_unsigned(data_length, ADDR_WIDTH+1));
+           end if;
+	       if(send_arp_reply = '1') then
+	           arp_response_pending <= '1';
+	       elsif(tx_sent_arp = '1') then
+	           arp_response_pending <= '0';
+	       else
+	           arp_response_pending <= arp_response_pending;
+	       end if;
+	       
+
+	       
+	       if(tx_is_idle = '1' and state = idle and send_countdown = 0) then
+	           tx_data_valid <= '1';
+	           send_countdown <= 6000;
+	           if(data_length > 0 and unsigned(pc_ip) /= 0) then
+                   udp_send_data_valid <= '1';
+               end if;
+               if(arp_response_pending = '1') then
+                    arp_send_valid <= '1';
+               end if;
+	       elsif(send_countdown > 0) then
+	           tx_data_valid <= '0';
+	           send_countdown <= send_countdown-1;
+	       else
+	           tx_data_valid <= '0';
+	       end if;
+
+	   end if;
+	end process;
+
+-- tri-state buffers
+eth_rxd(0) <= '0' when MODE(0) = '0' else 'Z';
+eth_rxd(1) <= '0' when MODE(1) = '0' else 'Z';
+eth_crsdv <= '0' when MODE(2) = '0' else 'Z';
+eth_rxerr <= '0' when PHYAD = '0' else 'Z';
+-- RMII and MDC clocks
+eth_refclk <= b_clk50mhz;
+eth_mdc <= b_clk2_5mhz;--clk2_5mhz;
+
+-- outputs for debugging
+--mode0 <= eth_rxd(0);
+--mode1 <= eth_rxd(1);
+--mode2 <= eth_crsdv;
+--refclk <= b_clk50mhz;
+--rxerr <= eth_rxerr;
+--txd <= eth_txd;
+--txen <= eth_txen;
+
+udp_packet_recieved <= send_ethernet_protocol;
+udp_packet_sending <= tx_data_valid and udp_send_data_valid and not arp_response_pending;
+fifo_write_data <= fifo_write;
+fifo_write_enable <= fifo_we;
+fifo_read_enable <= fifo_re;
+
+end Behavioral;
+

ip_repo_sources/UDP_echo-server/src/led1.vhd

@@ -0,0 +1,94 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov 
+-- 
+-- Create Date:    14:15:42 03/30/2017 
+-- Design Name: 
+-- Module Name:    led1 - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- LED module visualise inflow of the valid data packets changing the colour of the 
+-- tri-colour LED's every time when valid ARP or UDP packet arrives
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity led1 is
+    Port ( clk50mhz : in  STD_LOGIC;
+			  rstn : in STD_LOGIC;
+           dv_arp : in  STD_LOGIC;
+			  dv_eth : in  STD_LOGIC;
+           led16_b : out  STD_LOGIC;
+			  led16_g : out  STD_LOGIC;
+			  led16_r : out  STD_LOGIC;
+			  led17_b : out  STD_LOGIC;
+			  led17_g : out  STD_LOGIC;
+			  led17_r : out  STD_LOGIC);
+end led1;
+
+architecture Behavioral of led1 is
+type state_type is (idle,arp_signal,eth_signal);
+signal state : state_type := idle;
+signal count_arp : integer range 0 to 3 := 0;
+signal count_eth : integer range 0 to 3 := 0;
+
+begin
+	led: process (clk50mhz,rstn,dv_arp,dv_eth)
+	begin
+		if (rstn = '0') then -- if Hardware Reset refresh counters and turn off led's
+			led16_b <= '0'; led16_g <= '0'; led16_r <= '0';
+			led17_b <= '0'; led17_g <= '0'; led17_r <= '0';
+			count_arp <= 0;
+			count_eth <= 0;
+		elsif (rising_edge(clk50mhz)) then
+			if (dv_arp ='1') then 			-- if valid ARP packet received
+				count_arp <= count_arp+1;  -- increment ARP counter 
+				if(count_arp+1 > 3) then
+					count_arp <= 1;
+				end if;
+			else
+				count_arp <= count_arp;
+			end if;
+				case count_arp is -- change ARP's led colour depending on the packet number 
+					when 0 => led16_b <= '0'; led16_g <= '0'; led16_r <= '0';
+					when 1 => led16_b <= '1'; led16_g <= '0'; led16_r <= '0';
+					when 2 => led16_b <= '0'; led16_g <= '1'; led16_r <= '0';
+					when 3 => led16_b <= '0'; led16_g <= '0'; led16_r <= '1';
+				end case;
+			
+			if (dv_eth ='1') then       -- if valid UDP packet received
+				count_eth <= count_eth+1;-- increment UDP counter 
+				if(count_eth+1 > 3) then
+					count_eth <= 1;
+				end if;
+			else
+				count_eth <= count_eth;
+			end if;
+				case count_eth is -- change UDP's led colour depending on the packet number 
+					when 0 => led17_b <= '0'; led17_g <= '0'; led17_r <= '0';
+					when 1 => led17_b <= '1'; led17_g <= '0'; led17_r <= '0';
+					when 2 => led17_b <= '0'; led17_g <= '1'; led17_r <= '0';
+					when 3 => led17_b <= '0'; led17_g <= '0'; led17_r <= '1';
+				end case;
+		end if;
+	end process led;
+
+end Behavioral;
+

ip_repo_sources/UDP_echo-server/src/md_interface.vhd

@@ -0,0 +1,162 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov 
+-- 
+-- Create Date:    10:34:00 02/22/2017 
+-- Design Name: 
+-- Module Name:    md_interface - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- MDIO interface reads content of the SMI registers selected by input sw<4:0> and displays 
+-- their content using 16 on-board LED's
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity md_interface is
+    Port ( mdc_shift : in STD_LOGIC; -- clock for read/write SMI
+           mdio : inout  STD_LOGIC;  -- SMI data in/out line
+           eth_rstn : in  STD_LOGIC; -- reset
+           led : out  STD_LOGIC_VECTOR (15 downto 0); -- display for SMI registers
+           sw : in  STD_LOGIC_VECTOR (4 downto 0));   -- SMI register address
+end md_interface;
+
+architecture Behavioral of md_interface is
+
+signal mdio_prime : std_logic;
+constant preamble : std_logic_vector (31 downto 0) := x"FFFFFFFF"; -- preamble 32 1's
+constant start : std_logic_vector (1 downto 0) := "01";            -- start-of-frame
+constant wrt_mdio : std_logic_vector (1 downto 0) := "01";         -- code of write operation
+constant phy_addr : std_logic_vector (4 downto 0) := "00001";      -- physical address of chip
+signal reg_addr : std_logic_vector (4 downto 0);                   -- SMI register's address
+signal reg_data : std_logic_vector (15 downto 0);                  -- content of the SMI register
+type state_type is (idle, read_mdio);--, write_mdio);
+signal state : state_type := idle;
+signal counter : integer range  0 to 63 := 0;
+
+begin
+-- pull-up on I2C MDIO pin
+	PULLUP_MDIO: PULLUP PORT MAP (O => mdio);
+
+	mdio_interface: process (mdc_shift, eth_rstn)
+	begin
+		if (eth_rstn = '0') then
+			counter <= 0;
+			state <= idle;
+		elsif (rising_edge(mdc_shift)) then
+			case state is
+			
+			-- SMI module remains idle during reset
+			when idle =>
+				counter <= 0;
+				state <= read_mdio;
+			
+			-- in this state the SMI register, selected by sw<4:0> is read
+			when read_mdio =>
+				-- write preamble
+				if (counter <= 31) then
+					mdio_prime <= preamble(counter);
+					counter <= counter+1;
+					state <= read_mdio;
+				-- write start-of-frame bits
+				elsif (counter > 31 and counter <= 33)then
+					mdio_prime <= start(33-counter);
+					counter <= counter+1;
+					state <= read_mdio;
+				-- write operation code (read)
+				elsif (counter > 33 and counter <= 35) then
+					mdio_prime <= not(wrt_mdio(35-counter)); -- not(write) is read
+					counter <= counter+1;
+					state <= read_mdio;
+				-- write physical address of the device
+				elsif (counter > 35 and counter <=40) then
+					mdio_prime <= phy_addr(40-counter);
+					counter <= counter+1;
+					state <= read_mdio;
+				-- write register address to be read (sw<4:0>)
+				elsif (counter > 40 and counter <= 45) then
+					mdio_prime <= reg_addr(45-counter);
+					counter <= counter+1;
+					state <= read_mdio;
+				-- release line for turnaround bits
+				elsif (counter = 46 or counter = 47) then
+					mdio_prime <= '1'; --
+					counter <= counter+1;
+					state <= read_mdio;
+				-- read register's content
+				elsif (counter > 47 and counter < 63) then
+					reg_data(63-counter) <= mdio;
+					counter <= counter+1;
+					state <= read_mdio;
+				elsif (counter = 63) then
+					reg_data(63-counter) <= mdio;
+					counter <= 0;
+					state <= idle; -- go back to idle
+				end if;
+			
+			-- this state handles write SMI operation (not used in this design)
+--			when write_mdio =>
+--				read_done <= '0';
+--				if (counter <= 31) then
+--					mdio_prime <= preamble(counter);
+--					counter <= counter+1;
+--					state <= write_mdio;
+--				elsif (counter > 31 and counter <= 33)then
+--					mdio_prime <= start(33-counter);
+--					counter <= counter+1;
+--					state <= write_mdio;
+--				elsif (counter > 33 and counter <= 35) then
+--					mdio_prime <= wrt_mdio(35-counter);
+--					counter <= counter+1;
+--					state <= write_mdio;
+--				elsif (counter > 35 and counter <=40) then
+--					mdio_prime <= phy_addr(40-counter);
+--					counter <= counter+1;
+--					state <= write_mdio;
+--				elsif (counter > 40 and counter <= 45) then
+--					mdio_prime <= reg_addr_wrt(45-counter);
+--					counter <= counter+1;
+--					state <= write_mdio;
+--				elsif (counter = 46 or counter = 47) then -- turnaround bits
+--					mdio_prime <= '1';--
+--					counter <= counter+1;
+--					state <= write_mdio;
+--				elsif (counter > 47 and counter < 63) then
+--					mdio_prime <= reg_data_wrt(63-counter);
+--					counter <= counter+1;
+--					state <= write_mdio;
+--				elsif (counter = 63) then
+--					mdio_prime <= reg_data_wrt(63-counter);
+--					counter <= 0;
+--					write_done <= '1';
+--					state <= idle;
+--				end if;
+			
+			end case;
+		end if;
+	end process mdio_interface;
+	
+
+led <= reg_data; -- display content of the SMI register
+reg_addr <= sw;  -- read this register's content
+mdio <= '0' when mdio_prime = '0' else 'Z';
+
+end Behavioral;
+

ip_repo_sources/UDP_echo-server/src/nexys 4 ddr.xdc

@@ -0,0 +1,57 @@
+#clock
+
+set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk100mhz]
+#create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk100mhz]
+set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports btn_reset]
+
+
+# ethernet phy
+
+set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS33} [get_ports eth_mdc]
+set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports eth_mdio]
+set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports eth_rstn]
+set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports eth_crsdv]
+set_property -dict {PACKAGE_PIN C10 IOSTANDARD LVCMOS33} [get_ports eth_rxerr]
+set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports {eth_rxd[0]}]
+set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports {eth_rxd[1]}]
+set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS33} [get_ports eth_txen]
+set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS33} [get_ports {eth_txd[0]}]
+set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports {eth_txd[1]}]
+set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports eth_refclk]
+#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }];
+
+# rgb led
+
+set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L5P_T0_D06_14 Sch=led16_b
+set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g
+set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
+set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
+set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g
+set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
+
+## LEDs
+
+set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
+set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
+set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
+set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
+set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
+set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
+set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
+set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
+set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
+set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
+set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
+set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
+set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
+set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
+set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
+set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
+
+##Switches
+
+set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
+set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
+set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
+set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
+set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { sw[4] }];

ip_repo_sources/UDP_echo-server/src/shiftIn.vhd

@@ -0,0 +1,58 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 06/03/2019 01:56:01 PM
+-- Design Name: 
+-- Module Name: shiftOut - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity shiftIn is
+    generic(
+        inWidth : integer := 8;
+        outWidth : integer := 32);
+    Port ( clk : in STD_LOGIC;
+           sync_reset : in STD_LOGIC;
+           dataIn : in std_logic_vector(inWidth-1 downto 0);
+           dataOut : out std_logic_vector(outWidth-1 downto 0);
+           finished : out STD_LOGIC);
+end shiftIn;
+
+architecture Behavioral of shiftIn is
+    signal dataIndex : integer range 0 to (outWidth / inWidth) := 0;
+begin
+
+p_s2p : process(clk, sync_reset)
+begin
+    if(sync_reset = '0') then
+        dataIndex <= 0;
+        finished <= '0';
+        dataOut <= (others => '0');
+    elsif(rising_edge(clk)) then
+        if(dataIndex < outWidth/inWidth) then
+            dataOut(outWidth - dataIndex * inWidth - 1 downto outWidth - dataIndex * inWidth - inWidth) <= dataIn;
+            dataIndex <= dataIndex + 1;
+            finished <= '0';
+        else
+            dataIndex <= dataIndex;
+            finished <= '1';
+        end if;
+    end if;
+end process;
+
+end Behavioral;

ip_repo_sources/UDP_echo-server/src/single_port_RAM.vhd

@@ -0,0 +1,66 @@
+----------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov 
+-- 
+-- Create Date:    17:24:25 02/19/2017 
+-- Design Name: 
+-- Module Name:    single_port_RAM - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- RAM module stores the data received with incoming packets and supplies it back to 
+-- Transmitter module for outgoing packets
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity single_port_RAM is
+	 Generic ( ADDR_WIDTH : integer;
+				  DATA_WIDTH : integer);
+    Port ( clk50mhz : in  STD_LOGIC; -- reference clock
+           we : in  STD_LOGIC;       -- write enable
+			  re : in STD_LOGIC;        -- read enable
+           addr_r : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0); -- address to write
+			  addr_w : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0); -- address to read
+           din : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);    -- data-in bus
+           dout : out  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)); -- data-out bus
+end single_port_RAM;
+
+architecture Behavioral of single_port_RAM is
+
+type ram_type is array (2**ADDR_WIDTH-1 downto 0) of 
+	std_logic_vector (DATA_WIDTH-1 downto 0);
+signal ram: ram_type := (others =>(others => '0'));
+
+begin
+	
+	memory: process (clk50mhz)
+	begin
+		if (rising_edge(clk50mhz)) then
+			if (we = '1') then -- when write is enabled
+				ram(to_integer(unsigned(addr_w))) <= din; -- write data on data-in bus into specified in addr_w register
+			end if;
+			if (re = '1') then -- when read is enabled
+				dout <= ram(to_integer(unsigned(addr_r)));-- read data from specified in addr_r register and place it on data-out bus
+			end if;
+		end if;
+	end process memory;
+
+end Behavioral;
+

ip_repo_sources/UDP_echo-server/src/tb_eth_rxtx_arp_udp_ram.vhd

@@ -0,0 +1,234 @@
+--------------------------------------------------------------------------------
+-- Company: The Hong Kong Polytechnic University
+-- Engineer: Alexandr Melnikov
+--
+-- Create Date:   14:39:20 04/06/2017
+-- Design Name:   
+-- Module Name:   C:/Users/AM/Documents/ISE_projects/Nexyx4DDR/Ethernet/Ethernet_arp_udp_ram/eth_transceiver/tb_eth_rxtx_arp_udp_ram.vhd
+-- Project Name:  eth_transceiver
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: ethernet_transciever
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- This testbench file is used to test functionality of the UDP echo-server.
+-- First packet is ARP request being sent to echo-server from external
+-- data server to resolve the board's MAC address.
+-- 2nd and 4th packets are valid UDP messages of diffrent length and
+-- 3rd packet is invalid UDP message designated to the wrong port number.
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ 
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+ 
+ENTITY tb_eth_rxtx_arp_udp_ram IS
+END tb_eth_rxtx_arp_udp_ram;
+ 
+ARCHITECTURE behavior OF tb_eth_rxtx_arp_udp_ram IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT ethernet_transceiver2
+    Port ( clk100mhz : in  STD_LOGIC;
+           eth_rxd : inout  STD_LOGIC_VECTOR (1 downto 0);
+           eth_txd : inout  STD_LOGIC_VECTOR (1 downto 0);
+           eth_crsdv : inout  STD_LOGIC;
+			  eth_txen : inout  STD_LOGIC;
+           eth_rxerr : inout  STD_LOGIC;
+			  eth_mdc : out  STD_LOGIC;
+           eth_mdio : inout  STD_LOGIC;
+           eth_refclk : out  STD_LOGIC;
+           eth_rstn : inout  STD_LOGIC;
+			  -- display signals for ARP and UDP packets
+			  led16_b : out  STD_LOGIC;
+			  led16_g : out  STD_LOGIC;
+			  led16_r : out  STD_LOGIC;
+			  led17_b : out  STD_LOGIC;
+			  led17_g : out  STD_LOGIC;
+			  led17_r : out  STD_LOGIC;
+			  -- outputs for debugging
+--			  mode0 : out std_logic;
+--			  mode1 : out std_logic;
+--			  mode2 : out std_logic;
+--			  refclk : out std_logic;
+--			  rxerr : out std_logic;
+--			  txd : out  STD_LOGIC_VECTOR (1 downto 0);
+--			  txen : out  STD_LOGIC;
+			  -- Reset and SMI inputs/outputs
+			  btn_reset : in std_logic;
+			  led : out std_logic_vector (15 downto 0);
+			  sw : in std_logic_vector (4 downto 0));
+    END COMPONENT;
+    
+
+   --Inputs
+   signal clk100mhz : std_logic := '0';
+   signal btn_reset : std_logic := '0';
+   signal sw : std_logic_vector(4 downto 0) := (others => '0');
+
+	--BiDirs
+   signal eth_rxd : std_logic_vector(1 downto 0);
+   signal eth_txd : std_logic_vector(1 downto 0);
+   signal eth_crsdv : std_logic;
+   signal eth_mdio : std_logic;
+   signal eth_rstn : std_logic;
+   signal eth_rxerr : std_logic;
+
+ 	--Outputs
+   signal led16_b : std_logic;
+   signal led16_g : std_logic;
+   signal led16_r : std_logic;
+   signal led17_b : std_logic;
+   signal led17_g : std_logic;
+   signal led17_r : std_logic;
+   signal eth_mdc : std_logic;
+   signal eth_refclk : std_logic;
+--   signal mode0 : std_logic;
+--   signal mode1 : std_logic;
+--   signal mode2 : std_logic;
+--   signal refclk : std_logic;
+--   signal rxerr : std_logic;
+   signal led : std_logic_vector(15 downto 0);
+   signal eth_txen : std_logic;
+
+   -- Clock period definitions
+   constant clk100mhz_period : time := 10 ns;
+   constant eth_refclk_period : time := 20 ns;
+   ---
+	signal data_arp : std_logic_vector(591 downto 0);
+	signal data_udp1 : std_logic_vector(591 downto 0);
+	signal data_udp2 : std_logic_vector(591 downto 0);
+	signal data_udp_err : std_logic_vector(591 downto 0);
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: ethernet_transceiver2 PORT MAP (
+          clk100mhz => clk100mhz,
+          eth_rxd => eth_rxd,
+          eth_txd => eth_txd,
+          eth_crsdv => eth_crsdv,
+          led16_b => led16_b,
+          led16_g => led16_g,
+          led16_r => led16_r,
+          led17_b => led17_b,
+          led17_g => led17_g,
+          led17_r => led17_r,
+          eth_mdc => eth_mdc,
+          eth_mdio => eth_mdio,
+          eth_refclk => eth_refclk,
+          eth_rstn => eth_rstn,
+--          mode0 => mode0,
+--          mode1 => mode1,
+--          mode2 => mode2,
+--          refclk => refclk,
+--          rxerr => rxerr,
+          btn_reset => btn_reset,
+          led => led,
+          sw => sw,
+          eth_txen => eth_txen,
+          eth_rxerr => eth_rxerr
+        );
+
+   -- Clock process definitions
+   clk100mhz_process :process
+   begin
+		clk100mhz <= '0';
+		wait for clk100mhz_period/2;
+		clk100mhz <= '1';
+		wait for clk100mhz_period/2;
+   end process;
+ 
+   -- Stimulus process
+   stim_proc: process
+   begin		
+      eth_crsdv <= '0';
+		eth_rxd <= "00";
+		eth_rxerr <= '0';
+		data_arp <= x"0000aaaaaaaaaaaaaaabffffffffffff0007326ce4a6106000801000602000800007326ce4a6031580e00000000000000315805000000000000000000000000000000000000076052b35";
+		data_udp1 <= x"0000aaaaaaaaaaaaaaab00187c80ff8e0007326ce4a61000a20000a4e87e00000188f917031580e0031580506344c74600889d0b8040c020a060e0109000000000000000000014045003";
+		data_udp2 <= x"0000aaaaaaaaaaaaaaab00187c80ff8e0007326ce4a61000a20000b44c2b000001882151031580e0031580506344c74600983828f70f8f4fcf2faf6fef1f9f5fdf3fbf7fff009e1a4c3a";
+      data_udp_err <= x"0000aaaaaaaaaaaaaaab00187c80ff8e0007326ce4a61000a20000b44c2b000001882151031580e0031580506344c74500983829f60e8c3fce21af2def7f1a57df01b67bee009e1a4c3a";
+		
+		wait for 51 ms;
+		wait for 5 ns;
+
+		eth_crsdv <= '1';
+		for j in 295 downto 0 loop
+			eth_rxd(0) <= data_arp (2*j+1);
+			eth_rxd(1) <= data_arp (2*j);
+			if (j > 0) then
+				wait for eth_refclk_period;
+			elsif (j = 0) then
+				wait for eth_refclk_period;
+				eth_crsdv <= '0';
+			end if;
+		end loop;
+		eth_crsdv <= '0';
+      eth_rxd <= "00"; 
+		
+		wait for 200 us;
+		eth_crsdv <= '1';
+		for j in 295 downto 0 loop
+			eth_rxd(0) <= data_udp1 (2*j+1);
+			eth_rxd(1) <= data_udp1 (2*j);
+			if (j > 0) then
+				wait for eth_refclk_period;
+			elsif (j = 0) then
+				wait for eth_refclk_period;
+				eth_crsdv <= '0';
+			end if;
+		end loop;
+		eth_crsdv <= '0';
+		eth_rxd <= "00";
+		
+		wait for 200 us;
+		eth_crsdv <= '1';
+		for j in 295 downto 0 loop
+			eth_rxd(0) <= data_udp_err (2*j+1);
+			eth_rxd(1) <= data_udp_err (2*j);
+			if (j > 0) then
+				wait for eth_refclk_period;
+			elsif (j = 0) then
+				wait for eth_refclk_period;
+				eth_crsdv <= '0';
+			end if;
+		end loop;
+		eth_crsdv <= '0';
+		eth_rxd <= "00";
+		
+		wait for 200 us;
+		eth_crsdv <= '1';
+		for j in 295 downto 0 loop
+			eth_rxd(0) <= data_udp2 (2*j+1);
+			eth_rxd(1) <= data_udp2 (2*j);
+			if (j > 0) then
+				wait for eth_refclk_period;
+			elsif (j = 0) then
+				wait for eth_refclk_period;
+				eth_crsdv <= '0';
+			end if;
+		end loop;
+		eth_crsdv <= '0';
+		eth_rxd <= "00";
+
+      wait;
+   end process;
+
+END;

ip_repo_sources/UDP_echo-server/xgui/ethernet_transceiver2_v1_0.tcl

@@ -0,0 +1,55 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  ipgui::add_page $IPINST -name "Page 0"
+
+  ipgui::add_param $IPINST -name "FIFO_WIDTH"
+
+}
+
+proc update_PARAM_VALUE.FIFO_WIDTH { PARAM_VALUE.FIFO_WIDTH } {
+	# Procedure called to update FIFO_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.FIFO_WIDTH { PARAM_VALUE.FIFO_WIDTH } {
+	# Procedure called to validate FIFO_WIDTH
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.M_clk2_5mhz1 { MODELPARAM_VALUE.M_clk2_5mhz1 } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "M_clk2_5mhz1". Setting updated value from the model parameter.
+set_property value 20 ${MODELPARAM_VALUE.M_clk2_5mhz1}
+}
+
+proc update_MODELPARAM_VALUE.M_clk2_5mhz2 { MODELPARAM_VALUE.M_clk2_5mhz2 } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "M_clk2_5mhz2". Setting updated value from the model parameter.
+set_property value 10 ${MODELPARAM_VALUE.M_clk2_5mhz2}
+}
+
+proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "N". Setting updated value from the model parameter.
+set_property value 22 ${MODELPARAM_VALUE.N}
+}
+
+proc update_MODELPARAM_VALUE.ADDR_WIDTH { MODELPARAM_VALUE.ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "ADDR_WIDTH". Setting updated value from the model parameter.
+set_property value 10 ${MODELPARAM_VALUE.ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "DATA_WIDTH". Setting updated value from the model parameter.
+set_property value 8 ${MODELPARAM_VALUE.DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.FIFO_WIDTH { MODELPARAM_VALUE.FIFO_WIDTH PARAM_VALUE.FIFO_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.FIFO_WIDTH}] ${MODELPARAM_VALUE.FIFO_WIDTH}
+}
+

ip_repo_sources/component.xml

@@ -0,0 +1,650 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>user.org</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>packaging</spirit:name>
+  <spirit:version>3.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>rst</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">rst</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>fifo_read</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RD_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>inputStream</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RD_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>inpRdEn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EMPTY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>inputEmpty</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>fifo_write</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WR_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>outData</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WR_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>outWrEn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>FULL</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>outputFull</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>packaging</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>80fccf26</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>packaging</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>80fccf26</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_testbench</spirit:name>
+        <spirit:displayName>Test Bench</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation.testbench</spirit:envIdentifier>
+        <spirit:modelName>tb</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_testbench_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>88e53ccc</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>b2335c60</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>inputStream</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.busWidth&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>inpRdEn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>inputEmpty</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>outData</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.busWidth&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>outWrEn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>outputFull</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>errorCode</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>stateOut</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>busWidth</spirit:name>
+        <spirit:displayName>Buswidth</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.busWidth">32</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>src/Block_proc.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_Border_proc.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_Border_proc_borderbuf.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_HConvH_proc6.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_VConvH_proc.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_VConvH_proc_linebuf_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/globals.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/checksum.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/conv2d_5x5_224p.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/dummyModule.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/fifo_w32_d2_A.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/fifo_w32_d3_A.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/filter11x11_strm.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/filter11x11_strm_ent.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/kernel_5x5.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/multiplex.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/ram.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/shiftIn.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/start_for_Block_proc_U0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/start_for_Loop_Border_proc_U0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/start_for_Loop_VConvH_proc_U0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/packaging.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_c867fa61</spirit:userFileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>src/Block_proc.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_Border_proc.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_Border_proc_borderbuf.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_HConvH_proc6.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_VConvH_proc.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_VConvH_proc_linebuf_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/globals.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/checksum.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/conv2d_5x5_224p.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/dummyModule.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/fifo_w32_d2_A.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/fifo_w32_d3_A.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/filter11x11_strm.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/filter11x11_strm_ent.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/kernel_5x5.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/multiplex.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/ram.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/shiftIn.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/start_for_Block_proc_U0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/start_for_Loop_Border_proc_U0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/start_for_Loop_VConvH_proc_U0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/packaging.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_testbench_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>src/tb.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/tb_behav.wcfg</spirit:name>
+        <spirit:fileType>unknown</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/packaging_v3_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_b2335c60</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>new conv2d and stall signals</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>busWidth</spirit:name>
+      <spirit:displayName>Buswidth</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.busWidth">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">packaging_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>packaging_v3_0</xilinx:displayName>
+      <xilinx:definitionSource>package_project</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:upgrades>
+        <xilinx:canUpgradeFrom>user.org:user:packaging:1.0</xilinx:canUpgradeFrom>
+      </xilinx:upgrades>
+      <xilinx:coreCreationDateTime>2019-11-06T13:49:40Z</xilinx:coreCreationDateTime>
+      <xilinx:tags>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@68377156_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@3fa25e38_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@32ab59c8_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@222ffcb7_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@4cef5bd3_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@b33b43c_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@4de31678_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@3a6b7ec3_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@192f5ada_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@db6d276_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@54727a33_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@3c83999c_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@6c8e4417_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@2b43ef59_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@469f3a04_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo</xilinx:tag>
+      </xilinx:tags>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6c272f9d"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="75e15df1"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="427ec09f"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="4c9ef9f8"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="017f4340"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>

ip_repo_sources/myip_1.0/bd/bd.tcl

@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {                                                                   
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	set full_sbusif_list [list  ]
+			                                                                                                 
+	foreach busif $all_busif {                                                                               
+		if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {                            
+			set busif_param_list [list]                                                                      
+			set busif_name [get_property NAME $busif]					                                     
+			if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {					         
+			    continue                                                                                     
+			}                                                                                                
+			foreach tparam $axi_standard_param_list {                                                        
+				lappend busif_param_list "C_${busif_name}_${tparam}"                                       
+			}                                                                                                
+			bd::mark_propagate_only $cell_handle $busif_param_list			                                 
+		}		                                                                                             
+	}                                                                                                        
+}
+
+
+proc pre_propagate {cellpath otherInfo } {                                                           
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	                                                                                                         
+	foreach busif $all_busif {	                                                                             
+		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
+			continue                                                                                         
+		}                                                                                                    
+		if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {                           
+			continue                                                                                         
+		}			                                                                                         
+		                                                                                                     
+		set busif_name [get_property NAME $busif]			                                                 
+		foreach tparam $axi_standard_param_list {		                                                     
+			set busif_param_name "C_${busif_name}_${tparam}"			                                     
+			                                                                                                 
+			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
+			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
+			                                                                                                 
+			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
+				if { $val_on_cell != "" } {                                                                  
+					set_property CONFIG.${tparam} $val_on_cell $busif                                        
+				}                                                                                            
+			}			                                                                                     
+		}		                                                                                             
+	}                                                                                                        
+}
+
+
+proc propagate {cellpath otherInfo } {                                                               
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	                                                                                                         
+	foreach busif $all_busif {                                                                               
+		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
+			continue                                                                                         
+		}                                                                                                    
+		if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {                            
+			continue                                                                                         
+		}			                                                                                         
+	                                                                                                         
+		set busif_name [get_property NAME $busif]		                                                     
+		foreach tparam $axi_standard_param_list {			                                                 
+			set busif_param_name "C_${busif_name}_${tparam}"			                                     
+                                                                                                             
+			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
+			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
+			                                                                                                 
+			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
+				#override property of bd_interface_net to bd_cell -- only for slaves.  May check for supported values..
+				if { $val_on_cell_intf_pin != "" } {                                                         
+					set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle               
+				}                                                                                            
+			}                                                                                                
+		}		                                                                                             
+	}                                                                                                        
+}
+

ip_repo_sources/myip_1.0/component.xml

@@ -0,0 +1,828 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>user.org</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>myip</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S00_AXI</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WIZ_NUM_REG</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">32</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S00_AXI_RST</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_RST.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>S00_AXI_CLK</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_BUSIF">S00_AXI</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
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+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_DATA_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
+      <spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
+      <spirit:description>Width of S_AXI address bus</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_ADDR_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S00_AXI_BASEADDR</spirit:name>
+      <spirit:displayName>C S00 AXI BASEADDR</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_BASEADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
+      <spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_HIGHADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">myip_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">artix7</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>myip_v1.0</xilinx:displayName>
+      <xilinx:coreRevision>2</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2019-05-29T08:18:55Z</xilinx:coreCreationDateTime>
+      <xilinx:tags>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@4200fa94_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/myip_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@25589aa_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/myip_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@789342e6_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/myip_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@7fc904b4_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/myip_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@37d27b0d_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/myip_1.0</xilinx:tag>
+      </xilinx:tags>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="df70cddf"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ed1368d5"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="121ab58e"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="1b4053fb"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="a0a6f17f"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="07da88f9"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>

ip_repo_sources/myip_1.0/drivers/myip_v1_0/data/myip.mdd

@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER myip
+	OPTION supported_peripherals = (myip);
+	OPTION copyfiles = all;
+	OPTION VERSION = 1.0;
+	OPTION NAME = myip;
+END DRIVER

ip_repo_sources/myip_1.0/drivers/myip_v1_0/data/myip.tcl

@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+	xdefine_include_file $drv_handle "xparameters.h" "myip" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}

ip_repo_sources/myip_1.0/drivers/myip_v1_0/src/Makefile

@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling myip..."
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}

ip_repo_sources/myip_1.0/drivers/myip_v1_0/src/myip.c

@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "myip.h"
+
+/************************** Function Definitions ***************************/

ip_repo_sources/myip_1.0/drivers/myip_v1_0/src/myip.h

@@ -0,0 +1,107 @@
+
+#ifndef MYIP_H
+#define MYIP_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define MYIP_S00_AXI_SLV_REG0_OFFSET 0
+#define MYIP_S00_AXI_SLV_REG1_OFFSET 4
+#define MYIP_S00_AXI_SLV_REG2_OFFSET 8
+#define MYIP_S00_AXI_SLV_REG3_OFFSET 12
+#define MYIP_S00_AXI_SLV_REG4_OFFSET 16
+#define MYIP_S00_AXI_SLV_REG5_OFFSET 20
+#define MYIP_S00_AXI_SLV_REG6_OFFSET 24
+#define MYIP_S00_AXI_SLV_REG7_OFFSET 28
+#define MYIP_S00_AXI_SLV_REG8_OFFSET 32
+#define MYIP_S00_AXI_SLV_REG9_OFFSET 36
+#define MYIP_S00_AXI_SLV_REG10_OFFSET 40
+#define MYIP_S00_AXI_SLV_REG11_OFFSET 44
+#define MYIP_S00_AXI_SLV_REG12_OFFSET 48
+#define MYIP_S00_AXI_SLV_REG13_OFFSET 52
+#define MYIP_S00_AXI_SLV_REG14_OFFSET 56
+#define MYIP_S00_AXI_SLV_REG15_OFFSET 60
+#define MYIP_S00_AXI_SLV_REG16_OFFSET 64
+#define MYIP_S00_AXI_SLV_REG17_OFFSET 68
+#define MYIP_S00_AXI_SLV_REG18_OFFSET 72
+#define MYIP_S00_AXI_SLV_REG19_OFFSET 76
+#define MYIP_S00_AXI_SLV_REG20_OFFSET 80
+#define MYIP_S00_AXI_SLV_REG21_OFFSET 84
+#define MYIP_S00_AXI_SLV_REG22_OFFSET 88
+#define MYIP_S00_AXI_SLV_REG23_OFFSET 92
+#define MYIP_S00_AXI_SLV_REG24_OFFSET 96
+#define MYIP_S00_AXI_SLV_REG25_OFFSET 100
+#define MYIP_S00_AXI_SLV_REG26_OFFSET 104
+#define MYIP_S00_AXI_SLV_REG27_OFFSET 108
+#define MYIP_S00_AXI_SLV_REG28_OFFSET 112
+#define MYIP_S00_AXI_SLV_REG29_OFFSET 116
+#define MYIP_S00_AXI_SLV_REG30_OFFSET 120
+#define MYIP_S00_AXI_SLV_REG31_OFFSET 124
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a MYIP register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the MYIPdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void MYIP_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define MYIP_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a MYIP register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the MYIP device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 MYIP_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define MYIP_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the MYIP instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus MYIP_Reg_SelfTest(void * baseaddr_p);
+
+#endif // MYIP_H

ip_repo_sources/myip_1.0/drivers/myip_v1_0/src/myip_selftest.c

@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "myip.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the MYIPinstance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus MYIP_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  MYIP_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( MYIP_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}

ip_repo_sources/myip_1.0/example_designs/bfm_design/design.tcl

@@ -0,0 +1,88 @@
+proc create_ipi_design { offsetfile design_name } {
+	create_bd_design $design_name
+	open_bd_design $design_name
+
+	# Create Clock and Reset Ports
+	set ACLK [ create_bd_port -dir I -type clk ACLK ]
+	set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
+	set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
+	set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $ARESETN
+	set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
+
+	# Create instance: myip_0, and set properties
+	set myip_0 [ create_bd_cell -type ip -vlnv user.org:user:myip:1.0 myip_0]
+
+	# Create instance: master_0, and set properties
+	set master_0 [ create_bd_cell -type ip -vlnv  xilinx.com:ip:axi_vip master_0]
+	set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
+
+	# Create interface connections
+	connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins myip_0/S00_AXI]
+
+	# Create port connections
+	connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins myip_0/S00_AXI_ACLK]
+	connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins myip_0/S00_AXI_ARESETN]
+set_property target_simulator XSim [current_project]
+set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
+
+	# Auto assign address
+	assign_bd_address
+
+	# Copy all address to interface_address.vh file
+	set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
+	upvar 1 $offsetfile offset_file
+	set offset_file "${bd_path}/myip_v1_0_tb_include.svh"
+	set fp [open $offset_file "w"]
+	puts $fp "`ifndef myip_v1_0_tb_include_vh_"
+	puts $fp "`define myip_v1_0_tb_include_vh_\n"
+	puts $fp "//Configuration current bd names"
+	puts $fp "`define BD_NAME ${design_name}"
+	puts $fp "`define BD_INST_NAME ${design_name}_i"
+	puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
+	puts $fp "//Configuration address parameters"
+
+	puts $fp "`endif"
+	close $fp
+}
+
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:myip:1.0]]]]
+set test_bench_file ${ip_path}/example_designs/bfm_design/myip_v1_0_tb.sv
+set interface_address_vh_file ""
+
+# Set IP Repository and Update IP Catalogue 
+set repo_paths [get_property ip_repo_paths [current_fileset]] 
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+	update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+	set design_name "myip_v1_0_bfm_${i}"
+	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+		break
+	}
+}
+
+create_ipi_design interface_address_vh_file ${design_name}
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+import_files -fileset sim_1 -norecurse -force $test_bench_file
+remove_files -quiet -fileset sim_1 myip_v1_0_tb_include.vh
+import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
+set_property top myip_v1_0_tb [get_filesets sim_1]
+set_property top_lib {} [get_filesets sim_1]
+set_property top_file {} [get_filesets sim_1]
+launch_simulation -simset sim_1 -mode behavioral

ip_repo_sources/myip_1.0/example_designs/bfm_design/myip_v1_0_tb.sv

@@ -0,0 +1,197 @@
+
+`timescale 1ns / 1ps
+`include "myip_v1_0_tb_include.svh"
+
+import axi_vip_pkg::*;
+import myip_v1_0_bfm_1_master_0_0_pkg::*;
+
+module myip_v1_0_tb();
+
+
+xil_axi_uint                            error_cnt = 0;
+xil_axi_uint                            comparison_cnt = 0;
+axi_transaction                         wr_transaction;   
+axi_transaction                         rd_transaction;   
+axi_monitor_transaction                 mst_monitor_transaction;  
+axi_monitor_transaction                 master_moniter_transaction_queue[$];  
+xil_axi_uint                            master_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 mst_scb_transaction;  
+axi_monitor_transaction                 passthrough_monitor_transaction;  
+axi_monitor_transaction                 passthrough_master_moniter_transaction_queue[$];  
+xil_axi_uint                            passthrough_master_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 passthrough_mst_scb_transaction;  
+axi_monitor_transaction                 passthrough_slave_moniter_transaction_queue[$];  
+xil_axi_uint                            passthrough_slave_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 passthrough_slv_scb_transaction;  
+axi_monitor_transaction                 slv_monitor_transaction;  
+axi_monitor_transaction                 slave_moniter_transaction_queue[$];  
+xil_axi_uint                            slave_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 slv_scb_transaction;  
+xil_axi_uint                           mst_agent_verbosity = 0;  
+xil_axi_uint                           slv_agent_verbosity = 0;  
+xil_axi_uint                           passthrough_agent_verbosity = 0;  
+bit                                     clock;
+bit                                     reset;
+integer result_slave;  
+bit [31:0] S00_AXI_test_data[3:0]; 
+ localparam LC_AXI_BURST_LENGTH = 8; 
+ localparam LC_AXI_DATA_WIDTH = 32; 
+task automatic COMPARE_DATA; 
+  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected; 
+  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual; 
+  begin 
+    if (expected === 'hx || actual === 'hx) begin 
+      $display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); 
+ result_slave = 0;    $stop; 
+  end 
+  if (actual != expected) begin 
+    $display("TESTBENCH ERROR! Data expected is not equal to actual.",     " expected = 0x%h",expected,     " actual   = 0x%h",actual); 
+    result_slave = 0; 
+    $stop; 
+  end 
+  else  
+    begin 
+     $display("TESTBENCH Passed! Data expected is equal to actual.", 
+              " expected = 0x%h",expected,               " actual   = 0x%h",actual); 
+    end 
+  end 
+endtask 
+integer                                 i; 
+integer                                 j;  
+xil_axi_uint                            trans_cnt_before_switch = 48;  
+xil_axi_uint                            passthrough_cmd_switch_cnt = 0;  
+event                                   passthrough_mastermode_start_event;  
+event                                   passthrough_mastermode_end_event;  
+event                                   passthrough_slavemode_end_event;  
+xil_axi_uint                            mtestID;  
+xil_axi_ulong                           mtestADDR;  
+xil_axi_len_t                           mtestBurstLength;  
+xil_axi_size_t                          mtestDataSize;   
+xil_axi_burst_t                         mtestBurstType;   
+xil_axi_lock_t                          mtestLOCK;  
+xil_axi_cache_t                         mtestCacheType = 0;  
+xil_axi_prot_t                          mtestProtectionType = 3'b000;  
+xil_axi_region_t                        mtestRegion = 4'b000;  
+xil_axi_qos_t                           mtestQOS = 4'b000;  
+xil_axi_data_beat                       dbeat;  
+xil_axi_data_beat [255:0]               mtestWUSER;   
+xil_axi_data_beat                       mtestAWUSER = 'h0;  
+xil_axi_data_beat                       mtestARUSER = 0;  
+xil_axi_data_beat [255:0]               mtestRUSER;      
+xil_axi_uint                            mtestBUSER = 0;  
+xil_axi_resp_t                          mtestBresp;  
+xil_axi_resp_t[255:0]                   mtestRresp;  
+bit [63:0]                              mtestWDataL; 
+bit [63:0]                              mtestRDataL; 
+axi_transaction                         pss_wr_transaction;   
+axi_transaction                         pss_rd_transaction;   
+axi_transaction                         reactive_transaction;   
+axi_transaction                         rd_payload_transaction;  
+axi_transaction                         wr_rand;  
+axi_transaction                         rd_rand;  
+axi_transaction                         wr_reactive;  
+axi_transaction                         rd_reactive;  
+axi_transaction                         wr_reactive2;   
+axi_transaction                         rd_reactive2;  
+axi_ready_gen                           bready_gen;  
+axi_ready_gen                           rready_gen;  
+axi_ready_gen                           awready_gen;  
+axi_ready_gen                           wready_gen;  
+axi_ready_gen                           arready_gen;  
+axi_ready_gen                           bready_gen2;  
+axi_ready_gen                           rready_gen2;  
+axi_ready_gen                           awready_gen2;  
+axi_ready_gen                           wready_gen2;  
+axi_ready_gen                           arready_gen2;  
+xil_axi_payload_byte                    data_mem[xil_axi_ulong];  
+myip_v1_0_bfm_1_master_0_0_mst_t          mst_agent_0;
+
+  `BD_WRAPPER DUT(
+      .ARESETN(reset), 
+      .ACLK(clock) 
+    ); 
+  
+initial begin
+     mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms  
+   mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE); 
+   mst_agent_0.set_agent_tag("Master VIP"); 
+   mst_agent_0.set_verbosity(mst_agent_verbosity); 
+   mst_agent_0.start_master(); 
+     $timeformat (-12, 1, " ps", 1);
+  end
+  initial begin
+    reset <= 1'b0;
+    #200ns;
+    reset <= 1'b1;
+    repeat (5) @(negedge clock); 
+  end
+  always #5 clock <= ~clock;
+  initial begin
+      S_AXI_TEST ( );
+
+      #1ns;
+      $finish;
+  end
+task automatic S_AXI_TEST;  
+begin   
+#1; 
+   $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method starts"); 
+   mtestID = 0; 
+   mtestADDR = 64'h00000000; 
+   mtestBurstLength = 0; 
+   mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
+   mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
+   mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
+   mtestCacheType = 0;  
+   mtestProtectionType = 0;  
+   mtestRegion = 0; 
+   mtestQOS = 0; 
+   result_slave = 1; 
+  mtestWDataL[31:0] = 32'h00000001; 
+  for(int i = 0; i < 4;i++) begin 
+  S00_AXI_test_data[i] <= mtestWDataL[31:0];   
+  mst_agent_0.AXI4LITE_WRITE_BURST( 
+  mtestADDR, 
+  mtestProtectionType, 
+  mtestWDataL, 
+  mtestBresp 
+  );   
+  mtestWDataL[31:0] = mtestWDataL[31:0] + 1; 
+  mtestADDR = mtestADDR + 64'h4; 
+  end 
+     $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method completes"); 
+     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method starts"); 
+     mtestID = 0; 
+     mtestADDR = 64'h00000000; 
+     mtestBurstLength = 0; 
+     mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
+     mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
+     mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
+     mtestCacheType = 0;  
+     mtestProtectionType = 0;  
+     mtestRegion = 0; 
+     mtestQOS = 0; 
+ for(int i = 0; i < 4;i++) begin 
+   mst_agent_0.AXI4LITE_READ_BURST( 
+        mtestADDR, 
+        mtestProtectionType, 
+        mtestRDataL, 
+        mtestRresp 
+      ); 
+   mtestADDR = mtestADDR + 64'h4; 
+   COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL); 
+ end 
+     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method completes"); 
+     $display("Sequential read transfers example similar to  AXI VIP READ_BURST method completes"); 
+     $display("---------------------------------------------------------"); 
+     $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); 
+     if ( result_slave ) begin                    
+       $display("PTGEN_TEST: PASSED!");                  
+     end    else begin                                       
+       $display("PTGEN_TEST: FAILED!");                  
+     end                                
+     $display("---------------------------------------------------------"); 
+  end 
+endtask  
+
+endmodule

ip_repo_sources/myip_1.0/example_designs/debug_hw_design/design.tcl

@@ -0,0 +1,118 @@
+
+proc create_ipi_design { offsetfile design_name } {
+
+	create_bd_design $design_name
+	open_bd_design $design_name
+
+	# Create and configure Clock/Reset
+	create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
+	create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
+
+	#Constraints will be provided manually while pin planning.
+		create_bd_port -dir I -type rst reset_rtl
+		set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
+		connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
+		connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
+		set external_reset_port reset_rtl
+		create_bd_port -dir I -type clk clock_rtl
+		connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
+		set external_clock_port clock_rtl
+	
+	#Avoid IPI DRC, make clock port synchronous to reset
+	if { $external_clock_port ne "" && $external_reset_port ne "" } {
+		set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
+	}
+
+	# Connect other sys_reset pins
+	connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
+
+	# Create instance: myip_0, and set properties
+	set myip_0 [ create_bd_cell -type ip -vlnv user.org:user:myip:1.0 myip_0 ]
+
+	# Create instance: jtag_axi_0, and set properties
+	set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
+	set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
+	connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+	# Create instance: axi_peri_interconnect, and set properties
+	set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
+	set_property -dict [ list CONFIG.NUM_SI {1}  ] $axi_peri_interconnect
+	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+	connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
+
+	set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
+	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+	# Connect all clock & reset of myip_0 slave interfaces..
+	connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins myip_0/S00_AXI]
+	connect_bd_net [get_bd_pins myip_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins myip_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+
+	# Auto assign address
+	assign_bd_address
+
+	# Copy all address to myip_v1_0_include.tcl file
+	set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+	upvar 1 $offsetfile offset_file
+	set offset_file "${bd_path}/myip_v1_0_include.tcl"
+	set fp [open $offset_file "w"]
+	puts $fp "# Configuration address parameters"
+
+	set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_myip_0_S00_AXI_* ]]
+	puts $fp "set s00_axi_addr ${offset}"
+
+	close $fp
+}
+
+# Set IP Repository and Update IP Catalogue 
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:myip:1.0]]]]
+set hw_test_file ${ip_path}/example_designs/debug_hw_design/myip_v1_0_hw_test.tcl
+
+set repo_paths [get_property ip_repo_paths [current_fileset]] 
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+	update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+	set design_name "myip_v1_0_hw_${i}"
+	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+		break
+	}
+}
+
+set intf_address_include_file ""
+create_ipi_design intf_address_include_file ${design_name}
+save_bd_design
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+puts "-------------------------------------------------------------------------------------------------"
+puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
+puts "   please perform following steps to test design in targeted board."
+puts "1. Generate bitstream"
+puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
+puts "3. Download generated bitstream"
+puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
+puts "   to every interface present in the peripheral : xilinx.com:user:myip:1.0"
+puts "   : source -notrace ${hw_test_file}"
+puts "-------------------------------------------------------------------------------------------------"
+

ip_repo_sources/myip_1.0/example_designs/debug_hw_design/myip_v1_0_hw_test.tcl

@@ -0,0 +1,45 @@
+# Runtime Tcl commands to interact with - myip_v1_0
+
+# Sourcing design address info tcl
+set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+source ${bd_path}/myip_v1_0_include.tcl
+
+# jtag axi master interface hardware name, change as per your design.
+set jtag_axi_master hw_axi_1
+set ec 0
+
+# hw test script
+# Delete all previous axis transactions
+if { [llength [get_hw_axi_txns -quiet]] } {
+	delete_hw_axi_txn [get_hw_axi_txns -quiet]
+}
+
+
+# Test all lite slaves.
+set wdata_1 abcd1234
+
+# Test: S00_AXI
+# Create a write transaction at s00_axi_addr address
+create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
+# Create a read transaction at s00_axi_addr address
+create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
+# Initiate transactions
+run_hw_axi r_s00_axi_addr
+run_hw_axi w_s00_axi_addr
+run_hw_axi r_s00_axi_addr
+set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
+# Compare read data
+if { $rdata_tmp == $wdata_1 } {
+	puts "Data comparison test pass for - S00_AXI"
+} else {
+	puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
+	inc ec
+}
+
+# Check error flag
+if { $ec == 0 } {
+	 puts "PTGEN_TEST: PASSED!" 
+} else {
+	 puts "PTGEN_TEST: FAILED!" 
+}
+

ip_repo_sources/myip_1.0/hdl/myip_v1_0.vhd

@@ -0,0 +1,118 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity myip_v1_0 is
+	generic (
+		-- Users to add parameters here
+
+		-- User parameters ends
+		-- Do not modify the parameters beyond this line
+
+
+		-- Parameters of Axi Slave Bus Interface S00_AXI
+		C_S00_AXI_DATA_WIDTH	: integer	:= 32;
+		C_S00_AXI_ADDR_WIDTH	: integer	:= 7
+	);
+	port (
+		-- Users to add ports here
+
+		-- User ports ends
+		-- Do not modify the ports beyond this line
+
+
+		-- Ports of Axi Slave Bus Interface S00_AXI
+		s00_axi_aclk	: in std_logic;
+		s00_axi_aresetn	: in std_logic;
+		s00_axi_awaddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
+		s00_axi_awprot	: in std_logic_vector(2 downto 0);
+		s00_axi_awvalid	: in std_logic;
+		s00_axi_awready	: out std_logic;
+		s00_axi_wdata	: in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
+		s00_axi_wstrb	: in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
+		s00_axi_wvalid	: in std_logic;
+		s00_axi_wready	: out std_logic;
+		s00_axi_bresp	: out std_logic_vector(1 downto 0);
+		s00_axi_bvalid	: out std_logic;
+		s00_axi_bready	: in std_logic;
+		s00_axi_araddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
+		s00_axi_arprot	: in std_logic_vector(2 downto 0);
+		s00_axi_arvalid	: in std_logic;
+		s00_axi_arready	: out std_logic;
+		s00_axi_rdata	: out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
+		s00_axi_rresp	: out std_logic_vector(1 downto 0);
+		s00_axi_rvalid	: out std_logic;
+		s00_axi_rready	: in std_logic
+	);
+end myip_v1_0;
+
+architecture arch_imp of myip_v1_0 is
+
+	-- component declaration
+	component myip_v1_0_S00_AXI is
+		generic (
+		C_S_AXI_DATA_WIDTH	: integer	:= 32;
+		C_S_AXI_ADDR_WIDTH	: integer	:= 7
+		);
+		port (
+		S_AXI_ACLK	: in std_logic;
+		S_AXI_ARESETN	: in std_logic;
+		S_AXI_AWADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+		S_AXI_AWPROT	: in std_logic_vector(2 downto 0);
+		S_AXI_AWVALID	: in std_logic;
+		S_AXI_AWREADY	: out std_logic;
+		S_AXI_WDATA	: in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+		S_AXI_WSTRB	: in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
+		S_AXI_WVALID	: in std_logic;
+		S_AXI_WREADY	: out std_logic;
+		S_AXI_BRESP	: out std_logic_vector(1 downto 0);
+		S_AXI_BVALID	: out std_logic;
+		S_AXI_BREADY	: in std_logic;
+		S_AXI_ARADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+		S_AXI_ARPROT	: in std_logic_vector(2 downto 0);
+		S_AXI_ARVALID	: in std_logic;
+		S_AXI_ARREADY	: out std_logic;
+		S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+		S_AXI_RRESP	: out std_logic_vector(1 downto 0);
+		S_AXI_RVALID	: out std_logic;
+		S_AXI_RREADY	: in std_logic
+		);
+	end component myip_v1_0_S00_AXI;
+
+begin
+
+-- Instantiation of Axi Bus Interface S00_AXI
+myip_v1_0_S00_AXI_inst : myip_v1_0_S00_AXI
+	generic map (
+		C_S_AXI_DATA_WIDTH	=> C_S00_AXI_DATA_WIDTH,
+		C_S_AXI_ADDR_WIDTH	=> C_S00_AXI_ADDR_WIDTH
+	)
+	port map (
+		S_AXI_ACLK	=> s00_axi_aclk,
+		S_AXI_ARESETN	=> s00_axi_aresetn,
+		S_AXI_AWADDR	=> s00_axi_awaddr,
+		S_AXI_AWPROT	=> s00_axi_awprot,
+		S_AXI_AWVALID	=> s00_axi_awvalid,
+		S_AXI_AWREADY	=> s00_axi_awready,
+		S_AXI_WDATA	=> s00_axi_wdata,
+		S_AXI_WSTRB	=> s00_axi_wstrb,
+		S_AXI_WVALID	=> s00_axi_wvalid,
+		S_AXI_WREADY	=> s00_axi_wready,
+		S_AXI_BRESP	=> s00_axi_bresp,
+		S_AXI_BVALID	=> s00_axi_bvalid,
+		S_AXI_BREADY	=> s00_axi_bready,
+		S_AXI_ARADDR	=> s00_axi_araddr,
+		S_AXI_ARPROT	=> s00_axi_arprot,
+		S_AXI_ARVALID	=> s00_axi_arvalid,
+		S_AXI_ARREADY	=> s00_axi_arready,
+		S_AXI_RDATA	=> s00_axi_rdata,
+		S_AXI_RRESP	=> s00_axi_rresp,
+		S_AXI_RVALID	=> s00_axi_rvalid,
+		S_AXI_RREADY	=> s00_axi_rready
+	);
+
+	-- Add user logic here
+
+	-- User logic ends
+
+end arch_imp;

ip_repo_sources/myip_1.0/hdl/myip_v1_0_S00_AXI.vhd

@@ -0,0 +1,755 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity myip_v1_0_S00_AXI is
+	generic (
+		-- Users to add parameters here
+
+		-- User parameters ends
+		-- Do not modify the parameters beyond this line
+
+		-- Width of S_AXI data bus
+		C_S_AXI_DATA_WIDTH	: integer	:= 32;
+		-- Width of S_AXI address bus
+		C_S_AXI_ADDR_WIDTH	: integer	:= 7
+	);
+	port (
+		-- Users to add ports here
+
+		-- User ports ends
+		-- Do not modify the ports beyond this line
+
+		-- Global Clock Signal
+		S_AXI_ACLK	: in std_logic;
+		-- Global Reset Signal. This Signal is Active LOW
+		S_AXI_ARESETN	: in std_logic;
+		-- Write address (issued by master, acceped by Slave)
+		S_AXI_AWADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+		-- Write channel Protection type. This signal indicates the
+    		-- privilege and security level of the transaction, and whether
+    		-- the transaction is a data access or an instruction access.
+		S_AXI_AWPROT	: in std_logic_vector(2 downto 0);
+		-- Write address valid. This signal indicates that the master signaling
+    		-- valid write address and control information.
+		S_AXI_AWVALID	: in std_logic;
+		-- Write address ready. This signal indicates that the slave is ready
+    		-- to accept an address and associated control signals.
+		S_AXI_AWREADY	: out std_logic;
+		-- Write data (issued by master, acceped by Slave) 
+		S_AXI_WDATA	: in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+		-- Write strobes. This signal indicates which byte lanes hold
+    		-- valid data. There is one write strobe bit for each eight
+    		-- bits of the write data bus.    
+		S_AXI_WSTRB	: in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
+		-- Write valid. This signal indicates that valid write
+    		-- data and strobes are available.
+		S_AXI_WVALID	: in std_logic;
+		-- Write ready. This signal indicates that the slave
+    		-- can accept the write data.
+		S_AXI_WREADY	: out std_logic;
+		-- Write response. This signal indicates the status
+    		-- of the write transaction.
+		S_AXI_BRESP	: out std_logic_vector(1 downto 0);
+		-- Write response valid. This signal indicates that the channel
+    		-- is signaling a valid write response.
+		S_AXI_BVALID	: out std_logic;
+		-- Response ready. This signal indicates that the master
+    		-- can accept a write response.
+		S_AXI_BREADY	: in std_logic;
+		-- Read address (issued by master, acceped by Slave)
+		S_AXI_ARADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+		-- Protection type. This signal indicates the privilege
+    		-- and security level of the transaction, and whether the
+    		-- transaction is a data access or an instruction access.
+		S_AXI_ARPROT	: in std_logic_vector(2 downto 0);
+		-- Read address valid. This signal indicates that the channel
+    		-- is signaling valid read address and control information.
+		S_AXI_ARVALID	: in std_logic;
+		-- Read address ready. This signal indicates that the slave is
+    		-- ready to accept an address and associated control signals.
+		S_AXI_ARREADY	: out std_logic;
+		-- Read data (issued by slave)
+		S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+		-- Read response. This signal indicates the status of the
+    		-- read transfer.
+		S_AXI_RRESP	: out std_logic_vector(1 downto 0);
+		-- Read valid. This signal indicates that the channel is
+    		-- signaling the required read data.
+		S_AXI_RVALID	: out std_logic;
+		-- Read ready. This signal indicates that the master can
+    		-- accept the read data and response information.
+		S_AXI_RREADY	: in std_logic
+	);
+end myip_v1_0_S00_AXI;
+
+architecture arch_imp of myip_v1_0_S00_AXI is
+
+	-- AXI4LITE signals
+	signal axi_awaddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+	signal axi_awready	: std_logic;
+	signal axi_wready	: std_logic;
+	signal axi_bresp	: std_logic_vector(1 downto 0);
+	signal axi_bvalid	: std_logic;
+	signal axi_araddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+	signal axi_arready	: std_logic;
+	signal axi_rdata	: std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal axi_rresp	: std_logic_vector(1 downto 0);
+	signal axi_rvalid	: std_logic;
+
+	-- Example-specific design signals
+	-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+	-- ADDR_LSB is used for addressing 32/64 bit registers/memories
+	-- ADDR_LSB = 2 for 32 bits (n downto 2)
+	-- ADDR_LSB = 3 for 64 bits (n downto 3)
+	constant ADDR_LSB  : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
+	constant OPT_MEM_ADDR_BITS : integer := 4;
+	------------------------------------------------
+	---- Signals for user logic register space example
+	--------------------------------------------------
+	---- Number of Slave Registers 32
+	signal slv_reg0	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg1	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg2	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg3	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg4	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg5	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg6	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg7	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg8	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg9	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg10	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg11	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg12	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg13	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg14	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg15	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg16	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg17	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg18	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg19	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg20	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg21	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg22	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg23	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg24	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg25	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg26	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg27	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg28	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg29	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg30	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg31	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg_rden	: std_logic;
+	signal slv_reg_wren	: std_logic;
+	signal reg_data_out	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal byte_index	: integer;
+	signal aw_en	: std_logic;
+
+begin
+	-- I/O Connections assignments
+
+	S_AXI_AWREADY	<= axi_awready;
+	S_AXI_WREADY	<= axi_wready;
+	S_AXI_BRESP	<= axi_bresp;
+	S_AXI_BVALID	<= axi_bvalid;
+	S_AXI_ARREADY	<= axi_arready;
+	S_AXI_RDATA	<= axi_rdata;
+	S_AXI_RRESP	<= axi_rresp;
+	S_AXI_RVALID	<= axi_rvalid;
+	-- Implement axi_awready generation
+	-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+	-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+	-- de-asserted when reset is low.
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_awready <= '0';
+	      aw_en <= '1';
+	    else
+	      if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
+	        -- slave is ready to accept write address when
+	        -- there is a valid write address and write data
+	        -- on the write address and data bus. This design 
+	        -- expects no outstanding transactions. 
+	           axi_awready <= '1';
+	           aw_en <= '0';
+	        elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
+	           aw_en <= '1';
+	           axi_awready <= '0';
+	      else
+	        axi_awready <= '0';
+	      end if;
+	    end if;
+	  end if;
+	end process;
+
+	-- Implement axi_awaddr latching
+	-- This process is used to latch the address when both 
+	-- S_AXI_AWVALID and S_AXI_WVALID are valid. 
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_awaddr <= (others => '0');
+	    else
+	      if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
+	        -- Write Address latching
+	        axi_awaddr <= S_AXI_AWADDR;
+	      end if;
+	    end if;
+	  end if;                   
+	end process; 
+
+	-- Implement axi_wready generation
+	-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+	-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
+	-- de-asserted when reset is low. 
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_wready <= '0';
+	    else
+	      if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
+	          -- slave is ready to accept write data when 
+	          -- there is a valid write address and write data
+	          -- on the write address and data bus. This design 
+	          -- expects no outstanding transactions.           
+	          axi_wready <= '1';
+	      else
+	        axi_wready <= '0';
+	      end if;
+	    end if;
+	  end if;
+	end process; 
+
+	-- Implement memory mapped register select and write logic generation
+	-- The write data is accepted and written to memory mapped registers when
+	-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+	-- select byte enables of slave registers while writing.
+	-- These registers are cleared when reset (active low) is applied.
+	-- Slave register write enable is asserted when valid address and data are available
+	-- and the slave is ready to accept the write address and write data.
+	slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
+
+	process (S_AXI_ACLK)
+	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); 
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      slv_reg0 <= (others => '0');
+	      slv_reg1 <= (others => '0');
+	      slv_reg2 <= (others => '0');
+	      slv_reg3 <= (others => '0');
+	      slv_reg4 <= (others => '0');
+	      slv_reg5 <= (others => '0');
+	      slv_reg6 <= (others => '0');
+	      slv_reg7 <= (others => '0');
+	      slv_reg8 <= (others => '0');
+	      slv_reg9 <= (others => '0');
+	      slv_reg10 <= (others => '0');
+	      slv_reg11 <= (others => '0');
+	      slv_reg12 <= (others => '0');
+	      slv_reg13 <= (others => '0');
+	      slv_reg14 <= (others => '0');
+	      slv_reg15 <= (others => '0');
+	      slv_reg16 <= (others => '0');
+	      slv_reg17 <= (others => '0');
+	      slv_reg18 <= (others => '0');
+	      slv_reg19 <= (others => '0');
+	      slv_reg20 <= (others => '0');
+	      slv_reg21 <= (others => '0');
+	      slv_reg22 <= (others => '0');
+	      slv_reg23 <= (others => '0');
+	      slv_reg24 <= (others => '0');
+	      slv_reg25 <= (others => '0');
+	      slv_reg26 <= (others => '0');
+	      slv_reg27 <= (others => '0');
+	      slv_reg28 <= (others => '0');
+	      slv_reg29 <= (others => '0');
+	      slv_reg30 <= (others => '0');
+	      slv_reg31 <= (others => '0');
+	    else
+	      loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
+	      if (slv_reg_wren = '1') then
+	        case loc_addr is
+	          when b"00000" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 0
+	                slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00001" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 1
+	                slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00010" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 2
+	                slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00011" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 3
+	                slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00100" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 4
+	                slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00101" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 5
+	                slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00110" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 6
+	                slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00111" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 7
+	                slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01000" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 8
+	                slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01001" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 9
+	                slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01010" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 10
+	                slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01011" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 11
+	                slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01100" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 12
+	                slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01101" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 13
+	                slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01110" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 14
+	                slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01111" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 15
+	                slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10000" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 16
+	                slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10001" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 17
+	                slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10010" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 18
+	                slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10011" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 19
+	                slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10100" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 20
+	                slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10101" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 21
+	                slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10110" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 22
+	                slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10111" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 23
+	                slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11000" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 24
+	                slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11001" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 25
+	                slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11010" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 26
+	                slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11011" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 27
+	                slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11100" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 28
+	                slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11101" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 29
+	                slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11110" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 30
+	                slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11111" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 31
+	                slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when others =>
+	            slv_reg0 <= slv_reg0;
+	            slv_reg1 <= slv_reg1;
+	            slv_reg2 <= slv_reg2;
+	            slv_reg3 <= slv_reg3;
+	            slv_reg4 <= slv_reg4;
+	            slv_reg5 <= slv_reg5;
+	            slv_reg6 <= slv_reg6;
+	            slv_reg7 <= slv_reg7;
+	            slv_reg8 <= slv_reg8;
+	            slv_reg9 <= slv_reg9;
+	            slv_reg10 <= slv_reg10;
+	            slv_reg11 <= slv_reg11;
+	            slv_reg12 <= slv_reg12;
+	            slv_reg13 <= slv_reg13;
+	            slv_reg14 <= slv_reg14;
+	            slv_reg15 <= slv_reg15;
+	            slv_reg16 <= slv_reg16;
+	            slv_reg17 <= slv_reg17;
+	            slv_reg18 <= slv_reg18;
+	            slv_reg19 <= slv_reg19;
+	            slv_reg20 <= slv_reg20;
+	            slv_reg21 <= slv_reg21;
+	            slv_reg22 <= slv_reg22;
+	            slv_reg23 <= slv_reg23;
+	            slv_reg24 <= slv_reg24;
+	            slv_reg25 <= slv_reg25;
+	            slv_reg26 <= slv_reg26;
+	            slv_reg27 <= slv_reg27;
+	            slv_reg28 <= slv_reg28;
+	            slv_reg29 <= slv_reg29;
+	            slv_reg30 <= slv_reg30;
+	            slv_reg31 <= slv_reg31;
+	        end case;
+	      end if;
+	    end if;
+	  end if;                   
+	end process; 
+
+	-- Implement write response logic generation
+	-- The write response and response valid signals are asserted by the slave 
+	-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
+	-- This marks the acceptance of address and indicates the status of 
+	-- write transaction.
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_bvalid  <= '0';
+	      axi_bresp   <= "00"; --need to work more on the responses
+	    else
+	      if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0'  ) then
+	        axi_bvalid <= '1';
+	        axi_bresp  <= "00"; 
+	      elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then   --check if bready is asserted while bvalid is high)
+	        axi_bvalid <= '0';                                 -- (there is a possibility that bready is always asserted high)
+	      end if;
+	    end if;
+	  end if;                   
+	end process; 
+
+	-- Implement axi_arready generation
+	-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
+	-- S_AXI_ARVALID is asserted. axi_awready is 
+	-- de-asserted when reset (active low) is asserted. 
+	-- The read address is also latched when S_AXI_ARVALID is 
+	-- asserted. axi_araddr is reset to zero on reset assertion.
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_arready <= '0';
+	      axi_araddr  <= (others => '1');
+	    else
+	      if (axi_arready = '0' and S_AXI_ARVALID = '1') then
+	        -- indicates that the slave has acceped the valid read address
+	        axi_arready <= '1';
+	        -- Read Address latching 
+	        axi_araddr  <= S_AXI_ARADDR;           
+	      else
+	        axi_arready <= '0';
+	      end if;
+	    end if;
+	  end if;                   
+	end process; 
+
+	-- Implement axi_arvalid generation
+	-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
+	-- S_AXI_ARVALID and axi_arready are asserted. The slave registers 
+	-- data are available on the axi_rdata bus at this instance. The 
+	-- assertion of axi_rvalid marks the validity of read data on the 
+	-- bus and axi_rresp indicates the status of read transaction.axi_rvalid 
+	-- is deasserted on reset (active low). axi_rresp and axi_rdata are 
+	-- cleared to zero on reset (active low).  
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then
+	    if S_AXI_ARESETN = '0' then
+	      axi_rvalid <= '0';
+	      axi_rresp  <= "00";
+	    else
+	      if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
+	        -- Valid read data is available at the read data bus
+	        axi_rvalid <= '1';
+	        axi_rresp  <= "00"; -- 'OKAY' response
+	      elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
+	        -- Read data is accepted by the master
+	        axi_rvalid <= '0';
+	      end if;            
+	    end if;
+	  end if;
+	end process;
+
+	-- Implement memory mapped register select and read logic generation
+	-- Slave register read enable is asserted when valid address is available
+	-- and the slave is ready to accept the read address.
+	slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
+
+	process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
+	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
+	begin
+	    -- Address decoding for reading registers
+	    loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
+	    case loc_addr is
+	      when b"00000" =>
+	        reg_data_out <= slv_reg0;
+	      when b"00001" =>
+	        reg_data_out <= slv_reg1;
+	      when b"00010" =>
+	        reg_data_out <= slv_reg2;
+	      when b"00011" =>
+	        reg_data_out <= slv_reg3;
+	      when b"00100" =>
+	        reg_data_out <= slv_reg4;
+	      when b"00101" =>
+	        reg_data_out <= slv_reg5;
+	      when b"00110" =>
+	        reg_data_out <= slv_reg6;
+	      when b"00111" =>
+	        reg_data_out <= slv_reg7;
+	      when b"01000" =>
+	        reg_data_out <= slv_reg8;
+	      when b"01001" =>
+	        reg_data_out <= slv_reg9;
+	      when b"01010" =>
+	        reg_data_out <= slv_reg10;
+	      when b"01011" =>
+	        reg_data_out <= slv_reg11;
+	      when b"01100" =>
+	        reg_data_out <= slv_reg12;
+	      when b"01101" =>
+	        reg_data_out <= slv_reg13;
+	      when b"01110" =>
+	        reg_data_out <= slv_reg14;
+	      when b"01111" =>
+	        reg_data_out <= slv_reg15;
+	      when b"10000" =>
+	        reg_data_out <= slv_reg16;
+	      when b"10001" =>
+	        reg_data_out <= slv_reg17;
+	      when b"10010" =>
+	        reg_data_out <= slv_reg18;
+	      when b"10011" =>
+	        reg_data_out <= slv_reg19;
+	      when b"10100" =>
+	        reg_data_out <= slv_reg20;
+	      when b"10101" =>
+	        reg_data_out <= slv_reg21;
+	      when b"10110" =>
+	        reg_data_out <= slv_reg22;
+	      when b"10111" =>
+	        reg_data_out <= slv_reg23;
+	      when b"11000" =>
+	        reg_data_out <= slv_reg24;
+	      when b"11001" =>
+	        reg_data_out <= slv_reg25;
+	      when b"11010" =>
+	        reg_data_out <= slv_reg26;
+	      when b"11011" =>
+	        reg_data_out <= slv_reg27;
+	      when b"11100" =>
+	        reg_data_out <= slv_reg28;
+	      when b"11101" =>
+	        reg_data_out <= slv_reg29;
+	      when b"11110" =>
+	        reg_data_out <= slv_reg30;
+	      when b"11111" =>
+	        reg_data_out <= slv_reg31;
+	      when others =>
+	        reg_data_out  <= (others => '0');
+	    end case;
+	end process; 
+
+	-- Output register or memory read data
+	process( S_AXI_ACLK ) is
+	begin
+	  if (rising_edge (S_AXI_ACLK)) then
+	    if ( S_AXI_ARESETN = '0' ) then
+	      axi_rdata  <= (others => '0');
+	    else
+	      if (slv_reg_rden = '1') then
+	        -- When there is a valid read address (S_AXI_ARVALID) with 
+	        -- acceptance of read address by the slave (axi_arready), 
+	        -- output the read dada 
+	        -- Read address mux
+	          axi_rdata <= reg_data_out;     -- register read data
+	      end if;   
+	    end if;
+	  end if;
+	end process;
+
+
+	-- Add user logic here
+
+	-- User logic ends
+
+end arch_imp;

ip_repo_sources/myip_1.0/xgui/myip_v1_0.tcl

@@ -0,0 +1,62 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox]
+  set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH}
+  set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}]
+  set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH}
+  ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to validate C_S00_AXI_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to validate C_S00_AXI_ADDR_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+	# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+	# Procedure called to validate C_S00_AXI_BASEADDR
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+	# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+	# Procedure called to validate C_S00_AXI_HIGHADDR
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
+}
+

ip_repo_sources/neuron_1.0/bd/bd.tcl

@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {                                                                   
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	set full_sbusif_list [list  ]
+			                                                                                                 
+	foreach busif $all_busif {                                                                               
+		if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {                            
+			set busif_param_list [list]                                                                      
+			set busif_name [get_property NAME $busif]					                                     
+			if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {					         
+			    continue                                                                                     
+			}                                                                                                
+			foreach tparam $axi_standard_param_list {                                                        
+				lappend busif_param_list "C_${busif_name}_${tparam}"                                       
+			}                                                                                                
+			bd::mark_propagate_only $cell_handle $busif_param_list			                                 
+		}		                                                                                             
+	}                                                                                                        
+}
+
+
+proc pre_propagate {cellpath otherInfo } {                                                           
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	                                                                                                         
+	foreach busif $all_busif {	                                                                             
+		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
+			continue                                                                                         
+		}                                                                                                    
+		if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {                           
+			continue                                                                                         
+		}			                                                                                         
+		                                                                                                     
+		set busif_name [get_property NAME $busif]			                                                 
+		foreach tparam $axi_standard_param_list {		                                                     
+			set busif_param_name "C_${busif_name}_${tparam}"			                                     
+			                                                                                                 
+			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
+			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
+			                                                                                                 
+			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
+				if { $val_on_cell != "" } {                                                                  
+					set_property CONFIG.${tparam} $val_on_cell $busif                                        
+				}                                                                                            
+			}			                                                                                     
+		}		                                                                                             
+	}                                                                                                        
+}
+
+
+proc propagate {cellpath otherInfo } {                                                               
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	                                                                                                         
+	foreach busif $all_busif {                                                                               
+		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
+			continue                                                                                         
+		}                                                                                                    
+		if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {                            
+			continue                                                                                         
+		}			                                                                                         
+	                                                                                                         
+		set busif_name [get_property NAME $busif]		                                                     
+		foreach tparam $axi_standard_param_list {			                                                 
+			set busif_param_name "C_${busif_name}_${tparam}"			                                     
+                                                                                                             
+			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
+			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
+			                                                                                                 
+			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
+				#override property of bd_interface_net to bd_cell -- only for slaves.  May check for supported values..
+				if { $val_on_cell_intf_pin != "" } {                                                         
+					set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle               
+				}                                                                                            
+			}                                                                                                
+		}		                                                                                             
+	}                                                                                                        
+}
+

ip_repo_sources/neuron_1.0/component.xml

@@ -0,0 +1,945 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>user.org</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>neuron</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>S00_AXI</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
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+        <xilinx:tag xilinx:name="ui.data.coregen.dd@196805a2_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@17893ce3_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@6d04b983_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@394af5a1_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@491eef8_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@3ad18d25_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@3494e786_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@4d9dac41_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@15c987d_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@564b3e5c_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@5cdeb362_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@7a0e5435_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@2d470ce7_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@28c52e18_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@56a64117_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@169e0b13_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@3a6e36b8_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@575472ac_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@1f6dc6fe_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@ff67f3b_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@7e53ec5b_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@5fa7cc2d_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@37f09b93_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@16cb8134_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@59cfdc3a_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@659a0dcb_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@6713b819_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@1ac3b1c3_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_1.0</xilinx:tag>
+      </xilinx:tags>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="0312d308"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ed1368d5"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0c1d33f5"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="48e360dd"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="a0a6f17f"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="ae442535"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>

ip_repo_sources/neuron_1.0/drivers/neuron_v1_0/data/neuron.mdd

@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER neuron
+	OPTION supported_peripherals = (neuron);
+	OPTION copyfiles = all;
+	OPTION VERSION = 1.0;
+	OPTION NAME = neuron;
+END DRIVER

ip_repo_sources/neuron_1.0/drivers/neuron_v1_0/data/neuron.tcl

@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+	xdefine_include_file $drv_handle "xparameters.h" "neuron" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}

ip_repo_sources/neuron_1.0/drivers/neuron_v1_0/src/Makefile

@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling neuron..."
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}

ip_repo_sources/neuron_1.0/drivers/neuron_v1_0/src/neuron.c

@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "neuron.h"
+
+/************************** Function Definitions ***************************/

ip_repo_sources/neuron_1.0/drivers/neuron_v1_0/src/neuron.h

@@ -0,0 +1,107 @@
+
+#ifndef NEURON_H
+#define NEURON_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define NEURON_S00_AXI_SLV_REG0_OFFSET 0
+#define NEURON_S00_AXI_SLV_REG1_OFFSET 4
+#define NEURON_S00_AXI_SLV_REG2_OFFSET 8
+#define NEURON_S00_AXI_SLV_REG3_OFFSET 12
+#define NEURON_S00_AXI_SLV_REG4_OFFSET 16
+#define NEURON_S00_AXI_SLV_REG5_OFFSET 20
+#define NEURON_S00_AXI_SLV_REG6_OFFSET 24
+#define NEURON_S00_AXI_SLV_REG7_OFFSET 28
+#define NEURON_S00_AXI_SLV_REG8_OFFSET 32
+#define NEURON_S00_AXI_SLV_REG9_OFFSET 36
+#define NEURON_S00_AXI_SLV_REG10_OFFSET 40
+#define NEURON_S00_AXI_SLV_REG11_OFFSET 44
+#define NEURON_S00_AXI_SLV_REG12_OFFSET 48
+#define NEURON_S00_AXI_SLV_REG13_OFFSET 52
+#define NEURON_S00_AXI_SLV_REG14_OFFSET 56
+#define NEURON_S00_AXI_SLV_REG15_OFFSET 60
+#define NEURON_S00_AXI_SLV_REG16_OFFSET 64
+#define NEURON_S00_AXI_SLV_REG17_OFFSET 68
+#define NEURON_S00_AXI_SLV_REG18_OFFSET 72
+#define NEURON_S00_AXI_SLV_REG19_OFFSET 76
+#define NEURON_S00_AXI_SLV_REG20_OFFSET 80
+#define NEURON_S00_AXI_SLV_REG21_OFFSET 84
+#define NEURON_S00_AXI_SLV_REG22_OFFSET 88
+#define NEURON_S00_AXI_SLV_REG23_OFFSET 92
+#define NEURON_S00_AXI_SLV_REG24_OFFSET 96
+#define NEURON_S00_AXI_SLV_REG25_OFFSET 100
+#define NEURON_S00_AXI_SLV_REG26_OFFSET 104
+#define NEURON_S00_AXI_SLV_REG27_OFFSET 108
+#define NEURON_S00_AXI_SLV_REG28_OFFSET 112
+#define NEURON_S00_AXI_SLV_REG29_OFFSET 116
+#define NEURON_S00_AXI_SLV_REG30_OFFSET 120
+#define NEURON_S00_AXI_SLV_REG31_OFFSET 124
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a NEURON register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the NEURONdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void NEURON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define NEURON_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a NEURON register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the NEURON device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 NEURON_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define NEURON_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the NEURON instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus NEURON_Reg_SelfTest(void * baseaddr_p);
+
+#endif // NEURON_H

ip_repo_sources/neuron_1.0/drivers/neuron_v1_0/src/neuron_selftest.c

@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "neuron.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the NEURONinstance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus NEURON_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  NEURON_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( NEURON_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}

ip_repo_sources/neuron_1.0/example_designs/bfm_design/design.tcl

@@ -0,0 +1,88 @@
+proc create_ipi_design { offsetfile design_name } {
+	create_bd_design $design_name
+	open_bd_design $design_name
+
+	# Create Clock and Reset Ports
+	set ACLK [ create_bd_port -dir I -type clk ACLK ]
+	set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
+	set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
+	set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $ARESETN
+	set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
+
+	# Create instance: neuron_0, and set properties
+	set neuron_0 [ create_bd_cell -type ip -vlnv user.org:user:neuron:1.0 neuron_0]
+
+	# Create instance: master_0, and set properties
+	set master_0 [ create_bd_cell -type ip -vlnv  xilinx.com:ip:axi_vip master_0]
+	set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
+
+	# Create interface connections
+	connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins neuron_0/S00_AXI]
+
+	# Create port connections
+	connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins neuron_0/S00_AXI_ACLK]
+	connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins neuron_0/S00_AXI_ARESETN]
+set_property target_simulator XSim [current_project]
+set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
+
+	# Auto assign address
+	assign_bd_address
+
+	# Copy all address to interface_address.vh file
+	set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
+	upvar 1 $offsetfile offset_file
+	set offset_file "${bd_path}/neuron_v1_0_tb_include.svh"
+	set fp [open $offset_file "w"]
+	puts $fp "`ifndef neuron_v1_0_tb_include_vh_"
+	puts $fp "`define neuron_v1_0_tb_include_vh_\n"
+	puts $fp "//Configuration current bd names"
+	puts $fp "`define BD_NAME ${design_name}"
+	puts $fp "`define BD_INST_NAME ${design_name}_i"
+	puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
+	puts $fp "//Configuration address parameters"
+
+	puts $fp "`endif"
+	close $fp
+}
+
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:neuron:1.0]]]]
+set test_bench_file ${ip_path}/example_designs/bfm_design/neuron_v1_0_tb.sv
+set interface_address_vh_file ""
+
+# Set IP Repository and Update IP Catalogue 
+set repo_paths [get_property ip_repo_paths [current_fileset]] 
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+	update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+	set design_name "neuron_v1_0_bfm_${i}"
+	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+		break
+	}
+}
+
+create_ipi_design interface_address_vh_file ${design_name}
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+import_files -fileset sim_1 -norecurse -force $test_bench_file
+remove_files -quiet -fileset sim_1 neuron_v1_0_tb_include.vh
+import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
+set_property top neuron_v1_0_tb [get_filesets sim_1]
+set_property top_lib {} [get_filesets sim_1]
+set_property top_file {} [get_filesets sim_1]
+launch_simulation -simset sim_1 -mode behavioral

ip_repo_sources/neuron_1.0/example_designs/bfm_design/neuron_v1_0_tb.sv

@@ -0,0 +1,197 @@
+
+`timescale 1ns / 1ps
+`include "neuron_v1_0_tb_include.svh"
+
+import axi_vip_pkg::*;
+import neuron_v1_0_bfm_1_master_0_0_pkg::*;
+
+module neuron_v1_0_tb();
+
+
+xil_axi_uint                            error_cnt = 0;
+xil_axi_uint                            comparison_cnt = 0;
+axi_transaction                         wr_transaction;   
+axi_transaction                         rd_transaction;   
+axi_monitor_transaction                 mst_monitor_transaction;  
+axi_monitor_transaction                 master_moniter_transaction_queue[$];  
+xil_axi_uint                            master_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 mst_scb_transaction;  
+axi_monitor_transaction                 passthrough_monitor_transaction;  
+axi_monitor_transaction                 passthrough_master_moniter_transaction_queue[$];  
+xil_axi_uint                            passthrough_master_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 passthrough_mst_scb_transaction;  
+axi_monitor_transaction                 passthrough_slave_moniter_transaction_queue[$];  
+xil_axi_uint                            passthrough_slave_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 passthrough_slv_scb_transaction;  
+axi_monitor_transaction                 slv_monitor_transaction;  
+axi_monitor_transaction                 slave_moniter_transaction_queue[$];  
+xil_axi_uint                            slave_moniter_transaction_queue_size =0;  
+axi_monitor_transaction                 slv_scb_transaction;  
+xil_axi_uint                           mst_agent_verbosity = 0;  
+xil_axi_uint                           slv_agent_verbosity = 0;  
+xil_axi_uint                           passthrough_agent_verbosity = 0;  
+bit                                     clock;
+bit                                     reset;
+integer result_slave;  
+bit [31:0] S00_AXI_test_data[3:0]; 
+ localparam LC_AXI_BURST_LENGTH = 8; 
+ localparam LC_AXI_DATA_WIDTH = 32; 
+task automatic COMPARE_DATA; 
+  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected; 
+  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual; 
+  begin 
+    if (expected === 'hx || actual === 'hx) begin 
+      $display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); 
+ result_slave = 0;    $stop; 
+  end 
+  if (actual != expected) begin 
+    $display("TESTBENCH ERROR! Data expected is not equal to actual.",     " expected = 0x%h",expected,     " actual   = 0x%h",actual); 
+    result_slave = 0; 
+    $stop; 
+  end 
+  else  
+    begin 
+     $display("TESTBENCH Passed! Data expected is equal to actual.", 
+              " expected = 0x%h",expected,               " actual   = 0x%h",actual); 
+    end 
+  end 
+endtask 
+integer                                 i; 
+integer                                 j;  
+xil_axi_uint                            trans_cnt_before_switch = 48;  
+xil_axi_uint                            passthrough_cmd_switch_cnt = 0;  
+event                                   passthrough_mastermode_start_event;  
+event                                   passthrough_mastermode_end_event;  
+event                                   passthrough_slavemode_end_event;  
+xil_axi_uint                            mtestID;  
+xil_axi_ulong                           mtestADDR;  
+xil_axi_len_t                           mtestBurstLength;  
+xil_axi_size_t                          mtestDataSize;   
+xil_axi_burst_t                         mtestBurstType;   
+xil_axi_lock_t                          mtestLOCK;  
+xil_axi_cache_t                         mtestCacheType = 0;  
+xil_axi_prot_t                          mtestProtectionType = 3'b000;  
+xil_axi_region_t                        mtestRegion = 4'b000;  
+xil_axi_qos_t                           mtestQOS = 4'b000;  
+xil_axi_data_beat                       dbeat;  
+xil_axi_data_beat [255:0]               mtestWUSER;   
+xil_axi_data_beat                       mtestAWUSER = 'h0;  
+xil_axi_data_beat                       mtestARUSER = 0;  
+xil_axi_data_beat [255:0]               mtestRUSER;      
+xil_axi_uint                            mtestBUSER = 0;  
+xil_axi_resp_t                          mtestBresp;  
+xil_axi_resp_t[255:0]                   mtestRresp;  
+bit [63:0]                              mtestWDataL; 
+bit [63:0]                              mtestRDataL; 
+axi_transaction                         pss_wr_transaction;   
+axi_transaction                         pss_rd_transaction;   
+axi_transaction                         reactive_transaction;   
+axi_transaction                         rd_payload_transaction;  
+axi_transaction                         wr_rand;  
+axi_transaction                         rd_rand;  
+axi_transaction                         wr_reactive;  
+axi_transaction                         rd_reactive;  
+axi_transaction                         wr_reactive2;   
+axi_transaction                         rd_reactive2;  
+axi_ready_gen                           bready_gen;  
+axi_ready_gen                           rready_gen;  
+axi_ready_gen                           awready_gen;  
+axi_ready_gen                           wready_gen;  
+axi_ready_gen                           arready_gen;  
+axi_ready_gen                           bready_gen2;  
+axi_ready_gen                           rready_gen2;  
+axi_ready_gen                           awready_gen2;  
+axi_ready_gen                           wready_gen2;  
+axi_ready_gen                           arready_gen2;  
+xil_axi_payload_byte                    data_mem[xil_axi_ulong];  
+neuron_v1_0_bfm_1_master_0_0_mst_t          mst_agent_0;
+
+  `BD_WRAPPER DUT(
+      .ARESETN(reset), 
+      .ACLK(clock) 
+    ); 
+  
+initial begin
+     mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms  
+   mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE); 
+   mst_agent_0.set_agent_tag("Master VIP"); 
+   mst_agent_0.set_verbosity(mst_agent_verbosity); 
+   mst_agent_0.start_master(); 
+     $timeformat (-12, 1, " ps", 1);
+  end
+  initial begin
+    reset <= 1'b0;
+    #200ns;
+    reset <= 1'b1;
+    repeat (5) @(negedge clock); 
+  end
+  always #5 clock <= ~clock;
+  initial begin
+      S_AXI_TEST ( );
+
+      #1ns;
+      $finish;
+  end
+task automatic S_AXI_TEST;  
+begin   
+#1; 
+   $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method starts"); 
+   mtestID = 0; 
+   mtestADDR = 64'h00000000; 
+   mtestBurstLength = 0; 
+   mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
+   mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
+   mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
+   mtestCacheType = 0;  
+   mtestProtectionType = 0;  
+   mtestRegion = 0; 
+   mtestQOS = 0; 
+   result_slave = 1; 
+  mtestWDataL[31:0] = 32'h00000001; 
+  for(int i = 0; i < 4;i++) begin 
+  S00_AXI_test_data[i] <= mtestWDataL[31:0];   
+  mst_agent_0.AXI4LITE_WRITE_BURST( 
+  mtestADDR, 
+  mtestProtectionType, 
+  mtestWDataL, 
+  mtestBresp 
+  );   
+  mtestWDataL[31:0] = mtestWDataL[31:0] + 1; 
+  mtestADDR = mtestADDR + 64'h4; 
+  end 
+     $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method completes"); 
+     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method starts"); 
+     mtestID = 0; 
+     mtestADDR = 64'h00000000; 
+     mtestBurstLength = 0; 
+     mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
+     mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
+     mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
+     mtestCacheType = 0;  
+     mtestProtectionType = 0;  
+     mtestRegion = 0; 
+     mtestQOS = 0; 
+ for(int i = 0; i < 4;i++) begin 
+   mst_agent_0.AXI4LITE_READ_BURST( 
+        mtestADDR, 
+        mtestProtectionType, 
+        mtestRDataL, 
+        mtestRresp 
+      ); 
+   mtestADDR = mtestADDR + 64'h4; 
+   COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL); 
+ end 
+     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method completes"); 
+     $display("Sequential read transfers example similar to  AXI VIP READ_BURST method completes"); 
+     $display("---------------------------------------------------------"); 
+     $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); 
+     if ( result_slave ) begin                    
+       $display("PTGEN_TEST: PASSED!");                  
+     end    else begin                                       
+       $display("PTGEN_TEST: FAILED!");                  
+     end                                
+     $display("---------------------------------------------------------"); 
+  end 
+endtask  
+
+endmodule

ip_repo_sources/neuron_1.0/example_designs/debug_hw_design/design.tcl

@@ -0,0 +1,118 @@
+
+proc create_ipi_design { offsetfile design_name } {
+
+	create_bd_design $design_name
+	open_bd_design $design_name
+
+	# Create and configure Clock/Reset
+	create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
+	create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
+
+	#Constraints will be provided manually while pin planning.
+		create_bd_port -dir I -type rst reset_rtl
+		set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
+		connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
+		connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
+		set external_reset_port reset_rtl
+		create_bd_port -dir I -type clk clock_rtl
+		connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
+		set external_clock_port clock_rtl
+	
+	#Avoid IPI DRC, make clock port synchronous to reset
+	if { $external_clock_port ne "" && $external_reset_port ne "" } {
+		set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
+	}
+
+	# Connect other sys_reset pins
+	connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
+
+	# Create instance: neuron_0, and set properties
+	set neuron_0 [ create_bd_cell -type ip -vlnv user.org:user:neuron:1.0 neuron_0 ]
+
+	# Create instance: jtag_axi_0, and set properties
+	set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
+	set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
+	connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+	# Create instance: axi_peri_interconnect, and set properties
+	set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
+	set_property -dict [ list CONFIG.NUM_SI {1}  ] $axi_peri_interconnect
+	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+	connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
+
+	set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
+	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+	# Connect all clock & reset of neuron_0 slave interfaces..
+	connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins neuron_0/S00_AXI]
+	connect_bd_net [get_bd_pins neuron_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
+	connect_bd_net [get_bd_pins neuron_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+
+	# Auto assign address
+	assign_bd_address
+
+	# Copy all address to neuron_v1_0_include.tcl file
+	set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+	upvar 1 $offsetfile offset_file
+	set offset_file "${bd_path}/neuron_v1_0_include.tcl"
+	set fp [open $offset_file "w"]
+	puts $fp "# Configuration address parameters"
+
+	set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_neuron_0_S00_AXI_* ]]
+	puts $fp "set s00_axi_addr ${offset}"
+
+	close $fp
+}
+
+# Set IP Repository and Update IP Catalogue 
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:neuron:1.0]]]]
+set hw_test_file ${ip_path}/example_designs/debug_hw_design/neuron_v1_0_hw_test.tcl
+
+set repo_paths [get_property ip_repo_paths [current_fileset]] 
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+	update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+	set design_name "neuron_v1_0_hw_${i}"
+	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+		break
+	}
+}
+
+set intf_address_include_file ""
+create_ipi_design intf_address_include_file ${design_name}
+save_bd_design
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+puts "-------------------------------------------------------------------------------------------------"
+puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
+puts "   please perform following steps to test design in targeted board."
+puts "1. Generate bitstream"
+puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
+puts "3. Download generated bitstream"
+puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
+puts "   to every interface present in the peripheral : xilinx.com:user:myip:1.0"
+puts "   : source -notrace ${hw_test_file}"
+puts "-------------------------------------------------------------------------------------------------"
+

ip_repo_sources/neuron_1.0/example_designs/debug_hw_design/neuron_v1_0_hw_test.tcl

@@ -0,0 +1,45 @@
+# Runtime Tcl commands to interact with - neuron_v1_0
+
+# Sourcing design address info tcl
+set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+source ${bd_path}/neuron_v1_0_include.tcl
+
+# jtag axi master interface hardware name, change as per your design.
+set jtag_axi_master hw_axi_1
+set ec 0
+
+# hw test script
+# Delete all previous axis transactions
+if { [llength [get_hw_axi_txns -quiet]] } {
+	delete_hw_axi_txn [get_hw_axi_txns -quiet]
+}
+
+
+# Test all lite slaves.
+set wdata_1 abcd1234
+
+# Test: S00_AXI
+# Create a write transaction at s00_axi_addr address
+create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
+# Create a read transaction at s00_axi_addr address
+create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
+# Initiate transactions
+run_hw_axi r_s00_axi_addr
+run_hw_axi w_s00_axi_addr
+run_hw_axi r_s00_axi_addr
+set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
+# Compare read data
+if { $rdata_tmp == $wdata_1 } {
+	puts "Data comparison test pass for - S00_AXI"
+} else {
+	puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
+	inc ec
+}
+
+# Check error flag
+if { $ec == 0 } {
+	 puts "PTGEN_TEST: PASSED!" 
+} else {
+	 puts "PTGEN_TEST: FAILED!" 
+}
+

ip_repo_sources/neuron_1.0/hdl/neuron_v1_0.vhd

@@ -0,0 +1,117 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity neuron_v1_0 is
+	generic (
+		-- Users to add parameters here
+
+		-- User parameters ends
+		-- Do not modify the parameters beyond this line
+
+
+		-- Parameters of Axi Slave Bus Interface S00_AXI
+		C_S00_AXI_DATA_WIDTH	: integer	:= 32;
+		C_S00_AXI_ADDR_WIDTH	: integer	:= 7
+	);
+	port (
+		-- Users to add ports here
+
+		-- User ports ends
+		-- Do not modify the ports beyond this line
+
+
+		-- Ports of Axi Slave Bus Interface S00_AXI
+		s00_axi_aclk	: in std_logic;
+		s00_axi_aresetn	: in std_logic;
+		s00_axi_awaddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
+		s00_axi_awprot	: in std_logic_vector(2 downto 0);
+		s00_axi_awvalid	: in std_logic;
+		s00_axi_awready	: out std_logic;
+		s00_axi_wdata	: in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
+		s00_axi_wstrb	: in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
+		s00_axi_wvalid	: in std_logic;
+		s00_axi_wready	: out std_logic;
+		s00_axi_bresp	: out std_logic_vector(1 downto 0);
+		s00_axi_bvalid	: out std_logic;
+		s00_axi_bready	: in std_logic;
+		s00_axi_araddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
+		s00_axi_arprot	: in std_logic_vector(2 downto 0);
+		s00_axi_arvalid	: in std_logic;
+		s00_axi_arready	: out std_logic;
+		s00_axi_rdata	: out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
+		s00_axi_rresp	: out std_logic_vector(1 downto 0);
+		s00_axi_rvalid	: out std_logic;
+		s00_axi_rready	: in std_logic
+	);
+end neuron_v1_0;
+
+architecture arch_imp of neuron_v1_0 is
+
+	-- component declaration
+	component neuron_v1_0_S00_AXI is
+		generic (
+		C_S_AXI_DATA_WIDTH	: integer	:= 32;
+		C_S_AXI_ADDR_WIDTH	: integer	:= 7
+		);
+		port (
+		S_AXI_ACLK	: in std_logic;
+		S_AXI_ARESETN	: in std_logic;
+		S_AXI_AWADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+		S_AXI_AWPROT	: in std_logic_vector(2 downto 0);
+		S_AXI_AWVALID	: in std_logic;
+		S_AXI_AWREADY	: out std_logic;
+		S_AXI_WDATA	: in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+		S_AXI_WSTRB	: in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
+		S_AXI_WVALID	: in std_logic;
+		S_AXI_WREADY	: out std_logic;
+		S_AXI_BRESP	: out std_logic_vector(1 downto 0);
+		S_AXI_BVALID	: out std_logic;
+		S_AXI_BREADY	: in std_logic;
+		S_AXI_ARADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+		S_AXI_ARPROT	: in std_logic_vector(2 downto 0);
+		S_AXI_ARVALID	: in std_logic;
+		S_AXI_ARREADY	: out std_logic;
+		S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+		S_AXI_RRESP	: out std_logic_vector(1 downto 0);
+		S_AXI_RVALID	: out std_logic;
+		S_AXI_RREADY	: in std_logic
+		);
+	end component neuron_v1_0_S00_AXI;
+
+begin
+
+-- Instantiation of Axi Bus Interface S00_AXI
+neuron_v1_0_S00_AXI_inst : neuron_v1_0_S00_AXI
+	generic map (
+		C_S_AXI_DATA_WIDTH	=> C_S00_AXI_DATA_WIDTH,
+		C_S_AXI_ADDR_WIDTH	=> C_S00_AXI_ADDR_WIDTH
+	)
+	port map (
+		S_AXI_ACLK	=> s00_axi_aclk,
+		S_AXI_ARESETN	=> s00_axi_aresetn,
+		S_AXI_AWADDR	=> s00_axi_awaddr,
+		S_AXI_AWPROT	=> s00_axi_awprot,
+		S_AXI_AWVALID	=> s00_axi_awvalid,
+		S_AXI_AWREADY	=> s00_axi_awready,
+		S_AXI_WDATA	=> s00_axi_wdata,
+		S_AXI_WSTRB	=> s00_axi_wstrb,
+		S_AXI_WVALID	=> s00_axi_wvalid,
+		S_AXI_WREADY	=> s00_axi_wready,
+		S_AXI_BRESP	=> s00_axi_bresp,
+		S_AXI_BVALID	=> s00_axi_bvalid,
+		S_AXI_BREADY	=> s00_axi_bready,
+		S_AXI_ARADDR	=> s00_axi_araddr,
+		S_AXI_ARPROT	=> s00_axi_arprot,
+		S_AXI_ARVALID	=> s00_axi_arvalid,
+		S_AXI_ARREADY	=> s00_axi_arready,
+		S_AXI_RDATA	=> s00_axi_rdata,
+		S_AXI_RRESP	=> s00_axi_rresp,
+		S_AXI_RVALID	=> s00_axi_rvalid,
+		S_AXI_RREADY	=> s00_axi_rready
+	);
+
+	-- Add user logic here
+	-- User logic ends
+
+end arch_imp;

ip_repo_sources/neuron_1.0/hdl/neuron_v1_0_S00_AXI.vhd

@@ -0,0 +1,812 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.myPackage.ALL;
+
+entity neuron_v1_0_S00_AXI is
+	generic (
+		-- Users to add parameters here
+
+		-- User parameters ends
+		-- Do not modify the parameters beyond this line
+
+		-- Width of S_AXI data bus
+		C_S_AXI_DATA_WIDTH	: integer	:= 32;
+		-- Width of S_AXI address bus
+		C_S_AXI_ADDR_WIDTH	: integer	:= 7
+	);
+	port (
+		-- Users to add ports here
+
+		-- User ports ends
+		-- Do not modify the ports beyond this line
+
+		-- Global Clock Signal
+		S_AXI_ACLK	: in std_logic;
+		-- Global Reset Signal. This Signal is Active LOW
+		S_AXI_ARESETN	: in std_logic;
+		-- Write address (issued by master, acceped by Slave)
+		S_AXI_AWADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+		-- Write channel Protection type. This signal indicates the
+    		-- privilege and security level of the transaction, and whether
+    		-- the transaction is a data access or an instruction access.
+		S_AXI_AWPROT	: in std_logic_vector(2 downto 0);
+		-- Write address valid. This signal indicates that the master signaling
+    		-- valid write address and control information.
+		S_AXI_AWVALID	: in std_logic;
+		-- Write address ready. This signal indicates that the slave is ready
+    		-- to accept an address and associated control signals.
+		S_AXI_AWREADY	: out std_logic;
+		-- Write data (issued by master, acceped by Slave) 
+		S_AXI_WDATA	: in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+		-- Write strobes. This signal indicates which byte lanes hold
+    		-- valid data. There is one write strobe bit for each eight
+    		-- bits of the write data bus.    
+		S_AXI_WSTRB	: in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
+		-- Write valid. This signal indicates that valid write
+    		-- data and strobes are available.
+		S_AXI_WVALID	: in std_logic;
+		-- Write ready. This signal indicates that the slave
+    		-- can accept the write data.
+		S_AXI_WREADY	: out std_logic;
+		-- Write response. This signal indicates the status
+    		-- of the write transaction.
+		S_AXI_BRESP	: out std_logic_vector(1 downto 0);
+		-- Write response valid. This signal indicates that the channel
+    		-- is signaling a valid write response.
+		S_AXI_BVALID	: out std_logic;
+		-- Response ready. This signal indicates that the master
+    		-- can accept a write response.
+		S_AXI_BREADY	: in std_logic;
+		-- Read address (issued by master, acceped by Slave)
+		S_AXI_ARADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+		-- Protection type. This signal indicates the privilege
+    		-- and security level of the transaction, and whether the
+    		-- transaction is a data access or an instruction access.
+		S_AXI_ARPROT	: in std_logic_vector(2 downto 0);
+		-- Read address valid. This signal indicates that the channel
+    		-- is signaling valid read address and control information.
+		S_AXI_ARVALID	: in std_logic;
+		-- Read address ready. This signal indicates that the slave is
+    		-- ready to accept an address and associated control signals.
+		S_AXI_ARREADY	: out std_logic;
+		-- Read data (issued by slave)
+		S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+		-- Read response. This signal indicates the status of the
+    		-- read transfer.
+		S_AXI_RRESP	: out std_logic_vector(1 downto 0);
+		-- Read valid. This signal indicates that the channel is
+    		-- signaling the required read data.
+		S_AXI_RVALID	: out std_logic;
+		-- Read ready. This signal indicates that the master can
+    		-- accept the read data and response information.
+		S_AXI_RREADY	: in std_logic
+	);
+end neuron_v1_0_S00_AXI;
+
+architecture arch_imp of neuron_v1_0_S00_AXI is
+
+	-- AXI4LITE signals
+	signal axi_awaddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+	signal axi_awready	: std_logic;
+	signal axi_wready	: std_logic;
+	signal axi_bresp	: std_logic_vector(1 downto 0);
+	signal axi_bvalid	: std_logic;
+	signal axi_araddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+	signal axi_arready	: std_logic;
+	signal axi_rdata	: std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal axi_rresp	: std_logic_vector(1 downto 0);
+	signal axi_rvalid	: std_logic;
+
+	-- Example-specific design signals
+	-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+	-- ADDR_LSB is used for addressing 32/64 bit registers/memories
+	-- ADDR_LSB = 2 for 32 bits (n downto 2)
+	-- ADDR_LSB = 3 for 64 bits (n downto 3)
+	constant ADDR_LSB  : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
+	constant OPT_MEM_ADDR_BITS : integer := 4;
+	------------------------------------------------
+	---- Signals for user logic register space example
+	--------------------------------------------------
+	---- Number of Slave Registers 32
+	signal slv_reg0	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg1	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg2	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg3	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg4	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg5	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg6	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg7	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg8	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg9	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg10	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg11	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg12	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg13	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg14	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg15	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg16	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg17	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg18	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg19	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg20	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg21	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg22	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg23	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg24	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg25	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg26	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg27	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg28	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg29	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg30	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg31	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg_rden	: std_logic;
+	signal slv_reg_wren	: std_logic;
+	signal reg_data_out	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal byte_index	: integer;
+	signal aw_en	: std_logic;
+	
+
+    component mac is
+     port ( 
+       inputs : in dataVector;
+       weights : in dataVector;
+       bias : in dataType;
+       outp : out dataType;
+       clk: in STD_LOGIC);
+    end component;
+    
+    component sigmoid is
+     port ( 
+       inp : in dataType;
+       clk : in std_logic;
+       outp : out dataType);
+    end component;
+    
+    signal var1 : dataType;
+    signal calc_outp: dataType;
+    signal inputs : dataVector;
+    signal weights : dataVector;
+
+begin
+	-- I/O Connections assignments
+
+	S_AXI_AWREADY	<= axi_awready;
+	S_AXI_WREADY	<= axi_wready;
+	S_AXI_BRESP	<= axi_bresp;
+	S_AXI_BVALID	<= axi_bvalid;
+	S_AXI_ARREADY	<= axi_arready;
+	S_AXI_RDATA	<= axi_rdata;
+	S_AXI_RRESP	<= axi_rresp;
+	S_AXI_RVALID	<= axi_rvalid;
+	-- Implement axi_awready generation
+	-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+	-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+	-- de-asserted when reset is low.
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_awready <= '0';
+	      aw_en <= '1';
+	    else
+	      if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
+	        -- slave is ready to accept write address when
+	        -- there is a valid write address and write data
+	        -- on the write address and data bus. This design 
+	        -- expects no outstanding transactions. 
+	           axi_awready <= '1';
+	           aw_en <= '0';
+	        elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
+	           aw_en <= '1';
+	           axi_awready <= '0';
+	      else
+	        axi_awready <= '0';
+	      end if;
+	    end if;
+	  end if;
+	end process;
+
+	-- Implement axi_awaddr latching
+	-- This process is used to latch the address when both 
+	-- S_AXI_AWVALID and S_AXI_WVALID are valid. 
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_awaddr <= (others => '0');
+	    else
+	      if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
+	        -- Write Address latching
+	        axi_awaddr <= S_AXI_AWADDR;
+	      end if;
+	    end if;
+	  end if;                   
+	end process; 
+
+	-- Implement axi_wready generation
+	-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+	-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
+	-- de-asserted when reset is low. 
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_wready <= '0';
+	    else
+	      if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
+	          -- slave is ready to accept write data when 
+	          -- there is a valid write address and write data
+	          -- on the write address and data bus. This design 
+	          -- expects no outstanding transactions.           
+	          axi_wready <= '1';
+	      else
+	        axi_wready <= '0';
+	      end if;
+	    end if;
+	  end if;
+	end process; 
+
+	-- Implement memory mapped register select and write logic generation
+	-- The write data is accepted and written to memory mapped registers when
+	-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+	-- select byte enables of slave registers while writing.
+	-- These registers are cleared when reset (active low) is applied.
+	-- Slave register write enable is asserted when valid address and data are available
+	-- and the slave is ready to accept the write address and write data.
+	slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
+
+	process (S_AXI_ACLK)
+	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); 
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      slv_reg0 <= (others => '0');
+	      slv_reg1 <= (others => '0');
+	      slv_reg2 <= (others => '0');
+	      slv_reg3 <= (others => '0');
+	      slv_reg4 <= (others => '0');
+	      slv_reg5 <= (others => '0');
+	      slv_reg6 <= (others => '0');
+	      slv_reg7 <= (others => '0');
+	      slv_reg8 <= (others => '0');
+	      slv_reg9 <= (others => '0');
+	      slv_reg10 <= (others => '0');
+	      slv_reg11 <= (others => '0');
+	      slv_reg12 <= (others => '0');
+	      slv_reg13 <= (others => '0');
+	      slv_reg14 <= (others => '0');
+	      slv_reg15 <= (others => '0');
+	      slv_reg16 <= (others => '0');
+	      slv_reg17 <= (others => '0');
+	      slv_reg18 <= (others => '0');
+	      slv_reg19 <= (others => '0');
+	      slv_reg20 <= (others => '0');
+	      slv_reg21 <= (others => '0');
+	      slv_reg22 <= (others => '0');
+	      slv_reg23 <= (others => '0');
+	      slv_reg24 <= (others => '0');
+	      slv_reg25 <= (others => '0');
+	      slv_reg26 <= (others => '0');
+	      slv_reg27 <= (others => '0');
+	      slv_reg28 <= (others => '0');
+	      slv_reg29 <= (others => '0');
+	      slv_reg30 <= (others => '0');
+	      slv_reg31 <= (others => '0');
+	    else
+	      loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
+	      if (slv_reg_wren = '1') then
+	        case loc_addr is
+	          when b"00000" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 0
+	                slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00001" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 1
+	                slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00010" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 2
+	                slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00011" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 3
+	                slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00100" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 4
+	                slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00101" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 5
+	                slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00110" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 6
+	                slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00111" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 7
+	                slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01000" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 8
+	                slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01001" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 9
+	                slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01010" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 10
+	                slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01011" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 11
+	                slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01100" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 12
+	                slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01101" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 13
+	                slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01110" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 14
+	                slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01111" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 15
+	                slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10000" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 16
+	                slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10001" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 17
+	                slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10010" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 18
+	                slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10011" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 19
+	                slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10100" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 20
+	                slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10101" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 21
+	                slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10110" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 22
+	                slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10111" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 23
+	                slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11000" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 24
+	                slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11001" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 25
+	                slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11010" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 26
+	                slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11011" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 27
+	                slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11100" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 28
+	                slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11101" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 29
+	                slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11110" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 30
+	                slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11111" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 31
+	                slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when others =>
+	            slv_reg0 <= slv_reg0;
+	            slv_reg1 <= slv_reg1;
+	            slv_reg2 <= slv_reg2;
+	            slv_reg3 <= slv_reg3;
+	            slv_reg4 <= slv_reg4;
+	            slv_reg5 <= slv_reg5;
+	            slv_reg6 <= slv_reg6;
+	            slv_reg7 <= slv_reg7;
+	            slv_reg8 <= slv_reg8;
+	            slv_reg9 <= slv_reg9;
+	            slv_reg10 <= slv_reg10;
+	            slv_reg11 <= slv_reg11;
+	            slv_reg12 <= slv_reg12;
+	            slv_reg13 <= slv_reg13;
+	            slv_reg14 <= slv_reg14;
+	            slv_reg15 <= slv_reg15;
+	            slv_reg16 <= slv_reg16;
+	            slv_reg17 <= slv_reg17;
+	            slv_reg18 <= slv_reg18;
+	            slv_reg19 <= slv_reg19;
+	            slv_reg20 <= slv_reg20;
+	            slv_reg21 <= slv_reg21;
+	            slv_reg22 <= slv_reg22;
+	            slv_reg23 <= slv_reg23;
+	            slv_reg24 <= slv_reg24;
+	            slv_reg25 <= slv_reg25;
+	            slv_reg26 <= slv_reg26;
+	            slv_reg27 <= slv_reg27;
+	            slv_reg28 <= slv_reg28;
+	            slv_reg29 <= slv_reg29;
+	            slv_reg30 <= slv_reg30;
+	            slv_reg31 <= slv_reg31;
+	        end case;
+	      end if;
+	    end if;
+	  end if;                   
+	end process; 
+
+	-- Implement write response logic generation
+	-- The write response and response valid signals are asserted by the slave 
+	-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
+	-- This marks the acceptance of address and indicates the status of 
+	-- write transaction.
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_bvalid  <= '0';
+	      axi_bresp   <= "00"; --need to work more on the responses
+	    else
+	      if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0'  ) then
+	        axi_bvalid <= '1';
+	        axi_bresp  <= "00"; 
+	      elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then   --check if bready is asserted while bvalid is high)
+	        axi_bvalid <= '0';                                 -- (there is a possibility that bready is always asserted high)
+	      end if;
+	    end if;
+	  end if;                   
+	end process; 
+
+	-- Implement axi_arready generation
+	-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
+	-- S_AXI_ARVALID is asserted. axi_awready is 
+	-- de-asserted when reset (active low) is asserted. 
+	-- The read address is also latched when S_AXI_ARVALID is 
+	-- asserted. axi_araddr is reset to zero on reset assertion.
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_arready <= '0';
+	      axi_araddr  <= (others => '1');
+	    else
+	      if (axi_arready = '0' and S_AXI_ARVALID = '1') then
+	        -- indicates that the slave has acceped the valid read address
+	        axi_arready <= '1';
+	        -- Read Address latching 
+	        axi_araddr  <= S_AXI_ARADDR;           
+	      else
+	        axi_arready <= '0';
+	      end if;
+	    end if;
+	  end if;                   
+	end process; 
+
+	-- Implement axi_arvalid generation
+	-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
+	-- S_AXI_ARVALID and axi_arready are asserted. The slave registers 
+	-- data are available on the axi_rdata bus at this instance. The 
+	-- assertion of axi_rvalid marks the validity of read data on the 
+	-- bus and axi_rresp indicates the status of read transaction.axi_rvalid 
+	-- is deasserted on reset (active low). axi_rresp and axi_rdata are 
+	-- cleared to zero on reset (active low).  
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then
+	    if S_AXI_ARESETN = '0' then
+	      axi_rvalid <= '0';
+	      axi_rresp  <= "00";
+	    else
+	      if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
+	        -- Valid read data is available at the read data bus
+	        axi_rvalid <= '1';
+	        axi_rresp  <= "00"; -- 'OKAY' response
+	      elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
+	        -- Read data is accepted by the master
+	        axi_rvalid <= '0';
+	      end if;            
+	    end if;
+	  end if;
+	end process;
+
+	-- Implement memory mapped register select and read logic generation
+	-- Slave register read enable is asserted when valid address is available
+	-- and the slave is ready to accept the read address.
+	slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
+
+	process (calc_outp, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
+	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
+	begin
+	    -- Address decoding for reading registers
+	    loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
+	    case loc_addr is
+	      when b"00000" =>
+	        reg_data_out <= calc_outp;
+	      when b"00001" =>
+	        reg_data_out <= slv_reg1;
+	      when b"00010" =>
+	        reg_data_out <= slv_reg2;
+	      when b"00011" =>
+	        reg_data_out <= slv_reg3;
+	      when b"00100" =>
+	        reg_data_out <= slv_reg4;
+	      when b"00101" =>
+	        reg_data_out <= slv_reg5;
+	      when b"00110" =>
+	        reg_data_out <= slv_reg6;
+	      when b"00111" =>
+	        reg_data_out <= slv_reg7;
+	      when b"01000" =>
+	        reg_data_out <= slv_reg8;
+	      when b"01001" =>
+	        reg_data_out <= slv_reg9;
+	      when b"01010" =>
+	        reg_data_out <= slv_reg10;
+	      when b"01011" =>
+	        reg_data_out <= slv_reg11;
+	      when b"01100" =>
+	        reg_data_out <= slv_reg12;
+	      when b"01101" =>
+	        reg_data_out <= slv_reg13;
+	      when b"01110" =>
+	        reg_data_out <= slv_reg14;
+	      when b"01111" =>
+	        reg_data_out <= slv_reg15;
+	      when b"10000" =>
+	        reg_data_out <= slv_reg16;
+	      when b"10001" =>
+	        reg_data_out <= slv_reg17;
+	      when b"10010" =>
+	        reg_data_out <= slv_reg18;
+	      when b"10011" =>
+	        reg_data_out <= slv_reg19;
+	      when b"10100" =>
+	        reg_data_out <= slv_reg20;
+	      when b"10101" =>
+	        reg_data_out <= slv_reg21;
+	      when b"10110" =>
+	        reg_data_out <= slv_reg22;
+	      when b"10111" =>
+	        reg_data_out <= slv_reg23;
+	      when b"11000" =>
+	        reg_data_out <= slv_reg24;
+	      when b"11001" =>
+	        reg_data_out <= slv_reg25;
+	      when b"11010" =>
+	        reg_data_out <= slv_reg26;
+	      when b"11011" =>
+	        reg_data_out <= slv_reg27;
+	      when b"11100" =>
+	        reg_data_out <= slv_reg28;
+	      when b"11101" =>
+	        reg_data_out <= slv_reg29;
+	      when b"11110" =>
+	        reg_data_out <= slv_reg30;
+	      when b"11111" =>
+	        reg_data_out <= slv_reg31;
+	      when others =>
+	        reg_data_out  <= (others => '0');
+	    end case;
+	end process; 
+
+	-- Output register or memory read data
+	process( S_AXI_ACLK ) is
+	begin
+	  if (rising_edge (S_AXI_ACLK)) then
+	    if ( S_AXI_ARESETN = '0' ) then
+	      axi_rdata  <= (others => '0');
+	    else
+	      if (slv_reg_rden = '1') then
+	        -- When there is a valid read address (S_AXI_ARVALID) with 
+	        -- acceptance of read address by the slave (axi_arready), 
+	        -- output the read dada 
+	        -- Read address mux
+	          axi_rdata <= reg_data_out;     -- register read data
+	      end if;   
+	    end if;
+	  end if;
+	end process;
+
+
+	-- Add user logic here
+    mac1: mac port map (
+        inputs => inputs,
+        weights => weights,
+        bias => slv_reg20,
+        outp => var1,
+        clk => S_AXI_ACLK
+    );
+    
+    sig1: sigmoid port map (
+        inp => var1,
+        clk => S_AXI_ACLK,
+        outp => calc_outp
+    );
+    
+    inputs (0) <= slv_reg0;
+    weights(0) <= slv_reg1;
+    inputs (1) <= slv_reg2;
+    weights(1) <= slv_reg3;
+    inputs (2) <= slv_reg4;
+    weights(2) <= slv_reg5;
+    inputs (3) <= slv_reg6;
+    weights(3) <= slv_reg7;
+    inputs (4) <= slv_reg8;
+    weights(4) <= slv_reg9;
+    inputs (5) <= slv_reg10;
+    weights(5) <= slv_reg11;
+    inputs (6) <= slv_reg12;
+    weights(6) <= slv_reg13;
+    inputs (7) <= slv_reg14;
+    weights(7) <= slv_reg15;
+    inputs (8) <= slv_reg16;
+    weights(8) <= slv_reg17;
+    inputs (9) <= slv_reg18;
+    weights(9) <= slv_reg19;
+    
+	-- User logic ends
+
+end arch_imp;

ip_repo_sources/neuron_1.0/src/globals.vhd

@@ -0,0 +1,28 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.math_real.all;
+
+package myPackage is
+    
+    constant nNodes : integer := 10;
+    constant nBits : integer := 32;
+    subtype dataType is std_logic_vector(nBits-1 downto 0);
+    subtype dataTypeAdder is std_logic_vector(integer(ceil(log2(real(nBits)))) downto 0);
+    type dataVector is array(0 to nNodes-1) of std_logic_vector(nBits-1 downto 0);
+end myPackage;
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.myPackage.ALL;
+
+entity globals is
+--  Port ( );
+end globals;
+
+architecture Behavioral of globals is
+
+begin
+
+
+end Behavioral;

ip_repo_sources/neuron_1.0/src/mac.vhd

@@ -0,0 +1,42 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_arith.ALL;
+use IEEE.std_logic_textio.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.myPackage.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity mac is
+    Port ( inputs : in dataVector;
+           weights : in dataVector;
+           bias : in dataType;
+           outp : out dataType;
+           clk: in STD_LOGIC);
+end mac;
+
+architecture Behavioral of mac is
+
+begin
+
+MAIN: process(clk)
+    variable sum : dataType;
+begin
+    if rising_edge(clk) then
+        sum :=  bias;
+        for i in 0 to nNodes-1 loop
+            sum := sum + conv_integer(inputs(i)) * conv_integer(weights(i));
+        end loop;
+        
+        outp <= sum;
+    end if;
+end process;
+
+end Behavioral;

ip_repo_sources/neuron_1.0/src/neuron.vhd

@@ -0,0 +1,47 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.myPackage.ALL;
+
+entity neuron is
+    Port (
+        inputs : in dataVector;
+        weights : in dataVector;
+        bias : in dataType;
+        clk : in std_logic;
+        outp : out dataType);
+end neuron;
+
+architecture Behavioral of neuron is 
+
+component mac is
+ port ( 
+   inputs : in dataVector;
+   weights : in dataVector;
+   bias : in dataType;
+   outp : out dataType);
+end component;
+
+component sigmoid is
+ port ( 
+   inp : in dataType;
+   clk : in std_logic;
+   outp : out dataType);
+end component;
+
+signal var1 : dataType;
+
+begin
+mac1: mac port map (
+    inputs => inputs,
+    weights => weights,
+    bias => bias,
+    outp => var1
+);
+
+sig1: sigmoid port map (
+    inp => var1,
+    clk => clk,
+    outp => outp
+);
+
+end Behavioral;

ip_repo_sources/neuron_1.0/src/neuron4.vhd

@@ -0,0 +1,61 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.myPackage.ALL;
+
+entity neuron4 is
+    Port (
+        input0 : in std_logic_vector(nBits-1 downto 0);
+        input1 : in std_logic_vector(nBits-1 downto 0);
+        input2 : in std_logic_vector(nBits-1 downto 0);
+        input3 : in std_logic_vector(nBits-1 downto 0);
+        weight0 : in std_logic_vector(nBits-1 downto 0);
+        weight1 : in std_logic_vector(nBits-1 downto 0);
+        weight2 : in std_logic_vector(nBits-1 downto 0);
+        weight3 : in std_logic_vector(nBits-1 downto 0);
+        
+        bias : in std_logic_vector(nBits-1 downto 0);
+        clk : in std_logic;
+        outp : out std_logic_vector(nBits-1 downto 0));
+end neuron4;
+
+architecture Behavioral of neuron4 is 
+
+component mac is
+ port ( 
+   inputs : in dataVector;
+   weights : in dataVector;
+   bias : in dataType;
+   outp : out dataType);
+end component;
+
+component sigmoid is
+ port ( 
+   inp : in dataType;
+   clk : in std_logic;
+   outp : out dataType);
+end component;
+
+signal var1 : dataType;
+
+begin
+mac1: mac port map (
+    inputs(0) => input0,
+    inputs(1) => input1,
+    inputs(2) => input2,
+    inputs(3) => input3,
+    weights(0) => weight0,
+    weights(1) => weight1,
+    weights(2) => weight2,
+    weights(3) => weight3,
+    
+    bias => bias,
+    outp => var1
+);
+
+sig1: sigmoid port map (
+    inp => var1,
+    clk => clk,
+    outp => outp
+);
+
+end Behavioral;

ip_repo_sources/neuron_1.0/xgui/neuron_v1_0.tcl

@@ -0,0 +1,62 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox]
+  set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH}
+  set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}]
+  set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH}
+  ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to validate C_S00_AXI_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to validate C_S00_AXI_ADDR_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+	# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+	# Procedure called to validate C_S00_AXI_BASEADDR
+	return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+	# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+	# Procedure called to validate C_S00_AXI_HIGHADDR
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
+}
+

ip_repo_sources/neuron_packed/component.xml

@@ -0,0 +1,1492 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>packaging</spirit:name>
+  <spirit:version>2.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>rst</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rst</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">rst</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>fifo_read</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RD_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>inputStream</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EMPTY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>inputEmpty</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RD_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>inpRdEn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>fifo_write</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ALMOST_FULL</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>outputFull</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WR_DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>outData</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WR_EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>outWrEn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>packaging</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>e0830e35</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>VHDL</spirit:language>
+        <spirit:modelName>packaging</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>e0830e35</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>b2335c60</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rst</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>inputStream</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.busWidth&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>inpRdEn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>inputEmpty</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>outData</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.busWidth&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>outWrEn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>outputFull</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>errorCode</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>stateOut</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>busWidth</spirit:name>
+        <spirit:displayName>Buswidth</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.busWidth">32</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>src/globals.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/checksum.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/mac.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/multiplex.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/neuron.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/parallelize.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/relu.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/shiftIn.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/shiftOut.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/packaging.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_e24132ad</spirit:userFileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Block_proc.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_Border_proc.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_Border_proc_borderbuf.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_HConvH_proc6.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_VConvH_proc.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_VConvH_proc_linebuf_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/dummyModule.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/fifo_w32_d2_A.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/fifo_w32_d3_A.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/filter11x11_strm.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/filter11x11_strm_ent.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/start_for_Block_proc_U0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/start_for_Loop_Border_proc_U0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/start_for_Loop_VConvH_proc_U0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_636a71e0</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>src/globals.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/checksum.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/mac.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/multiplex.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/neuron.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/parallelize.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/relu.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/shiftIn.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/shiftOut.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/packaging.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Block_proc.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_Border_proc.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_Border_proc_borderbuf.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_HConvH_proc6.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_VConvH_proc.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/Loop_VConvH_proc_linebuf_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/dummyModule.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/fifo_w32_d2_A.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/fifo_w32_d3_A.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/filter11x11_strm.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>src/filter11x11_strm_ent.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
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+        <xilinx:tag xilinx:name="ui.data.coregen.dd@19e9ce5f_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_packed</xilinx:tag>
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+        <xilinx:tag xilinx:name="ui.data.coregen.dd@112d8f87_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_packed</xilinx:tag>
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+        <xilinx:tag xilinx:name="ui.data.coregen.dd@7b2935c7_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_packed</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@38138e4f_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_packed</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.dd@464ef59_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/neuron_packed</xilinx:tag>
+      </xilinx:tags>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="4107a84a"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ad41f57a"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="427ec09f"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="4c9ef9f8"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="017f4340"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>

ip_repo_sources/neuron_packed/src/Block_proc.vhd

@@ -0,0 +1,321 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+-- Version: 2018.3
+-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity Block_proc is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    start_full_n : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    start_out : OUT STD_LOGIC;
+    start_write : OUT STD_LOGIC;
+    width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    width_empty_n : IN STD_LOGIC;
+    width_read : OUT STD_LOGIC;
+    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    height_empty_n : IN STD_LOGIC;
+    height_read : OUT STD_LOGIC;
+    width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    width_out_full_n : IN STD_LOGIC;
+    width_out_write : OUT STD_LOGIC;
+    height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    height_out_full_n : IN STD_LOGIC;
+    height_out_write : OUT STD_LOGIC;
+    vconv_xlim_out_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    vconv_xlim_out_out_full_n : IN STD_LOGIC;
+    vconv_xlim_out_out_write : OUT STD_LOGIC );
+end;
+
+
+architecture behav of Block_proc is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv32_FFFFFFF6 : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111110110";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+
+    signal real_start : STD_LOGIC;
+    signal start_once_reg : STD_LOGIC := '0';
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal internal_ap_ready : STD_LOGIC;
+    signal width_blk_n : STD_LOGIC;
+    signal height_blk_n : STD_LOGIC;
+    signal width_out_blk_n : STD_LOGIC;
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal height_out_blk_n : STD_LOGIC;
+    signal vconv_xlim_out_out_blk_n : STD_LOGIC;
+    signal width_read_reg_69 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state1 : BOOLEAN;
+    signal height_read_reg_75 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state2 : BOOLEAN;
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
+
+
+begin
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    start_once_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                start_once_reg <= ap_const_logic_0;
+            else
+                if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then 
+                    start_once_reg <= ap_const_logic_1;
+                elsif ((internal_ap_ready = ap_const_logic_1)) then 
+                    start_once_reg <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                height_read_reg_75 <= height_dout;
+                width_read_reg_69 <= width_dout;
+            end if;
+        end if;
+    end process;
+
+    ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, width_empty_n, height_empty_n, width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                end if;
+            when others =>  
+                ap_NS_fsm <= "XX";
+        end case;
+    end process;
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+
+    ap_block_state1_assign_proc : process(real_start, ap_done_reg, width_empty_n, height_empty_n)
+    begin
+                ap_block_state1 <= ((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
+    end process;
+
+
+    ap_block_state2_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n)
+    begin
+                ap_block_state2 <= ((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0));
+    end process;
+
+
+    ap_done_assign_proc : process(ap_done_reg, width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_done_reg;
+        end if; 
+    end process;
+
+
+    ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
+    begin
+        if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_ready <= internal_ap_ready;
+
+    height_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_blk_n <= height_empty_n;
+        else 
+            height_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    height_out_blk_n_assign_proc : process(height_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            height_out_blk_n <= height_out_full_n;
+        else 
+            height_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    height_out_din <= height_read_reg_75;
+
+    height_out_write_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            height_out_write <= ap_const_logic_1;
+        else 
+            height_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    height_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_read <= ap_const_logic_1;
+        else 
+            height_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    internal_ap_ready_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            internal_ap_ready <= ap_const_logic_1;
+        else 
+            internal_ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
+    begin
+        if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then 
+            real_start <= ap_const_logic_0;
+        else 
+            real_start <= ap_start;
+        end if; 
+    end process;
+
+    start_out <= real_start;
+
+    start_write_assign_proc : process(real_start, start_once_reg)
+    begin
+        if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then 
+            start_write <= ap_const_logic_1;
+        else 
+            start_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    vconv_xlim_out_out_blk_n_assign_proc : process(vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            vconv_xlim_out_out_blk_n <= vconv_xlim_out_out_full_n;
+        else 
+            vconv_xlim_out_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    vconv_xlim_out_out_din <= std_logic_vector(unsigned(width_read_reg_69) + unsigned(ap_const_lv32_FFFFFFF6));
+
+    vconv_xlim_out_out_write_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            vconv_xlim_out_out_write <= ap_const_logic_1;
+        else 
+            vconv_xlim_out_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    width_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_blk_n <= width_empty_n;
+        else 
+            width_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    width_out_blk_n_assign_proc : process(width_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            width_out_blk_n <= width_out_full_n;
+        else 
+            width_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    width_out_din <= width_read_reg_69;
+
+    width_out_write_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            width_out_write <= ap_const_logic_1;
+        else 
+            width_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    width_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_read <= ap_const_logic_1;
+        else 
+            width_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+end behav;

ip_repo_sources/neuron_packed/src/Loop_Border_proc.vhd

@@ -0,0 +1,896 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+-- Version: 2018.3
+-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity Loop_Border_proc is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    width_empty_n : IN STD_LOGIC;
+    width_read : OUT STD_LOGIC;
+    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    height_empty_n : IN STD_LOGIC;
+    height_read : OUT STD_LOGIC;
+    dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+    dst_V_TVALID : OUT STD_LOGIC;
+    dst_V_TREADY : IN STD_LOGIC;
+    vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    vconv_xlim_loc_empty_n : IN STD_LOGIC;
+    vconv_xlim_loc_read : OUT STD_LOGIC;
+    vconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    vconv_V_empty_n : IN STD_LOGIC;
+    vconv_V_read : OUT STD_LOGIC );
+end;
+
+
+architecture behav of Loop_Border_proc is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
+    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
+    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
+    constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
+    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
+    constant ap_const_lv32_FFFFFFF5 : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111110101";
+    constant ap_const_lv32_FFFFFFFA : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111010";
+    constant ap_const_lv32_FFFFFFFB : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111011";
+    constant ap_const_lv10_5 : STD_LOGIC_VECTOR (9 downto 0) := "0000000101";
+    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
+    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
+    constant ap_const_lv10_6 : STD_LOGIC_VECTOR (9 downto 0) := "0000000110";
+    constant ap_const_lv10_3FB : STD_LOGIC_VECTOR (9 downto 0) := "1111111011";
+    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
+
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal dst_V_1_data_out : STD_LOGIC_VECTOR (31 downto 0);
+    signal dst_V_1_vld_in : STD_LOGIC;
+    signal dst_V_1_vld_out : STD_LOGIC;
+    signal dst_V_1_ack_in : STD_LOGIC;
+    signal dst_V_1_ack_out : STD_LOGIC;
+    signal dst_V_1_payload_A : STD_LOGIC_VECTOR (31 downto 0);
+    signal dst_V_1_payload_B : STD_LOGIC_VECTOR (31 downto 0);
+    signal dst_V_1_sel_rd : STD_LOGIC := '0';
+    signal dst_V_1_sel_wr : STD_LOGIC := '0';
+    signal dst_V_1_sel : STD_LOGIC;
+    signal dst_V_1_load_A : STD_LOGIC;
+    signal dst_V_1_load_B : STD_LOGIC;
+    signal dst_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    signal dst_V_1_state_cmp_full : STD_LOGIC;
+    signal width_blk_n : STD_LOGIC;
+    signal height_blk_n : STD_LOGIC;
+    signal dst_V_TDATA_blk_n : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0 : BOOLEAN;
+    signal exitcond_flatten_reg_499 : STD_LOGIC_VECTOR (0 downto 0);
+    signal exitcond_flatten_reg_499_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
+    signal exitcond_flatten_reg_499_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal vconv_xlim_loc_blk_n : STD_LOGIC;
+    signal vconv_V_blk_n : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
+    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
+    signal brmerge_mid2_reg_516 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_24_i_i_reg_525 : STD_LOGIC_VECTOR (0 downto 0);
+    signal indvar_flatten_reg_145 : STD_LOGIC_VECTOR (63 downto 0);
+    signal i6_0_i_i_i_reg_156 : STD_LOGIC_VECTOR (9 downto 0);
+    signal j_0_i_i_i_reg_167 : STD_LOGIC_VECTOR (9 downto 0);
+    signal width_read_reg_459 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state1 : BOOLEAN;
+    signal height_read_reg_467 : STD_LOGIC_VECTOR (31 downto 0);
+    signal vconv_xlim_loc_read_reg_473 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_9_i_i_fu_178_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_9_i_i_reg_478 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal tmp_i_i_fu_183_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_i_i_reg_483 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_7_i_i_fu_188_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_7_i_i_reg_488 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_199_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound_reg_494 : STD_LOGIC_VECTOR (63 downto 0);
+    signal exitcond_flatten_fu_247_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
+    signal ap_predicate_op59_read_state4 : BOOLEAN;
+    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
+    signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
+    signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
+    signal ap_block_state6_io : BOOLEAN;
+    signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
+    signal ap_block_state7_io : BOOLEAN;
+    signal ap_block_pp0_stage0_11001 : BOOLEAN;
+    signal exitcond_flatten_reg_499_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal indvar_flatten_next_fu_252_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
+    signal j_0_i_i_i_mid2_fu_268_p3 : STD_LOGIC_VECTOR (9 downto 0);
+    signal j_0_i_i_i_mid2_reg_508 : STD_LOGIC_VECTOR (9 downto 0);
+    signal brmerge_mid2_fu_305_p3 : STD_LOGIC_VECTOR (0 downto 0);
+    signal brmerge_mid2_reg_516_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal i6_0_i_i_i_mid2_fu_317_p3 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp_24_i_i_fu_325_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_28_i_i_fu_330_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_28_i_i_reg_529 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_28_i_i_reg_529_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_30_i_i_fu_335_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_30_i_i_reg_534 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_30_i_i_reg_534_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_30_i_i_reg_534_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal j_fu_340_p2 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp_27_i_i_fu_355_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_27_i_i_reg_544 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_29_i_i_fu_360_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_29_i_i_reg_549 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_29_i_i_reg_549_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal borderbuf_q1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal pix_out_7_reg_560 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
+    signal pix_out_8_fu_431_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_pp0_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
+    signal borderbuf_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal borderbuf_ce0 : STD_LOGIC;
+    signal borderbuf_we0 : STD_LOGIC;
+    signal borderbuf_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal borderbuf_ce1 : STD_LOGIC;
+    signal tmp_26_i_i_fu_346_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_32_i_i_fu_370_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal r_edge_pix_fu_74 : STD_LOGIC_VECTOR (31 downto 0);
+    signal pix_out_fu_78 : STD_LOGIC_VECTOR (31 downto 0);
+    signal l_edge_pix_fu_391_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal pix_out_1_fu_82 : STD_LOGIC_VECTOR (31 downto 0);
+    signal pix_in_2_l_edge_pix_s_fu_384_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_pp0_stage0_01001 : BOOLEAN;
+    signal bound_fu_199_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_199_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal i6_0_i_cast_i_i_mid1_fu_205_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal notrhs_fu_221_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal notlhs_fu_215_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_17_i_i_fu_209_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal brmerge_i_i_i_not_fu_226_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal j_0_i_cast_i_i_fu_238_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal i_fu_258_p2 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp_22_i_i_fu_242_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal i6_0_i_cast_i_i_fu_264_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal notrhs_mid1_fu_288_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal notlhs_mid1_fu_282_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_17_i_i_mid1_fu_276_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal brmerge_i_i_i_not_mi_fu_293_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal brmerge_fu_232_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal brmerge_mid1_fu_299_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal j_0_i_cast_i_i_mid2_s_fu_313_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_31_i_i_fu_365_p2 : STD_LOGIC_VECTOR (9 downto 0);
+    signal sel_tmp_fu_414_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal sel_tmp1_fu_419_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal pix_out_3_fu_424_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state8 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
+    signal ap_idle_pp0 : STD_LOGIC;
+    signal ap_enable_pp0 : STD_LOGIC;
+    signal bound_fu_199_p00 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound_fu_199_p10 : STD_LOGIC_VECTOR (63 downto 0);
+
+    component Loop_Border_proc_borderbuf IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (9 downto 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR (31 downto 0);
+        address1 : IN STD_LOGIC_VECTOR (9 downto 0);
+        ce1 : IN STD_LOGIC;
+        q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+
+begin
+    borderbuf_U : component Loop_Border_proc_borderbuf
+    generic map (
+        DataWidth => 32,
+        AddressRange => 662,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => borderbuf_address0,
+        ce0 => borderbuf_ce0,
+        we0 => borderbuf_we0,
+        d0 => vconv_V_dout,
+        address1 => borderbuf_address1,
+        ce1 => borderbuf_ce1,
+        q1 => borderbuf_q1);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then 
+                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                    ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    dst_V_1_sel_rd_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                dst_V_1_sel_rd <= ap_const_logic_0;
+            else
+                if (((dst_V_1_ack_out = ap_const_logic_1) and (dst_V_1_vld_out = ap_const_logic_1))) then 
+                                        dst_V_1_sel_rd <= not(dst_V_1_sel_rd);
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    dst_V_1_sel_wr_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                dst_V_1_sel_wr <= ap_const_logic_0;
+            else
+                if (((dst_V_1_ack_in = ap_const_logic_1) and (dst_V_1_vld_in = ap_const_logic_1))) then 
+                                        dst_V_1_sel_wr <= not(dst_V_1_sel_wr);
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    dst_V_1_state_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                dst_V_1_state <= ap_const_lv2_0;
+            else
+                if ((((dst_V_1_state = ap_const_lv2_2) and (dst_V_1_vld_in = ap_const_logic_0)) or ((dst_V_1_state = ap_const_lv2_3) and (dst_V_1_vld_in = ap_const_logic_0) and (dst_V_1_ack_out = ap_const_logic_1)))) then 
+                    dst_V_1_state <= ap_const_lv2_2;
+                elsif ((((dst_V_1_state = ap_const_lv2_1) and (dst_V_1_ack_out = ap_const_logic_0)) or ((dst_V_1_state = ap_const_lv2_3) and (dst_V_1_ack_out = ap_const_logic_0) and (dst_V_1_vld_in = ap_const_logic_1)))) then 
+                    dst_V_1_state <= ap_const_lv2_1;
+                elsif (((not(((dst_V_1_vld_in = ap_const_logic_0) and (dst_V_1_ack_out = ap_const_logic_1))) and not(((dst_V_1_ack_out = ap_const_logic_0) and (dst_V_1_vld_in = ap_const_logic_1))) and (dst_V_1_state = ap_const_lv2_3)) or ((dst_V_1_state = ap_const_lv2_1) and (dst_V_1_ack_out = ap_const_logic_1)) or ((dst_V_1_state = ap_const_lv2_2) and (dst_V_1_vld_in = ap_const_logic_1)))) then 
+                    dst_V_1_state <= ap_const_lv2_3;
+                else 
+                    dst_V_1_state <= ap_const_lv2_2;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    i6_0_i_i_i_reg_156_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                i6_0_i_i_i_reg_156 <= i6_0_i_i_i_mid2_fu_317_p3;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                i6_0_i_i_i_reg_156 <= ap_const_lv10_0;
+            end if; 
+        end if;
+    end process;
+
+    indvar_flatten_reg_145_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                indvar_flatten_reg_145 <= indvar_flatten_next_fu_252_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                indvar_flatten_reg_145 <= ap_const_lv64_0;
+            end if; 
+        end if;
+    end process;
+
+    j_0_i_i_i_reg_167_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                j_0_i_i_i_reg_167 <= j_fu_340_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                j_0_i_i_i_reg_167 <= ap_const_lv10_0;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
+                bound_reg_494 <= bound_fu_199_p2;
+                tmp_7_i_i_reg_488 <= tmp_7_i_i_fu_188_p2;
+                tmp_9_i_i_reg_478 <= tmp_9_i_i_fu_178_p2;
+                tmp_i_i_reg_483 <= tmp_i_i_fu_183_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                brmerge_mid2_reg_516 <= brmerge_mid2_fu_305_p3;
+                j_0_i_i_i_mid2_reg_508 <= j_0_i_i_i_mid2_fu_268_p3;
+                tmp_30_i_i_reg_534 <= tmp_30_i_i_fu_335_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                brmerge_mid2_reg_516_pp0_iter1_reg <= brmerge_mid2_reg_516;
+                exitcond_flatten_reg_499 <= exitcond_flatten_fu_247_p2;
+                exitcond_flatten_reg_499_pp0_iter1_reg <= exitcond_flatten_reg_499;
+                tmp_28_i_i_reg_529_pp0_iter1_reg <= tmp_28_i_i_reg_529;
+                tmp_30_i_i_reg_534_pp0_iter1_reg <= tmp_30_i_i_reg_534;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((dst_V_1_load_A = ap_const_logic_1)) then
+                dst_V_1_payload_A <= pix_out_8_fu_431_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((dst_V_1_load_B = ap_const_logic_1)) then
+                dst_V_1_payload_B <= pix_out_8_fu_431_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
+                exitcond_flatten_reg_499_pp0_iter2_reg <= exitcond_flatten_reg_499_pp0_iter1_reg;
+                exitcond_flatten_reg_499_pp0_iter3_reg <= exitcond_flatten_reg_499_pp0_iter2_reg;
+                tmp_29_i_i_reg_549_pp0_iter2_reg <= tmp_29_i_i_reg_549;
+                tmp_30_i_i_reg_534_pp0_iter2_reg <= tmp_30_i_i_reg_534_pp0_iter1_reg;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                height_read_reg_467 <= height_dout;
+                vconv_xlim_loc_read_reg_473 <= vconv_xlim_loc_dout;
+                width_read_reg_459 <= width_dout;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((brmerge_mid2_reg_516_pp0_iter1_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
+                pix_out_1_fu_82 <= pix_in_2_l_edge_pix_s_fu_384_p3;
+                pix_out_fu_78 <= l_edge_pix_fu_391_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_reg_499_pp0_iter1_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
+                pix_out_7_reg_560 <= borderbuf_q1;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                r_edge_pix_fu_74 <= vconv_V_dout;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((brmerge_mid2_fu_305_p3 = ap_const_lv1_1) and (exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                tmp_24_i_i_reg_525 <= tmp_24_i_i_fu_325_p2;
+                tmp_28_i_i_reg_529 <= tmp_28_i_i_fu_330_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                tmp_27_i_i_reg_544 <= tmp_27_i_i_fu_355_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_reg_499 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                tmp_29_i_i_reg_549 <= tmp_29_i_i_fu_360_p2;
+            end if;
+        end if;
+    end process;
+
+    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, width_empty_n, height_empty_n, dst_V_1_ack_in, vconv_xlim_loc_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, exitcond_flatten_fu_247_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_CS_fsm_state8)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+            when ap_ST_fsm_pp0_stage0 => 
+                if ((not(((exitcond_flatten_fu_247_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) and not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                elsif ((((exitcond_flatten_fu_247_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state8;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                end if;
+            when ap_ST_fsm_state8 => 
+                if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state8;
+                end if;
+            when others =>  
+                ap_NS_fsm <= "XXXX";
+        end case;
+    end process;
+    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state8 <= ap_CS_fsm(3);
+        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage0_01001_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4)
+    begin
+                ap_block_pp0_stage0_01001 <= ((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp0_stage0_11001_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_state6_io, ap_block_state7_io)
+    begin
+                ap_block_pp0_stage0_11001 <= (((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state7_io) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state6_io) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)));
+    end process;
+
+
+    ap_block_pp0_stage0_subdone_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_state6_io, ap_block_state7_io)
+    begin
+                ap_block_pp0_stage0_subdone <= (((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state7_io) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state6_io) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)));
+    end process;
+
+
+    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
+    begin
+                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
+    end process;
+
+        ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state4_pp0_stage0_iter1_assign_proc : process(vconv_V_empty_n, ap_predicate_op59_read_state4)
+    begin
+                ap_block_state4_pp0_stage0_iter1 <= ((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1));
+    end process;
+
+        ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state6_io_assign_proc : process(dst_V_1_ack_in, exitcond_flatten_reg_499_pp0_iter2_reg)
+    begin
+                ap_block_state6_io <= ((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (dst_V_1_ack_in = ap_const_logic_0));
+    end process;
+
+        ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state7_io_assign_proc : process(dst_V_1_ack_in, exitcond_flatten_reg_499_pp0_iter3_reg)
+    begin
+                ap_block_state7_io <= ((exitcond_flatten_reg_499_pp0_iter3_reg = ap_const_lv1_0) and (dst_V_1_ack_in = ap_const_logic_0));
+    end process;
+
+        ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_flatten_fu_247_p2)
+    begin
+        if ((exitcond_flatten_fu_247_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
+        else 
+            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_done_assign_proc : process(ap_done_reg, dst_V_1_ack_in, ap_CS_fsm_state8)
+    begin
+        if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_done_reg;
+        end if; 
+    end process;
+
+    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
+
+    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
+    begin
+        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if (((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0))) then 
+            ap_idle_pp0 <= ap_const_logic_1;
+        else 
+            ap_idle_pp0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_predicate_op59_read_state4_assign_proc : process(brmerge_mid2_reg_516, tmp_24_i_i_reg_525)
+    begin
+                ap_predicate_op59_read_state4 <= ((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1));
+    end process;
+
+
+    ap_ready_assign_proc : process(dst_V_1_ack_in, ap_CS_fsm_state8)
+    begin
+        if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
+            ap_ready <= ap_const_logic_1;
+        else 
+            ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    borderbuf_address0 <= tmp_26_i_i_fu_346_p1(10 - 1 downto 0);
+    borderbuf_address1 <= tmp_32_i_i_fu_370_p1(10 - 1 downto 0);
+
+    borderbuf_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            borderbuf_ce0 <= ap_const_logic_1;
+        else 
+            borderbuf_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    borderbuf_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            borderbuf_ce1 <= ap_const_logic_1;
+        else 
+            borderbuf_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    borderbuf_we0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, brmerge_mid2_reg_516, tmp_24_i_i_reg_525, ap_block_pp0_stage0_11001)
+    begin
+        if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            borderbuf_we0 <= ap_const_logic_1;
+        else 
+            borderbuf_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    bound_fu_199_p0 <= bound_fu_199_p00(32 - 1 downto 0);
+    bound_fu_199_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(width_read_reg_459),64));
+    bound_fu_199_p1 <= bound_fu_199_p10(32 - 1 downto 0);
+    bound_fu_199_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(height_read_reg_467),64));
+    bound_fu_199_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_199_p0) * unsigned(bound_fu_199_p1), 64));
+    brmerge_fu_232_p2 <= (tmp_17_i_i_fu_209_p2 or brmerge_i_i_i_not_fu_226_p2);
+    brmerge_i_i_i_not_fu_226_p2 <= (notrhs_fu_221_p2 and notlhs_fu_215_p2);
+    brmerge_i_i_i_not_mi_fu_293_p2 <= (notrhs_mid1_fu_288_p2 and notlhs_mid1_fu_282_p2);
+    brmerge_mid1_fu_299_p2 <= (tmp_17_i_i_mid1_fu_276_p2 or brmerge_i_i_i_not_mi_fu_293_p2);
+    brmerge_mid2_fu_305_p3 <= 
+        brmerge_fu_232_p2 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
+        brmerge_mid1_fu_299_p2;
+    dst_V_1_ack_in <= dst_V_1_state(1);
+    dst_V_1_ack_out <= dst_V_TREADY;
+
+    dst_V_1_data_out_assign_proc : process(dst_V_1_payload_A, dst_V_1_payload_B, dst_V_1_sel)
+    begin
+        if ((dst_V_1_sel = ap_const_logic_1)) then 
+            dst_V_1_data_out <= dst_V_1_payload_B;
+        else 
+            dst_V_1_data_out <= dst_V_1_payload_A;
+        end if; 
+    end process;
+
+    dst_V_1_load_A <= (not(dst_V_1_sel_wr) and dst_V_1_state_cmp_full);
+    dst_V_1_load_B <= (dst_V_1_state_cmp_full and dst_V_1_sel_wr);
+    dst_V_1_sel <= dst_V_1_sel_rd;
+    dst_V_1_state_cmp_full <= '0' when (dst_V_1_state = ap_const_lv2_1) else '1';
+
+    dst_V_1_vld_in_assign_proc : process(ap_enable_reg_pp0_iter3, exitcond_flatten_reg_499_pp0_iter2_reg, ap_block_pp0_stage0_11001)
+    begin
+        if (((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1))) then 
+            dst_V_1_vld_in <= ap_const_logic_1;
+        else 
+            dst_V_1_vld_in <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    dst_V_1_vld_out <= dst_V_1_state(0);
+    dst_V_TDATA <= dst_V_1_data_out;
+
+    dst_V_TDATA_blk_n_assign_proc : process(dst_V_1_state, ap_enable_reg_pp0_iter3, ap_block_pp0_stage0, exitcond_flatten_reg_499_pp0_iter2_reg, ap_enable_reg_pp0_iter4, exitcond_flatten_reg_499_pp0_iter3_reg)
+    begin
+        if ((((exitcond_flatten_reg_499_pp0_iter3_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)))) then 
+            dst_V_TDATA_blk_n <= dst_V_1_state(1);
+        else 
+            dst_V_TDATA_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    dst_V_TVALID <= dst_V_1_state(0);
+    exitcond_flatten_fu_247_p2 <= "1" when (indvar_flatten_reg_145 = bound_reg_494) else "0";
+
+    height_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_blk_n <= height_empty_n;
+        else 
+            height_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    height_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_read <= ap_const_logic_1;
+        else 
+            height_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    i6_0_i_cast_i_i_fu_264_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_fu_258_p2),32));
+    i6_0_i_cast_i_i_mid1_fu_205_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i6_0_i_i_i_reg_156),32));
+    i6_0_i_i_i_mid2_fu_317_p3 <= 
+        i6_0_i_i_i_reg_156 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
+        i_fu_258_p2;
+    i_fu_258_p2 <= std_logic_vector(unsigned(i6_0_i_i_i_reg_156) + unsigned(ap_const_lv10_1));
+    indvar_flatten_next_fu_252_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_145) + unsigned(ap_const_lv64_1));
+    j_0_i_cast_i_i_fu_238_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_reg_167),32));
+    j_0_i_cast_i_i_mid2_s_fu_313_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_mid2_fu_268_p3),32));
+    j_0_i_i_i_mid2_fu_268_p3 <= 
+        j_0_i_i_i_reg_167 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
+        ap_const_lv10_0;
+    j_fu_340_p2 <= std_logic_vector(unsigned(j_0_i_i_i_mid2_fu_268_p3) + unsigned(ap_const_lv10_1));
+    l_edge_pix_fu_391_p3 <= 
+        r_edge_pix_fu_74 when (tmp_28_i_i_reg_529_pp0_iter1_reg(0) = '1') else 
+        pix_out_fu_78;
+    notlhs_fu_215_p2 <= "1" when (unsigned(i6_0_i_i_i_reg_156) > unsigned(ap_const_lv10_5)) else "0";
+    notlhs_mid1_fu_282_p2 <= "1" when (unsigned(i_fu_258_p2) > unsigned(ap_const_lv10_5)) else "0";
+    notrhs_fu_221_p2 <= "1" when (signed(i6_0_i_cast_i_i_mid1_fu_205_p1) < signed(tmp_7_i_i_reg_488)) else "0";
+    notrhs_mid1_fu_288_p2 <= "1" when (signed(i6_0_i_cast_i_i_fu_264_p1) < signed(tmp_7_i_i_reg_488)) else "0";
+    pix_in_2_l_edge_pix_s_fu_384_p3 <= 
+        r_edge_pix_fu_74 when (tmp_27_i_i_reg_544(0) = '1') else 
+        pix_out_1_fu_82;
+    pix_out_3_fu_424_p3 <= 
+        pix_out_7_reg_560 when (sel_tmp1_fu_419_p2(0) = '1') else 
+        pix_out_fu_78;
+    pix_out_8_fu_431_p3 <= 
+        pix_out_1_fu_82 when (tmp_29_i_i_reg_549_pp0_iter2_reg(0) = '1') else 
+        pix_out_3_fu_424_p3;
+    sel_tmp1_fu_419_p2 <= (tmp_30_i_i_reg_534_pp0_iter2_reg and sel_tmp_fu_414_p2);
+    sel_tmp_fu_414_p2 <= (tmp_29_i_i_reg_549_pp0_iter2_reg xor ap_const_lv1_1);
+    tmp_17_i_i_fu_209_p2 <= "1" when (i6_0_i_i_i_reg_156 = ap_const_lv10_0) else "0";
+    tmp_17_i_i_mid1_fu_276_p2 <= "1" when (i_fu_258_p2 = ap_const_lv10_0) else "0";
+    tmp_22_i_i_fu_242_p2 <= "1" when (signed(j_0_i_cast_i_i_fu_238_p1) < signed(width_read_reg_459)) else "0";
+    tmp_24_i_i_fu_325_p2 <= "1" when (signed(j_0_i_cast_i_i_mid2_s_fu_313_p1) < signed(vconv_xlim_loc_read_reg_473)) else "0";
+    tmp_26_i_i_fu_346_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_mid2_reg_508),64));
+    tmp_27_i_i_fu_355_p2 <= "1" when (j_0_i_i_i_mid2_reg_508 = ap_const_lv10_0) else "0";
+    tmp_28_i_i_fu_330_p2 <= "1" when (j_0_i_cast_i_i_mid2_s_fu_313_p1 = tmp_9_i_i_reg_478) else "0";
+    tmp_29_i_i_fu_360_p2 <= "1" when (unsigned(j_0_i_i_i_mid2_reg_508) < unsigned(ap_const_lv10_6)) else "0";
+    tmp_30_i_i_fu_335_p2 <= "1" when (signed(j_0_i_cast_i_i_mid2_s_fu_313_p1) < signed(tmp_i_i_reg_483)) else "0";
+    tmp_31_i_i_fu_365_p2 <= std_logic_vector(unsigned(j_0_i_i_i_mid2_reg_508) + unsigned(ap_const_lv10_3FB));
+    tmp_32_i_i_fu_370_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_31_i_i_fu_365_p2),64));
+    tmp_7_i_i_fu_188_p2 <= std_logic_vector(unsigned(height_read_reg_467) + unsigned(ap_const_lv32_FFFFFFFB));
+    tmp_9_i_i_fu_178_p2 <= std_logic_vector(unsigned(width_read_reg_459) + unsigned(ap_const_lv32_FFFFFFF5));
+    tmp_i_i_fu_183_p2 <= std_logic_vector(unsigned(width_read_reg_459) + unsigned(ap_const_lv32_FFFFFFFA));
+
+    vconv_V_blk_n_assign_proc : process(vconv_V_empty_n, ap_block_pp0_stage0, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, brmerge_mid2_reg_516, tmp_24_i_i_reg_525)
+    begin
+        if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
+            vconv_V_blk_n <= vconv_V_empty_n;
+        else 
+            vconv_V_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    vconv_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            vconv_V_read <= ap_const_logic_1;
+        else 
+            vconv_V_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    vconv_xlim_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            vconv_xlim_loc_blk_n <= vconv_xlim_loc_empty_n;
+        else 
+            vconv_xlim_loc_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    vconv_xlim_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            vconv_xlim_loc_read <= ap_const_logic_1;
+        else 
+            vconv_xlim_loc_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    width_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_blk_n <= width_empty_n;
+        else 
+            width_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    width_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_read <= ap_const_logic_1;
+        else 
+            width_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+end behav;

ip_repo_sources/neuron_packed/src/Loop_Border_proc_borderbuf.vhd

@@ -0,0 +1,132 @@
+-- ==============================================================
+-- File generated on Wed Jun 26 16:53:30 CEST 2019
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
+-- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
+-- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity Loop_Border_proc_borderbuf_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 10; 
+            MEM_SIZE    : integer := 662
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          d0        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we0       : in std_logic; 
+          addr1     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce1       : in std_logic; 
+          q1        : out std_logic_vector(DWIDTH-1 downto 0);
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of Loop_Border_proc_borderbuf_ram is 
+
+signal addr1_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array;
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            if (we0 = '1') then 
+                ram(CONV_INTEGER(addr0)) := d0; 
+            end if;
+        end if;
+    end if;
+end process;
+
+memory_access_guard_1: process (addr1) 
+begin
+      addr1_tmp <= addr1;
+--synthesis translate_off
+      if (CONV_INTEGER(addr1) > mem_size-1) then
+           addr1_tmp <= (others => '0');
+      else 
+           addr1_tmp <= addr1;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_1: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce1 = '1') then 
+            q1 <= ram(CONV_INTEGER(addr1_tmp)); 
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity Loop_Border_proc_borderbuf is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 662;
+        AddressWidth : INTEGER := 10);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce1 : IN STD_LOGIC;
+        q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of Loop_Border_proc_borderbuf is
+    component Loop_Border_proc_borderbuf_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            we0 : IN STD_LOGIC;
+            d0 : IN STD_LOGIC_VECTOR;
+            addr1 : IN STD_LOGIC_VECTOR;
+            ce1 : IN STD_LOGIC;
+            q1 : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    Loop_Border_proc_borderbuf_ram_U :  component Loop_Border_proc_borderbuf_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        we0 => we0,
+        d0 => d0,
+        addr1 => address1,
+        ce1 => ce1,
+        q1 => q1);
+
+end architecture;
+
+

ip_repo_sources/neuron_packed/src/Loop_HConvH_proc6.vhd

@@ -0,0 +1,746 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+-- Version: 2018.3
+-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity Loop_HConvH_proc6 is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    height_empty_n : IN STD_LOGIC;
+    height_read : OUT STD_LOGIC;
+    width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    width_empty_n : IN STD_LOGIC;
+    width_read : OUT STD_LOGIC;
+    src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+    src_V_TVALID : IN STD_LOGIC;
+    src_V_TREADY : OUT STD_LOGIC;
+    filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    filt1_empty_n : IN STD_LOGIC;
+    filt1_read : OUT STD_LOGIC;
+    filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    filt2_empty_n : IN STD_LOGIC;
+    filt2_read : OUT STD_LOGIC;
+    hconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    hconv_V_full_n : IN STD_LOGIC;
+    hconv_V_write : OUT STD_LOGIC );
+end;
+
+
+architecture behav of Loop_HConvH_proc6 is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
+    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
+    constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
+    constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
+    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
+    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
+    constant ap_const_lv10_9 : STD_LOGIC_VECTOR (9 downto 0) := "0000001001";
+    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
+    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
+
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal src_V_0_data_out : STD_LOGIC_VECTOR (31 downto 0);
+    signal src_V_0_vld_in : STD_LOGIC;
+    signal src_V_0_vld_out : STD_LOGIC;
+    signal src_V_0_ack_in : STD_LOGIC;
+    signal src_V_0_ack_out : STD_LOGIC;
+    signal src_V_0_payload_A : STD_LOGIC_VECTOR (31 downto 0);
+    signal src_V_0_payload_B : STD_LOGIC_VECTOR (31 downto 0);
+    signal src_V_0_sel_rd : STD_LOGIC := '0';
+    signal src_V_0_sel_wr : STD_LOGIC := '0';
+    signal src_V_0_sel : STD_LOGIC;
+    signal src_V_0_load_A : STD_LOGIC;
+    signal src_V_0_load_B : STD_LOGIC;
+    signal src_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    signal src_V_0_state_cmp_full : STD_LOGIC;
+    signal height_blk_n : STD_LOGIC;
+    signal width_blk_n : STD_LOGIC;
+    signal src_V_TDATA_blk_n : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
+    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0 : BOOLEAN;
+    signal exitcond_flatten_fu_214_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal filt1_blk_n : STD_LOGIC;
+    signal filt2_blk_n : STD_LOGIC;
+    signal hconv_V_blk_n : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
+    signal tmp_10_i_reg_491 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_10_i_reg_491_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal indvar_flatten_reg_141 : STD_LOGIC_VECTOR (63 downto 0);
+    signal row_0_i_i_reg_152 : STD_LOGIC_VECTOR (9 downto 0);
+    signal height_read_reg_421 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state1 : BOOLEAN;
+    signal width_read_reg_426 : STD_LOGIC_VECTOR (31 downto 0);
+    signal filt1_read_reg_432 : STD_LOGIC_VECTOR (31 downto 0);
+    signal filt2_read_reg_437 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_169_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound_reg_442 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal hwin_5_load_reg_447 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
+    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
+    signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
+    signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
+    signal ap_block_pp0_stage0_11001 : BOOLEAN;
+    signal hwin_5_load_reg_447_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_8_load_reg_452 : STD_LOGIC_VECTOR (31 downto 0);
+    signal exitcond_flatten_reg_457 : STD_LOGIC_VECTOR (0 downto 0);
+    signal exitcond_flatten_reg_457_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal indvar_flatten_next_fu_219_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_23_9_i_fu_281_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_23_9_i_reg_466 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_23_i_fu_286_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_23_i_reg_471 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_fu_291_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_reg_476 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_reg_476_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_reg_476_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_fu_303_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_reg_481 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_reg_481_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_reg_481_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp7_fu_309_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp7_reg_486 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp7_reg_486_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_10_i_fu_315_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_10_i_reg_491_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal row_fu_326_p2 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp8_fu_336_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp8_reg_500 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp5_fu_345_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp5_reg_505 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_pp0_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0_01001 : BOOLEAN;
+    signal hwin_1_1_i_fu_64 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_1_fu_68 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_2_fu_72 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_3_fu_76 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_4_fu_80 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_5_fu_84 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_6_fu_88 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_7_fu_92 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_8_fu_96 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_9_fu_100 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_169_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_169_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal row_0_i_cast_i_fu_205_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_4_i_fu_209_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_23_9_i_fu_281_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_23_i_fu_286_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp4_fu_297_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal row_0_i_i_mid2_fu_273_p3 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp9_fu_332_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp6_fu_341_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp1_fu_350_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state7 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
+    signal ap_idle_pp0 : STD_LOGIC;
+    signal ap_enable_pp0 : STD_LOGIC;
+    signal bound_fu_169_p00 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound_fu_169_p10 : STD_LOGIC_VECTOR (63 downto 0);
+
+
+begin
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then 
+                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                    ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    src_V_0_sel_rd_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                src_V_0_sel_rd <= ap_const_logic_0;
+            else
+                if (((src_V_0_ack_out = ap_const_logic_1) and (src_V_0_vld_out = ap_const_logic_1))) then 
+                                        src_V_0_sel_rd <= not(src_V_0_sel_rd);
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    src_V_0_sel_wr_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                src_V_0_sel_wr <= ap_const_logic_0;
+            else
+                if (((src_V_0_ack_in = ap_const_logic_1) and (src_V_0_vld_in = ap_const_logic_1))) then 
+                                        src_V_0_sel_wr <= not(src_V_0_sel_wr);
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    src_V_0_state_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                src_V_0_state <= ap_const_lv2_0;
+            else
+                if ((((src_V_0_state = ap_const_lv2_2) and (src_V_0_vld_in = ap_const_logic_0)) or ((src_V_0_state = ap_const_lv2_3) and (src_V_0_vld_in = ap_const_logic_0) and (src_V_0_ack_out = ap_const_logic_1)))) then 
+                    src_V_0_state <= ap_const_lv2_2;
+                elsif ((((src_V_0_state = ap_const_lv2_1) and (src_V_0_ack_out = ap_const_logic_0)) or ((src_V_0_state = ap_const_lv2_3) and (src_V_0_ack_out = ap_const_logic_0) and (src_V_0_vld_in = ap_const_logic_1)))) then 
+                    src_V_0_state <= ap_const_lv2_1;
+                elsif (((not(((src_V_0_vld_in = ap_const_logic_0) and (src_V_0_ack_out = ap_const_logic_1))) and not(((src_V_0_ack_out = ap_const_logic_0) and (src_V_0_vld_in = ap_const_logic_1))) and (src_V_0_state = ap_const_lv2_3)) or ((src_V_0_state = ap_const_lv2_1) and (src_V_0_ack_out = ap_const_logic_1)) or ((src_V_0_state = ap_const_lv2_2) and (src_V_0_vld_in = ap_const_logic_1)))) then 
+                    src_V_0_state <= ap_const_lv2_3;
+                else 
+                    src_V_0_state <= ap_const_lv2_2;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    indvar_flatten_reg_141_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
+                indvar_flatten_reg_141 <= indvar_flatten_next_fu_219_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                indvar_flatten_reg_141 <= ap_const_lv64_0;
+            end if; 
+        end if;
+    end process;
+
+    row_0_i_i_reg_152_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
+                row_0_i_i_reg_152 <= row_fu_326_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                row_0_i_i_reg_152 <= ap_const_lv10_0;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
+                bound_reg_442 <= bound_fu_169_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
+                exitcond_flatten_reg_457 <= exitcond_flatten_fu_214_p2;
+                exitcond_flatten_reg_457_pp0_iter1_reg <= exitcond_flatten_reg_457;
+                hwin_5_load_reg_447 <= hwin_5_fu_84;
+                hwin_5_load_reg_447_pp0_iter1_reg <= hwin_5_load_reg_447;
+                hwin_8_load_reg_452 <= hwin_8_fu_96;
+                tmp2_reg_476_pp0_iter1_reg <= tmp2_reg_476;
+                tmp3_reg_481_pp0_iter1_reg <= tmp3_reg_481;
+                tmp7_reg_486_pp0_iter1_reg <= tmp7_reg_486;
+                tmp_10_i_reg_491_pp0_iter1_reg <= tmp_10_i_reg_491;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                filt1_read_reg_432 <= filt1_dout;
+                filt2_read_reg_437 <= filt2_dout;
+                height_read_reg_421 <= height_dout;
+                width_read_reg_426 <= width_dout;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
+                hwin_1_1_i_fu_64 <= hwin_1_fu_68;
+                hwin_1_fu_68 <= hwin_2_fu_72;
+                hwin_2_fu_72 <= hwin_3_fu_76;
+                hwin_3_fu_76 <= hwin_4_fu_80;
+                hwin_4_fu_80 <= hwin_5_fu_84;
+                hwin_5_fu_84 <= hwin_6_fu_88;
+                hwin_6_fu_88 <= hwin_7_fu_92;
+                hwin_7_fu_92 <= hwin_8_fu_96;
+                hwin_8_fu_96 <= hwin_9_fu_100;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
+                hwin_9_fu_100 <= src_V_0_data_out;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((src_V_0_load_A = ap_const_logic_1)) then
+                src_V_0_payload_A <= src_V_TDATA;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((src_V_0_load_B = ap_const_logic_1)) then
+                src_V_0_payload_B <= src_V_TDATA;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
+                tmp2_reg_476 <= tmp2_fu_291_p2;
+                tmp3_reg_481 <= tmp3_fu_303_p2;
+                tmp7_reg_486 <= tmp7_fu_309_p2;
+                tmp_10_i_reg_491 <= tmp_10_i_fu_315_p2;
+                tmp_23_9_i_reg_466 <= tmp_23_9_i_fu_281_p2;
+                tmp_23_i_reg_471 <= tmp_23_i_fu_286_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
+                tmp2_reg_476_pp0_iter2_reg <= tmp2_reg_476_pp0_iter1_reg;
+                tmp3_reg_481_pp0_iter2_reg <= tmp3_reg_481_pp0_iter1_reg;
+                tmp_10_i_reg_491_pp0_iter2_reg <= tmp_10_i_reg_491_pp0_iter1_reg;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_reg_457_pp0_iter1_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
+                tmp5_reg_505 <= tmp5_fu_345_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_reg_457 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
+                tmp8_reg_500 <= tmp8_fu_336_p2;
+            end if;
+        end if;
+    end process;
+
+    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+            when ap_ST_fsm_pp0_stage0 => 
+                if ((not(((exitcond_flatten_fu_214_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) and not(((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                elsif ((((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state7;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                end if;
+            when ap_ST_fsm_state7 => 
+                ap_NS_fsm <= ap_ST_fsm_state1;
+            when others =>  
+                ap_NS_fsm <= "XXXX";
+        end case;
+    end process;
+    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state7 <= ap_CS_fsm(3);
+        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage0_01001_assign_proc : process(src_V_0_vld_out, hconv_V_full_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
+    begin
+                ap_block_pp0_stage0_01001 <= (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)));
+    end process;
+
+
+    ap_block_pp0_stage0_11001_assign_proc : process(src_V_0_vld_out, hconv_V_full_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
+    begin
+                ap_block_pp0_stage0_11001 <= (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)));
+    end process;
+
+
+    ap_block_pp0_stage0_subdone_assign_proc : process(src_V_0_vld_out, hconv_V_full_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
+    begin
+                ap_block_pp0_stage0_subdone <= (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)));
+    end process;
+
+
+    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
+    begin
+                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
+    end process;
+
+
+    ap_block_state3_pp0_stage0_iter0_assign_proc : process(src_V_0_vld_out, exitcond_flatten_fu_214_p2)
+    begin
+                ap_block_state3_pp0_stage0_iter0 <= ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0));
+    end process;
+
+        ap_block_state4_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state6_pp0_stage0_iter3_assign_proc : process(hconv_V_full_n, tmp_10_i_reg_491_pp0_iter2_reg)
+    begin
+                ap_block_state6_pp0_stage0_iter3 <= ((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0));
+    end process;
+
+
+    ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_flatten_fu_214_p2)
+    begin
+        if ((exitcond_flatten_fu_214_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
+        else 
+            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state7)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_done_reg;
+        end if; 
+    end process;
+
+    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
+
+    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
+    begin
+        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
+    begin
+        if (((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then 
+            ap_idle_pp0 <= ap_const_logic_1;
+        else 
+            ap_idle_pp0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_ready_assign_proc : process(ap_CS_fsm_state7)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
+            ap_ready <= ap_const_logic_1;
+        else 
+            ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    bound_fu_169_p0 <= bound_fu_169_p00(32 - 1 downto 0);
+    bound_fu_169_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(width_read_reg_426),64));
+    bound_fu_169_p1 <= bound_fu_169_p10(32 - 1 downto 0);
+    bound_fu_169_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(height_read_reg_421),64));
+    bound_fu_169_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_169_p0) * unsigned(bound_fu_169_p1), 64));
+    exitcond_flatten_fu_214_p2 <= "1" when (indvar_flatten_reg_141 = bound_reg_442) else "0";
+
+    filt1_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt1_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt1_blk_n <= filt1_empty_n;
+        else 
+            filt1_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    filt1_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt1_read <= ap_const_logic_1;
+        else 
+            filt1_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    filt2_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt2_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt2_blk_n <= filt2_empty_n;
+        else 
+            filt2_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    filt2_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt2_read <= ap_const_logic_1;
+        else 
+            filt2_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    hconv_V_blk_n_assign_proc : process(hconv_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
+    begin
+        if (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
+            hconv_V_blk_n <= hconv_V_full_n;
+        else 
+            hconv_V_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    hconv_V_din <= std_logic_vector(unsigned(tmp5_reg_505) + unsigned(tmp1_fu_350_p2));
+
+    hconv_V_write_assign_proc : process(ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg, ap_block_pp0_stage0_11001)
+    begin
+        if (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
+            hconv_V_write <= ap_const_logic_1;
+        else 
+            hconv_V_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    height_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_blk_n <= height_empty_n;
+        else 
+            height_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    height_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_read <= ap_const_logic_1;
+        else 
+            height_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    indvar_flatten_next_fu_219_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_141) + unsigned(ap_const_lv64_1));
+    row_0_i_cast_i_fu_205_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_0_i_i_reg_152),32));
+    row_0_i_i_mid2_fu_273_p3 <= 
+        row_0_i_i_reg_152 when (tmp_4_i_fu_209_p2(0) = '1') else 
+        ap_const_lv10_0;
+    row_fu_326_p2 <= std_logic_vector(unsigned(row_0_i_i_mid2_fu_273_p3) + unsigned(ap_const_lv10_1));
+    src_V_0_ack_in <= src_V_0_state(1);
+
+    src_V_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_block_pp0_stage0_11001)
+    begin
+        if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
+            src_V_0_ack_out <= ap_const_logic_1;
+        else 
+            src_V_0_ack_out <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    src_V_0_data_out_assign_proc : process(src_V_0_payload_A, src_V_0_payload_B, src_V_0_sel)
+    begin
+        if ((src_V_0_sel = ap_const_logic_1)) then 
+            src_V_0_data_out <= src_V_0_payload_B;
+        else 
+            src_V_0_data_out <= src_V_0_payload_A;
+        end if; 
+    end process;
+
+    src_V_0_load_A <= (src_V_0_state_cmp_full and not(src_V_0_sel_wr));
+    src_V_0_load_B <= (src_V_0_state_cmp_full and src_V_0_sel_wr);
+    src_V_0_sel <= src_V_0_sel_rd;
+    src_V_0_state_cmp_full <= '0' when (src_V_0_state = ap_const_lv2_1) else '1';
+    src_V_0_vld_in <= src_V_TVALID;
+    src_V_0_vld_out <= src_V_0_state(0);
+
+    src_V_TDATA_blk_n_assign_proc : process(src_V_0_state, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0, exitcond_flatten_fu_214_p2)
+    begin
+        if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
+            src_V_TDATA_blk_n <= src_V_0_state(0);
+        else 
+            src_V_TDATA_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    src_V_TREADY <= src_V_0_state(1);
+    tmp1_fu_350_p2 <= std_logic_vector(unsigned(tmp3_reg_481_pp0_iter2_reg) + unsigned(tmp2_reg_476_pp0_iter2_reg));
+    tmp2_fu_291_p2 <= std_logic_vector(unsigned(hwin_1_1_i_fu_64) + unsigned(hwin_1_fu_68));
+    tmp3_fu_303_p2 <= std_logic_vector(unsigned(tmp4_fu_297_p2) + unsigned(hwin_2_fu_72));
+    tmp4_fu_297_p2 <= std_logic_vector(unsigned(hwin_3_fu_76) + unsigned(hwin_4_fu_80));
+    tmp5_fu_345_p2 <= std_logic_vector(unsigned(tmp8_reg_500) + unsigned(tmp6_fu_341_p2));
+    tmp6_fu_341_p2 <= std_logic_vector(unsigned(tmp7_reg_486_pp0_iter1_reg) + unsigned(hwin_5_load_reg_447_pp0_iter1_reg));
+    tmp7_fu_309_p2 <= std_logic_vector(unsigned(hwin_6_fu_88) + unsigned(hwin_7_fu_92));
+    tmp8_fu_336_p2 <= std_logic_vector(unsigned(tmp9_fu_332_p2) + unsigned(hwin_8_load_reg_452));
+    tmp9_fu_332_p2 <= std_logic_vector(unsigned(tmp_23_9_i_reg_466) + unsigned(tmp_23_i_reg_471));
+    tmp_10_i_fu_315_p2 <= "1" when (unsigned(row_0_i_i_mid2_fu_273_p3) > unsigned(ap_const_lv10_9)) else "0";
+    tmp_23_9_i_fu_281_p1 <= hwin_9_fu_100;
+    tmp_23_9_i_fu_281_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt1_read_reg_432) * signed(tmp_23_9_i_fu_281_p1))), 32));
+    tmp_23_i_fu_286_p1 <= src_V_0_data_out;
+    tmp_23_i_fu_286_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt2_read_reg_437) * signed(tmp_23_i_fu_286_p1))), 32));
+    tmp_4_i_fu_209_p2 <= "1" when (signed(row_0_i_cast_i_fu_205_p1) < signed(width_read_reg_426)) else "0";
+
+    width_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_blk_n <= width_empty_n;
+        else 
+            width_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    width_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_read <= ap_const_logic_1;
+        else 
+            width_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+end behav;

ip_repo_sources/neuron_packed/src/Loop_VConvH_proc.vhd

@@ -0,0 +1,1570 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+-- Version: 2018.3
+-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity Loop_VConvH_proc is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    height_empty_n : IN STD_LOGIC;
+    height_read : OUT STD_LOGIC;
+    vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    vconv_xlim_loc_empty_n : IN STD_LOGIC;
+    vconv_xlim_loc_read : OUT STD_LOGIC;
+    hconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    hconv_V_empty_n : IN STD_LOGIC;
+    hconv_V_read : OUT STD_LOGIC;
+    vconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    vconv_V_full_n : IN STD_LOGIC;
+    vconv_V_write : OUT STD_LOGIC;
+    filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    filt1_empty_n : IN STD_LOGIC;
+    filt1_read : OUT STD_LOGIC;
+    filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    filt2_empty_n : IN STD_LOGIC;
+    filt2_read : OUT STD_LOGIC;
+    height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    height_out_full_n : IN STD_LOGIC;
+    height_out_write : OUT STD_LOGIC;
+    vconv_xlim_loc_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    vconv_xlim_loc_out_full_n : IN STD_LOGIC;
+    vconv_xlim_loc_out_write : OUT STD_LOGIC );
+end;
+
+
+architecture behav of Loop_VConvH_proc is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
+    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
+    constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
+    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
+    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
+    constant ap_const_lv10_9 : STD_LOGIC_VECTOR (9 downto 0) := "0000001001";
+    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
+
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal linebuf_0_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_0_ce0 : STD_LOGIC;
+    signal linebuf_0_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_0_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_0_ce1 : STD_LOGIC;
+    signal linebuf_0_we1 : STD_LOGIC;
+    signal linebuf_1_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_1_ce0 : STD_LOGIC;
+    signal linebuf_1_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_1_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_1_ce1 : STD_LOGIC;
+    signal linebuf_1_we1 : STD_LOGIC;
+    signal linebuf_2_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_2_ce0 : STD_LOGIC;
+    signal linebuf_2_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_2_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_2_ce1 : STD_LOGIC;
+    signal linebuf_2_we1 : STD_LOGIC;
+    signal linebuf_3_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_3_ce0 : STD_LOGIC;
+    signal linebuf_3_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_3_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_3_ce1 : STD_LOGIC;
+    signal linebuf_3_we1 : STD_LOGIC;
+    signal linebuf_4_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_4_ce0 : STD_LOGIC;
+    signal linebuf_4_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_4_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_4_ce1 : STD_LOGIC;
+    signal linebuf_4_we1 : STD_LOGIC;
+    signal linebuf_5_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_5_ce0 : STD_LOGIC;
+    signal linebuf_5_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_5_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_5_ce1 : STD_LOGIC;
+    signal linebuf_5_we1 : STD_LOGIC;
+    signal linebuf_6_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_6_ce0 : STD_LOGIC;
+    signal linebuf_6_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_6_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_6_ce1 : STD_LOGIC;
+    signal linebuf_6_we1 : STD_LOGIC;
+    signal linebuf_7_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_7_ce0 : STD_LOGIC;
+    signal linebuf_7_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_7_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_7_ce1 : STD_LOGIC;
+    signal linebuf_7_we1 : STD_LOGIC;
+    signal linebuf_8_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_8_ce0 : STD_LOGIC;
+    signal linebuf_8_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_8_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_8_ce1 : STD_LOGIC;
+    signal linebuf_8_we1 : STD_LOGIC;
+    signal linebuf_9_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_9_ce0 : STD_LOGIC;
+    signal linebuf_9_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_9_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_9_ce1 : STD_LOGIC;
+    signal linebuf_9_we1 : STD_LOGIC;
+    signal height_blk_n : STD_LOGIC;
+    signal vconv_xlim_loc_blk_n : STD_LOGIC;
+    signal hconv_V_blk_n : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
+    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0 : BOOLEAN;
+    signal exitcond_flatten_reg_532 : STD_LOGIC_VECTOR (0 downto 0);
+    signal vconv_V_blk_n : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
+    signal tmp_8_i_i_mid2_reg_541 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_8_i_i_mid2_reg_541_pp0_iter4_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal filt1_blk_n : STD_LOGIC;
+    signal filt2_blk_n : STD_LOGIC;
+    signal height_out_blk_n : STD_LOGIC;
+    signal vconv_xlim_loc_out_blk_n : STD_LOGIC;
+    signal indvar_flatten_reg_319 : STD_LOGIC_VECTOR (63 downto 0);
+    signal col1_0_i_i_i_reg_330 : STD_LOGIC_VECTOR (9 downto 0);
+    signal row2_0_i_i_i_reg_341 : STD_LOGIC_VECTOR (9 downto 0);
+    signal height_read_reg_506 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state1 : BOOLEAN;
+    signal vconv_xlim_loc_read_reg_511 : STD_LOGIC_VECTOR (31 downto 0);
+    signal filt1_read_reg_517 : STD_LOGIC_VECTOR (31 downto 0);
+    signal filt2_read_reg_522 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_358_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound_reg_527 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal exitcond_flatten_fu_373_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
+    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
+    signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
+    signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
+    signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
+    signal ap_block_state8_pp0_stage0_iter5 : BOOLEAN;
+    signal ap_block_pp0_stage0_11001 : BOOLEAN;
+    signal exitcond_flatten_reg_532_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal exitcond_flatten_reg_532_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal exitcond_flatten_reg_532_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal indvar_flatten_next_fu_378_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
+    signal tmp_8_i_i_mid2_fu_410_p3 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_8_i_i_mid2_reg_541_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_8_i_i_mid2_reg_541_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_8_i_i_mid2_reg_541_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal col1_0_i_i_i_mid2_fu_418_p3 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_0_addr_reg_550 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_1_addr_reg_556 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_2_addr_reg_562 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_3_addr_reg_568 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_4_addr_reg_574 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_5_addr_reg_580 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_6_addr_reg_586 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_7_addr_reg_592 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_8_addr_reg_598 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_9_addr_reg_604 : STD_LOGIC_VECTOR (9 downto 0);
+    signal row_fu_440_p2 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp_1_reg_615 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_5_load_reg_620 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_5_load_reg_620_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_5_load_reg_620_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_8_load_reg_625 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_8_load_reg_625_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_9_load_reg_630 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_fu_446_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_reg_635 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_reg_635_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_reg_635_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_reg_635_pp0_iter4_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_fu_458_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_reg_640 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_reg_640_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_reg_640_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_reg_640_pp0_iter4_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp7_fu_464_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp7_reg_645 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp7_reg_645_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp7_reg_645_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_30_9_i_i_fu_470_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_30_9_i_i_reg_650 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_30_i_i_fu_474_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_30_i_i_reg_655 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp8_fu_482_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp8_reg_660 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp5_fu_491_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp5_reg_665 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_pp0_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
+    signal tmp_16_i_i_fu_426_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_block_pp0_stage0_01001 : BOOLEAN;
+    signal bound_fu_358_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_358_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal row2_0_i_cast_i_i_fu_364_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_11_i_i_fu_368_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal col_fu_392_p2 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp_8_i_i_fu_404_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_8_i_i_mid1_fu_398_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal row2_0_i_i_i_mid2_fu_384_p3 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp4_fu_452_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp9_fu_478_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp6_fu_487_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp1_fu_496_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state9 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
+    signal ap_block_pp0 : BOOLEAN;
+    signal ap_enable_operation_44 : BOOLEAN;
+    signal ap_enable_state3_pp0_iter0_stage0 : BOOLEAN;
+    signal ap_enable_operation_66 : BOOLEAN;
+    signal ap_enable_state4_pp0_iter1_stage0 : BOOLEAN;
+    signal ap_enable_operation_68 : BOOLEAN;
+    signal ap_enable_operation_46 : BOOLEAN;
+    signal ap_enable_operation_67 : BOOLEAN;
+    signal ap_enable_operation_70 : BOOLEAN;
+    signal ap_enable_operation_48 : BOOLEAN;
+    signal ap_enable_operation_69 : BOOLEAN;
+    signal ap_enable_operation_72 : BOOLEAN;
+    signal ap_enable_operation_50 : BOOLEAN;
+    signal ap_enable_operation_71 : BOOLEAN;
+    signal ap_enable_operation_74 : BOOLEAN;
+    signal ap_enable_operation_52 : BOOLEAN;
+    signal ap_enable_operation_73 : BOOLEAN;
+    signal ap_enable_operation_76 : BOOLEAN;
+    signal ap_enable_operation_54 : BOOLEAN;
+    signal ap_enable_operation_75 : BOOLEAN;
+    signal ap_enable_operation_78 : BOOLEAN;
+    signal ap_enable_operation_56 : BOOLEAN;
+    signal ap_enable_operation_77 : BOOLEAN;
+    signal ap_enable_operation_80 : BOOLEAN;
+    signal ap_enable_operation_58 : BOOLEAN;
+    signal ap_enable_operation_79 : BOOLEAN;
+    signal ap_enable_operation_82 : BOOLEAN;
+    signal ap_enable_operation_60 : BOOLEAN;
+    signal ap_enable_operation_81 : BOOLEAN;
+    signal ap_enable_operation_84 : BOOLEAN;
+    signal ap_enable_operation_62 : BOOLEAN;
+    signal ap_enable_operation_83 : BOOLEAN;
+    signal ap_enable_operation_89 : BOOLEAN;
+    signal ap_idle_pp0 : STD_LOGIC;
+    signal ap_enable_pp0 : STD_LOGIC;
+    signal bound_fu_358_p00 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound_fu_358_p10 : STD_LOGIC_VECTOR (63 downto 0);
+
+    component Loop_VConvH_proc_linebuf_0 IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (9 downto 0);
+        ce0 : IN STD_LOGIC;
+        q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        address1 : IN STD_LOGIC_VECTOR (9 downto 0);
+        ce1 : IN STD_LOGIC;
+        we1 : IN STD_LOGIC;
+        d1 : IN STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+
+begin
+    linebuf_0_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_0_address0,
+        ce0 => linebuf_0_ce0,
+        q0 => linebuf_0_q0,
+        address1 => linebuf_0_address1,
+        ce1 => linebuf_0_ce1,
+        we1 => linebuf_0_we1,
+        d1 => linebuf_1_q0);
+
+    linebuf_1_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_1_address0,
+        ce0 => linebuf_1_ce0,
+        q0 => linebuf_1_q0,
+        address1 => linebuf_1_address1,
+        ce1 => linebuf_1_ce1,
+        we1 => linebuf_1_we1,
+        d1 => linebuf_2_q0);
+
+    linebuf_2_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_2_address0,
+        ce0 => linebuf_2_ce0,
+        q0 => linebuf_2_q0,
+        address1 => linebuf_2_address1,
+        ce1 => linebuf_2_ce1,
+        we1 => linebuf_2_we1,
+        d1 => linebuf_3_q0);
+
+    linebuf_3_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_3_address0,
+        ce0 => linebuf_3_ce0,
+        q0 => linebuf_3_q0,
+        address1 => linebuf_3_address1,
+        ce1 => linebuf_3_ce1,
+        we1 => linebuf_3_we1,
+        d1 => linebuf_4_q0);
+
+    linebuf_4_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_4_address0,
+        ce0 => linebuf_4_ce0,
+        q0 => linebuf_4_q0,
+        address1 => linebuf_4_address1,
+        ce1 => linebuf_4_ce1,
+        we1 => linebuf_4_we1,
+        d1 => linebuf_5_q0);
+
+    linebuf_5_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_5_address0,
+        ce0 => linebuf_5_ce0,
+        q0 => linebuf_5_q0,
+        address1 => linebuf_5_address1,
+        ce1 => linebuf_5_ce1,
+        we1 => linebuf_5_we1,
+        d1 => linebuf_6_q0);
+
+    linebuf_6_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_6_address0,
+        ce0 => linebuf_6_ce0,
+        q0 => linebuf_6_q0,
+        address1 => linebuf_6_address1,
+        ce1 => linebuf_6_ce1,
+        we1 => linebuf_6_we1,
+        d1 => linebuf_7_q0);
+
+    linebuf_7_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_7_address0,
+        ce0 => linebuf_7_ce0,
+        q0 => linebuf_7_q0,
+        address1 => linebuf_7_address1,
+        ce1 => linebuf_7_ce1,
+        we1 => linebuf_7_we1,
+        d1 => linebuf_8_q0);
+
+    linebuf_8_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_8_address0,
+        ce0 => linebuf_8_ce0,
+        q0 => linebuf_8_q0,
+        address1 => linebuf_8_address1,
+        ce1 => linebuf_8_ce1,
+        we1 => linebuf_8_we1,
+        d1 => linebuf_9_q0);
+
+    linebuf_9_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_9_address0,
+        ce0 => linebuf_9_ce0,
+        q0 => linebuf_9_q0,
+        address1 => linebuf_9_address1,
+        ce1 => linebuf_9_ce1,
+        we1 => linebuf_9_we1,
+        d1 => hconv_V_dout);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then 
+                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                    ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    col1_0_i_i_i_reg_330_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
+                col1_0_i_i_i_reg_330 <= col1_0_i_i_i_mid2_fu_418_p3;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                col1_0_i_i_i_reg_330 <= ap_const_lv10_0;
+            end if; 
+        end if;
+    end process;
+
+    indvar_flatten_reg_319_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
+                indvar_flatten_reg_319 <= indvar_flatten_next_fu_378_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                indvar_flatten_reg_319 <= ap_const_lv64_0;
+            end if; 
+        end if;
+    end process;
+
+    row2_0_i_i_i_reg_341_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
+                row2_0_i_i_i_reg_341 <= row_fu_440_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                row2_0_i_i_i_reg_341 <= ap_const_lv10_0;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
+                bound_reg_527 <= bound_fu_358_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                exitcond_flatten_reg_532 <= exitcond_flatten_fu_373_p2;
+                exitcond_flatten_reg_532_pp0_iter1_reg <= exitcond_flatten_reg_532;
+                tmp_8_i_i_mid2_reg_541_pp0_iter1_reg <= tmp_8_i_i_mid2_reg_541;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
+                exitcond_flatten_reg_532_pp0_iter2_reg <= exitcond_flatten_reg_532_pp0_iter1_reg;
+                exitcond_flatten_reg_532_pp0_iter3_reg <= exitcond_flatten_reg_532_pp0_iter2_reg;
+                linebuf_5_load_reg_620_pp0_iter2_reg <= linebuf_5_load_reg_620;
+                linebuf_5_load_reg_620_pp0_iter3_reg <= linebuf_5_load_reg_620_pp0_iter2_reg;
+                linebuf_8_load_reg_625_pp0_iter2_reg <= linebuf_8_load_reg_625;
+                tmp2_reg_635_pp0_iter2_reg <= tmp2_reg_635;
+                tmp2_reg_635_pp0_iter3_reg <= tmp2_reg_635_pp0_iter2_reg;
+                tmp2_reg_635_pp0_iter4_reg <= tmp2_reg_635_pp0_iter3_reg;
+                tmp3_reg_640_pp0_iter2_reg <= tmp3_reg_640;
+                tmp3_reg_640_pp0_iter3_reg <= tmp3_reg_640_pp0_iter2_reg;
+                tmp3_reg_640_pp0_iter4_reg <= tmp3_reg_640_pp0_iter3_reg;
+                tmp7_reg_645_pp0_iter2_reg <= tmp7_reg_645;
+                tmp7_reg_645_pp0_iter3_reg <= tmp7_reg_645_pp0_iter2_reg;
+                tmp_8_i_i_mid2_reg_541_pp0_iter2_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter1_reg;
+                tmp_8_i_i_mid2_reg_541_pp0_iter3_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter2_reg;
+                tmp_8_i_i_mid2_reg_541_pp0_iter4_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter3_reg;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                filt1_read_reg_517 <= filt1_dout;
+                filt2_read_reg_522 <= filt2_dout;
+                height_read_reg_506 <= height_dout;
+                vconv_xlim_loc_read_reg_511 <= vconv_xlim_loc_dout;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then
+                linebuf_0_addr_reg_550 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_1_addr_reg_556 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_2_addr_reg_562 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_3_addr_reg_568 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_4_addr_reg_574 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_5_addr_reg_580 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_6_addr_reg_586 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_7_addr_reg_592 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_8_addr_reg_598 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_9_addr_reg_604 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                tmp_8_i_i_mid2_reg_541 <= tmp_8_i_i_mid2_fu_410_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then
+                linebuf_5_load_reg_620 <= linebuf_5_q0;
+                linebuf_8_load_reg_625 <= linebuf_8_q0;
+                linebuf_9_load_reg_630 <= linebuf_9_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then
+                tmp2_reg_635 <= tmp2_fu_446_p2;
+                tmp3_reg_640 <= tmp3_fu_458_p2;
+                tmp7_reg_645 <= tmp7_fu_464_p2;
+                tmp_1_reg_615 <= hconv_V_dout;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter3_reg = ap_const_lv1_0))) then
+                tmp5_reg_665 <= tmp5_fu_491_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter2_reg = ap_const_lv1_0))) then
+                tmp8_reg_660 <= tmp8_fu_482_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter1_reg = ap_const_lv1_0))) then
+                tmp_30_9_i_i_reg_650 <= tmp_30_9_i_i_fu_470_p2;
+                tmp_30_i_i_reg_655 <= tmp_30_i_i_fu_474_p2;
+            end if;
+        end if;
+    end process;
+
+    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter5, exitcond_flatten_fu_373_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter4)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+            when ap_ST_fsm_pp0_stage0 => 
+                if ((not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) and not(((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                elsif ((((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)) or ((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state9;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                end if;
+            when ap_ST_fsm_state9 => 
+                ap_NS_fsm <= ap_ST_fsm_state1;
+            when others =>  
+                ap_NS_fsm <= "XXXX";
+        end case;
+    end process;
+    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state9 <= ap_CS_fsm(3);
+
+    ap_block_pp0_assign_proc : process(ap_CS_fsm, ap_block_pp0_stage0_subdone)
+    begin
+                ap_block_pp0 <= ((ap_ST_fsm_pp0_stage0 = ap_CS_fsm) and (ap_const_boolean_1 = ap_block_pp0_stage0_subdone));
+    end process;
+
+        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage0_01001_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
+    begin
+                ap_block_pp0_stage0_01001 <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
+    end process;
+
+
+    ap_block_pp0_stage0_11001_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
+    begin
+                ap_block_pp0_stage0_11001 <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
+    end process;
+
+
+    ap_block_pp0_stage0_subdone_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
+    begin
+                ap_block_pp0_stage0_subdone <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
+    end process;
+
+
+    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
+    begin
+                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
+    end process;
+
+        ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state4_pp0_stage0_iter1_assign_proc : process(hconv_V_empty_n, exitcond_flatten_reg_532)
+    begin
+                ap_block_state4_pp0_stage0_iter1 <= ((hconv_V_empty_n = ap_const_logic_0) and (exitcond_flatten_reg_532 = ap_const_lv1_0));
+    end process;
+
+        ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state8_pp0_stage0_iter5_assign_proc : process(vconv_V_full_n, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
+    begin
+                ap_block_state8_pp0_stage0_iter5 <= ((vconv_V_full_n = ap_const_logic_0) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1));
+    end process;
+
+
+    ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+        if ((exitcond_flatten_fu_373_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
+        else 
+            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state9)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_done_reg;
+        end if; 
+    end process;
+
+
+    ap_enable_operation_44_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_44 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_46_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_46 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_48_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_48 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_50_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_50 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_52_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_52 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_54_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_54 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_56_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_56 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_58_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_58 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_60_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_60 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_62_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_62 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_66_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_66 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_67_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_67 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_68_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_68 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_69_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_69 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_70_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_70 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_71_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_71 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_72_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_72 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_73_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_73 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_74_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_74 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_75_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_75 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_76_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_76 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_77_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_77 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_78_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_78 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_79_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_79 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_80_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_80 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_81_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_81 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_82_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_82 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_83_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_83 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_84_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_84 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_89_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_89 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
+
+    ap_enable_state3_pp0_iter0_stage0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0)
+    begin
+                ap_enable_state3_pp0_iter0_stage0 <= ((ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0));
+    end process;
+
+
+    ap_enable_state4_pp0_iter1_stage0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
+    begin
+                ap_enable_state4_pp0_iter1_stage0 <= ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0));
+    end process;
+
+
+    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
+    begin
+        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4)
+    begin
+        if (((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then 
+            ap_idle_pp0 <= ap_const_logic_1;
+        else 
+            ap_idle_pp0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_ready_assign_proc : process(ap_CS_fsm_state9)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
+            ap_ready <= ap_const_logic_1;
+        else 
+            ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    bound_fu_358_p0 <= bound_fu_358_p00(32 - 1 downto 0);
+    bound_fu_358_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(vconv_xlim_loc_read_reg_511),64));
+    bound_fu_358_p1 <= bound_fu_358_p10(32 - 1 downto 0);
+    bound_fu_358_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(height_read_reg_506),64));
+    bound_fu_358_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_358_p0) * unsigned(bound_fu_358_p1), 64));
+    col1_0_i_i_i_mid2_fu_418_p3 <= 
+        col1_0_i_i_i_reg_330 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
+        col_fu_392_p2;
+    col_fu_392_p2 <= std_logic_vector(unsigned(col1_0_i_i_i_reg_330) + unsigned(ap_const_lv10_1));
+    exitcond_flatten_fu_373_p2 <= "1" when (indvar_flatten_reg_319 = bound_reg_527) else "0";
+
+    filt1_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt1_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt1_blk_n <= filt1_empty_n;
+        else 
+            filt1_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    filt1_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt1_read <= ap_const_logic_1;
+        else 
+            filt1_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    filt2_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt2_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt2_blk_n <= filt2_empty_n;
+        else 
+            filt2_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    filt2_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt2_read <= ap_const_logic_1;
+        else 
+            filt2_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    hconv_V_blk_n_assign_proc : process(hconv_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_flatten_reg_532)
+    begin
+        if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
+            hconv_V_blk_n <= hconv_V_empty_n;
+        else 
+            hconv_V_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    hconv_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            hconv_V_read <= ap_const_logic_1;
+        else 
+            hconv_V_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    height_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_blk_n <= height_empty_n;
+        else 
+            height_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    height_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_out_blk_n <= height_out_full_n;
+        else 
+            height_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    height_out_din <= height_dout;
+
+    height_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_out_write <= ap_const_logic_1;
+        else 
+            height_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    height_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_read <= ap_const_logic_1;
+        else 
+            height_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    indvar_flatten_next_fu_378_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_319) + unsigned(ap_const_lv64_1));
+    linebuf_0_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_0_address1 <= linebuf_0_addr_reg_550;
+
+    linebuf_0_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_0_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_0_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_0_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_0_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_0_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_0_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_0_we1 <= ap_const_logic_1;
+        else 
+            linebuf_0_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_1_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_1_address1 <= linebuf_1_addr_reg_556;
+
+    linebuf_1_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_1_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_1_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_1_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_1_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_1_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_1_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_1_we1 <= ap_const_logic_1;
+        else 
+            linebuf_1_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_2_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_2_address1 <= linebuf_2_addr_reg_562;
+
+    linebuf_2_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_2_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_2_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_2_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_2_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_2_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_2_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_2_we1 <= ap_const_logic_1;
+        else 
+            linebuf_2_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_3_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_3_address1 <= linebuf_3_addr_reg_568;
+
+    linebuf_3_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_3_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_3_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_3_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_3_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_3_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_3_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_3_we1 <= ap_const_logic_1;
+        else 
+            linebuf_3_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_4_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_4_address1 <= linebuf_4_addr_reg_574;
+
+    linebuf_4_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_4_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_4_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_4_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_4_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_4_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_4_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_4_we1 <= ap_const_logic_1;
+        else 
+            linebuf_4_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_5_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_5_address1 <= linebuf_5_addr_reg_580;
+
+    linebuf_5_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_5_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_5_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_5_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_5_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_5_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_5_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_5_we1 <= ap_const_logic_1;
+        else 
+            linebuf_5_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_6_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_6_address1 <= linebuf_6_addr_reg_586;
+
+    linebuf_6_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_6_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_6_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_6_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_6_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_6_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_6_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_6_we1 <= ap_const_logic_1;
+        else 
+            linebuf_6_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_7_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_7_address1 <= linebuf_7_addr_reg_592;
+
+    linebuf_7_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_7_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_7_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_7_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_7_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_7_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_7_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_7_we1 <= ap_const_logic_1;
+        else 
+            linebuf_7_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_8_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_8_address1 <= linebuf_8_addr_reg_598;
+
+    linebuf_8_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_8_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_8_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_8_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_8_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_8_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_8_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_8_we1 <= ap_const_logic_1;
+        else 
+            linebuf_8_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_9_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_9_address1 <= linebuf_9_addr_reg_604;
+
+    linebuf_9_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_9_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_9_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_9_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_9_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_9_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_9_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_9_we1 <= ap_const_logic_1;
+        else 
+            linebuf_9_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    row2_0_i_cast_i_i_fu_364_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row2_0_i_i_i_reg_341),32));
+    row2_0_i_i_i_mid2_fu_384_p3 <= 
+        row2_0_i_i_i_reg_341 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
+        ap_const_lv10_0;
+    row_fu_440_p2 <= std_logic_vector(unsigned(row2_0_i_i_i_mid2_fu_384_p3) + unsigned(ap_const_lv10_1));
+    tmp1_fu_496_p2 <= std_logic_vector(unsigned(tmp3_reg_640_pp0_iter4_reg) + unsigned(tmp2_reg_635_pp0_iter4_reg));
+    tmp2_fu_446_p2 <= std_logic_vector(unsigned(linebuf_0_q0) + unsigned(linebuf_1_q0));
+    tmp3_fu_458_p2 <= std_logic_vector(unsigned(tmp4_fu_452_p2) + unsigned(linebuf_2_q0));
+    tmp4_fu_452_p2 <= std_logic_vector(unsigned(linebuf_3_q0) + unsigned(linebuf_4_q0));
+    tmp5_fu_491_p2 <= std_logic_vector(unsigned(tmp8_reg_660) + unsigned(tmp6_fu_487_p2));
+    tmp6_fu_487_p2 <= std_logic_vector(unsigned(tmp7_reg_645_pp0_iter3_reg) + unsigned(linebuf_5_load_reg_620_pp0_iter3_reg));
+    tmp7_fu_464_p2 <= std_logic_vector(unsigned(linebuf_6_q0) + unsigned(linebuf_7_q0));
+    tmp8_fu_482_p2 <= std_logic_vector(unsigned(tmp9_fu_478_p2) + unsigned(linebuf_8_load_reg_625_pp0_iter2_reg));
+    tmp9_fu_478_p2 <= std_logic_vector(unsigned(tmp_30_9_i_i_reg_650) + unsigned(tmp_30_i_i_reg_655));
+    tmp_11_i_i_fu_368_p2 <= "1" when (signed(row2_0_i_cast_i_i_fu_364_p1) < signed(vconv_xlim_loc_read_reg_511)) else "0";
+    tmp_16_i_i_fu_426_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row2_0_i_i_i_mid2_fu_384_p3),64));
+    tmp_30_9_i_i_fu_470_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt1_read_reg_517) * signed(linebuf_9_load_reg_630))), 32));
+    tmp_30_i_i_fu_474_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt2_read_reg_522) * signed(tmp_1_reg_615))), 32));
+    tmp_8_i_i_fu_404_p2 <= "1" when (unsigned(col1_0_i_i_i_reg_330) > unsigned(ap_const_lv10_9)) else "0";
+    tmp_8_i_i_mid1_fu_398_p2 <= "1" when (unsigned(col_fu_392_p2) > unsigned(ap_const_lv10_9)) else "0";
+    tmp_8_i_i_mid2_fu_410_p3 <= 
+        tmp_8_i_i_fu_404_p2 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
+        tmp_8_i_i_mid1_fu_398_p2;
+
+    vconv_V_blk_n_assign_proc : process(vconv_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
+    begin
+        if (((ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
+            vconv_V_blk_n <= vconv_V_full_n;
+        else 
+            vconv_V_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    vconv_V_din <= std_logic_vector(unsigned(tmp5_reg_665) + unsigned(tmp1_fu_496_p2));
+
+    vconv_V_write_assign_proc : process(ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1))) then 
+            vconv_V_write <= ap_const_logic_1;
+        else 
+            vconv_V_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    vconv_xlim_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            vconv_xlim_loc_blk_n <= vconv_xlim_loc_empty_n;
+        else 
+            vconv_xlim_loc_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    vconv_xlim_loc_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            vconv_xlim_loc_out_blk_n <= vconv_xlim_loc_out_full_n;
+        else 
+            vconv_xlim_loc_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    vconv_xlim_loc_out_din <= vconv_xlim_loc_dout;
+
+    vconv_xlim_loc_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            vconv_xlim_loc_out_write <= ap_const_logic_1;
+        else 
+            vconv_xlim_loc_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    vconv_xlim_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            vconv_xlim_loc_read <= ap_const_logic_1;
+        else 
+            vconv_xlim_loc_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+end behav;

ip_repo_sources/neuron_packed/src/Loop_VConvH_proc_linebuf_0.vhd

@@ -0,0 +1,132 @@
+-- ==============================================================
+-- File generated on Wed Jun 26 16:53:30 CEST 2019
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
+-- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
+-- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity Loop_VConvH_proc_linebuf_0_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 10; 
+            MEM_SIZE    : integer := 672
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          q0        : out std_logic_vector(DWIDTH-1 downto 0);
+          addr1     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce1       : in std_logic; 
+          d1        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we1       : in std_logic; 
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of Loop_VConvH_proc_linebuf_0_ram is 
+
+signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array := (others=>(others=>'0'));
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+memory_access_guard_0: process (addr0) 
+begin
+      addr0_tmp <= addr0;
+--synthesis translate_off
+      if (CONV_INTEGER(addr0) > mem_size-1) then
+           addr0_tmp <= (others => '0');
+      else 
+           addr0_tmp <= addr0;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            q0 <= ram(CONV_INTEGER(addr0_tmp)); 
+        end if;
+    end if;
+end process;
+
+
+p_memory_access_1: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce1 = '1') then 
+            if (we1 = '1') then 
+                ram(CONV_INTEGER(addr1)) := d1; 
+            end if;
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity Loop_VConvH_proc_linebuf_0 is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 672;
+        AddressWidth : INTEGER := 10);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce1 : IN STD_LOGIC;
+        we1 : IN STD_LOGIC;
+        d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of Loop_VConvH_proc_linebuf_0 is
+    component Loop_VConvH_proc_linebuf_0_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            q0 : OUT STD_LOGIC_VECTOR;
+            addr1 : IN STD_LOGIC_VECTOR;
+            ce1 : IN STD_LOGIC;
+            we1 : IN STD_LOGIC;
+            d1 : IN STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    Loop_VConvH_proc_linebuf_0_ram_U :  component Loop_VConvH_proc_linebuf_0_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        q0 => q0,
+        addr1 => address1,
+        ce1 => ce1,
+        we1 => we1,
+        d1 => d1);
+
+end architecture;
+
+

ip_repo_sources/neuron_packed/src/checksum.vhd

@@ -0,0 +1,34 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_arith.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.myPackage.ALL;
+
+
+entity checksum is
+    generic(
+        busWidth : integer:=32);
+    Port ( clk : in STD_LOGIC;
+           reset : in STD_LOGIC;
+           enable : in STD_LOGIC;
+           dataIn : in std_logic_vector(busWidth-1 downto 0);
+           output : out std_logic_vector(busWidth-1 downto 0));
+end checksum;
+
+architecture Behavioral of checksum is
+    signal sum : unsigned(busWidth-1 downto 0);
+begin
+    main : process(clk, reset)
+        
+    begin
+        if(reset = '0') then
+            sum <= (others => '0');
+        elsif(rising_edge(clk)) then
+            if(enable = '1') then
+                sum <= sum + unsigned(dataIn);
+            end if;
+        end if;
+    end process;
+
+    output <= std_logic_vector(sum);
+end Behavioral;

ip_repo_sources/neuron_packed/src/dummyModule.vhd

@@ -0,0 +1,188 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 12.06.2019 22:30:43
+-- Design Name: 
+-- Module Name: dummyModule - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity dummyModule is
+    generic(
+        busWidth : integer:=32;
+        regDepth : integer:=4);
+    Port ( clk : in STD_LOGIC;
+           rst_n : in STD_LOGIC;
+           start : in STD_LOGIC;
+           ready: out std_logic;
+           idle : out std_logic;
+           done : out std_logic;
+           
+           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           srcValid : in std_logic;
+           srcReady : out std_logic;
+           
+           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           dstValid : out std_logic;
+           dstReady : in std_logic);
+end dummyModule;
+
+architecture Behavioral of dummyModule is
+
+    constant regWidth : integer:= regDepth * busWidth;
+
+    component shiftIn is
+        generic(
+            inWidth : integer := busWidth;
+            outWidth : integer := regWidth);
+        Port ( clk : in STD_LOGIC;
+               ce : in std_logic;
+               sync_reset : in STD_LOGIC;
+               dataIn : in std_logic_vector(inWidth-1 downto 0);
+               dataOut : out std_logic_vector(outWidth-1 downto 0);
+               finished : out STD_LOGIC);
+    end component;
+    component dummyModuleLogic is
+        generic(
+            regWidth : integer:=regWidth);
+        Port (
+            inputs : in std_logic_vector(regWidth-1 downto 0);
+            start : in std_logic;
+            finished : out std_logic;
+            clk : in std_logic;
+            outputs : out std_logic_vector(regWidth-1 downto 0));
+    end component;
+    component shiftOut is
+        generic(
+            inWidth : integer := regWidth;
+            outWidth : integer := busWidth);
+        Port ( clk : in STD_LOGIC;
+               ce : in std_logic;
+               sync_reset : in STD_LOGIC;
+               dataIn : in std_logic_vector(inWidth-1 downto 0);
+               dataOut : out std_logic_vector(outWidth-1 downto 0);
+               valid : out std_logic;
+               finished : out STD_LOGIC);
+    end component;
+    
+    signal dataInStorage : std_logic_vector(regWidth-1 downto 0);
+    signal dataOutStorage : std_logic_vector(regWidth-1 downto 0);
+    signal startShiftIn : std_logic;
+    signal shiftInFinished : std_logic;
+    signal calcFinished : std_logic;
+    signal shiftOutFinished : std_logic;
+    
+    type state_t is (waiting, srcShift, calc, dstShift);
+    signal state : state_t := waiting;
+
+begin
+    shiftIn2: shiftIn port map (
+        clk         => clk,
+        ce          => srcValid,
+        sync_reset  => startShiftIn,
+        dataIn      => srcData,
+        dataOut     => dataInStorage,
+        finished    => shiftInFinished
+    );
+    
+    dummyModuleLogic1: dummyModuleLogic port map (
+        inputs  => dataInStorage,
+        clk     => clk,
+        outputs => dataOutStorage,
+        start   => shiftInFinished,
+        finished=> calcFinished
+    );
+    
+    shiftOut2 : shiftOut port map (
+        clk         => clk,
+        ce      => dstReady,
+        sync_reset  => calcFinished,
+        dataIn      => dataOutStorage,
+        dataOut     => dstData,
+        finished    => shiftOutFinished,
+        valid       => dstValid
+    );
+    
+    fsm : process(clk, rst_n)
+    
+    begin
+        if rst_n = '0' then
+            state <= waiting;
+            ready <= '0';
+        elsif rising_edge(clk) then
+            startShiftIn <= '1';
+            idle <= '0';
+            ready <= '1';
+            case state is
+                when waiting =>
+                    if start='1' and shiftOutFinished = '0'  then
+                        state <= srcShift;
+                    else
+                        startShiftIn <= '0';
+                        idle <= '1';
+                    end if;
+                    
+                    
+                when srcShift =>
+                    
+                    if shiftInFinished = '1' then
+                        state <= calc;
+                    end if;
+                when calc =>
+                    if calcFinished='1' then
+                        state <= dstShift;
+                    end if;
+                when dstShift =>
+                    if shiftOutFinished='1' then
+                        state <= waiting;
+                    end if;
+            end case;
+        end if;
+    end process;
+    process(startShiftIn, shiftInFinished, shiftOutFinished, start) begin
+        srcReady <= startShiftIn and not shiftInFinished;
+        done <= start and shiftOutFinished;
+    end process;
+end Behavioral;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity dummyModuleLogic is
+    Generic (
+        regWidth : integer := 16
+    );
+    Port (
+        inputs : in std_logic_vector(regWidth-1 downto 0);
+        start : in std_logic;
+        finished : out std_logic;
+        clk : in std_logic;
+        outputs : out std_logic_vector(regWidth-1 downto 0));
+end dummyModuleLogic;
+
+architecture Behavioral of dummyModuleLogic is
+
+begin
+    process(clk)
+    begin
+        if(rising_edge(clk)) then
+            outputs <= inputs;
+            finished <= start;
+        end if;
+    end process;
+end Behavioral;

ip_repo_sources/neuron_packed/src/fifo_w32_d2_A.vhd

@@ -0,0 +1,140 @@
+-- ==============================================================
+-- File generated on Wed Jun 26 16:53:30 CEST 2019
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
+-- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
+-- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity fifo_w32_d2_A_shiftReg is
+    generic (
+        DATA_WIDTH : integer := 32;
+        ADDR_WIDTH : integer := 1;
+        DEPTH : integer := 2);
+    port (
+        clk : in std_logic;
+        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        ce : in std_logic;
+        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end fifo_w32_d2_A_shiftReg;
+
+architecture rtl of fifo_w32_d2_A_shiftReg is
+--constant DEPTH_WIDTH: integer := 16;
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+p_shift: process (clk)
+begin
+    if (clk'event and clk = '1') then
+        if (ce = '1') then
+            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
+        end if;
+    end if;
+end process;
+
+q <= SRL_SIG(conv_integer(a));
+
+end rtl;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+entity fifo_w32_d2_A is 
+    generic (
+        MEM_STYLE  : string := "shiftreg"; 
+        DATA_WIDTH : integer := 32;
+        ADDR_WIDTH : integer := 1;
+        DEPTH : integer := 2);
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        if_empty_n : OUT STD_LOGIC;
+        if_read_ce : IN STD_LOGIC;
+        if_read : IN STD_LOGIC;
+        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_full_n : OUT STD_LOGIC;
+        if_write_ce : IN STD_LOGIC;
+        if_write : IN STD_LOGIC;
+        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+end entity;
+
+architecture rtl of fifo_w32_d2_A is
+
+    component fifo_w32_d2_A_shiftReg is
+    generic (
+        DATA_WIDTH : integer := 32;
+        ADDR_WIDTH : integer := 1;
+        DEPTH : integer := 2);
+    port (
+        clk : in std_logic;
+        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        ce : in std_logic;
+        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
+    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+    signal shiftReg_ce : STD_LOGIC;
+    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
+    signal internal_empty_n : STD_LOGIC := '0';
+    signal internal_full_n  : STD_LOGIC := '1';
+
+begin
+    if_empty_n <= internal_empty_n;
+    if_full_n <= internal_full_n;
+    shiftReg_data <= if_din;
+    if_dout <= shiftReg_q;
+
+    process (clk)
+    begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '1');
+                internal_empty_n <= '0';
+                internal_full_n <= '1';
+            else
+                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
+                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
+                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2);
+                    if (mOutPtr = conv_std_logic_vector(0, 2)) then 
+                        internal_empty_n <= '0';
+                    end if;
+                    internal_full_n <= '1';
+                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
+                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
+                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2);
+                    internal_empty_n <= '1';
+                    if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then 
+                        internal_full_n <= '0';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
+    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
+
+    U_fifo_w32_d2_A_shiftReg : fifo_w32_d2_A_shiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => ADDR_WIDTH,
+        DEPTH => DEPTH)
+    port map (
+        clk => clk,
+        data => shiftReg_data,
+        ce => shiftReg_ce,
+        a => shiftReg_addr,
+        q => shiftReg_q);
+
+end rtl;
+

ip_repo_sources/neuron_packed/src/fifo_w32_d3_A.vhd

@@ -0,0 +1,140 @@
+-- ==============================================================
+-- File generated on Wed Jun 26 16:53:30 CEST 2019
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
+-- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
+-- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity fifo_w32_d3_A_shiftReg is
+    generic (
+        DATA_WIDTH : integer := 32;
+        ADDR_WIDTH : integer := 2;
+        DEPTH : integer := 3);
+    port (
+        clk : in std_logic;
+        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        ce : in std_logic;
+        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end fifo_w32_d3_A_shiftReg;
+
+architecture rtl of fifo_w32_d3_A_shiftReg is
+--constant DEPTH_WIDTH: integer := 16;
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+p_shift: process (clk)
+begin
+    if (clk'event and clk = '1') then
+        if (ce = '1') then
+            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
+        end if;
+    end if;
+end process;
+
+q <= SRL_SIG(conv_integer(a));
+
+end rtl;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+entity fifo_w32_d3_A is 
+    generic (
+        MEM_STYLE  : string := "shiftreg"; 
+        DATA_WIDTH : integer := 32;
+        ADDR_WIDTH : integer := 2;
+        DEPTH : integer := 3);
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        if_empty_n : OUT STD_LOGIC;
+        if_read_ce : IN STD_LOGIC;
+        if_read : IN STD_LOGIC;
+        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_full_n : OUT STD_LOGIC;
+        if_write_ce : IN STD_LOGIC;
+        if_write : IN STD_LOGIC;
+        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+end entity;
+
+architecture rtl of fifo_w32_d3_A is
+
+    component fifo_w32_d3_A_shiftReg is
+    generic (
+        DATA_WIDTH : integer := 32;
+        ADDR_WIDTH : integer := 2;
+        DEPTH : integer := 3);
+    port (
+        clk : in std_logic;
+        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        ce : in std_logic;
+        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
+    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+    signal shiftReg_ce : STD_LOGIC;
+    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
+    signal internal_empty_n : STD_LOGIC := '0';
+    signal internal_full_n  : STD_LOGIC := '1';
+
+begin
+    if_empty_n <= internal_empty_n;
+    if_full_n <= internal_full_n;
+    shiftReg_data <= if_din;
+    if_dout <= shiftReg_q;
+
+    process (clk)
+    begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '1');
+                internal_empty_n <= '0';
+                internal_full_n <= '1';
+            else
+                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
+                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
+                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
+                    if (mOutPtr = conv_std_logic_vector(0, 3)) then 
+                        internal_empty_n <= '0';
+                    end if;
+                    internal_full_n <= '1';
+                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
+                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
+                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
+                    internal_empty_n <= '1';
+                    if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then 
+                        internal_full_n <= '0';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
+    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
+
+    U_fifo_w32_d3_A_shiftReg : fifo_w32_d3_A_shiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => ADDR_WIDTH,
+        DEPTH => DEPTH)
+    port map (
+        clk => clk,
+        data => shiftReg_data,
+        ce => shiftReg_ce,
+        a => shiftReg_addr,
+        q => shiftReg_q);
+
+end rtl;
+

ip_repo_sources/neuron_packed/src/filter11x11_strm.vhd

@@ -0,0 +1,923 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+-- Version: 2018.3
+-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity filter11x11_strm is
+port (
+    width : IN STD_LOGIC_VECTOR (31 downto 0);
+    height : IN STD_LOGIC_VECTOR (31 downto 0);
+    filt1 : IN STD_LOGIC_VECTOR (31 downto 0);
+    filt2 : IN STD_LOGIC_VECTOR (31 downto 0);
+    src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+    dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+    ap_clk : IN STD_LOGIC;
+    ap_rst_n : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    src_V_TVALID : IN STD_LOGIC;
+    src_V_TREADY : OUT STD_LOGIC;
+    dst_V_TVALID : OUT STD_LOGIC;
+    dst_V_TREADY : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    ap_idle : OUT STD_LOGIC );
+end;
+
+
+architecture behav of filter11x11_strm is 
+    attribute CORE_GENERATION_INFO : STRING;
+    attribute CORE_GENERATION_INFO of behav : architecture is
+    "filter11x11_strm,hls_ip_2018_3,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7a100tcsg324-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.470000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=22,HLS_SYN_DSP=28,HLS_SYN_FF=3339,HLS_SYN_LUT=3643,HLS_VERSION=2018_3}";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+
+    signal ap_rst_n_inv : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_ap_start : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_start_full_n : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_ap_done : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_ap_continue : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_ap_idle : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_ap_ready : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_start_out : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_start_write : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_width_out_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal filter11x11_strm_ent_U0_width_out_write : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_width_out1_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal filter11x11_strm_ent_U0_width_out1_write : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_height_out_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal filter11x11_strm_ent_U0_height_out_write : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_height_out2_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal filter11x11_strm_ent_U0_height_out2_write : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_filt1_out_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal filter11x11_strm_ent_U0_filt1_out_write : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_filt1_out3_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal filter11x11_strm_ent_U0_filt1_out3_write : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_filt2_out_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal filter11x11_strm_ent_U0_filt2_out_write : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_filt2_out4_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal filter11x11_strm_ent_U0_filt2_out4_write : STD_LOGIC;
+    signal Block_proc_U0_ap_start : STD_LOGIC;
+    signal Block_proc_U0_ap_done : STD_LOGIC;
+    signal Block_proc_U0_ap_continue : STD_LOGIC;
+    signal Block_proc_U0_ap_idle : STD_LOGIC;
+    signal Block_proc_U0_ap_ready : STD_LOGIC;
+    signal Block_proc_U0_start_out : STD_LOGIC;
+    signal Block_proc_U0_start_write : STD_LOGIC;
+    signal Block_proc_U0_width_read : STD_LOGIC;
+    signal Block_proc_U0_height_read : STD_LOGIC;
+    signal Block_proc_U0_width_out_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal Block_proc_U0_width_out_write : STD_LOGIC;
+    signal Block_proc_U0_height_out_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal Block_proc_U0_height_out_write : STD_LOGIC;
+    signal Block_proc_U0_vconv_xlim_out_out_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal Block_proc_U0_vconv_xlim_out_out_write : STD_LOGIC;
+    signal Loop_HConvH_proc6_U0_ap_start : STD_LOGIC;
+    signal Loop_HConvH_proc6_U0_ap_done : STD_LOGIC;
+    signal Loop_HConvH_proc6_U0_ap_continue : STD_LOGIC;
+    signal Loop_HConvH_proc6_U0_ap_idle : STD_LOGIC;
+    signal Loop_HConvH_proc6_U0_ap_ready : STD_LOGIC;
+    signal Loop_HConvH_proc6_U0_height_read : STD_LOGIC;
+    signal Loop_HConvH_proc6_U0_width_read : STD_LOGIC;
+    signal Loop_HConvH_proc6_U0_src_V_TREADY : STD_LOGIC;
+    signal Loop_HConvH_proc6_U0_filt1_read : STD_LOGIC;
+    signal Loop_HConvH_proc6_U0_filt2_read : STD_LOGIC;
+    signal Loop_HConvH_proc6_U0_hconv_V_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal Loop_HConvH_proc6_U0_hconv_V_write : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_ap_start : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_ap_done : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_ap_continue : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_ap_idle : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_ap_ready : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_height_read : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_vconv_xlim_loc_read : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_hconv_V_read : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_vconv_V_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal Loop_VConvH_proc_U0_vconv_V_write : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_filt1_read : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_filt2_read : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_height_out_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal Loop_VConvH_proc_U0_height_out_write : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_vconv_xlim_loc_out_din : STD_LOGIC_VECTOR (31 downto 0);
+    signal Loop_VConvH_proc_U0_vconv_xlim_loc_out_write : STD_LOGIC;
+    signal Loop_Border_proc_U0_ap_start : STD_LOGIC;
+    signal Loop_Border_proc_U0_ap_done : STD_LOGIC;
+    signal Loop_Border_proc_U0_ap_continue : STD_LOGIC;
+    signal Loop_Border_proc_U0_ap_idle : STD_LOGIC;
+    signal Loop_Border_proc_U0_ap_ready : STD_LOGIC;
+    signal Loop_Border_proc_U0_width_read : STD_LOGIC;
+    signal Loop_Border_proc_U0_height_read : STD_LOGIC;
+    signal Loop_Border_proc_U0_dst_V_TDATA : STD_LOGIC_VECTOR (31 downto 0);
+    signal Loop_Border_proc_U0_dst_V_TVALID : STD_LOGIC;
+    signal Loop_Border_proc_U0_vconv_xlim_loc_read : STD_LOGIC;
+    signal Loop_Border_proc_U0_vconv_V_read : STD_LOGIC;
+    signal ap_sync_continue : STD_LOGIC;
+    signal width_c_full_n : STD_LOGIC;
+    signal width_c_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal width_c_empty_n : STD_LOGIC;
+    signal width_c155_full_n : STD_LOGIC;
+    signal width_c155_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal width_c155_empty_n : STD_LOGIC;
+    signal height_c_full_n : STD_LOGIC;
+    signal height_c_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal height_c_empty_n : STD_LOGIC;
+    signal height_c156_full_n : STD_LOGIC;
+    signal height_c156_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal height_c156_empty_n : STD_LOGIC;
+    signal filt1_c_full_n : STD_LOGIC;
+    signal filt1_c_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal filt1_c_empty_n : STD_LOGIC;
+    signal filt1_c157_full_n : STD_LOGIC;
+    signal filt1_c157_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal filt1_c157_empty_n : STD_LOGIC;
+    signal filt2_c_full_n : STD_LOGIC;
+    signal filt2_c_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal filt2_c_empty_n : STD_LOGIC;
+    signal filt2_c158_full_n : STD_LOGIC;
+    signal filt2_c158_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal filt2_c158_empty_n : STD_LOGIC;
+    signal width_c159_full_n : STD_LOGIC;
+    signal width_c159_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal width_c159_empty_n : STD_LOGIC;
+    signal height_c160_full_n : STD_LOGIC;
+    signal height_c160_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal height_c160_empty_n : STD_LOGIC;
+    signal vconv_xlim_loc_c_full_n : STD_LOGIC;
+    signal vconv_xlim_loc_c_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal vconv_xlim_loc_c_empty_n : STD_LOGIC;
+    signal hconv_V_full_n : STD_LOGIC;
+    signal hconv_V_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal hconv_V_empty_n : STD_LOGIC;
+    signal vconv_V_full_n : STD_LOGIC;
+    signal vconv_V_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal vconv_V_empty_n : STD_LOGIC;
+    signal height_c161_full_n : STD_LOGIC;
+    signal height_c161_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal height_c161_empty_n : STD_LOGIC;
+    signal vconv_xlim_loc_c162_full_n : STD_LOGIC;
+    signal vconv_xlim_loc_c162_dout : STD_LOGIC_VECTOR (31 downto 0);
+    signal vconv_xlim_loc_c162_empty_n : STD_LOGIC;
+    signal ap_sync_done : STD_LOGIC;
+    signal ap_sync_ready : STD_LOGIC;
+    signal ap_sync_reg_filter11x11_strm_ent_U0_ap_ready : STD_LOGIC := '0';
+    signal ap_sync_filter11x11_strm_ent_U0_ap_ready : STD_LOGIC;
+    signal filter11x11_strm_ent_U0_ap_ready_count : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    signal ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready : STD_LOGIC := '0';
+    signal ap_sync_Loop_HConvH_proc6_U0_ap_ready : STD_LOGIC;
+    signal Loop_HConvH_proc6_U0_ap_ready_count : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    signal start_for_Block_proc_U0_din : STD_LOGIC_VECTOR (0 downto 0);
+    signal start_for_Block_proc_U0_full_n : STD_LOGIC;
+    signal start_for_Block_proc_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
+    signal start_for_Block_proc_U0_empty_n : STD_LOGIC;
+    signal start_for_Loop_VConvH_proc_U0_din : STD_LOGIC_VECTOR (0 downto 0);
+    signal start_for_Loop_VConvH_proc_U0_full_n : STD_LOGIC;
+    signal start_for_Loop_VConvH_proc_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
+    signal start_for_Loop_VConvH_proc_U0_empty_n : STD_LOGIC;
+    signal start_for_Loop_Border_proc_U0_din : STD_LOGIC_VECTOR (0 downto 0);
+    signal start_for_Loop_Border_proc_U0_full_n : STD_LOGIC;
+    signal start_for_Loop_Border_proc_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
+    signal start_for_Loop_Border_proc_U0_empty_n : STD_LOGIC;
+    signal Loop_HConvH_proc6_U0_start_full_n : STD_LOGIC;
+    signal Loop_HConvH_proc6_U0_start_write : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_start_full_n : STD_LOGIC;
+    signal Loop_VConvH_proc_U0_start_write : STD_LOGIC;
+    signal Loop_Border_proc_U0_start_full_n : STD_LOGIC;
+    signal Loop_Border_proc_U0_start_write : STD_LOGIC;
+
+    component filter11x11_strm_ent IS
+    port (
+        ap_clk : IN STD_LOGIC;
+        ap_rst : IN STD_LOGIC;
+        ap_start : IN STD_LOGIC;
+        start_full_n : IN STD_LOGIC;
+        ap_done : OUT STD_LOGIC;
+        ap_continue : IN STD_LOGIC;
+        ap_idle : OUT STD_LOGIC;
+        ap_ready : OUT STD_LOGIC;
+        start_out : OUT STD_LOGIC;
+        start_write : OUT STD_LOGIC;
+        width : IN STD_LOGIC_VECTOR (31 downto 0);
+        height : IN STD_LOGIC_VECTOR (31 downto 0);
+        filt1 : IN STD_LOGIC_VECTOR (31 downto 0);
+        filt2 : IN STD_LOGIC_VECTOR (31 downto 0);
+        width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        width_out_full_n : IN STD_LOGIC;
+        width_out_write : OUT STD_LOGIC;
+        width_out1_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        width_out1_full_n : IN STD_LOGIC;
+        width_out1_write : OUT STD_LOGIC;
+        height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        height_out_full_n : IN STD_LOGIC;
+        height_out_write : OUT STD_LOGIC;
+        height_out2_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        height_out2_full_n : IN STD_LOGIC;
+        height_out2_write : OUT STD_LOGIC;
+        filt1_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        filt1_out_full_n : IN STD_LOGIC;
+        filt1_out_write : OUT STD_LOGIC;
+        filt1_out3_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        filt1_out3_full_n : IN STD_LOGIC;
+        filt1_out3_write : OUT STD_LOGIC;
+        filt2_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        filt2_out_full_n : IN STD_LOGIC;
+        filt2_out_write : OUT STD_LOGIC;
+        filt2_out4_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        filt2_out4_full_n : IN STD_LOGIC;
+        filt2_out4_write : OUT STD_LOGIC );
+    end component;
+
+
+    component Block_proc IS
+    port (
+        ap_clk : IN STD_LOGIC;
+        ap_rst : IN STD_LOGIC;
+        ap_start : IN STD_LOGIC;
+        start_full_n : IN STD_LOGIC;
+        ap_done : OUT STD_LOGIC;
+        ap_continue : IN STD_LOGIC;
+        ap_idle : OUT STD_LOGIC;
+        ap_ready : OUT STD_LOGIC;
+        start_out : OUT STD_LOGIC;
+        start_write : OUT STD_LOGIC;
+        width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        width_empty_n : IN STD_LOGIC;
+        width_read : OUT STD_LOGIC;
+        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        height_empty_n : IN STD_LOGIC;
+        height_read : OUT STD_LOGIC;
+        width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        width_out_full_n : IN STD_LOGIC;
+        width_out_write : OUT STD_LOGIC;
+        height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        height_out_full_n : IN STD_LOGIC;
+        height_out_write : OUT STD_LOGIC;
+        vconv_xlim_out_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        vconv_xlim_out_out_full_n : IN STD_LOGIC;
+        vconv_xlim_out_out_write : OUT STD_LOGIC );
+    end component;
+
+
+    component Loop_HConvH_proc6 IS
+    port (
+        ap_clk : IN STD_LOGIC;
+        ap_rst : IN STD_LOGIC;
+        ap_start : IN STD_LOGIC;
+        ap_done : OUT STD_LOGIC;
+        ap_continue : IN STD_LOGIC;
+        ap_idle : OUT STD_LOGIC;
+        ap_ready : OUT STD_LOGIC;
+        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        height_empty_n : IN STD_LOGIC;
+        height_read : OUT STD_LOGIC;
+        width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        width_empty_n : IN STD_LOGIC;
+        width_read : OUT STD_LOGIC;
+        src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+        src_V_TVALID : IN STD_LOGIC;
+        src_V_TREADY : OUT STD_LOGIC;
+        filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        filt1_empty_n : IN STD_LOGIC;
+        filt1_read : OUT STD_LOGIC;
+        filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        filt2_empty_n : IN STD_LOGIC;
+        filt2_read : OUT STD_LOGIC;
+        hconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        hconv_V_full_n : IN STD_LOGIC;
+        hconv_V_write : OUT STD_LOGIC );
+    end component;
+
+
+    component Loop_VConvH_proc IS
+    port (
+        ap_clk : IN STD_LOGIC;
+        ap_rst : IN STD_LOGIC;
+        ap_start : IN STD_LOGIC;
+        ap_done : OUT STD_LOGIC;
+        ap_continue : IN STD_LOGIC;
+        ap_idle : OUT STD_LOGIC;
+        ap_ready : OUT STD_LOGIC;
+        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        height_empty_n : IN STD_LOGIC;
+        height_read : OUT STD_LOGIC;
+        vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        vconv_xlim_loc_empty_n : IN STD_LOGIC;
+        vconv_xlim_loc_read : OUT STD_LOGIC;
+        hconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        hconv_V_empty_n : IN STD_LOGIC;
+        hconv_V_read : OUT STD_LOGIC;
+        vconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        vconv_V_full_n : IN STD_LOGIC;
+        vconv_V_write : OUT STD_LOGIC;
+        filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        filt1_empty_n : IN STD_LOGIC;
+        filt1_read : OUT STD_LOGIC;
+        filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        filt2_empty_n : IN STD_LOGIC;
+        filt2_read : OUT STD_LOGIC;
+        height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        height_out_full_n : IN STD_LOGIC;
+        height_out_write : OUT STD_LOGIC;
+        vconv_xlim_loc_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+        vconv_xlim_loc_out_full_n : IN STD_LOGIC;
+        vconv_xlim_loc_out_write : OUT STD_LOGIC );
+    end component;
+
+
+    component Loop_Border_proc IS
+    port (
+        ap_clk : IN STD_LOGIC;
+        ap_rst : IN STD_LOGIC;
+        ap_start : IN STD_LOGIC;
+        ap_done : OUT STD_LOGIC;
+        ap_continue : IN STD_LOGIC;
+        ap_idle : OUT STD_LOGIC;
+        ap_ready : OUT STD_LOGIC;
+        width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        width_empty_n : IN STD_LOGIC;
+        width_read : OUT STD_LOGIC;
+        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        height_empty_n : IN STD_LOGIC;
+        height_read : OUT STD_LOGIC;
+        dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+        dst_V_TVALID : OUT STD_LOGIC;
+        dst_V_TREADY : IN STD_LOGIC;
+        vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        vconv_xlim_loc_empty_n : IN STD_LOGIC;
+        vconv_xlim_loc_read : OUT STD_LOGIC;
+        vconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+        vconv_V_empty_n : IN STD_LOGIC;
+        vconv_V_read : OUT STD_LOGIC );
+    end component;
+
+
+    component fifo_w32_d2_A IS
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        if_read_ce : IN STD_LOGIC;
+        if_write_ce : IN STD_LOGIC;
+        if_din : IN STD_LOGIC_VECTOR (31 downto 0);
+        if_full_n : OUT STD_LOGIC;
+        if_write : IN STD_LOGIC;
+        if_dout : OUT STD_LOGIC_VECTOR (31 downto 0);
+        if_empty_n : OUT STD_LOGIC;
+        if_read : IN STD_LOGIC );
+    end component;
+
+
+    component fifo_w32_d3_A IS
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        if_read_ce : IN STD_LOGIC;
+        if_write_ce : IN STD_LOGIC;
+        if_din : IN STD_LOGIC_VECTOR (31 downto 0);
+        if_full_n : OUT STD_LOGIC;
+        if_write : IN STD_LOGIC;
+        if_dout : OUT STD_LOGIC_VECTOR (31 downto 0);
+        if_empty_n : OUT STD_LOGIC;
+        if_read : IN STD_LOGIC );
+    end component;
+
+
+    component start_for_Block_proc_U0 IS
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        if_read_ce : IN STD_LOGIC;
+        if_write_ce : IN STD_LOGIC;
+        if_din : IN STD_LOGIC_VECTOR (0 downto 0);
+        if_full_n : OUT STD_LOGIC;
+        if_write : IN STD_LOGIC;
+        if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
+        if_empty_n : OUT STD_LOGIC;
+        if_read : IN STD_LOGIC );
+    end component;
+
+
+    component start_for_Loop_VConvH_proc_U0 IS
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        if_read_ce : IN STD_LOGIC;
+        if_write_ce : IN STD_LOGIC;
+        if_din : IN STD_LOGIC_VECTOR (0 downto 0);
+        if_full_n : OUT STD_LOGIC;
+        if_write : IN STD_LOGIC;
+        if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
+        if_empty_n : OUT STD_LOGIC;
+        if_read : IN STD_LOGIC );
+    end component;
+
+
+    component start_for_Loop_Border_proc_U0 IS
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        if_read_ce : IN STD_LOGIC;
+        if_write_ce : IN STD_LOGIC;
+        if_din : IN STD_LOGIC_VECTOR (0 downto 0);
+        if_full_n : OUT STD_LOGIC;
+        if_write : IN STD_LOGIC;
+        if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
+        if_empty_n : OUT STD_LOGIC;
+        if_read : IN STD_LOGIC );
+    end component;
+
+
+
+begin
+    filter11x11_strm_ent_U0 : component filter11x11_strm_ent
+    port map (
+        ap_clk => ap_clk,
+        ap_rst => ap_rst_n_inv,
+        ap_start => filter11x11_strm_ent_U0_ap_start,
+        start_full_n => filter11x11_strm_ent_U0_start_full_n,
+        ap_done => filter11x11_strm_ent_U0_ap_done,
+        ap_continue => filter11x11_strm_ent_U0_ap_continue,
+        ap_idle => filter11x11_strm_ent_U0_ap_idle,
+        ap_ready => filter11x11_strm_ent_U0_ap_ready,
+        start_out => filter11x11_strm_ent_U0_start_out,
+        start_write => filter11x11_strm_ent_U0_start_write,
+        width => width,
+        height => height,
+        filt1 => filt1,
+        filt2 => filt2,
+        width_out_din => filter11x11_strm_ent_U0_width_out_din,
+        width_out_full_n => width_c_full_n,
+        width_out_write => filter11x11_strm_ent_U0_width_out_write,
+        width_out1_din => filter11x11_strm_ent_U0_width_out1_din,
+        width_out1_full_n => width_c155_full_n,
+        width_out1_write => filter11x11_strm_ent_U0_width_out1_write,
+        height_out_din => filter11x11_strm_ent_U0_height_out_din,
+        height_out_full_n => height_c_full_n,
+        height_out_write => filter11x11_strm_ent_U0_height_out_write,
+        height_out2_din => filter11x11_strm_ent_U0_height_out2_din,
+        height_out2_full_n => height_c156_full_n,
+        height_out2_write => filter11x11_strm_ent_U0_height_out2_write,
+        filt1_out_din => filter11x11_strm_ent_U0_filt1_out_din,
+        filt1_out_full_n => filt1_c_full_n,
+        filt1_out_write => filter11x11_strm_ent_U0_filt1_out_write,
+        filt1_out3_din => filter11x11_strm_ent_U0_filt1_out3_din,
+        filt1_out3_full_n => filt1_c157_full_n,
+        filt1_out3_write => filter11x11_strm_ent_U0_filt1_out3_write,
+        filt2_out_din => filter11x11_strm_ent_U0_filt2_out_din,
+        filt2_out_full_n => filt2_c_full_n,
+        filt2_out_write => filter11x11_strm_ent_U0_filt2_out_write,
+        filt2_out4_din => filter11x11_strm_ent_U0_filt2_out4_din,
+        filt2_out4_full_n => filt2_c158_full_n,
+        filt2_out4_write => filter11x11_strm_ent_U0_filt2_out4_write);
+
+    Block_proc_U0 : component Block_proc
+    port map (
+        ap_clk => ap_clk,
+        ap_rst => ap_rst_n_inv,
+        ap_start => Block_proc_U0_ap_start,
+        start_full_n => start_for_Loop_Border_proc_U0_full_n,
+        ap_done => Block_proc_U0_ap_done,
+        ap_continue => Block_proc_U0_ap_continue,
+        ap_idle => Block_proc_U0_ap_idle,
+        ap_ready => Block_proc_U0_ap_ready,
+        start_out => Block_proc_U0_start_out,
+        start_write => Block_proc_U0_start_write,
+        width_dout => width_c_dout,
+        width_empty_n => width_c_empty_n,
+        width_read => Block_proc_U0_width_read,
+        height_dout => height_c_dout,
+        height_empty_n => height_c_empty_n,
+        height_read => Block_proc_U0_height_read,
+        width_out_din => Block_proc_U0_width_out_din,
+        width_out_full_n => width_c159_full_n,
+        width_out_write => Block_proc_U0_width_out_write,
+        height_out_din => Block_proc_U0_height_out_din,
+        height_out_full_n => height_c160_full_n,
+        height_out_write => Block_proc_U0_height_out_write,
+        vconv_xlim_out_out_din => Block_proc_U0_vconv_xlim_out_out_din,
+        vconv_xlim_out_out_full_n => vconv_xlim_loc_c_full_n,
+        vconv_xlim_out_out_write => Block_proc_U0_vconv_xlim_out_out_write);
+
+    Loop_HConvH_proc6_U0 : component Loop_HConvH_proc6
+    port map (
+        ap_clk => ap_clk,
+        ap_rst => ap_rst_n_inv,
+        ap_start => Loop_HConvH_proc6_U0_ap_start,
+        ap_done => Loop_HConvH_proc6_U0_ap_done,
+        ap_continue => Loop_HConvH_proc6_U0_ap_continue,
+        ap_idle => Loop_HConvH_proc6_U0_ap_idle,
+        ap_ready => Loop_HConvH_proc6_U0_ap_ready,
+        height_dout => height_c156_dout,
+        height_empty_n => height_c156_empty_n,
+        height_read => Loop_HConvH_proc6_U0_height_read,
+        width_dout => width_c155_dout,
+        width_empty_n => width_c155_empty_n,
+        width_read => Loop_HConvH_proc6_U0_width_read,
+        src_V_TDATA => src_V_TDATA,
+        src_V_TVALID => src_V_TVALID,
+        src_V_TREADY => Loop_HConvH_proc6_U0_src_V_TREADY,
+        filt1_dout => filt1_c_dout,
+        filt1_empty_n => filt1_c_empty_n,
+        filt1_read => Loop_HConvH_proc6_U0_filt1_read,
+        filt2_dout => filt2_c_dout,
+        filt2_empty_n => filt2_c_empty_n,
+        filt2_read => Loop_HConvH_proc6_U0_filt2_read,
+        hconv_V_din => Loop_HConvH_proc6_U0_hconv_V_din,
+        hconv_V_full_n => hconv_V_full_n,
+        hconv_V_write => Loop_HConvH_proc6_U0_hconv_V_write);
+
+    Loop_VConvH_proc_U0 : component Loop_VConvH_proc
+    port map (
+        ap_clk => ap_clk,
+        ap_rst => ap_rst_n_inv,
+        ap_start => Loop_VConvH_proc_U0_ap_start,
+        ap_done => Loop_VConvH_proc_U0_ap_done,
+        ap_continue => Loop_VConvH_proc_U0_ap_continue,
+        ap_idle => Loop_VConvH_proc_U0_ap_idle,
+        ap_ready => Loop_VConvH_proc_U0_ap_ready,
+        height_dout => height_c160_dout,
+        height_empty_n => height_c160_empty_n,
+        height_read => Loop_VConvH_proc_U0_height_read,
+        vconv_xlim_loc_dout => vconv_xlim_loc_c_dout,
+        vconv_xlim_loc_empty_n => vconv_xlim_loc_c_empty_n,
+        vconv_xlim_loc_read => Loop_VConvH_proc_U0_vconv_xlim_loc_read,
+        hconv_V_dout => hconv_V_dout,
+        hconv_V_empty_n => hconv_V_empty_n,
+        hconv_V_read => Loop_VConvH_proc_U0_hconv_V_read,
+        vconv_V_din => Loop_VConvH_proc_U0_vconv_V_din,
+        vconv_V_full_n => vconv_V_full_n,
+        vconv_V_write => Loop_VConvH_proc_U0_vconv_V_write,
+        filt1_dout => filt1_c157_dout,
+        filt1_empty_n => filt1_c157_empty_n,
+        filt1_read => Loop_VConvH_proc_U0_filt1_read,
+        filt2_dout => filt2_c158_dout,
+        filt2_empty_n => filt2_c158_empty_n,
+        filt2_read => Loop_VConvH_proc_U0_filt2_read,
+        height_out_din => Loop_VConvH_proc_U0_height_out_din,
+        height_out_full_n => height_c161_full_n,
+        height_out_write => Loop_VConvH_proc_U0_height_out_write,
+        vconv_xlim_loc_out_din => Loop_VConvH_proc_U0_vconv_xlim_loc_out_din,
+        vconv_xlim_loc_out_full_n => vconv_xlim_loc_c162_full_n,
+        vconv_xlim_loc_out_write => Loop_VConvH_proc_U0_vconv_xlim_loc_out_write);
+
+    Loop_Border_proc_U0 : component Loop_Border_proc
+    port map (
+        ap_clk => ap_clk,
+        ap_rst => ap_rst_n_inv,
+        ap_start => Loop_Border_proc_U0_ap_start,
+        ap_done => Loop_Border_proc_U0_ap_done,
+        ap_continue => Loop_Border_proc_U0_ap_continue,
+        ap_idle => Loop_Border_proc_U0_ap_idle,
+        ap_ready => Loop_Border_proc_U0_ap_ready,
+        width_dout => width_c159_dout,
+        width_empty_n => width_c159_empty_n,
+        width_read => Loop_Border_proc_U0_width_read,
+        height_dout => height_c161_dout,
+        height_empty_n => height_c161_empty_n,
+        height_read => Loop_Border_proc_U0_height_read,
+        dst_V_TDATA => Loop_Border_proc_U0_dst_V_TDATA,
+        dst_V_TVALID => Loop_Border_proc_U0_dst_V_TVALID,
+        dst_V_TREADY => dst_V_TREADY,
+        vconv_xlim_loc_dout => vconv_xlim_loc_c162_dout,
+        vconv_xlim_loc_empty_n => vconv_xlim_loc_c162_empty_n,
+        vconv_xlim_loc_read => Loop_Border_proc_U0_vconv_xlim_loc_read,
+        vconv_V_dout => vconv_V_dout,
+        vconv_V_empty_n => vconv_V_empty_n,
+        vconv_V_read => Loop_Border_proc_U0_vconv_V_read);
+
+    width_c_U : component fifo_w32_d2_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => filter11x11_strm_ent_U0_width_out_din,
+        if_full_n => width_c_full_n,
+        if_write => filter11x11_strm_ent_U0_width_out_write,
+        if_dout => width_c_dout,
+        if_empty_n => width_c_empty_n,
+        if_read => Block_proc_U0_width_read);
+
+    width_c155_U : component fifo_w32_d2_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => filter11x11_strm_ent_U0_width_out1_din,
+        if_full_n => width_c155_full_n,
+        if_write => filter11x11_strm_ent_U0_width_out1_write,
+        if_dout => width_c155_dout,
+        if_empty_n => width_c155_empty_n,
+        if_read => Loop_HConvH_proc6_U0_width_read);
+
+    height_c_U : component fifo_w32_d2_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => filter11x11_strm_ent_U0_height_out_din,
+        if_full_n => height_c_full_n,
+        if_write => filter11x11_strm_ent_U0_height_out_write,
+        if_dout => height_c_dout,
+        if_empty_n => height_c_empty_n,
+        if_read => Block_proc_U0_height_read);
+
+    height_c156_U : component fifo_w32_d2_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => filter11x11_strm_ent_U0_height_out2_din,
+        if_full_n => height_c156_full_n,
+        if_write => filter11x11_strm_ent_U0_height_out2_write,
+        if_dout => height_c156_dout,
+        if_empty_n => height_c156_empty_n,
+        if_read => Loop_HConvH_proc6_U0_height_read);
+
+    filt1_c_U : component fifo_w32_d2_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => filter11x11_strm_ent_U0_filt1_out_din,
+        if_full_n => filt1_c_full_n,
+        if_write => filter11x11_strm_ent_U0_filt1_out_write,
+        if_dout => filt1_c_dout,
+        if_empty_n => filt1_c_empty_n,
+        if_read => Loop_HConvH_proc6_U0_filt1_read);
+
+    filt1_c157_U : component fifo_w32_d3_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => filter11x11_strm_ent_U0_filt1_out3_din,
+        if_full_n => filt1_c157_full_n,
+        if_write => filter11x11_strm_ent_U0_filt1_out3_write,
+        if_dout => filt1_c157_dout,
+        if_empty_n => filt1_c157_empty_n,
+        if_read => Loop_VConvH_proc_U0_filt1_read);
+
+    filt2_c_U : component fifo_w32_d2_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => filter11x11_strm_ent_U0_filt2_out_din,
+        if_full_n => filt2_c_full_n,
+        if_write => filter11x11_strm_ent_U0_filt2_out_write,
+        if_dout => filt2_c_dout,
+        if_empty_n => filt2_c_empty_n,
+        if_read => Loop_HConvH_proc6_U0_filt2_read);
+
+    filt2_c158_U : component fifo_w32_d3_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => filter11x11_strm_ent_U0_filt2_out4_din,
+        if_full_n => filt2_c158_full_n,
+        if_write => filter11x11_strm_ent_U0_filt2_out4_write,
+        if_dout => filt2_c158_dout,
+        if_empty_n => filt2_c158_empty_n,
+        if_read => Loop_VConvH_proc_U0_filt2_read);
+
+    width_c159_U : component fifo_w32_d3_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => Block_proc_U0_width_out_din,
+        if_full_n => width_c159_full_n,
+        if_write => Block_proc_U0_width_out_write,
+        if_dout => width_c159_dout,
+        if_empty_n => width_c159_empty_n,
+        if_read => Loop_Border_proc_U0_width_read);
+
+    height_c160_U : component fifo_w32_d2_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => Block_proc_U0_height_out_din,
+        if_full_n => height_c160_full_n,
+        if_write => Block_proc_U0_height_out_write,
+        if_dout => height_c160_dout,
+        if_empty_n => height_c160_empty_n,
+        if_read => Loop_VConvH_proc_U0_height_read);
+
+    vconv_xlim_loc_c_U : component fifo_w32_d2_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => Block_proc_U0_vconv_xlim_out_out_din,
+        if_full_n => vconv_xlim_loc_c_full_n,
+        if_write => Block_proc_U0_vconv_xlim_out_out_write,
+        if_dout => vconv_xlim_loc_c_dout,
+        if_empty_n => vconv_xlim_loc_c_empty_n,
+        if_read => Loop_VConvH_proc_U0_vconv_xlim_loc_read);
+
+    hconv_V_U : component fifo_w32_d2_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => Loop_HConvH_proc6_U0_hconv_V_din,
+        if_full_n => hconv_V_full_n,
+        if_write => Loop_HConvH_proc6_U0_hconv_V_write,
+        if_dout => hconv_V_dout,
+        if_empty_n => hconv_V_empty_n,
+        if_read => Loop_VConvH_proc_U0_hconv_V_read);
+
+    vconv_V_U : component fifo_w32_d2_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => Loop_VConvH_proc_U0_vconv_V_din,
+        if_full_n => vconv_V_full_n,
+        if_write => Loop_VConvH_proc_U0_vconv_V_write,
+        if_dout => vconv_V_dout,
+        if_empty_n => vconv_V_empty_n,
+        if_read => Loop_Border_proc_U0_vconv_V_read);
+
+    height_c161_U : component fifo_w32_d2_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => Loop_VConvH_proc_U0_height_out_din,
+        if_full_n => height_c161_full_n,
+        if_write => Loop_VConvH_proc_U0_height_out_write,
+        if_dout => height_c161_dout,
+        if_empty_n => height_c161_empty_n,
+        if_read => Loop_Border_proc_U0_height_read);
+
+    vconv_xlim_loc_c162_U : component fifo_w32_d2_A
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => Loop_VConvH_proc_U0_vconv_xlim_loc_out_din,
+        if_full_n => vconv_xlim_loc_c162_full_n,
+        if_write => Loop_VConvH_proc_U0_vconv_xlim_loc_out_write,
+        if_dout => vconv_xlim_loc_c162_dout,
+        if_empty_n => vconv_xlim_loc_c162_empty_n,
+        if_read => Loop_Border_proc_U0_vconv_xlim_loc_read);
+
+    start_for_Block_proc_U0_U : component start_for_Block_proc_U0
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => start_for_Block_proc_U0_din,
+        if_full_n => start_for_Block_proc_U0_full_n,
+        if_write => filter11x11_strm_ent_U0_start_write,
+        if_dout => start_for_Block_proc_U0_dout,
+        if_empty_n => start_for_Block_proc_U0_empty_n,
+        if_read => Block_proc_U0_ap_ready);
+
+    start_for_Loop_VConvH_proc_U0_U : component start_for_Loop_VConvH_proc_U0
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => start_for_Loop_VConvH_proc_U0_din,
+        if_full_n => start_for_Loop_VConvH_proc_U0_full_n,
+        if_write => filter11x11_strm_ent_U0_start_write,
+        if_dout => start_for_Loop_VConvH_proc_U0_dout,
+        if_empty_n => start_for_Loop_VConvH_proc_U0_empty_n,
+        if_read => Loop_VConvH_proc_U0_ap_ready);
+
+    start_for_Loop_Border_proc_U0_U : component start_for_Loop_Border_proc_U0
+    port map (
+        clk => ap_clk,
+        reset => ap_rst_n_inv,
+        if_read_ce => ap_const_logic_1,
+        if_write_ce => ap_const_logic_1,
+        if_din => start_for_Loop_Border_proc_U0_din,
+        if_full_n => start_for_Loop_Border_proc_U0_full_n,
+        if_write => Block_proc_U0_start_write,
+        if_dout => start_for_Loop_Border_proc_U0_dout,
+        if_empty_n => start_for_Loop_Border_proc_U0_empty_n,
+        if_read => Loop_Border_proc_U0_ap_ready);
+
+
+
+
+
+    ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready <= ap_const_logic_0;
+            else
+                if (((ap_sync_ready and ap_start) = ap_const_logic_1)) then 
+                    ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready <= ap_const_logic_0;
+                else 
+                    ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready <= ap_sync_Loop_HConvH_proc6_U0_ap_ready;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_sync_reg_filter11x11_strm_ent_U0_ap_ready_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst_n_inv = '1') then
+                ap_sync_reg_filter11x11_strm_ent_U0_ap_ready <= ap_const_logic_0;
+            else
+                if (((ap_sync_ready and ap_start) = ap_const_logic_1)) then 
+                    ap_sync_reg_filter11x11_strm_ent_U0_ap_ready <= ap_const_logic_0;
+                else 
+                    ap_sync_reg_filter11x11_strm_ent_U0_ap_ready <= ap_sync_filter11x11_strm_ent_U0_ap_ready;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    Loop_HConvH_proc6_U0_ap_ready_count_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_logic_0 = Loop_HConvH_proc6_U0_ap_ready) and (ap_sync_ready = ap_const_logic_1))) then 
+                Loop_HConvH_proc6_U0_ap_ready_count <= std_logic_vector(unsigned(Loop_HConvH_proc6_U0_ap_ready_count) - unsigned(ap_const_lv2_1));
+            elsif (((ap_const_logic_1 = Loop_HConvH_proc6_U0_ap_ready) and (ap_sync_ready = ap_const_logic_0))) then 
+                Loop_HConvH_proc6_U0_ap_ready_count <= std_logic_vector(unsigned(Loop_HConvH_proc6_U0_ap_ready_count) + unsigned(ap_const_lv2_1));
+            end if; 
+        end if;
+    end process;
+
+    filter11x11_strm_ent_U0_ap_ready_count_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_sync_ready = ap_const_logic_1) and (filter11x11_strm_ent_U0_ap_ready = ap_const_logic_0))) then 
+                filter11x11_strm_ent_U0_ap_ready_count <= std_logic_vector(unsigned(filter11x11_strm_ent_U0_ap_ready_count) - unsigned(ap_const_lv2_1));
+            elsif (((ap_sync_ready = ap_const_logic_0) and (filter11x11_strm_ent_U0_ap_ready = ap_const_logic_1))) then 
+                filter11x11_strm_ent_U0_ap_ready_count <= std_logic_vector(unsigned(filter11x11_strm_ent_U0_ap_ready_count) + unsigned(ap_const_lv2_1));
+            end if; 
+        end if;
+    end process;
+    Block_proc_U0_ap_continue <= ap_const_logic_1;
+    Block_proc_U0_ap_start <= start_for_Block_proc_U0_empty_n;
+    Loop_Border_proc_U0_ap_continue <= ap_const_logic_1;
+    Loop_Border_proc_U0_ap_start <= start_for_Loop_Border_proc_U0_empty_n;
+    Loop_Border_proc_U0_start_full_n <= ap_const_logic_1;
+    Loop_Border_proc_U0_start_write <= ap_const_logic_0;
+    Loop_HConvH_proc6_U0_ap_continue <= ap_const_logic_1;
+    Loop_HConvH_proc6_U0_ap_start <= ((ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready xor ap_const_logic_1) and ap_start);
+    Loop_HConvH_proc6_U0_start_full_n <= ap_const_logic_1;
+    Loop_HConvH_proc6_U0_start_write <= ap_const_logic_0;
+    Loop_VConvH_proc_U0_ap_continue <= ap_const_logic_1;
+    Loop_VConvH_proc_U0_ap_start <= start_for_Loop_VConvH_proc_U0_empty_n;
+    Loop_VConvH_proc_U0_start_full_n <= ap_const_logic_1;
+    Loop_VConvH_proc_U0_start_write <= ap_const_logic_0;
+    ap_done <= Loop_Border_proc_U0_ap_done;
+    ap_idle <= (filter11x11_strm_ent_U0_ap_idle and Loop_VConvH_proc_U0_ap_idle and Loop_HConvH_proc6_U0_ap_idle and Loop_Border_proc_U0_ap_idle and Block_proc_U0_ap_idle);
+    ap_ready <= ap_sync_ready;
+
+    ap_rst_n_inv_assign_proc : process(ap_rst_n)
+    begin
+                ap_rst_n_inv <= not(ap_rst_n);
+    end process;
+
+    ap_sync_Loop_HConvH_proc6_U0_ap_ready <= (ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready or Loop_HConvH_proc6_U0_ap_ready);
+    ap_sync_continue <= ap_const_logic_1;
+    ap_sync_done <= Loop_Border_proc_U0_ap_done;
+    ap_sync_filter11x11_strm_ent_U0_ap_ready <= (filter11x11_strm_ent_U0_ap_ready or ap_sync_reg_filter11x11_strm_ent_U0_ap_ready);
+    ap_sync_ready <= (ap_sync_filter11x11_strm_ent_U0_ap_ready and ap_sync_Loop_HConvH_proc6_U0_ap_ready);
+    dst_V_TDATA <= Loop_Border_proc_U0_dst_V_TDATA;
+    dst_V_TVALID <= Loop_Border_proc_U0_dst_V_TVALID;
+    filter11x11_strm_ent_U0_ap_continue <= ap_const_logic_1;
+    filter11x11_strm_ent_U0_ap_start <= ((ap_sync_reg_filter11x11_strm_ent_U0_ap_ready xor ap_const_logic_1) and ap_start);
+    filter11x11_strm_ent_U0_start_full_n <= (start_for_Loop_VConvH_proc_U0_full_n and start_for_Block_proc_U0_full_n);
+    src_V_TREADY <= Loop_HConvH_proc6_U0_src_V_TREADY;
+    start_for_Block_proc_U0_din <= (0=>ap_const_logic_1, others=>'-');
+    start_for_Loop_Border_proc_U0_din <= (0=>ap_const_logic_1, others=>'-');
+    start_for_Loop_VConvH_proc_U0_din <= (0=>ap_const_logic_1, others=>'-');
+end behav;

ip_repo_sources/neuron_packed/src/filter11x11_strm_ent.vhd

@@ -0,0 +1,368 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+-- Version: 2018.3
+-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity filter11x11_strm_ent is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    start_full_n : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    start_out : OUT STD_LOGIC;
+    start_write : OUT STD_LOGIC;
+    width : IN STD_LOGIC_VECTOR (31 downto 0);
+    height : IN STD_LOGIC_VECTOR (31 downto 0);
+    filt1 : IN STD_LOGIC_VECTOR (31 downto 0);
+    filt2 : IN STD_LOGIC_VECTOR (31 downto 0);
+    width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    width_out_full_n : IN STD_LOGIC;
+    width_out_write : OUT STD_LOGIC;
+    width_out1_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    width_out1_full_n : IN STD_LOGIC;
+    width_out1_write : OUT STD_LOGIC;
+    height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    height_out_full_n : IN STD_LOGIC;
+    height_out_write : OUT STD_LOGIC;
+    height_out2_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    height_out2_full_n : IN STD_LOGIC;
+    height_out2_write : OUT STD_LOGIC;
+    filt1_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    filt1_out_full_n : IN STD_LOGIC;
+    filt1_out_write : OUT STD_LOGIC;
+    filt1_out3_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    filt1_out3_full_n : IN STD_LOGIC;
+    filt1_out3_write : OUT STD_LOGIC;
+    filt2_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    filt2_out_full_n : IN STD_LOGIC;
+    filt2_out_write : OUT STD_LOGIC;
+    filt2_out4_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    filt2_out4_full_n : IN STD_LOGIC;
+    filt2_out4_write : OUT STD_LOGIC );
+end;
+
+
+architecture behav of filter11x11_strm_ent is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+
+    signal real_start : STD_LOGIC;
+    signal start_once_reg : STD_LOGIC := '0';
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal internal_ap_ready : STD_LOGIC;
+    signal width_out_blk_n : STD_LOGIC;
+    signal width_out1_blk_n : STD_LOGIC;
+    signal height_out_blk_n : STD_LOGIC;
+    signal height_out2_blk_n : STD_LOGIC;
+    signal filt1_out_blk_n : STD_LOGIC;
+    signal filt1_out3_blk_n : STD_LOGIC;
+    signal filt2_out_blk_n : STD_LOGIC;
+    signal filt2_out4_blk_n : STD_LOGIC;
+    signal ap_block_state1 : BOOLEAN;
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
+
+
+begin
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    start_once_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                start_once_reg <= ap_const_logic_0;
+            else
+                if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then 
+                    start_once_reg <= ap_const_logic_1;
+                elsif ((internal_ap_ready = ap_const_logic_1)) then 
+                    start_once_reg <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                ap_NS_fsm <= ap_ST_fsm_state1;
+            when others =>  
+                ap_NS_fsm <= "X";
+        end case;
+    end process;
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+
+    ap_block_state1_assign_proc : process(real_start, ap_done_reg, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
+    begin
+                ap_block_state1 <= ((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
+    end process;
+
+
+    ap_done_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
+    begin
+        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_done_reg;
+        end if; 
+    end process;
+
+
+    ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
+    begin
+        if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_ready <= internal_ap_ready;
+
+    filt1_out3_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, filt1_out3_full_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt1_out3_blk_n <= filt1_out3_full_n;
+        else 
+            filt1_out3_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    filt1_out3_din <= filt1;
+
+    filt1_out3_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
+    begin
+        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt1_out3_write <= ap_const_logic_1;
+        else 
+            filt1_out3_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    filt1_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, filt1_out_full_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt1_out_blk_n <= filt1_out_full_n;
+        else 
+            filt1_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    filt1_out_din <= filt1;
+
+    filt1_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
+    begin
+        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt1_out_write <= ap_const_logic_1;
+        else 
+            filt1_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    filt2_out4_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, filt2_out4_full_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt2_out4_blk_n <= filt2_out4_full_n;
+        else 
+            filt2_out4_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    filt2_out4_din <= filt2;
+
+    filt2_out4_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
+    begin
+        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt2_out4_write <= ap_const_logic_1;
+        else 
+            filt2_out4_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    filt2_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, filt2_out_full_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt2_out_blk_n <= filt2_out_full_n;
+        else 
+            filt2_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    filt2_out_din <= filt2;
+
+    filt2_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
+    begin
+        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt2_out_write <= ap_const_logic_1;
+        else 
+            filt2_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    height_out2_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, height_out2_full_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_out2_blk_n <= height_out2_full_n;
+        else 
+            height_out2_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    height_out2_din <= height;
+
+    height_out2_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
+    begin
+        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_out2_write <= ap_const_logic_1;
+        else 
+            height_out2_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    height_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, height_out_full_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_out_blk_n <= height_out_full_n;
+        else 
+            height_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    height_out_din <= height;
+
+    height_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
+    begin
+        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_out_write <= ap_const_logic_1;
+        else 
+            height_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    internal_ap_ready_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
+    begin
+        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            internal_ap_ready <= ap_const_logic_1;
+        else 
+            internal_ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
+    begin
+        if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then 
+            real_start <= ap_const_logic_0;
+        else 
+            real_start <= ap_start;
+        end if; 
+    end process;
+
+    start_out <= real_start;
+
+    start_write_assign_proc : process(real_start, start_once_reg)
+    begin
+        if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then 
+            start_write <= ap_const_logic_1;
+        else 
+            start_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    width_out1_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out1_full_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_out1_blk_n <= width_out1_full_n;
+        else 
+            width_out1_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    width_out1_din <= width;
+
+    width_out1_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
+    begin
+        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_out1_write <= ap_const_logic_1;
+        else 
+            width_out1_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    width_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_out_blk_n <= width_out_full_n;
+        else 
+            width_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    width_out_din <= width;
+
+    width_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
+    begin
+        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_out_write <= ap_const_logic_1;
+        else 
+            width_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+end behav;

ip_repo_sources/neuron_packed/src/globals.vhd

@@ -0,0 +1,40 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.math_real.all;
+
+package myPackage is
+    
+    constant nNodes : integer := 10;
+    constant nBits : integer := 32;
+    subtype dataType is std_logic_vector(nBits-1 downto 0);
+    type dataVector is array(nNodes-1 downto 0) of std_logic_vector(nBits-1 downto 0);
+    function to_dataVector(x : in std_logic_vector(nBits*nNodes-1 downto 0)) return dataVector;
+    
+end myPackage;
+
+package body myPackage is
+    function to_dataVector(x : in std_logic_vector(nBits*nNodes-1 downto 0)) return dataVector is
+    variable ret : dataVector;
+    begin
+        for i in integer range 0 to (x'length/nBits) - 1 loop
+            ret(i) := x(i * nBits + nBits - 1 downto i * nBits);
+        end loop;
+        return ret;
+    end function;
+
+end myPackage;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.myPackage.ALL;
+
+entity globals is
+--Port ( );
+end globals;
+
+architecture Behavioral of globals is
+
+begin
+
+
+end Behavioral;

ip_repo_sources/neuron_packed/src/mac.vhd

@@ -0,0 +1,42 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_arith.ALL;
+use IEEE.std_logic_textio.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.myPackage.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity mac is
+    Port ( inputs : in dataVector;
+           weights : in dataVector;
+           bias : in dataType;
+           outp : out dataType;
+           clk: in STD_LOGIC);
+end mac;
+
+architecture Behavioral of mac is
+
+begin
+
+MAIN: process(clk)
+    variable sum : dataType;
+begin
+    if rising_edge(clk) then
+        sum :=  bias;
+        for i in 0 to nNodes-1 loop
+            sum := signed(sum) + conv_integer(signed(inputs(i))) * conv_integer(signed(weights(i)));
+        end loop;
+        
+        outp <= sum;
+    end if;
+end process;
+
+end Behavioral;

ip_repo_sources/neuron_packed/src/multiplex.vhd

@@ -0,0 +1,228 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03.06.2019 18:42:50
+-- Design Name: 
+-- Module Name: multiplex - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_arith.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.myPackage.ALL;
+
+entity multiplex is
+    generic(
+        busWidth : integer:=32);
+    Port ( clk : in STD_LOGIC;
+           start : in STD_LOGIC;
+           ready: out std_logic;
+           rst : in STD_LOGIC;
+           done : out STD_LOGIC;
+           idle : out STD_LOGIC;
+           
+           moduleId : in STD_LOGIC_VECTOR (31 downto 0);
+           
+           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           srcValid : in std_logic;
+           srcReady : out std_logic;
+           
+           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           dstValid : out std_logic;
+           dstReady : in std_logic
+    );
+end multiplex;
+
+architecture Behavioral of multiplex is
+
+component parallelize is
+    generic(
+        busWidth : integer:=busWidth);
+    Port ( clk : in STD_LOGIC;
+           rst : in STD_LOGIC;
+           start : in STD_LOGIC;
+           dataIn : in std_logic_vector(busWidth-1 downto 0);
+           ready: out std_logic;
+           dataOutReset : in std_logic;
+           dataOut : out std_logic_vector(busWidth-1 downto 0);
+           finished : out STD_LOGIC);
+end component;
+
+component dummyModule is
+    generic(
+        busWidth : integer:=busWidth;
+        regDepth : integer);
+    Port ( clk : in STD_LOGIC;
+           rst_n : in STD_LOGIC;
+           start : in STD_LOGIC;
+           ready: out std_logic;
+           idle : out std_logic;
+           done : out std_logic;
+           
+           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           srcValid : in std_logic;
+           srcReady : out std_logic;
+           
+           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           dstValid : out std_logic;
+           dstReady : in std_logic);
+end component;
+
+component filter11x11_strm is
+port (
+    width : IN STD_LOGIC_VECTOR (31 downto 0);
+    height : IN STD_LOGIC_VECTOR (31 downto 0);
+    filt1 : IN STD_LOGIC_VECTOR (31 downto 0);
+    filt2 : IN STD_LOGIC_VECTOR (31 downto 0);
+    src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+    dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+    ap_clk : IN STD_LOGIC;
+    ap_rst_n : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    src_V_TVALID : IN STD_LOGIC;
+    src_V_TREADY : OUT STD_LOGIC;
+    dst_V_TVALID : OUT STD_LOGIC;
+    dst_V_TREADY : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    ap_idle : OUT STD_LOGIC);
+end component;
+
+constant N : integer := 3;
+type muxBitVector is array(0 to N-1) of std_logic;
+type muxDataVector is array(0 to N-1) of std_logic_vector(busWidth-1 downto 0);
+subtype filter11_t is std_logic_vector(busWidth-1 downto 0);
+
+constant moduleIds : muxDataVector :=(
+    0 => x"2cb31e7c",
+    1 => x"f218e0a2",
+    2 => x"9323eb24"
+);
+
+signal imgWidth : std_logic_vector(busWidth-1 downto 0) := std_logic_vector(conv_unsigned(224, 32));
+signal imgHeight : std_logic_vector(busWidth-1 downto 0) := std_logic_vector(conv_unsigned(224, 32));
+
+signal filt1 : filter11_t := x"00000001";
+signal filt2 : filter11_t := x"00000001";
+
+signal muxSrcData : std_logic_vector(busWidth-1 downto 0);
+signal muxSrcValid : std_logic;
+signal muxSrcReady : muxBitVector := (others => '1');
+
+signal muxDstData : muxDataVector;
+signal muxDstValid : muxBitVector := (others => '0');
+signal muxDstReady : std_logic;
+
+signal muxReady : muxBitVector := (others => '1');
+signal muxIdle : muxBitVector := (others => '1');
+signal muxDone : muxBitVector := (others => '1');
+
+signal muxStart : muxBitVector := (others => '0');
+
+
+
+begin
+    dummyBig : dummyModule 
+    generic map (
+        regDepth => 1024
+    ) port map (
+        clk     => clk,
+        rst_n   => rst,
+        
+        srcData => muxSrcData,
+        srcValid=> muxSrcValid,
+        srcReady=> muxSrcReady(0),
+        
+        dstData => muxDstData(0),
+        dstValid => muxDstValid(0),
+        dstReady => muxDstReady,
+        
+        start   => muxStart(0),
+        ready   => muxReady(0),
+        idle    => muxIdle(0),
+        done    => muxDone(0)
+    );
+    
+    dummy : dummyModule 
+    generic map (
+        regDepth => 4
+    ) port map (
+        clk     => clk,
+        rst_n   => rst,
+        
+        srcData => muxSrcData,
+        srcValid=> muxSrcValid,
+        srcReady=> muxSrcReady(1),
+        
+        dstData => muxDstData(1),
+        dstValid => muxDstValid(1),
+        dstReady => muxDstReady,
+        
+        start   => muxStart(1),
+        ready   => muxReady(1),
+        idle    => muxIdle(1),
+        done    => muxDone(1)
+    );
+    f11 : filter11x11_strm port map (
+        ap_clk => clk,
+        ap_rst_n => rst,
+        ap_start => muxStart(2),
+        ap_done => muxDone(2),
+        ap_ready => muxReady(2),
+        ap_idle => muxIdle(2),
+        width => imgWidth,
+        height => imgHeight,
+        
+        src_V_TDATA => muxSrcData,
+        src_V_TVALID => muxSrcValid,
+        src_V_TREADY => muxSrcReady(2),
+        
+        dst_V_TDATA => muxDstData(2),
+        dst_V_TVALID => muxDstValid(2),
+        dst_V_TREADY => muxDstReady,
+        
+        filt1 => filt1,
+        filt2 => filt2
+        
+    );
+
+    process(moduleId, muxSrcReady, muxReady, muxDstData, muxDstValid, muxDone, muxIdle, start)
+        variable i : integer range 0 to N-1;
+    begin
+        i := 0;
+        for k in 0 to N-1 loop
+            if moduleIds(k) = moduleId then
+                i := k;
+            end if;
+        end loop;
+        
+        ready <= muxReady(i);
+        dstData <= muxDstData(i);
+        done <= muxDone(i);
+        idle <= muxIdle(i);
+        dstValid <= muxDstValid(i);
+        srcReady <= muxSrcReady(i);
+        
+        muxStart <= (others => '0');
+        muxStart(i) <= start;
+    end process;
+    
+    muxSrcValid <= srcValid;
+    muxSrcData <= srcData;
+    muxDstReady <= dstReady;
+    
+end Behavioral;

ip_repo_sources/neuron_packed/src/neuron.vhd

@@ -0,0 +1,61 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.myPackage.ALL;
+
+entity neuron is
+    Port (
+        inputs : in dataVector;
+        weights : in dataVector;
+        bias : in dataType;
+        start : in std_logic;
+        finished : out std_logic;
+        clk : in std_logic;
+        outp : out dataType);
+end neuron;
+
+architecture Behavioral of neuron is 
+
+component mac is
+ port ( 
+   inputs : in dataVector;
+   weights : in dataVector;
+   bias : in dataType;
+   outp : out dataType;
+   clk : in std_logic);
+end component;
+
+component relu is
+ port ( 
+   inp : in dataType;
+   clk : in std_logic;
+   outp : out dataType);
+end component;
+
+signal var1 : dataType;
+
+signal macFinished: std_logic;
+
+begin
+mac1: mac port map (
+    inputs => inputs,
+    weights => weights,
+    bias => bias,
+    outp => var1,
+    clk => clk
+);
+
+relu1: relu port map (
+    inp => var1,
+    clk => clk,
+    outp => outp
+);
+
+timing : process(clk)
+begin
+    if(rising_edge(clk)) then
+        macFinished <= start;
+        finished <= macFinished;
+    end if;
+end process;
+
+end Behavioral;

ip_repo_sources/neuron_packed/src/packaging.vhd

@@ -0,0 +1,346 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03.06.2019 20:10:59
+-- Design Name: 
+-- Module Name: packaging - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_arith.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.myPackage.ALL;
+
+entity packaging is
+    generic(
+        busWidth : integer:=32);
+    Port ( clk : in STD_LOGIC;
+           rst : in STD_LOGIC;
+           inputStream : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           inpRdEn : out std_logic;
+           --inputDataCount : in STD_LOGIC_VECTOR (15 downto 0);
+           inputEmpty : in std_logic;
+           
+           outData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           outWrEn : out std_logic;
+           outputFull : in std_logic;
+           errorCode : out STD_LOGIC_VECTOR(3 DOWNTO 0);
+           stateOut : out STD_LOGIC_VECTOR(3 downto 0));
+end packaging;
+
+architecture Behavioral of packaging is
+
+    constant PREAMBLE : std_logic_vector(31 downto 0) := x"E1E4C312";
+    type state_t is (
+        waitPreamble, 
+        checkPreamble,
+        waitDatasetId,
+        getDatasetId,
+        waitModuleId,
+        checkModuleId, 
+        writeHeader,
+        waitProcessing,
+        waitChecksum,
+        readChecksum,
+        writeChecksum);
+    
+
+    component multiplex is
+        generic(
+            busWidth : integer:=busWidth);
+        Port (
+           clk : in STD_LOGIC;
+           start : in STD_LOGIC;
+           ready: out std_logic;
+           rst : in STD_LOGIC;
+           done : out STD_LOGIC;
+           idle : out STD_LOGIC;
+           
+           moduleId : in STD_LOGIC_VECTOR (31 downto 0);
+           
+           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           srcValid : in std_logic;
+           srcReady : out std_logic;
+           
+           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           dstValid : out std_logic;
+           dstReady : in std_logic);
+    end component;
+    
+    component checksum is
+        Port ( clk : in STD_LOGIC;
+           reset : in STD_LOGIC;
+           enable : in STD_LOGIC;
+           dataIn : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           output : out STD_LOGIC_VECTOR (busWidth-1 downto 0));
+    end component;
+    
+    signal state : state_t;
+    signal moduleId : STD_LOGIC_VECTOR (31 downto 0);
+    signal datasetId : STD_LOGIC_VECTOR (31 downto 0);
+    signal inputReadReady : std_logic;
+    signal outputWriteEnable_s : std_logic;
+    signal outputStream_s : STD_LOGIC_VECTOR (busWidth-1 downto 0);
+    signal inputReadEnable : std_logic;
+    signal outputWriteEnable : std_logic;
+    signal outputStream : STD_LOGIC_VECTOR (busWidth-1 downto 0);
+    signal errorCode_s : std_logic_vector(3 downto 0);
+    
+    signal outHeaderCounter : integer range 0 to 3;
+    
+    signal muxSrcData : STD_LOGIC_VECTOR (busWidth-1 downto 0);
+    signal muxSrcValid : std_logic;
+    signal muxSrcReady : std_logic;
+    
+    signal muxDstData : STD_LOGIC_VECTOR (busWidth-1 downto 0);
+    signal muxDstValid : std_logic;
+    signal muxDstReady : std_logic;
+    
+    signal muxStart  : std_logic;
+    signal muxReady  : std_logic;
+    signal muxDone   : std_logic;
+    signal muxIdle   : std_logic;
+    
+    signal muxControlsFIFO : std_logic;
+    
+    signal csReset : std_logic;
+    signal csOutReset : std_logic;
+    signal csSum : STD_LOGIC_VECTOR (busWidth-1 downto 0);
+    
+    signal csOutSum : STD_LOGIC_VECTOR (busWidth-1 downto 0);
+    
+begin
+
+    mux1 : multiplex port map (
+        clk => clk,
+        rst => rst,
+        start => muxStart,
+        ready  => muxReady,
+        done => muxDone,
+        idle => muxIdle,
+        
+        moduleId => moduleId,
+        
+        srcData     => muxSrcData,
+        srcValid    => muxSrcValid,
+        srcReady    => muxSrcReady,
+        
+        dstData     => muxDstData,
+        dstValid    => muxDstValid,
+        dstReady    => muxDstReady
+        
+    );
+    checksum1 : checksum port map (
+        clk => clk,
+        reset => csReset,
+        enable => inputReadEnable,
+        dataIn => inputStream,
+        output => csSum
+    );
+    checksum2 : checksum port map (
+        clk => clk,
+        reset => csOutReset,
+        enable => outputWriteEnable,
+        dataIn => outputStream,
+        output => csOutSum
+    );
+
+    sm : process(rst, clk)
+    
+    begin
+        if(rst = '0') then
+            state <= waitPreamble;
+            inputReadReady <= '0';
+            csReset <= '0';
+            csOutReset <= '0';
+            outHeaderCounter <= 3;
+            muxStart <= '0';
+            muxControlsFIFO <= '0';
+        elsif(rising_edge(clk)) then
+            csReset <= '1';
+            csOutReset <= '1';
+            errorCode_s <= x"0";
+            muxStart <= '0';
+            muxControlsFIFO <= '0';
+
+            outputWriteEnable_s <= '0';
+            outHeaderCounter <= 0;
+            
+            outputStream_s <= (others=>'0');
+        
+            case state is
+                -- wait for header
+                when waitPreamble =>
+                    csReset <= '0';
+                    inputReadReady <= '1';
+                    if(inputEmpty = '1' or outputFull = '1') then
+                        state <= waitPreamble;
+                    else
+                        state <= checkPreamble;
+                    end if;
+                    
+                -- is preamble correct?
+                when checkPreamble =>
+                    if(inputStream = PREAMBLE and inputEmpty = '0') then
+                        state <= getDatasetId;
+                    elsif inputStream = PREAMBLE then
+                        state <= waitDatasetId;
+                    else
+                        state <= waitPreamble;
+                        errorCode_s <= x"1";
+                    end if;
+                when waitDatasetId =>
+                    if inputEmpty = '1' then
+                        errorCode_s <= x"F";
+                        state <= waitDatasetId;
+                    else
+                        state <= getDatasetId;
+                    end if;
+                    
+                when getDatasetId =>
+                    datasetId <= inputStream;
+                    if inputEmpty = '1' then
+                        state <= waitModuleId;
+                    else
+                        state <= checkModuleId;
+                    end if;
+                
+                when waitModuleId =>
+                    if inputEmpty = '1' then
+                        errorCode_s <= x"E";
+                        state <= waitModuleId;
+                    else
+                        state <= checkModuleId;
+                    end if;
+                -- is moduleId known?
+                when checkModuleId =>
+                    inputReadReady <= '0';
+                    if outputFull = '1' then
+                        state <= checkModuleId;
+                        errorCode_s <= x"D";
+                    elsif(inputStream = x"2cb31e7c" or inputStream = x"f218e0a2" or inputStream = x"9323eb24") then
+                        state <= writeHeader;
+                        moduleId <= inputStream;
+                        outputStream_s <= PREAMBLE;
+                        csOutReset <= '0';
+                        outputWriteEnable_s <= '1';
+                        
+                    else
+                        state <= waitPreamble;
+                        errorCode_s <= x"2";
+                    end if;
+                    
+                -- wait for data
+                when writeHeader =>
+                    if outputFull = '1' then
+                        state <= writeHeader;
+                        errorCode_s <= x"C";
+                        outHeaderCounter <= outHeaderCounter;
+                    elsif(outHeaderCounter < 2) then
+                        outputWriteEnable_s <= '1';
+                        case outHeaderCounter is
+                            when 0 =>  outputStream_s <= datasetId;
+                            when others => outputStream_s <= moduleId;
+                        end case;
+                        outHeaderCounter <= outHeaderCounter + 1;
+                        state <= writeHeader;
+                    else
+                        state <= waitProcessing;
+                        muxStart <= '1';
+                        muxControlsFIFO <= '1';
+                    end if;
+
+                when waitProcessing =>
+                    if(muxDone = '0') then
+                        state <= waitProcessing;
+                        muxControlsFIFO <= '1';
+                        errorCode_s <= x"B";
+                        muxStart <= '1';
+                    else
+                        state <= waitChecksum;
+                        inputReadReady <= '1';
+                    end if;
+                
+                when waitChecksum =>
+                    if inputEmpty = '1' then
+                        errorCode_s <= x"A";
+                        state <= waitChecksum;
+                        inputReadReady <= '1';
+                    else
+                        state <= readChecksum;
+                        inputReadReady <= '0';
+                    end if;
+                when readChecksum =>
+                    state <= writeChecksum;
+                    
+                when writeChecksum =>
+                    if outputFull = '0' then
+                        outputWriteEnable_s <= '1';
+                        state <= waitPreamble;
+                    else
+                        state <= writeChecksum;
+                    end if;
+                    
+                    if(unsigned(csSum) = 0) then
+                        outputStream_s <= 0 - unsigned(csOutSum);
+                    else
+                        errorCode_s <= x"3";
+                        outputStream_s <= 1 - unsigned(csOutSum);
+                    end if;
+                
+                when others =>
+                    state <= waitPreamble;
+                    inputReadReady <= '0';
+            end case;
+            
+            if signed(errorCode_s) > 0 and outputFull = '0' then
+                outputWriteEnable_s <= '1';
+                outputStream_s <= x"E330300" & errorCode_s;
+            end if;
+            muxSrcValid <= muxSrcReady and not inputEmpty;
+            
+        end if;
+    end process;
+    
+    muxCtrl : process(muxControlsFIFO, outputWriteEnable_s, inputReadReady, outputStream_s, muxDstValid, muxSrcReady, muxDstData, inputStream, outputFull, inputEmpty)
+    
+    begin
+        if muxControlsFIFO = '0' then
+            outputWriteEnable   <= outputWriteEnable_s;
+            inputReadEnable     <= inputReadReady and not inputEmpty;
+            outputStream        <= outputStream_s;
+            
+            muxSrcData <= (others => 'U');
+            muxDstReady <= '0';
+        else
+            outputWriteEnable   <= muxDstValid and not outputFull;
+            inputReadEnable     <= muxSrcReady and not inputEmpty;
+            outputStream        <= muxDstData;
+            
+            muxSrcData <= inputStream;
+            muxDstReady <= not outputFull;
+        end if;
+        
+    end process;
+    errorCode <= errorCode_s;
+    stateOut <= std_logic_vector(conv_unsigned(state_t'POS(state), 4));
+    
+    outWrEn <= outputWriteEnable;
+    inpRdEn <= inputReadEnable;
+    outData <= outputStream;
+    
+end Behavioral;

ip_repo_sources/neuron_packed/src/parallelize.vhd

@@ -0,0 +1,86 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.myPackage.ALL;
+
+entity parallelize is
+    generic(
+        busWidth : integer:=8);
+    Port ( clk : in STD_LOGIC;
+           rst : in STD_LOGIC;
+           start : in STD_LOGIC;
+           dataIn : in std_logic_vector(busWidth-1 downto 0);
+           ready: out std_logic;
+           dataOutReset : in std_logic;
+           dataOut : out std_logic_vector(busWidth-1 downto 0);
+           finished : out STD_LOGIC);
+end parallelize;
+
+architecture Behavioral of parallelize is
+
+constant parallelInWidth : integer := (2*nNodes+1) * nBits;
+constant parallelOutWidth : integer := nBits;
+
+component shiftIn is
+    generic(
+        inWidth : integer := busWidth;
+        outWidth : integer := parallelInWidth);
+    Port ( clk : in STD_LOGIC;
+           sync_reset : in STD_LOGIC;
+           dataIn : in std_logic_vector(inWidth-1 downto 0);
+           dataOut : out std_logic_vector(outWidth-1 downto 0);
+           finished : out STD_LOGIC);
+end component;
+component neuron is
+    Port (
+        inputs : in dataVector;
+        weights : in dataVector;
+        bias : in dataType;
+        start : in std_logic;
+        finished : out std_logic;
+        clk : in std_logic;
+        outp : out dataType);
+end component;
+component shiftOut is
+    generic(
+        inWidth : integer := parallelOutWidth;
+        outWidth : integer := busWidth);
+    Port ( clk : in STD_LOGIC;
+           sync_reset : in STD_LOGIC;
+           dataIn : in std_logic_vector(inWidth-1 downto 0);
+           dataOut : out std_logic_vector(outWidth-1 downto 0);
+           finished : out STD_LOGIC);
+end component;
+
+signal dataInStorage : std_logic_vector(parallelInWidth-1 downto 0);
+signal dataOutStorage : std_logic_vector(parallelOutWidth-1 downto 0);
+signal shiftInFinished : std_logic;
+
+begin
+
+shiftIn1: shiftIn port map (
+    clk         => clk,
+    sync_reset  => start,
+    dataIn      => dataIn,
+    dataOut     => dataInStorage,
+    finished    => shiftInFinished
+);
+
+neuron1: neuron port map (
+    inputs  => to_dataVector(dataInStorage(parallelInWidth-1 downto (nNodes+1) * nBits)),
+    weights => to_dataVector(dataInStorage((nNodes+1) * nBits-1 downto nBits)),
+    bias    => dataInStorage(nBits-1 downto 0),
+    clk     => clk,
+    outp    => dataOutStorage,
+    start   => shiftInFinished,
+    finished=> ready
+);
+
+shiftOut1 : shiftOut port map (
+    clk         => clk,
+    sync_reset  => dataOutReset,
+    dataIn      => dataOutStorage,
+    dataOut     => dataOut,
+    finished    => finished
+);
+
+end Behavioral;

ip_repo_sources/neuron_packed/src/relu.vhd

@@ -0,0 +1,30 @@
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_signed.all;
+use IEEE.std_logic_arith.all;
+use IEEE.math_real.all;
+use work.myPackage.ALL;
+
+entity relu is
+    Port ( inp : in dataType;
+           outp : out dataType;
+           clk: in STD_LOGIC );
+end relu;
+
+architecture Behavioral of relu is
+
+begin
+    calc : process(clk)
+    begin
+        if(rising_edge(clk)) then
+            if(signed(inp) > 0) then
+                outp <= inp;
+            else
+                outp <= (others => '0');
+            end if;
+            
+        end if;
+    end process;
+end Behavioral;

ip_repo_sources/neuron_packed/src/shiftIn.vhd

@@ -0,0 +1,66 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 06/03/2019 01:56:01 PM
+-- Design Name: 
+-- Module Name: shiftOut - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity shiftIn is
+    generic(
+        inWidth : integer := 8;
+        outWidth : integer := 32);
+    Port ( clk : in STD_LOGIC;
+           ce : in std_logic;
+           sync_reset : in STD_LOGIC;
+           dataIn : in std_logic_vector(inWidth-1 downto 0);
+           dataOut : out std_logic_vector(outWidth-1 downto 0);
+           finished : out STD_LOGIC);
+end shiftIn;
+
+architecture Behavioral of shiftIn is
+    signal dataIndex : integer range 0 to (outWidth / inWidth) := 0;
+    signal dataOut_s : std_logic_vector(outWidth-1 downto 0);
+begin
+
+p_s2p : process(clk, sync_reset, dataIndex)
+begin
+    if(sync_reset = '0') then
+        dataIndex <= 0;
+        finished <= '0';
+        dataOut_s <= (others => '0');
+    elsif(rising_edge(clk)) then
+        if(dataIndex < outWidth/inWidth and ce = '1') then
+            --dataOut_s(outWidth - dataIndex * inWidth - 1 downto outWidth - dataIndex * inWidth - inWidth) <= dataIn;
+            dataOut_s <= dataOut_s(outWidth-1 - inWidth downto 0) & dataIn;
+            dataIndex <= dataIndex + 1;
+        else
+            dataIndex <= dataIndex;
+            dataOut_s <= dataOut_s;
+        end if;
+    end if;
+    if(dataIndex < outWidth/inWidth) then
+        finished <= '0';
+    else
+        finished <= '1';
+    end if;
+end process;
+
+dataOut <= dataOut_s;
+end Behavioral;

ip_repo_sources/neuron_packed/src/shiftOut.vhd

@@ -0,0 +1,72 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 06/03/2019 01:56:01 PM
+-- Design Name: 
+-- Module Name: shiftOut - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity shiftOut is
+    generic(
+        inWidth : integer := 32*4;
+        outWidth : integer := 32);
+    Port ( clk : in STD_LOGIC;
+           ce : in std_logic;
+           sync_reset : in STD_LOGIC;
+           dataIn : in std_logic_vector(inWidth-1 downto 0);
+           dataOut : out std_logic_vector(outWidth-1 downto 0);
+           valid : out std_logic;
+           finished : out STD_LOGIC);
+end shiftOut;
+
+architecture Behavioral of shiftOut is
+    signal dataIndex : integer range -1 to (inWidth / outWidth)-1 := 0;
+begin
+
+p_s2p : process(clk, sync_reset)
+begin
+    if(sync_reset = '0') then
+        dataIndex <= -1;
+        finished <= '0';
+        valid <= '0';
+    elsif(rising_edge(clk)) then
+        if dataIndex < inWidth/outWidth-1 and ce='0' then
+            finished <= '0';
+            dataIndex <= dataIndex;
+            valid <= '0';
+        elsif(dataIndex < inWidth/outWidth-1) then
+            finished <= '0';
+            dataIndex <= dataIndex + 1;
+            valid <= '1';
+        else
+            finished <= '1';
+            dataIndex <= dataIndex;
+            valid <= '0';
+        end if;
+    end if;
+end process;
+
+process(dataIn, dataIndex) begin
+    if dataIndex >= 0 then
+        dataOut <= dataIn(inWidth - dataIndex * outWidth - 1 downto inWidth - dataIndex * outWidth - outWidth);
+    else
+        dataOut <= (others => 'U');
+    end if;
+end process;
+end Behavioral;

ip_repo_sources/neuron_packed/src/start_for_Block_proc_U0.vhd

@@ -0,0 +1,140 @@
+-- ==============================================================
+-- File generated on Wed Jun 26 16:53:30 CEST 2019
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
+-- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
+-- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity start_for_Block_proc_U0_shiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH : integer := 2);
+    port (
+        clk : in std_logic;
+        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        ce : in std_logic;
+        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end start_for_Block_proc_U0_shiftReg;
+
+architecture rtl of start_for_Block_proc_U0_shiftReg is
+--constant DEPTH_WIDTH: integer := 16;
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+p_shift: process (clk)
+begin
+    if (clk'event and clk = '1') then
+        if (ce = '1') then
+            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
+        end if;
+    end if;
+end process;
+
+q <= SRL_SIG(conv_integer(a));
+
+end rtl;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+entity start_for_Block_proc_U0 is 
+    generic (
+        MEM_STYLE  : string := "shiftreg"; 
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH : integer := 2);
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        if_empty_n : OUT STD_LOGIC;
+        if_read_ce : IN STD_LOGIC;
+        if_read : IN STD_LOGIC;
+        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_full_n : OUT STD_LOGIC;
+        if_write_ce : IN STD_LOGIC;
+        if_write : IN STD_LOGIC;
+        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+end entity;
+
+architecture rtl of start_for_Block_proc_U0 is
+
+    component start_for_Block_proc_U0_shiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH : integer := 2);
+    port (
+        clk : in std_logic;
+        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        ce : in std_logic;
+        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
+    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+    signal shiftReg_ce : STD_LOGIC;
+    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
+    signal internal_empty_n : STD_LOGIC := '0';
+    signal internal_full_n  : STD_LOGIC := '1';
+
+begin
+    if_empty_n <= internal_empty_n;
+    if_full_n <= internal_full_n;
+    shiftReg_data <= if_din;
+    if_dout <= shiftReg_q;
+
+    process (clk)
+    begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '1');
+                internal_empty_n <= '0';
+                internal_full_n <= '1';
+            else
+                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
+                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
+                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2);
+                    if (mOutPtr = conv_std_logic_vector(0, 2)) then 
+                        internal_empty_n <= '0';
+                    end if;
+                    internal_full_n <= '1';
+                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
+                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
+                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2);
+                    internal_empty_n <= '1';
+                    if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then 
+                        internal_full_n <= '0';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
+    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
+
+    U_start_for_Block_proc_U0_shiftReg : start_for_Block_proc_U0_shiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => ADDR_WIDTH,
+        DEPTH => DEPTH)
+    port map (
+        clk => clk,
+        data => shiftReg_data,
+        ce => shiftReg_ce,
+        a => shiftReg_addr,
+        q => shiftReg_q);
+
+end rtl;
+

ip_repo_sources/neuron_packed/src/start_for_Loop_Border_proc_U0.vhd

@@ -0,0 +1,140 @@
+-- ==============================================================
+-- File generated on Wed Jun 26 16:53:30 CEST 2019
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
+-- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
+-- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity start_for_Loop_Border_proc_U0_shiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 2;
+        DEPTH : integer := 3);
+    port (
+        clk : in std_logic;
+        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        ce : in std_logic;
+        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end start_for_Loop_Border_proc_U0_shiftReg;
+
+architecture rtl of start_for_Loop_Border_proc_U0_shiftReg is
+--constant DEPTH_WIDTH: integer := 16;
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+p_shift: process (clk)
+begin
+    if (clk'event and clk = '1') then
+        if (ce = '1') then
+            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
+        end if;
+    end if;
+end process;
+
+q <= SRL_SIG(conv_integer(a));
+
+end rtl;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+entity start_for_Loop_Border_proc_U0 is 
+    generic (
+        MEM_STYLE  : string := "shiftreg"; 
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 2;
+        DEPTH : integer := 3);
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        if_empty_n : OUT STD_LOGIC;
+        if_read_ce : IN STD_LOGIC;
+        if_read : IN STD_LOGIC;
+        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_full_n : OUT STD_LOGIC;
+        if_write_ce : IN STD_LOGIC;
+        if_write : IN STD_LOGIC;
+        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+end entity;
+
+architecture rtl of start_for_Loop_Border_proc_U0 is
+
+    component start_for_Loop_Border_proc_U0_shiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 2;
+        DEPTH : integer := 3);
+    port (
+        clk : in std_logic;
+        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        ce : in std_logic;
+        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
+    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+    signal shiftReg_ce : STD_LOGIC;
+    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
+    signal internal_empty_n : STD_LOGIC := '0';
+    signal internal_full_n  : STD_LOGIC := '1';
+
+begin
+    if_empty_n <= internal_empty_n;
+    if_full_n <= internal_full_n;
+    shiftReg_data <= if_din;
+    if_dout <= shiftReg_q;
+
+    process (clk)
+    begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '1');
+                internal_empty_n <= '0';
+                internal_full_n <= '1';
+            else
+                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
+                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
+                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
+                    if (mOutPtr = conv_std_logic_vector(0, 3)) then 
+                        internal_empty_n <= '0';
+                    end if;
+                    internal_full_n <= '1';
+                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
+                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
+                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
+                    internal_empty_n <= '1';
+                    if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then 
+                        internal_full_n <= '0';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
+    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
+
+    U_start_for_Loop_Border_proc_U0_shiftReg : start_for_Loop_Border_proc_U0_shiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => ADDR_WIDTH,
+        DEPTH => DEPTH)
+    port map (
+        clk => clk,
+        data => shiftReg_data,
+        ce => shiftReg_ce,
+        a => shiftReg_addr,
+        q => shiftReg_q);
+
+end rtl;
+

ip_repo_sources/neuron_packed/src/start_for_Loop_VConvH_proc_U0.vhd

@@ -0,0 +1,140 @@
+-- ==============================================================
+-- File generated on Wed Jun 26 16:53:30 CEST 2019
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
+-- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
+-- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity start_for_Loop_VConvH_proc_U0_shiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 2;
+        DEPTH : integer := 3);
+    port (
+        clk : in std_logic;
+        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        ce : in std_logic;
+        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end start_for_Loop_VConvH_proc_U0_shiftReg;
+
+architecture rtl of start_for_Loop_VConvH_proc_U0_shiftReg is
+--constant DEPTH_WIDTH: integer := 16;
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+p_shift: process (clk)
+begin
+    if (clk'event and clk = '1') then
+        if (ce = '1') then
+            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
+        end if;
+    end if;
+end process;
+
+q <= SRL_SIG(conv_integer(a));
+
+end rtl;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+entity start_for_Loop_VConvH_proc_U0 is 
+    generic (
+        MEM_STYLE  : string := "shiftreg"; 
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 2;
+        DEPTH : integer := 3);
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        if_empty_n : OUT STD_LOGIC;
+        if_read_ce : IN STD_LOGIC;
+        if_read : IN STD_LOGIC;
+        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+        if_full_n : OUT STD_LOGIC;
+        if_write_ce : IN STD_LOGIC;
+        if_write : IN STD_LOGIC;
+        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
+end entity;
+
+architecture rtl of start_for_Loop_VConvH_proc_U0 is
+
+    component start_for_Loop_VConvH_proc_U0_shiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 2;
+        DEPTH : integer := 3);
+    port (
+        clk : in std_logic;
+        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        ce : in std_logic;
+        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
+    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
+    signal shiftReg_ce : STD_LOGIC;
+    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
+    signal internal_empty_n : STD_LOGIC := '0';
+    signal internal_full_n  : STD_LOGIC := '1';
+
+begin
+    if_empty_n <= internal_empty_n;
+    if_full_n <= internal_full_n;
+    shiftReg_data <= if_din;
+    if_dout <= shiftReg_q;
+
+    process (clk)
+    begin
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '1');
+                internal_empty_n <= '0';
+                internal_full_n <= '1';
+            else
+                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
+                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
+                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
+                    if (mOutPtr = conv_std_logic_vector(0, 3)) then 
+                        internal_empty_n <= '0';
+                    end if;
+                    internal_full_n <= '1';
+                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
+                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
+                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
+                    internal_empty_n <= '1';
+                    if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then 
+                        internal_full_n <= '0';
+                    end if;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
+    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
+
+    U_start_for_Loop_VConvH_proc_U0_shiftReg : start_for_Loop_VConvH_proc_U0_shiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => ADDR_WIDTH,
+        DEPTH => DEPTH)
+    port map (
+        clk => clk,
+        data => shiftReg_data,
+        ce => shiftReg_ce,
+        a => shiftReg_addr,
+        q => shiftReg_q);
+
+end rtl;
+

ip_repo_sources/neuron_packed/xgui/packaging_v1_0.tcl

@@ -0,0 +1,25 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "busWidth" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
+	# Procedure called to update busWidth when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
+	# Procedure called to validate busWidth
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.busWidth { MODELPARAM_VALUE.busWidth PARAM_VALUE.busWidth } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.busWidth}] ${MODELPARAM_VALUE.busWidth}
+}
+

ip_repo_sources/neuron_packed/xgui/packaging_v2_0.tcl

@@ -0,0 +1,25 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "busWidth" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
+	# Procedure called to update busWidth when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
+	# Procedure called to validate busWidth
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.busWidth { MODELPARAM_VALUE.busWidth PARAM_VALUE.busWidth } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.busWidth}] ${MODELPARAM_VALUE.busWidth}
+}
+

ip_repo_sources/src/Block_proc.vhd

@@ -0,0 +1,321 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+-- Version: 2018.3
+-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity Block_proc is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    start_full_n : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    start_out : OUT STD_LOGIC;
+    start_write : OUT STD_LOGIC;
+    width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    width_empty_n : IN STD_LOGIC;
+    width_read : OUT STD_LOGIC;
+    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    height_empty_n : IN STD_LOGIC;
+    height_read : OUT STD_LOGIC;
+    width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    width_out_full_n : IN STD_LOGIC;
+    width_out_write : OUT STD_LOGIC;
+    height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    height_out_full_n : IN STD_LOGIC;
+    height_out_write : OUT STD_LOGIC;
+    vconv_xlim_out_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    vconv_xlim_out_out_full_n : IN STD_LOGIC;
+    vconv_xlim_out_out_write : OUT STD_LOGIC );
+end;
+
+
+architecture behav of Block_proc is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv32_FFFFFFF6 : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111110110";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+
+    signal real_start : STD_LOGIC;
+    signal start_once_reg : STD_LOGIC := '0';
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal internal_ap_ready : STD_LOGIC;
+    signal width_blk_n : STD_LOGIC;
+    signal height_blk_n : STD_LOGIC;
+    signal width_out_blk_n : STD_LOGIC;
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal height_out_blk_n : STD_LOGIC;
+    signal vconv_xlim_out_out_blk_n : STD_LOGIC;
+    signal width_read_reg_69 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state1 : BOOLEAN;
+    signal height_read_reg_75 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state2 : BOOLEAN;
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
+
+
+begin
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    start_once_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                start_once_reg <= ap_const_logic_0;
+            else
+                if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then 
+                    start_once_reg <= ap_const_logic_1;
+                elsif ((internal_ap_ready = ap_const_logic_1)) then 
+                    start_once_reg <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                height_read_reg_75 <= height_dout;
+                width_read_reg_69 <= width_dout;
+            end if;
+        end if;
+    end process;
+
+    ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, width_empty_n, height_empty_n, width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                end if;
+            when others =>  
+                ap_NS_fsm <= "XX";
+        end case;
+    end process;
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+
+    ap_block_state1_assign_proc : process(real_start, ap_done_reg, width_empty_n, height_empty_n)
+    begin
+                ap_block_state1 <= ((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
+    end process;
+
+
+    ap_block_state2_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n)
+    begin
+                ap_block_state2 <= ((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0));
+    end process;
+
+
+    ap_done_assign_proc : process(ap_done_reg, width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_done_reg;
+        end if; 
+    end process;
+
+
+    ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
+    begin
+        if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_ready <= internal_ap_ready;
+
+    height_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_blk_n <= height_empty_n;
+        else 
+            height_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    height_out_blk_n_assign_proc : process(height_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            height_out_blk_n <= height_out_full_n;
+        else 
+            height_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    height_out_din <= height_read_reg_75;
+
+    height_out_write_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            height_out_write <= ap_const_logic_1;
+        else 
+            height_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    height_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_read <= ap_const_logic_1;
+        else 
+            height_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    internal_ap_ready_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            internal_ap_ready <= ap_const_logic_1;
+        else 
+            internal_ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
+    begin
+        if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then 
+            real_start <= ap_const_logic_0;
+        else 
+            real_start <= ap_start;
+        end if; 
+    end process;
+
+    start_out <= real_start;
+
+    start_write_assign_proc : process(real_start, start_once_reg)
+    begin
+        if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then 
+            start_write <= ap_const_logic_1;
+        else 
+            start_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    vconv_xlim_out_out_blk_n_assign_proc : process(vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            vconv_xlim_out_out_blk_n <= vconv_xlim_out_out_full_n;
+        else 
+            vconv_xlim_out_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    vconv_xlim_out_out_din <= std_logic_vector(unsigned(width_read_reg_69) + unsigned(ap_const_lv32_FFFFFFF6));
+
+    vconv_xlim_out_out_write_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            vconv_xlim_out_out_write <= ap_const_logic_1;
+        else 
+            vconv_xlim_out_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    width_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_blk_n <= width_empty_n;
+        else 
+            width_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    width_out_blk_n_assign_proc : process(width_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            width_out_blk_n <= width_out_full_n;
+        else 
+            width_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    width_out_din <= width_read_reg_69;
+
+    width_out_write_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
+    begin
+        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            width_out_write <= ap_const_logic_1;
+        else 
+            width_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    width_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n)
+    begin
+        if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_read <= ap_const_logic_1;
+        else 
+            width_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+end behav;

ip_repo_sources/src/Loop_Border_proc.vhd

@@ -0,0 +1,896 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+-- Version: 2018.3
+-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity Loop_Border_proc is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    width_empty_n : IN STD_LOGIC;
+    width_read : OUT STD_LOGIC;
+    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    height_empty_n : IN STD_LOGIC;
+    height_read : OUT STD_LOGIC;
+    dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
+    dst_V_TVALID : OUT STD_LOGIC;
+    dst_V_TREADY : IN STD_LOGIC;
+    vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    vconv_xlim_loc_empty_n : IN STD_LOGIC;
+    vconv_xlim_loc_read : OUT STD_LOGIC;
+    vconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    vconv_V_empty_n : IN STD_LOGIC;
+    vconv_V_read : OUT STD_LOGIC );
+end;
+
+
+architecture behav of Loop_Border_proc is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
+    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
+    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
+    constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
+    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
+    constant ap_const_lv32_FFFFFFF5 : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111110101";
+    constant ap_const_lv32_FFFFFFFA : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111010";
+    constant ap_const_lv32_FFFFFFFB : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111011";
+    constant ap_const_lv10_5 : STD_LOGIC_VECTOR (9 downto 0) := "0000000101";
+    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
+    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
+    constant ap_const_lv10_6 : STD_LOGIC_VECTOR (9 downto 0) := "0000000110";
+    constant ap_const_lv10_3FB : STD_LOGIC_VECTOR (9 downto 0) := "1111111011";
+    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
+
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal dst_V_1_data_out : STD_LOGIC_VECTOR (31 downto 0);
+    signal dst_V_1_vld_in : STD_LOGIC;
+    signal dst_V_1_vld_out : STD_LOGIC;
+    signal dst_V_1_ack_in : STD_LOGIC;
+    signal dst_V_1_ack_out : STD_LOGIC;
+    signal dst_V_1_payload_A : STD_LOGIC_VECTOR (31 downto 0);
+    signal dst_V_1_payload_B : STD_LOGIC_VECTOR (31 downto 0);
+    signal dst_V_1_sel_rd : STD_LOGIC := '0';
+    signal dst_V_1_sel_wr : STD_LOGIC := '0';
+    signal dst_V_1_sel : STD_LOGIC;
+    signal dst_V_1_load_A : STD_LOGIC;
+    signal dst_V_1_load_B : STD_LOGIC;
+    signal dst_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    signal dst_V_1_state_cmp_full : STD_LOGIC;
+    signal width_blk_n : STD_LOGIC;
+    signal height_blk_n : STD_LOGIC;
+    signal dst_V_TDATA_blk_n : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0 : BOOLEAN;
+    signal exitcond_flatten_reg_499 : STD_LOGIC_VECTOR (0 downto 0);
+    signal exitcond_flatten_reg_499_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
+    signal exitcond_flatten_reg_499_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal vconv_xlim_loc_blk_n : STD_LOGIC;
+    signal vconv_V_blk_n : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
+    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
+    signal brmerge_mid2_reg_516 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_24_i_i_reg_525 : STD_LOGIC_VECTOR (0 downto 0);
+    signal indvar_flatten_reg_145 : STD_LOGIC_VECTOR (63 downto 0);
+    signal i6_0_i_i_i_reg_156 : STD_LOGIC_VECTOR (9 downto 0);
+    signal j_0_i_i_i_reg_167 : STD_LOGIC_VECTOR (9 downto 0);
+    signal width_read_reg_459 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state1 : BOOLEAN;
+    signal height_read_reg_467 : STD_LOGIC_VECTOR (31 downto 0);
+    signal vconv_xlim_loc_read_reg_473 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_9_i_i_fu_178_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_9_i_i_reg_478 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal tmp_i_i_fu_183_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_i_i_reg_483 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_7_i_i_fu_188_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_7_i_i_reg_488 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_199_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound_reg_494 : STD_LOGIC_VECTOR (63 downto 0);
+    signal exitcond_flatten_fu_247_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
+    signal ap_predicate_op59_read_state4 : BOOLEAN;
+    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
+    signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
+    signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
+    signal ap_block_state6_io : BOOLEAN;
+    signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
+    signal ap_block_state7_io : BOOLEAN;
+    signal ap_block_pp0_stage0_11001 : BOOLEAN;
+    signal exitcond_flatten_reg_499_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal indvar_flatten_next_fu_252_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
+    signal j_0_i_i_i_mid2_fu_268_p3 : STD_LOGIC_VECTOR (9 downto 0);
+    signal j_0_i_i_i_mid2_reg_508 : STD_LOGIC_VECTOR (9 downto 0);
+    signal brmerge_mid2_fu_305_p3 : STD_LOGIC_VECTOR (0 downto 0);
+    signal brmerge_mid2_reg_516_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal i6_0_i_i_i_mid2_fu_317_p3 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp_24_i_i_fu_325_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_28_i_i_fu_330_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_28_i_i_reg_529 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_28_i_i_reg_529_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_30_i_i_fu_335_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_30_i_i_reg_534 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_30_i_i_reg_534_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_30_i_i_reg_534_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal j_fu_340_p2 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp_27_i_i_fu_355_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_27_i_i_reg_544 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_29_i_i_fu_360_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_29_i_i_reg_549 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_29_i_i_reg_549_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal borderbuf_q1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal pix_out_7_reg_560 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
+    signal pix_out_8_fu_431_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_pp0_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
+    signal borderbuf_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal borderbuf_ce0 : STD_LOGIC;
+    signal borderbuf_we0 : STD_LOGIC;
+    signal borderbuf_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal borderbuf_ce1 : STD_LOGIC;
+    signal tmp_26_i_i_fu_346_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_32_i_i_fu_370_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal r_edge_pix_fu_74 : STD_LOGIC_VECTOR (31 downto 0);
+    signal pix_out_fu_78 : STD_LOGIC_VECTOR (31 downto 0);
+    signal l_edge_pix_fu_391_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal pix_out_1_fu_82 : STD_LOGIC_VECTOR (31 downto 0);
+    signal pix_in_2_l_edge_pix_s_fu_384_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_pp0_stage0_01001 : BOOLEAN;
+    signal bound_fu_199_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_199_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal i6_0_i_cast_i_i_mid1_fu_205_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal notrhs_fu_221_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal notlhs_fu_215_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_17_i_i_fu_209_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal brmerge_i_i_i_not_fu_226_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal j_0_i_cast_i_i_fu_238_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal i_fu_258_p2 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp_22_i_i_fu_242_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal i6_0_i_cast_i_i_fu_264_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal notrhs_mid1_fu_288_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal notlhs_mid1_fu_282_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_17_i_i_mid1_fu_276_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal brmerge_i_i_i_not_mi_fu_293_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal brmerge_fu_232_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal brmerge_mid1_fu_299_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal j_0_i_cast_i_i_mid2_s_fu_313_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_31_i_i_fu_365_p2 : STD_LOGIC_VECTOR (9 downto 0);
+    signal sel_tmp_fu_414_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal sel_tmp1_fu_419_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal pix_out_3_fu_424_p3 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state8 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
+    signal ap_idle_pp0 : STD_LOGIC;
+    signal ap_enable_pp0 : STD_LOGIC;
+    signal bound_fu_199_p00 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound_fu_199_p10 : STD_LOGIC_VECTOR (63 downto 0);
+
+    component Loop_Border_proc_borderbuf IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (9 downto 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR (31 downto 0);
+        address1 : IN STD_LOGIC_VECTOR (9 downto 0);
+        ce1 : IN STD_LOGIC;
+        q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+
+begin
+    borderbuf_U : component Loop_Border_proc_borderbuf
+    generic map (
+        DataWidth => 32,
+        AddressRange => 662,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => borderbuf_address0,
+        ce0 => borderbuf_ce0,
+        we0 => borderbuf_we0,
+        d0 => vconv_V_dout,
+        address1 => borderbuf_address1,
+        ce1 => borderbuf_ce1,
+        q1 => borderbuf_q1);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then 
+                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                    ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    dst_V_1_sel_rd_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                dst_V_1_sel_rd <= ap_const_logic_0;
+            else
+                if (((dst_V_1_ack_out = ap_const_logic_1) and (dst_V_1_vld_out = ap_const_logic_1))) then 
+                                        dst_V_1_sel_rd <= not(dst_V_1_sel_rd);
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    dst_V_1_sel_wr_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                dst_V_1_sel_wr <= ap_const_logic_0;
+            else
+                if (((dst_V_1_ack_in = ap_const_logic_1) and (dst_V_1_vld_in = ap_const_logic_1))) then 
+                                        dst_V_1_sel_wr <= not(dst_V_1_sel_wr);
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    dst_V_1_state_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                dst_V_1_state <= ap_const_lv2_0;
+            else
+                if ((((dst_V_1_state = ap_const_lv2_2) and (dst_V_1_vld_in = ap_const_logic_0)) or ((dst_V_1_state = ap_const_lv2_3) and (dst_V_1_vld_in = ap_const_logic_0) and (dst_V_1_ack_out = ap_const_logic_1)))) then 
+                    dst_V_1_state <= ap_const_lv2_2;
+                elsif ((((dst_V_1_state = ap_const_lv2_1) and (dst_V_1_ack_out = ap_const_logic_0)) or ((dst_V_1_state = ap_const_lv2_3) and (dst_V_1_ack_out = ap_const_logic_0) and (dst_V_1_vld_in = ap_const_logic_1)))) then 
+                    dst_V_1_state <= ap_const_lv2_1;
+                elsif (((not(((dst_V_1_vld_in = ap_const_logic_0) and (dst_V_1_ack_out = ap_const_logic_1))) and not(((dst_V_1_ack_out = ap_const_logic_0) and (dst_V_1_vld_in = ap_const_logic_1))) and (dst_V_1_state = ap_const_lv2_3)) or ((dst_V_1_state = ap_const_lv2_1) and (dst_V_1_ack_out = ap_const_logic_1)) or ((dst_V_1_state = ap_const_lv2_2) and (dst_V_1_vld_in = ap_const_logic_1)))) then 
+                    dst_V_1_state <= ap_const_lv2_3;
+                else 
+                    dst_V_1_state <= ap_const_lv2_2;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    i6_0_i_i_i_reg_156_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                i6_0_i_i_i_reg_156 <= i6_0_i_i_i_mid2_fu_317_p3;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                i6_0_i_i_i_reg_156 <= ap_const_lv10_0;
+            end if; 
+        end if;
+    end process;
+
+    indvar_flatten_reg_145_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                indvar_flatten_reg_145 <= indvar_flatten_next_fu_252_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                indvar_flatten_reg_145 <= ap_const_lv64_0;
+            end if; 
+        end if;
+    end process;
+
+    j_0_i_i_i_reg_167_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                j_0_i_i_i_reg_167 <= j_fu_340_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                j_0_i_i_i_reg_167 <= ap_const_lv10_0;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
+                bound_reg_494 <= bound_fu_199_p2;
+                tmp_7_i_i_reg_488 <= tmp_7_i_i_fu_188_p2;
+                tmp_9_i_i_reg_478 <= tmp_9_i_i_fu_178_p2;
+                tmp_i_i_reg_483 <= tmp_i_i_fu_183_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                brmerge_mid2_reg_516 <= brmerge_mid2_fu_305_p3;
+                j_0_i_i_i_mid2_reg_508 <= j_0_i_i_i_mid2_fu_268_p3;
+                tmp_30_i_i_reg_534 <= tmp_30_i_i_fu_335_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                brmerge_mid2_reg_516_pp0_iter1_reg <= brmerge_mid2_reg_516;
+                exitcond_flatten_reg_499 <= exitcond_flatten_fu_247_p2;
+                exitcond_flatten_reg_499_pp0_iter1_reg <= exitcond_flatten_reg_499;
+                tmp_28_i_i_reg_529_pp0_iter1_reg <= tmp_28_i_i_reg_529;
+                tmp_30_i_i_reg_534_pp0_iter1_reg <= tmp_30_i_i_reg_534;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((dst_V_1_load_A = ap_const_logic_1)) then
+                dst_V_1_payload_A <= pix_out_8_fu_431_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((dst_V_1_load_B = ap_const_logic_1)) then
+                dst_V_1_payload_B <= pix_out_8_fu_431_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
+                exitcond_flatten_reg_499_pp0_iter2_reg <= exitcond_flatten_reg_499_pp0_iter1_reg;
+                exitcond_flatten_reg_499_pp0_iter3_reg <= exitcond_flatten_reg_499_pp0_iter2_reg;
+                tmp_29_i_i_reg_549_pp0_iter2_reg <= tmp_29_i_i_reg_549;
+                tmp_30_i_i_reg_534_pp0_iter2_reg <= tmp_30_i_i_reg_534_pp0_iter1_reg;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                height_read_reg_467 <= height_dout;
+                vconv_xlim_loc_read_reg_473 <= vconv_xlim_loc_dout;
+                width_read_reg_459 <= width_dout;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((brmerge_mid2_reg_516_pp0_iter1_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
+                pix_out_1_fu_82 <= pix_in_2_l_edge_pix_s_fu_384_p3;
+                pix_out_fu_78 <= l_edge_pix_fu_391_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_reg_499_pp0_iter1_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
+                pix_out_7_reg_560 <= borderbuf_q1;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                r_edge_pix_fu_74 <= vconv_V_dout;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((brmerge_mid2_fu_305_p3 = ap_const_lv1_1) and (exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                tmp_24_i_i_reg_525 <= tmp_24_i_i_fu_325_p2;
+                tmp_28_i_i_reg_529 <= tmp_28_i_i_fu_330_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                tmp_27_i_i_reg_544 <= tmp_27_i_i_fu_355_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_reg_499 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                tmp_29_i_i_reg_549 <= tmp_29_i_i_fu_360_p2;
+            end if;
+        end if;
+    end process;
+
+    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, width_empty_n, height_empty_n, dst_V_1_ack_in, vconv_xlim_loc_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, exitcond_flatten_fu_247_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_CS_fsm_state8)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+            when ap_ST_fsm_pp0_stage0 => 
+                if ((not(((exitcond_flatten_fu_247_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) and not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                elsif ((((exitcond_flatten_fu_247_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state8;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                end if;
+            when ap_ST_fsm_state8 => 
+                if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state8;
+                end if;
+            when others =>  
+                ap_NS_fsm <= "XXXX";
+        end case;
+    end process;
+    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state8 <= ap_CS_fsm(3);
+        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage0_01001_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4)
+    begin
+                ap_block_pp0_stage0_01001 <= ((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
+    end process;
+
+
+    ap_block_pp0_stage0_11001_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_state6_io, ap_block_state7_io)
+    begin
+                ap_block_pp0_stage0_11001 <= (((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state7_io) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state6_io) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)));
+    end process;
+
+
+    ap_block_pp0_stage0_subdone_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_state6_io, ap_block_state7_io)
+    begin
+                ap_block_pp0_stage0_subdone <= (((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state7_io) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state6_io) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)));
+    end process;
+
+
+    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
+    begin
+                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
+    end process;
+
+        ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state4_pp0_stage0_iter1_assign_proc : process(vconv_V_empty_n, ap_predicate_op59_read_state4)
+    begin
+                ap_block_state4_pp0_stage0_iter1 <= ((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1));
+    end process;
+
+        ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state6_io_assign_proc : process(dst_V_1_ack_in, exitcond_flatten_reg_499_pp0_iter2_reg)
+    begin
+                ap_block_state6_io <= ((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (dst_V_1_ack_in = ap_const_logic_0));
+    end process;
+
+        ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state7_io_assign_proc : process(dst_V_1_ack_in, exitcond_flatten_reg_499_pp0_iter3_reg)
+    begin
+                ap_block_state7_io <= ((exitcond_flatten_reg_499_pp0_iter3_reg = ap_const_lv1_0) and (dst_V_1_ack_in = ap_const_logic_0));
+    end process;
+
+        ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_flatten_fu_247_p2)
+    begin
+        if ((exitcond_flatten_fu_247_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
+        else 
+            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_done_assign_proc : process(ap_done_reg, dst_V_1_ack_in, ap_CS_fsm_state8)
+    begin
+        if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_done_reg;
+        end if; 
+    end process;
+
+    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
+
+    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
+    begin
+        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2)
+    begin
+        if (((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0))) then 
+            ap_idle_pp0 <= ap_const_logic_1;
+        else 
+            ap_idle_pp0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_predicate_op59_read_state4_assign_proc : process(brmerge_mid2_reg_516, tmp_24_i_i_reg_525)
+    begin
+                ap_predicate_op59_read_state4 <= ((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1));
+    end process;
+
+
+    ap_ready_assign_proc : process(dst_V_1_ack_in, ap_CS_fsm_state8)
+    begin
+        if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
+            ap_ready <= ap_const_logic_1;
+        else 
+            ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    borderbuf_address0 <= tmp_26_i_i_fu_346_p1(10 - 1 downto 0);
+    borderbuf_address1 <= tmp_32_i_i_fu_370_p1(10 - 1 downto 0);
+
+    borderbuf_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            borderbuf_ce0 <= ap_const_logic_1;
+        else 
+            borderbuf_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    borderbuf_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            borderbuf_ce1 <= ap_const_logic_1;
+        else 
+            borderbuf_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    borderbuf_we0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, brmerge_mid2_reg_516, tmp_24_i_i_reg_525, ap_block_pp0_stage0_11001)
+    begin
+        if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            borderbuf_we0 <= ap_const_logic_1;
+        else 
+            borderbuf_we0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    bound_fu_199_p0 <= bound_fu_199_p00(32 - 1 downto 0);
+    bound_fu_199_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(width_read_reg_459),64));
+    bound_fu_199_p1 <= bound_fu_199_p10(32 - 1 downto 0);
+    bound_fu_199_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(height_read_reg_467),64));
+    bound_fu_199_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_199_p0) * unsigned(bound_fu_199_p1), 64));
+    brmerge_fu_232_p2 <= (tmp_17_i_i_fu_209_p2 or brmerge_i_i_i_not_fu_226_p2);
+    brmerge_i_i_i_not_fu_226_p2 <= (notrhs_fu_221_p2 and notlhs_fu_215_p2);
+    brmerge_i_i_i_not_mi_fu_293_p2 <= (notrhs_mid1_fu_288_p2 and notlhs_mid1_fu_282_p2);
+    brmerge_mid1_fu_299_p2 <= (tmp_17_i_i_mid1_fu_276_p2 or brmerge_i_i_i_not_mi_fu_293_p2);
+    brmerge_mid2_fu_305_p3 <= 
+        brmerge_fu_232_p2 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
+        brmerge_mid1_fu_299_p2;
+    dst_V_1_ack_in <= dst_V_1_state(1);
+    dst_V_1_ack_out <= dst_V_TREADY;
+
+    dst_V_1_data_out_assign_proc : process(dst_V_1_payload_A, dst_V_1_payload_B, dst_V_1_sel)
+    begin
+        if ((dst_V_1_sel = ap_const_logic_1)) then 
+            dst_V_1_data_out <= dst_V_1_payload_B;
+        else 
+            dst_V_1_data_out <= dst_V_1_payload_A;
+        end if; 
+    end process;
+
+    dst_V_1_load_A <= (not(dst_V_1_sel_wr) and dst_V_1_state_cmp_full);
+    dst_V_1_load_B <= (dst_V_1_state_cmp_full and dst_V_1_sel_wr);
+    dst_V_1_sel <= dst_V_1_sel_rd;
+    dst_V_1_state_cmp_full <= '0' when (dst_V_1_state = ap_const_lv2_1) else '1';
+
+    dst_V_1_vld_in_assign_proc : process(ap_enable_reg_pp0_iter3, exitcond_flatten_reg_499_pp0_iter2_reg, ap_block_pp0_stage0_11001)
+    begin
+        if (((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1))) then 
+            dst_V_1_vld_in <= ap_const_logic_1;
+        else 
+            dst_V_1_vld_in <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    dst_V_1_vld_out <= dst_V_1_state(0);
+    dst_V_TDATA <= dst_V_1_data_out;
+
+    dst_V_TDATA_blk_n_assign_proc : process(dst_V_1_state, ap_enable_reg_pp0_iter3, ap_block_pp0_stage0, exitcond_flatten_reg_499_pp0_iter2_reg, ap_enable_reg_pp0_iter4, exitcond_flatten_reg_499_pp0_iter3_reg)
+    begin
+        if ((((exitcond_flatten_reg_499_pp0_iter3_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)))) then 
+            dst_V_TDATA_blk_n <= dst_V_1_state(1);
+        else 
+            dst_V_TDATA_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    dst_V_TVALID <= dst_V_1_state(0);
+    exitcond_flatten_fu_247_p2 <= "1" when (indvar_flatten_reg_145 = bound_reg_494) else "0";
+
+    height_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_blk_n <= height_empty_n;
+        else 
+            height_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    height_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_read <= ap_const_logic_1;
+        else 
+            height_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    i6_0_i_cast_i_i_fu_264_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_fu_258_p2),32));
+    i6_0_i_cast_i_i_mid1_fu_205_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i6_0_i_i_i_reg_156),32));
+    i6_0_i_i_i_mid2_fu_317_p3 <= 
+        i6_0_i_i_i_reg_156 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
+        i_fu_258_p2;
+    i_fu_258_p2 <= std_logic_vector(unsigned(i6_0_i_i_i_reg_156) + unsigned(ap_const_lv10_1));
+    indvar_flatten_next_fu_252_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_145) + unsigned(ap_const_lv64_1));
+    j_0_i_cast_i_i_fu_238_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_reg_167),32));
+    j_0_i_cast_i_i_mid2_s_fu_313_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_mid2_fu_268_p3),32));
+    j_0_i_i_i_mid2_fu_268_p3 <= 
+        j_0_i_i_i_reg_167 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
+        ap_const_lv10_0;
+    j_fu_340_p2 <= std_logic_vector(unsigned(j_0_i_i_i_mid2_fu_268_p3) + unsigned(ap_const_lv10_1));
+    l_edge_pix_fu_391_p3 <= 
+        r_edge_pix_fu_74 when (tmp_28_i_i_reg_529_pp0_iter1_reg(0) = '1') else 
+        pix_out_fu_78;
+    notlhs_fu_215_p2 <= "1" when (unsigned(i6_0_i_i_i_reg_156) > unsigned(ap_const_lv10_5)) else "0";
+    notlhs_mid1_fu_282_p2 <= "1" when (unsigned(i_fu_258_p2) > unsigned(ap_const_lv10_5)) else "0";
+    notrhs_fu_221_p2 <= "1" when (signed(i6_0_i_cast_i_i_mid1_fu_205_p1) < signed(tmp_7_i_i_reg_488)) else "0";
+    notrhs_mid1_fu_288_p2 <= "1" when (signed(i6_0_i_cast_i_i_fu_264_p1) < signed(tmp_7_i_i_reg_488)) else "0";
+    pix_in_2_l_edge_pix_s_fu_384_p3 <= 
+        r_edge_pix_fu_74 when (tmp_27_i_i_reg_544(0) = '1') else 
+        pix_out_1_fu_82;
+    pix_out_3_fu_424_p3 <= 
+        pix_out_7_reg_560 when (sel_tmp1_fu_419_p2(0) = '1') else 
+        pix_out_fu_78;
+    pix_out_8_fu_431_p3 <= 
+        pix_out_1_fu_82 when (tmp_29_i_i_reg_549_pp0_iter2_reg(0) = '1') else 
+        pix_out_3_fu_424_p3;
+    sel_tmp1_fu_419_p2 <= (tmp_30_i_i_reg_534_pp0_iter2_reg and sel_tmp_fu_414_p2);
+    sel_tmp_fu_414_p2 <= (tmp_29_i_i_reg_549_pp0_iter2_reg xor ap_const_lv1_1);
+    tmp_17_i_i_fu_209_p2 <= "1" when (i6_0_i_i_i_reg_156 = ap_const_lv10_0) else "0";
+    tmp_17_i_i_mid1_fu_276_p2 <= "1" when (i_fu_258_p2 = ap_const_lv10_0) else "0";
+    tmp_22_i_i_fu_242_p2 <= "1" when (signed(j_0_i_cast_i_i_fu_238_p1) < signed(width_read_reg_459)) else "0";
+    tmp_24_i_i_fu_325_p2 <= "1" when (signed(j_0_i_cast_i_i_mid2_s_fu_313_p1) < signed(vconv_xlim_loc_read_reg_473)) else "0";
+    tmp_26_i_i_fu_346_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_mid2_reg_508),64));
+    tmp_27_i_i_fu_355_p2 <= "1" when (j_0_i_i_i_mid2_reg_508 = ap_const_lv10_0) else "0";
+    tmp_28_i_i_fu_330_p2 <= "1" when (j_0_i_cast_i_i_mid2_s_fu_313_p1 = tmp_9_i_i_reg_478) else "0";
+    tmp_29_i_i_fu_360_p2 <= "1" when (unsigned(j_0_i_i_i_mid2_reg_508) < unsigned(ap_const_lv10_6)) else "0";
+    tmp_30_i_i_fu_335_p2 <= "1" when (signed(j_0_i_cast_i_i_mid2_s_fu_313_p1) < signed(tmp_i_i_reg_483)) else "0";
+    tmp_31_i_i_fu_365_p2 <= std_logic_vector(unsigned(j_0_i_i_i_mid2_reg_508) + unsigned(ap_const_lv10_3FB));
+    tmp_32_i_i_fu_370_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_31_i_i_fu_365_p2),64));
+    tmp_7_i_i_fu_188_p2 <= std_logic_vector(unsigned(height_read_reg_467) + unsigned(ap_const_lv32_FFFFFFFB));
+    tmp_9_i_i_fu_178_p2 <= std_logic_vector(unsigned(width_read_reg_459) + unsigned(ap_const_lv32_FFFFFFF5));
+    tmp_i_i_fu_183_p2 <= std_logic_vector(unsigned(width_read_reg_459) + unsigned(ap_const_lv32_FFFFFFFA));
+
+    vconv_V_blk_n_assign_proc : process(vconv_V_empty_n, ap_block_pp0_stage0, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, brmerge_mid2_reg_516, tmp_24_i_i_reg_525)
+    begin
+        if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
+            vconv_V_blk_n <= vconv_V_empty_n;
+        else 
+            vconv_V_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    vconv_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            vconv_V_read <= ap_const_logic_1;
+        else 
+            vconv_V_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    vconv_xlim_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            vconv_xlim_loc_blk_n <= vconv_xlim_loc_empty_n;
+        else 
+            vconv_xlim_loc_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    vconv_xlim_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            vconv_xlim_loc_read <= ap_const_logic_1;
+        else 
+            vconv_xlim_loc_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    width_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_blk_n <= width_empty_n;
+        else 
+            width_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    width_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_read <= ap_const_logic_1;
+        else 
+            width_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+end behav;

ip_repo_sources/src/Loop_Border_proc_borderbuf.vhd

@@ -0,0 +1,132 @@
+-- ==============================================================
+-- File generated on Wed Jun 26 16:53:30 CEST 2019
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
+-- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
+-- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
+-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity Loop_Border_proc_borderbuf_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 10; 
+            MEM_SIZE    : integer := 662
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          d0        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we0       : in std_logic; 
+          addr1     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce1       : in std_logic; 
+          q1        : out std_logic_vector(DWIDTH-1 downto 0);
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of Loop_Border_proc_borderbuf_ram is 
+
+signal addr1_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array;
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            if (we0 = '1') then 
+                ram(CONV_INTEGER(addr0)) := d0; 
+            end if;
+        end if;
+    end if;
+end process;
+
+memory_access_guard_1: process (addr1) 
+begin
+      addr1_tmp <= addr1;
+--synthesis translate_off
+      if (CONV_INTEGER(addr1) > mem_size-1) then
+           addr1_tmp <= (others => '0');
+      else 
+           addr1_tmp <= addr1;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_1: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce1 = '1') then 
+            q1 <= ram(CONV_INTEGER(addr1_tmp)); 
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity Loop_Border_proc_borderbuf is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 662;
+        AddressWidth : INTEGER := 10);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce1 : IN STD_LOGIC;
+        q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of Loop_Border_proc_borderbuf is
+    component Loop_Border_proc_borderbuf_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            we0 : IN STD_LOGIC;
+            d0 : IN STD_LOGIC_VECTOR;
+            addr1 : IN STD_LOGIC_VECTOR;
+            ce1 : IN STD_LOGIC;
+            q1 : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    Loop_Border_proc_borderbuf_ram_U :  component Loop_Border_proc_borderbuf_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        we0 => we0,
+        d0 => d0,
+        addr1 => address1,
+        ce1 => ce1,
+        q1 => q1);
+
+end architecture;
+
+

ip_repo_sources/src/Loop_HConvH_proc6.vhd

@@ -0,0 +1,746 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+-- Version: 2018.3
+-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity Loop_HConvH_proc6 is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    height_empty_n : IN STD_LOGIC;
+    height_read : OUT STD_LOGIC;
+    width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    width_empty_n : IN STD_LOGIC;
+    width_read : OUT STD_LOGIC;
+    src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
+    src_V_TVALID : IN STD_LOGIC;
+    src_V_TREADY : OUT STD_LOGIC;
+    filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    filt1_empty_n : IN STD_LOGIC;
+    filt1_read : OUT STD_LOGIC;
+    filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    filt2_empty_n : IN STD_LOGIC;
+    filt2_read : OUT STD_LOGIC;
+    hconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    hconv_V_full_n : IN STD_LOGIC;
+    hconv_V_write : OUT STD_LOGIC );
+end;
+
+
+architecture behav of Loop_HConvH_proc6 is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
+    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
+    constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
+    constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
+    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
+    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
+    constant ap_const_lv10_9 : STD_LOGIC_VECTOR (9 downto 0) := "0000001001";
+    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
+    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
+
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal src_V_0_data_out : STD_LOGIC_VECTOR (31 downto 0);
+    signal src_V_0_vld_in : STD_LOGIC;
+    signal src_V_0_vld_out : STD_LOGIC;
+    signal src_V_0_ack_in : STD_LOGIC;
+    signal src_V_0_ack_out : STD_LOGIC;
+    signal src_V_0_payload_A : STD_LOGIC_VECTOR (31 downto 0);
+    signal src_V_0_payload_B : STD_LOGIC_VECTOR (31 downto 0);
+    signal src_V_0_sel_rd : STD_LOGIC := '0';
+    signal src_V_0_sel_wr : STD_LOGIC := '0';
+    signal src_V_0_sel : STD_LOGIC;
+    signal src_V_0_load_A : STD_LOGIC;
+    signal src_V_0_load_B : STD_LOGIC;
+    signal src_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
+    signal src_V_0_state_cmp_full : STD_LOGIC;
+    signal height_blk_n : STD_LOGIC;
+    signal width_blk_n : STD_LOGIC;
+    signal src_V_TDATA_blk_n : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
+    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0 : BOOLEAN;
+    signal exitcond_flatten_fu_214_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal filt1_blk_n : STD_LOGIC;
+    signal filt2_blk_n : STD_LOGIC;
+    signal hconv_V_blk_n : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
+    signal tmp_10_i_reg_491 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_10_i_reg_491_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal indvar_flatten_reg_141 : STD_LOGIC_VECTOR (63 downto 0);
+    signal row_0_i_i_reg_152 : STD_LOGIC_VECTOR (9 downto 0);
+    signal height_read_reg_421 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state1 : BOOLEAN;
+    signal width_read_reg_426 : STD_LOGIC_VECTOR (31 downto 0);
+    signal filt1_read_reg_432 : STD_LOGIC_VECTOR (31 downto 0);
+    signal filt2_read_reg_437 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_169_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound_reg_442 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal hwin_5_load_reg_447 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
+    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
+    signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
+    signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
+    signal ap_block_pp0_stage0_11001 : BOOLEAN;
+    signal hwin_5_load_reg_447_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_8_load_reg_452 : STD_LOGIC_VECTOR (31 downto 0);
+    signal exitcond_flatten_reg_457 : STD_LOGIC_VECTOR (0 downto 0);
+    signal exitcond_flatten_reg_457_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal indvar_flatten_next_fu_219_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal tmp_23_9_i_fu_281_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_23_9_i_reg_466 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_23_i_fu_286_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_23_i_reg_471 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_fu_291_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_reg_476 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_reg_476_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_reg_476_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_fu_303_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_reg_481 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_reg_481_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_reg_481_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp7_fu_309_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp7_reg_486 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp7_reg_486_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_10_i_fu_315_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_10_i_reg_491_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal row_fu_326_p2 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp8_fu_336_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp8_reg_500 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp5_fu_345_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp5_reg_505 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_pp0_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0_01001 : BOOLEAN;
+    signal hwin_1_1_i_fu_64 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_1_fu_68 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_2_fu_72 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_3_fu_76 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_4_fu_80 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_5_fu_84 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_6_fu_88 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_7_fu_92 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_8_fu_96 : STD_LOGIC_VECTOR (31 downto 0);
+    signal hwin_9_fu_100 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_169_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_169_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal row_0_i_cast_i_fu_205_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_4_i_fu_209_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_23_9_i_fu_281_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_23_i_fu_286_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp4_fu_297_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal row_0_i_i_mid2_fu_273_p3 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp9_fu_332_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp6_fu_341_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp1_fu_350_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state7 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
+    signal ap_idle_pp0 : STD_LOGIC;
+    signal ap_enable_pp0 : STD_LOGIC;
+    signal bound_fu_169_p00 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound_fu_169_p10 : STD_LOGIC_VECTOR (63 downto 0);
+
+
+begin
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then 
+                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                    ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    src_V_0_sel_rd_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                src_V_0_sel_rd <= ap_const_logic_0;
+            else
+                if (((src_V_0_ack_out = ap_const_logic_1) and (src_V_0_vld_out = ap_const_logic_1))) then 
+                                        src_V_0_sel_rd <= not(src_V_0_sel_rd);
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    src_V_0_sel_wr_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                src_V_0_sel_wr <= ap_const_logic_0;
+            else
+                if (((src_V_0_ack_in = ap_const_logic_1) and (src_V_0_vld_in = ap_const_logic_1))) then 
+                                        src_V_0_sel_wr <= not(src_V_0_sel_wr);
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    src_V_0_state_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                src_V_0_state <= ap_const_lv2_0;
+            else
+                if ((((src_V_0_state = ap_const_lv2_2) and (src_V_0_vld_in = ap_const_logic_0)) or ((src_V_0_state = ap_const_lv2_3) and (src_V_0_vld_in = ap_const_logic_0) and (src_V_0_ack_out = ap_const_logic_1)))) then 
+                    src_V_0_state <= ap_const_lv2_2;
+                elsif ((((src_V_0_state = ap_const_lv2_1) and (src_V_0_ack_out = ap_const_logic_0)) or ((src_V_0_state = ap_const_lv2_3) and (src_V_0_ack_out = ap_const_logic_0) and (src_V_0_vld_in = ap_const_logic_1)))) then 
+                    src_V_0_state <= ap_const_lv2_1;
+                elsif (((not(((src_V_0_vld_in = ap_const_logic_0) and (src_V_0_ack_out = ap_const_logic_1))) and not(((src_V_0_ack_out = ap_const_logic_0) and (src_V_0_vld_in = ap_const_logic_1))) and (src_V_0_state = ap_const_lv2_3)) or ((src_V_0_state = ap_const_lv2_1) and (src_V_0_ack_out = ap_const_logic_1)) or ((src_V_0_state = ap_const_lv2_2) and (src_V_0_vld_in = ap_const_logic_1)))) then 
+                    src_V_0_state <= ap_const_lv2_3;
+                else 
+                    src_V_0_state <= ap_const_lv2_2;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    indvar_flatten_reg_141_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
+                indvar_flatten_reg_141 <= indvar_flatten_next_fu_219_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                indvar_flatten_reg_141 <= ap_const_lv64_0;
+            end if; 
+        end if;
+    end process;
+
+    row_0_i_i_reg_152_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
+                row_0_i_i_reg_152 <= row_fu_326_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                row_0_i_i_reg_152 <= ap_const_lv10_0;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
+                bound_reg_442 <= bound_fu_169_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
+                exitcond_flatten_reg_457 <= exitcond_flatten_fu_214_p2;
+                exitcond_flatten_reg_457_pp0_iter1_reg <= exitcond_flatten_reg_457;
+                hwin_5_load_reg_447 <= hwin_5_fu_84;
+                hwin_5_load_reg_447_pp0_iter1_reg <= hwin_5_load_reg_447;
+                hwin_8_load_reg_452 <= hwin_8_fu_96;
+                tmp2_reg_476_pp0_iter1_reg <= tmp2_reg_476;
+                tmp3_reg_481_pp0_iter1_reg <= tmp3_reg_481;
+                tmp7_reg_486_pp0_iter1_reg <= tmp7_reg_486;
+                tmp_10_i_reg_491_pp0_iter1_reg <= tmp_10_i_reg_491;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                filt1_read_reg_432 <= filt1_dout;
+                filt2_read_reg_437 <= filt2_dout;
+                height_read_reg_421 <= height_dout;
+                width_read_reg_426 <= width_dout;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
+                hwin_1_1_i_fu_64 <= hwin_1_fu_68;
+                hwin_1_fu_68 <= hwin_2_fu_72;
+                hwin_2_fu_72 <= hwin_3_fu_76;
+                hwin_3_fu_76 <= hwin_4_fu_80;
+                hwin_4_fu_80 <= hwin_5_fu_84;
+                hwin_5_fu_84 <= hwin_6_fu_88;
+                hwin_6_fu_88 <= hwin_7_fu_92;
+                hwin_7_fu_92 <= hwin_8_fu_96;
+                hwin_8_fu_96 <= hwin_9_fu_100;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
+                hwin_9_fu_100 <= src_V_0_data_out;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((src_V_0_load_A = ap_const_logic_1)) then
+                src_V_0_payload_A <= src_V_TDATA;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((src_V_0_load_B = ap_const_logic_1)) then
+                src_V_0_payload_B <= src_V_TDATA;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
+                tmp2_reg_476 <= tmp2_fu_291_p2;
+                tmp3_reg_481 <= tmp3_fu_303_p2;
+                tmp7_reg_486 <= tmp7_fu_309_p2;
+                tmp_10_i_reg_491 <= tmp_10_i_fu_315_p2;
+                tmp_23_9_i_reg_466 <= tmp_23_9_i_fu_281_p2;
+                tmp_23_i_reg_471 <= tmp_23_i_fu_286_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
+                tmp2_reg_476_pp0_iter2_reg <= tmp2_reg_476_pp0_iter1_reg;
+                tmp3_reg_481_pp0_iter2_reg <= tmp3_reg_481_pp0_iter1_reg;
+                tmp_10_i_reg_491_pp0_iter2_reg <= tmp_10_i_reg_491_pp0_iter1_reg;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_reg_457_pp0_iter1_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
+                tmp5_reg_505 <= tmp5_fu_345_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((exitcond_flatten_reg_457 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
+                tmp8_reg_500 <= tmp8_fu_336_p2;
+            end if;
+        end if;
+    end process;
+
+    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+            when ap_ST_fsm_pp0_stage0 => 
+                if ((not(((exitcond_flatten_fu_214_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) and not(((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                elsif ((((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state7;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                end if;
+            when ap_ST_fsm_state7 => 
+                ap_NS_fsm <= ap_ST_fsm_state1;
+            when others =>  
+                ap_NS_fsm <= "XXXX";
+        end case;
+    end process;
+    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state7 <= ap_CS_fsm(3);
+        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage0_01001_assign_proc : process(src_V_0_vld_out, hconv_V_full_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
+    begin
+                ap_block_pp0_stage0_01001 <= (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)));
+    end process;
+
+
+    ap_block_pp0_stage0_11001_assign_proc : process(src_V_0_vld_out, hconv_V_full_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
+    begin
+                ap_block_pp0_stage0_11001 <= (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)));
+    end process;
+
+
+    ap_block_pp0_stage0_subdone_assign_proc : process(src_V_0_vld_out, hconv_V_full_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
+    begin
+                ap_block_pp0_stage0_subdone <= (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)));
+    end process;
+
+
+    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
+    begin
+                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
+    end process;
+
+
+    ap_block_state3_pp0_stage0_iter0_assign_proc : process(src_V_0_vld_out, exitcond_flatten_fu_214_p2)
+    begin
+                ap_block_state3_pp0_stage0_iter0 <= ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0));
+    end process;
+
+        ap_block_state4_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state6_pp0_stage0_iter3_assign_proc : process(hconv_V_full_n, tmp_10_i_reg_491_pp0_iter2_reg)
+    begin
+                ap_block_state6_pp0_stage0_iter3 <= ((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0));
+    end process;
+
+
+    ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_flatten_fu_214_p2)
+    begin
+        if ((exitcond_flatten_fu_214_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
+        else 
+            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state7)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_done_reg;
+        end if; 
+    end process;
+
+    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
+
+    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
+    begin
+        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
+    begin
+        if (((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then 
+            ap_idle_pp0 <= ap_const_logic_1;
+        else 
+            ap_idle_pp0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_ready_assign_proc : process(ap_CS_fsm_state7)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
+            ap_ready <= ap_const_logic_1;
+        else 
+            ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    bound_fu_169_p0 <= bound_fu_169_p00(32 - 1 downto 0);
+    bound_fu_169_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(width_read_reg_426),64));
+    bound_fu_169_p1 <= bound_fu_169_p10(32 - 1 downto 0);
+    bound_fu_169_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(height_read_reg_421),64));
+    bound_fu_169_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_169_p0) * unsigned(bound_fu_169_p1), 64));
+    exitcond_flatten_fu_214_p2 <= "1" when (indvar_flatten_reg_141 = bound_reg_442) else "0";
+
+    filt1_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt1_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt1_blk_n <= filt1_empty_n;
+        else 
+            filt1_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    filt1_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt1_read <= ap_const_logic_1;
+        else 
+            filt1_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    filt2_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt2_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt2_blk_n <= filt2_empty_n;
+        else 
+            filt2_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    filt2_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt2_read <= ap_const_logic_1;
+        else 
+            filt2_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    hconv_V_blk_n_assign_proc : process(hconv_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
+    begin
+        if (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
+            hconv_V_blk_n <= hconv_V_full_n;
+        else 
+            hconv_V_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    hconv_V_din <= std_logic_vector(unsigned(tmp5_reg_505) + unsigned(tmp1_fu_350_p2));
+
+    hconv_V_write_assign_proc : process(ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg, ap_block_pp0_stage0_11001)
+    begin
+        if (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
+            hconv_V_write <= ap_const_logic_1;
+        else 
+            hconv_V_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    height_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_blk_n <= height_empty_n;
+        else 
+            height_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    height_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_read <= ap_const_logic_1;
+        else 
+            height_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    indvar_flatten_next_fu_219_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_141) + unsigned(ap_const_lv64_1));
+    row_0_i_cast_i_fu_205_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_0_i_i_reg_152),32));
+    row_0_i_i_mid2_fu_273_p3 <= 
+        row_0_i_i_reg_152 when (tmp_4_i_fu_209_p2(0) = '1') else 
+        ap_const_lv10_0;
+    row_fu_326_p2 <= std_logic_vector(unsigned(row_0_i_i_mid2_fu_273_p3) + unsigned(ap_const_lv10_1));
+    src_V_0_ack_in <= src_V_0_state(1);
+
+    src_V_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_block_pp0_stage0_11001)
+    begin
+        if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
+            src_V_0_ack_out <= ap_const_logic_1;
+        else 
+            src_V_0_ack_out <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    src_V_0_data_out_assign_proc : process(src_V_0_payload_A, src_V_0_payload_B, src_V_0_sel)
+    begin
+        if ((src_V_0_sel = ap_const_logic_1)) then 
+            src_V_0_data_out <= src_V_0_payload_B;
+        else 
+            src_V_0_data_out <= src_V_0_payload_A;
+        end if; 
+    end process;
+
+    src_V_0_load_A <= (src_V_0_state_cmp_full and not(src_V_0_sel_wr));
+    src_V_0_load_B <= (src_V_0_state_cmp_full and src_V_0_sel_wr);
+    src_V_0_sel <= src_V_0_sel_rd;
+    src_V_0_state_cmp_full <= '0' when (src_V_0_state = ap_const_lv2_1) else '1';
+    src_V_0_vld_in <= src_V_TVALID;
+    src_V_0_vld_out <= src_V_0_state(0);
+
+    src_V_TDATA_blk_n_assign_proc : process(src_V_0_state, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0, exitcond_flatten_fu_214_p2)
+    begin
+        if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
+            src_V_TDATA_blk_n <= src_V_0_state(0);
+        else 
+            src_V_TDATA_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    src_V_TREADY <= src_V_0_state(1);
+    tmp1_fu_350_p2 <= std_logic_vector(unsigned(tmp3_reg_481_pp0_iter2_reg) + unsigned(tmp2_reg_476_pp0_iter2_reg));
+    tmp2_fu_291_p2 <= std_logic_vector(unsigned(hwin_1_1_i_fu_64) + unsigned(hwin_1_fu_68));
+    tmp3_fu_303_p2 <= std_logic_vector(unsigned(tmp4_fu_297_p2) + unsigned(hwin_2_fu_72));
+    tmp4_fu_297_p2 <= std_logic_vector(unsigned(hwin_3_fu_76) + unsigned(hwin_4_fu_80));
+    tmp5_fu_345_p2 <= std_logic_vector(unsigned(tmp8_reg_500) + unsigned(tmp6_fu_341_p2));
+    tmp6_fu_341_p2 <= std_logic_vector(unsigned(tmp7_reg_486_pp0_iter1_reg) + unsigned(hwin_5_load_reg_447_pp0_iter1_reg));
+    tmp7_fu_309_p2 <= std_logic_vector(unsigned(hwin_6_fu_88) + unsigned(hwin_7_fu_92));
+    tmp8_fu_336_p2 <= std_logic_vector(unsigned(tmp9_fu_332_p2) + unsigned(hwin_8_load_reg_452));
+    tmp9_fu_332_p2 <= std_logic_vector(unsigned(tmp_23_9_i_reg_466) + unsigned(tmp_23_i_reg_471));
+    tmp_10_i_fu_315_p2 <= "1" when (unsigned(row_0_i_i_mid2_fu_273_p3) > unsigned(ap_const_lv10_9)) else "0";
+    tmp_23_9_i_fu_281_p1 <= hwin_9_fu_100;
+    tmp_23_9_i_fu_281_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt1_read_reg_432) * signed(tmp_23_9_i_fu_281_p1))), 32));
+    tmp_23_i_fu_286_p1 <= src_V_0_data_out;
+    tmp_23_i_fu_286_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt2_read_reg_437) * signed(tmp_23_i_fu_286_p1))), 32));
+    tmp_4_i_fu_209_p2 <= "1" when (signed(row_0_i_cast_i_fu_205_p1) < signed(width_read_reg_426)) else "0";
+
+    width_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_blk_n <= width_empty_n;
+        else 
+            width_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    width_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            width_read <= ap_const_logic_1;
+        else 
+            width_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+end behav;

ip_repo_sources/src/Loop_VConvH_proc.vhd

@@ -0,0 +1,1570 @@
+-- ==============================================================
+-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
+-- Version: 2018.3
+-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
+-- 
+-- ===========================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity Loop_VConvH_proc is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    height_empty_n : IN STD_LOGIC;
+    height_read : OUT STD_LOGIC;
+    vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    vconv_xlim_loc_empty_n : IN STD_LOGIC;
+    vconv_xlim_loc_read : OUT STD_LOGIC;
+    hconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    hconv_V_empty_n : IN STD_LOGIC;
+    hconv_V_read : OUT STD_LOGIC;
+    vconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    vconv_V_full_n : IN STD_LOGIC;
+    vconv_V_write : OUT STD_LOGIC;
+    filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    filt1_empty_n : IN STD_LOGIC;
+    filt1_read : OUT STD_LOGIC;
+    filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
+    filt2_empty_n : IN STD_LOGIC;
+    filt2_read : OUT STD_LOGIC;
+    height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    height_out_full_n : IN STD_LOGIC;
+    height_out_write : OUT STD_LOGIC;
+    vconv_xlim_loc_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
+    vconv_xlim_loc_out_full_n : IN STD_LOGIC;
+    vconv_xlim_loc_out_write : OUT STD_LOGIC );
+end;
+
+
+architecture behav of Loop_VConvH_proc is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
+    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
+    constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
+    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
+    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
+    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
+    constant ap_const_lv10_9 : STD_LOGIC_VECTOR (9 downto 0) := "0000001001";
+    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
+
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal linebuf_0_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_0_ce0 : STD_LOGIC;
+    signal linebuf_0_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_0_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_0_ce1 : STD_LOGIC;
+    signal linebuf_0_we1 : STD_LOGIC;
+    signal linebuf_1_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_1_ce0 : STD_LOGIC;
+    signal linebuf_1_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_1_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_1_ce1 : STD_LOGIC;
+    signal linebuf_1_we1 : STD_LOGIC;
+    signal linebuf_2_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_2_ce0 : STD_LOGIC;
+    signal linebuf_2_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_2_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_2_ce1 : STD_LOGIC;
+    signal linebuf_2_we1 : STD_LOGIC;
+    signal linebuf_3_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_3_ce0 : STD_LOGIC;
+    signal linebuf_3_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_3_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_3_ce1 : STD_LOGIC;
+    signal linebuf_3_we1 : STD_LOGIC;
+    signal linebuf_4_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_4_ce0 : STD_LOGIC;
+    signal linebuf_4_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_4_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_4_ce1 : STD_LOGIC;
+    signal linebuf_4_we1 : STD_LOGIC;
+    signal linebuf_5_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_5_ce0 : STD_LOGIC;
+    signal linebuf_5_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_5_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_5_ce1 : STD_LOGIC;
+    signal linebuf_5_we1 : STD_LOGIC;
+    signal linebuf_6_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_6_ce0 : STD_LOGIC;
+    signal linebuf_6_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_6_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_6_ce1 : STD_LOGIC;
+    signal linebuf_6_we1 : STD_LOGIC;
+    signal linebuf_7_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_7_ce0 : STD_LOGIC;
+    signal linebuf_7_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_7_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_7_ce1 : STD_LOGIC;
+    signal linebuf_7_we1 : STD_LOGIC;
+    signal linebuf_8_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_8_ce0 : STD_LOGIC;
+    signal linebuf_8_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_8_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_8_ce1 : STD_LOGIC;
+    signal linebuf_8_we1 : STD_LOGIC;
+    signal linebuf_9_address0 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_9_ce0 : STD_LOGIC;
+    signal linebuf_9_q0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_9_address1 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_9_ce1 : STD_LOGIC;
+    signal linebuf_9_we1 : STD_LOGIC;
+    signal height_blk_n : STD_LOGIC;
+    signal vconv_xlim_loc_blk_n : STD_LOGIC;
+    signal hconv_V_blk_n : STD_LOGIC;
+    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
+    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
+    signal ap_block_pp0_stage0 : BOOLEAN;
+    signal exitcond_flatten_reg_532 : STD_LOGIC_VECTOR (0 downto 0);
+    signal vconv_V_blk_n : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
+    signal tmp_8_i_i_mid2_reg_541 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_8_i_i_mid2_reg_541_pp0_iter4_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal filt1_blk_n : STD_LOGIC;
+    signal filt2_blk_n : STD_LOGIC;
+    signal height_out_blk_n : STD_LOGIC;
+    signal vconv_xlim_loc_out_blk_n : STD_LOGIC;
+    signal indvar_flatten_reg_319 : STD_LOGIC_VECTOR (63 downto 0);
+    signal col1_0_i_i_i_reg_330 : STD_LOGIC_VECTOR (9 downto 0);
+    signal row2_0_i_i_i_reg_341 : STD_LOGIC_VECTOR (9 downto 0);
+    signal height_read_reg_506 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_state1 : BOOLEAN;
+    signal vconv_xlim_loc_read_reg_511 : STD_LOGIC_VECTOR (31 downto 0);
+    signal filt1_read_reg_517 : STD_LOGIC_VECTOR (31 downto 0);
+    signal filt2_read_reg_522 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_358_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound_reg_527 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal exitcond_flatten_fu_373_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
+    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
+    signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
+    signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
+    signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
+    signal ap_block_state8_pp0_stage0_iter5 : BOOLEAN;
+    signal ap_block_pp0_stage0_11001 : BOOLEAN;
+    signal exitcond_flatten_reg_532_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal exitcond_flatten_reg_532_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal exitcond_flatten_reg_532_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal indvar_flatten_next_fu_378_p2 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
+    signal tmp_8_i_i_mid2_fu_410_p3 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_8_i_i_mid2_reg_541_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_8_i_i_mid2_reg_541_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_8_i_i_mid2_reg_541_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
+    signal col1_0_i_i_i_mid2_fu_418_p3 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_0_addr_reg_550 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_1_addr_reg_556 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_2_addr_reg_562 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_3_addr_reg_568 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_4_addr_reg_574 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_5_addr_reg_580 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_6_addr_reg_586 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_7_addr_reg_592 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_8_addr_reg_598 : STD_LOGIC_VECTOR (9 downto 0);
+    signal linebuf_9_addr_reg_604 : STD_LOGIC_VECTOR (9 downto 0);
+    signal row_fu_440_p2 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp_1_reg_615 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_5_load_reg_620 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_5_load_reg_620_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_5_load_reg_620_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_8_load_reg_625 : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_8_load_reg_625_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal linebuf_9_load_reg_630 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_fu_446_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_reg_635 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_reg_635_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_reg_635_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp2_reg_635_pp0_iter4_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_fu_458_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_reg_640 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_reg_640_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_reg_640_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp3_reg_640_pp0_iter4_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp7_fu_464_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp7_reg_645 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp7_reg_645_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp7_reg_645_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_30_9_i_i_fu_470_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_30_9_i_i_reg_650 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_30_i_i_fu_474_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_30_i_i_reg_655 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp8_fu_482_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp8_reg_660 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp5_fu_491_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp5_reg_665 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_block_pp0_stage0_subdone : BOOLEAN;
+    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
+    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
+    signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
+    signal tmp_16_i_i_fu_426_p1 : STD_LOGIC_VECTOR (63 downto 0);
+    signal ap_block_pp0_stage0_01001 : BOOLEAN;
+    signal bound_fu_358_p0 : STD_LOGIC_VECTOR (31 downto 0);
+    signal bound_fu_358_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal row2_0_i_cast_i_i_fu_364_p1 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp_11_i_i_fu_368_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal col_fu_392_p2 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp_8_i_i_fu_404_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal tmp_8_i_i_mid1_fu_398_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal row2_0_i_i_i_mid2_fu_384_p3 : STD_LOGIC_VECTOR (9 downto 0);
+    signal tmp4_fu_452_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp9_fu_478_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp6_fu_487_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal tmp1_fu_496_p2 : STD_LOGIC_VECTOR (31 downto 0);
+    signal ap_CS_fsm_state9 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
+    signal ap_block_pp0 : BOOLEAN;
+    signal ap_enable_operation_44 : BOOLEAN;
+    signal ap_enable_state3_pp0_iter0_stage0 : BOOLEAN;
+    signal ap_enable_operation_66 : BOOLEAN;
+    signal ap_enable_state4_pp0_iter1_stage0 : BOOLEAN;
+    signal ap_enable_operation_68 : BOOLEAN;
+    signal ap_enable_operation_46 : BOOLEAN;
+    signal ap_enable_operation_67 : BOOLEAN;
+    signal ap_enable_operation_70 : BOOLEAN;
+    signal ap_enable_operation_48 : BOOLEAN;
+    signal ap_enable_operation_69 : BOOLEAN;
+    signal ap_enable_operation_72 : BOOLEAN;
+    signal ap_enable_operation_50 : BOOLEAN;
+    signal ap_enable_operation_71 : BOOLEAN;
+    signal ap_enable_operation_74 : BOOLEAN;
+    signal ap_enable_operation_52 : BOOLEAN;
+    signal ap_enable_operation_73 : BOOLEAN;
+    signal ap_enable_operation_76 : BOOLEAN;
+    signal ap_enable_operation_54 : BOOLEAN;
+    signal ap_enable_operation_75 : BOOLEAN;
+    signal ap_enable_operation_78 : BOOLEAN;
+    signal ap_enable_operation_56 : BOOLEAN;
+    signal ap_enable_operation_77 : BOOLEAN;
+    signal ap_enable_operation_80 : BOOLEAN;
+    signal ap_enable_operation_58 : BOOLEAN;
+    signal ap_enable_operation_79 : BOOLEAN;
+    signal ap_enable_operation_82 : BOOLEAN;
+    signal ap_enable_operation_60 : BOOLEAN;
+    signal ap_enable_operation_81 : BOOLEAN;
+    signal ap_enable_operation_84 : BOOLEAN;
+    signal ap_enable_operation_62 : BOOLEAN;
+    signal ap_enable_operation_83 : BOOLEAN;
+    signal ap_enable_operation_89 : BOOLEAN;
+    signal ap_idle_pp0 : STD_LOGIC;
+    signal ap_enable_pp0 : STD_LOGIC;
+    signal bound_fu_358_p00 : STD_LOGIC_VECTOR (63 downto 0);
+    signal bound_fu_358_p10 : STD_LOGIC_VECTOR (63 downto 0);
+
+    component Loop_VConvH_proc_linebuf_0 IS
+    generic (
+        DataWidth : INTEGER;
+        AddressRange : INTEGER;
+        AddressWidth : INTEGER );
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR (9 downto 0);
+        ce0 : IN STD_LOGIC;
+        q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
+        address1 : IN STD_LOGIC_VECTOR (9 downto 0);
+        ce1 : IN STD_LOGIC;
+        we1 : IN STD_LOGIC;
+        d1 : IN STD_LOGIC_VECTOR (31 downto 0) );
+    end component;
+
+
+
+begin
+    linebuf_0_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_0_address0,
+        ce0 => linebuf_0_ce0,
+        q0 => linebuf_0_q0,
+        address1 => linebuf_0_address1,
+        ce1 => linebuf_0_ce1,
+        we1 => linebuf_0_we1,
+        d1 => linebuf_1_q0);
+
+    linebuf_1_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_1_address0,
+        ce0 => linebuf_1_ce0,
+        q0 => linebuf_1_q0,
+        address1 => linebuf_1_address1,
+        ce1 => linebuf_1_ce1,
+        we1 => linebuf_1_we1,
+        d1 => linebuf_2_q0);
+
+    linebuf_2_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_2_address0,
+        ce0 => linebuf_2_ce0,
+        q0 => linebuf_2_q0,
+        address1 => linebuf_2_address1,
+        ce1 => linebuf_2_ce1,
+        we1 => linebuf_2_we1,
+        d1 => linebuf_3_q0);
+
+    linebuf_3_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_3_address0,
+        ce0 => linebuf_3_ce0,
+        q0 => linebuf_3_q0,
+        address1 => linebuf_3_address1,
+        ce1 => linebuf_3_ce1,
+        we1 => linebuf_3_we1,
+        d1 => linebuf_4_q0);
+
+    linebuf_4_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_4_address0,
+        ce0 => linebuf_4_ce0,
+        q0 => linebuf_4_q0,
+        address1 => linebuf_4_address1,
+        ce1 => linebuf_4_ce1,
+        we1 => linebuf_4_we1,
+        d1 => linebuf_5_q0);
+
+    linebuf_5_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_5_address0,
+        ce0 => linebuf_5_ce0,
+        q0 => linebuf_5_q0,
+        address1 => linebuf_5_address1,
+        ce1 => linebuf_5_ce1,
+        we1 => linebuf_5_we1,
+        d1 => linebuf_6_q0);
+
+    linebuf_6_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_6_address0,
+        ce0 => linebuf_6_ce0,
+        q0 => linebuf_6_q0,
+        address1 => linebuf_6_address1,
+        ce1 => linebuf_6_ce1,
+        we1 => linebuf_6_we1,
+        d1 => linebuf_7_q0);
+
+    linebuf_7_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_7_address0,
+        ce0 => linebuf_7_ce0,
+        q0 => linebuf_7_q0,
+        address1 => linebuf_7_address1,
+        ce1 => linebuf_7_ce1,
+        we1 => linebuf_7_we1,
+        d1 => linebuf_8_q0);
+
+    linebuf_8_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_8_address0,
+        ce0 => linebuf_8_ce0,
+        q0 => linebuf_8_q0,
+        address1 => linebuf_8_address1,
+        ce1 => linebuf_8_ce1,
+        we1 => linebuf_8_we1,
+        d1 => linebuf_9_q0);
+
+    linebuf_9_U : component Loop_VConvH_proc_linebuf_0
+    generic map (
+        DataWidth => 32,
+        AddressRange => 672,
+        AddressWidth => 10)
+    port map (
+        clk => ap_clk,
+        reset => ap_rst,
+        address0 => linebuf_9_address0,
+        ce0 => linebuf_9_ce0,
+        q0 => linebuf_9_q0,
+        address1 => linebuf_9_address1,
+        ce1 => linebuf_9_ce1,
+        we1 => linebuf_9_we1,
+        d1 => hconv_V_dout);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
+                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then 
+                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
+                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
+                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
+                    end if;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
+            else
+                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
+                    ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
+                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                    ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    col1_0_i_i_i_reg_330_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
+                col1_0_i_i_i_reg_330 <= col1_0_i_i_i_mid2_fu_418_p3;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                col1_0_i_i_i_reg_330 <= ap_const_lv10_0;
+            end if; 
+        end if;
+    end process;
+
+    indvar_flatten_reg_319_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
+                indvar_flatten_reg_319 <= indvar_flatten_next_fu_378_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                indvar_flatten_reg_319 <= ap_const_lv64_0;
+            end if; 
+        end if;
+    end process;
+
+    row2_0_i_i_i_reg_341_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
+                row2_0_i_i_i_reg_341 <= row_fu_440_p2;
+            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+                row2_0_i_i_i_reg_341 <= ap_const_lv10_0;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
+                bound_reg_527 <= bound_fu_358_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
+                exitcond_flatten_reg_532 <= exitcond_flatten_fu_373_p2;
+                exitcond_flatten_reg_532_pp0_iter1_reg <= exitcond_flatten_reg_532;
+                tmp_8_i_i_mid2_reg_541_pp0_iter1_reg <= tmp_8_i_i_mid2_reg_541;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
+                exitcond_flatten_reg_532_pp0_iter2_reg <= exitcond_flatten_reg_532_pp0_iter1_reg;
+                exitcond_flatten_reg_532_pp0_iter3_reg <= exitcond_flatten_reg_532_pp0_iter2_reg;
+                linebuf_5_load_reg_620_pp0_iter2_reg <= linebuf_5_load_reg_620;
+                linebuf_5_load_reg_620_pp0_iter3_reg <= linebuf_5_load_reg_620_pp0_iter2_reg;
+                linebuf_8_load_reg_625_pp0_iter2_reg <= linebuf_8_load_reg_625;
+                tmp2_reg_635_pp0_iter2_reg <= tmp2_reg_635;
+                tmp2_reg_635_pp0_iter3_reg <= tmp2_reg_635_pp0_iter2_reg;
+                tmp2_reg_635_pp0_iter4_reg <= tmp2_reg_635_pp0_iter3_reg;
+                tmp3_reg_640_pp0_iter2_reg <= tmp3_reg_640;
+                tmp3_reg_640_pp0_iter3_reg <= tmp3_reg_640_pp0_iter2_reg;
+                tmp3_reg_640_pp0_iter4_reg <= tmp3_reg_640_pp0_iter3_reg;
+                tmp7_reg_645_pp0_iter2_reg <= tmp7_reg_645;
+                tmp7_reg_645_pp0_iter3_reg <= tmp7_reg_645_pp0_iter2_reg;
+                tmp_8_i_i_mid2_reg_541_pp0_iter2_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter1_reg;
+                tmp_8_i_i_mid2_reg_541_pp0_iter3_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter2_reg;
+                tmp_8_i_i_mid2_reg_541_pp0_iter4_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter3_reg;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                filt1_read_reg_517 <= filt1_dout;
+                filt2_read_reg_522 <= filt2_dout;
+                height_read_reg_506 <= height_dout;
+                vconv_xlim_loc_read_reg_511 <= vconv_xlim_loc_dout;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then
+                linebuf_0_addr_reg_550 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_1_addr_reg_556 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_2_addr_reg_562 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_3_addr_reg_568 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_4_addr_reg_574 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_5_addr_reg_580 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_6_addr_reg_586 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_7_addr_reg_592 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_8_addr_reg_598 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                linebuf_9_addr_reg_604 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+                tmp_8_i_i_mid2_reg_541 <= tmp_8_i_i_mid2_fu_410_p3;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then
+                linebuf_5_load_reg_620 <= linebuf_5_q0;
+                linebuf_8_load_reg_625 <= linebuf_8_q0;
+                linebuf_9_load_reg_630 <= linebuf_9_q0;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then
+                tmp2_reg_635 <= tmp2_fu_446_p2;
+                tmp3_reg_640 <= tmp3_fu_458_p2;
+                tmp7_reg_645 <= tmp7_fu_464_p2;
+                tmp_1_reg_615 <= hconv_V_dout;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter3_reg = ap_const_lv1_0))) then
+                tmp5_reg_665 <= tmp5_fu_491_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter2_reg = ap_const_lv1_0))) then
+                tmp8_reg_660 <= tmp8_fu_482_p2;
+            end if;
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter1_reg = ap_const_lv1_0))) then
+                tmp_30_9_i_i_reg_650 <= tmp_30_9_i_i_fu_470_p2;
+                tmp_30_i_i_reg_655 <= tmp_30_i_i_fu_474_p2;
+            end if;
+        end if;
+    end process;
+
+    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter5, exitcond_flatten_fu_373_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter4)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+            when ap_ST_fsm_pp0_stage0 => 
+                if ((not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) and not(((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1))))) then
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                elsif ((((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)) or ((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1)))) then
+                    ap_NS_fsm <= ap_ST_fsm_state9;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
+                end if;
+            when ap_ST_fsm_state9 => 
+                ap_NS_fsm <= ap_ST_fsm_state1;
+            when others =>  
+                ap_NS_fsm <= "XXXX";
+        end case;
+    end process;
+    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state9 <= ap_CS_fsm(3);
+
+    ap_block_pp0_assign_proc : process(ap_CS_fsm, ap_block_pp0_stage0_subdone)
+    begin
+                ap_block_pp0 <= ((ap_ST_fsm_pp0_stage0 = ap_CS_fsm) and (ap_const_boolean_1 = ap_block_pp0_stage0_subdone));
+    end process;
+
+        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_pp0_stage0_01001_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
+    begin
+                ap_block_pp0_stage0_01001 <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
+    end process;
+
+
+    ap_block_pp0_stage0_11001_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
+    begin
+                ap_block_pp0_stage0_11001 <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
+    end process;
+
+
+    ap_block_pp0_stage0_subdone_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
+    begin
+                ap_block_pp0_stage0_subdone <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
+    end process;
+
+
+    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
+    begin
+                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
+    end process;
+
+        ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state4_pp0_stage0_iter1_assign_proc : process(hconv_V_empty_n, exitcond_flatten_reg_532)
+    begin
+                ap_block_state4_pp0_stage0_iter1 <= ((hconv_V_empty_n = ap_const_logic_0) and (exitcond_flatten_reg_532 = ap_const_lv1_0));
+    end process;
+
+        ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+        ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
+
+    ap_block_state8_pp0_stage0_iter5_assign_proc : process(vconv_V_full_n, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
+    begin
+                ap_block_state8_pp0_stage0_iter5 <= ((vconv_V_full_n = ap_const_logic_0) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1));
+    end process;
+
+
+    ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+        if ((exitcond_flatten_fu_373_p2 = ap_const_lv1_1)) then 
+            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
+        else 
+            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state9)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_done_reg;
+        end if; 
+    end process;
+
+
+    ap_enable_operation_44_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_44 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_46_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_46 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_48_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_48 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_50_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_50 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_52_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_52 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_54_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_54 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_56_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_56 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_58_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_58 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_60_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_60 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_62_assign_proc : process(exitcond_flatten_fu_373_p2)
+    begin
+                ap_enable_operation_62 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_66_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_66 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_67_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_67 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_68_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_68 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_69_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_69 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_70_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_70 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_71_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_71 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_72_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_72 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_73_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_73 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_74_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_74 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_75_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_75 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_76_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_76 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_77_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_77 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_78_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_78 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_79_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_79 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_80_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_80 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_81_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_81 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_82_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_82 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_83_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_83 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_84_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_84 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+
+    ap_enable_operation_89_assign_proc : process(exitcond_flatten_reg_532)
+    begin
+                ap_enable_operation_89 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
+    end process;
+
+    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
+
+    ap_enable_state3_pp0_iter0_stage0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0)
+    begin
+                ap_enable_state3_pp0_iter0_stage0 <= ((ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0));
+    end process;
+
+
+    ap_enable_state4_pp0_iter1_stage0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
+    begin
+                ap_enable_state4_pp0_iter1_stage0 <= ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0));
+    end process;
+
+
+    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
+    begin
+        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4)
+    begin
+        if (((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then 
+            ap_idle_pp0 <= ap_const_logic_1;
+        else 
+            ap_idle_pp0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_ready_assign_proc : process(ap_CS_fsm_state9)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
+            ap_ready <= ap_const_logic_1;
+        else 
+            ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    bound_fu_358_p0 <= bound_fu_358_p00(32 - 1 downto 0);
+    bound_fu_358_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(vconv_xlim_loc_read_reg_511),64));
+    bound_fu_358_p1 <= bound_fu_358_p10(32 - 1 downto 0);
+    bound_fu_358_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(height_read_reg_506),64));
+    bound_fu_358_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_358_p0) * unsigned(bound_fu_358_p1), 64));
+    col1_0_i_i_i_mid2_fu_418_p3 <= 
+        col1_0_i_i_i_reg_330 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
+        col_fu_392_p2;
+    col_fu_392_p2 <= std_logic_vector(unsigned(col1_0_i_i_i_reg_330) + unsigned(ap_const_lv10_1));
+    exitcond_flatten_fu_373_p2 <= "1" when (indvar_flatten_reg_319 = bound_reg_527) else "0";
+
+    filt1_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt1_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt1_blk_n <= filt1_empty_n;
+        else 
+            filt1_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    filt1_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt1_read <= ap_const_logic_1;
+        else 
+            filt1_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    filt2_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt2_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt2_blk_n <= filt2_empty_n;
+        else 
+            filt2_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    filt2_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            filt2_read <= ap_const_logic_1;
+        else 
+            filt2_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    hconv_V_blk_n_assign_proc : process(hconv_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_flatten_reg_532)
+    begin
+        if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
+            hconv_V_blk_n <= hconv_V_empty_n;
+        else 
+            hconv_V_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    hconv_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            hconv_V_read <= ap_const_logic_1;
+        else 
+            hconv_V_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    height_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_blk_n <= height_empty_n;
+        else 
+            height_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    height_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_out_blk_n <= height_out_full_n;
+        else 
+            height_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    height_out_din <= height_dout;
+
+    height_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_out_write <= ap_const_logic_1;
+        else 
+            height_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    height_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            height_read <= ap_const_logic_1;
+        else 
+            height_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    indvar_flatten_next_fu_378_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_319) + unsigned(ap_const_lv64_1));
+    linebuf_0_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_0_address1 <= linebuf_0_addr_reg_550;
+
+    linebuf_0_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_0_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_0_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_0_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_0_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_0_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_0_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_0_we1 <= ap_const_logic_1;
+        else 
+            linebuf_0_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_1_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_1_address1 <= linebuf_1_addr_reg_556;
+
+    linebuf_1_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_1_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_1_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_1_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_1_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_1_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_1_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_1_we1 <= ap_const_logic_1;
+        else 
+            linebuf_1_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_2_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_2_address1 <= linebuf_2_addr_reg_562;
+
+    linebuf_2_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_2_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_2_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_2_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_2_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_2_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_2_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_2_we1 <= ap_const_logic_1;
+        else 
+            linebuf_2_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_3_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_3_address1 <= linebuf_3_addr_reg_568;
+
+    linebuf_3_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_3_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_3_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_3_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_3_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_3_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_3_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_3_we1 <= ap_const_logic_1;
+        else 
+            linebuf_3_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_4_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_4_address1 <= linebuf_4_addr_reg_574;
+
+    linebuf_4_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_4_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_4_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_4_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_4_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_4_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_4_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_4_we1 <= ap_const_logic_1;
+        else 
+            linebuf_4_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_5_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_5_address1 <= linebuf_5_addr_reg_580;
+
+    linebuf_5_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_5_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_5_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_5_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_5_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_5_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_5_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_5_we1 <= ap_const_logic_1;
+        else 
+            linebuf_5_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_6_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_6_address1 <= linebuf_6_addr_reg_586;
+
+    linebuf_6_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_6_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_6_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_6_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_6_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_6_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_6_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_6_we1 <= ap_const_logic_1;
+        else 
+            linebuf_6_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_7_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_7_address1 <= linebuf_7_addr_reg_592;
+
+    linebuf_7_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_7_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_7_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_7_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_7_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_7_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_7_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_7_we1 <= ap_const_logic_1;
+        else 
+            linebuf_7_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_8_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_8_address1 <= linebuf_8_addr_reg_598;
+
+    linebuf_8_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_8_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_8_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_8_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_8_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_8_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_8_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_8_we1 <= ap_const_logic_1;
+        else 
+            linebuf_8_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    linebuf_9_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
+    linebuf_9_address1 <= linebuf_9_addr_reg_604;
+
+    linebuf_9_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_9_ce0 <= ap_const_logic_1;
+        else 
+            linebuf_9_ce0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_9_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
+            linebuf_9_ce1 <= ap_const_logic_1;
+        else 
+            linebuf_9_ce1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    linebuf_9_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
+            linebuf_9_we1 <= ap_const_logic_1;
+        else 
+            linebuf_9_we1 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    row2_0_i_cast_i_i_fu_364_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row2_0_i_i_i_reg_341),32));
+    row2_0_i_i_i_mid2_fu_384_p3 <= 
+        row2_0_i_i_i_reg_341 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
+        ap_const_lv10_0;
+    row_fu_440_p2 <= std_logic_vector(unsigned(row2_0_i_i_i_mid2_fu_384_p3) + unsigned(ap_const_lv10_1));
+    tmp1_fu_496_p2 <= std_logic_vector(unsigned(tmp3_reg_640_pp0_iter4_reg) + unsigned(tmp2_reg_635_pp0_iter4_reg));
+    tmp2_fu_446_p2 <= std_logic_vector(unsigned(linebuf_0_q0) + unsigned(linebuf_1_q0));
+    tmp3_fu_458_p2 <= std_logic_vector(unsigned(tmp4_fu_452_p2) + unsigned(linebuf_2_q0));
+    tmp4_fu_452_p2 <= std_logic_vector(unsigned(linebuf_3_q0) + unsigned(linebuf_4_q0));
+    tmp5_fu_491_p2 <= std_logic_vector(unsigned(tmp8_reg_660) + unsigned(tmp6_fu_487_p2));
+    tmp6_fu_487_p2 <= std_logic_vector(unsigned(tmp7_reg_645_pp0_iter3_reg) + unsigned(linebuf_5_load_reg_620_pp0_iter3_reg));
+    tmp7_fu_464_p2 <= std_logic_vector(unsigned(linebuf_6_q0) + unsigned(linebuf_7_q0));
+    tmp8_fu_482_p2 <= std_logic_vector(unsigned(tmp9_fu_478_p2) + unsigned(linebuf_8_load_reg_625_pp0_iter2_reg));
+    tmp9_fu_478_p2 <= std_logic_vector(unsigned(tmp_30_9_i_i_reg_650) + unsigned(tmp_30_i_i_reg_655));
+    tmp_11_i_i_fu_368_p2 <= "1" when (signed(row2_0_i_cast_i_i_fu_364_p1) < signed(vconv_xlim_loc_read_reg_511)) else "0";
+    tmp_16_i_i_fu_426_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row2_0_i_i_i_mid2_fu_384_p3),64));
+    tmp_30_9_i_i_fu_470_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt1_read_reg_517) * signed(linebuf_9_load_reg_630))), 32));
+    tmp_30_i_i_fu_474_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt2_read_reg_522) * signed(tmp_1_reg_615))), 32));
+    tmp_8_i_i_fu_404_p2 <= "1" when (unsigned(col1_0_i_i_i_reg_330) > unsigned(ap_const_lv10_9)) else "0";
+    tmp_8_i_i_mid1_fu_398_p2 <= "1" when (unsigned(col_fu_392_p2) > unsigned(ap_const_lv10_9)) else "0";
+    tmp_8_i_i_mid2_fu_410_p3 <= 
+        tmp_8_i_i_fu_404_p2 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
+        tmp_8_i_i_mid1_fu_398_p2;
+
+    vconv_V_blk_n_assign_proc : process(vconv_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
+    begin
+        if (((ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
+            vconv_V_blk_n <= vconv_V_full_n;
+        else 
+            vconv_V_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    vconv_V_din <= std_logic_vector(unsigned(tmp5_reg_665) + unsigned(tmp1_fu_496_p2));
+
+    vconv_V_write_assign_proc : process(ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg, ap_block_pp0_stage0_11001)
+    begin
+        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1))) then 
+            vconv_V_write <= ap_const_logic_1;
+        else 
+            vconv_V_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    vconv_xlim_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_empty_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            vconv_xlim_loc_blk_n <= vconv_xlim_loc_empty_n;
+        else 
+            vconv_xlim_loc_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+
+    vconv_xlim_loc_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            vconv_xlim_loc_out_blk_n <= vconv_xlim_loc_out_full_n;
+        else 
+            vconv_xlim_loc_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    vconv_xlim_loc_out_din <= vconv_xlim_loc_dout;
+
+    vconv_xlim_loc_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            vconv_xlim_loc_out_write <= ap_const_logic_1;
+        else 
+            vconv_xlim_loc_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    vconv_xlim_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
+    begin
+        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            vconv_xlim_loc_read <= ap_const_logic_1;
+        else 
+            vconv_xlim_loc_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+end behav;