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- `timescale 1 ps / 1 ps
- module nios2_uc_nios2 (
- input wire clk,
- input wire reset_n,
- input wire reset_req,
- output wire [19:0] d_address,
- output wire [3:0] d_byteenable,
- output wire d_read,
- input wire [31:0] d_readdata,
- input wire d_waitrequest,
- output wire d_write,
- output wire [31:0] d_writedata,
- output wire debug_mem_slave_debugaccess_to_roms,
- output wire [19:0] i_address,
- output wire i_read,
- input wire [31:0] i_readdata,
- input wire i_waitrequest,
- input wire [31:0] irq,
- output wire debug_reset_request,
- input wire [8:0] debug_mem_slave_address,
- input wire [3:0] debug_mem_slave_byteenable,
- input wire debug_mem_slave_debugaccess,
- input wire debug_mem_slave_read,
- output wire [31:0] debug_mem_slave_readdata,
- output wire debug_mem_slave_waitrequest,
- input wire debug_mem_slave_write,
- input wire [31:0] debug_mem_slave_writedata,
- output wire dummy_ci_port
- );
- nios2_uc_nios2_cpu cpu (
- .clk (clk),
- .reset_n (reset_n),
- .reset_req (reset_req),
- .d_address (d_address),
- .d_byteenable (d_byteenable),
- .d_read (d_read),
- .d_readdata (d_readdata),
- .d_waitrequest (d_waitrequest),
- .d_write (d_write),
- .d_writedata (d_writedata),
- .debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms),
- .i_address (i_address),
- .i_read (i_read),
- .i_readdata (i_readdata),
- .i_waitrequest (i_waitrequest),
- .irq (irq),
- .debug_reset_request (debug_reset_request),
- .debug_mem_slave_address (debug_mem_slave_address),
- .debug_mem_slave_byteenable (debug_mem_slave_byteenable),
- .debug_mem_slave_debugaccess (debug_mem_slave_debugaccess),
- .debug_mem_slave_read (debug_mem_slave_read),
- .debug_mem_slave_readdata (debug_mem_slave_readdata),
- .debug_mem_slave_waitrequest (debug_mem_slave_waitrequest),
- .debug_mem_slave_write (debug_mem_slave_write),
- .debug_mem_slave_writedata (debug_mem_slave_writedata),
- .dummy_ci_port (dummy_ci_port)
- );
- endmodule
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