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- `timescale 1 ns / 1 ns
- module altera_reset_synchronizer
- #(
- parameter ASYNC_RESET = 1,
- parameter DEPTH = 2
- )
- (
- input reset_in ,
- input clk,
- output reset_out
- );
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- (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
- reg altera_reset_synchronizer_int_chain_out;
- generate if (ASYNC_RESET) begin
-
-
-
- always @(posedge clk or posedge reset_in) begin
- if (reset_in) begin
- altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
- altera_reset_synchronizer_int_chain_out <= 1'b1;
- end
- else begin
- altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
- altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
- altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
- end
- end
- assign reset_out = altera_reset_synchronizer_int_chain_out;
-
- end else begin
-
-
-
- always @(posedge clk) begin
- altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
- altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
- altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
- end
- assign reset_out = altera_reset_synchronizer_int_chain_out;
-
- end
- endgenerate
- endmodule
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