updated readme

README.md

@@ -1,13 +1,38 @@
 # DE2-115-FPGA-Pong
 
-Pong game on Altera FPGA as exercise in Hardware-/Software-Codesign
+This is a Pong game on an Altera FPGA as an exercise in Hardware-/Software-Codesign.
+
+The video below shows it in action, running on an university-made extension board.
 [![](images/video.jpeg)](images/video.mp4)
 
+## Source files
+
+```
+.
+├── myfirst_niosii.vhd
+├── nios2_uc
+│   ├── nios2_uc.bsf
+│   └── synthesis
+│       └── nios2_uc.vhd
+├── README.md
+└── software
+    ├── hello_world
+    ├── hello_world_bsp
+    ├── Pong_Code
+    │   ├── Display.h
+    │   ├── Main.c
+    │   └── structs.h
+    └── Pong_Code_bsp
+```
+
 ## Data flow
+This diagram shows all the implemented parts and the singnals to connect them. The implementation is split in pysical Hareware, programmable logic as VHDL and instruction based C software.
 ![](images/data_graph.png)
 
 ## Flowcharts of the VHDL program
 
+Below are shown the two main processes that are implemented in VHDL. They run simultanously and independent of each other. All processes and the synthesized CPU are connected to a common 50 MHz clock and a reset signal. When reset, all processes are asynchronously forced to output their default values, as seen in the first block.
+
 ### Multiplex process
 ![](images/matrix_multiplex.png)
 
@@ -28,7 +53,7 @@ See:
 ---
 
 ### Subfunctions Flowcharts
-Flowchart of draw function. Function output the virtual screen to the output pins to be processed by VHDL
+This is the flowchart of the draw function. This function outputs the virtual screen to the matrix instruction register to be processed by VHDL.
 
 ![](images/draw.png)