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@@ -29,16 +29,43 @@ This is a Pong game on an Altera FPGA as an exercise in Hardware-/Software-Codes
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This diagram shows all the implemented parts and the singnals to connect them. The implementation is split in pysical Hareware, programmable logic as VHDL and instruction based C software.
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-## Flowcharts of the VHDL program
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+## VHDL program
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Below are shown the two main processes that are implemented in VHDL. They run simultanously and independent of each other. All processes and the synthesized CPU are connected to a common 50 MHz clock and a reset signal. When reset, all processes are asynchronously forced to output their default values, as seen in the first block.
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### Multiplex process
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+
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+The matrix multiplexing timer has been sized regarding the following equations:
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+- Timer frequency: `50Mhz / 2**20 = 1526 Hz`
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+- Time per column: `1 / 1526 Hz = 0.66 ms`
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+- 1526 Hz / 8 = 190 Hz matrix refresh rate
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+
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### Debounce process
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+### Matrix instruction
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+
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+The matrix instruction contains 20 bits that are split in three parts:
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+```
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+ 20 16 12 8 4 0
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+ XXXX CCCC RRRR RRRR RRRR
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+```
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+| Symbol | Bit range | Description |
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+|---------|--------------|----------------|
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+| X | 19 downto 16 | unused |
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+| C | 15 downto 12 | column number |
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+| R | 11 downto 0 | row data |
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+
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+The column number can be one of the following values:
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+- 0000: don't set anything
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+- 0001: set column 0 to row data
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+- 0010: set column 1 to row data
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+- 0011: set column 2 to row data
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+- ...
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+
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## Flowcharts of the C program
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Below images show flowcharts for all featured software functions.
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Fist chart feature the main game function. Subfunctions are described below.
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