vhdl-modules/ip_repo_sources/UDP-server/component.xml

<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
  <spirit:vendor>user.org</spirit:vendor>
  <spirit:library>user</spirit:library>
  <spirit:name>ethernet_transceiver</spirit:name>
  <spirit:version>1.0</spirit:version>
  <spirit:busInterfaces>
    <spirit:busInterface>
      <spirit:name>btn_reset</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>btn_reset</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>eth_rstn</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>eth_rstn</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.ETH_RSTN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>fifo_read</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RD_DATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>fifoReadData</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RD_EN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>fifoReadEnable</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>EMPTY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>fifoReadEmpty</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ALMOST_EMPTY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>fifoReadAlmostEmpty</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>fifo_write</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WR_DATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>fifoWriteData</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WR_EN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>fifoWriteEnable</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ALMOST_FULL</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>fifoWriteAlmostFull</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>FULL</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>fifoWriteFull</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
    </spirit:busInterface>
  </spirit:busInterfaces>
  <spirit:model>
    <spirit:views>
      <spirit:view>
        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
        <spirit:displayName>Synthesis</spirit:displayName>
        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
        <spirit:language>VHDL</spirit:language>
        <spirit:modelName>ethernet_transceiver2</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>viewChecksum</spirit:name>
            <spirit:value>c97fa251</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
        <spirit:displayName>Simulation</spirit:displayName>
        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
        <spirit:language>VHDL</spirit:language>
        <spirit:modelName>ethernet_transceiver2</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>viewChecksum</spirit:name>
            <spirit:value>c97fa251</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_xpgui</spirit:name>
        <spirit:displayName>UI Layout</spirit:displayName>
        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>viewChecksum</spirit:name>
            <spirit:value>1df2b5c5</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_testbench</spirit:name>
        <spirit:displayName>Test Bench</spirit:displayName>
        <spirit:envIdentifier>:vivado.xilinx.com:simulation.testbench</spirit:envIdentifier>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_testbench_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>viewChecksum</spirit:name>
            <spirit:value>936fb5ed</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
    </spirit:views>
    <spirit:ports>
      <spirit:port>
        <spirit:name>clk100mhz</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eth_rxd</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eth_txd</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">1</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eth_crsdv</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eth_txen</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eth_rxerr</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eth_mdc</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eth_mdio</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eth_refclk</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>eth_rstn</spirit:name>
        <spirit:wire>
          <spirit:direction>inout</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>led16_b</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>led16_g</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>led16_r</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>led17_b</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>led17_g</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>led17_r</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>btn_reset</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>led</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sw</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">4</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>fifoWriteEnable</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>fifoWriteData</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">31</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>fifoWriteAlmostFull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>fifoWriteFull</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>fifoReadEnable</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>fifoReadData</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.DATA_WIDTH&apos;)) - 1)">7</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>fifoReadAlmostEmpty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>fifoReadEmpty</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sendPacketLength</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>sendPacketChecksum</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
    </spirit:ports>
    <spirit:modelParameters>
      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
        <spirit:name>M_clk2_5mhz1</spirit:name>
        <spirit:displayName>M Clk2 5mhz1</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_clk2_5mhz1">20</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="integer">
        <spirit:name>M_clk2_5mhz2</spirit:name>
        <spirit:displayName>M Clk2 5mhz2</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.M_clk2_5mhz2">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="integer">
        <spirit:name>N</spirit:name>
        <spirit:displayName>N</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.N">22</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="integer">
        <spirit:name>ADDR_WIDTH</spirit:name>
        <spirit:displayName>Addr Width</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ADDR_WIDTH">10</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="integer">
        <spirit:name>DATA_WIDTH</spirit:name>
        <spirit:displayName>Data Width</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:value>
      </spirit:modelParameter>
    </spirit:modelParameters>
  </spirit:model>
  <spirit:choices>
    <spirit:choice>
      <spirit:name>choice_list_9d8b0d81</spirit:name>
      <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
      <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
    </spirit:choice>
  </spirit:choices>
  <spirit:fileSets>
    <spirit:fileSet>
      <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>src/clock_mod.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/clock_mod2.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/crc32_parallel.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/debounce_switch.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/eth_receiver.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/eth_transmitter.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/led1.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/md_interface.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/single_port_RAM.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/ethernet_transceiver.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>CHECKSUM_e9b44322</spirit:userFileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>src/clock_mod.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/clock_mod2.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/crc32_parallel.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/debounce_switch.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/eth_receiver.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/eth_transmitter.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/led1.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/md_interface.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/single_port_RAM.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>src/ethernet_transceiver.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>xgui/ethernet_transceiver_v1_0.tcl</spirit:name>
        <spirit:fileType>tclSource</spirit:fileType>
        <spirit:userFileType>CHECKSUM_1df2b5c5</spirit:userFileType>
        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_testbench_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>src/tb_eth_rxtx_arp_udp_ram.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
      </spirit:file>
    </spirit:fileSet>
  </spirit:fileSets>
  <spirit:description>ethernet_transceiver_v1_0</spirit:description>
  <spirit:parameters>
    <spirit:parameter>
      <spirit:name>M_clk2_5mhz1</spirit:name>
      <spirit:displayName>M Clk2 5mhz1</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.M_clk2_5mhz1">20</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>M_clk2_5mhz2</spirit:name>
      <spirit:displayName>M Clk2 5mhz2</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.M_clk2_5mhz2">10</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>N</spirit:name>
      <spirit:displayName>N</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.N">22</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>ADDR_WIDTH</spirit:name>
      <spirit:displayName>Addr Width</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADDR_WIDTH">10</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>DATA_WIDTH</spirit:name>
      <spirit:displayName>Data Width</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH">8</spirit:value>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>Component_Name</spirit:name>
      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ethernet_transceiver_v1_0</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
  <spirit:vendorExtensions>
    <xilinx:coreExtensions>
      <xilinx:supportedFamilies>
        <xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
        <xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
        <xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
        <xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
        <xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
        <xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
        <xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
        <xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
        <xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
        <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
        <xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
      </xilinx:supportedFamilies>
      <xilinx:taxonomies>
        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
      </xilinx:taxonomies>
      <xilinx:displayName>ethernet_transceiver_v1_0</xilinx:displayName>
      <xilinx:definitionSource>package_project</xilinx:definitionSource>
      <xilinx:coreRevision>7</xilinx:coreRevision>
      <xilinx:coreCreationDateTime>2019-06-05T17:02:37Z</xilinx:coreCreationDateTime>
      <xilinx:tags>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@1cca7b9e_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@512ae0b8_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@3be9c5a_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6044a408_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@63d58c7d_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@1b067c59_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@69940983_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@16d527f7_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@3503ae9b_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@2f625fd3_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@7841c2f2_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@2b97caf0_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@285260c8_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@5f56d5b2_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@4691b533_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@2030a36c_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@755797b0_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@3d4a117d_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@21a1ef5c_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6913b0fc_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@44878978_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@3451a234_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@667ba4e5_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@4121d04b_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@28a75f29_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@3003e9ca_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@464895b1_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@de5d05b_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6fba657d_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@a3fdf81_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6ee77635_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@620b205_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6e1547bb_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@11d49f69_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@fd31830_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6ff5073a_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@4e4e45e5_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@ee0380a_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6c6bca2a_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@4762baaa_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@20e5eab1_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@511fd267_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@109f16_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@3c186ce8_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@76143e39_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@2f305f71_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6f25c702_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6b56bc69_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@58701471_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6eb1a799_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@5e0c36f2_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@36b34ca2_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@50314909_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@3d644a88_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@507b5534_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@f6b48a1_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@2d176f9_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@759cc027_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@2b0bfdf0_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@1b96cca0_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@4aba8487_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@37255aaf_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6a05126c_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@1b05223_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@68e688dd_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@449ceeb7_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@3736752f_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@79a6855e_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@42ba2d43_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@5bb95204_ARCHIVE_LOCATION">z:/ip_repo/UDP echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@3e46692b_ARCHIVE_LOCATION">z:/ip_repo/UDP_echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@2b8da74a_ARCHIVE_LOCATION">z:/ip_repo/UDP_echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6ad2bc11_ARCHIVE_LOCATION">z:/ip_repo/UDP_echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@8970653_ARCHIVE_LOCATION">z:/ip_repo/UDP_echo-server</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6b223ca5_ARCHIVE_LOCATION">z:/ip_repo/UDP_echo-server</xilinx:tag>
      </xilinx:tags>
    </xilinx:coreExtensions>
    <xilinx:packagingInfo>
      <xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="07378459"/>
      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b3d3b01c"/>
      <xilinx:checksum xilinx:scope="ports" xilinx:value="bc474e3e"/>
      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="a682ebb0"/>
      <xilinx:checksum xilinx:scope="parameters" xilinx:value="cc975b8c"/>
    </xilinx:packagingInfo>
  </spirit:vendorExtensions>
</spirit:component>