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component.xml

component.xml 144 KB
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  1. <?xml version="1.0" encoding="UTF-8"?>
    2. 

  2. <spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
    3. 

  3.   <spirit:vendor>xilinx.com</spirit:vendor>
    4. 

  4.   <spirit:library>user</spirit:library>
    5. 

  5.   <spirit:name>packaging</spirit:name>
    6. 

  6.   <spirit:version>2.0</spirit:version>
    7. 

  7.   <spirit:busInterfaces>
    8. 

  8.     <spirit:busInterface>
    9. 

  9.       <spirit:name>rst</spirit:name>
    10. 

  10.       <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
    11. 

  11.       <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
    12. 

  12.       <spirit:slave/>
    13. 

  13.       <spirit:portMaps>
    14. 

  14.         <spirit:portMap>
    15. 

  15.           <spirit:logicalPort>
    16. 

  16.             <spirit:name>RST</spirit:name>
    17. 

  17.           </spirit:logicalPort>
    18. 

  18.           <spirit:physicalPort>
    19. 

  19.             <spirit:name>rst</spirit:name>
    20. 

  20.           </spirit:physicalPort>
    21. 

  21.         </spirit:portMap>
    22. 

  22.       </spirit:portMaps>
    23. 

  23.     </spirit:busInterface>
    24. 

  24.     <spirit:busInterface>
    25. 

  25.       <spirit:name>clk</spirit:name>
    26. 

  26.       <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
    27. 

  27.       <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
    28. 

  28.       <spirit:slave/>
    29. 

  29.       <spirit:portMaps>
    30. 

  30.         <spirit:portMap>
    31. 

  31.           <spirit:logicalPort>
    32. 

  32.             <spirit:name>CLK</spirit:name>
    33. 

  33.           </spirit:logicalPort>
    34. 

  34.           <spirit:physicalPort>
    35. 

  35.             <spirit:name>clk</spirit:name>
    36. 

  36.           </spirit:physicalPort>
    37. 

  37.         </spirit:portMap>
    38. 

  38.       </spirit:portMaps>
    39. 

  39.       <spirit:parameters>
    40. 

  40.         <spirit:parameter>
    41. 

  41.           <spirit:name>ASSOCIATED_RESET</spirit:name>
    42. 

  42.           <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">rst</spirit:value>
    43. 

  43.         </spirit:parameter>
    44. 

  44.       </spirit:parameters>
    45. 

  45.     </spirit:busInterface>
    46. 

  46.     <spirit:busInterface>
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  47.       <spirit:name>fifo_read</spirit:name>
    48. 

  48.       <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read" spirit:version="1.0"/>
    49. 

  49.       <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read_rtl" spirit:version="1.0"/>
    50. 

  50.       <spirit:master/>
    51. 

  51.       <spirit:portMaps>
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  52.         <spirit:portMap>
    53. 

  53.           <spirit:logicalPort>
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  54.             <spirit:name>RD_DATA</spirit:name>
    55. 

  55.           </spirit:logicalPort>
    56. 

  56.           <spirit:physicalPort>
    57. 

  57.             <spirit:name>inputStream</spirit:name>
    58. 

  58.           </spirit:physicalPort>
    59. 

  59.         </spirit:portMap>
    60. 

  60.         <spirit:portMap>
    61. 

  61.           <spirit:logicalPort>
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  62.             <spirit:name>EMPTY</spirit:name>
    63. 

  63.           </spirit:logicalPort>
    64. 

  64.           <spirit:physicalPort>
    65. 

  65.             <spirit:name>inputEmpty</spirit:name>
    66. 

  66.           </spirit:physicalPort>
    67. 

  67.         </spirit:portMap>
    68. 

  68.         <spirit:portMap>
    69. 

  69.           <spirit:logicalPort>
    70. 

  70.             <spirit:name>RD_EN</spirit:name>
    71. 

  71.           </spirit:logicalPort>
    72. 

  72.           <spirit:physicalPort>
    73. 

  73.             <spirit:name>inpRdEn</spirit:name>
    74. 

  74.           </spirit:physicalPort>
    75. 

  75.         </spirit:portMap>
    76. 

  76.       </spirit:portMaps>
    77. 

  77.     </spirit:busInterface>
    78. 

  78.     <spirit:busInterface>
    79. 

  79.       <spirit:name>fifo_write</spirit:name>
    80. 

  80.       <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write" spirit:version="1.0"/>
    81. 

  81.       <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write_rtl" spirit:version="1.0"/>
    82. 

  82.       <spirit:master/>
    83. 

  83.       <spirit:portMaps>
    84. 

  84.         <spirit:portMap>
    85. 

  85.           <spirit:logicalPort>
    86. 

  86.             <spirit:name>ALMOST_FULL</spirit:name>
    87. 

  87.           </spirit:logicalPort>
    88. 

  88.           <spirit:physicalPort>
    89. 

  89.             <spirit:name>outputFull</spirit:name>
    90. 

  90.           </spirit:physicalPort>
    91. 

  91.         </spirit:portMap>
    92. 

  92.         <spirit:portMap>
    93. 

  93.           <spirit:logicalPort>
    94. 

  94.             <spirit:name>WR_DATA</spirit:name>
    95. 

  95.           </spirit:logicalPort>
    96. 

  96.           <spirit:physicalPort>
    97. 

  97.             <spirit:name>outData</spirit:name>
    98. 

  98.           </spirit:physicalPort>
    99. 

  99.         </spirit:portMap>
    100. 

  100.         <spirit:portMap>
    101. 

  101.           <spirit:logicalPort>
    102. 

  102.             <spirit:name>WR_EN</spirit:name>
    103. 

  103.           </spirit:logicalPort>
    104. 

  104.           <spirit:physicalPort>
    105. 

  105.             <spirit:name>outWrEn</spirit:name>
    106. 

  106.           </spirit:physicalPort>
    107. 

  107.         </spirit:portMap>
    108. 

  108.       </spirit:portMaps>
    109. 

  109.     </spirit:busInterface>
    110. 

  110.   </spirit:busInterfaces>
    111. 

  111.   <spirit:model>
    112. 

  112.     <spirit:views>
    113. 

  113.       <spirit:view>
    114. 

  114.         <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
    115. 

  115.         <spirit:displayName>Synthesis</spirit:displayName>
    116. 

  116.         <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
    117. 

  117.         <spirit:language>VHDL</spirit:language>
    118. 

  118.         <spirit:modelName>packaging</spirit:modelName>
    119. 

  119.         <spirit:fileSetRef>
    120. 

  120.           <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
    121. 

  121.         </spirit:fileSetRef>
    122. 

  122.         <spirit:parameters>
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  123.           <spirit:parameter>
    124. 

  124.             <spirit:name>viewChecksum</spirit:name>
    125. 

  125.             <spirit:value>e0830e35</spirit:value>
    126. 

  126.           </spirit:parameter>
    127. 

  127.         </spirit:parameters>
    128. 

  128.       </spirit:view>
    129. 

  129.       <spirit:view>
    130. 

  130.         <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
    131. 

  131.         <spirit:displayName>Simulation</spirit:displayName>
    132. 

  132.         <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
    133. 

  133.         <spirit:language>VHDL</spirit:language>
    134. 

  134.         <spirit:modelName>packaging</spirit:modelName>
    135. 

  135.         <spirit:fileSetRef>
    136. 

  136.           <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
    137. 

  137.         </spirit:fileSetRef>
    138. 

  138.         <spirit:parameters>
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  139.           <spirit:parameter>
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  140.             <spirit:name>viewChecksum</spirit:name>
    141. 

  141.             <spirit:value>e0830e35</spirit:value>
    142. 

  142.           </spirit:parameter>
    143. 

  143.         </spirit:parameters>
    144. 

  144.       </spirit:view>
    145. 

  145.       <spirit:view>
    146. 

  146.         <spirit:name>xilinx_xpgui</spirit:name>
    147. 

  147.         <spirit:displayName>UI Layout</spirit:displayName>
    148. 

  148.         <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
    149. 

  149.         <spirit:fileSetRef>
    150. 

  150.           <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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  151.         </spirit:fileSetRef>
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  152.         <spirit:parameters>
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  153.           <spirit:parameter>
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  154.             <spirit:name>viewChecksum</spirit:name>
    155. 

  155.             <spirit:value>b2335c60</spirit:value>
    156. 

  156.           </spirit:parameter>
    157. 

  157.         </spirit:parameters>
    158. 

  158.       </spirit:view>
    159. 

  159.     </spirit:views>
    160. 

  160.     <spirit:ports>
    161. 

  161.       <spirit:port>
    162. 

  162.         <spirit:name>clk</spirit:name>
    163. 

  163.         <spirit:wire>
    164. 

  164.           <spirit:direction>in</spirit:direction>
    165. 

  165.           <spirit:wireTypeDefs>
    166. 

  166.             <spirit:wireTypeDef>
    167. 

  167.               <spirit:typeName>STD_LOGIC</spirit:typeName>
    168. 

  168.               <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
    169. 

  169.               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
    170. 

  170.             </spirit:wireTypeDef>
    171. 

  171.           </spirit:wireTypeDefs>
    172. 

  172.         </spirit:wire>
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  173.       </spirit:port>
    174. 

  174.       <spirit:port>
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  175.         <spirit:name>rst</spirit:name>
    176. 

  176.         <spirit:wire>
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  177.           <spirit:direction>in</spirit:direction>
    178. 

  178.           <spirit:wireTypeDefs>
    179. 

  179.             <spirit:wireTypeDef>
    180. 

  180.               <spirit:typeName>STD_LOGIC</spirit:typeName>
    181. 

  181.               <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
    182. 

  182.               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
    183. 

  183.             </spirit:wireTypeDef>
    184. 

  184.           </spirit:wireTypeDefs>
    185. 

  185.         </spirit:wire>
    186. 

  186.       </spirit:port>
    187. 

  187.       <spirit:port>
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  188.         <spirit:name>inputStream</spirit:name>
    189. 

  189.         <spirit:wire>
    190. 

  190.           <spirit:direction>in</spirit:direction>
    191. 

  191.           <spirit:vector>
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  192.             <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.busWidth&apos;)) - 1)">31</spirit:left>
    193. 

  193.             <spirit:right spirit:format="long">0</spirit:right>
    194. 

  194.           </spirit:vector>
    195. 

  195.           <spirit:wireTypeDefs>
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  196.             <spirit:wireTypeDef>
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  197.               <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
    198. 

  198.               <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
    199. 

  199.               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
    200. 

  200.             </spirit:wireTypeDef>
    201. 

  201.           </spirit:wireTypeDefs>
    202. 

  202.         </spirit:wire>
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  203.       </spirit:port>
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  204.       <spirit:port>
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  205.         <spirit:name>inpRdEn</spirit:name>
    206. 

  206.         <spirit:wire>
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  207.           <spirit:direction>out</spirit:direction>
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  208.           <spirit:wireTypeDefs>
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  209.             <spirit:wireTypeDef>
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  210.               <spirit:typeName>std_logic</spirit:typeName>
    211. 

  211.               <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
    212. 

  212.               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
    213. 

  213.             </spirit:wireTypeDef>
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  214.           </spirit:wireTypeDefs>
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  215.         </spirit:wire>
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  216.       </spirit:port>
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  217.       <spirit:port>
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  218.         <spirit:name>inputEmpty</spirit:name>
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  219.         <spirit:wire>
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  220.           <spirit:direction>in</spirit:direction>
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  221.           <spirit:wireTypeDefs>
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  222.             <spirit:wireTypeDef>
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  223.               <spirit:typeName>std_logic</spirit:typeName>
    224. 

  224.               <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
    225. 

  225.               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
    226. 

  226.             </spirit:wireTypeDef>
    227. 

  227.           </spirit:wireTypeDefs>
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  228.         </spirit:wire>
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  229.       </spirit:port>
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  230.       <spirit:port>
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  231.         <spirit:name>outData</spirit:name>
    232. 

  232.         <spirit:wire>
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  233.           <spirit:direction>out</spirit:direction>
    234. 

  234.           <spirit:vector>
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  235.             <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.busWidth&apos;)) - 1)">31</spirit:left>
    236. 

  236.             <spirit:right spirit:format="long">0</spirit:right>
    237. 

  237.           </spirit:vector>
    238. 

  238.           <spirit:wireTypeDefs>
    239. 

  239.             <spirit:wireTypeDef>
    240. 

  240.               <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
    241. 

  241.               <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
    242. 

  242.               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
    243. 

  243.             </spirit:wireTypeDef>
    244. 

  244.           </spirit:wireTypeDefs>
    245. 

  245.         </spirit:wire>
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  246.       </spirit:port>
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  247.       <spirit:port>
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  248.         <spirit:name>outWrEn</spirit:name>
    249. 

  249.         <spirit:wire>
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  250.           <spirit:direction>out</spirit:direction>
    251. 

  251.           <spirit:wireTypeDefs>
    252. 

  252.             <spirit:wireTypeDef>
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  253.               <spirit:typeName>std_logic</spirit:typeName>
    254. 

  254.               <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
    255. 

  255.               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
    256. 

  256.             </spirit:wireTypeDef>
    257. 

  257.           </spirit:wireTypeDefs>
    258. 

  258.         </spirit:wire>
    259. 

  259.       </spirit:port>
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  260.       <spirit:port>
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  261.         <spirit:name>outputFull</spirit:name>
    262. 

  262.         <spirit:wire>
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  263.           <spirit:direction>in</spirit:direction>
    264. 

  264.           <spirit:wireTypeDefs>
    265. 

  265.             <spirit:wireTypeDef>
    266. 

  266.               <spirit:typeName>std_logic</spirit:typeName>
    267. 

  267.               <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
    268. 

  268.               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
    269. 

  269.             </spirit:wireTypeDef>
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  270.           </spirit:wireTypeDefs>
    271. 

  271.         </spirit:wire>
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  272.       </spirit:port>
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  273.       <spirit:port>
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  274.         <spirit:name>errorCode</spirit:name>
    275. 

  275.         <spirit:wire>
    276. 

  276.           <spirit:direction>out</spirit:direction>
    277. 

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