user.org user packaging 3.0 rst RST rst clk CLK clk ASSOCIATED_RESET rst fifo_read RD_DATA inputStream RD_EN inpRdEn EMPTY inputEmpty fifo_write WR_DATA outData WR_EN outWrEn FULL outputFull xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL packaging xilinx_anylanguagesynthesis_view_fileset viewChecksum 80fccf26 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL packaging xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 80fccf26 xilinx_testbench Test Bench :vivado.xilinx.com:simulation.testbench tb xilinx_testbench_view_fileset viewChecksum 88e53ccc xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum b2335c60 clk in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rst in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation inputStream in 31 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation inpRdEn out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation inputEmpty in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation outData out 31 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation outWrEn out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation outputFull in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation errorCode out 3 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation stateOut out 3 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation busWidth Buswidth 32 xilinx_anylanguagesynthesis_view_fileset src/Block_proc.vhd vhdlSource IMPORTED_FILE src/Loop_Border_proc.vhd vhdlSource IMPORTED_FILE src/Loop_Border_proc_borderbuf.vhd vhdlSource IMPORTED_FILE src/Loop_HConvH_proc6.vhd vhdlSource IMPORTED_FILE src/Loop_VConvH_proc.vhd vhdlSource IMPORTED_FILE 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