user.org user ethernet_transceiver 1.0 btn_reset RST btn_reset eth_rstn RST eth_rstn POLARITY ACTIVE_LOW fifo_read RD_DATA fifoReadData RD_EN fifoReadEnable EMPTY fifoReadEmpty ALMOST_EMPTY fifoReadAlmostEmpty fifo_write WR_DATA fifoWriteData WR_EN fifoWriteEnable ALMOST_FULL fifoWriteAlmostFull FULL fifoWriteFull xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL ethernet_transceiver2 xilinx_anylanguagesynthesis_view_fileset viewChecksum c97fa251 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL ethernet_transceiver2 xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum c97fa251 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 1df2b5c5 xilinx_testbench Test Bench :vivado.xilinx.com:simulation.testbench xilinx_testbench_view_fileset viewChecksum 936fb5ed clk100mhz in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_rxd inout 1 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_txd inout 1 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_crsdv inout STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_txen inout STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_rxerr inout STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_mdc out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_mdio inout STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_refclk out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_rstn inout STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led16_b out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led16_g out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led16_r out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led17_b out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led17_g out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led17_r out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation btn_reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sw in 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifoWriteEnable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifoWriteData out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifoWriteAlmostFull in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifoWriteFull in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifoReadEnable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifoReadData in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifoReadAlmostEmpty in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifoReadEmpty in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sendPacketLength in 15 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sendPacketChecksum in 15 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 M_clk2_5mhz1 M Clk2 5mhz1 20 M_clk2_5mhz2 M Clk2 5mhz2 10 N N 22 ADDR_WIDTH Addr Width 10 DATA_WIDTH Data Width 8 choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset src/clock_mod.vhd vhdlSource IMPORTED_FILE src/clock_mod2.vhd vhdlSource IMPORTED_FILE src/crc32_parallel.vhd vhdlSource IMPORTED_FILE src/debounce_switch.vhd vhdlSource IMPORTED_FILE src/eth_receiver.vhd vhdlSource IMPORTED_FILE src/eth_transmitter.vhd vhdlSource IMPORTED_FILE src/led1.vhd vhdlSource IMPORTED_FILE src/md_interface.vhd vhdlSource IMPORTED_FILE src/single_port_RAM.vhd vhdlSource IMPORTED_FILE src/ethernet_transceiver.vhd vhdlSource CHECKSUM_e9b44322 IMPORTED_FILE xilinx_anylanguagebehavioralsimulation_view_fileset src/clock_mod.vhd vhdlSource IMPORTED_FILE src/clock_mod2.vhd vhdlSource IMPORTED_FILE src/crc32_parallel.vhd vhdlSource IMPORTED_FILE src/debounce_switch.vhd vhdlSource IMPORTED_FILE src/eth_receiver.vhd vhdlSource IMPORTED_FILE src/eth_transmitter.vhd vhdlSource IMPORTED_FILE src/led1.vhd vhdlSource IMPORTED_FILE src/md_interface.vhd vhdlSource IMPORTED_FILE src/single_port_RAM.vhd vhdlSource IMPORTED_FILE src/ethernet_transceiver.vhd vhdlSource IMPORTED_FILE xilinx_xpgui_view_fileset xgui/ethernet_transceiver_v1_0.tcl tclSource CHECKSUM_1df2b5c5 XGUI_VERSION_2 xilinx_testbench_view_fileset src/tb_eth_rxtx_arp_udp_ram.vhd vhdlSource USED_IN_simulation USED_IN_synthesis ethernet_transceiver_v1_0 M_clk2_5mhz1 M Clk2 5mhz1 20 M_clk2_5mhz2 M Clk2 5mhz2 10 N N 22 ADDR_WIDTH Addr Width 10 DATA_WIDTH Data Width 8 Component_Name ethernet_transceiver_v1_0 kintex7 kintex7l artix7 artix7l aartix7 zynq azynq spartan7 aspartan7 kintexuplus zynquplus kintexu /UserIP ethernet_transceiver_v1_0 package_project 7 2019-06-05T17:02:37Z z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP echo-server z:/ip_repo/UDP_echo-server z:/ip_repo/UDP_echo-server z:/ip_repo/UDP_echo-server z:/ip_repo/UDP_echo-server z:/ip_repo/UDP_echo-server 2018.3