xilinx.com user ethernet_transceiver2 1.0 btn_reset RST btn_reset eth_rstn RST eth_rstn POLARITY ACTIVE_LOW fifo_read RD_DATA fifo_read_data RD_EN fifo_read_enable EMPTY fifo_read_empty fifo_write WR_DATA fifo_write_data WR_EN fifo_write_enable FULL fifo_write_full xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL ethernet_transceiver2 xilinx_anylanguagesynthesis_view_fileset viewChecksum 4218cab6 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL ethernet_transceiver2 xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum f5e29829 xilinx_testbench Test Bench :vivado.xilinx.com:simulation.testbench ethernet_transceiver2 xilinx_testbench_view_fileset viewChecksum dd12fe65 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 4aa324c9 clk100mhz in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_rxd inout 1 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_txd inout 1 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_crsdv inout STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_txen inout STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_rxerr inout STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_mdc out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_mdio inout STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_refclk out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation eth_rstn inout STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led16_b out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led16_g out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led16_r out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led17_b out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led17_g out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led17_r out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation btn_reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation udp_packet_checksum in 15 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation udp_packet_recieved out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation udp_packet_sending out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifo_write_data out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifo_write_enable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifo_write_full in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifo_read_data in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifo_read_enable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifo_read_length in 15 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifo_read_empty in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ip in 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation M_clk2_5mhz1 M Clk2 5mhz1 20 M_clk2_5mhz2 M Clk2 5mhz2 10 N N 22 ADDR_WIDTH Addr Width 10 DATA_WIDTH Data Width 8 FIFO_WIDTH Fifo Width 32 choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset src/nexys 4 ddr.xdc xdc IMPORTED_FILE src/clock_mod.vhd vhdlSource IMPORTED_FILE src/clock_mod2.vhd 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