user.org user myip 1.0 S00_AXI AWADDR s00_axi_awaddr AWPROT s00_axi_awprot AWVALID s00_axi_awvalid AWREADY s00_axi_awready WDATA s00_axi_wdata WSTRB s00_axi_wstrb WVALID s00_axi_wvalid WREADY s00_axi_wready BRESP s00_axi_bresp BVALID s00_axi_bvalid BREADY s00_axi_bready ARADDR s00_axi_araddr ARPROT s00_axi_arprot ARVALID s00_axi_arvalid ARREADY s00_axi_arready RDATA s00_axi_rdata RRESP s00_axi_rresp RVALID s00_axi_rvalid RREADY s00_axi_rready WIZ_DATA_WIDTH 32 WIZ_NUM_REG 32 SUPPORTS_NARROW_BURST 0 S00_AXI_RST RST s00_axi_aresetn POLARITY ACTIVE_LOW S00_AXI_CLK CLK s00_axi_aclk ASSOCIATED_BUSIF S00_AXI ASSOCIATED_RESET s00_axi_aresetn S00_AXI S00_AXI_reg 0 4096 32 register OFFSET_BASE_PARAM C_S00_AXI_BASEADDR OFFSET_HIGH_PARAM C_S00_AXI_HIGHADDR xilinx_vhdlsynthesis VHDL Synthesis vhdlSource:vivado.xilinx.com:synthesis vhdl myip_v1_0 xilinx_vhdlsynthesis_view_fileset viewChecksum 68e2ce51 xilinx_vhdlbehavioralsimulation VHDL Simulation vhdlSource:vivado.xilinx.com:simulation vhdl myip_v1_0 xilinx_vhdlbehavioralsimulation_view_fileset viewChecksum 68e2ce51 xilinx_softwaredriver Software Driver :vivado.xilinx.com:sw.driver xilinx_softwaredriver_view_fileset viewChecksum 3ccb2799 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum fd592ead bd_tcl Block Diagram :vivado.xilinx.com:block.diagram bd_tcl_view_fileset viewChecksum 45a2f450 s00_axi_awaddr in 6 0 wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_awprot in 2 0 wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_awvalid in wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_awready out wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_wdata in 31 0 wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_wstrb in 3 0 wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_wvalid in wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_wready out wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_bresp out 1 0 wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_bvalid out wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_bready in wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_araddr in 6 0 wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_arprot in 2 0 wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_arvalid in wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_arready out wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_rdata out 31 0 wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_rresp out 1 0 wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_rvalid out wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_rready in wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_aclk in wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axi_aresetn in wire xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation C_S00_AXI_DATA_WIDTH C S00 AXI DATA WIDTH Width of S_AXI data bus 32 C_S00_AXI_ADDR_WIDTH C S00 AXI ADDR WIDTH Width of S_AXI address bus 7 choice_list_6fc15197 32 choice_pairs_ce1226b1 1 0 xilinx_vhdlsynthesis_view_fileset hdl/myip_v1_0_S00_AXI.vhd vhdlSource hdl/myip_v1_0.vhd vhdlSource CHECKSUM_7e1348a6 xilinx_vhdlbehavioralsimulation_view_fileset hdl/myip_v1_0_S00_AXI.vhd vhdlSource hdl/myip_v1_0.vhd vhdlSource xilinx_softwaredriver_view_fileset drivers/myip_v1_0/data/myip.mdd mdd driver_mdd drivers/myip_v1_0/data/myip.tcl tclSource driver_tcl drivers/myip_v1_0/src/Makefile driver_src drivers/myip_v1_0/src/myip.h cSource driver_src drivers/myip_v1_0/src/myip.c cSource driver_src drivers/myip_v1_0/src/myip_selftest.c cSource driver_src xilinx_xpgui_view_fileset xgui/myip_v1_0.tcl tclSource CHECKSUM_fd592ead XGUI_VERSION_2 bd_tcl_view_fileset bd/bd.tcl tclSource My new AXI IP C_S00_AXI_DATA_WIDTH C S00 AXI DATA WIDTH Width of S_AXI data bus 32 false C_S00_AXI_ADDR_WIDTH C S00 AXI ADDR WIDTH Width of S_AXI address bus 7 false C_S00_AXI_BASEADDR C S00 AXI BASEADDR 0xFFFFFFFF false C_S00_AXI_HIGHADDR C S00 AXI HIGHADDR 0x00000000 false Component_Name myip_v1_0 artix7 AXI_Peripheral myip_v1.0 2 2019-05-29T08:18:55Z /home/johannes/Desktop/mlfpga/ip_repo/myip_1.0 /home/johannes/Desktop/mlfpga/ip_repo/myip_1.0 /home/johannes/Desktop/mlfpga/ip_repo/myip_1.0 /home/johannes/Desktop/mlfpga/ip_repo/myip_1.0 /home/johannes/Desktop/mlfpga/ip_repo/myip_1.0 2018.3