don't copy constraints

src/hdl/mac.vhd

@@ -1,42 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_arith.ALL;
-use IEEE.std_logic_textio.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.myPackage.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity mac is
-    Port ( inputs : in dataVector;
-           weights : in dataVector;
-           bias : in dataType;
-           outp : out dataType;
-           clk: in STD_LOGIC);
-end mac;
-
-architecture Behavioral of mac is
-
-begin
-
-MAIN: process(clk)
-    variable sum : dataType;
-begin
-    if rising_edge(clk) then
-        sum :=  bias;
-        for i in 0 to nNodes-1 loop
-            sum := signed(sum) + conv_integer(signed(inputs(i))) * conv_integer(signed(weights(i)));
-        end loop;
-        
-        outp <= sum;
-    end if;
-end process;
-
-end Behavioral;

src/hdl/neuron.vhd

@@ -1,61 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity neuron is
-    Port (
-        inputs : in dataVector;
-        weights : in dataVector;
-        bias : in dataType;
-        start : in std_logic;
-        finished : out std_logic;
-        clk : in std_logic;
-        outp : out dataType);
-end neuron;
-
-architecture Behavioral of neuron is 
-
-component mac is
- port ( 
-   inputs : in dataVector;
-   weights : in dataVector;
-   bias : in dataType;
-   outp : out dataType;
-   clk : in std_logic);
-end component;
-
-component relu is
- port ( 
-   inp : in dataType;
-   clk : in std_logic;
-   outp : out dataType);
-end component;
-
-signal var1 : dataType;
-
-signal macFinished: std_logic;
-
-begin
-mac1: mac port map (
-    inputs => inputs,
-    weights => weights,
-    bias => bias,
-    outp => var1,
-    clk => clk
-);
-
-relu1: relu port map (
-    inp => var1,
-    clk => clk,
-    outp => outp
-);
-
-timing : process(clk)
-begin
-    if(rising_edge(clk)) then
-        macFinished <= start;
-        finished <= macFinished;
-    end if;
-end process;
-
-end Behavioral;

src/hdl/parallelize.vhd

@@ -1,86 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity parallelize is
-    generic(
-        busWidth : integer:=8);
-    Port ( clk : in STD_LOGIC;
-           rst : in STD_LOGIC;
-           start : in STD_LOGIC;
-           dataIn : in std_logic_vector(busWidth-1 downto 0);
-           ready: out std_logic;
-           dataOutReset : in std_logic;
-           dataOut : out std_logic_vector(busWidth-1 downto 0);
-           finished : out STD_LOGIC);
-end parallelize;
-
-architecture Behavioral of parallelize is
-
-constant parallelInWidth : integer := (2*nNodes+1) * nBits;
-constant parallelOutWidth : integer := nBits;
-
-component shiftIn is
-    generic(
-        inWidth : integer := busWidth;
-        outWidth : integer := parallelInWidth);
-    Port ( clk : in STD_LOGIC;
-           sync_reset : in STD_LOGIC;
-           dataIn : in std_logic_vector(inWidth-1 downto 0);
-           dataOut : out std_logic_vector(outWidth-1 downto 0);
-           finished : out STD_LOGIC);
-end component;
-component neuron is
-    Port (
-        inputs : in dataVector;
-        weights : in dataVector;
-        bias : in dataType;
-        start : in std_logic;
-        finished : out std_logic;
-        clk : in std_logic;
-        outp : out dataType);
-end component;
-component shiftOut is
-    generic(
-        inWidth : integer := parallelOutWidth;
-        outWidth : integer := busWidth);
-    Port ( clk : in STD_LOGIC;
-           sync_reset : in STD_LOGIC;
-           dataIn : in std_logic_vector(inWidth-1 downto 0);
-           dataOut : out std_logic_vector(outWidth-1 downto 0);
-           finished : out STD_LOGIC);
-end component;
-
-signal dataInStorage : std_logic_vector(parallelInWidth-1 downto 0);
-signal dataOutStorage : std_logic_vector(parallelOutWidth-1 downto 0);
-signal shiftInFinished : std_logic;
-
-begin
-
-shiftIn1: shiftIn port map (
-    clk         => clk,
-    sync_reset  => start,
-    dataIn      => dataIn,
-    dataOut     => dataInStorage,
-    finished    => shiftInFinished
-);
-
-neuron1: neuron port map (
-    inputs  => to_dataVector(dataInStorage(parallelInWidth-1 downto (nNodes+1) * nBits)),
-    weights => to_dataVector(dataInStorage((nNodes+1) * nBits-1 downto nBits)),
-    bias    => dataInStorage(nBits-1 downto 0),
-    clk     => clk,
-    outp    => dataOutStorage,
-    start   => shiftInFinished,
-    finished=> ready
-);
-
-shiftOut1 : shiftOut port map (
-    clk         => clk,
-    sync_reset  => dataOutReset,
-    dataIn      => dataOutStorage,
-    dataOut     => dataOut,
-    finished    => finished
-);
-
-end Behavioral;

src/hdl/relu.vhd

@@ -1,30 +0,0 @@
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_signed.all;
-use IEEE.std_logic_arith.all;
-use IEEE.math_real.all;
-use work.myPackage.ALL;
-
-entity relu is
-    Port ( inp : in dataType;
-           outp : out dataType;
-           clk: in STD_LOGIC );
-end relu;
-
-architecture Behavioral of relu is
-
-begin
-    calc : process(clk)
-    begin
-        if(rising_edge(clk)) then
-            if(signed(inp) > 0) then
-                outp <= inp;
-            else
-                outp <= (others => '0');
-            end if;
-            
-        end if;
-    end process;
-end Behavioral;

src/hdl/shiftOut.vhd

@@ -1,62 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 06/03/2019 01:56:01 PM
--- Design Name: 
--- Module Name: shiftOut - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity shiftOut is
-    generic(
-        inWidth : integer := 32*4;
-        outWidth : integer := 32);
-    Port ( clk : in STD_LOGIC;
-           sync_reset : in STD_LOGIC;
-           dataIn : in std_logic_vector(inWidth-1 downto 0);
-           dataOut : out std_logic_vector(outWidth-1 downto 0);
-           finished : out STD_LOGIC);
-end shiftOut;
-
-architecture Behavioral of shiftOut is
-    signal dataIndex : integer range 0 to (inWidth / outWidth) := 0;
-begin
-
-p_s2p : process(clk, sync_reset)
-begin
-    if(sync_reset = '0') then
-        dataIndex <= 0;
-        finished <= '0';
-    elsif(rising_edge(clk)) then
-        if(dataIndex < inWidth/outWidth) then
-            
-        else
-            
-        end if;
-        if(dataIndex < inWidth/outWidth-1) then
-            finished <= '0';
-            dataIndex <= dataIndex + 1;
-        else
-            finished <= '1';
-            dataIndex <= dataIndex;
-        end if;
-    end if;
-end process;
-
-dataOut <= dataIn(inWidth - dataIndex * outWidth - 1 downto inWidth - dataIndex * outWidth - outWidth);
-end Behavioral;

src/hdl/tb.vhd

@@ -1,177 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_arith.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use STD.textio.all;
-use ieee.std_logic_textio.all;
-
-entity tb_module is
-        
-end tb_module;
-
-architecture Behavioral of tb_module is
-
-constant busWidth : integer:=32;
-
-    component packaging is
-    generic(
-        busWidth : integer:=32);
-    Port ( clk : in STD_LOGIC;
-           rst : in STD_LOGIC;
-           
-           inputStream : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           inpRdEn : out std_logic;
-           inputEmpty : in std_logic;
-           
-           outData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           outWrEn : out std_logic;
-           outputFull : in std_logic;
-           
-           errorCode : out STD_LOGIC_VECTOR(3 DOWNTO 0);
-           stateOut : out STD_LOGIC_VECTOR(3 downto 0));
-    end component;
-    
-    signal clk : std_logic := '1';
-    signal rst : std_logic := '0';
-    
-    
-    
-
-    file inputFile : text;
-    file outputTimingsFile : text;
-    file outputFile : text;
-    
-    signal s_inData : std_logic_vector(busWidth-1 downto 0);
-    
-    signal srcAvail: std_logic := '1';
-    signal inputEmpty : std_logic := '0';
-    signal rdEn : std_logic;
-    
-    signal s_outData : std_logic_vector(busWidth-1 downto 0);
-    signal outputFull : std_logic := '0';
-    signal wrEn : std_logic;
-    
-
-    signal done: std_logic := '0'; 
-
-    signal index : integer := 0;
-    signal seek : integer := 0;
-    signal eth : integer range 0 to 7 := 0;
-
-begin
-
-    dut : packaging port map (
-        clk => clk,
-        rst => rst,
-        
-        inputStream => s_inData,
-        inputEmpty => inputEmpty,
-        inpRdEn => rdEn,
-        
-        outData => s_outData,
-        outWrEn => wrEn,
-        outputFull => outputFull
-        
-    );
-
-    p_read : process
-        variable v_inLine : line;
-        variable v_inTime : time;
-        variable v_space  : character;
-        variable v_inData : std_logic_vector(busWidth-1 downto 0);
-        
-
-    begin
-        file_open(inputFile, "input.txt", read_mode);
-        
-        while not endfile(inputFile) loop
-            wait until rising_edge(clk);
-            if rdEn = '1' then
-
-                assert srcAvail = '1'
-                report "input underflow"
-                severity warning;
-            
-                readline(inputFile, v_inLine);
-                read(v_inLine, v_inTime);
-                read(v_inLine, v_space);
-                read(v_inLine, v_inData);
-                s_inData <= v_inData;
-                
-                if v_inTime > 10 ns then
-                    srcAvail <= '0';
-                    srcAvail <= '1' after v_inTime;
-                end if;
-            end if;
-        end loop;
-        wait until rising_edge(clk);
-        file_close(inputFile);
-        srcAvail <= '0';
-        done <= '1' after 100 ns;
-        wait;
-    end process;
-    
-    inputEmpty <= not srcAvail or not rst;
-
-    p_write : process
-        variable v_outLine : line;
-        variable v_outTime : time;
-        variable c_space   : character := ' ';
-    begin
-        file_open(outputFile, "output.txt", write_mode);
-        while not done = '1' loop
-            wait until rising_edge(clk);
-            if wrEn = '1' then
-                assert outputFull = '0'
-                report "output overflow"
-                severity warning;
-                write(v_outLine, time'image(now));
-                write(v_outLine, c_space);
-                write(v_outLine, s_outData);
-                writeline(outputFile, v_outLine);
-            end if;
-        end loop;
-        file_close(outputFile);
-        wait;
-    end process;
-    
-    p_throttleOut : process
-        variable v_inLine : line;
-        variable v_inTime : time;
-    begin
-        file_open(outputTimingsFile, "outputTimings.txt", read_mode);
-        while not endfile(outputTimingsFile) and done = '0' loop
-            wait until rising_edge(clk);
-            
-            if wrEn = '1' then
-                readline(outputTimingsFile, v_inLine);
-                read(v_inLine, v_inTime);
-                
-                if v_inTime > 10 ns then
-                    outputFull <= '1';
-                    outputFull <= '0' after v_inTime;
-                end if;
-            end if;
-        end loop;
-        file_close(outputTimingsFile);
-        wait;
-    end process;
-
-    clkGen : process begin
-        wait for 5ns;
-        clk <= not clk;
-    end process;
-   
-    
-    rstGen : process begin
-        rst <= '0';
-        wait for 15 ns;
-        rst <= '1';
-        wait until rising_edge(done);
-        wait until rising_edge(clk);
-        assert false
-        report "simulation ended"
-        severity failure;
-    end process;
-
-end Behavioral;

src/testbench/dut_packaging/dut_packaging.bd

@@ -1,123 +0,0 @@
-{
-  "design": {
-    "design_info": {
-      "boundary_crc": "0xAE875A0F1BECE399",
-      "device": "xc7a100tcsg324-1",
-      "name": "dut_packaging",
-      "synth_flow_mode": "None",
-      "tool_version": "2018.3",
-      "validated": "true"
-    },
-    "design_tree": {
-      "packaging_0": ""
-    },
-    "interface_ports": {
-      "fifo_write_0": {
-        "mode": "Master",
-        "vlnv": "xilinx.com:interface:fifo_write_rtl:1.0"
-      },
-      "fifo_read_0": {
-        "mode": "Master",
-        "vlnv": "xilinx.com:interface:fifo_read_rtl:1.0"
-      }
-    },
-    "ports": {
-      "errorCode_0": {
-        "direction": "O",
-        "left": "3",
-        "right": "0"
-      },
-      "clk_0": {
-        "type": "clk",
-        "direction": "I",
-        "parameters": {
-          "ASSOCIATED_RESET": {
-            "value": "rst_0",
-            "value_src": "default"
-          },
-          "CLK_DOMAIN": {
-            "value": "dut_packaging_clk_0",
-            "value_src": "default"
-          },
-          "FREQ_HZ": {
-            "value": "100000000",
-            "value_src": "default"
-          },
-          "INSERT_VIP": {
-            "value": "0",
-            "value_src": "default"
-          },
-          "PHASE": {
-            "value": "0.000",
-            "value_src": "default"
-          }
-        }
-      },
-      "rst_0": {
-        "type": "rst",
-        "direction": "I",
-        "parameters": {
-          "INSERT_VIP": {
-            "value": "0",
-            "value_src": "default"
-          },
-          "POLARITY": {
-            "value": "ACTIVE_LOW",
-            "value_src": "default"
-          }
-        }
-      },
-      "stateOut_0": {
-        "direction": "O",
-        "left": "3",
-        "right": "0"
-      }
-    },
-    "components": {
-      "packaging_0": {
-        "vlnv": "user.org:user:packaging:3.0",
-        "xci_name": "dut_packaging_packaging_0_0"
-      }
-    },
-    "interface_nets": {
-      "packaging_0_fifo_read": {
-        "interface_ports": [
-          "fifo_read_0",
-          "packaging_0/fifo_read"
-        ]
-      },
-      "packaging_0_fifo_write": {
-        "interface_ports": [
-          "fifo_write_0",
-          "packaging_0/fifo_write"
-        ]
-      }
-    },
-    "nets": {
-      "packaging_0_errorCode": {
-        "ports": [
-          "packaging_0/errorCode",
-          "errorCode_0"
-        ]
-      },
-      "clk_0_1": {
-        "ports": [
-          "clk_0",
-          "packaging_0/clk"
-        ]
-      },
-      "rst_0_1": {
-        "ports": [
-          "rst_0",
-          "packaging_0/rst"
-        ]
-      },
-      "packaging_0_stateOut": {
-        "ports": [
-          "packaging_0/stateOut",
-          "stateOut_0"
-        ]
-      }
-    }
-  }
-}

src/testbench/dut_packaging/dut_packaging.bxml

@@ -1,57 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Root MajorVersion="0" MinorVersion="36">
-  <CompositeFile CompositeFileTopName="dut_packaging" CanBeSetAsTop="true" CanDisplayChildGraph="true">
-    <Description>Composite Fileset</Description>
-    <Generation Name="SYNTHESIS" State="STALE" Timestamp="1587993364"/>
-    <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1587993364"/>
-    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1587993365"/>
-    <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1587993365"/>
-    <FileCollection Name="SOURCES" Type="SOURCES">
-      <File Name="ip\dut_packaging_packaging_0_0\dut_packaging_packaging_0_0.xci" Type="IP">
-        <Instance HierarchyPath="packaging_0"/>
-        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
-        <Library Name="xil_defaultlib"/>
-        <UsedIn Val="SYNTHESIS"/>
-        <UsedIn Val="IMPLEMENTATION"/>
-        <UsedIn Val="SIMULATION"/>
-      </File>
-      <File Name="synth\dut_packaging.vhd" Type="VHDL">
-        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
-        <Library Name="xil_defaultlib"/>
-        <UsedIn Val="SYNTHESIS"/>
-      </File>
-      <File Name="sim\dut_packaging.vhd" Type="VHDL">
-        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
-        <Library Name="xil_defaultlib"/>
-        <UsedIn Val="SIMULATION"/>
-      </File>
-      <File Name="dut_packaging_ooc.xdc" Type="XDC">
-        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
-        <Library Name="xil_defaultlib"/>
-        <UsedIn Val="SYNTHESIS"/>
-        <UsedIn Val="IMPLEMENTATION"/>
-        <UsedIn Val="OUT_OF_CONTEXT"/>
-      </File>
-      <File Name="hw_handoff\dut_packaging.hwh" Type="HwHandoff">
-        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
-        <Library Name="xil_defaultlib"/>
-        <UsedIn Val="HW_HANDOFF"/>
-      </File>
-      <File Name="hw_handoff\dut_packaging_bd.tcl">
-        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
-        <Library Name="xil_defaultlib"/>
-        <UsedIn Val="HW_HANDOFF"/>
-      </File>
-      <File Name="synth\dut_packaging.hwdef">
-        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
-        <Library Name="xil_defaultlib"/>
-        <UsedIn Val="HW_HANDOFF"/>
-      </File>
-      <File Name="sim\dut_packaging.protoinst">
-        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
-        <Library Name="xil_defaultlib"/>
-        <UsedIn Val="SIMULATION"/>
-      </File>
-    </FileCollection>
-  </CompositeFile>
-</Root>

src/testbench/dut_packaging/dut_packaging_ooc.xdc

@@ -1,11 +0,0 @@
-################################################################################
-
-# This XDC is used only for OOC mode of synthesis, implementation
-# This constraints file contains default clock frequencies to be used during
-# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
-# This constraints file is not used in normal top-down synthesis (default flow
-# of Vivado)
-################################################################################
-create_clock -name clk_0 -period 10 [get_ports clk_0]
-
-################################################################################

src/testbench/dut_packaging/hdl/dut_packaging_wrapper.vhd

@@ -1,58 +0,0 @@
---Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
---Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
---Date        : Mon Apr 27 15:16:04 2020
---Host        : DESKTOP-L9P0FU6 running 64-bit major release  (build 9200)
---Command     : generate_target dut_packaging_wrapper.bd
---Design      : dut_packaging_wrapper
---Purpose     : IP block netlist
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity dut_packaging_wrapper is
-  port (
-    clk_0 : in STD_LOGIC;
-    errorCode_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
-    fifo_read_0_empty : in STD_LOGIC;
-    fifo_read_0_rd_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
-    fifo_read_0_rd_en : out STD_LOGIC;
-    fifo_write_0_full : in STD_LOGIC;
-    fifo_write_0_wr_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
-    fifo_write_0_wr_en : out STD_LOGIC;
-    rst_0 : in STD_LOGIC;
-    stateOut_0 : out STD_LOGIC_VECTOR ( 3 downto 0 )
-  );
-end dut_packaging_wrapper;
-
-architecture STRUCTURE of dut_packaging_wrapper is
-  component dut_packaging is
-  port (
-    errorCode_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
-    clk_0 : in STD_LOGIC;
-    rst_0 : in STD_LOGIC;
-    stateOut_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
-    fifo_write_0_wr_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
-    fifo_write_0_wr_en : out STD_LOGIC;
-    fifo_write_0_full : in STD_LOGIC;
-    fifo_read_0_rd_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
-    fifo_read_0_rd_en : out STD_LOGIC;
-    fifo_read_0_empty : in STD_LOGIC
-  );
-  end component dut_packaging;
-begin
-dut_packaging_i: component dut_packaging
-     port map (
-      clk_0 => clk_0,
-      errorCode_0(3 downto 0) => errorCode_0(3 downto 0),
-      fifo_read_0_empty => fifo_read_0_empty,
-      fifo_read_0_rd_data(31 downto 0) => fifo_read_0_rd_data(31 downto 0),
-      fifo_read_0_rd_en => fifo_read_0_rd_en,
-      fifo_write_0_full => fifo_write_0_full,
-      fifo_write_0_wr_data(31 downto 0) => fifo_write_0_wr_data(31 downto 0),
-      fifo_write_0_wr_en => fifo_write_0_wr_en,
-      rst_0 => rst_0,
-      stateOut_0(3 downto 0) => stateOut_0(3 downto 0)
-    );
-end STRUCTURE;

src/testbench/dut_packaging/hw_handoff/dut_packaging.hwh

@@ -1,155 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Mon Apr 27 15:16:05 2020" VIVADOVERSION="2018.3">
-
-  <SYSTEMINFO ARCH="artix7" DEVICE="7a100t" NAME="dut_packaging" PACKAGE="csg324" SPEEDGRADE="-1"/>
-
-  <EXTERNALPORTS>
-    <PORT DIR="O" LEFT="3" NAME="errorCode_0" RIGHT="0" SIGIS="undef" SIGNAME="packaging_0_errorCode">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="packaging_0" PORT="errorCode"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="clk_0" SIGIS="clk" SIGNAME="External_Ports_clk_0">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="packaging_0" PORT="clk"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" NAME="rst_0" SIGIS="rst" SIGNAME="External_Ports_rst_0">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="packaging_0" PORT="rst"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="O" LEFT="3" NAME="stateOut_0" RIGHT="0" SIGIS="undef" SIGNAME="packaging_0_stateOut">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="packaging_0" PORT="stateOut"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="O" LEFT="31" NAME="fifo_write_0_wr_data" RIGHT="0" SIGIS="undef" SIGNAME="packaging_0_outData">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="packaging_0" PORT="outData"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="O" NAME="fifo_write_0_wr_en" SIGIS="undef" SIGNAME="packaging_0_outWrEn">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="packaging_0" PORT="outWrEn"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" NAME="fifo_write_0_full" SIGIS="undef" SIGNAME="packaging_0_outputFull">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="packaging_0" PORT="outputFull"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" LEFT="31" NAME="fifo_read_0_rd_data" RIGHT="0" SIGIS="undef" SIGNAME="packaging_0_inputStream">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="packaging_0" PORT="inputStream"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="O" NAME="fifo_read_0_rd_en" SIGIS="undef" SIGNAME="packaging_0_inpRdEn">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="packaging_0" PORT="inpRdEn"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" NAME="fifo_read_0_empty" SIGIS="undef" SIGNAME="packaging_0_inputEmpty">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="packaging_0" PORT="inputEmpty"/>
-      </CONNECTIONS>
-    </PORT>
-  </EXTERNALPORTS>
-
-  <EXTERNALINTERFACES>
-    <BUSINTERFACE BUSNAME="packaging_0_fifo_write" NAME="fifo_write_0" TYPE="INITIATOR">
-      <PORTMAPS>
-        <PORTMAP LOGICAL="WR_DATA" PHYSICAL="fifo_write_0_wr_data"/>
-        <PORTMAP LOGICAL="WR_EN" PHYSICAL="fifo_write_0_wr_en"/>
-        <PORTMAP LOGICAL="FULL" PHYSICAL="fifo_write_0_full"/>
-      </PORTMAPS>
-    </BUSINTERFACE>
-    <BUSINTERFACE BUSNAME="packaging_0_fifo_read" NAME="fifo_read_0" TYPE="INITIATOR">
-      <PORTMAPS>
-        <PORTMAP LOGICAL="RD_DATA" PHYSICAL="fifo_read_0_rd_data"/>
-        <PORTMAP LOGICAL="RD_EN" PHYSICAL="fifo_read_0_rd_en"/>
-        <PORTMAP LOGICAL="EMPTY" PHYSICAL="fifo_read_0_empty"/>
-      </PORTMAPS>
-    </BUSINTERFACE>
-  </EXTERNALINTERFACES>
-
-  <MODULES>
-    <MODULE COREREVISION="1" FULLNAME="/packaging_0" HWVERSION="3.0" INSTANCE="packaging_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="packaging" VLNV="user.org:user:packaging:3.0">
-      <DOCUMENTS/>
-      <PARAMETERS>
-        <PARAMETER NAME="busWidth" VALUE="32"/>
-        <PARAMETER NAME="Component_Name" VALUE="dut_packaging_packaging_0_0"/>
-        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="clk" SIGIS="clk" SIGNAME="External_Ports_clk_0">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External_Ports" PORT="clk_0"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" NAME="rst" SIGIS="rst" SIGNAME="External_Ports_rst_0">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External_Ports" PORT="rst_0"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" LEFT="31" NAME="inputStream" RIGHT="0" SIGIS="undef" SIGNAME="packaging_0_inputStream">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="dut_packaging_imp" PORT="fifo_read_0_rd_data"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" NAME="inpRdEn" SIGIS="undef" SIGNAME="packaging_0_inpRdEn">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="dut_packaging_imp" PORT="fifo_read_0_rd_en"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" NAME="inputEmpty" SIGIS="undef" SIGNAME="packaging_0_inputEmpty">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="dut_packaging_imp" PORT="fifo_read_0_empty"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" LEFT="31" NAME="outData" RIGHT="0" SIGIS="undef" SIGNAME="packaging_0_outData">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="dut_packaging_imp" PORT="fifo_write_0_wr_data"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" NAME="outWrEn" SIGIS="undef" SIGNAME="packaging_0_outWrEn">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="dut_packaging_imp" PORT="fifo_write_0_wr_en"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" NAME="outputFull" SIGIS="undef" SIGNAME="packaging_0_outputFull">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="dut_packaging_imp" PORT="fifo_write_0_full"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" LEFT="3" NAME="errorCode" RIGHT="0" SIGIS="undef" SIGNAME="packaging_0_errorCode">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External_Ports" PORT="errorCode_0"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" LEFT="3" NAME="stateOut" RIGHT="0" SIGIS="undef" SIGNAME="packaging_0_stateOut">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External_Ports" PORT="stateOut_0"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="packaging_0_fifo_read" NAME="fifo_read" TYPE="INITIATOR" VLNV="xilinx.com:interface:fifo_read:1.0">
-          <PORTMAPS>
-            <PORTMAP LOGICAL="RD_DATA" PHYSICAL="inputStream"/>
-            <PORTMAP LOGICAL="RD_EN" PHYSICAL="inpRdEn"/>
-            <PORTMAP LOGICAL="EMPTY" PHYSICAL="inputEmpty"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="packaging_0_fifo_write" NAME="fifo_write" TYPE="INITIATOR" VLNV="xilinx.com:interface:fifo_write:1.0">
-          <PORTMAPS>
-            <PORTMAP LOGICAL="WR_DATA" PHYSICAL="outData"/>
-            <PORTMAP LOGICAL="WR_EN" PHYSICAL="outWrEn"/>
-            <PORTMAP LOGICAL="FULL" PHYSICAL="outputFull"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-    </MODULE>
-  </MODULES>
-
-</EDKSYSTEM>

src/testbench/dut_packaging/hw_handoff/dut_packaging_bd.tcl

@@ -1,196 +0,0 @@
-
-################################################################
-# This is a generated script based on design: dut_packaging
-#
-# Though there are limitations about the generated script,
-# the main purpose of this utility is to make learning
-# IP Integrator Tcl commands easier.
-################################################################
-
-namespace eval _tcl {
-proc get_script_folder {} {
-   set script_path [file normalize [info script]]
-   set script_folder [file dirname $script_path]
-   return $script_folder
-}
-}
-variable script_folder
-set script_folder [_tcl::get_script_folder]
-
-################################################################
-# Check if script is running in correct Vivado version.
-################################################################
-set scripts_vivado_version 2018.3
-set current_vivado_version [version -short]
-
-if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
-   puts ""
-   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
-
-   return 1
-}
-
-################################################################
-# START
-################################################################
-
-# To test this script, run the following commands from Vivado Tcl console:
-# source dut_packaging_script.tcl
-
-# If there is no project opened, this script will create a
-# project, but make sure you do not have an existing project
-# <./myproj/project_1.xpr> in the current working folder.
-
-set list_projs [get_projects -quiet]
-if { $list_projs eq "" } {
-   create_project project_1 myproj -part xc7a100tcsg324-1
-}
-
-
-# CHANGE DESIGN NAME HERE
-variable design_name
-set design_name dut_packaging
-
-# This script was generated for a remote BD. To create a non-remote design,
-# change the variable <run_remote_bd_flow> to <0>.
-
-set run_remote_bd_flow 1
-if { $run_remote_bd_flow == 1 } {
-  # Set the reference directory for source file relative paths (by default 
-  # the value is script directory path)
-  set origin_dir ./src/testbench
-
-  # Use origin directory path location variable, if specified in the tcl shell
-  if { [info exists ::origin_dir_loc] } {
-     set origin_dir $::origin_dir_loc
-  }
-
-  set str_bd_folder [file normalize ${origin_dir}]
-  set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd
-
-  # Check if remote design exists on disk
-  if { [file exists $str_bd_filepath ] == 1 } {
-     catch {common::send_msg_id "BD_TCL-110" "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
-     common::send_msg_id "BD_TCL-008" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
-     common::send_msg_id "BD_TCL-009" "INFO" "Also make sure there is no design <$design_name> existing in your current project."
-
-     return 1
-  }
-
-  # Check if design exists in memory
-  set list_existing_designs [get_bd_designs -quiet $design_name]
-  if { $list_existing_designs ne "" } {
-     catch {common::send_msg_id "BD_TCL-111" "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
-
-     common::send_msg_id "BD_TCL-010" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
-
-     return 1
-  }
-
-  # Check if design exists on disk within project
-  set list_existing_designs [get_files -quiet */${design_name}.bd]
-  if { $list_existing_designs ne "" } {
-     catch {common::send_msg_id "BD_TCL-112" "ERROR" "The design <$design_name> already exists in this project at location:
-    $list_existing_designs"}
-     catch {common::send_msg_id "BD_TCL-113" "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
-
-     common::send_msg_id "BD_TCL-011" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
-
-     return 1
-  }
-
-  # Now can create the remote BD
-  # NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd>
-  create_bd_design -dir $str_bd_folder $design_name
-} else {
-
-  # Create regular design
-  if { [catch {create_bd_design $design_name} errmsg] } {
-     common::send_msg_id "BD_TCL-012" "INFO" "Please set a different value to variable <design_name>."
-
-     return 1
-  }
-}
-
-current_bd_design $design_name
-
-##################################################################
-# DESIGN PROCs
-##################################################################
-
-
-
-# Procedure to create entire design; Provide argument to make
-# procedure reusable. If parentCell is "", will use root.
-proc create_root_design { parentCell } {
-
-  variable script_folder
-  variable design_name
-
-  if { $parentCell eq "" } {
-     set parentCell [get_bd_cells /]
-  }
-
-  # Get object for parentCell
-  set parentObj [get_bd_cells $parentCell]
-  if { $parentObj == "" } {
-     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
-     return
-  }
-
-  # Make sure parentObj is hier blk
-  set parentType [get_property TYPE $parentObj]
-  if { $parentType ne "hier" } {
-     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
-     return
-  }
-
-  # Save current instance; Restore later
-  set oldCurInst [current_bd_instance .]
-
-  # Set parent object as current
-  current_bd_instance $parentObj
-
-
-  # Create interface ports
-  set fifo_read_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:fifo_read_rtl:1.0 fifo_read_0 ]
-  set fifo_write_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:fifo_write_rtl:1.0 fifo_write_0 ]
-
-  # Create ports
-  set clk_0 [ create_bd_port -dir I -type clk clk_0 ]
-  set errorCode_0 [ create_bd_port -dir O -from 3 -to 0 errorCode_0 ]
-  set rst_0 [ create_bd_port -dir I -type rst rst_0 ]
-  set stateOut_0 [ create_bd_port -dir O -from 3 -to 0 stateOut_0 ]
-
-  # Create instance: packaging_0, and set properties
-  set packaging_0 [ create_bd_cell -type ip -vlnv user.org:user:packaging:3.0 packaging_0 ]
-
-  # Create interface connections
-  connect_bd_intf_net -intf_net packaging_0_fifo_read [get_bd_intf_ports fifo_read_0] [get_bd_intf_pins packaging_0/fifo_read]
-  connect_bd_intf_net -intf_net packaging_0_fifo_write [get_bd_intf_ports fifo_write_0] [get_bd_intf_pins packaging_0/fifo_write]
-
-  # Create port connections
-  connect_bd_net -net clk_0_1 [get_bd_ports clk_0] [get_bd_pins packaging_0/clk]
-  connect_bd_net -net packaging_0_errorCode [get_bd_ports errorCode_0] [get_bd_pins packaging_0/errorCode]
-  connect_bd_net -net packaging_0_stateOut [get_bd_ports stateOut_0] [get_bd_pins packaging_0/stateOut]
-  connect_bd_net -net rst_0_1 [get_bd_ports rst_0] [get_bd_pins packaging_0/rst]
-
-  # Create address segments
-
-
-  # Restore current instance
-  current_bd_instance $oldCurInst
-
-  validate_bd_design
-  save_bd_design
-}
-# End of create_root_design()
-
-
-##################################################################
-# MAIN FLOW
-##################################################################
-
-create_root_design ""
-
-

src/testbench/dut_packaging/ip/dut_packaging_packaging_0_0/dut_packaging_packaging_0_0.xci

@@ -1,52 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-  <spirit:vendor>xilinx.com</spirit:vendor>
-  <spirit:library>xci</spirit:library>
-  <spirit:name>unknown</spirit:name>
-  <spirit:version>1.0</spirit:version>
-  <spirit:componentInstances>
-    <spirit:componentInstance>
-      <spirit:instanceName>dut_packaging_packaging_0_0</spirit:instanceName>
-      <spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="packaging" spirit:version="3.0"/>
-      <spirit:configurableElementValues>
-        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
-        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">dut_packaging_clk_0</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.INSERT_VIP">0</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.busWidth">32</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">dut_packaging_packaging_0_0</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.busWidth">32</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100t</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">csg324</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
-        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2018.3</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
-      </spirit:configurableElementValues>
-      <spirit:vendorExtensions>
-        <xilinx:componentInstanceExtensions>
-          <xilinx:configElementInfos>
-            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
-          </xilinx:configElementInfos>
-        </xilinx:componentInstanceExtensions>
-      </spirit:vendorExtensions>
-    </spirit:componentInstance>
-  </spirit:componentInstances>
-</spirit:design>

src/testbench/dut_packaging/ip/dut_packaging_packaging_0_0/dut_packaging_packaging_0_0.xml

@@ -1,512 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-  <spirit:vendor>user.org</spirit:vendor>
-  <spirit:library>customized_ip</spirit:library>
-  <spirit:name>dut_packaging_packaging_0_0</spirit:name>
-  <spirit:version>1.0</spirit:version>
-  <spirit:busInterfaces>
-    <spirit:busInterface>
-      <spirit:name>rst</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RST</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>rst</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>POLARITY</spirit:name>
-          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RST.POLARITY">ACTIVE_LOW</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>none</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>INSERT_VIP</spirit:name>
-          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.INSERT_VIP">0</spirit:value>
-          <spirit:vendorExtensions>
-            <xilinx:parameterInfo>
-              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
-            </xilinx:parameterInfo>
-          </spirit:vendorExtensions>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>clk</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>CLK</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>clk</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
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src/testbench/dut_packaging/ip/dut_packaging_packaging_0_0/sim/dut_packaging_packaging_0_0.vhd

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--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
--- DO NOT MODIFY THIS FILE.
-
--- IP VLNV: user.org:user:packaging:3.0
--- IP Revision: 1
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY dut_packaging_packaging_0_0 IS
-  PORT (
-    clk : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    inputStream : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-    inpRdEn : OUT STD_LOGIC;
-    inputEmpty : IN STD_LOGIC;
-    outData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    outWrEn : OUT STD_LOGIC;
-    outputFull : IN STD_LOGIC;
-    errorCode : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-    stateOut : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
-  );
-END dut_packaging_packaging_0_0;
-
-ARCHITECTURE dut_packaging_packaging_0_0_arch OF dut_packaging_packaging_0_0 IS
-  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
-  ATTRIBUTE DowngradeIPIdentifiedWarnings OF dut_packaging_packaging_0_0_arch: ARCHITECTURE IS "yes";
-  COMPONENT packaging IS
-    GENERIC (
-      busWidth : INTEGER
-    );
-    PORT (
-      clk : IN STD_LOGIC;
-      rst : IN STD_LOGIC;
-      inputStream : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-      inpRdEn : OUT STD_LOGIC;
-      inputEmpty : IN STD_LOGIC;
-      outData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-      outWrEn : OUT STD_LOGIC;
-      outputFull : IN STD_LOGIC;
-      errorCode : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-      stateOut : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
-    );
-  END COMPONENT packaging;
-  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
-  ATTRIBUTE IP_DEFINITION_SOURCE OF dut_packaging_packaging_0_0_arch: ARCHITECTURE IS "package_project";
-  ATTRIBUTE X_INTERFACE_INFO : STRING;
-  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
-  ATTRIBUTE X_INTERFACE_INFO OF outputFull: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 fifo_write FULL";
-  ATTRIBUTE X_INTERFACE_INFO OF outWrEn: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 fifo_write WR_EN";
-  ATTRIBUTE X_INTERFACE_INFO OF outData: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 fifo_write WR_DATA";
-  ATTRIBUTE X_INTERFACE_INFO OF inputEmpty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 fifo_read EMPTY";
-  ATTRIBUTE X_INTERFACE_INFO OF inpRdEn: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 fifo_read RD_EN";
-  ATTRIBUTE X_INTERFACE_INFO OF inputStream: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 fifo_read RD_DATA";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF rst: SIGNAL IS "XIL_INTERFACENAME rst, POLARITY ACTIVE_LOW, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
-  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN dut_packaging_clk_0, INSERT_VIP 0";
-  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
-BEGIN
-  U0 : packaging
-    GENERIC MAP (
-      busWidth => 32
-    )
-    PORT MAP (
-      clk => clk,
-      rst => rst,
-      inputStream => inputStream,
-      inpRdEn => inpRdEn,
-      inputEmpty => inputEmpty,
-      outData => outData,
-      outWrEn => outWrEn,
-      outputFull => outputFull,
-      errorCode => errorCode,
-      stateOut => stateOut
-    );
-END dut_packaging_packaging_0_0_arch;

src/testbench/dut_packaging/ipshared/22b5/src/Block_proc.vhd

@@ -1,321 +0,0 @@
--- ==============================================================
--- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
--- Version: 2018.3
--- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--- 
--- ===========================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity Block_proc is
-port (
-    ap_clk : IN STD_LOGIC;
-    ap_rst : IN STD_LOGIC;
-    ap_start : IN STD_LOGIC;
-    start_full_n : IN STD_LOGIC;
-    ap_done : OUT STD_LOGIC;
-    ap_continue : IN STD_LOGIC;
-    ap_idle : OUT STD_LOGIC;
-    ap_ready : OUT STD_LOGIC;
-    start_out : OUT STD_LOGIC;
-    start_write : OUT STD_LOGIC;
-    width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    width_empty_n : IN STD_LOGIC;
-    width_read : OUT STD_LOGIC;
-    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    height_empty_n : IN STD_LOGIC;
-    height_read : OUT STD_LOGIC;
-    width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    width_out_full_n : IN STD_LOGIC;
-    width_out_write : OUT STD_LOGIC;
-    height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    height_out_full_n : IN STD_LOGIC;
-    height_out_write : OUT STD_LOGIC;
-    vconv_xlim_out_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    vconv_xlim_out_out_full_n : IN STD_LOGIC;
-    vconv_xlim_out_out_write : OUT STD_LOGIC );
-end;
-
-
-architecture behav of Block_proc is 
-    constant ap_const_logic_1 : STD_LOGIC := '1';
-    constant ap_const_logic_0 : STD_LOGIC := '0';
-    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
-    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
-    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
-    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
-    constant ap_const_lv32_FFFFFFF6 : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111110110";
-    constant ap_const_boolean_1 : BOOLEAN := true;
-
-    signal real_start : STD_LOGIC;
-    signal start_once_reg : STD_LOGIC := '0';
-    signal ap_done_reg : STD_LOGIC := '0';
-    signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
-    attribute fsm_encoding : string;
-    attribute fsm_encoding of ap_CS_fsm : signal is "none";
-    signal ap_CS_fsm_state1 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
-    signal internal_ap_ready : STD_LOGIC;
-    signal width_blk_n : STD_LOGIC;
-    signal height_blk_n : STD_LOGIC;
-    signal width_out_blk_n : STD_LOGIC;
-    signal ap_CS_fsm_state2 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
-    signal height_out_blk_n : STD_LOGIC;
-    signal vconv_xlim_out_out_blk_n : STD_LOGIC;
-    signal width_read_reg_69 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_state1 : BOOLEAN;
-    signal height_read_reg_75 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_state2 : BOOLEAN;
-    signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
-
-
-begin
-
-
-
-
-    ap_CS_fsm_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_CS_fsm <= ap_ST_fsm_state1;
-            else
-                ap_CS_fsm <= ap_NS_fsm;
-            end if;
-        end if;
-    end process;
-
-
-    ap_done_reg_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_done_reg <= ap_const_logic_0;
-            else
-                if ((ap_continue = ap_const_logic_1)) then 
-                    ap_done_reg <= ap_const_logic_0;
-                elsif ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
-                    ap_done_reg <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    start_once_reg_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                start_once_reg <= ap_const_logic_0;
-            else
-                if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then 
-                    start_once_reg <= ap_const_logic_1;
-                elsif ((internal_ap_ready = ap_const_logic_1)) then 
-                    start_once_reg <= ap_const_logic_0;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                height_read_reg_75 <= height_dout;
-                width_read_reg_69 <= width_dout;
-            end if;
-        end if;
-    end process;
-
-    ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, width_empty_n, height_empty_n, width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
-    begin
-        case ap_CS_fsm is
-            when ap_ST_fsm_state1 => 
-                if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                    ap_NS_fsm <= ap_ST_fsm_state2;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_state1;
-                end if;
-            when ap_ST_fsm_state2 => 
-                if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
-                    ap_NS_fsm <= ap_ST_fsm_state1;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_state2;
-                end if;
-            when others =>  
-                ap_NS_fsm <= "XX";
-        end case;
-    end process;
-    ap_CS_fsm_state1 <= ap_CS_fsm(0);
-    ap_CS_fsm_state2 <= ap_CS_fsm(1);
-
-    ap_block_state1_assign_proc : process(real_start, ap_done_reg, width_empty_n, height_empty_n)
-    begin
-                ap_block_state1 <= ((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
-    end process;
-
-
-    ap_block_state2_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n)
-    begin
-                ap_block_state2 <= ((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0));
-    end process;
-
-
-    ap_done_assign_proc : process(ap_done_reg, width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
-            ap_done <= ap_const_logic_1;
-        else 
-            ap_done <= ap_done_reg;
-        end if; 
-    end process;
-
-
-    ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
-    begin
-        if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            ap_idle <= ap_const_logic_1;
-        else 
-            ap_idle <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    ap_ready <= internal_ap_ready;
-
-    height_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_blk_n <= height_empty_n;
-        else 
-            height_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    height_out_blk_n_assign_proc : process(height_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-            height_out_blk_n <= height_out_full_n;
-        else 
-            height_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    height_out_din <= height_read_reg_75;
-
-    height_out_write_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
-            height_out_write <= ap_const_logic_1;
-        else 
-            height_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    height_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_read <= ap_const_logic_1;
-        else 
-            height_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    internal_ap_ready_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
-            internal_ap_ready <= ap_const_logic_1;
-        else 
-            internal_ap_ready <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
-    begin
-        if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then 
-            real_start <= ap_const_logic_0;
-        else 
-            real_start <= ap_start;
-        end if; 
-    end process;
-
-    start_out <= real_start;
-
-    start_write_assign_proc : process(real_start, start_once_reg)
-    begin
-        if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then 
-            start_write <= ap_const_logic_1;
-        else 
-            start_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    vconv_xlim_out_out_blk_n_assign_proc : process(vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-            vconv_xlim_out_out_blk_n <= vconv_xlim_out_out_full_n;
-        else 
-            vconv_xlim_out_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    vconv_xlim_out_out_din <= std_logic_vector(unsigned(width_read_reg_69) + unsigned(ap_const_lv32_FFFFFFF6));
-
-    vconv_xlim_out_out_write_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
-            vconv_xlim_out_out_write <= ap_const_logic_1;
-        else 
-            vconv_xlim_out_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    width_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_blk_n <= width_empty_n;
-        else 
-            width_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    width_out_blk_n_assign_proc : process(width_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-            width_out_blk_n <= width_out_full_n;
-        else 
-            width_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    width_out_din <= width_read_reg_69;
-
-    width_out_write_assign_proc : process(width_out_full_n, height_out_full_n, vconv_xlim_out_out_full_n, ap_CS_fsm_state2)
-    begin
-        if ((not(((vconv_xlim_out_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
-            width_out_write <= ap_const_logic_1;
-        else 
-            width_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    width_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_read <= ap_const_logic_1;
-        else 
-            width_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-end behav;

src/testbench/dut_packaging/ipshared/22b5/src/Loop_Border_proc.vhd

@@ -1,896 +0,0 @@
--- ==============================================================
--- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
--- Version: 2018.3
--- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--- 
--- ===========================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity Loop_Border_proc is
-port (
-    ap_clk : IN STD_LOGIC;
-    ap_rst : IN STD_LOGIC;
-    ap_start : IN STD_LOGIC;
-    ap_done : OUT STD_LOGIC;
-    ap_continue : IN STD_LOGIC;
-    ap_idle : OUT STD_LOGIC;
-    ap_ready : OUT STD_LOGIC;
-    width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    width_empty_n : IN STD_LOGIC;
-    width_read : OUT STD_LOGIC;
-    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    height_empty_n : IN STD_LOGIC;
-    height_read : OUT STD_LOGIC;
-    dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
-    dst_V_TVALID : OUT STD_LOGIC;
-    dst_V_TREADY : IN STD_LOGIC;
-    vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    vconv_xlim_loc_empty_n : IN STD_LOGIC;
-    vconv_xlim_loc_read : OUT STD_LOGIC;
-    vconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    vconv_V_empty_n : IN STD_LOGIC;
-    vconv_V_read : OUT STD_LOGIC );
-end;
-
-
-architecture behav of Loop_Border_proc is 
-    constant ap_const_logic_1 : STD_LOGIC := '1';
-    constant ap_const_logic_0 : STD_LOGIC := '0';
-    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
-    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
-    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
-    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
-    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
-    constant ap_const_boolean_1 : BOOLEAN := true;
-    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
-    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
-    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
-    constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
-    constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
-    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
-    constant ap_const_boolean_0 : BOOLEAN := false;
-    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
-    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
-    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
-    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
-    constant ap_const_lv32_FFFFFFF5 : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111110101";
-    constant ap_const_lv32_FFFFFFFA : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111010";
-    constant ap_const_lv32_FFFFFFFB : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111011";
-    constant ap_const_lv10_5 : STD_LOGIC_VECTOR (9 downto 0) := "0000000101";
-    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
-    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
-    constant ap_const_lv10_6 : STD_LOGIC_VECTOR (9 downto 0) := "0000000110";
-    constant ap_const_lv10_3FB : STD_LOGIC_VECTOR (9 downto 0) := "1111111011";
-    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
-
-    signal ap_done_reg : STD_LOGIC := '0';
-    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
-    attribute fsm_encoding : string;
-    attribute fsm_encoding of ap_CS_fsm : signal is "none";
-    signal ap_CS_fsm_state1 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
-    signal dst_V_1_data_out : STD_LOGIC_VECTOR (31 downto 0);
-    signal dst_V_1_vld_in : STD_LOGIC;
-    signal dst_V_1_vld_out : STD_LOGIC;
-    signal dst_V_1_ack_in : STD_LOGIC;
-    signal dst_V_1_ack_out : STD_LOGIC;
-    signal dst_V_1_payload_A : STD_LOGIC_VECTOR (31 downto 0);
-    signal dst_V_1_payload_B : STD_LOGIC_VECTOR (31 downto 0);
-    signal dst_V_1_sel_rd : STD_LOGIC := '0';
-    signal dst_V_1_sel_wr : STD_LOGIC := '0';
-    signal dst_V_1_sel : STD_LOGIC;
-    signal dst_V_1_load_A : STD_LOGIC;
-    signal dst_V_1_load_B : STD_LOGIC;
-    signal dst_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
-    signal dst_V_1_state_cmp_full : STD_LOGIC;
-    signal width_blk_n : STD_LOGIC;
-    signal height_blk_n : STD_LOGIC;
-    signal dst_V_TDATA_blk_n : STD_LOGIC;
-    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
-    signal ap_block_pp0_stage0 : BOOLEAN;
-    signal exitcond_flatten_reg_499 : STD_LOGIC_VECTOR (0 downto 0);
-    signal exitcond_flatten_reg_499_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
-    signal exitcond_flatten_reg_499_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal vconv_xlim_loc_blk_n : STD_LOGIC;
-    signal vconv_V_blk_n : STD_LOGIC;
-    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
-    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
-    signal brmerge_mid2_reg_516 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_24_i_i_reg_525 : STD_LOGIC_VECTOR (0 downto 0);
-    signal indvar_flatten_reg_145 : STD_LOGIC_VECTOR (63 downto 0);
-    signal i6_0_i_i_i_reg_156 : STD_LOGIC_VECTOR (9 downto 0);
-    signal j_0_i_i_i_reg_167 : STD_LOGIC_VECTOR (9 downto 0);
-    signal width_read_reg_459 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_state1 : BOOLEAN;
-    signal height_read_reg_467 : STD_LOGIC_VECTOR (31 downto 0);
-    signal vconv_xlim_loc_read_reg_473 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_9_i_i_fu_178_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_9_i_i_reg_478 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_CS_fsm_state2 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
-    signal tmp_i_i_fu_183_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_i_i_reg_483 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_7_i_i_fu_188_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_7_i_i_reg_488 : STD_LOGIC_VECTOR (31 downto 0);
-    signal bound_fu_199_p2 : STD_LOGIC_VECTOR (63 downto 0);
-    signal bound_reg_494 : STD_LOGIC_VECTOR (63 downto 0);
-    signal exitcond_flatten_fu_247_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
-    signal ap_predicate_op59_read_state4 : BOOLEAN;
-    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
-    signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
-    signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
-    signal ap_block_state6_io : BOOLEAN;
-    signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
-    signal ap_block_state7_io : BOOLEAN;
-    signal ap_block_pp0_stage0_11001 : BOOLEAN;
-    signal exitcond_flatten_reg_499_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal indvar_flatten_next_fu_252_p2 : STD_LOGIC_VECTOR (63 downto 0);
-    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
-    signal j_0_i_i_i_mid2_fu_268_p3 : STD_LOGIC_VECTOR (9 downto 0);
-    signal j_0_i_i_i_mid2_reg_508 : STD_LOGIC_VECTOR (9 downto 0);
-    signal brmerge_mid2_fu_305_p3 : STD_LOGIC_VECTOR (0 downto 0);
-    signal brmerge_mid2_reg_516_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal i6_0_i_i_i_mid2_fu_317_p3 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp_24_i_i_fu_325_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_28_i_i_fu_330_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_28_i_i_reg_529 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_28_i_i_reg_529_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_30_i_i_fu_335_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_30_i_i_reg_534 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_30_i_i_reg_534_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_30_i_i_reg_534_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal j_fu_340_p2 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp_27_i_i_fu_355_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_27_i_i_reg_544 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_29_i_i_fu_360_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_29_i_i_reg_549 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_29_i_i_reg_549_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal borderbuf_q1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal pix_out_7_reg_560 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
-    signal pix_out_8_fu_431_p3 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_pp0_stage0_subdone : BOOLEAN;
-    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
-    signal borderbuf_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal borderbuf_ce0 : STD_LOGIC;
-    signal borderbuf_we0 : STD_LOGIC;
-    signal borderbuf_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal borderbuf_ce1 : STD_LOGIC;
-    signal tmp_26_i_i_fu_346_p1 : STD_LOGIC_VECTOR (63 downto 0);
-    signal tmp_32_i_i_fu_370_p1 : STD_LOGIC_VECTOR (63 downto 0);
-    signal r_edge_pix_fu_74 : STD_LOGIC_VECTOR (31 downto 0);
-    signal pix_out_fu_78 : STD_LOGIC_VECTOR (31 downto 0);
-    signal l_edge_pix_fu_391_p3 : STD_LOGIC_VECTOR (31 downto 0);
-    signal pix_out_1_fu_82 : STD_LOGIC_VECTOR (31 downto 0);
-    signal pix_in_2_l_edge_pix_s_fu_384_p3 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_pp0_stage0_01001 : BOOLEAN;
-    signal bound_fu_199_p0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal bound_fu_199_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal i6_0_i_cast_i_i_mid1_fu_205_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal notrhs_fu_221_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal notlhs_fu_215_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_17_i_i_fu_209_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal brmerge_i_i_i_not_fu_226_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal j_0_i_cast_i_i_fu_238_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal i_fu_258_p2 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp_22_i_i_fu_242_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal i6_0_i_cast_i_i_fu_264_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal notrhs_mid1_fu_288_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal notlhs_mid1_fu_282_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_17_i_i_mid1_fu_276_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal brmerge_i_i_i_not_mi_fu_293_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal brmerge_fu_232_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal brmerge_mid1_fu_299_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal j_0_i_cast_i_i_mid2_s_fu_313_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_31_i_i_fu_365_p2 : STD_LOGIC_VECTOR (9 downto 0);
-    signal sel_tmp_fu_414_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal sel_tmp1_fu_419_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal pix_out_3_fu_424_p3 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_CS_fsm_state8 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
-    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
-    signal ap_idle_pp0 : STD_LOGIC;
-    signal ap_enable_pp0 : STD_LOGIC;
-    signal bound_fu_199_p00 : STD_LOGIC_VECTOR (63 downto 0);
-    signal bound_fu_199_p10 : STD_LOGIC_VECTOR (63 downto 0);
-
-    component Loop_Border_proc_borderbuf IS
-    generic (
-        DataWidth : INTEGER;
-        AddressRange : INTEGER;
-        AddressWidth : INTEGER );
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        address0 : IN STD_LOGIC_VECTOR (9 downto 0);
-        ce0 : IN STD_LOGIC;
-        we0 : IN STD_LOGIC;
-        d0 : IN STD_LOGIC_VECTOR (31 downto 0);
-        address1 : IN STD_LOGIC_VECTOR (9 downto 0);
-        ce1 : IN STD_LOGIC;
-        q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
-    end component;
-
-
-
-begin
-    borderbuf_U : component Loop_Border_proc_borderbuf
-    generic map (
-        DataWidth => 32,
-        AddressRange => 662,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => borderbuf_address0,
-        ce0 => borderbuf_ce0,
-        we0 => borderbuf_we0,
-        d0 => vconv_V_dout,
-        address1 => borderbuf_address1,
-        ce1 => borderbuf_ce1,
-        q1 => borderbuf_q1);
-
-
-
-
-
-    ap_CS_fsm_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_CS_fsm <= ap_ST_fsm_state1;
-            else
-                ap_CS_fsm <= ap_NS_fsm;
-            end if;
-        end if;
-    end process;
-
-
-    ap_done_reg_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_done_reg <= ap_const_logic_0;
-            else
-                if ((ap_continue = ap_const_logic_1)) then 
-                    ap_done_reg <= ap_const_logic_0;
-                elsif (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
-                    ap_done_reg <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
-            else
-                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
-                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then 
-                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
-                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
-                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
-                    end if;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                    ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    dst_V_1_sel_rd_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                dst_V_1_sel_rd <= ap_const_logic_0;
-            else
-                if (((dst_V_1_ack_out = ap_const_logic_1) and (dst_V_1_vld_out = ap_const_logic_1))) then 
-                                        dst_V_1_sel_rd <= not(dst_V_1_sel_rd);
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    dst_V_1_sel_wr_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                dst_V_1_sel_wr <= ap_const_logic_0;
-            else
-                if (((dst_V_1_ack_in = ap_const_logic_1) and (dst_V_1_vld_in = ap_const_logic_1))) then 
-                                        dst_V_1_sel_wr <= not(dst_V_1_sel_wr);
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    dst_V_1_state_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                dst_V_1_state <= ap_const_lv2_0;
-            else
-                if ((((dst_V_1_state = ap_const_lv2_2) and (dst_V_1_vld_in = ap_const_logic_0)) or ((dst_V_1_state = ap_const_lv2_3) and (dst_V_1_vld_in = ap_const_logic_0) and (dst_V_1_ack_out = ap_const_logic_1)))) then 
-                    dst_V_1_state <= ap_const_lv2_2;
-                elsif ((((dst_V_1_state = ap_const_lv2_1) and (dst_V_1_ack_out = ap_const_logic_0)) or ((dst_V_1_state = ap_const_lv2_3) and (dst_V_1_ack_out = ap_const_logic_0) and (dst_V_1_vld_in = ap_const_logic_1)))) then 
-                    dst_V_1_state <= ap_const_lv2_1;
-                elsif (((not(((dst_V_1_vld_in = ap_const_logic_0) and (dst_V_1_ack_out = ap_const_logic_1))) and not(((dst_V_1_ack_out = ap_const_logic_0) and (dst_V_1_vld_in = ap_const_logic_1))) and (dst_V_1_state = ap_const_lv2_3)) or ((dst_V_1_state = ap_const_lv2_1) and (dst_V_1_ack_out = ap_const_logic_1)) or ((dst_V_1_state = ap_const_lv2_2) and (dst_V_1_vld_in = ap_const_logic_1)))) then 
-                    dst_V_1_state <= ap_const_lv2_3;
-                else 
-                    dst_V_1_state <= ap_const_lv2_2;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    i6_0_i_i_i_reg_156_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-                i6_0_i_i_i_reg_156 <= i6_0_i_i_i_mid2_fu_317_p3;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                i6_0_i_i_i_reg_156 <= ap_const_lv10_0;
-            end if; 
-        end if;
-    end process;
-
-    indvar_flatten_reg_145_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-                indvar_flatten_reg_145 <= indvar_flatten_next_fu_252_p2;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                indvar_flatten_reg_145 <= ap_const_lv64_0;
-            end if; 
-        end if;
-    end process;
-
-    j_0_i_i_i_reg_167_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-                j_0_i_i_i_reg_167 <= j_fu_340_p2;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                j_0_i_i_i_reg_167 <= ap_const_lv10_0;
-            end if; 
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
-                bound_reg_494 <= bound_fu_199_p2;
-                tmp_7_i_i_reg_488 <= tmp_7_i_i_fu_188_p2;
-                tmp_9_i_i_reg_478 <= tmp_9_i_i_fu_178_p2;
-                tmp_i_i_reg_483 <= tmp_i_i_fu_183_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
-                brmerge_mid2_reg_516 <= brmerge_mid2_fu_305_p3;
-                j_0_i_i_i_mid2_reg_508 <= j_0_i_i_i_mid2_fu_268_p3;
-                tmp_30_i_i_reg_534 <= tmp_30_i_i_fu_335_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
-                brmerge_mid2_reg_516_pp0_iter1_reg <= brmerge_mid2_reg_516;
-                exitcond_flatten_reg_499 <= exitcond_flatten_fu_247_p2;
-                exitcond_flatten_reg_499_pp0_iter1_reg <= exitcond_flatten_reg_499;
-                tmp_28_i_i_reg_529_pp0_iter1_reg <= tmp_28_i_i_reg_529;
-                tmp_30_i_i_reg_534_pp0_iter1_reg <= tmp_30_i_i_reg_534;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((dst_V_1_load_A = ap_const_logic_1)) then
-                dst_V_1_payload_A <= pix_out_8_fu_431_p3;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((dst_V_1_load_B = ap_const_logic_1)) then
-                dst_V_1_payload_B <= pix_out_8_fu_431_p3;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
-                exitcond_flatten_reg_499_pp0_iter2_reg <= exitcond_flatten_reg_499_pp0_iter1_reg;
-                exitcond_flatten_reg_499_pp0_iter3_reg <= exitcond_flatten_reg_499_pp0_iter2_reg;
-                tmp_29_i_i_reg_549_pp0_iter2_reg <= tmp_29_i_i_reg_549;
-                tmp_30_i_i_reg_534_pp0_iter2_reg <= tmp_30_i_i_reg_534_pp0_iter1_reg;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                height_read_reg_467 <= height_dout;
-                vconv_xlim_loc_read_reg_473 <= vconv_xlim_loc_dout;
-                width_read_reg_459 <= width_dout;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((brmerge_mid2_reg_516_pp0_iter1_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
-                pix_out_1_fu_82 <= pix_in_2_l_edge_pix_s_fu_384_p3;
-                pix_out_fu_78 <= l_edge_pix_fu_391_p3;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_reg_499_pp0_iter1_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
-                pix_out_7_reg_560 <= borderbuf_q1;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
-                r_edge_pix_fu_74 <= vconv_V_dout;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((brmerge_mid2_fu_305_p3 = ap_const_lv1_1) and (exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
-                tmp_24_i_i_reg_525 <= tmp_24_i_i_fu_325_p2;
-                tmp_28_i_i_reg_529 <= tmp_28_i_i_fu_330_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
-                tmp_27_i_i_reg_544 <= tmp_27_i_i_fu_355_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_reg_499 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
-                tmp_29_i_i_reg_549 <= tmp_29_i_i_fu_360_p2;
-            end if;
-        end if;
-    end process;
-
-    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, width_empty_n, height_empty_n, dst_V_1_ack_in, vconv_xlim_loc_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, exitcond_flatten_fu_247_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_CS_fsm_state8)
-    begin
-        case ap_CS_fsm is
-            when ap_ST_fsm_state1 => 
-                if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                    ap_NS_fsm <= ap_ST_fsm_state2;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_state1;
-                end if;
-            when ap_ST_fsm_state2 => 
-                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-            when ap_ST_fsm_pp0_stage0 => 
-                if ((not(((exitcond_flatten_fu_247_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) and not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0))))) then
-                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-                elsif ((((exitcond_flatten_fu_247_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0)))) then
-                    ap_NS_fsm <= ap_ST_fsm_state8;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-                end if;
-            when ap_ST_fsm_state8 => 
-                if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then
-                    ap_NS_fsm <= ap_ST_fsm_state1;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_state8;
-                end if;
-            when others =>  
-                ap_NS_fsm <= "XXXX";
-        end case;
-    end process;
-    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
-    ap_CS_fsm_state1 <= ap_CS_fsm(0);
-    ap_CS_fsm_state2 <= ap_CS_fsm(1);
-    ap_CS_fsm_state8 <= ap_CS_fsm(3);
-        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_pp0_stage0_01001_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4)
-    begin
-                ap_block_pp0_stage0_01001 <= ((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
-    end process;
-
-
-    ap_block_pp0_stage0_11001_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_state6_io, ap_block_state7_io)
-    begin
-                ap_block_pp0_stage0_11001 <= (((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state7_io) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state6_io) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)));
-    end process;
-
-
-    ap_block_pp0_stage0_subdone_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_state6_io, ap_block_state7_io)
-    begin
-                ap_block_pp0_stage0_subdone <= (((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state7_io) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state6_io) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)));
-    end process;
-
-
-    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
-    begin
-                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
-    end process;
-
-        ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_state4_pp0_stage0_iter1_assign_proc : process(vconv_V_empty_n, ap_predicate_op59_read_state4)
-    begin
-                ap_block_state4_pp0_stage0_iter1 <= ((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1));
-    end process;
-
-        ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_state6_io_assign_proc : process(dst_V_1_ack_in, exitcond_flatten_reg_499_pp0_iter2_reg)
-    begin
-                ap_block_state6_io <= ((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (dst_V_1_ack_in = ap_const_logic_0));
-    end process;
-
-        ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_state7_io_assign_proc : process(dst_V_1_ack_in, exitcond_flatten_reg_499_pp0_iter3_reg)
-    begin
-                ap_block_state7_io <= ((exitcond_flatten_reg_499_pp0_iter3_reg = ap_const_lv1_0) and (dst_V_1_ack_in = ap_const_logic_0));
-    end process;
-
-        ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_flatten_fu_247_p2)
-    begin
-        if ((exitcond_flatten_fu_247_p2 = ap_const_lv1_1)) then 
-            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
-        else 
-            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_done_assign_proc : process(ap_done_reg, dst_V_1_ack_in, ap_CS_fsm_state8)
-    begin
-        if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
-            ap_done <= ap_const_logic_1;
-        else 
-            ap_done <= ap_done_reg;
-        end if; 
-    end process;
-
-    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
-
-    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
-    begin
-        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            ap_idle <= ap_const_logic_1;
-        else 
-            ap_idle <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2)
-    begin
-        if (((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0))) then 
-            ap_idle_pp0 <= ap_const_logic_1;
-        else 
-            ap_idle_pp0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_predicate_op59_read_state4_assign_proc : process(brmerge_mid2_reg_516, tmp_24_i_i_reg_525)
-    begin
-                ap_predicate_op59_read_state4 <= ((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1));
-    end process;
-
-
-    ap_ready_assign_proc : process(dst_V_1_ack_in, ap_CS_fsm_state8)
-    begin
-        if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
-            ap_ready <= ap_const_logic_1;
-        else 
-            ap_ready <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    borderbuf_address0 <= tmp_26_i_i_fu_346_p1(10 - 1 downto 0);
-    borderbuf_address1 <= tmp_32_i_i_fu_370_p1(10 - 1 downto 0);
-
-    borderbuf_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            borderbuf_ce0 <= ap_const_logic_1;
-        else 
-            borderbuf_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    borderbuf_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            borderbuf_ce1 <= ap_const_logic_1;
-        else 
-            borderbuf_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    borderbuf_we0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, brmerge_mid2_reg_516, tmp_24_i_i_reg_525, ap_block_pp0_stage0_11001)
-    begin
-        if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            borderbuf_we0 <= ap_const_logic_1;
-        else 
-            borderbuf_we0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    bound_fu_199_p0 <= bound_fu_199_p00(32 - 1 downto 0);
-    bound_fu_199_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(width_read_reg_459),64));
-    bound_fu_199_p1 <= bound_fu_199_p10(32 - 1 downto 0);
-    bound_fu_199_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(height_read_reg_467),64));
-    bound_fu_199_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_199_p0) * unsigned(bound_fu_199_p1), 64));
-    brmerge_fu_232_p2 <= (tmp_17_i_i_fu_209_p2 or brmerge_i_i_i_not_fu_226_p2);
-    brmerge_i_i_i_not_fu_226_p2 <= (notrhs_fu_221_p2 and notlhs_fu_215_p2);
-    brmerge_i_i_i_not_mi_fu_293_p2 <= (notrhs_mid1_fu_288_p2 and notlhs_mid1_fu_282_p2);
-    brmerge_mid1_fu_299_p2 <= (tmp_17_i_i_mid1_fu_276_p2 or brmerge_i_i_i_not_mi_fu_293_p2);
-    brmerge_mid2_fu_305_p3 <= 
-        brmerge_fu_232_p2 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
-        brmerge_mid1_fu_299_p2;
-    dst_V_1_ack_in <= dst_V_1_state(1);
-    dst_V_1_ack_out <= dst_V_TREADY;
-
-    dst_V_1_data_out_assign_proc : process(dst_V_1_payload_A, dst_V_1_payload_B, dst_V_1_sel)
-    begin
-        if ((dst_V_1_sel = ap_const_logic_1)) then 
-            dst_V_1_data_out <= dst_V_1_payload_B;
-        else 
-            dst_V_1_data_out <= dst_V_1_payload_A;
-        end if; 
-    end process;
-
-    dst_V_1_load_A <= (not(dst_V_1_sel_wr) and dst_V_1_state_cmp_full);
-    dst_V_1_load_B <= (dst_V_1_state_cmp_full and dst_V_1_sel_wr);
-    dst_V_1_sel <= dst_V_1_sel_rd;
-    dst_V_1_state_cmp_full <= '0' when (dst_V_1_state = ap_const_lv2_1) else '1';
-
-    dst_V_1_vld_in_assign_proc : process(ap_enable_reg_pp0_iter3, exitcond_flatten_reg_499_pp0_iter2_reg, ap_block_pp0_stage0_11001)
-    begin
-        if (((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1))) then 
-            dst_V_1_vld_in <= ap_const_logic_1;
-        else 
-            dst_V_1_vld_in <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    dst_V_1_vld_out <= dst_V_1_state(0);
-    dst_V_TDATA <= dst_V_1_data_out;
-
-    dst_V_TDATA_blk_n_assign_proc : process(dst_V_1_state, ap_enable_reg_pp0_iter3, ap_block_pp0_stage0, exitcond_flatten_reg_499_pp0_iter2_reg, ap_enable_reg_pp0_iter4, exitcond_flatten_reg_499_pp0_iter3_reg)
-    begin
-        if ((((exitcond_flatten_reg_499_pp0_iter3_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)))) then 
-            dst_V_TDATA_blk_n <= dst_V_1_state(1);
-        else 
-            dst_V_TDATA_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    dst_V_TVALID <= dst_V_1_state(0);
-    exitcond_flatten_fu_247_p2 <= "1" when (indvar_flatten_reg_145 = bound_reg_494) else "0";
-
-    height_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_blk_n <= height_empty_n;
-        else 
-            height_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    height_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_read <= ap_const_logic_1;
-        else 
-            height_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    i6_0_i_cast_i_i_fu_264_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_fu_258_p2),32));
-    i6_0_i_cast_i_i_mid1_fu_205_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i6_0_i_i_i_reg_156),32));
-    i6_0_i_i_i_mid2_fu_317_p3 <= 
-        i6_0_i_i_i_reg_156 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
-        i_fu_258_p2;
-    i_fu_258_p2 <= std_logic_vector(unsigned(i6_0_i_i_i_reg_156) + unsigned(ap_const_lv10_1));
-    indvar_flatten_next_fu_252_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_145) + unsigned(ap_const_lv64_1));
-    j_0_i_cast_i_i_fu_238_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_reg_167),32));
-    j_0_i_cast_i_i_mid2_s_fu_313_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_mid2_fu_268_p3),32));
-    j_0_i_i_i_mid2_fu_268_p3 <= 
-        j_0_i_i_i_reg_167 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
-        ap_const_lv10_0;
-    j_fu_340_p2 <= std_logic_vector(unsigned(j_0_i_i_i_mid2_fu_268_p3) + unsigned(ap_const_lv10_1));
-    l_edge_pix_fu_391_p3 <= 
-        r_edge_pix_fu_74 when (tmp_28_i_i_reg_529_pp0_iter1_reg(0) = '1') else 
-        pix_out_fu_78;
-    notlhs_fu_215_p2 <= "1" when (unsigned(i6_0_i_i_i_reg_156) > unsigned(ap_const_lv10_5)) else "0";
-    notlhs_mid1_fu_282_p2 <= "1" when (unsigned(i_fu_258_p2) > unsigned(ap_const_lv10_5)) else "0";
-    notrhs_fu_221_p2 <= "1" when (signed(i6_0_i_cast_i_i_mid1_fu_205_p1) < signed(tmp_7_i_i_reg_488)) else "0";
-    notrhs_mid1_fu_288_p2 <= "1" when (signed(i6_0_i_cast_i_i_fu_264_p1) < signed(tmp_7_i_i_reg_488)) else "0";
-    pix_in_2_l_edge_pix_s_fu_384_p3 <= 
-        r_edge_pix_fu_74 when (tmp_27_i_i_reg_544(0) = '1') else 
-        pix_out_1_fu_82;
-    pix_out_3_fu_424_p3 <= 
-        pix_out_7_reg_560 when (sel_tmp1_fu_419_p2(0) = '1') else 
-        pix_out_fu_78;
-    pix_out_8_fu_431_p3 <= 
-        pix_out_1_fu_82 when (tmp_29_i_i_reg_549_pp0_iter2_reg(0) = '1') else 
-        pix_out_3_fu_424_p3;
-    sel_tmp1_fu_419_p2 <= (tmp_30_i_i_reg_534_pp0_iter2_reg and sel_tmp_fu_414_p2);
-    sel_tmp_fu_414_p2 <= (tmp_29_i_i_reg_549_pp0_iter2_reg xor ap_const_lv1_1);
-    tmp_17_i_i_fu_209_p2 <= "1" when (i6_0_i_i_i_reg_156 = ap_const_lv10_0) else "0";
-    tmp_17_i_i_mid1_fu_276_p2 <= "1" when (i_fu_258_p2 = ap_const_lv10_0) else "0";
-    tmp_22_i_i_fu_242_p2 <= "1" when (signed(j_0_i_cast_i_i_fu_238_p1) < signed(width_read_reg_459)) else "0";
-    tmp_24_i_i_fu_325_p2 <= "1" when (signed(j_0_i_cast_i_i_mid2_s_fu_313_p1) < signed(vconv_xlim_loc_read_reg_473)) else "0";
-    tmp_26_i_i_fu_346_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_mid2_reg_508),64));
-    tmp_27_i_i_fu_355_p2 <= "1" when (j_0_i_i_i_mid2_reg_508 = ap_const_lv10_0) else "0";
-    tmp_28_i_i_fu_330_p2 <= "1" when (j_0_i_cast_i_i_mid2_s_fu_313_p1 = tmp_9_i_i_reg_478) else "0";
-    tmp_29_i_i_fu_360_p2 <= "1" when (unsigned(j_0_i_i_i_mid2_reg_508) < unsigned(ap_const_lv10_6)) else "0";
-    tmp_30_i_i_fu_335_p2 <= "1" when (signed(j_0_i_cast_i_i_mid2_s_fu_313_p1) < signed(tmp_i_i_reg_483)) else "0";
-    tmp_31_i_i_fu_365_p2 <= std_logic_vector(unsigned(j_0_i_i_i_mid2_reg_508) + unsigned(ap_const_lv10_3FB));
-    tmp_32_i_i_fu_370_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_31_i_i_fu_365_p2),64));
-    tmp_7_i_i_fu_188_p2 <= std_logic_vector(unsigned(height_read_reg_467) + unsigned(ap_const_lv32_FFFFFFFB));
-    tmp_9_i_i_fu_178_p2 <= std_logic_vector(unsigned(width_read_reg_459) + unsigned(ap_const_lv32_FFFFFFF5));
-    tmp_i_i_fu_183_p2 <= std_logic_vector(unsigned(width_read_reg_459) + unsigned(ap_const_lv32_FFFFFFFA));
-
-    vconv_V_blk_n_assign_proc : process(vconv_V_empty_n, ap_block_pp0_stage0, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, brmerge_mid2_reg_516, tmp_24_i_i_reg_525)
-    begin
-        if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
-            vconv_V_blk_n <= vconv_V_empty_n;
-        else 
-            vconv_V_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    vconv_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            vconv_V_read <= ap_const_logic_1;
-        else 
-            vconv_V_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    vconv_xlim_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            vconv_xlim_loc_blk_n <= vconv_xlim_loc_empty_n;
-        else 
-            vconv_xlim_loc_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    vconv_xlim_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            vconv_xlim_loc_read <= ap_const_logic_1;
-        else 
-            vconv_xlim_loc_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    width_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_blk_n <= width_empty_n;
-        else 
-            width_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    width_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_read <= ap_const_logic_1;
-        else 
-            width_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-end behav;

src/testbench/dut_packaging/ipshared/22b5/src/Loop_Border_proc_borderbuf.vhd

@@ -1,132 +0,0 @@
--- ==============================================================
--- File generated on Wed Jun 26 16:53:30 CEST 2019
--- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
--- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
--- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--- ==============================================================
---
-library ieee; 
-use ieee.std_logic_1164.all; 
-use ieee.std_logic_unsigned.all;
-
-entity Loop_Border_proc_borderbuf_ram is 
-    generic(
-            MEM_TYPE    : string := "block"; 
-            DWIDTH     : integer := 32; 
-            AWIDTH     : integer := 10; 
-            MEM_SIZE    : integer := 662
-    ); 
-    port (
-          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
-          ce0       : in std_logic; 
-          d0        : in std_logic_vector(DWIDTH-1 downto 0); 
-          we0       : in std_logic; 
-          addr1     : in std_logic_vector(AWIDTH-1 downto 0); 
-          ce1       : in std_logic; 
-          q1        : out std_logic_vector(DWIDTH-1 downto 0);
-          clk        : in std_logic 
-    ); 
-end entity; 
-
-
-architecture rtl of Loop_Border_proc_borderbuf_ram is 
-
-signal addr1_tmp : std_logic_vector(AWIDTH-1 downto 0); 
-type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
-shared variable ram : mem_array;
-
-attribute syn_ramstyle : string; 
-attribute syn_ramstyle of ram : variable is "block_ram";
-attribute ram_style : string;
-attribute ram_style of ram : variable is MEM_TYPE;
-
-begin 
-
-
-
-p_memory_access_0: process (clk)  
-begin 
-    if (clk'event and clk = '1') then
-        if (ce0 = '1') then 
-            if (we0 = '1') then 
-                ram(CONV_INTEGER(addr0)) := d0; 
-            end if;
-        end if;
-    end if;
-end process;
-
-memory_access_guard_1: process (addr1) 
-begin
-      addr1_tmp <= addr1;
---synthesis translate_off
-      if (CONV_INTEGER(addr1) > mem_size-1) then
-           addr1_tmp <= (others => '0');
-      else 
-           addr1_tmp <= addr1;
-      end if;
---synthesis translate_on
-end process;
-
-p_memory_access_1: process (clk)  
-begin 
-    if (clk'event and clk = '1') then
-        if (ce1 = '1') then 
-            q1 <= ram(CONV_INTEGER(addr1_tmp)); 
-        end if;
-    end if;
-end process;
-
-
-end rtl;
-
-Library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity Loop_Border_proc_borderbuf is
-    generic (
-        DataWidth : INTEGER := 32;
-        AddressRange : INTEGER := 662;
-        AddressWidth : INTEGER := 10);
-    port (
-        reset : IN STD_LOGIC;
-        clk : IN STD_LOGIC;
-        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
-        ce0 : IN STD_LOGIC;
-        we0 : IN STD_LOGIC;
-        d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
-        address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
-        ce1 : IN STD_LOGIC;
-        q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
-end entity;
-
-architecture arch of Loop_Border_proc_borderbuf is
-    component Loop_Border_proc_borderbuf_ram is
-        port (
-            clk : IN STD_LOGIC;
-            addr0 : IN STD_LOGIC_VECTOR;
-            ce0 : IN STD_LOGIC;
-            we0 : IN STD_LOGIC;
-            d0 : IN STD_LOGIC_VECTOR;
-            addr1 : IN STD_LOGIC_VECTOR;
-            ce1 : IN STD_LOGIC;
-            q1 : OUT STD_LOGIC_VECTOR);
-    end component;
-
-
-
-begin
-    Loop_Border_proc_borderbuf_ram_U :  component Loop_Border_proc_borderbuf_ram
-    port map (
-        clk => clk,
-        addr0 => address0,
-        ce0 => ce0,
-        we0 => we0,
-        d0 => d0,
-        addr1 => address1,
-        ce1 => ce1,
-        q1 => q1);
-
-end architecture;
-
-

src/testbench/dut_packaging/ipshared/22b5/src/Loop_HConvH_proc6.vhd

@@ -1,746 +0,0 @@
--- ==============================================================
--- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
--- Version: 2018.3
--- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--- 
--- ===========================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity Loop_HConvH_proc6 is
-port (
-    ap_clk : IN STD_LOGIC;
-    ap_rst : IN STD_LOGIC;
-    ap_start : IN STD_LOGIC;
-    ap_done : OUT STD_LOGIC;
-    ap_continue : IN STD_LOGIC;
-    ap_idle : OUT STD_LOGIC;
-    ap_ready : OUT STD_LOGIC;
-    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    height_empty_n : IN STD_LOGIC;
-    height_read : OUT STD_LOGIC;
-    width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    width_empty_n : IN STD_LOGIC;
-    width_read : OUT STD_LOGIC;
-    src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
-    src_V_TVALID : IN STD_LOGIC;
-    src_V_TREADY : OUT STD_LOGIC;
-    filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt1_empty_n : IN STD_LOGIC;
-    filt1_read : OUT STD_LOGIC;
-    filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt2_empty_n : IN STD_LOGIC;
-    filt2_read : OUT STD_LOGIC;
-    hconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    hconv_V_full_n : IN STD_LOGIC;
-    hconv_V_write : OUT STD_LOGIC );
-end;
-
-
-architecture behav of Loop_HConvH_proc6 is 
-    constant ap_const_logic_1 : STD_LOGIC := '1';
-    constant ap_const_logic_0 : STD_LOGIC := '0';
-    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
-    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
-    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
-    constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
-    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
-    constant ap_const_boolean_1 : BOOLEAN := true;
-    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
-    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
-    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
-    constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
-    constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
-    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
-    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
-    constant ap_const_boolean_0 : BOOLEAN := false;
-    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
-    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
-    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
-    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
-    constant ap_const_lv10_9 : STD_LOGIC_VECTOR (9 downto 0) := "0000001001";
-    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
-    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
-
-    signal ap_done_reg : STD_LOGIC := '0';
-    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
-    attribute fsm_encoding : string;
-    attribute fsm_encoding of ap_CS_fsm : signal is "none";
-    signal ap_CS_fsm_state1 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
-    signal src_V_0_data_out : STD_LOGIC_VECTOR (31 downto 0);
-    signal src_V_0_vld_in : STD_LOGIC;
-    signal src_V_0_vld_out : STD_LOGIC;
-    signal src_V_0_ack_in : STD_LOGIC;
-    signal src_V_0_ack_out : STD_LOGIC;
-    signal src_V_0_payload_A : STD_LOGIC_VECTOR (31 downto 0);
-    signal src_V_0_payload_B : STD_LOGIC_VECTOR (31 downto 0);
-    signal src_V_0_sel_rd : STD_LOGIC := '0';
-    signal src_V_0_sel_wr : STD_LOGIC := '0';
-    signal src_V_0_sel : STD_LOGIC;
-    signal src_V_0_load_A : STD_LOGIC;
-    signal src_V_0_load_B : STD_LOGIC;
-    signal src_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
-    signal src_V_0_state_cmp_full : STD_LOGIC;
-    signal height_blk_n : STD_LOGIC;
-    signal width_blk_n : STD_LOGIC;
-    signal src_V_TDATA_blk_n : STD_LOGIC;
-    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
-    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
-    signal ap_block_pp0_stage0 : BOOLEAN;
-    signal exitcond_flatten_fu_214_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal filt1_blk_n : STD_LOGIC;
-    signal filt2_blk_n : STD_LOGIC;
-    signal hconv_V_blk_n : STD_LOGIC;
-    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
-    signal tmp_10_i_reg_491 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_10_i_reg_491_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal indvar_flatten_reg_141 : STD_LOGIC_VECTOR (63 downto 0);
-    signal row_0_i_i_reg_152 : STD_LOGIC_VECTOR (9 downto 0);
-    signal height_read_reg_421 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_state1 : BOOLEAN;
-    signal width_read_reg_426 : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt1_read_reg_432 : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt2_read_reg_437 : STD_LOGIC_VECTOR (31 downto 0);
-    signal bound_fu_169_p2 : STD_LOGIC_VECTOR (63 downto 0);
-    signal bound_reg_442 : STD_LOGIC_VECTOR (63 downto 0);
-    signal ap_CS_fsm_state2 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
-    signal hwin_5_load_reg_447 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
-    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
-    signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
-    signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
-    signal ap_block_pp0_stage0_11001 : BOOLEAN;
-    signal hwin_5_load_reg_447_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_8_load_reg_452 : STD_LOGIC_VECTOR (31 downto 0);
-    signal exitcond_flatten_reg_457 : STD_LOGIC_VECTOR (0 downto 0);
-    signal exitcond_flatten_reg_457_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal indvar_flatten_next_fu_219_p2 : STD_LOGIC_VECTOR (63 downto 0);
-    signal tmp_23_9_i_fu_281_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_23_9_i_reg_466 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_23_i_fu_286_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_23_i_reg_471 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_fu_291_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_reg_476 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_reg_476_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_reg_476_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_fu_303_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_reg_481 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_reg_481_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_reg_481_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp7_fu_309_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp7_reg_486 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp7_reg_486_pp0_iter1_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_10_i_fu_315_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_10_i_reg_491_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal row_fu_326_p2 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp8_fu_336_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp8_reg_500 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp5_fu_345_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp5_reg_505 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_pp0_stage0_subdone : BOOLEAN;
-    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
-    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
-    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
-    signal ap_block_pp0_stage0_01001 : BOOLEAN;
-    signal hwin_1_1_i_fu_64 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_1_fu_68 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_2_fu_72 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_3_fu_76 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_4_fu_80 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_5_fu_84 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_6_fu_88 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_7_fu_92 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_8_fu_96 : STD_LOGIC_VECTOR (31 downto 0);
-    signal hwin_9_fu_100 : STD_LOGIC_VECTOR (31 downto 0);
-    signal bound_fu_169_p0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal bound_fu_169_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal row_0_i_cast_i_fu_205_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_4_i_fu_209_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_23_9_i_fu_281_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_23_i_fu_286_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp4_fu_297_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal row_0_i_i_mid2_fu_273_p3 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp9_fu_332_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp6_fu_341_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp1_fu_350_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_CS_fsm_state7 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
-    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
-    signal ap_idle_pp0 : STD_LOGIC;
-    signal ap_enable_pp0 : STD_LOGIC;
-    signal bound_fu_169_p00 : STD_LOGIC_VECTOR (63 downto 0);
-    signal bound_fu_169_p10 : STD_LOGIC_VECTOR (63 downto 0);
-
-
-begin
-
-
-
-
-    ap_CS_fsm_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_CS_fsm <= ap_ST_fsm_state1;
-            else
-                ap_CS_fsm <= ap_NS_fsm;
-            end if;
-        end if;
-    end process;
-
-
-    ap_done_reg_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_done_reg <= ap_const_logic_0;
-            else
-                if ((ap_continue = ap_const_logic_1)) then 
-                    ap_done_reg <= ap_const_logic_0;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
-                    ap_done_reg <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
-            else
-                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
-                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then 
-                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
-                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
-                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
-                    end if;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                    ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    src_V_0_sel_rd_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                src_V_0_sel_rd <= ap_const_logic_0;
-            else
-                if (((src_V_0_ack_out = ap_const_logic_1) and (src_V_0_vld_out = ap_const_logic_1))) then 
-                                        src_V_0_sel_rd <= not(src_V_0_sel_rd);
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    src_V_0_sel_wr_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                src_V_0_sel_wr <= ap_const_logic_0;
-            else
-                if (((src_V_0_ack_in = ap_const_logic_1) and (src_V_0_vld_in = ap_const_logic_1))) then 
-                                        src_V_0_sel_wr <= not(src_V_0_sel_wr);
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    src_V_0_state_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                src_V_0_state <= ap_const_lv2_0;
-            else
-                if ((((src_V_0_state = ap_const_lv2_2) and (src_V_0_vld_in = ap_const_logic_0)) or ((src_V_0_state = ap_const_lv2_3) and (src_V_0_vld_in = ap_const_logic_0) and (src_V_0_ack_out = ap_const_logic_1)))) then 
-                    src_V_0_state <= ap_const_lv2_2;
-                elsif ((((src_V_0_state = ap_const_lv2_1) and (src_V_0_ack_out = ap_const_logic_0)) or ((src_V_0_state = ap_const_lv2_3) and (src_V_0_ack_out = ap_const_logic_0) and (src_V_0_vld_in = ap_const_logic_1)))) then 
-                    src_V_0_state <= ap_const_lv2_1;
-                elsif (((not(((src_V_0_vld_in = ap_const_logic_0) and (src_V_0_ack_out = ap_const_logic_1))) and not(((src_V_0_ack_out = ap_const_logic_0) and (src_V_0_vld_in = ap_const_logic_1))) and (src_V_0_state = ap_const_lv2_3)) or ((src_V_0_state = ap_const_lv2_1) and (src_V_0_ack_out = ap_const_logic_1)) or ((src_V_0_state = ap_const_lv2_2) and (src_V_0_vld_in = ap_const_logic_1)))) then 
-                    src_V_0_state <= ap_const_lv2_3;
-                else 
-                    src_V_0_state <= ap_const_lv2_2;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    indvar_flatten_reg_141_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
-                indvar_flatten_reg_141 <= indvar_flatten_next_fu_219_p2;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                indvar_flatten_reg_141 <= ap_const_lv64_0;
-            end if; 
-        end if;
-    end process;
-
-    row_0_i_i_reg_152_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
-                row_0_i_i_reg_152 <= row_fu_326_p2;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                row_0_i_i_reg_152 <= ap_const_lv10_0;
-            end if; 
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
-                bound_reg_442 <= bound_fu_169_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
-                exitcond_flatten_reg_457 <= exitcond_flatten_fu_214_p2;
-                exitcond_flatten_reg_457_pp0_iter1_reg <= exitcond_flatten_reg_457;
-                hwin_5_load_reg_447 <= hwin_5_fu_84;
-                hwin_5_load_reg_447_pp0_iter1_reg <= hwin_5_load_reg_447;
-                hwin_8_load_reg_452 <= hwin_8_fu_96;
-                tmp2_reg_476_pp0_iter1_reg <= tmp2_reg_476;
-                tmp3_reg_481_pp0_iter1_reg <= tmp3_reg_481;
-                tmp7_reg_486_pp0_iter1_reg <= tmp7_reg_486;
-                tmp_10_i_reg_491_pp0_iter1_reg <= tmp_10_i_reg_491;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                filt1_read_reg_432 <= filt1_dout;
-                filt2_read_reg_437 <= filt2_dout;
-                height_read_reg_421 <= height_dout;
-                width_read_reg_426 <= width_dout;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
-                hwin_1_1_i_fu_64 <= hwin_1_fu_68;
-                hwin_1_fu_68 <= hwin_2_fu_72;
-                hwin_2_fu_72 <= hwin_3_fu_76;
-                hwin_3_fu_76 <= hwin_4_fu_80;
-                hwin_4_fu_80 <= hwin_5_fu_84;
-                hwin_5_fu_84 <= hwin_6_fu_88;
-                hwin_6_fu_88 <= hwin_7_fu_92;
-                hwin_7_fu_92 <= hwin_8_fu_96;
-                hwin_8_fu_96 <= hwin_9_fu_100;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
-                hwin_9_fu_100 <= src_V_0_data_out;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((src_V_0_load_A = ap_const_logic_1)) then
-                src_V_0_payload_A <= src_V_TDATA;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((src_V_0_load_B = ap_const_logic_1)) then
-                src_V_0_payload_B <= src_V_TDATA;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
-                tmp2_reg_476 <= tmp2_fu_291_p2;
-                tmp3_reg_481 <= tmp3_fu_303_p2;
-                tmp7_reg_486 <= tmp7_fu_309_p2;
-                tmp_10_i_reg_491 <= tmp_10_i_fu_315_p2;
-                tmp_23_9_i_reg_466 <= tmp_23_9_i_fu_281_p2;
-                tmp_23_i_reg_471 <= tmp_23_i_fu_286_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
-                tmp2_reg_476_pp0_iter2_reg <= tmp2_reg_476_pp0_iter1_reg;
-                tmp3_reg_481_pp0_iter2_reg <= tmp3_reg_481_pp0_iter1_reg;
-                tmp_10_i_reg_491_pp0_iter2_reg <= tmp_10_i_reg_491_pp0_iter1_reg;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_reg_457_pp0_iter1_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
-                tmp5_reg_505 <= tmp5_fu_345_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((exitcond_flatten_reg_457 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
-                tmp8_reg_500 <= tmp8_fu_336_p2;
-            end if;
-        end if;
-    end process;
-
-    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
-    begin
-        case ap_CS_fsm is
-            when ap_ST_fsm_state1 => 
-                if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                    ap_NS_fsm <= ap_ST_fsm_state2;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_state1;
-                end if;
-            when ap_ST_fsm_state2 => 
-                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-            when ap_ST_fsm_pp0_stage0 => 
-                if ((not(((exitcond_flatten_fu_214_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) and not(((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1))))) then
-                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-                elsif ((((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)))) then
-                    ap_NS_fsm <= ap_ST_fsm_state7;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-                end if;
-            when ap_ST_fsm_state7 => 
-                ap_NS_fsm <= ap_ST_fsm_state1;
-            when others =>  
-                ap_NS_fsm <= "XXXX";
-        end case;
-    end process;
-    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
-    ap_CS_fsm_state1 <= ap_CS_fsm(0);
-    ap_CS_fsm_state2 <= ap_CS_fsm(1);
-    ap_CS_fsm_state7 <= ap_CS_fsm(3);
-        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_pp0_stage0_01001_assign_proc : process(src_V_0_vld_out, hconv_V_full_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
-    begin
-                ap_block_pp0_stage0_01001 <= (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)));
-    end process;
-
-
-    ap_block_pp0_stage0_11001_assign_proc : process(src_V_0_vld_out, hconv_V_full_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
-    begin
-                ap_block_pp0_stage0_11001 <= (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)));
-    end process;
-
-
-    ap_block_pp0_stage0_subdone_assign_proc : process(src_V_0_vld_out, hconv_V_full_n, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
-    begin
-                ap_block_pp0_stage0_subdone <= (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)) or ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)));
-    end process;
-
-
-    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
-    begin
-                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
-    end process;
-
-
-    ap_block_state3_pp0_stage0_iter0_assign_proc : process(src_V_0_vld_out, exitcond_flatten_fu_214_p2)
-    begin
-                ap_block_state3_pp0_stage0_iter0 <= ((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (src_V_0_vld_out = ap_const_logic_0));
-    end process;
-
-        ap_block_state4_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-        ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_state6_pp0_stage0_iter3_assign_proc : process(hconv_V_full_n, tmp_10_i_reg_491_pp0_iter2_reg)
-    begin
-                ap_block_state6_pp0_stage0_iter3 <= ((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (hconv_V_full_n = ap_const_logic_0));
-    end process;
-
-
-    ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_flatten_fu_214_p2)
-    begin
-        if ((exitcond_flatten_fu_214_p2 = ap_const_lv1_1)) then 
-            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
-        else 
-            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state7)
-    begin
-        if ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
-            ap_done <= ap_const_logic_1;
-        else 
-            ap_done <= ap_done_reg;
-        end if; 
-    end process;
-
-    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
-
-    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
-    begin
-        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            ap_idle <= ap_const_logic_1;
-        else 
-            ap_idle <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
-    begin
-        if (((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then 
-            ap_idle_pp0 <= ap_const_logic_1;
-        else 
-            ap_idle_pp0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_ready_assign_proc : process(ap_CS_fsm_state7)
-    begin
-        if ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
-            ap_ready <= ap_const_logic_1;
-        else 
-            ap_ready <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    bound_fu_169_p0 <= bound_fu_169_p00(32 - 1 downto 0);
-    bound_fu_169_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(width_read_reg_426),64));
-    bound_fu_169_p1 <= bound_fu_169_p10(32 - 1 downto 0);
-    bound_fu_169_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(height_read_reg_421),64));
-    bound_fu_169_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_169_p0) * unsigned(bound_fu_169_p1), 64));
-    exitcond_flatten_fu_214_p2 <= "1" when (indvar_flatten_reg_141 = bound_reg_442) else "0";
-
-    filt1_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt1_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_blk_n <= filt1_empty_n;
-        else 
-            filt1_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    filt1_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_read <= ap_const_logic_1;
-        else 
-            filt1_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    filt2_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt2_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_blk_n <= filt2_empty_n;
-        else 
-            filt2_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    filt2_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_read <= ap_const_logic_1;
-        else 
-            filt2_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    hconv_V_blk_n_assign_proc : process(hconv_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg)
-    begin
-        if (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
-            hconv_V_blk_n <= hconv_V_full_n;
-        else 
-            hconv_V_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    hconv_V_din <= std_logic_vector(unsigned(tmp5_reg_505) + unsigned(tmp1_fu_350_p2));
-
-    hconv_V_write_assign_proc : process(ap_enable_reg_pp0_iter3, tmp_10_i_reg_491_pp0_iter2_reg, ap_block_pp0_stage0_11001)
-    begin
-        if (((tmp_10_i_reg_491_pp0_iter2_reg = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
-            hconv_V_write <= ap_const_logic_1;
-        else 
-            hconv_V_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    height_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_blk_n <= height_empty_n;
-        else 
-            height_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    height_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_read <= ap_const_logic_1;
-        else 
-            height_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    indvar_flatten_next_fu_219_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_141) + unsigned(ap_const_lv64_1));
-    row_0_i_cast_i_fu_205_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_0_i_i_reg_152),32));
-    row_0_i_i_mid2_fu_273_p3 <= 
-        row_0_i_i_reg_152 when (tmp_4_i_fu_209_p2(0) = '1') else 
-        ap_const_lv10_0;
-    row_fu_326_p2 <= std_logic_vector(unsigned(row_0_i_i_mid2_fu_273_p3) + unsigned(ap_const_lv10_1));
-    src_V_0_ack_in <= src_V_0_state(1);
-
-    src_V_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, exitcond_flatten_fu_214_p2, ap_block_pp0_stage0_11001)
-    begin
-        if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
-            src_V_0_ack_out <= ap_const_logic_1;
-        else 
-            src_V_0_ack_out <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    src_V_0_data_out_assign_proc : process(src_V_0_payload_A, src_V_0_payload_B, src_V_0_sel)
-    begin
-        if ((src_V_0_sel = ap_const_logic_1)) then 
-            src_V_0_data_out <= src_V_0_payload_B;
-        else 
-            src_V_0_data_out <= src_V_0_payload_A;
-        end if; 
-    end process;
-
-    src_V_0_load_A <= (src_V_0_state_cmp_full and not(src_V_0_sel_wr));
-    src_V_0_load_B <= (src_V_0_state_cmp_full and src_V_0_sel_wr);
-    src_V_0_sel <= src_V_0_sel_rd;
-    src_V_0_state_cmp_full <= '0' when (src_V_0_state = ap_const_lv2_1) else '1';
-    src_V_0_vld_in <= src_V_TVALID;
-    src_V_0_vld_out <= src_V_0_state(0);
-
-    src_V_TDATA_blk_n_assign_proc : process(src_V_0_state, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0, exitcond_flatten_fu_214_p2)
-    begin
-        if (((exitcond_flatten_fu_214_p2 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
-            src_V_TDATA_blk_n <= src_V_0_state(0);
-        else 
-            src_V_TDATA_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    src_V_TREADY <= src_V_0_state(1);
-    tmp1_fu_350_p2 <= std_logic_vector(unsigned(tmp3_reg_481_pp0_iter2_reg) + unsigned(tmp2_reg_476_pp0_iter2_reg));
-    tmp2_fu_291_p2 <= std_logic_vector(unsigned(hwin_1_1_i_fu_64) + unsigned(hwin_1_fu_68));
-    tmp3_fu_303_p2 <= std_logic_vector(unsigned(tmp4_fu_297_p2) + unsigned(hwin_2_fu_72));
-    tmp4_fu_297_p2 <= std_logic_vector(unsigned(hwin_3_fu_76) + unsigned(hwin_4_fu_80));
-    tmp5_fu_345_p2 <= std_logic_vector(unsigned(tmp8_reg_500) + unsigned(tmp6_fu_341_p2));
-    tmp6_fu_341_p2 <= std_logic_vector(unsigned(tmp7_reg_486_pp0_iter1_reg) + unsigned(hwin_5_load_reg_447_pp0_iter1_reg));
-    tmp7_fu_309_p2 <= std_logic_vector(unsigned(hwin_6_fu_88) + unsigned(hwin_7_fu_92));
-    tmp8_fu_336_p2 <= std_logic_vector(unsigned(tmp9_fu_332_p2) + unsigned(hwin_8_load_reg_452));
-    tmp9_fu_332_p2 <= std_logic_vector(unsigned(tmp_23_9_i_reg_466) + unsigned(tmp_23_i_reg_471));
-    tmp_10_i_fu_315_p2 <= "1" when (unsigned(row_0_i_i_mid2_fu_273_p3) > unsigned(ap_const_lv10_9)) else "0";
-    tmp_23_9_i_fu_281_p1 <= hwin_9_fu_100;
-    tmp_23_9_i_fu_281_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt1_read_reg_432) * signed(tmp_23_9_i_fu_281_p1))), 32));
-    tmp_23_i_fu_286_p1 <= src_V_0_data_out;
-    tmp_23_i_fu_286_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt2_read_reg_437) * signed(tmp_23_i_fu_286_p1))), 32));
-    tmp_4_i_fu_209_p2 <= "1" when (signed(row_0_i_cast_i_fu_205_p1) < signed(width_read_reg_426)) else "0";
-
-    width_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_blk_n <= width_empty_n;
-        else 
-            width_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    width_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, width_empty_n, filt1_empty_n, filt2_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_read <= ap_const_logic_1;
-        else 
-            width_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-end behav;

src/testbench/dut_packaging/ipshared/22b5/src/Loop_VConvH_proc.vhd

@@ -1,1570 +0,0 @@
--- ==============================================================
--- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
--- Version: 2018.3
--- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--- 
--- ===========================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity Loop_VConvH_proc is
-port (
-    ap_clk : IN STD_LOGIC;
-    ap_rst : IN STD_LOGIC;
-    ap_start : IN STD_LOGIC;
-    ap_done : OUT STD_LOGIC;
-    ap_continue : IN STD_LOGIC;
-    ap_idle : OUT STD_LOGIC;
-    ap_ready : OUT STD_LOGIC;
-    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    height_empty_n : IN STD_LOGIC;
-    height_read : OUT STD_LOGIC;
-    vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    vconv_xlim_loc_empty_n : IN STD_LOGIC;
-    vconv_xlim_loc_read : OUT STD_LOGIC;
-    hconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    hconv_V_empty_n : IN STD_LOGIC;
-    hconv_V_read : OUT STD_LOGIC;
-    vconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    vconv_V_full_n : IN STD_LOGIC;
-    vconv_V_write : OUT STD_LOGIC;
-    filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt1_empty_n : IN STD_LOGIC;
-    filt1_read : OUT STD_LOGIC;
-    filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt2_empty_n : IN STD_LOGIC;
-    filt2_read : OUT STD_LOGIC;
-    height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    height_out_full_n : IN STD_LOGIC;
-    height_out_write : OUT STD_LOGIC;
-    vconv_xlim_loc_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    vconv_xlim_loc_out_full_n : IN STD_LOGIC;
-    vconv_xlim_loc_out_write : OUT STD_LOGIC );
-end;
-
-
-architecture behav of Loop_VConvH_proc is 
-    constant ap_const_logic_1 : STD_LOGIC := '1';
-    constant ap_const_logic_0 : STD_LOGIC := '0';
-    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
-    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
-    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
-    constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
-    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
-    constant ap_const_boolean_1 : BOOLEAN := true;
-    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
-    constant ap_const_boolean_0 : BOOLEAN := false;
-    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
-    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
-    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
-    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
-    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
-    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
-    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
-    constant ap_const_lv10_9 : STD_LOGIC_VECTOR (9 downto 0) := "0000001001";
-    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
-
-    signal ap_done_reg : STD_LOGIC := '0';
-    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
-    attribute fsm_encoding : string;
-    attribute fsm_encoding of ap_CS_fsm : signal is "none";
-    signal ap_CS_fsm_state1 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
-    signal linebuf_0_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_0_ce0 : STD_LOGIC;
-    signal linebuf_0_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_0_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_0_ce1 : STD_LOGIC;
-    signal linebuf_0_we1 : STD_LOGIC;
-    signal linebuf_1_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_1_ce0 : STD_LOGIC;
-    signal linebuf_1_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_1_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_1_ce1 : STD_LOGIC;
-    signal linebuf_1_we1 : STD_LOGIC;
-    signal linebuf_2_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_2_ce0 : STD_LOGIC;
-    signal linebuf_2_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_2_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_2_ce1 : STD_LOGIC;
-    signal linebuf_2_we1 : STD_LOGIC;
-    signal linebuf_3_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_3_ce0 : STD_LOGIC;
-    signal linebuf_3_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_3_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_3_ce1 : STD_LOGIC;
-    signal linebuf_3_we1 : STD_LOGIC;
-    signal linebuf_4_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_4_ce0 : STD_LOGIC;
-    signal linebuf_4_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_4_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_4_ce1 : STD_LOGIC;
-    signal linebuf_4_we1 : STD_LOGIC;
-    signal linebuf_5_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_5_ce0 : STD_LOGIC;
-    signal linebuf_5_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_5_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_5_ce1 : STD_LOGIC;
-    signal linebuf_5_we1 : STD_LOGIC;
-    signal linebuf_6_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_6_ce0 : STD_LOGIC;
-    signal linebuf_6_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_6_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_6_ce1 : STD_LOGIC;
-    signal linebuf_6_we1 : STD_LOGIC;
-    signal linebuf_7_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_7_ce0 : STD_LOGIC;
-    signal linebuf_7_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_7_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_7_ce1 : STD_LOGIC;
-    signal linebuf_7_we1 : STD_LOGIC;
-    signal linebuf_8_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_8_ce0 : STD_LOGIC;
-    signal linebuf_8_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_8_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_8_ce1 : STD_LOGIC;
-    signal linebuf_8_we1 : STD_LOGIC;
-    signal linebuf_9_address0 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_9_ce0 : STD_LOGIC;
-    signal linebuf_9_q0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_9_address1 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_9_ce1 : STD_LOGIC;
-    signal linebuf_9_we1 : STD_LOGIC;
-    signal height_blk_n : STD_LOGIC;
-    signal vconv_xlim_loc_blk_n : STD_LOGIC;
-    signal hconv_V_blk_n : STD_LOGIC;
-    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
-    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
-    signal ap_block_pp0_stage0 : BOOLEAN;
-    signal exitcond_flatten_reg_532 : STD_LOGIC_VECTOR (0 downto 0);
-    signal vconv_V_blk_n : STD_LOGIC;
-    signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
-    signal tmp_8_i_i_mid2_reg_541 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_8_i_i_mid2_reg_541_pp0_iter4_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal filt1_blk_n : STD_LOGIC;
-    signal filt2_blk_n : STD_LOGIC;
-    signal height_out_blk_n : STD_LOGIC;
-    signal vconv_xlim_loc_out_blk_n : STD_LOGIC;
-    signal indvar_flatten_reg_319 : STD_LOGIC_VECTOR (63 downto 0);
-    signal col1_0_i_i_i_reg_330 : STD_LOGIC_VECTOR (9 downto 0);
-    signal row2_0_i_i_i_reg_341 : STD_LOGIC_VECTOR (9 downto 0);
-    signal height_read_reg_506 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_state1 : BOOLEAN;
-    signal vconv_xlim_loc_read_reg_511 : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt1_read_reg_517 : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt2_read_reg_522 : STD_LOGIC_VECTOR (31 downto 0);
-    signal bound_fu_358_p2 : STD_LOGIC_VECTOR (63 downto 0);
-    signal bound_reg_527 : STD_LOGIC_VECTOR (63 downto 0);
-    signal ap_CS_fsm_state2 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
-    signal exitcond_flatten_fu_373_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
-    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
-    signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
-    signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
-    signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
-    signal ap_block_state8_pp0_stage0_iter5 : BOOLEAN;
-    signal ap_block_pp0_stage0_11001 : BOOLEAN;
-    signal exitcond_flatten_reg_532_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal exitcond_flatten_reg_532_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal exitcond_flatten_reg_532_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal indvar_flatten_next_fu_378_p2 : STD_LOGIC_VECTOR (63 downto 0);
-    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
-    signal tmp_8_i_i_mid2_fu_410_p3 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_8_i_i_mid2_reg_541_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_8_i_i_mid2_reg_541_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_8_i_i_mid2_reg_541_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
-    signal col1_0_i_i_i_mid2_fu_418_p3 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_0_addr_reg_550 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_1_addr_reg_556 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_2_addr_reg_562 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_3_addr_reg_568 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_4_addr_reg_574 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_5_addr_reg_580 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_6_addr_reg_586 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_7_addr_reg_592 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_8_addr_reg_598 : STD_LOGIC_VECTOR (9 downto 0);
-    signal linebuf_9_addr_reg_604 : STD_LOGIC_VECTOR (9 downto 0);
-    signal row_fu_440_p2 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp_1_reg_615 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_5_load_reg_620 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_5_load_reg_620_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_5_load_reg_620_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_8_load_reg_625 : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_8_load_reg_625_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal linebuf_9_load_reg_630 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_fu_446_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_reg_635 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_reg_635_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_reg_635_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp2_reg_635_pp0_iter4_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_fu_458_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_reg_640 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_reg_640_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_reg_640_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp3_reg_640_pp0_iter4_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp7_fu_464_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp7_reg_645 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp7_reg_645_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp7_reg_645_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_30_9_i_i_fu_470_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_30_9_i_i_reg_650 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_30_i_i_fu_474_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_30_i_i_reg_655 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp8_fu_482_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp8_reg_660 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp5_fu_491_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp5_reg_665 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_block_pp0_stage0_subdone : BOOLEAN;
-    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
-    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
-    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
-    signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
-    signal tmp_16_i_i_fu_426_p1 : STD_LOGIC_VECTOR (63 downto 0);
-    signal ap_block_pp0_stage0_01001 : BOOLEAN;
-    signal bound_fu_358_p0 : STD_LOGIC_VECTOR (31 downto 0);
-    signal bound_fu_358_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal row2_0_i_cast_i_i_fu_364_p1 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp_11_i_i_fu_368_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal col_fu_392_p2 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp_8_i_i_fu_404_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal tmp_8_i_i_mid1_fu_398_p2 : STD_LOGIC_VECTOR (0 downto 0);
-    signal row2_0_i_i_i_mid2_fu_384_p3 : STD_LOGIC_VECTOR (9 downto 0);
-    signal tmp4_fu_452_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp9_fu_478_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp6_fu_487_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal tmp1_fu_496_p2 : STD_LOGIC_VECTOR (31 downto 0);
-    signal ap_CS_fsm_state9 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
-    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
-    signal ap_block_pp0 : BOOLEAN;
-    signal ap_enable_operation_44 : BOOLEAN;
-    signal ap_enable_state3_pp0_iter0_stage0 : BOOLEAN;
-    signal ap_enable_operation_66 : BOOLEAN;
-    signal ap_enable_state4_pp0_iter1_stage0 : BOOLEAN;
-    signal ap_enable_operation_68 : BOOLEAN;
-    signal ap_enable_operation_46 : BOOLEAN;
-    signal ap_enable_operation_67 : BOOLEAN;
-    signal ap_enable_operation_70 : BOOLEAN;
-    signal ap_enable_operation_48 : BOOLEAN;
-    signal ap_enable_operation_69 : BOOLEAN;
-    signal ap_enable_operation_72 : BOOLEAN;
-    signal ap_enable_operation_50 : BOOLEAN;
-    signal ap_enable_operation_71 : BOOLEAN;
-    signal ap_enable_operation_74 : BOOLEAN;
-    signal ap_enable_operation_52 : BOOLEAN;
-    signal ap_enable_operation_73 : BOOLEAN;
-    signal ap_enable_operation_76 : BOOLEAN;
-    signal ap_enable_operation_54 : BOOLEAN;
-    signal ap_enable_operation_75 : BOOLEAN;
-    signal ap_enable_operation_78 : BOOLEAN;
-    signal ap_enable_operation_56 : BOOLEAN;
-    signal ap_enable_operation_77 : BOOLEAN;
-    signal ap_enable_operation_80 : BOOLEAN;
-    signal ap_enable_operation_58 : BOOLEAN;
-    signal ap_enable_operation_79 : BOOLEAN;
-    signal ap_enable_operation_82 : BOOLEAN;
-    signal ap_enable_operation_60 : BOOLEAN;
-    signal ap_enable_operation_81 : BOOLEAN;
-    signal ap_enable_operation_84 : BOOLEAN;
-    signal ap_enable_operation_62 : BOOLEAN;
-    signal ap_enable_operation_83 : BOOLEAN;
-    signal ap_enable_operation_89 : BOOLEAN;
-    signal ap_idle_pp0 : STD_LOGIC;
-    signal ap_enable_pp0 : STD_LOGIC;
-    signal bound_fu_358_p00 : STD_LOGIC_VECTOR (63 downto 0);
-    signal bound_fu_358_p10 : STD_LOGIC_VECTOR (63 downto 0);
-
-    component Loop_VConvH_proc_linebuf_0 IS
-    generic (
-        DataWidth : INTEGER;
-        AddressRange : INTEGER;
-        AddressWidth : INTEGER );
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        address0 : IN STD_LOGIC_VECTOR (9 downto 0);
-        ce0 : IN STD_LOGIC;
-        q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
-        address1 : IN STD_LOGIC_VECTOR (9 downto 0);
-        ce1 : IN STD_LOGIC;
-        we1 : IN STD_LOGIC;
-        d1 : IN STD_LOGIC_VECTOR (31 downto 0) );
-    end component;
-
-
-
-begin
-    linebuf_0_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_0_address0,
-        ce0 => linebuf_0_ce0,
-        q0 => linebuf_0_q0,
-        address1 => linebuf_0_address1,
-        ce1 => linebuf_0_ce1,
-        we1 => linebuf_0_we1,
-        d1 => linebuf_1_q0);
-
-    linebuf_1_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_1_address0,
-        ce0 => linebuf_1_ce0,
-        q0 => linebuf_1_q0,
-        address1 => linebuf_1_address1,
-        ce1 => linebuf_1_ce1,
-        we1 => linebuf_1_we1,
-        d1 => linebuf_2_q0);
-
-    linebuf_2_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_2_address0,
-        ce0 => linebuf_2_ce0,
-        q0 => linebuf_2_q0,
-        address1 => linebuf_2_address1,
-        ce1 => linebuf_2_ce1,
-        we1 => linebuf_2_we1,
-        d1 => linebuf_3_q0);
-
-    linebuf_3_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_3_address0,
-        ce0 => linebuf_3_ce0,
-        q0 => linebuf_3_q0,
-        address1 => linebuf_3_address1,
-        ce1 => linebuf_3_ce1,
-        we1 => linebuf_3_we1,
-        d1 => linebuf_4_q0);
-
-    linebuf_4_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_4_address0,
-        ce0 => linebuf_4_ce0,
-        q0 => linebuf_4_q0,
-        address1 => linebuf_4_address1,
-        ce1 => linebuf_4_ce1,
-        we1 => linebuf_4_we1,
-        d1 => linebuf_5_q0);
-
-    linebuf_5_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_5_address0,
-        ce0 => linebuf_5_ce0,
-        q0 => linebuf_5_q0,
-        address1 => linebuf_5_address1,
-        ce1 => linebuf_5_ce1,
-        we1 => linebuf_5_we1,
-        d1 => linebuf_6_q0);
-
-    linebuf_6_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_6_address0,
-        ce0 => linebuf_6_ce0,
-        q0 => linebuf_6_q0,
-        address1 => linebuf_6_address1,
-        ce1 => linebuf_6_ce1,
-        we1 => linebuf_6_we1,
-        d1 => linebuf_7_q0);
-
-    linebuf_7_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_7_address0,
-        ce0 => linebuf_7_ce0,
-        q0 => linebuf_7_q0,
-        address1 => linebuf_7_address1,
-        ce1 => linebuf_7_ce1,
-        we1 => linebuf_7_we1,
-        d1 => linebuf_8_q0);
-
-    linebuf_8_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_8_address0,
-        ce0 => linebuf_8_ce0,
-        q0 => linebuf_8_q0,
-        address1 => linebuf_8_address1,
-        ce1 => linebuf_8_ce1,
-        we1 => linebuf_8_we1,
-        d1 => linebuf_9_q0);
-
-    linebuf_9_U : component Loop_VConvH_proc_linebuf_0
-    generic map (
-        DataWidth => 32,
-        AddressRange => 672,
-        AddressWidth => 10)
-    port map (
-        clk => ap_clk,
-        reset => ap_rst,
-        address0 => linebuf_9_address0,
-        ce0 => linebuf_9_ce0,
-        q0 => linebuf_9_q0,
-        address1 => linebuf_9_address1,
-        ce1 => linebuf_9_ce1,
-        we1 => linebuf_9_we1,
-        d1 => hconv_V_dout);
-
-
-
-
-
-    ap_CS_fsm_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_CS_fsm <= ap_ST_fsm_state1;
-            else
-                ap_CS_fsm <= ap_NS_fsm;
-            end if;
-        end if;
-    end process;
-
-
-    ap_done_reg_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_done_reg <= ap_const_logic_0;
-            else
-                if ((ap_continue = ap_const_logic_1)) then 
-                    ap_done_reg <= ap_const_logic_0;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
-                    ap_done_reg <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
-            else
-                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
-                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then 
-                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
-                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
-                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
-                    end if;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
-            else
-                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
-                    ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
-                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                    ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    col1_0_i_i_i_reg_330_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
-                col1_0_i_i_i_reg_330 <= col1_0_i_i_i_mid2_fu_418_p3;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                col1_0_i_i_i_reg_330 <= ap_const_lv10_0;
-            end if; 
-        end if;
-    end process;
-
-    indvar_flatten_reg_319_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
-                indvar_flatten_reg_319 <= indvar_flatten_next_fu_378_p2;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                indvar_flatten_reg_319 <= ap_const_lv64_0;
-            end if; 
-        end if;
-    end process;
-
-    row2_0_i_i_i_reg_341_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
-                row2_0_i_i_i_reg_341 <= row_fu_440_p2;
-            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
-                row2_0_i_i_i_reg_341 <= ap_const_lv10_0;
-            end if; 
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
-                bound_reg_527 <= bound_fu_358_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
-                exitcond_flatten_reg_532 <= exitcond_flatten_fu_373_p2;
-                exitcond_flatten_reg_532_pp0_iter1_reg <= exitcond_flatten_reg_532;
-                tmp_8_i_i_mid2_reg_541_pp0_iter1_reg <= tmp_8_i_i_mid2_reg_541;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
-                exitcond_flatten_reg_532_pp0_iter2_reg <= exitcond_flatten_reg_532_pp0_iter1_reg;
-                exitcond_flatten_reg_532_pp0_iter3_reg <= exitcond_flatten_reg_532_pp0_iter2_reg;
-                linebuf_5_load_reg_620_pp0_iter2_reg <= linebuf_5_load_reg_620;
-                linebuf_5_load_reg_620_pp0_iter3_reg <= linebuf_5_load_reg_620_pp0_iter2_reg;
-                linebuf_8_load_reg_625_pp0_iter2_reg <= linebuf_8_load_reg_625;
-                tmp2_reg_635_pp0_iter2_reg <= tmp2_reg_635;
-                tmp2_reg_635_pp0_iter3_reg <= tmp2_reg_635_pp0_iter2_reg;
-                tmp2_reg_635_pp0_iter4_reg <= tmp2_reg_635_pp0_iter3_reg;
-                tmp3_reg_640_pp0_iter2_reg <= tmp3_reg_640;
-                tmp3_reg_640_pp0_iter3_reg <= tmp3_reg_640_pp0_iter2_reg;
-                tmp3_reg_640_pp0_iter4_reg <= tmp3_reg_640_pp0_iter3_reg;
-                tmp7_reg_645_pp0_iter2_reg <= tmp7_reg_645;
-                tmp7_reg_645_pp0_iter3_reg <= tmp7_reg_645_pp0_iter2_reg;
-                tmp_8_i_i_mid2_reg_541_pp0_iter2_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter1_reg;
-                tmp_8_i_i_mid2_reg_541_pp0_iter3_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter2_reg;
-                tmp_8_i_i_mid2_reg_541_pp0_iter4_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter3_reg;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                filt1_read_reg_517 <= filt1_dout;
-                filt2_read_reg_522 <= filt2_dout;
-                height_read_reg_506 <= height_dout;
-                vconv_xlim_loc_read_reg_511 <= vconv_xlim_loc_dout;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then
-                linebuf_0_addr_reg_550 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_1_addr_reg_556 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_2_addr_reg_562 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_3_addr_reg_568 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_4_addr_reg_574 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_5_addr_reg_580 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_6_addr_reg_586 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_7_addr_reg_592 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_8_addr_reg_598 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                linebuf_9_addr_reg_604 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-                tmp_8_i_i_mid2_reg_541 <= tmp_8_i_i_mid2_fu_410_p3;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then
-                linebuf_5_load_reg_620 <= linebuf_5_q0;
-                linebuf_8_load_reg_625 <= linebuf_8_q0;
-                linebuf_9_load_reg_630 <= linebuf_9_q0;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then
-                tmp2_reg_635 <= tmp2_fu_446_p2;
-                tmp3_reg_640 <= tmp3_fu_458_p2;
-                tmp7_reg_645 <= tmp7_fu_464_p2;
-                tmp_1_reg_615 <= hconv_V_dout;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter3_reg = ap_const_lv1_0))) then
-                tmp5_reg_665 <= tmp5_fu_491_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter2_reg = ap_const_lv1_0))) then
-                tmp8_reg_660 <= tmp8_fu_482_p2;
-            end if;
-        end if;
-    end process;
-    process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter1_reg = ap_const_lv1_0))) then
-                tmp_30_9_i_i_reg_650 <= tmp_30_9_i_i_fu_470_p2;
-                tmp_30_i_i_reg_655 <= tmp_30_i_i_fu_474_p2;
-            end if;
-        end if;
-    end process;
-
-    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter5, exitcond_flatten_fu_373_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter4)
-    begin
-        case ap_CS_fsm is
-            when ap_ST_fsm_state1 => 
-                if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
-                    ap_NS_fsm <= ap_ST_fsm_state2;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_state1;
-                end if;
-            when ap_ST_fsm_state2 => 
-                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-            when ap_ST_fsm_pp0_stage0 => 
-                if ((not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) and not(((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1))))) then
-                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-                elsif ((((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)) or ((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1)))) then
-                    ap_NS_fsm <= ap_ST_fsm_state9;
-                else
-                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
-                end if;
-            when ap_ST_fsm_state9 => 
-                ap_NS_fsm <= ap_ST_fsm_state1;
-            when others =>  
-                ap_NS_fsm <= "XXXX";
-        end case;
-    end process;
-    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
-    ap_CS_fsm_state1 <= ap_CS_fsm(0);
-    ap_CS_fsm_state2 <= ap_CS_fsm(1);
-    ap_CS_fsm_state9 <= ap_CS_fsm(3);
-
-    ap_block_pp0_assign_proc : process(ap_CS_fsm, ap_block_pp0_stage0_subdone)
-    begin
-                ap_block_pp0 <= ((ap_ST_fsm_pp0_stage0 = ap_CS_fsm) and (ap_const_boolean_1 = ap_block_pp0_stage0_subdone));
-    end process;
-
-        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_pp0_stage0_01001_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
-    begin
-                ap_block_pp0_stage0_01001 <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
-    end process;
-
-
-    ap_block_pp0_stage0_11001_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
-    begin
-                ap_block_pp0_stage0_11001 <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
-    end process;
-
-
-    ap_block_pp0_stage0_subdone_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
-    begin
-                ap_block_pp0_stage0_subdone <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
-    end process;
-
-
-    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
-    begin
-                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
-    end process;
-
-        ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_state4_pp0_stage0_iter1_assign_proc : process(hconv_V_empty_n, exitcond_flatten_reg_532)
-    begin
-                ap_block_state4_pp0_stage0_iter1 <= ((hconv_V_empty_n = ap_const_logic_0) and (exitcond_flatten_reg_532 = ap_const_lv1_0));
-    end process;
-
-        ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-        ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-        ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
-
-    ap_block_state8_pp0_stage0_iter5_assign_proc : process(vconv_V_full_n, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
-    begin
-                ap_block_state8_pp0_stage0_iter5 <= ((vconv_V_full_n = ap_const_logic_0) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1));
-    end process;
-
-
-    ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-        if ((exitcond_flatten_fu_373_p2 = ap_const_lv1_1)) then 
-            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
-        else 
-            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state9)
-    begin
-        if ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
-            ap_done <= ap_const_logic_1;
-        else 
-            ap_done <= ap_done_reg;
-        end if; 
-    end process;
-
-
-    ap_enable_operation_44_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_44 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_46_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_46 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_48_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_48 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_50_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_50 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_52_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_52 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_54_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_54 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_56_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_56 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_58_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_58 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_60_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_60 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_62_assign_proc : process(exitcond_flatten_fu_373_p2)
-    begin
-                ap_enable_operation_62 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_66_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_66 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_67_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_67 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_68_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_68 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_69_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_69 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_70_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_70 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_71_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_71 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_72_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_72 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_73_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_73 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_74_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_74 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_75_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_75 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_76_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_76 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_77_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_77 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_78_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_78 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_79_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_79 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_80_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_80 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_81_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_81 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_82_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_82 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_83_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_83 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_84_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_84 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-
-    ap_enable_operation_89_assign_proc : process(exitcond_flatten_reg_532)
-    begin
-                ap_enable_operation_89 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
-    end process;
-
-    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
-
-    ap_enable_state3_pp0_iter0_stage0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0)
-    begin
-                ap_enable_state3_pp0_iter0_stage0 <= ((ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0));
-    end process;
-
-
-    ap_enable_state4_pp0_iter1_stage0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
-    begin
-                ap_enable_state4_pp0_iter1_stage0 <= ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0));
-    end process;
-
-
-    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
-    begin
-        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            ap_idle <= ap_const_logic_1;
-        else 
-            ap_idle <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4)
-    begin
-        if (((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then 
-            ap_idle_pp0 <= ap_const_logic_1;
-        else 
-            ap_idle_pp0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    ap_ready_assign_proc : process(ap_CS_fsm_state9)
-    begin
-        if ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
-            ap_ready <= ap_const_logic_1;
-        else 
-            ap_ready <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    bound_fu_358_p0 <= bound_fu_358_p00(32 - 1 downto 0);
-    bound_fu_358_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(vconv_xlim_loc_read_reg_511),64));
-    bound_fu_358_p1 <= bound_fu_358_p10(32 - 1 downto 0);
-    bound_fu_358_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(height_read_reg_506),64));
-    bound_fu_358_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_358_p0) * unsigned(bound_fu_358_p1), 64));
-    col1_0_i_i_i_mid2_fu_418_p3 <= 
-        col1_0_i_i_i_reg_330 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
-        col_fu_392_p2;
-    col_fu_392_p2 <= std_logic_vector(unsigned(col1_0_i_i_i_reg_330) + unsigned(ap_const_lv10_1));
-    exitcond_flatten_fu_373_p2 <= "1" when (indvar_flatten_reg_319 = bound_reg_527) else "0";
-
-    filt1_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt1_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_blk_n <= filt1_empty_n;
-        else 
-            filt1_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    filt1_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_read <= ap_const_logic_1;
-        else 
-            filt1_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    filt2_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt2_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_blk_n <= filt2_empty_n;
-        else 
-            filt2_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    filt2_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_read <= ap_const_logic_1;
-        else 
-            filt2_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    hconv_V_blk_n_assign_proc : process(hconv_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_flatten_reg_532)
-    begin
-        if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
-            hconv_V_blk_n <= hconv_V_empty_n;
-        else 
-            hconv_V_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    hconv_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            hconv_V_read <= ap_const_logic_1;
-        else 
-            hconv_V_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    height_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_blk_n <= height_empty_n;
-        else 
-            height_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    height_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_out_blk_n <= height_out_full_n;
-        else 
-            height_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    height_out_din <= height_dout;
-
-    height_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_out_write <= ap_const_logic_1;
-        else 
-            height_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    height_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_read <= ap_const_logic_1;
-        else 
-            height_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    indvar_flatten_next_fu_378_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_319) + unsigned(ap_const_lv64_1));
-    linebuf_0_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_0_address1 <= linebuf_0_addr_reg_550;
-
-    linebuf_0_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_0_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_0_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_0_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_0_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_0_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_0_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_0_we1 <= ap_const_logic_1;
-        else 
-            linebuf_0_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_1_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_1_address1 <= linebuf_1_addr_reg_556;
-
-    linebuf_1_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_1_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_1_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_1_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_1_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_1_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_1_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_1_we1 <= ap_const_logic_1;
-        else 
-            linebuf_1_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_2_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_2_address1 <= linebuf_2_addr_reg_562;
-
-    linebuf_2_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_2_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_2_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_2_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_2_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_2_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_2_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_2_we1 <= ap_const_logic_1;
-        else 
-            linebuf_2_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_3_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_3_address1 <= linebuf_3_addr_reg_568;
-
-    linebuf_3_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_3_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_3_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_3_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_3_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_3_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_3_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_3_we1 <= ap_const_logic_1;
-        else 
-            linebuf_3_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_4_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_4_address1 <= linebuf_4_addr_reg_574;
-
-    linebuf_4_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_4_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_4_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_4_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_4_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_4_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_4_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_4_we1 <= ap_const_logic_1;
-        else 
-            linebuf_4_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_5_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_5_address1 <= linebuf_5_addr_reg_580;
-
-    linebuf_5_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_5_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_5_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_5_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_5_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_5_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_5_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_5_we1 <= ap_const_logic_1;
-        else 
-            linebuf_5_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_6_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_6_address1 <= linebuf_6_addr_reg_586;
-
-    linebuf_6_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_6_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_6_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_6_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_6_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_6_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_6_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_6_we1 <= ap_const_logic_1;
-        else 
-            linebuf_6_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_7_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_7_address1 <= linebuf_7_addr_reg_592;
-
-    linebuf_7_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_7_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_7_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_7_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_7_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_7_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_7_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_7_we1 <= ap_const_logic_1;
-        else 
-            linebuf_7_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_8_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_8_address1 <= linebuf_8_addr_reg_598;
-
-    linebuf_8_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_8_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_8_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_8_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_8_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_8_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_8_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_8_we1 <= ap_const_logic_1;
-        else 
-            linebuf_8_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    linebuf_9_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
-    linebuf_9_address1 <= linebuf_9_addr_reg_604;
-
-    linebuf_9_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_9_ce0 <= ap_const_logic_1;
-        else 
-            linebuf_9_ce0 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_9_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
-            linebuf_9_ce1 <= ap_const_logic_1;
-        else 
-            linebuf_9_ce1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    linebuf_9_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
-            linebuf_9_we1 <= ap_const_logic_1;
-        else 
-            linebuf_9_we1 <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    row2_0_i_cast_i_i_fu_364_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row2_0_i_i_i_reg_341),32));
-    row2_0_i_i_i_mid2_fu_384_p3 <= 
-        row2_0_i_i_i_reg_341 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
-        ap_const_lv10_0;
-    row_fu_440_p2 <= std_logic_vector(unsigned(row2_0_i_i_i_mid2_fu_384_p3) + unsigned(ap_const_lv10_1));
-    tmp1_fu_496_p2 <= std_logic_vector(unsigned(tmp3_reg_640_pp0_iter4_reg) + unsigned(tmp2_reg_635_pp0_iter4_reg));
-    tmp2_fu_446_p2 <= std_logic_vector(unsigned(linebuf_0_q0) + unsigned(linebuf_1_q0));
-    tmp3_fu_458_p2 <= std_logic_vector(unsigned(tmp4_fu_452_p2) + unsigned(linebuf_2_q0));
-    tmp4_fu_452_p2 <= std_logic_vector(unsigned(linebuf_3_q0) + unsigned(linebuf_4_q0));
-    tmp5_fu_491_p2 <= std_logic_vector(unsigned(tmp8_reg_660) + unsigned(tmp6_fu_487_p2));
-    tmp6_fu_487_p2 <= std_logic_vector(unsigned(tmp7_reg_645_pp0_iter3_reg) + unsigned(linebuf_5_load_reg_620_pp0_iter3_reg));
-    tmp7_fu_464_p2 <= std_logic_vector(unsigned(linebuf_6_q0) + unsigned(linebuf_7_q0));
-    tmp8_fu_482_p2 <= std_logic_vector(unsigned(tmp9_fu_478_p2) + unsigned(linebuf_8_load_reg_625_pp0_iter2_reg));
-    tmp9_fu_478_p2 <= std_logic_vector(unsigned(tmp_30_9_i_i_reg_650) + unsigned(tmp_30_i_i_reg_655));
-    tmp_11_i_i_fu_368_p2 <= "1" when (signed(row2_0_i_cast_i_i_fu_364_p1) < signed(vconv_xlim_loc_read_reg_511)) else "0";
-    tmp_16_i_i_fu_426_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row2_0_i_i_i_mid2_fu_384_p3),64));
-    tmp_30_9_i_i_fu_470_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt1_read_reg_517) * signed(linebuf_9_load_reg_630))), 32));
-    tmp_30_i_i_fu_474_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt2_read_reg_522) * signed(tmp_1_reg_615))), 32));
-    tmp_8_i_i_fu_404_p2 <= "1" when (unsigned(col1_0_i_i_i_reg_330) > unsigned(ap_const_lv10_9)) else "0";
-    tmp_8_i_i_mid1_fu_398_p2 <= "1" when (unsigned(col_fu_392_p2) > unsigned(ap_const_lv10_9)) else "0";
-    tmp_8_i_i_mid2_fu_410_p3 <= 
-        tmp_8_i_i_fu_404_p2 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
-        tmp_8_i_i_mid1_fu_398_p2;
-
-    vconv_V_blk_n_assign_proc : process(vconv_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
-    begin
-        if (((ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
-            vconv_V_blk_n <= vconv_V_full_n;
-        else 
-            vconv_V_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    vconv_V_din <= std_logic_vector(unsigned(tmp5_reg_665) + unsigned(tmp1_fu_496_p2));
-
-    vconv_V_write_assign_proc : process(ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg, ap_block_pp0_stage0_11001)
-    begin
-        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1))) then 
-            vconv_V_write <= ap_const_logic_1;
-        else 
-            vconv_V_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    vconv_xlim_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_empty_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            vconv_xlim_loc_blk_n <= vconv_xlim_loc_empty_n;
-        else 
-            vconv_xlim_loc_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-
-    vconv_xlim_loc_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            vconv_xlim_loc_out_blk_n <= vconv_xlim_loc_out_full_n;
-        else 
-            vconv_xlim_loc_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    vconv_xlim_loc_out_din <= vconv_xlim_loc_dout;
-
-    vconv_xlim_loc_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            vconv_xlim_loc_out_write <= ap_const_logic_1;
-        else 
-            vconv_xlim_loc_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    vconv_xlim_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
-    begin
-        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            vconv_xlim_loc_read <= ap_const_logic_1;
-        else 
-            vconv_xlim_loc_read <= ap_const_logic_0;
-        end if; 
-    end process;
-
-end behav;

src/testbench/dut_packaging/ipshared/22b5/src/Loop_VConvH_proc_linebuf_0.vhd

@@ -1,132 +0,0 @@
--- ==============================================================
--- File generated on Wed Jun 26 16:53:30 CEST 2019
--- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
--- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
--- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--- ==============================================================
---
-library ieee; 
-use ieee.std_logic_1164.all; 
-use ieee.std_logic_unsigned.all;
-
-entity Loop_VConvH_proc_linebuf_0_ram is 
-    generic(
-            MEM_TYPE    : string := "block"; 
-            DWIDTH     : integer := 32; 
-            AWIDTH     : integer := 10; 
-            MEM_SIZE    : integer := 672
-    ); 
-    port (
-          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
-          ce0       : in std_logic; 
-          q0        : out std_logic_vector(DWIDTH-1 downto 0);
-          addr1     : in std_logic_vector(AWIDTH-1 downto 0); 
-          ce1       : in std_logic; 
-          d1        : in std_logic_vector(DWIDTH-1 downto 0); 
-          we1       : in std_logic; 
-          clk        : in std_logic 
-    ); 
-end entity; 
-
-
-architecture rtl of Loop_VConvH_proc_linebuf_0_ram is 
-
-signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
-type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
-shared variable ram : mem_array := (others=>(others=>'0'));
-
-attribute syn_ramstyle : string; 
-attribute syn_ramstyle of ram : variable is "block_ram";
-attribute ram_style : string;
-attribute ram_style of ram : variable is MEM_TYPE;
-
-begin 
-
-
-memory_access_guard_0: process (addr0) 
-begin
-      addr0_tmp <= addr0;
---synthesis translate_off
-      if (CONV_INTEGER(addr0) > mem_size-1) then
-           addr0_tmp <= (others => '0');
-      else 
-           addr0_tmp <= addr0;
-      end if;
---synthesis translate_on
-end process;
-
-p_memory_access_0: process (clk)  
-begin 
-    if (clk'event and clk = '1') then
-        if (ce0 = '1') then 
-            q0 <= ram(CONV_INTEGER(addr0_tmp)); 
-        end if;
-    end if;
-end process;
-
-
-p_memory_access_1: process (clk)  
-begin 
-    if (clk'event and clk = '1') then
-        if (ce1 = '1') then 
-            if (we1 = '1') then 
-                ram(CONV_INTEGER(addr1)) := d1; 
-            end if;
-        end if;
-    end if;
-end process;
-
-
-end rtl;
-
-Library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity Loop_VConvH_proc_linebuf_0 is
-    generic (
-        DataWidth : INTEGER := 32;
-        AddressRange : INTEGER := 672;
-        AddressWidth : INTEGER := 10);
-    port (
-        reset : IN STD_LOGIC;
-        clk : IN STD_LOGIC;
-        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
-        ce0 : IN STD_LOGIC;
-        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
-        address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
-        ce1 : IN STD_LOGIC;
-        we1 : IN STD_LOGIC;
-        d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
-end entity;
-
-architecture arch of Loop_VConvH_proc_linebuf_0 is
-    component Loop_VConvH_proc_linebuf_0_ram is
-        port (
-            clk : IN STD_LOGIC;
-            addr0 : IN STD_LOGIC_VECTOR;
-            ce0 : IN STD_LOGIC;
-            q0 : OUT STD_LOGIC_VECTOR;
-            addr1 : IN STD_LOGIC_VECTOR;
-            ce1 : IN STD_LOGIC;
-            we1 : IN STD_LOGIC;
-            d1 : IN STD_LOGIC_VECTOR);
-    end component;
-
-
-
-begin
-    Loop_VConvH_proc_linebuf_0_ram_U :  component Loop_VConvH_proc_linebuf_0_ram
-    port map (
-        clk => clk,
-        addr0 => address0,
-        ce0 => ce0,
-        q0 => q0,
-        addr1 => address1,
-        ce1 => ce1,
-        we1 => we1,
-        d1 => d1);
-
-end architecture;
-
-

src/testbench/dut_packaging/ipshared/22b5/src/checksum.vhd

@@ -1,34 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_arith.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.myPackage.ALL;
-
-
-entity checksum is
-    generic(
-        busWidth : integer:=32);
-    Port ( clk : in STD_LOGIC;
-           reset : in STD_LOGIC;
-           enable : in STD_LOGIC;
-           dataIn : in std_logic_vector(busWidth-1 downto 0);
-           output : out std_logic_vector(busWidth-1 downto 0));
-end checksum;
-
-architecture Behavioral of checksum is
-    signal sum : unsigned(busWidth-1 downto 0);
-begin
-    main : process(clk, reset)
-        
-    begin
-        if(reset = '0') then
-            sum <= (others => '0');
-        elsif(rising_edge(clk)) then
-            if(enable = '1') then
-                sum <= sum + unsigned(dataIn);
-            end if;
-        end if;
-    end process;
-
-    output <= std_logic_vector(sum);
-end Behavioral;

src/testbench/dut_packaging/ipshared/22b5/src/conv2d_5x5_224p.vhd

@@ -1,164 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-
-entity conv2d_5x5_224p is
-    generic(
-        busWidth : integer := 32;
-        kernelSize : integer := 5;
-        imageWidth : integer := 224 + 4);
-    Port ( clk : in STD_LOGIC;
-           rst_n : in std_logic;
-           start : in STD_LOGIC;
-           ready: out std_logic;
-           idle : out std_logic := '0';
-           done : out std_logic := '0';
-           
-           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           srcValid : in std_logic;
-           srcReady : out std_logic;
-           
-           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           dstValid : out std_logic;
-           dstReady : in std_logic);
-end conv2d_5x5_224p;
-
-architecture Behavioral of conv2d_5x5_224p is
-    constant regDepth : integer := ((kernelSize-1) * imageWidth + kernelSize);
-    component shiftIn is
-        generic(
-            busWidth : integer := busWidth;
-            regDepth : integer := regDepth;
-            maxCount : integer := imageWidth*imageWidth);
-        Port ( clk : in STD_LOGIC;
-               ce : in std_logic;
-               sync_reset : in STD_LOGIC;
-               dataIn : in std_logic_vector(busWidth-1 downto 0);
-               dataOut : out register_file(0 to regDepth-1);
-               finished : out STD_LOGIC;
-               dataIndex : out integer range 0 to maxCount);
-    end component;
-    
-    component kernel_NxN is
-    Generic(
-        N: integer := kernelSize
-    );
-    Port (
-        kernelValues: in register_file(0 to N*N-1);
-        inputValues: in register_file(0 to N*N-1);
-        outputValue: out std_logic_vector(31 downto 0)
-    );
-    end component;
-    
-    function buffer_to_kernel(inp : in register_file(0 to regDepth-1)) return register_file is
-        variable ret : register_file(0 to kernelSize*kernelSize-1);
-    begin
-        for x in integer range 0 to kernelSize - 1 loop
-            for y in integer range 0 to kernelSize - 1 loop
-                ret(x + y * kernelSize) := inp(imageWidth*(kernelSize-1-y) + (kernelSize-1-x));
-            end loop;
-        end loop;
-        return ret;
-    end function;
-    
-    signal kernelOutput : std_logic_vector(busWidth-1 downto 0);
-    signal inputBuffer : register_file(0 to regDepth-1);
-    signal kernelValues : register_file(0 to kernelSize*kernelSize-1);
-    signal dataIndex : integer range 0 to imageWidth*imageWidth;
-    
-    signal working : std_logic := '0';
-    signal dstStalled_s : std_logic := '0';
-    signal dstValid_s : std_logic := '0';
-    
-begin
-    kernel_5x5 : kernel_NxN port map (
-        kernelValues => kernelValues,
-        inputValues => buffer_to_kernel(inputBuffer),
-        outputValue => kernelOutput
-    );
-    dstData <= kernelOutput;
-    shiftIn2: shiftIn port map (
-        clk         => clk,
-        ce          => dstValid_s,
-        sync_reset  => working,
-        dataIn      => srcData,
-        dataOut     => inputBuffer,
-        dataIndex    => dataIndex
-    );
-    
-    setKernel : process(rst_n) begin
-        kernelValues <= (others => (others => '0'));
-        
-        -- 0  0  0  0  0
-        -- 0 -1 -1 -1  0
-        -- 0 -1  8 -1  0
-        -- 0 -1 -1 -1  0
-        -- 0  0  0  0  0
-        
-        kernelValues(6) <= x"FFFFFFFF";
-        kernelValues(7) <= x"FFFFFFFF";
-        kernelValues(8) <= x"FFFFFFFF";
-        
-        kernelValues(11) <= x"FFFFFFFF";
-        kernelValues(12) <= x"00000008";
-        kernelValues(13) <= x"FFFFFFFF";
-        
-        kernelValues(16) <= x"FFFFFFFF";
-        kernelValues(17) <= x"FFFFFFFF";
-        kernelValues(18) <= x"FFFFFFFF";
-        
-    end process;
-    
-    dataPathStall : process(rst_n, clk)
-    
-    begin
-        if rst_n = '0' then
-            dstStalled_s <= '0';
-        elsif rising_edge(clk) then
-            if working = '1' and srcValid = '1' and dstReady = '0' then
-                dstStalled_s <= '1';
-            elsif dstStalled_s = '1' and working = '1' and dstReady = '1' then
-                dstStalled_s <= '0';
-            end if;
-        end if;
-    end process;
-    
-    dstValid_s <= working and dstReady and (srcValid or dstStalled_s);
-    dstValid <= dstValid_s;
-    
-    srcRdy : process(dataIndex, working, dstReady, srcValid, start) begin
-        if (dataIndex = imageWidth*imageWidth - 1 and srcValid = '1') or dataIndex = imageWidth*imageWidth then
-            srcReady <= '0';
-        else
-            srcReady <= working and dstReady and not dstStalled_s and start;
-        end if;
-    end process;
-    
-    reset : process(rst_n, clk)
-    begin
-        if rst_n = '0' then
-            working <= '0';
-            done <= '0';
-        elsif rising_edge(clk) then
-            done <= '0';
-            working <= '0';
-           
-            if dataIndex = imageWidth*imageWidth - 1 and dstValid_s = '1' then
-                done <= '1';
-                working <= '1';
-            elsif dataIndex = imageWidth*imageWidth then
-                working <= '0';
-            elsif start = '1' then
-                working <= '1';
-            end if;
-        end if;
-    end process;
-    
-    idle <= rst_n and not working;
-    ready <= rst_n;
-    
-    
-
-end Behavioral;

src/testbench/dut_packaging/ipshared/22b5/src/dummyModule.vhd

@@ -1,117 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 12.06.2019 22:30:43
--- Design Name: 
--- Module Name: dummyModule - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity dummyModule is
-    generic(
-        busWidth : integer:=32;
-        regDepth : integer:=4);
-    Port ( clk : in STD_LOGIC;
-           rst_n : in STD_LOGIC;
-           start : in STD_LOGIC;
-           ready: out std_logic;
-           idle : out std_logic;
-           done : out std_logic;
-           
-           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           srcValid : in std_logic;
-           srcReady : out std_logic;
-           
-           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           dstValid : out std_logic;
-           dstReady : in std_logic);
-end dummyModule;
-
-architecture Behavioral of dummyModule is
-    signal working : std_logic := '0';
-    signal dstStalled_s : std_logic := '0';
-    signal dstValid_s : std_logic := '0';
-    
-    signal dataIndex : integer range 0 to regDepth;
-begin
-    
-    dstData <= srcData;
-    
-    reset : process(rst_n, clk)
-    begin
-        if rst_n = '0' then
-            working <= '0';
-            done <= '0';
-        elsif rising_edge(clk) then
-            done <= '0';
-            working <= '0';
-           
-            if dataIndex = regDepth - 1 and dstValid_s = '1' then
-                done <= '1';
-                working <= '1';
-            elsif dataIndex = regDepth then
-                working <= '0';
-            elsif start = '1' then
-                working <= '1';
-            end if;
-        end if;
-    end process;
-    
-    idle <= rst_n and not working;
-    ready <= rst_n;
-    
-    dataPathStall : process(rst_n, clk)
-    
-    begin
-        if rst_n = '0' then
-            dstStalled_s <= '0';
-        elsif rising_edge(clk) then
-            if working = '1' and srcValid = '1' and dstReady = '0' then
-                dstStalled_s <= '1';
-            elsif dstStalled_s = '1' and working = '1' and dstReady = '1' then
-                dstStalled_s <= '0';
-            end if;
-        end if;
-    end process;
-    
-    dstValid_s <= working and dstReady and (srcValid or dstStalled_s);
-    dstValid <= dstValid_s;
-    
-    srcRdy : process(dataIndex, working, dstReady, srcValid, start) begin
-        if (dataIndex = regDepth - 1 and srcValid = '1') or dataIndex = regDepth then
-            srcReady <= '0';
-        else
-            srcReady <= working and dstReady and not dstStalled_s and start;
-        end if;
-    end process;
-    
-    dataCounter : process(rst_n, clk) begin
-        if rst_n = '0' then
-            dataIndex <= 0;
-        elsif rising_edge(clk) then
-            if start = '1' and srcValid = '1' then
-                dataIndex <= dataIndex + 1;
-            elsif start = '0' then
-                dataIndex <= 0;
-            else
-                dataIndex <= dataIndex;
-            end if;
-        end if;
-    end process;
-end Behavioral;

src/testbench/dut_packaging/ipshared/22b5/src/fifo_w32_d2_A.vhd

@@ -1,140 +0,0 @@
--- ==============================================================
--- File generated on Wed Jun 26 16:53:30 CEST 2019
--- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
--- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
--- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--- ==============================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity fifo_w32_d2_A_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 32;
-        ADDR_WIDTH : integer := 1;
-        DEPTH : integer := 2);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-end fifo_w32_d2_A_shiftReg;
-
-architecture rtl of fifo_w32_d2_A_shiftReg is
---constant DEPTH_WIDTH: integer := 16;
-type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-signal SRL_SIG : SRL_ARRAY;
-
-begin
-p_shift: process (clk)
-begin
-    if (clk'event and clk = '1') then
-        if (ce = '1') then
-            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
-        end if;
-    end if;
-end process;
-
-q <= SRL_SIG(conv_integer(a));
-
-end rtl;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-entity fifo_w32_d2_A is 
-    generic (
-        MEM_STYLE  : string := "shiftreg"; 
-        DATA_WIDTH : integer := 32;
-        ADDR_WIDTH : integer := 1;
-        DEPTH : integer := 2);
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_empty_n : OUT STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_read : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
-end entity;
-
-architecture rtl of fifo_w32_d2_A is
-
-    component fifo_w32_d2_A_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 32;
-        ADDR_WIDTH : integer := 1;
-        DEPTH : integer := 2);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-    end component;
-
-    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
-    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-    signal shiftReg_ce : STD_LOGIC;
-    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
-    signal internal_empty_n : STD_LOGIC := '0';
-    signal internal_full_n  : STD_LOGIC := '1';
-
-begin
-    if_empty_n <= internal_empty_n;
-    if_full_n <= internal_full_n;
-    shiftReg_data <= if_din;
-    if_dout <= shiftReg_q;
-
-    process (clk)
-    begin
-        if clk'event and clk = '1' then
-            if reset = '1' then
-                mOutPtr <= (others => '1');
-                internal_empty_n <= '0';
-                internal_full_n <= '1';
-            else
-                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
-                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
-                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2);
-                    if (mOutPtr = conv_std_logic_vector(0, 2)) then 
-                        internal_empty_n <= '0';
-                    end if;
-                    internal_full_n <= '1';
-                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
-                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
-                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2);
-                    internal_empty_n <= '1';
-                    if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then 
-                        internal_full_n <= '0';
-                    end if;
-                end if;
-            end if;
-        end if;
-    end process;
-
-    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
-    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
-
-    U_fifo_w32_d2_A_shiftReg : fifo_w32_d2_A_shiftReg
-    generic map (
-        DATA_WIDTH => DATA_WIDTH,
-        ADDR_WIDTH => ADDR_WIDTH,
-        DEPTH => DEPTH)
-    port map (
-        clk => clk,
-        data => shiftReg_data,
-        ce => shiftReg_ce,
-        a => shiftReg_addr,
-        q => shiftReg_q);
-
-end rtl;
-

src/testbench/dut_packaging/ipshared/22b5/src/fifo_w32_d3_A.vhd

@@ -1,140 +0,0 @@
--- ==============================================================
--- File generated on Wed Jun 26 16:53:30 CEST 2019
--- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
--- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
--- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--- ==============================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity fifo_w32_d3_A_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 32;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-end fifo_w32_d3_A_shiftReg;
-
-architecture rtl of fifo_w32_d3_A_shiftReg is
---constant DEPTH_WIDTH: integer := 16;
-type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-signal SRL_SIG : SRL_ARRAY;
-
-begin
-p_shift: process (clk)
-begin
-    if (clk'event and clk = '1') then
-        if (ce = '1') then
-            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
-        end if;
-    end if;
-end process;
-
-q <= SRL_SIG(conv_integer(a));
-
-end rtl;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-entity fifo_w32_d3_A is 
-    generic (
-        MEM_STYLE  : string := "shiftreg"; 
-        DATA_WIDTH : integer := 32;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_empty_n : OUT STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_read : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
-end entity;
-
-architecture rtl of fifo_w32_d3_A is
-
-    component fifo_w32_d3_A_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 32;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-    end component;
-
-    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
-    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-    signal shiftReg_ce : STD_LOGIC;
-    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
-    signal internal_empty_n : STD_LOGIC := '0';
-    signal internal_full_n  : STD_LOGIC := '1';
-
-begin
-    if_empty_n <= internal_empty_n;
-    if_full_n <= internal_full_n;
-    shiftReg_data <= if_din;
-    if_dout <= shiftReg_q;
-
-    process (clk)
-    begin
-        if clk'event and clk = '1' then
-            if reset = '1' then
-                mOutPtr <= (others => '1');
-                internal_empty_n <= '0';
-                internal_full_n <= '1';
-            else
-                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
-                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
-                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
-                    if (mOutPtr = conv_std_logic_vector(0, 3)) then 
-                        internal_empty_n <= '0';
-                    end if;
-                    internal_full_n <= '1';
-                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
-                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
-                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
-                    internal_empty_n <= '1';
-                    if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then 
-                        internal_full_n <= '0';
-                    end if;
-                end if;
-            end if;
-        end if;
-    end process;
-
-    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
-    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
-
-    U_fifo_w32_d3_A_shiftReg : fifo_w32_d3_A_shiftReg
-    generic map (
-        DATA_WIDTH => DATA_WIDTH,
-        ADDR_WIDTH => ADDR_WIDTH,
-        DEPTH => DEPTH)
-    port map (
-        clk => clk,
-        data => shiftReg_data,
-        ce => shiftReg_ce,
-        a => shiftReg_addr,
-        q => shiftReg_q);
-
-end rtl;
-

src/testbench/dut_packaging/ipshared/22b5/src/filter11x11_strm.vhd

@@ -1,923 +0,0 @@
--- ==============================================================
--- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
--- Version: 2018.3
--- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--- 
--- ===========================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity filter11x11_strm is
-port (
-    width : IN STD_LOGIC_VECTOR (31 downto 0);
-    height : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt1 : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt2 : IN STD_LOGIC_VECTOR (31 downto 0);
-    src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
-    dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
-    ap_clk : IN STD_LOGIC;
-    ap_rst_n : IN STD_LOGIC;
-    ap_start : IN STD_LOGIC;
-    src_V_TVALID : IN STD_LOGIC;
-    src_V_TREADY : OUT STD_LOGIC;
-    dst_V_TVALID : OUT STD_LOGIC;
-    dst_V_TREADY : IN STD_LOGIC;
-    ap_done : OUT STD_LOGIC;
-    ap_ready : OUT STD_LOGIC;
-    ap_idle : OUT STD_LOGIC );
-end;
-
-
-architecture behav of filter11x11_strm is 
-    attribute CORE_GENERATION_INFO : STRING;
-    attribute CORE_GENERATION_INFO of behav : architecture is
-    "filter11x11_strm,hls_ip_2018_3,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7a100tcsg324-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.470000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=22,HLS_SYN_DSP=28,HLS_SYN_FF=3339,HLS_SYN_LUT=3643,HLS_VERSION=2018_3}";
-    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
-    constant ap_const_logic_1 : STD_LOGIC := '1';
-    constant ap_const_logic_0 : STD_LOGIC := '0';
-    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
-    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
-    constant ap_const_boolean_1 : BOOLEAN := true;
-
-    signal ap_rst_n_inv : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_ap_start : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_start_full_n : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_ap_done : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_ap_continue : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_ap_idle : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_ap_ready : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_start_out : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_start_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_width_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_width_out_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_width_out1_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_width_out1_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_height_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_height_out_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_height_out2_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_height_out2_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_filt1_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_filt1_out_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_filt1_out3_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_filt1_out3_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_filt2_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_filt2_out_write : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_filt2_out4_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal filter11x11_strm_ent_U0_filt2_out4_write : STD_LOGIC;
-    signal Block_proc_U0_ap_start : STD_LOGIC;
-    signal Block_proc_U0_ap_done : STD_LOGIC;
-    signal Block_proc_U0_ap_continue : STD_LOGIC;
-    signal Block_proc_U0_ap_idle : STD_LOGIC;
-    signal Block_proc_U0_ap_ready : STD_LOGIC;
-    signal Block_proc_U0_start_out : STD_LOGIC;
-    signal Block_proc_U0_start_write : STD_LOGIC;
-    signal Block_proc_U0_width_read : STD_LOGIC;
-    signal Block_proc_U0_height_read : STD_LOGIC;
-    signal Block_proc_U0_width_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal Block_proc_U0_width_out_write : STD_LOGIC;
-    signal Block_proc_U0_height_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal Block_proc_U0_height_out_write : STD_LOGIC;
-    signal Block_proc_U0_vconv_xlim_out_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal Block_proc_U0_vconv_xlim_out_out_write : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_ap_start : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_ap_done : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_ap_continue : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_ap_idle : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_ap_ready : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_height_read : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_width_read : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_src_V_TREADY : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_filt1_read : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_filt2_read : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_hconv_V_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal Loop_HConvH_proc6_U0_hconv_V_write : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_ap_start : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_ap_done : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_ap_continue : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_ap_idle : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_ap_ready : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_height_read : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_vconv_xlim_loc_read : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_hconv_V_read : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_vconv_V_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal Loop_VConvH_proc_U0_vconv_V_write : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_filt1_read : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_filt2_read : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_height_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal Loop_VConvH_proc_U0_height_out_write : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_vconv_xlim_loc_out_din : STD_LOGIC_VECTOR (31 downto 0);
-    signal Loop_VConvH_proc_U0_vconv_xlim_loc_out_write : STD_LOGIC;
-    signal Loop_Border_proc_U0_ap_start : STD_LOGIC;
-    signal Loop_Border_proc_U0_ap_done : STD_LOGIC;
-    signal Loop_Border_proc_U0_ap_continue : STD_LOGIC;
-    signal Loop_Border_proc_U0_ap_idle : STD_LOGIC;
-    signal Loop_Border_proc_U0_ap_ready : STD_LOGIC;
-    signal Loop_Border_proc_U0_width_read : STD_LOGIC;
-    signal Loop_Border_proc_U0_height_read : STD_LOGIC;
-    signal Loop_Border_proc_U0_dst_V_TDATA : STD_LOGIC_VECTOR (31 downto 0);
-    signal Loop_Border_proc_U0_dst_V_TVALID : STD_LOGIC;
-    signal Loop_Border_proc_U0_vconv_xlim_loc_read : STD_LOGIC;
-    signal Loop_Border_proc_U0_vconv_V_read : STD_LOGIC;
-    signal ap_sync_continue : STD_LOGIC;
-    signal width_c_full_n : STD_LOGIC;
-    signal width_c_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal width_c_empty_n : STD_LOGIC;
-    signal width_c155_full_n : STD_LOGIC;
-    signal width_c155_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal width_c155_empty_n : STD_LOGIC;
-    signal height_c_full_n : STD_LOGIC;
-    signal height_c_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal height_c_empty_n : STD_LOGIC;
-    signal height_c156_full_n : STD_LOGIC;
-    signal height_c156_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal height_c156_empty_n : STD_LOGIC;
-    signal filt1_c_full_n : STD_LOGIC;
-    signal filt1_c_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt1_c_empty_n : STD_LOGIC;
-    signal filt1_c157_full_n : STD_LOGIC;
-    signal filt1_c157_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt1_c157_empty_n : STD_LOGIC;
-    signal filt2_c_full_n : STD_LOGIC;
-    signal filt2_c_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt2_c_empty_n : STD_LOGIC;
-    signal filt2_c158_full_n : STD_LOGIC;
-    signal filt2_c158_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal filt2_c158_empty_n : STD_LOGIC;
-    signal width_c159_full_n : STD_LOGIC;
-    signal width_c159_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal width_c159_empty_n : STD_LOGIC;
-    signal height_c160_full_n : STD_LOGIC;
-    signal height_c160_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal height_c160_empty_n : STD_LOGIC;
-    signal vconv_xlim_loc_c_full_n : STD_LOGIC;
-    signal vconv_xlim_loc_c_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal vconv_xlim_loc_c_empty_n : STD_LOGIC;
-    signal hconv_V_full_n : STD_LOGIC;
-    signal hconv_V_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal hconv_V_empty_n : STD_LOGIC;
-    signal vconv_V_full_n : STD_LOGIC;
-    signal vconv_V_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal vconv_V_empty_n : STD_LOGIC;
-    signal height_c161_full_n : STD_LOGIC;
-    signal height_c161_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal height_c161_empty_n : STD_LOGIC;
-    signal vconv_xlim_loc_c162_full_n : STD_LOGIC;
-    signal vconv_xlim_loc_c162_dout : STD_LOGIC_VECTOR (31 downto 0);
-    signal vconv_xlim_loc_c162_empty_n : STD_LOGIC;
-    signal ap_sync_done : STD_LOGIC;
-    signal ap_sync_ready : STD_LOGIC;
-    signal ap_sync_reg_filter11x11_strm_ent_U0_ap_ready : STD_LOGIC := '0';
-    signal ap_sync_filter11x11_strm_ent_U0_ap_ready : STD_LOGIC;
-    signal filter11x11_strm_ent_U0_ap_ready_count : STD_LOGIC_VECTOR (1 downto 0) := "00";
-    signal ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready : STD_LOGIC := '0';
-    signal ap_sync_Loop_HConvH_proc6_U0_ap_ready : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_ap_ready_count : STD_LOGIC_VECTOR (1 downto 0) := "00";
-    signal start_for_Block_proc_U0_din : STD_LOGIC_VECTOR (0 downto 0);
-    signal start_for_Block_proc_U0_full_n : STD_LOGIC;
-    signal start_for_Block_proc_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
-    signal start_for_Block_proc_U0_empty_n : STD_LOGIC;
-    signal start_for_Loop_VConvH_proc_U0_din : STD_LOGIC_VECTOR (0 downto 0);
-    signal start_for_Loop_VConvH_proc_U0_full_n : STD_LOGIC;
-    signal start_for_Loop_VConvH_proc_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
-    signal start_for_Loop_VConvH_proc_U0_empty_n : STD_LOGIC;
-    signal start_for_Loop_Border_proc_U0_din : STD_LOGIC_VECTOR (0 downto 0);
-    signal start_for_Loop_Border_proc_U0_full_n : STD_LOGIC;
-    signal start_for_Loop_Border_proc_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
-    signal start_for_Loop_Border_proc_U0_empty_n : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_start_full_n : STD_LOGIC;
-    signal Loop_HConvH_proc6_U0_start_write : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_start_full_n : STD_LOGIC;
-    signal Loop_VConvH_proc_U0_start_write : STD_LOGIC;
-    signal Loop_Border_proc_U0_start_full_n : STD_LOGIC;
-    signal Loop_Border_proc_U0_start_write : STD_LOGIC;
-
-    component filter11x11_strm_ent IS
-    port (
-        ap_clk : IN STD_LOGIC;
-        ap_rst : IN STD_LOGIC;
-        ap_start : IN STD_LOGIC;
-        start_full_n : IN STD_LOGIC;
-        ap_done : OUT STD_LOGIC;
-        ap_continue : IN STD_LOGIC;
-        ap_idle : OUT STD_LOGIC;
-        ap_ready : OUT STD_LOGIC;
-        start_out : OUT STD_LOGIC;
-        start_write : OUT STD_LOGIC;
-        width : IN STD_LOGIC_VECTOR (31 downto 0);
-        height : IN STD_LOGIC_VECTOR (31 downto 0);
-        filt1 : IN STD_LOGIC_VECTOR (31 downto 0);
-        filt2 : IN STD_LOGIC_VECTOR (31 downto 0);
-        width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        width_out_full_n : IN STD_LOGIC;
-        width_out_write : OUT STD_LOGIC;
-        width_out1_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        width_out1_full_n : IN STD_LOGIC;
-        width_out1_write : OUT STD_LOGIC;
-        height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        height_out_full_n : IN STD_LOGIC;
-        height_out_write : OUT STD_LOGIC;
-        height_out2_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        height_out2_full_n : IN STD_LOGIC;
-        height_out2_write : OUT STD_LOGIC;
-        filt1_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        filt1_out_full_n : IN STD_LOGIC;
-        filt1_out_write : OUT STD_LOGIC;
-        filt1_out3_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        filt1_out3_full_n : IN STD_LOGIC;
-        filt1_out3_write : OUT STD_LOGIC;
-        filt2_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        filt2_out_full_n : IN STD_LOGIC;
-        filt2_out_write : OUT STD_LOGIC;
-        filt2_out4_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        filt2_out4_full_n : IN STD_LOGIC;
-        filt2_out4_write : OUT STD_LOGIC );
-    end component;
-
-
-    component Block_proc IS
-    port (
-        ap_clk : IN STD_LOGIC;
-        ap_rst : IN STD_LOGIC;
-        ap_start : IN STD_LOGIC;
-        start_full_n : IN STD_LOGIC;
-        ap_done : OUT STD_LOGIC;
-        ap_continue : IN STD_LOGIC;
-        ap_idle : OUT STD_LOGIC;
-        ap_ready : OUT STD_LOGIC;
-        start_out : OUT STD_LOGIC;
-        start_write : OUT STD_LOGIC;
-        width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        width_empty_n : IN STD_LOGIC;
-        width_read : OUT STD_LOGIC;
-        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        height_empty_n : IN STD_LOGIC;
-        height_read : OUT STD_LOGIC;
-        width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        width_out_full_n : IN STD_LOGIC;
-        width_out_write : OUT STD_LOGIC;
-        height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        height_out_full_n : IN STD_LOGIC;
-        height_out_write : OUT STD_LOGIC;
-        vconv_xlim_out_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        vconv_xlim_out_out_full_n : IN STD_LOGIC;
-        vconv_xlim_out_out_write : OUT STD_LOGIC );
-    end component;
-
-
-    component Loop_HConvH_proc6 IS
-    port (
-        ap_clk : IN STD_LOGIC;
-        ap_rst : IN STD_LOGIC;
-        ap_start : IN STD_LOGIC;
-        ap_done : OUT STD_LOGIC;
-        ap_continue : IN STD_LOGIC;
-        ap_idle : OUT STD_LOGIC;
-        ap_ready : OUT STD_LOGIC;
-        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        height_empty_n : IN STD_LOGIC;
-        height_read : OUT STD_LOGIC;
-        width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        width_empty_n : IN STD_LOGIC;
-        width_read : OUT STD_LOGIC;
-        src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
-        src_V_TVALID : IN STD_LOGIC;
-        src_V_TREADY : OUT STD_LOGIC;
-        filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        filt1_empty_n : IN STD_LOGIC;
-        filt1_read : OUT STD_LOGIC;
-        filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        filt2_empty_n : IN STD_LOGIC;
-        filt2_read : OUT STD_LOGIC;
-        hconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        hconv_V_full_n : IN STD_LOGIC;
-        hconv_V_write : OUT STD_LOGIC );
-    end component;
-
-
-    component Loop_VConvH_proc IS
-    port (
-        ap_clk : IN STD_LOGIC;
-        ap_rst : IN STD_LOGIC;
-        ap_start : IN STD_LOGIC;
-        ap_done : OUT STD_LOGIC;
-        ap_continue : IN STD_LOGIC;
-        ap_idle : OUT STD_LOGIC;
-        ap_ready : OUT STD_LOGIC;
-        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        height_empty_n : IN STD_LOGIC;
-        height_read : OUT STD_LOGIC;
-        vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        vconv_xlim_loc_empty_n : IN STD_LOGIC;
-        vconv_xlim_loc_read : OUT STD_LOGIC;
-        hconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        hconv_V_empty_n : IN STD_LOGIC;
-        hconv_V_read : OUT STD_LOGIC;
-        vconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        vconv_V_full_n : IN STD_LOGIC;
-        vconv_V_write : OUT STD_LOGIC;
-        filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        filt1_empty_n : IN STD_LOGIC;
-        filt1_read : OUT STD_LOGIC;
-        filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        filt2_empty_n : IN STD_LOGIC;
-        filt2_read : OUT STD_LOGIC;
-        height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        height_out_full_n : IN STD_LOGIC;
-        height_out_write : OUT STD_LOGIC;
-        vconv_xlim_loc_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-        vconv_xlim_loc_out_full_n : IN STD_LOGIC;
-        vconv_xlim_loc_out_write : OUT STD_LOGIC );
-    end component;
-
-
-    component Loop_Border_proc IS
-    port (
-        ap_clk : IN STD_LOGIC;
-        ap_rst : IN STD_LOGIC;
-        ap_start : IN STD_LOGIC;
-        ap_done : OUT STD_LOGIC;
-        ap_continue : IN STD_LOGIC;
-        ap_idle : OUT STD_LOGIC;
-        ap_ready : OUT STD_LOGIC;
-        width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        width_empty_n : IN STD_LOGIC;
-        width_read : OUT STD_LOGIC;
-        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        height_empty_n : IN STD_LOGIC;
-        height_read : OUT STD_LOGIC;
-        dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
-        dst_V_TVALID : OUT STD_LOGIC;
-        dst_V_TREADY : IN STD_LOGIC;
-        vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        vconv_xlim_loc_empty_n : IN STD_LOGIC;
-        vconv_xlim_loc_read : OUT STD_LOGIC;
-        vconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
-        vconv_V_empty_n : IN STD_LOGIC;
-        vconv_V_read : OUT STD_LOGIC );
-    end component;
-
-
-    component fifo_w32_d2_A IS
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR (31 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR (31 downto 0);
-        if_empty_n : OUT STD_LOGIC;
-        if_read : IN STD_LOGIC );
-    end component;
-
-
-    component fifo_w32_d3_A IS
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR (31 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR (31 downto 0);
-        if_empty_n : OUT STD_LOGIC;
-        if_read : IN STD_LOGIC );
-    end component;
-
-
-    component start_for_Block_proc_U0 IS
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR (0 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
-        if_empty_n : OUT STD_LOGIC;
-        if_read : IN STD_LOGIC );
-    end component;
-
-
-    component start_for_Loop_VConvH_proc_U0 IS
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR (0 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
-        if_empty_n : OUT STD_LOGIC;
-        if_read : IN STD_LOGIC );
-    end component;
-
-
-    component start_for_Loop_Border_proc_U0 IS
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR (0 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
-        if_empty_n : OUT STD_LOGIC;
-        if_read : IN STD_LOGIC );
-    end component;
-
-
-
-begin
-    filter11x11_strm_ent_U0 : component filter11x11_strm_ent
-    port map (
-        ap_clk => ap_clk,
-        ap_rst => ap_rst_n_inv,
-        ap_start => filter11x11_strm_ent_U0_ap_start,
-        start_full_n => filter11x11_strm_ent_U0_start_full_n,
-        ap_done => filter11x11_strm_ent_U0_ap_done,
-        ap_continue => filter11x11_strm_ent_U0_ap_continue,
-        ap_idle => filter11x11_strm_ent_U0_ap_idle,
-        ap_ready => filter11x11_strm_ent_U0_ap_ready,
-        start_out => filter11x11_strm_ent_U0_start_out,
-        start_write => filter11x11_strm_ent_U0_start_write,
-        width => width,
-        height => height,
-        filt1 => filt1,
-        filt2 => filt2,
-        width_out_din => filter11x11_strm_ent_U0_width_out_din,
-        width_out_full_n => width_c_full_n,
-        width_out_write => filter11x11_strm_ent_U0_width_out_write,
-        width_out1_din => filter11x11_strm_ent_U0_width_out1_din,
-        width_out1_full_n => width_c155_full_n,
-        width_out1_write => filter11x11_strm_ent_U0_width_out1_write,
-        height_out_din => filter11x11_strm_ent_U0_height_out_din,
-        height_out_full_n => height_c_full_n,
-        height_out_write => filter11x11_strm_ent_U0_height_out_write,
-        height_out2_din => filter11x11_strm_ent_U0_height_out2_din,
-        height_out2_full_n => height_c156_full_n,
-        height_out2_write => filter11x11_strm_ent_U0_height_out2_write,
-        filt1_out_din => filter11x11_strm_ent_U0_filt1_out_din,
-        filt1_out_full_n => filt1_c_full_n,
-        filt1_out_write => filter11x11_strm_ent_U0_filt1_out_write,
-        filt1_out3_din => filter11x11_strm_ent_U0_filt1_out3_din,
-        filt1_out3_full_n => filt1_c157_full_n,
-        filt1_out3_write => filter11x11_strm_ent_U0_filt1_out3_write,
-        filt2_out_din => filter11x11_strm_ent_U0_filt2_out_din,
-        filt2_out_full_n => filt2_c_full_n,
-        filt2_out_write => filter11x11_strm_ent_U0_filt2_out_write,
-        filt2_out4_din => filter11x11_strm_ent_U0_filt2_out4_din,
-        filt2_out4_full_n => filt2_c158_full_n,
-        filt2_out4_write => filter11x11_strm_ent_U0_filt2_out4_write);
-
-    Block_proc_U0 : component Block_proc
-    port map (
-        ap_clk => ap_clk,
-        ap_rst => ap_rst_n_inv,
-        ap_start => Block_proc_U0_ap_start,
-        start_full_n => start_for_Loop_Border_proc_U0_full_n,
-        ap_done => Block_proc_U0_ap_done,
-        ap_continue => Block_proc_U0_ap_continue,
-        ap_idle => Block_proc_U0_ap_idle,
-        ap_ready => Block_proc_U0_ap_ready,
-        start_out => Block_proc_U0_start_out,
-        start_write => Block_proc_U0_start_write,
-        width_dout => width_c_dout,
-        width_empty_n => width_c_empty_n,
-        width_read => Block_proc_U0_width_read,
-        height_dout => height_c_dout,
-        height_empty_n => height_c_empty_n,
-        height_read => Block_proc_U0_height_read,
-        width_out_din => Block_proc_U0_width_out_din,
-        width_out_full_n => width_c159_full_n,
-        width_out_write => Block_proc_U0_width_out_write,
-        height_out_din => Block_proc_U0_height_out_din,
-        height_out_full_n => height_c160_full_n,
-        height_out_write => Block_proc_U0_height_out_write,
-        vconv_xlim_out_out_din => Block_proc_U0_vconv_xlim_out_out_din,
-        vconv_xlim_out_out_full_n => vconv_xlim_loc_c_full_n,
-        vconv_xlim_out_out_write => Block_proc_U0_vconv_xlim_out_out_write);
-
-    Loop_HConvH_proc6_U0 : component Loop_HConvH_proc6
-    port map (
-        ap_clk => ap_clk,
-        ap_rst => ap_rst_n_inv,
-        ap_start => Loop_HConvH_proc6_U0_ap_start,
-        ap_done => Loop_HConvH_proc6_U0_ap_done,
-        ap_continue => Loop_HConvH_proc6_U0_ap_continue,
-        ap_idle => Loop_HConvH_proc6_U0_ap_idle,
-        ap_ready => Loop_HConvH_proc6_U0_ap_ready,
-        height_dout => height_c156_dout,
-        height_empty_n => height_c156_empty_n,
-        height_read => Loop_HConvH_proc6_U0_height_read,
-        width_dout => width_c155_dout,
-        width_empty_n => width_c155_empty_n,
-        width_read => Loop_HConvH_proc6_U0_width_read,
-        src_V_TDATA => src_V_TDATA,
-        src_V_TVALID => src_V_TVALID,
-        src_V_TREADY => Loop_HConvH_proc6_U0_src_V_TREADY,
-        filt1_dout => filt1_c_dout,
-        filt1_empty_n => filt1_c_empty_n,
-        filt1_read => Loop_HConvH_proc6_U0_filt1_read,
-        filt2_dout => filt2_c_dout,
-        filt2_empty_n => filt2_c_empty_n,
-        filt2_read => Loop_HConvH_proc6_U0_filt2_read,
-        hconv_V_din => Loop_HConvH_proc6_U0_hconv_V_din,
-        hconv_V_full_n => hconv_V_full_n,
-        hconv_V_write => Loop_HConvH_proc6_U0_hconv_V_write);
-
-    Loop_VConvH_proc_U0 : component Loop_VConvH_proc
-    port map (
-        ap_clk => ap_clk,
-        ap_rst => ap_rst_n_inv,
-        ap_start => Loop_VConvH_proc_U0_ap_start,
-        ap_done => Loop_VConvH_proc_U0_ap_done,
-        ap_continue => Loop_VConvH_proc_U0_ap_continue,
-        ap_idle => Loop_VConvH_proc_U0_ap_idle,
-        ap_ready => Loop_VConvH_proc_U0_ap_ready,
-        height_dout => height_c160_dout,
-        height_empty_n => height_c160_empty_n,
-        height_read => Loop_VConvH_proc_U0_height_read,
-        vconv_xlim_loc_dout => vconv_xlim_loc_c_dout,
-        vconv_xlim_loc_empty_n => vconv_xlim_loc_c_empty_n,
-        vconv_xlim_loc_read => Loop_VConvH_proc_U0_vconv_xlim_loc_read,
-        hconv_V_dout => hconv_V_dout,
-        hconv_V_empty_n => hconv_V_empty_n,
-        hconv_V_read => Loop_VConvH_proc_U0_hconv_V_read,
-        vconv_V_din => Loop_VConvH_proc_U0_vconv_V_din,
-        vconv_V_full_n => vconv_V_full_n,
-        vconv_V_write => Loop_VConvH_proc_U0_vconv_V_write,
-        filt1_dout => filt1_c157_dout,
-        filt1_empty_n => filt1_c157_empty_n,
-        filt1_read => Loop_VConvH_proc_U0_filt1_read,
-        filt2_dout => filt2_c158_dout,
-        filt2_empty_n => filt2_c158_empty_n,
-        filt2_read => Loop_VConvH_proc_U0_filt2_read,
-        height_out_din => Loop_VConvH_proc_U0_height_out_din,
-        height_out_full_n => height_c161_full_n,
-        height_out_write => Loop_VConvH_proc_U0_height_out_write,
-        vconv_xlim_loc_out_din => Loop_VConvH_proc_U0_vconv_xlim_loc_out_din,
-        vconv_xlim_loc_out_full_n => vconv_xlim_loc_c162_full_n,
-        vconv_xlim_loc_out_write => Loop_VConvH_proc_U0_vconv_xlim_loc_out_write);
-
-    Loop_Border_proc_U0 : component Loop_Border_proc
-    port map (
-        ap_clk => ap_clk,
-        ap_rst => ap_rst_n_inv,
-        ap_start => Loop_Border_proc_U0_ap_start,
-        ap_done => Loop_Border_proc_U0_ap_done,
-        ap_continue => Loop_Border_proc_U0_ap_continue,
-        ap_idle => Loop_Border_proc_U0_ap_idle,
-        ap_ready => Loop_Border_proc_U0_ap_ready,
-        width_dout => width_c159_dout,
-        width_empty_n => width_c159_empty_n,
-        width_read => Loop_Border_proc_U0_width_read,
-        height_dout => height_c161_dout,
-        height_empty_n => height_c161_empty_n,
-        height_read => Loop_Border_proc_U0_height_read,
-        dst_V_TDATA => Loop_Border_proc_U0_dst_V_TDATA,
-        dst_V_TVALID => Loop_Border_proc_U0_dst_V_TVALID,
-        dst_V_TREADY => dst_V_TREADY,
-        vconv_xlim_loc_dout => vconv_xlim_loc_c162_dout,
-        vconv_xlim_loc_empty_n => vconv_xlim_loc_c162_empty_n,
-        vconv_xlim_loc_read => Loop_Border_proc_U0_vconv_xlim_loc_read,
-        vconv_V_dout => vconv_V_dout,
-        vconv_V_empty_n => vconv_V_empty_n,
-        vconv_V_read => Loop_Border_proc_U0_vconv_V_read);
-
-    width_c_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_width_out_din,
-        if_full_n => width_c_full_n,
-        if_write => filter11x11_strm_ent_U0_width_out_write,
-        if_dout => width_c_dout,
-        if_empty_n => width_c_empty_n,
-        if_read => Block_proc_U0_width_read);
-
-    width_c155_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_width_out1_din,
-        if_full_n => width_c155_full_n,
-        if_write => filter11x11_strm_ent_U0_width_out1_write,
-        if_dout => width_c155_dout,
-        if_empty_n => width_c155_empty_n,
-        if_read => Loop_HConvH_proc6_U0_width_read);
-
-    height_c_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_height_out_din,
-        if_full_n => height_c_full_n,
-        if_write => filter11x11_strm_ent_U0_height_out_write,
-        if_dout => height_c_dout,
-        if_empty_n => height_c_empty_n,
-        if_read => Block_proc_U0_height_read);
-
-    height_c156_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_height_out2_din,
-        if_full_n => height_c156_full_n,
-        if_write => filter11x11_strm_ent_U0_height_out2_write,
-        if_dout => height_c156_dout,
-        if_empty_n => height_c156_empty_n,
-        if_read => Loop_HConvH_proc6_U0_height_read);
-
-    filt1_c_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_filt1_out_din,
-        if_full_n => filt1_c_full_n,
-        if_write => filter11x11_strm_ent_U0_filt1_out_write,
-        if_dout => filt1_c_dout,
-        if_empty_n => filt1_c_empty_n,
-        if_read => Loop_HConvH_proc6_U0_filt1_read);
-
-    filt1_c157_U : component fifo_w32_d3_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_filt1_out3_din,
-        if_full_n => filt1_c157_full_n,
-        if_write => filter11x11_strm_ent_U0_filt1_out3_write,
-        if_dout => filt1_c157_dout,
-        if_empty_n => filt1_c157_empty_n,
-        if_read => Loop_VConvH_proc_U0_filt1_read);
-
-    filt2_c_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_filt2_out_din,
-        if_full_n => filt2_c_full_n,
-        if_write => filter11x11_strm_ent_U0_filt2_out_write,
-        if_dout => filt2_c_dout,
-        if_empty_n => filt2_c_empty_n,
-        if_read => Loop_HConvH_proc6_U0_filt2_read);
-
-    filt2_c158_U : component fifo_w32_d3_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => filter11x11_strm_ent_U0_filt2_out4_din,
-        if_full_n => filt2_c158_full_n,
-        if_write => filter11x11_strm_ent_U0_filt2_out4_write,
-        if_dout => filt2_c158_dout,
-        if_empty_n => filt2_c158_empty_n,
-        if_read => Loop_VConvH_proc_U0_filt2_read);
-
-    width_c159_U : component fifo_w32_d3_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => Block_proc_U0_width_out_din,
-        if_full_n => width_c159_full_n,
-        if_write => Block_proc_U0_width_out_write,
-        if_dout => width_c159_dout,
-        if_empty_n => width_c159_empty_n,
-        if_read => Loop_Border_proc_U0_width_read);
-
-    height_c160_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => Block_proc_U0_height_out_din,
-        if_full_n => height_c160_full_n,
-        if_write => Block_proc_U0_height_out_write,
-        if_dout => height_c160_dout,
-        if_empty_n => height_c160_empty_n,
-        if_read => Loop_VConvH_proc_U0_height_read);
-
-    vconv_xlim_loc_c_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => Block_proc_U0_vconv_xlim_out_out_din,
-        if_full_n => vconv_xlim_loc_c_full_n,
-        if_write => Block_proc_U0_vconv_xlim_out_out_write,
-        if_dout => vconv_xlim_loc_c_dout,
-        if_empty_n => vconv_xlim_loc_c_empty_n,
-        if_read => Loop_VConvH_proc_U0_vconv_xlim_loc_read);
-
-    hconv_V_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => Loop_HConvH_proc6_U0_hconv_V_din,
-        if_full_n => hconv_V_full_n,
-        if_write => Loop_HConvH_proc6_U0_hconv_V_write,
-        if_dout => hconv_V_dout,
-        if_empty_n => hconv_V_empty_n,
-        if_read => Loop_VConvH_proc_U0_hconv_V_read);
-
-    vconv_V_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => Loop_VConvH_proc_U0_vconv_V_din,
-        if_full_n => vconv_V_full_n,
-        if_write => Loop_VConvH_proc_U0_vconv_V_write,
-        if_dout => vconv_V_dout,
-        if_empty_n => vconv_V_empty_n,
-        if_read => Loop_Border_proc_U0_vconv_V_read);
-
-    height_c161_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => Loop_VConvH_proc_U0_height_out_din,
-        if_full_n => height_c161_full_n,
-        if_write => Loop_VConvH_proc_U0_height_out_write,
-        if_dout => height_c161_dout,
-        if_empty_n => height_c161_empty_n,
-        if_read => Loop_Border_proc_U0_height_read);
-
-    vconv_xlim_loc_c162_U : component fifo_w32_d2_A
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => Loop_VConvH_proc_U0_vconv_xlim_loc_out_din,
-        if_full_n => vconv_xlim_loc_c162_full_n,
-        if_write => Loop_VConvH_proc_U0_vconv_xlim_loc_out_write,
-        if_dout => vconv_xlim_loc_c162_dout,
-        if_empty_n => vconv_xlim_loc_c162_empty_n,
-        if_read => Loop_Border_proc_U0_vconv_xlim_loc_read);
-
-    start_for_Block_proc_U0_U : component start_for_Block_proc_U0
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => start_for_Block_proc_U0_din,
-        if_full_n => start_for_Block_proc_U0_full_n,
-        if_write => filter11x11_strm_ent_U0_start_write,
-        if_dout => start_for_Block_proc_U0_dout,
-        if_empty_n => start_for_Block_proc_U0_empty_n,
-        if_read => Block_proc_U0_ap_ready);
-
-    start_for_Loop_VConvH_proc_U0_U : component start_for_Loop_VConvH_proc_U0
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => start_for_Loop_VConvH_proc_U0_din,
-        if_full_n => start_for_Loop_VConvH_proc_U0_full_n,
-        if_write => filter11x11_strm_ent_U0_start_write,
-        if_dout => start_for_Loop_VConvH_proc_U0_dout,
-        if_empty_n => start_for_Loop_VConvH_proc_U0_empty_n,
-        if_read => Loop_VConvH_proc_U0_ap_ready);
-
-    start_for_Loop_Border_proc_U0_U : component start_for_Loop_Border_proc_U0
-    port map (
-        clk => ap_clk,
-        reset => ap_rst_n_inv,
-        if_read_ce => ap_const_logic_1,
-        if_write_ce => ap_const_logic_1,
-        if_din => start_for_Loop_Border_proc_U0_din,
-        if_full_n => start_for_Loop_Border_proc_U0_full_n,
-        if_write => Block_proc_U0_start_write,
-        if_dout => start_for_Loop_Border_proc_U0_dout,
-        if_empty_n => start_for_Loop_Border_proc_U0_empty_n,
-        if_read => Loop_Border_proc_U0_ap_ready);
-
-
-
-
-
-    ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst_n_inv = '1') then
-                ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready <= ap_const_logic_0;
-            else
-                if (((ap_sync_ready and ap_start) = ap_const_logic_1)) then 
-                    ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready <= ap_const_logic_0;
-                else 
-                    ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready <= ap_sync_Loop_HConvH_proc6_U0_ap_ready;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_sync_reg_filter11x11_strm_ent_U0_ap_ready_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst_n_inv = '1') then
-                ap_sync_reg_filter11x11_strm_ent_U0_ap_ready <= ap_const_logic_0;
-            else
-                if (((ap_sync_ready and ap_start) = ap_const_logic_1)) then 
-                    ap_sync_reg_filter11x11_strm_ent_U0_ap_ready <= ap_const_logic_0;
-                else 
-                    ap_sync_reg_filter11x11_strm_ent_U0_ap_ready <= ap_sync_filter11x11_strm_ent_U0_ap_ready;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    Loop_HConvH_proc6_U0_ap_ready_count_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_const_logic_0 = Loop_HConvH_proc6_U0_ap_ready) and (ap_sync_ready = ap_const_logic_1))) then 
-                Loop_HConvH_proc6_U0_ap_ready_count <= std_logic_vector(unsigned(Loop_HConvH_proc6_U0_ap_ready_count) - unsigned(ap_const_lv2_1));
-            elsif (((ap_const_logic_1 = Loop_HConvH_proc6_U0_ap_ready) and (ap_sync_ready = ap_const_logic_0))) then 
-                Loop_HConvH_proc6_U0_ap_ready_count <= std_logic_vector(unsigned(Loop_HConvH_proc6_U0_ap_ready_count) + unsigned(ap_const_lv2_1));
-            end if; 
-        end if;
-    end process;
-
-    filter11x11_strm_ent_U0_ap_ready_count_assign_proc : process (ap_clk)
-    begin
-        if (ap_clk'event and ap_clk = '1') then
-            if (((ap_sync_ready = ap_const_logic_1) and (filter11x11_strm_ent_U0_ap_ready = ap_const_logic_0))) then 
-                filter11x11_strm_ent_U0_ap_ready_count <= std_logic_vector(unsigned(filter11x11_strm_ent_U0_ap_ready_count) - unsigned(ap_const_lv2_1));
-            elsif (((ap_sync_ready = ap_const_logic_0) and (filter11x11_strm_ent_U0_ap_ready = ap_const_logic_1))) then 
-                filter11x11_strm_ent_U0_ap_ready_count <= std_logic_vector(unsigned(filter11x11_strm_ent_U0_ap_ready_count) + unsigned(ap_const_lv2_1));
-            end if; 
-        end if;
-    end process;
-    Block_proc_U0_ap_continue <= ap_const_logic_1;
-    Block_proc_U0_ap_start <= start_for_Block_proc_U0_empty_n;
-    Loop_Border_proc_U0_ap_continue <= ap_const_logic_1;
-    Loop_Border_proc_U0_ap_start <= start_for_Loop_Border_proc_U0_empty_n;
-    Loop_Border_proc_U0_start_full_n <= ap_const_logic_1;
-    Loop_Border_proc_U0_start_write <= ap_const_logic_0;
-    Loop_HConvH_proc6_U0_ap_continue <= ap_const_logic_1;
-    Loop_HConvH_proc6_U0_ap_start <= ((ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready xor ap_const_logic_1) and ap_start);
-    Loop_HConvH_proc6_U0_start_full_n <= ap_const_logic_1;
-    Loop_HConvH_proc6_U0_start_write <= ap_const_logic_0;
-    Loop_VConvH_proc_U0_ap_continue <= ap_const_logic_1;
-    Loop_VConvH_proc_U0_ap_start <= start_for_Loop_VConvH_proc_U0_empty_n;
-    Loop_VConvH_proc_U0_start_full_n <= ap_const_logic_1;
-    Loop_VConvH_proc_U0_start_write <= ap_const_logic_0;
-    ap_done <= Loop_Border_proc_U0_ap_done;
-    ap_idle <= (filter11x11_strm_ent_U0_ap_idle and Loop_VConvH_proc_U0_ap_idle and Loop_HConvH_proc6_U0_ap_idle and Loop_Border_proc_U0_ap_idle and Block_proc_U0_ap_idle);
-    ap_ready <= ap_sync_ready;
-
-    ap_rst_n_inv_assign_proc : process(ap_rst_n)
-    begin
-                ap_rst_n_inv <= not(ap_rst_n);
-    end process;
-
-    ap_sync_Loop_HConvH_proc6_U0_ap_ready <= (ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready or Loop_HConvH_proc6_U0_ap_ready);
-    ap_sync_continue <= ap_const_logic_1;
-    ap_sync_done <= Loop_Border_proc_U0_ap_done;
-    ap_sync_filter11x11_strm_ent_U0_ap_ready <= (filter11x11_strm_ent_U0_ap_ready or ap_sync_reg_filter11x11_strm_ent_U0_ap_ready);
-    ap_sync_ready <= (ap_sync_filter11x11_strm_ent_U0_ap_ready and ap_sync_Loop_HConvH_proc6_U0_ap_ready);
-    dst_V_TDATA <= Loop_Border_proc_U0_dst_V_TDATA;
-    dst_V_TVALID <= Loop_Border_proc_U0_dst_V_TVALID;
-    filter11x11_strm_ent_U0_ap_continue <= ap_const_logic_1;
-    filter11x11_strm_ent_U0_ap_start <= ((ap_sync_reg_filter11x11_strm_ent_U0_ap_ready xor ap_const_logic_1) and ap_start);
-    filter11x11_strm_ent_U0_start_full_n <= (start_for_Loop_VConvH_proc_U0_full_n and start_for_Block_proc_U0_full_n);
-    src_V_TREADY <= Loop_HConvH_proc6_U0_src_V_TREADY;
-    start_for_Block_proc_U0_din <= (0=>ap_const_logic_1, others=>'-');
-    start_for_Loop_Border_proc_U0_din <= (0=>ap_const_logic_1, others=>'-');
-    start_for_Loop_VConvH_proc_U0_din <= (0=>ap_const_logic_1, others=>'-');
-end behav;

src/testbench/dut_packaging/ipshared/22b5/src/filter11x11_strm_ent.vhd

@@ -1,368 +0,0 @@
--- ==============================================================
--- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
--- Version: 2018.3
--- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--- 
--- ===========================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity filter11x11_strm_ent is
-port (
-    ap_clk : IN STD_LOGIC;
-    ap_rst : IN STD_LOGIC;
-    ap_start : IN STD_LOGIC;
-    start_full_n : IN STD_LOGIC;
-    ap_done : OUT STD_LOGIC;
-    ap_continue : IN STD_LOGIC;
-    ap_idle : OUT STD_LOGIC;
-    ap_ready : OUT STD_LOGIC;
-    start_out : OUT STD_LOGIC;
-    start_write : OUT STD_LOGIC;
-    width : IN STD_LOGIC_VECTOR (31 downto 0);
-    height : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt1 : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt2 : IN STD_LOGIC_VECTOR (31 downto 0);
-    width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    width_out_full_n : IN STD_LOGIC;
-    width_out_write : OUT STD_LOGIC;
-    width_out1_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    width_out1_full_n : IN STD_LOGIC;
-    width_out1_write : OUT STD_LOGIC;
-    height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    height_out_full_n : IN STD_LOGIC;
-    height_out_write : OUT STD_LOGIC;
-    height_out2_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    height_out2_full_n : IN STD_LOGIC;
-    height_out2_write : OUT STD_LOGIC;
-    filt1_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    filt1_out_full_n : IN STD_LOGIC;
-    filt1_out_write : OUT STD_LOGIC;
-    filt1_out3_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    filt1_out3_full_n : IN STD_LOGIC;
-    filt1_out3_write : OUT STD_LOGIC;
-    filt2_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    filt2_out_full_n : IN STD_LOGIC;
-    filt2_out_write : OUT STD_LOGIC;
-    filt2_out4_din : OUT STD_LOGIC_VECTOR (31 downto 0);
-    filt2_out4_full_n : IN STD_LOGIC;
-    filt2_out4_write : OUT STD_LOGIC );
-end;
-
-
-architecture behav of filter11x11_strm_ent is 
-    constant ap_const_logic_1 : STD_LOGIC := '1';
-    constant ap_const_logic_0 : STD_LOGIC := '0';
-    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
-    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
-    constant ap_const_boolean_1 : BOOLEAN := true;
-
-    signal real_start : STD_LOGIC;
-    signal start_once_reg : STD_LOGIC := '0';
-    signal ap_done_reg : STD_LOGIC := '0';
-    signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
-    attribute fsm_encoding : string;
-    attribute fsm_encoding of ap_CS_fsm : signal is "none";
-    signal ap_CS_fsm_state1 : STD_LOGIC;
-    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
-    signal internal_ap_ready : STD_LOGIC;
-    signal width_out_blk_n : STD_LOGIC;
-    signal width_out1_blk_n : STD_LOGIC;
-    signal height_out_blk_n : STD_LOGIC;
-    signal height_out2_blk_n : STD_LOGIC;
-    signal filt1_out_blk_n : STD_LOGIC;
-    signal filt1_out3_blk_n : STD_LOGIC;
-    signal filt2_out_blk_n : STD_LOGIC;
-    signal filt2_out4_blk_n : STD_LOGIC;
-    signal ap_block_state1 : BOOLEAN;
-    signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
-
-
-begin
-
-
-
-
-    ap_CS_fsm_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_CS_fsm <= ap_ST_fsm_state1;
-            else
-                ap_CS_fsm <= ap_NS_fsm;
-            end if;
-        end if;
-    end process;
-
-
-    ap_done_reg_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                ap_done_reg <= ap_const_logic_0;
-            else
-                if ((ap_continue = ap_const_logic_1)) then 
-                    ap_done_reg <= ap_const_logic_0;
-                elsif ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-                    ap_done_reg <= ap_const_logic_1;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    start_once_reg_assign_proc : process(ap_clk)
-    begin
-        if (ap_clk'event and ap_clk =  '1') then
-            if (ap_rst = '1') then
-                start_once_reg <= ap_const_logic_0;
-            else
-                if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then 
-                    start_once_reg <= ap_const_logic_1;
-                elsif ((internal_ap_ready = ap_const_logic_1)) then 
-                    start_once_reg <= ap_const_logic_0;
-                end if; 
-            end if;
-        end if;
-    end process;
-
-
-    ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        case ap_CS_fsm is
-            when ap_ST_fsm_state1 => 
-                ap_NS_fsm <= ap_ST_fsm_state1;
-            when others =>  
-                ap_NS_fsm <= "X";
-        end case;
-    end process;
-    ap_CS_fsm_state1 <= ap_CS_fsm(0);
-
-    ap_block_state1_assign_proc : process(real_start, ap_done_reg, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-                ap_block_state1 <= ((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
-    end process;
-
-
-    ap_done_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            ap_done <= ap_const_logic_1;
-        else 
-            ap_done <= ap_done_reg;
-        end if; 
-    end process;
-
-
-    ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
-    begin
-        if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            ap_idle <= ap_const_logic_1;
-        else 
-            ap_idle <= ap_const_logic_0;
-        end if; 
-    end process;
-
-    ap_ready <= internal_ap_ready;
-
-    filt1_out3_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, filt1_out3_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_out3_blk_n <= filt1_out3_full_n;
-        else 
-            filt1_out3_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    filt1_out3_din <= filt1;
-
-    filt1_out3_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_out3_write <= ap_const_logic_1;
-        else 
-            filt1_out3_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    filt1_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, filt1_out_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_out_blk_n <= filt1_out_full_n;
-        else 
-            filt1_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    filt1_out_din <= filt1;
-
-    filt1_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt1_out_write <= ap_const_logic_1;
-        else 
-            filt1_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    filt2_out4_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, filt2_out4_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_out4_blk_n <= filt2_out4_full_n;
-        else 
-            filt2_out4_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    filt2_out4_din <= filt2;
-
-    filt2_out4_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_out4_write <= ap_const_logic_1;
-        else 
-            filt2_out4_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    filt2_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, filt2_out_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_out_blk_n <= filt2_out_full_n;
-        else 
-            filt2_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    filt2_out_din <= filt2;
-
-    filt2_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            filt2_out_write <= ap_const_logic_1;
-        else 
-            filt2_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    height_out2_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, height_out2_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_out2_blk_n <= height_out2_full_n;
-        else 
-            height_out2_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    height_out2_din <= height;
-
-    height_out2_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_out2_write <= ap_const_logic_1;
-        else 
-            height_out2_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    height_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, height_out_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_out_blk_n <= height_out_full_n;
-        else 
-            height_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    height_out_din <= height;
-
-    height_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            height_out_write <= ap_const_logic_1;
-        else 
-            height_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    internal_ap_ready_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            internal_ap_ready <= ap_const_logic_1;
-        else 
-            internal_ap_ready <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
-    begin
-        if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then 
-            real_start <= ap_const_logic_0;
-        else 
-            real_start <= ap_start;
-        end if; 
-    end process;
-
-    start_out <= real_start;
-
-    start_write_assign_proc : process(real_start, start_once_reg)
-    begin
-        if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then 
-            start_write <= ap_const_logic_1;
-        else 
-            start_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    width_out1_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out1_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_out1_blk_n <= width_out1_full_n;
-        else 
-            width_out1_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    width_out1_din <= width;
-
-    width_out1_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_out1_write <= ap_const_logic_1;
-        else 
-            width_out1_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-
-    width_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n)
-    begin
-        if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_out_blk_n <= width_out_full_n;
-        else 
-            width_out_blk_n <= ap_const_logic_1;
-        end if; 
-    end process;
-
-    width_out_din <= width;
-
-    width_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, width_out_full_n, width_out1_full_n, height_out_full_n, height_out2_full_n, filt1_out_full_n, filt1_out3_full_n, filt2_out_full_n, filt2_out4_full_n)
-    begin
-        if ((not(((filt2_out4_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (filt2_out_full_n = ap_const_logic_0) or (filt1_out3_full_n = ap_const_logic_0) or (filt1_out_full_n = ap_const_logic_0) or (height_out2_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (width_out1_full_n = ap_const_logic_0) or (width_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
-            width_out_write <= ap_const_logic_1;
-        else 
-            width_out_write <= ap_const_logic_0;
-        end if; 
-    end process;
-
-end behav;

src/testbench/dut_packaging/ipshared/22b5/src/globals.vhd

@@ -1,36 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.math_real.all;
-
-package myPackage is
-    
-    type register_file is array(integer range <>) of std_logic_vector(31 downto 0);
-    
-    constant moduleCount : integer := 4;
-    constant moduleIds : register_file(0 to moduleCount-1) :=(
-        0 => x"2cb31e7c", --dummyBig
-        1 => x"f218e0a2", --dummy
-        2 => x"9323eb24", --f11
-        3 => x"4cd2e19c"  --conv2d_5x5
-    );
-    
-end myPackage;
-
-package body myPackage is
-
-end myPackage;
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity globals is
---Port ( );
-end globals;
-
-architecture Behavioral of globals is
-
-begin
-
-
-end Behavioral;

src/testbench/dut_packaging/ipshared/22b5/src/kernel_5x5.vhd

@@ -1,31 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-use work.myPackage.ALL;
-
-entity kernel_NxN is
-    Generic(
-        N: integer := 5
-    );
-    Port (
-        kernelValues: in register_file(0 to N*N-1);
-        inputValues: in register_file(0 to N*N-1);
-        outputValue: out std_logic_vector(31 downto 0)
-    );
-end kernel_NxN;
-
-architecture Behavioral of kernel_NxN is
-
-begin
-    calc : process(kernelValues, inputValues)
-        variable sum : integer := 0;
-    begin
-        sum := 0;
-        for i in integer range 0 to N*N-1 loop
-            sum := sum + to_integer(signed(kernelValues(i)(17 downto 0))) * to_integer(signed(inputValues(i)(24 downto 0)));
-        end loop;
-        outputValue <= std_logic_vector(to_signed(sum, outputValue'length));
-    end process;
-
-end Behavioral;

src/testbench/dut_packaging/ipshared/22b5/src/multiplex.vhd

@@ -1,296 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 03.06.2019 18:42:50
--- Design Name: 
--- Module Name: multiplex - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_arith.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.myPackage.ALL;
-
-entity multiplex is
-    generic(
-        busWidth : integer:=32
-        );
-    Port ( clk : in STD_LOGIC;
-           start : in STD_LOGIC;
-           ready: out std_logic;
-           rst : in STD_LOGIC;
-           done : out STD_LOGIC;
-           idle : out STD_LOGIC;
-           
-           moduleId : in STD_LOGIC_VECTOR (31 downto 0);
-           
-           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           srcValid : in std_logic;
-           srcReady : out std_logic;
-           
-           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           dstValid : out std_logic;
-           dstReady : in std_logic
-    );
-end multiplex;
-
-architecture Behavioral of multiplex is
-
-component dummyModule is
-    generic(
-        busWidth : integer:=32;
-        regDepth : integer:=4);
-    Port ( clk : in STD_LOGIC;
-           rst_n : in STD_LOGIC;
-           start : in STD_LOGIC;
-           ready: out std_logic;
-           idle : out std_logic;
-           done : out std_logic;
-           
-           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           srcValid : in std_logic;
-           srcReady : out std_logic;
-           
-           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           dstValid : out std_logic;
-           dstReady : in std_logic);
-end component;
-
-component filter11x11_strm is
-port (
-    width : IN STD_LOGIC_VECTOR (31 downto 0);
-    height : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt1 : IN STD_LOGIC_VECTOR (31 downto 0);
-    filt2 : IN STD_LOGIC_VECTOR (31 downto 0);
-    src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
-    dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
-    ap_clk : IN STD_LOGIC;
-    ap_rst_n : IN STD_LOGIC;
-    ap_start : IN STD_LOGIC;
-    src_V_TVALID : IN STD_LOGIC;
-    src_V_TREADY : OUT STD_LOGIC;
-    dst_V_TVALID : OUT STD_LOGIC;
-    dst_V_TREADY : IN STD_LOGIC;
-    ap_done : OUT STD_LOGIC;
-    ap_ready : OUT STD_LOGIC;
-    ap_idle : OUT STD_LOGIC);
-end component;
-
-component conv2d_5x5_224p is
-    generic(
-        busWidth : integer := 32;
-        kernelSize : integer := 5;
-        imageWidth : integer := 224 + 4);
-    Port ( clk : in STD_LOGIC;
-           rst_n : in std_logic;
-           start : in STD_LOGIC;
-           ready: out std_logic;
-           idle : out std_logic := '0';
-           done : out std_logic := '0';
-           
-           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           srcValid : in std_logic;
-           srcReady : out std_logic;
-           
-           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           dstValid : out std_logic;
-           dstReady : in std_logic);
-end component;
-
-component ram is
-    generic(
-        busWidth : integer:=busWidth;
-        addrWidth: integer);
-    port(
-        clk : in std_logic;
-        wrEn : in std_logic;
-        wrAddr : in std_logic_vector(addrWidth-1 downto 0);
-        rdAddr : in std_logic_vector(addrWidth-1 downto 0);
-        wrData : in std_logic_vector(busWidth-1 downto 0);
-        rdData : out std_logic_vector(busWidth-1 downto 0)
-    );
-end component;
-
-constant ramAddrWidth : integer := 4;
-type muxBitVector is array(0 to moduleCount-1) of std_logic;
-type muxDataVector is array(0 to moduleCount-1) of std_logic_vector(busWidth-1 downto 0);
-
-type configRam_t is array(integer range <>) of std_logic_vector(busWidth-1 downto 0);
-
-signal imgWidth : std_logic_vector(busWidth-1 downto 0) := std_logic_vector(conv_unsigned(224, 32));
-signal imgHeight : std_logic_vector(busWidth-1 downto 0) := std_logic_vector(conv_unsigned(224, 32));
-
-signal h_coeff : configRam_t(0 to 4);
-signal v_coeff : configRam_t(0 to 4);
-
-signal h_coeff_rdAddr : std_logic_vector(2 downto 0);
-signal h_coeff_rdEn : std_logic;
-signal v_coeff_rdAddr : std_logic_vector(2 downto 0);
-signal v_coeff_rdEn : std_logic;
-
-signal ram_wrEn   : std_logic;
-signal ram_wrAddr : std_logic_vector(ramAddrWidth-1 downto 0);
-signal ram_wrData : std_logic_vector(busWidth-1 downto 0);
-signal ram_rdAddr : std_logic_vector(ramAddrWidth-1 downto 0);
-signal ram_rdData : std_logic_vector(busWidth-1 downto 0);
-
-signal muxSrcData : std_logic_vector(busWidth-1 downto 0);
-signal muxSrcValid : std_logic;
-signal muxSrcReady : muxBitVector := (others => '1');
-
-signal muxDstData : muxDataVector;
-signal muxDstValid : muxBitVector := (others => '0');
-signal muxDstReady : std_logic;
-
-signal muxReady : muxBitVector := (others => '1');
-signal muxIdle : muxBitVector := (others => '1');
-signal muxDone : muxBitVector := (others => '1');
-
-signal muxStart : muxBitVector := (others => '0');
-
-
-
-begin
-    dummyBig : dummyModule 
-    generic map (
-        regDepth => 1024
-    ) port map (
-        clk     => clk,
-        rst_n   => rst,
-        
-        srcData => muxSrcData,
-        srcValid=> muxSrcValid,
-        srcReady=> muxSrcReady(0),
-        
-        dstData => muxDstData(0),
-        dstValid => muxDstValid(0),
-        dstReady => muxDstReady,
-        
-        start   => muxStart(0),
-        ready   => muxReady(0),
-        idle    => muxIdle(0),
-        done    => muxDone(0)
-    );
-    
-    dummy : dummyModule 
-    generic map (
-        regDepth => 4
-    ) port map (
-        clk     => clk,
-        rst_n   => rst,
-        
-        srcData => muxSrcData,
-        srcValid=> muxSrcValid,
-        srcReady=> muxSrcReady(1),
-        
-        dstData => muxDstData(1),
-        dstValid => muxDstValid(1),
-        dstReady => muxDstReady,
-        
-        start   => muxStart(1),
-        ready   => muxReady(1),
-        idle    => muxIdle(1),
-        done    => muxDone(1)
-    );
-    f11 : filter11x11_strm port map (
-        ap_clk => clk,
-        ap_rst_n => rst,
-        ap_start => muxStart(2),
-        ap_done => muxDone(2),
-        ap_ready => muxReady(2),
-        ap_idle => muxIdle(2),
-        width => imgWidth,
-        height => imgHeight,
-        
-        src_V_TDATA => muxSrcData,
-        src_V_TVALID => muxSrcValid,
-        src_V_TREADY => muxSrcReady(2),
-        
-        dst_V_TDATA => muxDstData(2),
-        dst_V_TVALID => muxDstValid(2),
-        dst_V_TREADY => muxDstReady,
-        
-        filt1 => x"00000001",
-        filt2 => x"00000001"
-        
-    );
-    
-    conv2d_5x5 : conv2d_5x5_224p port map (
-        clk => clk,
-        rst_n => rst,
-
-        srcData => muxSrcData,
-        srcValid=> muxSrcValid,
-        srcReady=> muxSrcReady(3),
-        
-        dstData => muxDstData(3),
-        dstValid => muxDstValid(3),
-        dstReady => muxDstReady,
-        
-        start   => muxStart(3),
-        ready   => muxReady(3),
-        idle    => muxIdle(3),
-        done    => muxDone(3)
-    );
-    
-    config_ram : ram generic map(
-        addrWidth => ramAddrWidth
-    ) port map(
-        clk => clk,
-        wrEn => ram_wrEn,
-        wrAddr => ram_wrAddr,
-        rdAddr => ram_rdAddr,
-        wrData => ram_wrData,
-        rdData => ram_rdData
-    );
-    
-    readConfig : process(h_coeff_rdEn)
-        variable rdAddr : std_logic_vector(ramAddrWidth-1 downto 0);
-    begin
-        if h_coeff_rdEn = '1' then
-        
-        elsif v_coeff_rdEn = '1' then
-        
-        end if;
-    end process;
-    
-    switching : process(moduleId, muxSrcReady, muxReady, muxDstData, muxDstValid, muxDone, muxIdle, start)
-        variable i : integer range 0 to moduleCount-1;
-    begin
-        i := 0;
-        for k in 0 to moduleCount-1 loop
-            if moduleIds(k) = moduleId then
-                i := k;
-            end if;
-        end loop;
-        
-        ready <= muxReady(i);
-        dstData <= muxDstData(i);
-        done <= muxDone(i);
-        idle <= muxIdle(i);
-        dstValid <= muxDstValid(i);
-        srcReady <= muxSrcReady(i);
-        
-        muxStart <= (others => '0');
-        muxStart(i) <= start;
-    end process;
-    
-    muxSrcValid <= srcValid;
-    muxSrcData <= srcData;
-    muxDstReady <= dstReady;
-    
-end Behavioral;

src/testbench/dut_packaging/ipshared/22b5/src/packaging.vhd

@@ -1,388 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 03.06.2019 20:10:59
--- Design Name: 
--- Module Name: packaging - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_arith.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.myPackage.ALL;
-
-entity packaging is
-    generic(
-        busWidth : integer:=32);
-    Port ( clk : in STD_LOGIC;
-           rst : in STD_LOGIC;
-           
-           inputStream : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           inpRdEn : out std_logic;
-           inputEmpty : in std_logic;
-           
-           outData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           outWrEn : out std_logic;
-           outputFull : in std_logic;
-           
-           errorCode : out STD_LOGIC_VECTOR(3 DOWNTO 0);
-           stateOut : out STD_LOGIC_VECTOR(3 downto 0));
-end packaging;
-
-architecture Behavioral of packaging is
-
-    constant PREAMBLE : std_logic_vector(31 downto 0) := x"E1E4C312";
-    type state_t is (
-        waitPreamble, 
-        checkPreamble,
-        waitDatasetId,
-        getDatasetId,
-        waitModuleId,
-        checkModuleId, 
-        writeHeader,
-        waitProcessing,
-        waitChecksum,
-        readChecksum,
-        writeChecksum);
-    
-
-    component multiplex is
-        generic(
-            busWidth : integer:=busWidth);
-        Port (
-           clk : in STD_LOGIC;
-           start : in STD_LOGIC;
-           ready: out std_logic;
-           rst : in STD_LOGIC;
-           done : out STD_LOGIC;
-           idle : out STD_LOGIC;
-           
-           moduleId : in STD_LOGIC_VECTOR (31 downto 0);
-           
-           srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           srcValid : in std_logic;
-           srcReady : out std_logic;
-           
-           dstData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           dstValid : out std_logic;
-           dstReady : in std_logic);
-    end component;
-    
-    component checksum is
-        Port ( clk : in STD_LOGIC;
-           reset : in STD_LOGIC;
-           enable : in STD_LOGIC;
-           dataIn : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
-           output : out STD_LOGIC_VECTOR (busWidth-1 downto 0));
-    end component;
-    
-    signal state : state_t;
-    signal moduleId : STD_LOGIC_VECTOR (31 downto 0);
-    signal datasetId : STD_LOGIC_VECTOR (31 downto 0);
-    signal inputReadReady : std_logic;
-    signal inputReadEnable : std_logic;
-    
-    signal outputWriteReady : std_logic;
-    signal outputStream_s : STD_LOGIC_VECTOR (busWidth-1 downto 0);
-    
-    signal outputWriteEnable : std_logic;
-    signal outputStream : STD_LOGIC_VECTOR (busWidth-1 downto 0);
-    signal errorCode_s : std_logic_vector(3 downto 0);
-    
-    signal outHeaderCounter : integer range 0 to 3;
-    
-    signal muxSrcData : STD_LOGIC_VECTOR (busWidth-1 downto 0);
-    signal muxSrcValid : std_logic;
-    signal muxSrcReady : std_logic;
-    
-    signal muxDstData : STD_LOGIC_VECTOR (busWidth-1 downto 0);
-    signal muxDstValid : std_logic;
-    signal muxDstReady : std_logic;
-    
-    signal muxStart  : std_logic;
-    signal muxReady  : std_logic;
-    signal muxDone   : std_logic;
-    signal muxIdle   : std_logic;
-    
-    signal muxControlsFIFO : std_logic;
-    
-    signal csEnable : std_logic;
-    signal csReset : std_logic;
-    signal csOutReset : std_logic;
-    signal csSum : STD_LOGIC_VECTOR (busWidth-1 downto 0);
-    
-    signal csOutSum : STD_LOGIC_VECTOR (busWidth-1 downto 0);
-    
-begin
-
-    mux1 : multiplex port map (
-        clk => clk,
-        rst => rst,
-        start => muxStart,
-        ready  => muxReady,
-        done => muxDone,
-        idle => muxIdle,
-        
-        moduleId => moduleId,
-        
-        srcData     => muxSrcData,
-        srcValid    => muxSrcValid,
-        srcReady    => muxSrcReady,
-        
-        dstData     => muxDstData,
-        dstValid    => muxDstValid,
-        dstReady    => muxDstReady
-        
-    );
-    checksum1 : checksum port map (
-        clk => clk,
-        reset => csReset,
-        enable => csEnable,
-        dataIn => inputStream,
-        output => csSum
-    );
-    checksum2 : checksum port map (
-        clk => clk,
-        reset => csOutReset,
-        enable => outputWriteEnable,
-        dataIn => outputStream,
-        output => csOutSum
-    );
-
-    fsm : process(rst, clk)
-        variable validModuleId : std_logic := '0';
-    begin
-        if(rst = '0') then
-            state <= waitPreamble;
-            inputReadReady <= '0';
-            csReset <= '0';
-            csOutReset <= '0';
-            outHeaderCounter <= 3;
-            muxStart <= '0';
-            muxControlsFIFO <= '0';
-            
-            errorCode_s <= x"0";
-            
-            outputWriteReady <= '0';
-            outputStream_s <= (others=>'U');
-        elsif(rising_edge(clk)) then
-            csReset <= '1';
-            csOutReset <= '1';
-            errorCode_s <= x"0";
-            muxStart <= '0';
-            muxControlsFIFO <= '0';
-            inputReadReady <= '0';
-            
-            outputWriteReady <= '0';
-            outHeaderCounter <= 0;
-            
-            outputStream_s <= (others=>'U');
-        
-            case state is
-                -- wait for header
-                when waitPreamble =>
-                    csReset <= '0';
-                    inputReadReady <= '1';
-                    if inputReadEnable = '0' then
-                        state <= waitPreamble;
-                    else
-                        state <= checkPreamble;
-                    end if;
-                    
-                -- is preamble correct?
-                when checkPreamble =>
-                    inputReadReady <= '1';
-                    if(inputStream = PREAMBLE and inputReadEnable = '1') then
-                        state <= getDatasetId;
-                    elsif inputStream = PREAMBLE then
-                        state <= waitDatasetId;
-                    elsif inputReadEnable = '1' then
-                        state <= checkPreamble;
-                        errorCode_s <= x"1";
-                    else
-                        state <= waitPreamble;
-                        errorCode_s <= x"1";
-                    end if;
-                when waitDatasetId =>
-                    inputReadReady <= '1';
-                    if inputReadEnable = '0' then
-                        errorCode_s <= x"F";
-                        state <= waitDatasetId;
-                    else
-                        state <= getDatasetId;
-                    end if;
-                    
-                when getDatasetId =>
-                    datasetId <= inputStream;
-                    if inputReadEnable = '0' then
-                        state <= waitModuleId;
-                        inputReadReady <= '1';
-                    else
-                        state <= checkModuleId;
-                    end if;
-                
-                when waitModuleId =>
-                    
-                    if inputReadEnable = '0' then
-                        errorCode_s <= x"E";
-                        state <= waitModuleId;
-                        inputReadReady <= '1';
-                    else
-                        state <= checkModuleId;
-                    end if;
-                -- is moduleId known?
-                when checkModuleId =>
-                    
-                    validModuleId := '0';
-                    
-                    for i in integer range 0 to moduleCount-1 loop
-                        if inputStream = moduleIds(i) then
-                            validModuleId := '1';
-                        end if;
-                    end loop;
-                    
-                    if validModuleId = '0' then
-                        state <= waitPreamble;
-                        errorCode_s <= x"2";
-                    else
-                        csOutReset <= '0';
-                        moduleId <= inputStream;
-                        if outputWriteEnable = '1' then
-                            state <= writeHeader;
-                            csOutReset <= '0';
-                        else
-                            outputWriteReady <= '1';
-                            outputStream_s <= PREAMBLE;
-                            errorCode_s <= x"D";
-                        end if;
-                    end if;
-                    
-                -- wait for data
-                when writeHeader =>
-                    case outHeaderCounter is
-                        when 0 =>  outputStream_s <= datasetId;
-                        when others => outputStream_s <= moduleId;
-                    end case;
-                    
-                    if outHeaderCounter > 1 then
-                        state <= waitProcessing;
-                        muxStart <= '1';
-                        muxControlsFIFO <= '1';
-                    elsif outputWriteEnable = '0' then
-                        state <= writeHeader;
-                        errorCode_s <= x"C";
-                        outHeaderCounter <= outHeaderCounter;
-                        outputWriteReady <= '1';
-                    elsif outHeaderCounter < 1 then
-                        outHeaderCounter <= outHeaderCounter + 1;
-                        state <= writeHeader;
-                        outputWriteReady <= '1';
-                        outputStream_s <= moduleId;
-                    else
-                        state <= waitProcessing;
-                        muxStart <= '1';
-                        muxControlsFIFO <= '1';
-                    end if;
-
-                when waitProcessing =>
-                    if(muxDone = '0') then
-                        state <= waitProcessing;
-                        muxControlsFIFO <= '1';
-                        errorCode_s <= x"B";
-                        muxStart <= '1';
-                    else
-                        state <= waitChecksum;
-                        inputReadReady <= '1';
-                    end if;
-                
-                when waitChecksum =>
-                    if inputReadEnable = '0' then
-                        errorCode_s <= x"A";
-                        state <= waitChecksum;
-                        inputReadReady <= '1';
-                    else
-                        state <= readChecksum;
-                    end if;
-                when readChecksum =>
-                    state <= writeChecksum;
-                    
-                when writeChecksum =>
-                    if outputWriteEnable = '1' then
-                        state <= waitPreamble;
-                    else
-                        state <= writeChecksum;
-                        outputWriteReady <= '1';
-                    end if;
-                    
-                    if(unsigned(csSum) = 0) then
-                        outputStream_s <= 0 - unsigned(csOutSum);
-                    else
-                        errorCode_s <= x"3";
-                        outputStream_s <= 1 - unsigned(csOutSum);
-                    end if;
-                
-                when others =>
-                    state <= waitPreamble;
-                    inputReadReady <= '0';
-            end case;
-            
-            if signed(errorCode_s) > 0 then
-                outputWriteReady <= '1';
-                outputStream_s <= x"E330300" & errorCode_s;
-            end if;
-            muxSrcValid <= inputReadEnable;
-            
-        end if;
-    end process;
-    
-    muxCtrl : process(muxControlsFIFO, outputWriteReady, inputReadReady, outputStream_s, muxDstValid, muxSrcReady, muxDstData, inputStream, outputFull, inputEmpty)
-    
-    begin
-        if muxControlsFIFO = '0' then
-            outputWriteEnable   <= outputWriteReady and not outputFull;
-            inputReadEnable     <= inputReadReady and not inputEmpty;
-            outputStream        <= outputStream_s;
-            
-            muxSrcData <= (others => 'U');
-            muxDstReady <= '0';
-        else
-            outputWriteEnable   <= muxDstValid and not outputFull;
-            inputReadEnable     <= muxSrcReady and not inputEmpty;
-            outputStream        <= muxDstData;
-            
-            muxSrcData <= inputStream;
-            muxDstReady <= not outputFull;
-        end if;
-        
-    end process;
-    
-    sumInput : process(rst, clk) begin
-        if rst = '0' then
-            csEnable <= '0';
-        elsif rising_edge(clk) then
-            csEnable <= inputReadEnable;
-        end if;
-    end process;
-    
-    errorCode <= errorCode_s;
-    stateOut <= std_logic_vector(conv_unsigned(state_t'POS(state), 4));
-    
-    outWrEn <= outputWriteEnable;
-    inpRdEn <= inputReadEnable;
-    outData <= outputStream;
-    
-end Behavioral;

src/testbench/dut_packaging/ipshared/22b5/src/ram.vhd

@@ -1,37 +0,0 @@
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-
-entity ram is
-    generic(
-        busWidth : integer:=32;
-        addrWidth: integer := 8);
-    port(
-        clk : in std_logic;
-        wrEn : in std_logic;
-        wrAddr : in std_logic_vector(addrWidth-1 downto 0);
-        rdAddr : in std_logic_vector(addrWidth-1 downto 0);
-        wrData : in std_logic_vector(busWidth-1 downto 0);
-        rdData : out std_logic_vector(busWidth-1 downto 0)
-    );
-end ram;
-
-architecture Behavioral of ram is
-    type ram_t is array(0 to 2**addrWidth) of std_logic_vector(busWidth-1 downto 0);
-    signal memory : ram_t;
-begin
-    process(clk)
-    
-    begin
-        if rising_edge(clk) then
-            if wrEn = '1' then
-                memory(to_integer(unsigned(wrAddr))) <= wrData;
-            end if;
-            rdData <= memory(to_integer(unsigned(rdAddr)));
-        end if;
-    end process;
-
-end Behavioral;

src/testbench/dut_packaging/ipshared/22b5/src/shiftIn.vhd

@@ -1,75 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 06/03/2019 01:56:01 PM
--- Design Name: 
--- Module Name: shiftOut - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity shiftIn is
-    generic(
-        busWidth : integer := 32;
-        regDepth : integer := 4;
-        maxCount : integer := 4);
-    Port ( clk : in STD_LOGIC;
-               ce : in std_logic;
-               sync_reset : in STD_LOGIC;
-               dataIn : in std_logic_vector(busWidth-1 downto 0);
-               dataOut : out register_file(0 to regDepth-1);
-               finished : out STD_LOGIC;
-               dataIndex : out integer range 0 to maxCount);
-end shiftIn;
-
-architecture Behavioral of shiftIn is
-    signal dataIndex_s : integer range 0 to maxCount := 0;
-    signal dataOut_s : register_file(0 to regDepth-1);
-begin
-
-p_s2p : process(clk, sync_reset, dataIndex_s)
-begin
-    if(sync_reset = '0') then
-        dataIndex_s <= 0;
-        finished <= '0';
-        dataOut_s <= (others => (others => '0'));
-    elsif(rising_edge(clk)) then
-        if(ce = '1') then
-            dataOut_s(0) <= dataIn;
-            for i in integer range 1 to regDepth - 1 loop
-                dataOut_s(i) <= dataOut_s(i-1);
-            end loop;
-            
-            dataIndex_s <= dataIndex_s + 1;
-        else
-            dataIndex_s <= dataIndex_s;
-            dataOut_s <= dataOut_s;
-        end if;
-    end if;
-    if dataIndex_s < regDepth-1 then
-        finished <= '0';
-    elsif dataIndex_s < regDepth and ce = '0' then
-        finished <= '0';
-    else
-        finished <= '1';
-    end if;
-end process;
-
-dataOut <= dataOut_s;
-dataIndex <= dataIndex_s;
-end Behavioral;

src/testbench/dut_packaging/ipshared/22b5/src/start_for_Block_proc_U0.vhd

@@ -1,140 +0,0 @@
--- ==============================================================
--- File generated on Wed Jun 26 16:53:30 CEST 2019
--- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
--- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
--- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--- ==============================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity start_for_Block_proc_U0_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 1;
-        DEPTH : integer := 2);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-end start_for_Block_proc_U0_shiftReg;
-
-architecture rtl of start_for_Block_proc_U0_shiftReg is
---constant DEPTH_WIDTH: integer := 16;
-type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-signal SRL_SIG : SRL_ARRAY;
-
-begin
-p_shift: process (clk)
-begin
-    if (clk'event and clk = '1') then
-        if (ce = '1') then
-            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
-        end if;
-    end if;
-end process;
-
-q <= SRL_SIG(conv_integer(a));
-
-end rtl;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-entity start_for_Block_proc_U0 is 
-    generic (
-        MEM_STYLE  : string := "shiftreg"; 
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 1;
-        DEPTH : integer := 2);
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_empty_n : OUT STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_read : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
-end entity;
-
-architecture rtl of start_for_Block_proc_U0 is
-
-    component start_for_Block_proc_U0_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 1;
-        DEPTH : integer := 2);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-    end component;
-
-    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
-    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-    signal shiftReg_ce : STD_LOGIC;
-    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
-    signal internal_empty_n : STD_LOGIC := '0';
-    signal internal_full_n  : STD_LOGIC := '1';
-
-begin
-    if_empty_n <= internal_empty_n;
-    if_full_n <= internal_full_n;
-    shiftReg_data <= if_din;
-    if_dout <= shiftReg_q;
-
-    process (clk)
-    begin
-        if clk'event and clk = '1' then
-            if reset = '1' then
-                mOutPtr <= (others => '1');
-                internal_empty_n <= '0';
-                internal_full_n <= '1';
-            else
-                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
-                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
-                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2);
-                    if (mOutPtr = conv_std_logic_vector(0, 2)) then 
-                        internal_empty_n <= '0';
-                    end if;
-                    internal_full_n <= '1';
-                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
-                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
-                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2);
-                    internal_empty_n <= '1';
-                    if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then 
-                        internal_full_n <= '0';
-                    end if;
-                end if;
-            end if;
-        end if;
-    end process;
-
-    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
-    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
-
-    U_start_for_Block_proc_U0_shiftReg : start_for_Block_proc_U0_shiftReg
-    generic map (
-        DATA_WIDTH => DATA_WIDTH,
-        ADDR_WIDTH => ADDR_WIDTH,
-        DEPTH => DEPTH)
-    port map (
-        clk => clk,
-        data => shiftReg_data,
-        ce => shiftReg_ce,
-        a => shiftReg_addr,
-        q => shiftReg_q);
-
-end rtl;
-

src/testbench/dut_packaging/ipshared/22b5/src/start_for_Loop_Border_proc_U0.vhd

@@ -1,140 +0,0 @@
--- ==============================================================
--- File generated on Wed Jun 26 16:53:30 CEST 2019
--- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
--- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
--- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--- ==============================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity start_for_Loop_Border_proc_U0_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-end start_for_Loop_Border_proc_U0_shiftReg;
-
-architecture rtl of start_for_Loop_Border_proc_U0_shiftReg is
---constant DEPTH_WIDTH: integer := 16;
-type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-signal SRL_SIG : SRL_ARRAY;
-
-begin
-p_shift: process (clk)
-begin
-    if (clk'event and clk = '1') then
-        if (ce = '1') then
-            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
-        end if;
-    end if;
-end process;
-
-q <= SRL_SIG(conv_integer(a));
-
-end rtl;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-entity start_for_Loop_Border_proc_U0 is 
-    generic (
-        MEM_STYLE  : string := "shiftreg"; 
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_empty_n : OUT STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_read : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
-end entity;
-
-architecture rtl of start_for_Loop_Border_proc_U0 is
-
-    component start_for_Loop_Border_proc_U0_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-    end component;
-
-    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
-    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-    signal shiftReg_ce : STD_LOGIC;
-    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
-    signal internal_empty_n : STD_LOGIC := '0';
-    signal internal_full_n  : STD_LOGIC := '1';
-
-begin
-    if_empty_n <= internal_empty_n;
-    if_full_n <= internal_full_n;
-    shiftReg_data <= if_din;
-    if_dout <= shiftReg_q;
-
-    process (clk)
-    begin
-        if clk'event and clk = '1' then
-            if reset = '1' then
-                mOutPtr <= (others => '1');
-                internal_empty_n <= '0';
-                internal_full_n <= '1';
-            else
-                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
-                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
-                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
-                    if (mOutPtr = conv_std_logic_vector(0, 3)) then 
-                        internal_empty_n <= '0';
-                    end if;
-                    internal_full_n <= '1';
-                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
-                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
-                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
-                    internal_empty_n <= '1';
-                    if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then 
-                        internal_full_n <= '0';
-                    end if;
-                end if;
-            end if;
-        end if;
-    end process;
-
-    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
-    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
-
-    U_start_for_Loop_Border_proc_U0_shiftReg : start_for_Loop_Border_proc_U0_shiftReg
-    generic map (
-        DATA_WIDTH => DATA_WIDTH,
-        ADDR_WIDTH => ADDR_WIDTH,
-        DEPTH => DEPTH)
-    port map (
-        clk => clk,
-        data => shiftReg_data,
-        ce => shiftReg_ce,
-        a => shiftReg_addr,
-        q => shiftReg_q);
-
-end rtl;
-

src/testbench/dut_packaging/ipshared/22b5/src/start_for_Loop_VConvH_proc_U0.vhd

@@ -1,140 +0,0 @@
--- ==============================================================
--- File generated on Wed Jun 26 16:53:30 CEST 2019
--- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
--- SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
--- IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
--- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--- ==============================================================
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity start_for_Loop_VConvH_proc_U0_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-end start_for_Loop_VConvH_proc_U0_shiftReg;
-
-architecture rtl of start_for_Loop_VConvH_proc_U0_shiftReg is
---constant DEPTH_WIDTH: integer := 16;
-type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-signal SRL_SIG : SRL_ARRAY;
-
-begin
-p_shift: process (clk)
-begin
-    if (clk'event and clk = '1') then
-        if (ce = '1') then
-            SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
-        end if;
-    end if;
-end process;
-
-q <= SRL_SIG(conv_integer(a));
-
-end rtl;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-entity start_for_Loop_VConvH_proc_U0 is 
-    generic (
-        MEM_STYLE  : string := "shiftreg"; 
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : IN STD_LOGIC;
-        reset : IN STD_LOGIC;
-        if_empty_n : OUT STD_LOGIC;
-        if_read_ce : IN STD_LOGIC;
-        if_read : IN STD_LOGIC;
-        if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-        if_full_n : OUT STD_LOGIC;
-        if_write_ce : IN STD_LOGIC;
-        if_write : IN STD_LOGIC;
-        if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
-end entity;
-
-architecture rtl of start_for_Loop_VConvH_proc_U0 is
-
-    component start_for_Loop_VConvH_proc_U0_shiftReg is
-    generic (
-        DATA_WIDTH : integer := 1;
-        ADDR_WIDTH : integer := 2;
-        DEPTH : integer := 3);
-    port (
-        clk : in std_logic;
-        data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-        ce : in std_logic;
-        a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-        q : out std_logic_vector(DATA_WIDTH-1 downto 0));
-    end component;
-
-    signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
-    signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
-    signal shiftReg_ce : STD_LOGIC;
-    signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
-    signal internal_empty_n : STD_LOGIC := '0';
-    signal internal_full_n  : STD_LOGIC := '1';
-
-begin
-    if_empty_n <= internal_empty_n;
-    if_full_n <= internal_full_n;
-    shiftReg_data <= if_din;
-    if_dout <= shiftReg_q;
-
-    process (clk)
-    begin
-        if clk'event and clk = '1' then
-            if reset = '1' then
-                mOutPtr <= (others => '1');
-                internal_empty_n <= '0';
-                internal_full_n <= '1';
-            else
-                if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 
-                   ((if_write and if_write_ce) = '0' or internal_full_n = '0') then
-                    mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
-                    if (mOutPtr = conv_std_logic_vector(0, 3)) then 
-                        internal_empty_n <= '0';
-                    end if;
-                    internal_full_n <= '1';
-                elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 
-                   ((if_write and if_write_ce) = '1' and internal_full_n = '1') then
-                    mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
-                    internal_empty_n <= '1';
-                    if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then 
-                        internal_full_n <= '0';
-                    end if;
-                end if;
-            end if;
-        end if;
-    end process;
-
-    shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
-    shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
-
-    U_start_for_Loop_VConvH_proc_U0_shiftReg : start_for_Loop_VConvH_proc_U0_shiftReg
-    generic map (
-        DATA_WIDTH => DATA_WIDTH,
-        ADDR_WIDTH => ADDR_WIDTH,
-        DEPTH => DEPTH)
-    port map (
-        clk => clk,
-        data => shiftReg_data,
-        ce => shiftReg_ce,
-        a => shiftReg_addr,
-        q => shiftReg_q);
-
-end rtl;
-

src/testbench/dut_packaging/sim/dut_packaging.protoinst

@@ -1,9 +0,0 @@
-{
-	"version": "1.0",
-	"modules": {
-		"dut_packaging": {
-			"proto_instances": {
-			}
-		}
-	}
-}

src/testbench/dut_packaging/sim/dut_packaging.vhd

@@ -1,94 +0,0 @@
---Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
---Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
---Date        : Mon Apr 27 15:16:04 2020
---Host        : DESKTOP-L9P0FU6 running 64-bit major release  (build 9200)
---Command     : generate_target dut_packaging.bd
---Design      : dut_packaging
---Purpose     : IP block netlist
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity dut_packaging is
-  port (
-    clk_0 : in STD_LOGIC;
-    errorCode_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
-    fifo_read_0_empty : in STD_LOGIC;
-    fifo_read_0_rd_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
-    fifo_read_0_rd_en : out STD_LOGIC;
-    fifo_write_0_full : in STD_LOGIC;
-    fifo_write_0_wr_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
-    fifo_write_0_wr_en : out STD_LOGIC;
-    rst_0 : in STD_LOGIC;
-    stateOut_0 : out STD_LOGIC_VECTOR ( 3 downto 0 )
-  );
-  attribute CORE_GENERATION_INFO : string;
-  attribute CORE_GENERATION_INFO of dut_packaging : entity is "dut_packaging,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=dut_packaging,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=1,numReposBlks=1,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
-  attribute HW_HANDOFF : string;
-  attribute HW_HANDOFF of dut_packaging : entity is "dut_packaging.hwdef";
-end dut_packaging;
-
-architecture STRUCTURE of dut_packaging is
-  component dut_packaging_packaging_0_0 is
-  port (
-    clk : in STD_LOGIC;
-    rst : in STD_LOGIC;
-    inputStream : in STD_LOGIC_VECTOR ( 31 downto 0 );
-    inpRdEn : out STD_LOGIC;
-    inputEmpty : in STD_LOGIC;
-    outData : out STD_LOGIC_VECTOR ( 31 downto 0 );
-    outWrEn : out STD_LOGIC;
-    outputFull : in STD_LOGIC;
-    errorCode : out STD_LOGIC_VECTOR ( 3 downto 0 );
-    stateOut : out STD_LOGIC_VECTOR ( 3 downto 0 )
-  );
-  end component dut_packaging_packaging_0_0;
-  signal clk_0_1 : STD_LOGIC;
-  signal packaging_0_errorCode : STD_LOGIC_VECTOR ( 3 downto 0 );
-  signal packaging_0_fifo_read_EMPTY : STD_LOGIC;
-  signal packaging_0_fifo_read_RD_DATA : STD_LOGIC_VECTOR ( 31 downto 0 );
-  signal packaging_0_fifo_read_RD_EN : STD_LOGIC;
-  signal packaging_0_fifo_write_FULL : STD_LOGIC;
-  signal packaging_0_fifo_write_WR_DATA : STD_LOGIC_VECTOR ( 31 downto 0 );
-  signal packaging_0_fifo_write_WR_EN : STD_LOGIC;
-  signal packaging_0_stateOut : STD_LOGIC_VECTOR ( 3 downto 0 );
-  signal rst_0_1 : STD_LOGIC;
-  attribute X_INTERFACE_INFO : string;
-  attribute X_INTERFACE_INFO of clk_0 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_0 CLK";
-  attribute X_INTERFACE_PARAMETER : string;
-  attribute X_INTERFACE_PARAMETER of clk_0 : signal is "XIL_INTERFACENAME CLK.CLK_0, ASSOCIATED_RESET rst_0, CLK_DOMAIN dut_packaging_clk_0, FREQ_HZ 100000000, INSERT_VIP 0, PHASE 0.000";
-  attribute X_INTERFACE_INFO of fifo_read_0_empty : signal is "xilinx.com:interface:fifo_read:1.0 fifo_read_0 EMPTY";
-  attribute X_INTERFACE_INFO of fifo_read_0_rd_en : signal is "xilinx.com:interface:fifo_read:1.0 fifo_read_0 RD_EN";
-  attribute X_INTERFACE_INFO of fifo_write_0_full : signal is "xilinx.com:interface:fifo_write:1.0 fifo_write_0 FULL";
-  attribute X_INTERFACE_INFO of fifo_write_0_wr_en : signal is "xilinx.com:interface:fifo_write:1.0 fifo_write_0 WR_EN";
-  attribute X_INTERFACE_INFO of rst_0 : signal is "xilinx.com:signal:reset:1.0 RST.RST_0 RST";
-  attribute X_INTERFACE_PARAMETER of rst_0 : signal is "XIL_INTERFACENAME RST.RST_0, INSERT_VIP 0, POLARITY ACTIVE_LOW";
-  attribute X_INTERFACE_INFO of fifo_read_0_rd_data : signal is "xilinx.com:interface:fifo_read:1.0 fifo_read_0 RD_DATA";
-  attribute X_INTERFACE_INFO of fifo_write_0_wr_data : signal is "xilinx.com:interface:fifo_write:1.0 fifo_write_0 WR_DATA";
-begin
-  clk_0_1 <= clk_0;
-  errorCode_0(3 downto 0) <= packaging_0_errorCode(3 downto 0);
-  fifo_read_0_rd_en <= packaging_0_fifo_read_RD_EN;
-  fifo_write_0_wr_data(31 downto 0) <= packaging_0_fifo_write_WR_DATA(31 downto 0);
-  fifo_write_0_wr_en <= packaging_0_fifo_write_WR_EN;
-  packaging_0_fifo_read_EMPTY <= fifo_read_0_empty;
-  packaging_0_fifo_read_RD_DATA(31 downto 0) <= fifo_read_0_rd_data(31 downto 0);
-  packaging_0_fifo_write_FULL <= fifo_write_0_full;
-  rst_0_1 <= rst_0;
-  stateOut_0(3 downto 0) <= packaging_0_stateOut(3 downto 0);
-packaging_0: component dut_packaging_packaging_0_0
-     port map (
-      clk => clk_0_1,
-      errorCode(3 downto 0) => packaging_0_errorCode(3 downto 0),
-      inpRdEn => packaging_0_fifo_read_RD_EN,
-      inputEmpty => packaging_0_fifo_read_EMPTY,
-      inputStream(31 downto 0) => packaging_0_fifo_read_RD_DATA(31 downto 0),
-      outData(31 downto 0) => packaging_0_fifo_write_WR_DATA(31 downto 0),
-      outWrEn => packaging_0_fifo_write_WR_EN,
-      outputFull => packaging_0_fifo_write_FULL,
-      rst => rst_0_1,
-      stateOut(3 downto 0) => packaging_0_stateOut(3 downto 0)
-    );
-end STRUCTURE;

src/testbench/dut_packaging/synth/dut_packaging.vhd

@@ -1,94 +0,0 @@
---Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
---Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
---Date        : Mon Apr 27 15:16:04 2020
---Host        : DESKTOP-L9P0FU6 running 64-bit major release  (build 9200)
---Command     : generate_target dut_packaging.bd
---Design      : dut_packaging
---Purpose     : IP block netlist
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity dut_packaging is
-  port (
-    clk_0 : in STD_LOGIC;
-    errorCode_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
-    fifo_read_0_empty : in STD_LOGIC;
-    fifo_read_0_rd_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
-    fifo_read_0_rd_en : out STD_LOGIC;
-    fifo_write_0_full : in STD_LOGIC;
-    fifo_write_0_wr_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
-    fifo_write_0_wr_en : out STD_LOGIC;
-    rst_0 : in STD_LOGIC;
-    stateOut_0 : out STD_LOGIC_VECTOR ( 3 downto 0 )
-  );
-  attribute CORE_GENERATION_INFO : string;
-  attribute CORE_GENERATION_INFO of dut_packaging : entity is "dut_packaging,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=dut_packaging,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=1,numReposBlks=1,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
-  attribute HW_HANDOFF : string;
-  attribute HW_HANDOFF of dut_packaging : entity is "dut_packaging.hwdef";
-end dut_packaging;
-
-architecture STRUCTURE of dut_packaging is
-  component dut_packaging_packaging_0_0 is
-  port (
-    clk : in STD_LOGIC;
-    rst : in STD_LOGIC;
-    inputStream : in STD_LOGIC_VECTOR ( 31 downto 0 );
-    inpRdEn : out STD_LOGIC;
-    inputEmpty : in STD_LOGIC;
-    outData : out STD_LOGIC_VECTOR ( 31 downto 0 );
-    outWrEn : out STD_LOGIC;
-    outputFull : in STD_LOGIC;
-    errorCode : out STD_LOGIC_VECTOR ( 3 downto 0 );
-    stateOut : out STD_LOGIC_VECTOR ( 3 downto 0 )
-  );
-  end component dut_packaging_packaging_0_0;
-  signal clk_0_1 : STD_LOGIC;
-  signal packaging_0_errorCode : STD_LOGIC_VECTOR ( 3 downto 0 );
-  signal packaging_0_fifo_read_EMPTY : STD_LOGIC;
-  signal packaging_0_fifo_read_RD_DATA : STD_LOGIC_VECTOR ( 31 downto 0 );
-  signal packaging_0_fifo_read_RD_EN : STD_LOGIC;
-  signal packaging_0_fifo_write_FULL : STD_LOGIC;
-  signal packaging_0_fifo_write_WR_DATA : STD_LOGIC_VECTOR ( 31 downto 0 );
-  signal packaging_0_fifo_write_WR_EN : STD_LOGIC;
-  signal packaging_0_stateOut : STD_LOGIC_VECTOR ( 3 downto 0 );
-  signal rst_0_1 : STD_LOGIC;
-  attribute X_INTERFACE_INFO : string;
-  attribute X_INTERFACE_INFO of clk_0 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_0 CLK";
-  attribute X_INTERFACE_PARAMETER : string;
-  attribute X_INTERFACE_PARAMETER of clk_0 : signal is "XIL_INTERFACENAME CLK.CLK_0, ASSOCIATED_RESET rst_0, CLK_DOMAIN dut_packaging_clk_0, FREQ_HZ 100000000, INSERT_VIP 0, PHASE 0.000";
-  attribute X_INTERFACE_INFO of fifo_read_0_empty : signal is "xilinx.com:interface:fifo_read:1.0 fifo_read_0 EMPTY";
-  attribute X_INTERFACE_INFO of fifo_read_0_rd_en : signal is "xilinx.com:interface:fifo_read:1.0 fifo_read_0 RD_EN";
-  attribute X_INTERFACE_INFO of fifo_write_0_full : signal is "xilinx.com:interface:fifo_write:1.0 fifo_write_0 FULL";
-  attribute X_INTERFACE_INFO of fifo_write_0_wr_en : signal is "xilinx.com:interface:fifo_write:1.0 fifo_write_0 WR_EN";
-  attribute X_INTERFACE_INFO of rst_0 : signal is "xilinx.com:signal:reset:1.0 RST.RST_0 RST";
-  attribute X_INTERFACE_PARAMETER of rst_0 : signal is "XIL_INTERFACENAME RST.RST_0, INSERT_VIP 0, POLARITY ACTIVE_LOW";
-  attribute X_INTERFACE_INFO of fifo_read_0_rd_data : signal is "xilinx.com:interface:fifo_read:1.0 fifo_read_0 RD_DATA";
-  attribute X_INTERFACE_INFO of fifo_write_0_wr_data : signal is "xilinx.com:interface:fifo_write:1.0 fifo_write_0 WR_DATA";
-begin
-  clk_0_1 <= clk_0;
-  errorCode_0(3 downto 0) <= packaging_0_errorCode(3 downto 0);
-  fifo_read_0_rd_en <= packaging_0_fifo_read_RD_EN;
-  fifo_write_0_wr_data(31 downto 0) <= packaging_0_fifo_write_WR_DATA(31 downto 0);
-  fifo_write_0_wr_en <= packaging_0_fifo_write_WR_EN;
-  packaging_0_fifo_read_EMPTY <= fifo_read_0_empty;
-  packaging_0_fifo_read_RD_DATA(31 downto 0) <= fifo_read_0_rd_data(31 downto 0);
-  packaging_0_fifo_write_FULL <= fifo_write_0_full;
-  rst_0_1 <= rst_0;
-  stateOut_0(3 downto 0) <= packaging_0_stateOut(3 downto 0);
-packaging_0: component dut_packaging_packaging_0_0
-     port map (
-      clk => clk_0_1,
-      errorCode(3 downto 0) => packaging_0_errorCode(3 downto 0),
-      inpRdEn => packaging_0_fifo_read_RD_EN,
-      inputEmpty => packaging_0_fifo_read_EMPTY,
-      inputStream(31 downto 0) => packaging_0_fifo_read_RD_DATA(31 downto 0),
-      outData(31 downto 0) => packaging_0_fifo_write_WR_DATA(31 downto 0),
-      outWrEn => packaging_0_fifo_write_WR_EN,
-      outputFull => packaging_0_fifo_write_FULL,
-      rst => rst_0_1,
-      stateOut(3 downto 0) => packaging_0_stateOut(3 downto 0)
-    );
-end STRUCTURE;

src/testbench/dut_packaging/ui/bd_6c72d067.ui

@@ -1,21 +0,0 @@
-{
-   "ExpandedHierarchyInLayout":"",
-   "guistr":"# # String gsaved with Nlview 6.8.11  2018-08-07 bk=1.4403 VDI=40 GEI=35 GUI=JA:9.0 non-TLS
-#  -string -flagsOSRD
-preplace port rst_0 -pg 1 -y -280 -defaultsOSRD
-preplace port fifo_read_0 -pg 1 -y -320 -defaultsOSRD
-preplace port clk_0 -pg 1 -y -310 -defaultsOSRD
-preplace port fifo_write_0 -pg 1 -y -290 -defaultsOSRD
-preplace portBus stateOut_0 -pg 1 -y -230 -defaultsOSRD
-preplace portBus errorCode_0 -pg 1 -y -260 -defaultsOSRD
-preplace inst packaging_0 -pg 1 -lvl 1 -y -290 -defaultsOSRD
-preplace netloc packaging_0_errorCode 1 1 1 210J
-preplace netloc packaging_0_fifo_write 1 1 1 210J
-preplace netloc clk_0_1 1 0 1 0J
-preplace netloc rst_0_1 1 0 1 NJ
-preplace netloc packaging_0_fifo_read 1 1 1 NJ
-preplace netloc packaging_0_stateOut 1 1 1 200J
-levelinfo -pg 1 -20 100 230 -top -380 -bot 180
-"
-}
-

src/testbench/packaging_tb.vhd

@@ -5,27 +5,30 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
 use STD.textio.all;
 use ieee.std_logic_textio.all;
 
-entity tb is
+entity tb_module is
         
-end tb;
+end tb_module;
 
-architecture Behavioral of tb is
+architecture Behavioral of tb_module is
 
 constant busWidth : integer:=32;
 
-    component dut_packaging_wrapper is
-      port (
-        clk_0 : in STD_LOGIC;
-        errorCode_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
-        fifo_read_0_empty : in STD_LOGIC;
-        fifo_read_0_rd_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
-        fifo_read_0_rd_en : out STD_LOGIC;
-        fifo_write_0_full : in STD_LOGIC;
-        fifo_write_0_wr_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
-        fifo_write_0_wr_en : out STD_LOGIC;
-        rst_0 : in STD_LOGIC;
-        stateOut_0 : out STD_LOGIC_VECTOR ( 3 downto 0 )
-      );
+    component packaging is
+    generic(
+        busWidth : integer:=32);
+    Port ( clk : in STD_LOGIC;
+           rst : in STD_LOGIC;
+           
+           inputStream : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           inpRdEn : out std_logic;
+           inputEmpty : in std_logic;
+           
+           outData : out STD_LOGIC_VECTOR (busWidth-1 downto 0);
+           outWrEn : out std_logic;
+           outputFull : in std_logic;
+           
+           errorCode : out STD_LOGIC_VECTOR(3 DOWNTO 0);
+           stateOut : out STD_LOGIC_VECTOR(3 downto 0));
     end component;
     
     signal clk : std_logic := '1';
@@ -57,17 +60,17 @@ constant busWidth : integer:=32;
 
 begin
 
-    dut : dut_packaging_wrapper port map (
-        clk_0 => clk,
-        rst_0 => rst,
+    dut : packaging port map (
+        clk => clk,
+        rst => rst,
         
-        fifo_read_0_rd_data => s_inData,
-        fifo_read_0_empty => inputEmpty,
-        fifo_read_0_rd_en => rdEn,
+        inputStream => s_inData,
+        inputEmpty => inputEmpty,
+        inpRdEn => rdEn,
         
-        fifo_write_0_wr_data => s_outData,
-        fifo_write_0_wr_en => wrEn,
-        fifo_write_0_full => outputFull
+        outData => s_outData,
+        outWrEn => wrEn,
+        outputFull => outputFull
         
     );
 

vhdl-modules.tcl

@@ -99,14 +99,14 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use
 set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
 set_property -name "simulator_language" -value "Mixed" -objects $obj
 set_property -name "target_language" -value "VHDL" -objects $obj
-set_property -name "webtalk.activehdl_export_sim" -value "2" -objects $obj
-set_property -name "webtalk.ies_export_sim" -value "2" -objects $obj
-set_property -name "webtalk.modelsim_export_sim" -value "2" -objects $obj
-set_property -name "webtalk.questa_export_sim" -value "2" -objects $obj
-set_property -name "webtalk.riviera_export_sim" -value "2" -objects $obj
-set_property -name "webtalk.vcs_export_sim" -value "2" -objects $obj
-set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj
-set_property -name "webtalk.xsim_export_sim" -value "2" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "4" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "4" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "4" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "4" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "4" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "4" -objects $obj
+set_property -name "webtalk.xcelium_export_sim" -value "3" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "4" -objects $obj
 set_property -name "webtalk.xsim_launch_sim" -value "3" -objects $obj
 set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
 
@@ -125,13 +125,13 @@ update_ip_catalog -rebuild
 # Set 'sources_1' fileset object
 set obj [get_filesets sources_1]
 set files [list \
+ [file normalize "${origin_dir}/src/hdl/globals.vhd"] \
  [file normalize "${origin_dir}/src/hdl/Block_proc.vhd"] \
  [file normalize "${origin_dir}/src/hdl/Loop_Border_proc.vhd"] \
  [file normalize "${origin_dir}/src/hdl/Loop_Border_proc_borderbuf.vhd"] \
  [file normalize "${origin_dir}/src/hdl/Loop_HConvH_proc6.vhd"] \
  [file normalize "${origin_dir}/src/hdl/Loop_VConvH_proc.vhd"] \
  [file normalize "${origin_dir}/src/hdl/Loop_VConvH_proc_linebuf_0.vhd"] \
- [file normalize "${origin_dir}/src/hdl/globals.vhd"] \
  [file normalize "${origin_dir}/src/hdl/checksum.vhd"] \
  [file normalize "${origin_dir}/src/hdl/conv2d.vhd"] \
  [file normalize "${origin_dir}/src/hdl/conv2d_5x5_224p.vhd"] \
@@ -153,6 +153,11 @@ set files [list \
 add_files -norecurse -fileset $obj $files
 
 # Set 'sources_1' fileset file properties for remote files
+set file "$origin_dir/src/hdl/globals.vhd"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
 set file "$origin_dir/src/hdl/Block_proc.vhd"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
@@ -183,11 +188,6 @@ set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "VHDL" -objects $file_obj
 
-set file "$origin_dir/src/hdl/globals.vhd"
-set file [file normalize $file]
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "file_type" -value "VHDL" -objects $file_obj
-
 set file "$origin_dir/src/hdl/checksum.vhd"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
@@ -286,9 +286,9 @@ if {[string equal [get_filesets -quiet constrs_1] ""]} {
 set obj [get_filesets constrs_1]
 
 # Add/Import constrs file and set constrs file properties
-set file "[file normalize ${origin_dir}/vivado_project/vhdl-modules.srcs/constrs_1/imports/constraints/nexys_4_ddr.xdc]"
+set file "[file normalize "$origin_dir/src/constraints/nexys_4_ddr.xdc"]"
 set file_added [add_files -norecurse -fileset $obj [list $file]]
-set file "$origin_dir/vivado_project/vhdl-modules.srcs/constrs_1/imports/constraints/nexys_4_ddr.xdc"
+set file "$origin_dir/src/constraints/nexys_4_ddr.xdc"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
 set_property -name "file_type" -value "XDC" -objects $file_obj
@@ -305,18 +305,13 @@ if {[string equal [get_filesets -quiet sim_1] ""]} {
 # Set 'sim_1' fileset object
 set obj [get_filesets sim_1]
 set files [list \
- [file normalize "${origin_dir}/src/hdl/tb.vhd"] \
- [file normalize "${origin_dir}/src/testbench/packaging_tb.vhd"] \
+ [file normalize "${origin_dir}/vivado_project/vhdl-modules.srcs/sim_1/imports/testbench/packaging_tb.vhd"] \
+ [file normalize "${origin_dir}/vivado_project/vhdl-modules.srcs/sim_1/imports/testbench/tb_module_behav.wcfg"] \
 ]
 add_files -norecurse -fileset $obj $files
 
 # Set 'sim_1' fileset file properties for remote files
-set file "$origin_dir/src/hdl/tb.vhd"
-set file [file normalize $file]
-set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
-set_property -name "file_type" -value "VHDL" -objects $file_obj
-
-set file "$origin_dir/src/testbench/packaging_tb.vhd"
+set file "$origin_dir/vivado_project/vhdl-modules.srcs/sim_1/imports/testbench/packaging_tb.vhd"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
 set_property -name "file_type" -value "VHDL" -objects $file_obj
@@ -327,6 +322,7 @@ set_property -name "file_type" -value "VHDL" -objects $file_obj
 
 # Set 'sim_1' fileset properties
 set obj [get_filesets sim_1]
+set_property -name "source_set" -value "" -objects $obj
 set_property -name "top" -value "tb_module" -objects $obj
 set_property -name "top_auto_set" -value "0" -objects $obj
 set_property -name "top_lib" -value "xil_defaultlib" -objects $obj