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@@ -1,7 +1,7 @@
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# VHDL neural network accelerators for distributed computation on FPGAs
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VHDL implementation of job parser and hardware accelerator modules.
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-It uses a modified version of a [UDP echo server](https://forum.digilentinc.com/topic/3968-ethernet-udp-echo-server/) to send and recieve jobs from [this library](/bachelor/tf-fpga).
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+It uses a modified version of a [UDP echo server](https://forum.digilentinc.com/topic/3968-ethernet-udp-echo-server/) to send and recieve jobs from [this library](https://github.com/jm-hsn/tf-fpga).
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Each job is contained in a 32-bit data stream and comprised of
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- preamble
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