deleted old ips

src/ip_repo/myip_1.0/bd/bd.tcl

@@ -1,86 +0,0 @@
-
-proc init { cellpath otherInfo } {                                                                   
-                                                                                                             
-	set cell_handle [get_bd_cells $cellpath]                                                                 
-	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
-	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-	set full_sbusif_list [list  ]
-			                                                                                                 
-	foreach busif $all_busif {                                                                               
-		if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {                            
-			set busif_param_list [list]                                                                      
-			set busif_name [get_property NAME $busif]					                                     
-			if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {					         
-			    continue                                                                                     
-			}                                                                                                
-			foreach tparam $axi_standard_param_list {                                                        
-				lappend busif_param_list "C_${busif_name}_${tparam}"                                       
-			}                                                                                                
-			bd::mark_propagate_only $cell_handle $busif_param_list			                                 
-		}		                                                                                             
-	}                                                                                                        
-}
-
-
-proc pre_propagate {cellpath otherInfo } {                                                           
-                                                                                                             
-	set cell_handle [get_bd_cells $cellpath]                                                                 
-	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
-	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-	                                                                                                         
-	foreach busif $all_busif {	                                                                             
-		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
-			continue                                                                                         
-		}                                                                                                    
-		if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {                           
-			continue                                                                                         
-		}			                                                                                         
-		                                                                                                     
-		set busif_name [get_property NAME $busif]			                                                 
-		foreach tparam $axi_standard_param_list {		                                                     
-			set busif_param_name "C_${busif_name}_${tparam}"			                                     
-			                                                                                                 
-			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
-			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
-			                                                                                                 
-			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
-				if { $val_on_cell != "" } {                                                                  
-					set_property CONFIG.${tparam} $val_on_cell $busif                                        
-				}                                                                                            
-			}			                                                                                     
-		}		                                                                                             
-	}                                                                                                        
-}
-
-
-proc propagate {cellpath otherInfo } {                                                               
-                                                                                                             
-	set cell_handle [get_bd_cells $cellpath]                                                                 
-	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
-	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-	                                                                                                         
-	foreach busif $all_busif {                                                                               
-		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
-			continue                                                                                         
-		}                                                                                                    
-		if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {                            
-			continue                                                                                         
-		}			                                                                                         
-	                                                                                                         
-		set busif_name [get_property NAME $busif]		                                                     
-		foreach tparam $axi_standard_param_list {			                                                 
-			set busif_param_name "C_${busif_name}_${tparam}"			                                     
-                                                                                                             
-			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
-			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
-			                                                                                                 
-			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
-				#override property of bd_interface_net to bd_cell -- only for slaves.  May check for supported values..
-				if { $val_on_cell_intf_pin != "" } {                                                         
-					set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle               
-				}                                                                                            
-			}                                                                                                
-		}		                                                                                             
-	}                                                                                                        
-}
-

src/ip_repo/myip_1.0/component.xml

@@ -1,828 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-  <spirit:vendor>user.org</spirit:vendor>
-  <spirit:library>user</spirit:library>
-  <spirit:name>myip</spirit:name>
-  <spirit:version>1.0</spirit:version>
-  <spirit:busInterfaces>
-    <spirit:busInterface>
-      <spirit:name>S00_AXI</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
-      <spirit:slave>
-        <spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
-      </spirit:slave>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWADDR</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awaddr</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWPROT</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awprot</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WDATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wdata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WSTRB</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wstrb</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>BRESP</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_bresp</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>BVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_bvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>BREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_bready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARADDR</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_araddr</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARPROT</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_arprot</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_arvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_arready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RDATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rdata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RRESP</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rresp</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>WIZ_DATA_WIDTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>WIZ_NUM_REG</spirit:name>
-          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
-          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>S00_AXI_RST</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RST</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_aresetn</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>POLARITY</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_RST.POLARITY">ACTIVE_LOW</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>S00_AXI_CLK</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>CLK</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_aclk</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_BUSIF">S00_AXI</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>ASSOCIATED_RESET</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-  </spirit:busInterfaces>
-  <spirit:memoryMaps>
-    <spirit:memoryMap>
-      <spirit:name>S00_AXI</spirit:name>
-      <spirit:addressBlock>
-        <spirit:name>S00_AXI_reg</spirit:name>
-        <spirit:baseAddress spirit:format="long" spirit:resolve="user">0</spirit:baseAddress>
-        <spirit:range spirit:format="long">4096</spirit:range>
-        <spirit:width spirit:format="long">32</spirit:width>
-        <spirit:usage>register</spirit:usage>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
-            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_BASE_PARAM">C_S00_AXI_BASEADDR</spirit:value>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
-            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_HIGH_PARAM">C_S00_AXI_HIGHADDR</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:addressBlock>
-    </spirit:memoryMap>
-  </spirit:memoryMaps>
-  <spirit:model>
-    <spirit:views>
-      <spirit:view>
-        <spirit:name>xilinx_vhdlsynthesis</spirit:name>
-        <spirit:displayName>VHDL Synthesis</spirit:displayName>
-        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
-        <spirit:language>vhdl</spirit:language>
-        <spirit:modelName>myip_v1_0</spirit:modelName>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>68e2ce51</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
-        <spirit:displayName>VHDL Simulation</spirit:displayName>
-        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
-        <spirit:language>vhdl</spirit:language>
-        <spirit:modelName>myip_v1_0</spirit:modelName>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>68e2ce51</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_softwaredriver</spirit:name>
-        <spirit:displayName>Software Driver</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:sw.driver</spirit:envIdentifier>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_softwaredriver_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>3ccb2799</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_xpgui</spirit:name>
-        <spirit:displayName>UI Layout</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>fd592ead</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>bd_tcl</spirit:name>
-        <spirit:displayName>Block Diagram</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
-        <spirit:fileSetRef>
-          <spirit:localName>bd_tcl_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>45a2f450</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-    </spirit:views>
-    <spirit:ports>
-      <spirit:port>
-        <spirit:name>s00_axi_awaddr</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH&apos;))-1)">6</spirit:left>
-            <spirit:right spirit:format="long">0</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_awprot</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left spirit:format="long">2</spirit:left>
-            <spirit:right spirit:format="long">0</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_awvalid</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_awready</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_wdata</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH&apos;))-1)">31</spirit:left>
-            <spirit:right spirit:format="long">0</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_wstrb</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH&apos;))/8)-1)">3</spirit:left>
-            <spirit:right spirit:format="long">0</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_wvalid</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
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-            </spirit:wireTypeDef>
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-        <spirit:name>s00_axi_araddr</spirit:name>
-        <spirit:wire>
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-      <spirit:port>
-        <spirit:name>s00_axi_arvalid</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_arready</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
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-      <spirit:port>
-        <spirit:name>s00_axi_rdata</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH&apos;))-1)">31</spirit:left>
-            <spirit:right spirit:format="long">0</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
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-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_aclk</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>s00_axi_aresetn</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-    </spirit:ports>
-    <spirit:modelParameters>
-      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
-        <spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
-        <spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
-        <spirit:description>Width of S_AXI data bus</spirit:description>
-        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:order="3" spirit:rangeType="long">32</spirit:value>
-      </spirit:modelParameter>
-      <spirit:modelParameter spirit:dataType="integer">
-        <spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
-        <spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
-        <spirit:description>Width of S_AXI address bus</spirit:description>
-        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">7</spirit:value>
-      </spirit:modelParameter>
-    </spirit:modelParameters>
-  </spirit:model>
-  <spirit:choices>
-    <spirit:choice>
-      <spirit:name>choice_list_6fc15197</spirit:name>
-      <spirit:enumeration>32</spirit:enumeration>
-    </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_ce1226b1</spirit:name>
-      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
-    </spirit:choice>
-  </spirit:choices>
-  <spirit:fileSets>
-    <spirit:fileSet>
-      <spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
-      <spirit:file>
-        <spirit:name>hdl/myip_v1_0_S00_AXI.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>hdl/myip_v1_0.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_7e1348a6</spirit:userFileType>
-      </spirit:file>
-    </spirit:fileSet>
-    <spirit:fileSet>
-      <spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
-      <spirit:file>
-        <spirit:name>hdl/myip_v1_0_S00_AXI.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
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-      <spirit:file>
-        <spirit:name>hdl/myip_v1_0.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-      </spirit:file>
-    </spirit:fileSet>
-    <spirit:fileSet>
-      <spirit:name>xilinx_softwaredriver_view_fileset</spirit:name>
-      <spirit:file>
-        <spirit:name>drivers/myip_v1_0/data/myip.mdd</spirit:name>
-        <spirit:userFileType>mdd</spirit:userFileType>
-        <spirit:userFileType>driver_mdd</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>drivers/myip_v1_0/data/myip.tcl</spirit:name>
-        <spirit:fileType>tclSource</spirit:fileType>
-        <spirit:userFileType>driver_tcl</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>drivers/myip_v1_0/src/Makefile</spirit:name>
-        <spirit:userFileType>driver_src</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>drivers/myip_v1_0/src/myip.h</spirit:name>
-        <spirit:fileType>cSource</spirit:fileType>
-        <spirit:userFileType>driver_src</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>drivers/myip_v1_0/src/myip.c</spirit:name>
-        <spirit:fileType>cSource</spirit:fileType>
-        <spirit:userFileType>driver_src</spirit:userFileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>drivers/myip_v1_0/src/myip_selftest.c</spirit:name>
-        <spirit:fileType>cSource</spirit:fileType>
-        <spirit:userFileType>driver_src</spirit:userFileType>
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-        <spirit:userFileType>CHECKSUM_fd592ead</spirit:userFileType>
-        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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-    </spirit:fileSet>
-    <spirit:fileSet>
-      <spirit:name>bd_tcl_view_fileset</spirit:name>
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-        <spirit:name>bd/bd.tcl</spirit:name>
-        <spirit:fileType>tclSource</spirit:fileType>
-      </spirit:file>
-    </spirit:fileSet>
-  </spirit:fileSets>
-  <spirit:description>My new AXI IP</spirit:description>
-  <spirit:parameters>
-    <spirit:parameter>
-      <spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
-      <spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
-      <spirit:description>Width of S_AXI data bus</spirit:description>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="3">32</spirit:value>
-      <spirit:vendorExtensions>
-        <xilinx:parameterInfo>
-          <xilinx:enablement>
-            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_DATA_WIDTH">false</xilinx:isEnabled>
-          </xilinx:enablement>
-        </xilinx:parameterInfo>
-      </spirit:vendorExtensions>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
-      <spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
-      <spirit:description>Width of S_AXI address bus</spirit:description>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">7</spirit:value>
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-        <xilinx:parameterInfo>
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-          </xilinx:enablement>
-        </xilinx:parameterInfo>
-      </spirit:vendorExtensions>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>C_S00_AXI_BASEADDR</spirit:name>
-      <spirit:displayName>C S00 AXI BASEADDR</spirit:displayName>
-      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
-      <spirit:vendorExtensions>
-        <xilinx:parameterInfo>
-          <xilinx:enablement>
-            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_BASEADDR">false</xilinx:isEnabled>
-          </xilinx:enablement>
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-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
-      <spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
-      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
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-        <xilinx:parameterInfo>
-          <xilinx:enablement>
-            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_HIGHADDR">false</xilinx:isEnabled>
-          </xilinx:enablement>
-        </xilinx:parameterInfo>
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-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>Component_Name</spirit:name>
-      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">myip_v1_0</spirit:value>
-    </spirit:parameter>
-  </spirit:parameters>
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-      <xilinx:supportedFamilies>
-        <xilinx:family xilinx:lifeCycle="Pre-Production">artix7</xilinx:family>
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-      <xilinx:taxonomies>
-        <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
-      </xilinx:taxonomies>
-      <xilinx:displayName>myip_v1.0</xilinx:displayName>
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-        <xilinx:tag xilinx:name="ui.data.coregen.dd@25589aa_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/myip_1.0</xilinx:tag>
-        <xilinx:tag xilinx:name="ui.data.coregen.dd@789342e6_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/myip_1.0</xilinx:tag>
-        <xilinx:tag xilinx:name="ui.data.coregen.dd@7fc904b4_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/myip_1.0</xilinx:tag>
-        <xilinx:tag xilinx:name="ui.data.coregen.dd@37d27b0d_ARCHIVE_LOCATION">/home/johannes/Desktop/mlfpga/ip_repo/myip_1.0</xilinx:tag>
-      </xilinx:tags>
-    </xilinx:coreExtensions>
-    <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
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-      <xilinx:checksum xilinx:scope="ports" xilinx:value="1b4053fb"/>
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-  </spirit:vendorExtensions>
-</spirit:component>

src/ip_repo/myip_1.0/drivers/myip_v1_0/data/myip.mdd

@@ -1,10 +0,0 @@
-
-
-OPTION psf_version = 2.1;
-
-BEGIN DRIVER myip
-	OPTION supported_peripherals = (myip);
-	OPTION copyfiles = all;
-	OPTION VERSION = 1.0;
-	OPTION NAME = myip;
-END DRIVER

src/ip_repo/myip_1.0/drivers/myip_v1_0/data/myip.tcl

@@ -1,5 +0,0 @@
-
-
-proc generate {drv_handle} {
-	xdefine_include_file $drv_handle "xparameters.h" "myip" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
-}

src/ip_repo/myip_1.0/drivers/myip_v1_0/src/Makefile

@@ -1,26 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-LIBSOURCES=*.c
-OUTS = *.o
-
-libs:
-	echo "Compiling myip..."
-	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
-	make clean
-
-include:
-	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
-	rm -rf ${OUTS}

src/ip_repo/myip_1.0/drivers/myip_v1_0/src/myip.c

@@ -1,6 +0,0 @@
-
-
-/***************************** Include Files *******************************/
-#include "myip.h"
-
-/************************** Function Definitions ***************************/

src/ip_repo/myip_1.0/drivers/myip_v1_0/src/myip.h

@@ -1,107 +0,0 @@
-
-#ifndef MYIP_H
-#define MYIP_H
-
-
-/****************** Include Files ********************/
-#include "xil_types.h"
-#include "xstatus.h"
-
-#define MYIP_S00_AXI_SLV_REG0_OFFSET 0
-#define MYIP_S00_AXI_SLV_REG1_OFFSET 4
-#define MYIP_S00_AXI_SLV_REG2_OFFSET 8
-#define MYIP_S00_AXI_SLV_REG3_OFFSET 12
-#define MYIP_S00_AXI_SLV_REG4_OFFSET 16
-#define MYIP_S00_AXI_SLV_REG5_OFFSET 20
-#define MYIP_S00_AXI_SLV_REG6_OFFSET 24
-#define MYIP_S00_AXI_SLV_REG7_OFFSET 28
-#define MYIP_S00_AXI_SLV_REG8_OFFSET 32
-#define MYIP_S00_AXI_SLV_REG9_OFFSET 36
-#define MYIP_S00_AXI_SLV_REG10_OFFSET 40
-#define MYIP_S00_AXI_SLV_REG11_OFFSET 44
-#define MYIP_S00_AXI_SLV_REG12_OFFSET 48
-#define MYIP_S00_AXI_SLV_REG13_OFFSET 52
-#define MYIP_S00_AXI_SLV_REG14_OFFSET 56
-#define MYIP_S00_AXI_SLV_REG15_OFFSET 60
-#define MYIP_S00_AXI_SLV_REG16_OFFSET 64
-#define MYIP_S00_AXI_SLV_REG17_OFFSET 68
-#define MYIP_S00_AXI_SLV_REG18_OFFSET 72
-#define MYIP_S00_AXI_SLV_REG19_OFFSET 76
-#define MYIP_S00_AXI_SLV_REG20_OFFSET 80
-#define MYIP_S00_AXI_SLV_REG21_OFFSET 84
-#define MYIP_S00_AXI_SLV_REG22_OFFSET 88
-#define MYIP_S00_AXI_SLV_REG23_OFFSET 92
-#define MYIP_S00_AXI_SLV_REG24_OFFSET 96
-#define MYIP_S00_AXI_SLV_REG25_OFFSET 100
-#define MYIP_S00_AXI_SLV_REG26_OFFSET 104
-#define MYIP_S00_AXI_SLV_REG27_OFFSET 108
-#define MYIP_S00_AXI_SLV_REG28_OFFSET 112
-#define MYIP_S00_AXI_SLV_REG29_OFFSET 116
-#define MYIP_S00_AXI_SLV_REG30_OFFSET 120
-#define MYIP_S00_AXI_SLV_REG31_OFFSET 124
-
-
-/**************************** Type Definitions *****************************/
-/**
- *
- * Write a value to a MYIP register. A 32 bit write is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is written.
- *
- * @param   BaseAddress is the base address of the MYIPdevice.
- * @param   RegOffset is the register offset from the base to write to.
- * @param   Data is the data written to the register.
- *
- * @return  None.
- *
- * @note
- * C-style signature:
- * 	void MYIP_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
- *
- */
-#define MYIP_mWriteReg(BaseAddress, RegOffset, Data) \
-  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/**
- *
- * Read a value from a MYIP register. A 32 bit read is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is read from the register. The most significant data
- * will be read as 0.
- *
- * @param   BaseAddress is the base address of the MYIP device.
- * @param   RegOffset is the register offset from the base to write to.
- *
- * @return  Data is the data from the register.
- *
- * @note
- * C-style signature:
- * 	u32 MYIP_mReadReg(u32 BaseAddress, unsigned RegOffset)
- *
- */
-#define MYIP_mReadReg(BaseAddress, RegOffset) \
-    Xil_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ****************************/
-/**
- *
- * Run a self-test on the driver/device. Note this may be a destructive test if
- * resets of the device are performed.
- *
- * If the hardware system is not built correctly, this function may never
- * return to the caller.
- *
- * @param   baseaddr_p is the base address of the MYIP instance to be worked on.
- *
- * @return
- *
- *    - XST_SUCCESS   if all self-test code passed
- *    - XST_FAILURE   if any self-test code failed
- *
- * @note    Caching must be turned off for this function to work.
- * @note    Self test may fail if data memory and device are not on the same bus.
- *
- */
-XStatus MYIP_Reg_SelfTest(void * baseaddr_p);
-
-#endif // MYIP_H

src/ip_repo/myip_1.0/drivers/myip_v1_0/src/myip_selftest.c

@@ -1,60 +0,0 @@
-
-/***************************** Include Files *******************************/
-#include "myip.h"
-#include "xparameters.h"
-#include "stdio.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ***************************/
-#define READ_WRITE_MUL_FACTOR 0x10
-
-/************************** Function Definitions ***************************/
-/**
- *
- * Run a self-test on the driver/device. Note this may be a destructive test if
- * resets of the device are performed.
- *
- * If the hardware system is not built correctly, this function may never
- * return to the caller.
- *
- * @param   baseaddr_p is the base address of the MYIPinstance to be worked on.
- *
- * @return
- *
- *    - XST_SUCCESS   if all self-test code passed
- *    - XST_FAILURE   if any self-test code failed
- *
- * @note    Caching must be turned off for this function to work.
- * @note    Self test may fail if data memory and device are not on the same bus.
- *
- */
-XStatus MYIP_Reg_SelfTest(void * baseaddr_p)
-{
-	u32 baseaddr;
-	int write_loop_index;
-	int read_loop_index;
-	int Index;
-
-	baseaddr = (u32) baseaddr_p;
-
-	xil_printf("******************************\n\r");
-	xil_printf("* User Peripheral Self Test\n\r");
-	xil_printf("******************************\n\n\r");
-
-	/*
-	 * Write to user logic slave module register(s) and read back
-	 */
-	xil_printf("User logic slave module test...\n\r");
-
-	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
-	  MYIP_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
-	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
-	  if ( MYIP_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
-	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
-	    return XST_FAILURE;
-	  }
-
-	xil_printf("   - slave register write/read passed\n\n\r");
-
-	return XST_SUCCESS;
-}

src/ip_repo/myip_1.0/example_designs/bfm_design/design.tcl

@@ -1,88 +0,0 @@
-proc create_ipi_design { offsetfile design_name } {
-	create_bd_design $design_name
-	open_bd_design $design_name
-
-	# Create Clock and Reset Ports
-	set ACLK [ create_bd_port -dir I -type clk ACLK ]
-	set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
-	set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
-	set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $ARESETN
-	set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
-
-	# Create instance: myip_0, and set properties
-	set myip_0 [ create_bd_cell -type ip -vlnv user.org:user:myip:1.0 myip_0]
-
-	# Create instance: master_0, and set properties
-	set master_0 [ create_bd_cell -type ip -vlnv  xilinx.com:ip:axi_vip master_0]
-	set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
-
-	# Create interface connections
-	connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins myip_0/S00_AXI]
-
-	# Create port connections
-	connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins myip_0/S00_AXI_ACLK]
-	connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins myip_0/S00_AXI_ARESETN]
-set_property target_simulator XSim [current_project]
-set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
-
-	# Auto assign address
-	assign_bd_address
-
-	# Copy all address to interface_address.vh file
-	set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
-	upvar 1 $offsetfile offset_file
-	set offset_file "${bd_path}/myip_v1_0_tb_include.svh"
-	set fp [open $offset_file "w"]
-	puts $fp "`ifndef myip_v1_0_tb_include_vh_"
-	puts $fp "`define myip_v1_0_tb_include_vh_\n"
-	puts $fp "//Configuration current bd names"
-	puts $fp "`define BD_NAME ${design_name}"
-	puts $fp "`define BD_INST_NAME ${design_name}_i"
-	puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
-	puts $fp "//Configuration address parameters"
-
-	puts $fp "`endif"
-	close $fp
-}
-
-set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:myip:1.0]]]]
-set test_bench_file ${ip_path}/example_designs/bfm_design/myip_v1_0_tb.sv
-set interface_address_vh_file ""
-
-# Set IP Repository and Update IP Catalogue 
-set repo_paths [get_property ip_repo_paths [current_fileset]] 
-if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
-	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
-	update_ip_catalog
-}
-
-set design_name ""
-set all_bd {}
-set all_bd_files [get_files *.bd -quiet]
-foreach file $all_bd_files {
-set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
-set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
-lappend all_bd $bd_name
-}
-
-for { set i 1 } { 1 } { incr i } {
-	set design_name "myip_v1_0_bfm_${i}"
-	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
-		break
-	}
-}
-
-create_ipi_design interface_address_vh_file ${design_name}
-validate_bd_design
-
-set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
-import_files -force -norecurse $wrapper_file
-
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
-import_files -fileset sim_1 -norecurse -force $test_bench_file
-remove_files -quiet -fileset sim_1 myip_v1_0_tb_include.vh
-import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
-set_property top myip_v1_0_tb [get_filesets sim_1]
-set_property top_lib {} [get_filesets sim_1]
-set_property top_file {} [get_filesets sim_1]
-launch_simulation -simset sim_1 -mode behavioral

src/ip_repo/myip_1.0/example_designs/bfm_design/myip_v1_0_tb.sv

@@ -1,197 +0,0 @@
-
-`timescale 1ns / 1ps
-`include "myip_v1_0_tb_include.svh"
-
-import axi_vip_pkg::*;
-import myip_v1_0_bfm_1_master_0_0_pkg::*;
-
-module myip_v1_0_tb();
-
-
-xil_axi_uint                            error_cnt = 0;
-xil_axi_uint                            comparison_cnt = 0;
-axi_transaction                         wr_transaction;   
-axi_transaction                         rd_transaction;   
-axi_monitor_transaction                 mst_monitor_transaction;  
-axi_monitor_transaction                 master_moniter_transaction_queue[$];  
-xil_axi_uint                            master_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 mst_scb_transaction;  
-axi_monitor_transaction                 passthrough_monitor_transaction;  
-axi_monitor_transaction                 passthrough_master_moniter_transaction_queue[$];  
-xil_axi_uint                            passthrough_master_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 passthrough_mst_scb_transaction;  
-axi_monitor_transaction                 passthrough_slave_moniter_transaction_queue[$];  
-xil_axi_uint                            passthrough_slave_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 passthrough_slv_scb_transaction;  
-axi_monitor_transaction                 slv_monitor_transaction;  
-axi_monitor_transaction                 slave_moniter_transaction_queue[$];  
-xil_axi_uint                            slave_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 slv_scb_transaction;  
-xil_axi_uint                           mst_agent_verbosity = 0;  
-xil_axi_uint                           slv_agent_verbosity = 0;  
-xil_axi_uint                           passthrough_agent_verbosity = 0;  
-bit                                     clock;
-bit                                     reset;
-integer result_slave;  
-bit [31:0] S00_AXI_test_data[3:0]; 
- localparam LC_AXI_BURST_LENGTH = 8; 
- localparam LC_AXI_DATA_WIDTH = 32; 
-task automatic COMPARE_DATA; 
-  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected; 
-  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual; 
-  begin 
-    if (expected === 'hx || actual === 'hx) begin 
-      $display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); 
- result_slave = 0;    $stop; 
-  end 
-  if (actual != expected) begin 
-    $display("TESTBENCH ERROR! Data expected is not equal to actual.",     " expected = 0x%h",expected,     " actual   = 0x%h",actual); 
-    result_slave = 0; 
-    $stop; 
-  end 
-  else  
-    begin 
-     $display("TESTBENCH Passed! Data expected is equal to actual.", 
-              " expected = 0x%h",expected,               " actual   = 0x%h",actual); 
-    end 
-  end 
-endtask 
-integer                                 i; 
-integer                                 j;  
-xil_axi_uint                            trans_cnt_before_switch = 48;  
-xil_axi_uint                            passthrough_cmd_switch_cnt = 0;  
-event                                   passthrough_mastermode_start_event;  
-event                                   passthrough_mastermode_end_event;  
-event                                   passthrough_slavemode_end_event;  
-xil_axi_uint                            mtestID;  
-xil_axi_ulong                           mtestADDR;  
-xil_axi_len_t                           mtestBurstLength;  
-xil_axi_size_t                          mtestDataSize;   
-xil_axi_burst_t                         mtestBurstType;   
-xil_axi_lock_t                          mtestLOCK;  
-xil_axi_cache_t                         mtestCacheType = 0;  
-xil_axi_prot_t                          mtestProtectionType = 3'b000;  
-xil_axi_region_t                        mtestRegion = 4'b000;  
-xil_axi_qos_t                           mtestQOS = 4'b000;  
-xil_axi_data_beat                       dbeat;  
-xil_axi_data_beat [255:0]               mtestWUSER;   
-xil_axi_data_beat                       mtestAWUSER = 'h0;  
-xil_axi_data_beat                       mtestARUSER = 0;  
-xil_axi_data_beat [255:0]               mtestRUSER;      
-xil_axi_uint                            mtestBUSER = 0;  
-xil_axi_resp_t                          mtestBresp;  
-xil_axi_resp_t[255:0]                   mtestRresp;  
-bit [63:0]                              mtestWDataL; 
-bit [63:0]                              mtestRDataL; 
-axi_transaction                         pss_wr_transaction;   
-axi_transaction                         pss_rd_transaction;   
-axi_transaction                         reactive_transaction;   
-axi_transaction                         rd_payload_transaction;  
-axi_transaction                         wr_rand;  
-axi_transaction                         rd_rand;  
-axi_transaction                         wr_reactive;  
-axi_transaction                         rd_reactive;  
-axi_transaction                         wr_reactive2;   
-axi_transaction                         rd_reactive2;  
-axi_ready_gen                           bready_gen;  
-axi_ready_gen                           rready_gen;  
-axi_ready_gen                           awready_gen;  
-axi_ready_gen                           wready_gen;  
-axi_ready_gen                           arready_gen;  
-axi_ready_gen                           bready_gen2;  
-axi_ready_gen                           rready_gen2;  
-axi_ready_gen                           awready_gen2;  
-axi_ready_gen                           wready_gen2;  
-axi_ready_gen                           arready_gen2;  
-xil_axi_payload_byte                    data_mem[xil_axi_ulong];  
-myip_v1_0_bfm_1_master_0_0_mst_t          mst_agent_0;
-
-  `BD_WRAPPER DUT(
-      .ARESETN(reset), 
-      .ACLK(clock) 
-    ); 
-  
-initial begin
-     mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms  
-   mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE); 
-   mst_agent_0.set_agent_tag("Master VIP"); 
-   mst_agent_0.set_verbosity(mst_agent_verbosity); 
-   mst_agent_0.start_master(); 
-     $timeformat (-12, 1, " ps", 1);
-  end
-  initial begin
-    reset <= 1'b0;
-    #200ns;
-    reset <= 1'b1;
-    repeat (5) @(negedge clock); 
-  end
-  always #5 clock <= ~clock;
-  initial begin
-      S_AXI_TEST ( );
-
-      #1ns;
-      $finish;
-  end
-task automatic S_AXI_TEST;  
-begin   
-#1; 
-   $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method starts"); 
-   mtestID = 0; 
-   mtestADDR = 64'h00000000; 
-   mtestBurstLength = 0; 
-   mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
-   mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
-   mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
-   mtestCacheType = 0;  
-   mtestProtectionType = 0;  
-   mtestRegion = 0; 
-   mtestQOS = 0; 
-   result_slave = 1; 
-  mtestWDataL[31:0] = 32'h00000001; 
-  for(int i = 0; i < 4;i++) begin 
-  S00_AXI_test_data[i] <= mtestWDataL[31:0];   
-  mst_agent_0.AXI4LITE_WRITE_BURST( 
-  mtestADDR, 
-  mtestProtectionType, 
-  mtestWDataL, 
-  mtestBresp 
-  );   
-  mtestWDataL[31:0] = mtestWDataL[31:0] + 1; 
-  mtestADDR = mtestADDR + 64'h4; 
-  end 
-     $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method completes"); 
-     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method starts"); 
-     mtestID = 0; 
-     mtestADDR = 64'h00000000; 
-     mtestBurstLength = 0; 
-     mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
-     mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
-     mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
-     mtestCacheType = 0;  
-     mtestProtectionType = 0;  
-     mtestRegion = 0; 
-     mtestQOS = 0; 
- for(int i = 0; i < 4;i++) begin 
-   mst_agent_0.AXI4LITE_READ_BURST( 
-        mtestADDR, 
-        mtestProtectionType, 
-        mtestRDataL, 
-        mtestRresp 
-      ); 
-   mtestADDR = mtestADDR + 64'h4; 
-   COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL); 
- end 
-     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method completes"); 
-     $display("Sequential read transfers example similar to  AXI VIP READ_BURST method completes"); 
-     $display("---------------------------------------------------------"); 
-     $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); 
-     if ( result_slave ) begin                    
-       $display("PTGEN_TEST: PASSED!");                  
-     end    else begin                                       
-       $display("PTGEN_TEST: FAILED!");                  
-     end                                
-     $display("---------------------------------------------------------"); 
-  end 
-endtask  
-
-endmodule

src/ip_repo/myip_1.0/example_designs/debug_hw_design/design.tcl

@@ -1,118 +0,0 @@
-
-proc create_ipi_design { offsetfile design_name } {
-
-	create_bd_design $design_name
-	open_bd_design $design_name
-
-	# Create and configure Clock/Reset
-	create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
-	create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
-
-	#Constraints will be provided manually while pin planning.
-		create_bd_port -dir I -type rst reset_rtl
-		set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
-		connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
-		connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
-		set external_reset_port reset_rtl
-		create_bd_port -dir I -type clk clock_rtl
-		connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
-		set external_clock_port clock_rtl
-	
-	#Avoid IPI DRC, make clock port synchronous to reset
-	if { $external_clock_port ne "" && $external_reset_port ne "" } {
-		set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
-	}
-
-	# Connect other sys_reset pins
-	connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
-
-	# Create instance: myip_0, and set properties
-	set myip_0 [ create_bd_cell -type ip -vlnv user.org:user:myip:1.0 myip_0 ]
-
-	# Create instance: jtag_axi_0, and set properties
-	set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
-	set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
-	connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
-	# Create instance: axi_peri_interconnect, and set properties
-	set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
-	set_property -dict [ list CONFIG.NUM_SI {1}  ] $axi_peri_interconnect
-	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
-	connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
-
-	set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
-	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
-	# Connect all clock & reset of myip_0 slave interfaces..
-	connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins myip_0/S00_AXI]
-	connect_bd_net [get_bd_pins myip_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins myip_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
-
-	# Auto assign address
-	assign_bd_address
-
-	# Copy all address to myip_v1_0_include.tcl file
-	set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
-	upvar 1 $offsetfile offset_file
-	set offset_file "${bd_path}/myip_v1_0_include.tcl"
-	set fp [open $offset_file "w"]
-	puts $fp "# Configuration address parameters"
-
-	set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_myip_0_S00_AXI_* ]]
-	puts $fp "set s00_axi_addr ${offset}"
-
-	close $fp
-}
-
-# Set IP Repository and Update IP Catalogue 
-set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:myip:1.0]]]]
-set hw_test_file ${ip_path}/example_designs/debug_hw_design/myip_v1_0_hw_test.tcl
-
-set repo_paths [get_property ip_repo_paths [current_fileset]] 
-if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
-	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
-	update_ip_catalog
-}
-
-set design_name ""
-set all_bd {}
-set all_bd_files [get_files *.bd -quiet]
-foreach file $all_bd_files {
-set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
-set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
-lappend all_bd $bd_name
-}
-
-for { set i 1 } { 1 } { incr i } {
-	set design_name "myip_v1_0_hw_${i}"
-	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
-		break
-	}
-}
-
-set intf_address_include_file ""
-create_ipi_design intf_address_include_file ${design_name}
-save_bd_design
-validate_bd_design
-
-set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
-import_files -force -norecurse $wrapper_file
-
-puts "-------------------------------------------------------------------------------------------------"
-puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
-puts "   please perform following steps to test design in targeted board."
-puts "1. Generate bitstream"
-puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
-puts "3. Download generated bitstream"
-puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
-puts "   to every interface present in the peripheral : xilinx.com:user:myip:1.0"
-puts "   : source -notrace ${hw_test_file}"
-puts "-------------------------------------------------------------------------------------------------"
-

src/ip_repo/myip_1.0/example_designs/debug_hw_design/myip_v1_0_hw_test.tcl

@@ -1,45 +0,0 @@
-# Runtime Tcl commands to interact with - myip_v1_0
-
-# Sourcing design address info tcl
-set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
-source ${bd_path}/myip_v1_0_include.tcl
-
-# jtag axi master interface hardware name, change as per your design.
-set jtag_axi_master hw_axi_1
-set ec 0
-
-# hw test script
-# Delete all previous axis transactions
-if { [llength [get_hw_axi_txns -quiet]] } {
-	delete_hw_axi_txn [get_hw_axi_txns -quiet]
-}
-
-
-# Test all lite slaves.
-set wdata_1 abcd1234
-
-# Test: S00_AXI
-# Create a write transaction at s00_axi_addr address
-create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
-# Create a read transaction at s00_axi_addr address
-create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
-# Initiate transactions
-run_hw_axi r_s00_axi_addr
-run_hw_axi w_s00_axi_addr
-run_hw_axi r_s00_axi_addr
-set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
-# Compare read data
-if { $rdata_tmp == $wdata_1 } {
-	puts "Data comparison test pass for - S00_AXI"
-} else {
-	puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
-	inc ec
-}
-
-# Check error flag
-if { $ec == 0 } {
-	 puts "PTGEN_TEST: PASSED!" 
-} else {
-	 puts "PTGEN_TEST: FAILED!" 
-}
-

src/ip_repo/myip_1.0/hdl/myip_v1_0.vhd

@@ -1,118 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity myip_v1_0 is
-	generic (
-		-- Users to add parameters here
-
-		-- User parameters ends
-		-- Do not modify the parameters beyond this line
-
-
-		-- Parameters of Axi Slave Bus Interface S00_AXI
-		C_S00_AXI_DATA_WIDTH	: integer	:= 32;
-		C_S00_AXI_ADDR_WIDTH	: integer	:= 7
-	);
-	port (
-		-- Users to add ports here
-
-		-- User ports ends
-		-- Do not modify the ports beyond this line
-
-
-		-- Ports of Axi Slave Bus Interface S00_AXI
-		s00_axi_aclk	: in std_logic;
-		s00_axi_aresetn	: in std_logic;
-		s00_axi_awaddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
-		s00_axi_awprot	: in std_logic_vector(2 downto 0);
-		s00_axi_awvalid	: in std_logic;
-		s00_axi_awready	: out std_logic;
-		s00_axi_wdata	: in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
-		s00_axi_wstrb	: in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
-		s00_axi_wvalid	: in std_logic;
-		s00_axi_wready	: out std_logic;
-		s00_axi_bresp	: out std_logic_vector(1 downto 0);
-		s00_axi_bvalid	: out std_logic;
-		s00_axi_bready	: in std_logic;
-		s00_axi_araddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
-		s00_axi_arprot	: in std_logic_vector(2 downto 0);
-		s00_axi_arvalid	: in std_logic;
-		s00_axi_arready	: out std_logic;
-		s00_axi_rdata	: out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
-		s00_axi_rresp	: out std_logic_vector(1 downto 0);
-		s00_axi_rvalid	: out std_logic;
-		s00_axi_rready	: in std_logic
-	);
-end myip_v1_0;
-
-architecture arch_imp of myip_v1_0 is
-
-	-- component declaration
-	component myip_v1_0_S00_AXI is
-		generic (
-		C_S_AXI_DATA_WIDTH	: integer	:= 32;
-		C_S_AXI_ADDR_WIDTH	: integer	:= 7
-		);
-		port (
-		S_AXI_ACLK	: in std_logic;
-		S_AXI_ARESETN	: in std_logic;
-		S_AXI_AWADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		S_AXI_AWPROT	: in std_logic_vector(2 downto 0);
-		S_AXI_AWVALID	: in std_logic;
-		S_AXI_AWREADY	: out std_logic;
-		S_AXI_WDATA	: in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		S_AXI_WSTRB	: in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-		S_AXI_WVALID	: in std_logic;
-		S_AXI_WREADY	: out std_logic;
-		S_AXI_BRESP	: out std_logic_vector(1 downto 0);
-		S_AXI_BVALID	: out std_logic;
-		S_AXI_BREADY	: in std_logic;
-		S_AXI_ARADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		S_AXI_ARPROT	: in std_logic_vector(2 downto 0);
-		S_AXI_ARVALID	: in std_logic;
-		S_AXI_ARREADY	: out std_logic;
-		S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		S_AXI_RRESP	: out std_logic_vector(1 downto 0);
-		S_AXI_RVALID	: out std_logic;
-		S_AXI_RREADY	: in std_logic
-		);
-	end component myip_v1_0_S00_AXI;
-
-begin
-
--- Instantiation of Axi Bus Interface S00_AXI
-myip_v1_0_S00_AXI_inst : myip_v1_0_S00_AXI
-	generic map (
-		C_S_AXI_DATA_WIDTH	=> C_S00_AXI_DATA_WIDTH,
-		C_S_AXI_ADDR_WIDTH	=> C_S00_AXI_ADDR_WIDTH
-	)
-	port map (
-		S_AXI_ACLK	=> s00_axi_aclk,
-		S_AXI_ARESETN	=> s00_axi_aresetn,
-		S_AXI_AWADDR	=> s00_axi_awaddr,
-		S_AXI_AWPROT	=> s00_axi_awprot,
-		S_AXI_AWVALID	=> s00_axi_awvalid,
-		S_AXI_AWREADY	=> s00_axi_awready,
-		S_AXI_WDATA	=> s00_axi_wdata,
-		S_AXI_WSTRB	=> s00_axi_wstrb,
-		S_AXI_WVALID	=> s00_axi_wvalid,
-		S_AXI_WREADY	=> s00_axi_wready,
-		S_AXI_BRESP	=> s00_axi_bresp,
-		S_AXI_BVALID	=> s00_axi_bvalid,
-		S_AXI_BREADY	=> s00_axi_bready,
-		S_AXI_ARADDR	=> s00_axi_araddr,
-		S_AXI_ARPROT	=> s00_axi_arprot,
-		S_AXI_ARVALID	=> s00_axi_arvalid,
-		S_AXI_ARREADY	=> s00_axi_arready,
-		S_AXI_RDATA	=> s00_axi_rdata,
-		S_AXI_RRESP	=> s00_axi_rresp,
-		S_AXI_RVALID	=> s00_axi_rvalid,
-		S_AXI_RREADY	=> s00_axi_rready
-	);
-
-	-- Add user logic here
-
-	-- User logic ends
-
-end arch_imp;

src/ip_repo/myip_1.0/hdl/myip_v1_0_S00_AXI.vhd

@@ -1,755 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity myip_v1_0_S00_AXI is
-	generic (
-		-- Users to add parameters here
-
-		-- User parameters ends
-		-- Do not modify the parameters beyond this line
-
-		-- Width of S_AXI data bus
-		C_S_AXI_DATA_WIDTH	: integer	:= 32;
-		-- Width of S_AXI address bus
-		C_S_AXI_ADDR_WIDTH	: integer	:= 7
-	);
-	port (
-		-- Users to add ports here
-
-		-- User ports ends
-		-- Do not modify the ports beyond this line
-
-		-- Global Clock Signal
-		S_AXI_ACLK	: in std_logic;
-		-- Global Reset Signal. This Signal is Active LOW
-		S_AXI_ARESETN	: in std_logic;
-		-- Write address (issued by master, acceped by Slave)
-		S_AXI_AWADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		-- Write channel Protection type. This signal indicates the
-    		-- privilege and security level of the transaction, and whether
-    		-- the transaction is a data access or an instruction access.
-		S_AXI_AWPROT	: in std_logic_vector(2 downto 0);
-		-- Write address valid. This signal indicates that the master signaling
-    		-- valid write address and control information.
-		S_AXI_AWVALID	: in std_logic;
-		-- Write address ready. This signal indicates that the slave is ready
-    		-- to accept an address and associated control signals.
-		S_AXI_AWREADY	: out std_logic;
-		-- Write data (issued by master, acceped by Slave) 
-		S_AXI_WDATA	: in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		-- Write strobes. This signal indicates which byte lanes hold
-    		-- valid data. There is one write strobe bit for each eight
-    		-- bits of the write data bus.    
-		S_AXI_WSTRB	: in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-		-- Write valid. This signal indicates that valid write
-    		-- data and strobes are available.
-		S_AXI_WVALID	: in std_logic;
-		-- Write ready. This signal indicates that the slave
-    		-- can accept the write data.
-		S_AXI_WREADY	: out std_logic;
-		-- Write response. This signal indicates the status
-    		-- of the write transaction.
-		S_AXI_BRESP	: out std_logic_vector(1 downto 0);
-		-- Write response valid. This signal indicates that the channel
-    		-- is signaling a valid write response.
-		S_AXI_BVALID	: out std_logic;
-		-- Response ready. This signal indicates that the master
-    		-- can accept a write response.
-		S_AXI_BREADY	: in std_logic;
-		-- Read address (issued by master, acceped by Slave)
-		S_AXI_ARADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		-- Protection type. This signal indicates the privilege
-    		-- and security level of the transaction, and whether the
-    		-- transaction is a data access or an instruction access.
-		S_AXI_ARPROT	: in std_logic_vector(2 downto 0);
-		-- Read address valid. This signal indicates that the channel
-    		-- is signaling valid read address and control information.
-		S_AXI_ARVALID	: in std_logic;
-		-- Read address ready. This signal indicates that the slave is
-    		-- ready to accept an address and associated control signals.
-		S_AXI_ARREADY	: out std_logic;
-		-- Read data (issued by slave)
-		S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		-- Read response. This signal indicates the status of the
-    		-- read transfer.
-		S_AXI_RRESP	: out std_logic_vector(1 downto 0);
-		-- Read valid. This signal indicates that the channel is
-    		-- signaling the required read data.
-		S_AXI_RVALID	: out std_logic;
-		-- Read ready. This signal indicates that the master can
-    		-- accept the read data and response information.
-		S_AXI_RREADY	: in std_logic
-	);
-end myip_v1_0_S00_AXI;
-
-architecture arch_imp of myip_v1_0_S00_AXI is
-
-	-- AXI4LITE signals
-	signal axi_awaddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-	signal axi_awready	: std_logic;
-	signal axi_wready	: std_logic;
-	signal axi_bresp	: std_logic_vector(1 downto 0);
-	signal axi_bvalid	: std_logic;
-	signal axi_araddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-	signal axi_arready	: std_logic;
-	signal axi_rdata	: std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal axi_rresp	: std_logic_vector(1 downto 0);
-	signal axi_rvalid	: std_logic;
-
-	-- Example-specific design signals
-	-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-	-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-	-- ADDR_LSB = 2 for 32 bits (n downto 2)
-	-- ADDR_LSB = 3 for 64 bits (n downto 3)
-	constant ADDR_LSB  : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
-	constant OPT_MEM_ADDR_BITS : integer := 4;
-	------------------------------------------------
-	---- Signals for user logic register space example
-	--------------------------------------------------
-	---- Number of Slave Registers 32
-	signal slv_reg0	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg1	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg2	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg3	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg4	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg5	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg6	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg7	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg8	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg9	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg10	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg11	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg12	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg13	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg14	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg15	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg16	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg17	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg18	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg19	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg20	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg21	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg22	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg23	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg24	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg25	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg26	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg27	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg28	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg29	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg30	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg31	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg_rden	: std_logic;
-	signal slv_reg_wren	: std_logic;
-	signal reg_data_out	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal byte_index	: integer;
-	signal aw_en	: std_logic;
-
-begin
-	-- I/O Connections assignments
-
-	S_AXI_AWREADY	<= axi_awready;
-	S_AXI_WREADY	<= axi_wready;
-	S_AXI_BRESP	<= axi_bresp;
-	S_AXI_BVALID	<= axi_bvalid;
-	S_AXI_ARREADY	<= axi_arready;
-	S_AXI_RDATA	<= axi_rdata;
-	S_AXI_RRESP	<= axi_rresp;
-	S_AXI_RVALID	<= axi_rvalid;
-	-- Implement axi_awready generation
-	-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-	-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-	-- de-asserted when reset is low.
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_awready <= '0';
-	      aw_en <= '1';
-	    else
-	      if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-	        -- slave is ready to accept write address when
-	        -- there is a valid write address and write data
-	        -- on the write address and data bus. This design 
-	        -- expects no outstanding transactions. 
-	           axi_awready <= '1';
-	           aw_en <= '0';
-	        elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
-	           aw_en <= '1';
-	           axi_awready <= '0';
-	      else
-	        axi_awready <= '0';
-	      end if;
-	    end if;
-	  end if;
-	end process;
-
-	-- Implement axi_awaddr latching
-	-- This process is used to latch the address when both 
-	-- S_AXI_AWVALID and S_AXI_WVALID are valid. 
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_awaddr <= (others => '0');
-	    else
-	      if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-	        -- Write Address latching
-	        axi_awaddr <= S_AXI_AWADDR;
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement axi_wready generation
-	-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-	-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
-	-- de-asserted when reset is low. 
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_wready <= '0';
-	    else
-	      if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
-	          -- slave is ready to accept write data when 
-	          -- there is a valid write address and write data
-	          -- on the write address and data bus. This design 
-	          -- expects no outstanding transactions.           
-	          axi_wready <= '1';
-	      else
-	        axi_wready <= '0';
-	      end if;
-	    end if;
-	  end if;
-	end process; 
-
-	-- Implement memory mapped register select and write logic generation
-	-- The write data is accepted and written to memory mapped registers when
-	-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-	-- select byte enables of slave registers while writing.
-	-- These registers are cleared when reset (active low) is applied.
-	-- Slave register write enable is asserted when valid address and data are available
-	-- and the slave is ready to accept the write address and write data.
-	slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
-
-	process (S_AXI_ACLK)
-	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); 
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      slv_reg0 <= (others => '0');
-	      slv_reg1 <= (others => '0');
-	      slv_reg2 <= (others => '0');
-	      slv_reg3 <= (others => '0');
-	      slv_reg4 <= (others => '0');
-	      slv_reg5 <= (others => '0');
-	      slv_reg6 <= (others => '0');
-	      slv_reg7 <= (others => '0');
-	      slv_reg8 <= (others => '0');
-	      slv_reg9 <= (others => '0');
-	      slv_reg10 <= (others => '0');
-	      slv_reg11 <= (others => '0');
-	      slv_reg12 <= (others => '0');
-	      slv_reg13 <= (others => '0');
-	      slv_reg14 <= (others => '0');
-	      slv_reg15 <= (others => '0');
-	      slv_reg16 <= (others => '0');
-	      slv_reg17 <= (others => '0');
-	      slv_reg18 <= (others => '0');
-	      slv_reg19 <= (others => '0');
-	      slv_reg20 <= (others => '0');
-	      slv_reg21 <= (others => '0');
-	      slv_reg22 <= (others => '0');
-	      slv_reg23 <= (others => '0');
-	      slv_reg24 <= (others => '0');
-	      slv_reg25 <= (others => '0');
-	      slv_reg26 <= (others => '0');
-	      slv_reg27 <= (others => '0');
-	      slv_reg28 <= (others => '0');
-	      slv_reg29 <= (others => '0');
-	      slv_reg30 <= (others => '0');
-	      slv_reg31 <= (others => '0');
-	    else
-	      loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
-	      if (slv_reg_wren = '1') then
-	        case loc_addr is
-	          when b"00000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 0
-	                slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 1
-	                slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 2
-	                slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 3
-	                slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 4
-	                slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 5
-	                slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 6
-	                slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 7
-	                slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 8
-	                slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 9
-	                slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 10
-	                slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 11
-	                slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 12
-	                slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 13
-	                slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 14
-	                slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 15
-	                slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 16
-	                slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 17
-	                slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 18
-	                slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 19
-	                slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 20
-	                slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 21
-	                slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 22
-	                slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 23
-	                slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 24
-	                slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 25
-	                slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 26
-	                slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 27
-	                slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 28
-	                slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 29
-	                slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 30
-	                slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 31
-	                slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when others =>
-	            slv_reg0 <= slv_reg0;
-	            slv_reg1 <= slv_reg1;
-	            slv_reg2 <= slv_reg2;
-	            slv_reg3 <= slv_reg3;
-	            slv_reg4 <= slv_reg4;
-	            slv_reg5 <= slv_reg5;
-	            slv_reg6 <= slv_reg6;
-	            slv_reg7 <= slv_reg7;
-	            slv_reg8 <= slv_reg8;
-	            slv_reg9 <= slv_reg9;
-	            slv_reg10 <= slv_reg10;
-	            slv_reg11 <= slv_reg11;
-	            slv_reg12 <= slv_reg12;
-	            slv_reg13 <= slv_reg13;
-	            slv_reg14 <= slv_reg14;
-	            slv_reg15 <= slv_reg15;
-	            slv_reg16 <= slv_reg16;
-	            slv_reg17 <= slv_reg17;
-	            slv_reg18 <= slv_reg18;
-	            slv_reg19 <= slv_reg19;
-	            slv_reg20 <= slv_reg20;
-	            slv_reg21 <= slv_reg21;
-	            slv_reg22 <= slv_reg22;
-	            slv_reg23 <= slv_reg23;
-	            slv_reg24 <= slv_reg24;
-	            slv_reg25 <= slv_reg25;
-	            slv_reg26 <= slv_reg26;
-	            slv_reg27 <= slv_reg27;
-	            slv_reg28 <= slv_reg28;
-	            slv_reg29 <= slv_reg29;
-	            slv_reg30 <= slv_reg30;
-	            slv_reg31 <= slv_reg31;
-	        end case;
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement write response logic generation
-	-- The write response and response valid signals are asserted by the slave 
-	-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
-	-- This marks the acceptance of address and indicates the status of 
-	-- write transaction.
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_bvalid  <= '0';
-	      axi_bresp   <= "00"; --need to work more on the responses
-	    else
-	      if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0'  ) then
-	        axi_bvalid <= '1';
-	        axi_bresp  <= "00"; 
-	      elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then   --check if bready is asserted while bvalid is high)
-	        axi_bvalid <= '0';                                 -- (there is a possibility that bready is always asserted high)
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement axi_arready generation
-	-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-	-- S_AXI_ARVALID is asserted. axi_awready is 
-	-- de-asserted when reset (active low) is asserted. 
-	-- The read address is also latched when S_AXI_ARVALID is 
-	-- asserted. axi_araddr is reset to zero on reset assertion.
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_arready <= '0';
-	      axi_araddr  <= (others => '1');
-	    else
-	      if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-	        -- indicates that the slave has acceped the valid read address
-	        axi_arready <= '1';
-	        -- Read Address latching 
-	        axi_araddr  <= S_AXI_ARADDR;           
-	      else
-	        axi_arready <= '0';
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement axi_arvalid generation
-	-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
-	-- S_AXI_ARVALID and axi_arready are asserted. The slave registers 
-	-- data are available on the axi_rdata bus at this instance. The 
-	-- assertion of axi_rvalid marks the validity of read data on the 
-	-- bus and axi_rresp indicates the status of read transaction.axi_rvalid 
-	-- is deasserted on reset (active low). axi_rresp and axi_rdata are 
-	-- cleared to zero on reset (active low).  
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then
-	    if S_AXI_ARESETN = '0' then
-	      axi_rvalid <= '0';
-	      axi_rresp  <= "00";
-	    else
-	      if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-	        -- Valid read data is available at the read data bus
-	        axi_rvalid <= '1';
-	        axi_rresp  <= "00"; -- 'OKAY' response
-	      elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-	        -- Read data is accepted by the master
-	        axi_rvalid <= '0';
-	      end if;            
-	    end if;
-	  end if;
-	end process;
-
-	-- Implement memory mapped register select and read logic generation
-	-- Slave register read enable is asserted when valid address is available
-	-- and the slave is ready to accept the read address.
-	slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
-
-	process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
-	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
-	begin
-	    -- Address decoding for reading registers
-	    loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
-	    case loc_addr is
-	      when b"00000" =>
-	        reg_data_out <= slv_reg0;
-	      when b"00001" =>
-	        reg_data_out <= slv_reg1;
-	      when b"00010" =>
-	        reg_data_out <= slv_reg2;
-	      when b"00011" =>
-	        reg_data_out <= slv_reg3;
-	      when b"00100" =>
-	        reg_data_out <= slv_reg4;
-	      when b"00101" =>
-	        reg_data_out <= slv_reg5;
-	      when b"00110" =>
-	        reg_data_out <= slv_reg6;
-	      when b"00111" =>
-	        reg_data_out <= slv_reg7;
-	      when b"01000" =>
-	        reg_data_out <= slv_reg8;
-	      when b"01001" =>
-	        reg_data_out <= slv_reg9;
-	      when b"01010" =>
-	        reg_data_out <= slv_reg10;
-	      when b"01011" =>
-	        reg_data_out <= slv_reg11;
-	      when b"01100" =>
-	        reg_data_out <= slv_reg12;
-	      when b"01101" =>
-	        reg_data_out <= slv_reg13;
-	      when b"01110" =>
-	        reg_data_out <= slv_reg14;
-	      when b"01111" =>
-	        reg_data_out <= slv_reg15;
-	      when b"10000" =>
-	        reg_data_out <= slv_reg16;
-	      when b"10001" =>
-	        reg_data_out <= slv_reg17;
-	      when b"10010" =>
-	        reg_data_out <= slv_reg18;
-	      when b"10011" =>
-	        reg_data_out <= slv_reg19;
-	      when b"10100" =>
-	        reg_data_out <= slv_reg20;
-	      when b"10101" =>
-	        reg_data_out <= slv_reg21;
-	      when b"10110" =>
-	        reg_data_out <= slv_reg22;
-	      when b"10111" =>
-	        reg_data_out <= slv_reg23;
-	      when b"11000" =>
-	        reg_data_out <= slv_reg24;
-	      when b"11001" =>
-	        reg_data_out <= slv_reg25;
-	      when b"11010" =>
-	        reg_data_out <= slv_reg26;
-	      when b"11011" =>
-	        reg_data_out <= slv_reg27;
-	      when b"11100" =>
-	        reg_data_out <= slv_reg28;
-	      when b"11101" =>
-	        reg_data_out <= slv_reg29;
-	      when b"11110" =>
-	        reg_data_out <= slv_reg30;
-	      when b"11111" =>
-	        reg_data_out <= slv_reg31;
-	      when others =>
-	        reg_data_out  <= (others => '0');
-	    end case;
-	end process; 
-
-	-- Output register or memory read data
-	process( S_AXI_ACLK ) is
-	begin
-	  if (rising_edge (S_AXI_ACLK)) then
-	    if ( S_AXI_ARESETN = '0' ) then
-	      axi_rdata  <= (others => '0');
-	    else
-	      if (slv_reg_rden = '1') then
-	        -- When there is a valid read address (S_AXI_ARVALID) with 
-	        -- acceptance of read address by the slave (axi_arready), 
-	        -- output the read dada 
-	        -- Read address mux
-	          axi_rdata <= reg_data_out;     -- register read data
-	      end if;   
-	    end if;
-	  end if;
-	end process;
-
-
-	-- Add user logic here
-
-	-- User logic ends
-
-end arch_imp;

src/ip_repo/myip_1.0/xgui/myip_v1_0.tcl

@@ -1,62 +0,0 @@
-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
-  ipgui::add_param $IPINST -name "Component_Name"
-  #Adding Page
-  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
-  set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox]
-  set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH}
-  set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}]
-  set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH}
-  ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
-  ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
-
-
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
-	# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
-	# Procedure called to validate C_S00_AXI_DATA_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
-	# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
-	# Procedure called to validate C_S00_AXI_ADDR_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
-	# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
-	# Procedure called to validate C_S00_AXI_BASEADDR
-	return true
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
-	# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
-	# Procedure called to validate C_S00_AXI_HIGHADDR
-	return true
-}
-
-
-proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
-	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
-	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
-}
-

src/ip_repo/neuron_1.0/bd/bd.tcl

@@ -1,86 +0,0 @@
-
-proc init { cellpath otherInfo } {                                                                   
-                                                                                                             
-	set cell_handle [get_bd_cells $cellpath]                                                                 
-	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
-	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-	set full_sbusif_list [list  ]
-			                                                                                                 
-	foreach busif $all_busif {                                                                               
-		if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {                            
-			set busif_param_list [list]                                                                      
-			set busif_name [get_property NAME $busif]					                                     
-			if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {					         
-			    continue                                                                                     
-			}                                                                                                
-			foreach tparam $axi_standard_param_list {                                                        
-				lappend busif_param_list "C_${busif_name}_${tparam}"                                       
-			}                                                                                                
-			bd::mark_propagate_only $cell_handle $busif_param_list			                                 
-		}		                                                                                             
-	}                                                                                                        
-}
-
-
-proc pre_propagate {cellpath otherInfo } {                                                           
-                                                                                                             
-	set cell_handle [get_bd_cells $cellpath]                                                                 
-	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
-	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-	                                                                                                         
-	foreach busif $all_busif {	                                                                             
-		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
-			continue                                                                                         
-		}                                                                                                    
-		if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {                           
-			continue                                                                                         
-		}			                                                                                         
-		                                                                                                     
-		set busif_name [get_property NAME $busif]			                                                 
-		foreach tparam $axi_standard_param_list {		                                                     
-			set busif_param_name "C_${busif_name}_${tparam}"			                                     
-			                                                                                                 
-			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
-			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
-			                                                                                                 
-			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
-				if { $val_on_cell != "" } {                                                                  
-					set_property CONFIG.${tparam} $val_on_cell $busif                                        
-				}                                                                                            
-			}			                                                                                     
-		}		                                                                                             
-	}                                                                                                        
-}
-
-
-proc propagate {cellpath otherInfo } {                                                               
-                                                                                                             
-	set cell_handle [get_bd_cells $cellpath]                                                                 
-	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
-	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
-	                                                                                                         
-	foreach busif $all_busif {                                                                               
-		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
-			continue                                                                                         
-		}                                                                                                    
-		if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {                            
-			continue                                                                                         
-		}			                                                                                         
-	                                                                                                         
-		set busif_name [get_property NAME $busif]		                                                     
-		foreach tparam $axi_standard_param_list {			                                                 
-			set busif_param_name "C_${busif_name}_${tparam}"			                                     
-                                                                                                             
-			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
-			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
-			                                                                                                 
-			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
-				#override property of bd_interface_net to bd_cell -- only for slaves.  May check for supported values..
-				if { $val_on_cell_intf_pin != "" } {                                                         
-					set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle               
-				}                                                                                            
-			}                                                                                                
-		}		                                                                                             
-	}                                                                                                        
-}
-

src/ip_repo/neuron_1.0/component.xml

@@ -1,945 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-  <spirit:vendor>user.org</spirit:vendor>
-  <spirit:library>user</spirit:library>
-  <spirit:name>neuron</spirit:name>
-  <spirit:version>1.0</spirit:version>
-  <spirit:busInterfaces>
-    <spirit:busInterface>
-      <spirit:name>S00_AXI</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
-      <spirit:slave>
-        <spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
-      </spirit:slave>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWADDR</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awaddr</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWPROT</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awprot</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>AWREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_awready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WDATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wdata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WSTRB</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wstrb</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>WREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_wready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>BRESP</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_bresp</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>BVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_bvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>BREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_bready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARADDR</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_araddr</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARPROT</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_arprot</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_arvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>ARREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_arready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RDATA</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rdata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RRESP</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rresp</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RVALID</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rvalid</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RREADY</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_rready</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>WIZ_DATA_WIDTH</spirit:name>
-          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>WIZ_NUM_REG</spirit:name>
-          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
-          <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>S00_AXI_RST</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>RST</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_aresetn</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>POLARITY</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_RST.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>S00_AXI_CLK</spirit:name>
-      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
-      <spirit:slave/>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>CLK</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>s00_axi_aclk</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_BUSIF">S00_AXI</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>ASSOCIATED_RESET</spirit:name>
-          <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-  </spirit:busInterfaces>
-  <spirit:memoryMaps>
-    <spirit:memoryMap>
-      <spirit:name>S00_AXI</spirit:name>
-      <spirit:addressBlock>
-        <spirit:name>S00_AXI_reg</spirit:name>
-        <spirit:baseAddress spirit:format="long" spirit:resolve="user">0</spirit:baseAddress>
-        <spirit:range spirit:format="long">4096</spirit:range>
-        <spirit:width spirit:format="long">32</spirit:width>
-        <spirit:usage>register</spirit:usage>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>OFFSET_BASE_PARAM</spirit:name>
-            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_BASE_PARAM">C_S00_AXI_BASEADDR</spirit:value>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
-            <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_HIGH_PARAM">C_S00_AXI_HIGHADDR</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:addressBlock>
-    </spirit:memoryMap>
-  </spirit:memoryMaps>
-  <spirit:model>
-    <spirit:views>
-      <spirit:view>
-        <spirit:name>xilinx_vhdlsynthesis</spirit:name>
-        <spirit:displayName>VHDL Synthesis</spirit:displayName>
-        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
-        <spirit:language>vhdl</spirit:language>
-        <spirit:modelName>neuron_v1_0</spirit:modelName>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>11a4ae67</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
-        <spirit:displayName>VHDL Simulation</spirit:displayName>
-        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
-        <spirit:language>vhdl</spirit:language>
-        <spirit:modelName>neuron_v1_0</spirit:modelName>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>11a4ae67</spirit:value>
-          </spirit:parameter>
-        </spirit:parameters>
-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_softwaredriver</spirit:name>
-        <spirit:displayName>Software Driver</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:sw.driver</spirit:envIdentifier>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_softwaredriver_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
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-    <spirit:parameter>
-      <spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
-      <spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
-      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
-      <spirit:vendorExtensions>
-        <xilinx:parameterInfo>
-          <xilinx:enablement>
-            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_HIGHADDR">false</xilinx:isEnabled>
-          </xilinx:enablement>
-        </xilinx:parameterInfo>
-      </spirit:vendorExtensions>
-    </spirit:parameter>
-    <spirit:parameter>
-      <spirit:name>Component_Name</spirit:name>
-      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">neuron_v1_0</spirit:value>
-    </spirit:parameter>
-  </spirit:parameters>
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-        <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
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-      <xilinx:displayName>neuron_v1.0</xilinx:displayName>
-      <xilinx:coreRevision>6</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2019-05-29T08:46:29Z</xilinx:coreCreationDateTime>
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-      </xilinx:tags>
-    </xilinx:coreExtensions>
-    <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="0312d308"/>
-      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ed1368d5"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0c1d33f5"/>
-      <xilinx:checksum xilinx:scope="ports" xilinx:value="48e360dd"/>
-      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="a0a6f17f"/>
-      <xilinx:checksum xilinx:scope="parameters" xilinx:value="ae442535"/>
-    </xilinx:packagingInfo>
-  </spirit:vendorExtensions>
-</spirit:component>

src/ip_repo/neuron_1.0/drivers/neuron_v1_0/data/neuron.mdd

@@ -1,10 +0,0 @@
-
-
-OPTION psf_version = 2.1;
-
-BEGIN DRIVER neuron
-	OPTION supported_peripherals = (neuron);
-	OPTION copyfiles = all;
-	OPTION VERSION = 1.0;
-	OPTION NAME = neuron;
-END DRIVER

src/ip_repo/neuron_1.0/drivers/neuron_v1_0/data/neuron.tcl

@@ -1,5 +0,0 @@
-
-
-proc generate {drv_handle} {
-	xdefine_include_file $drv_handle "xparameters.h" "neuron" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
-}

src/ip_repo/neuron_1.0/drivers/neuron_v1_0/src/Makefile

@@ -1,26 +0,0 @@
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-LIBSOURCES=*.c
-OUTS = *.o
-
-libs:
-	echo "Compiling neuron..."
-	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
-	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
-	make clean
-
-include:
-	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
-	rm -rf ${OUTS}

src/ip_repo/neuron_1.0/drivers/neuron_v1_0/src/neuron.c

@@ -1,6 +0,0 @@
-
-
-/***************************** Include Files *******************************/
-#include "neuron.h"
-
-/************************** Function Definitions ***************************/

src/ip_repo/neuron_1.0/drivers/neuron_v1_0/src/neuron.h

@@ -1,107 +0,0 @@
-
-#ifndef NEURON_H
-#define NEURON_H
-
-
-/****************** Include Files ********************/
-#include "xil_types.h"
-#include "xstatus.h"
-
-#define NEURON_S00_AXI_SLV_REG0_OFFSET 0
-#define NEURON_S00_AXI_SLV_REG1_OFFSET 4
-#define NEURON_S00_AXI_SLV_REG2_OFFSET 8
-#define NEURON_S00_AXI_SLV_REG3_OFFSET 12
-#define NEURON_S00_AXI_SLV_REG4_OFFSET 16
-#define NEURON_S00_AXI_SLV_REG5_OFFSET 20
-#define NEURON_S00_AXI_SLV_REG6_OFFSET 24
-#define NEURON_S00_AXI_SLV_REG7_OFFSET 28
-#define NEURON_S00_AXI_SLV_REG8_OFFSET 32
-#define NEURON_S00_AXI_SLV_REG9_OFFSET 36
-#define NEURON_S00_AXI_SLV_REG10_OFFSET 40
-#define NEURON_S00_AXI_SLV_REG11_OFFSET 44
-#define NEURON_S00_AXI_SLV_REG12_OFFSET 48
-#define NEURON_S00_AXI_SLV_REG13_OFFSET 52
-#define NEURON_S00_AXI_SLV_REG14_OFFSET 56
-#define NEURON_S00_AXI_SLV_REG15_OFFSET 60
-#define NEURON_S00_AXI_SLV_REG16_OFFSET 64
-#define NEURON_S00_AXI_SLV_REG17_OFFSET 68
-#define NEURON_S00_AXI_SLV_REG18_OFFSET 72
-#define NEURON_S00_AXI_SLV_REG19_OFFSET 76
-#define NEURON_S00_AXI_SLV_REG20_OFFSET 80
-#define NEURON_S00_AXI_SLV_REG21_OFFSET 84
-#define NEURON_S00_AXI_SLV_REG22_OFFSET 88
-#define NEURON_S00_AXI_SLV_REG23_OFFSET 92
-#define NEURON_S00_AXI_SLV_REG24_OFFSET 96
-#define NEURON_S00_AXI_SLV_REG25_OFFSET 100
-#define NEURON_S00_AXI_SLV_REG26_OFFSET 104
-#define NEURON_S00_AXI_SLV_REG27_OFFSET 108
-#define NEURON_S00_AXI_SLV_REG28_OFFSET 112
-#define NEURON_S00_AXI_SLV_REG29_OFFSET 116
-#define NEURON_S00_AXI_SLV_REG30_OFFSET 120
-#define NEURON_S00_AXI_SLV_REG31_OFFSET 124
-
-
-/**************************** Type Definitions *****************************/
-/**
- *
- * Write a value to a NEURON register. A 32 bit write is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is written.
- *
- * @param   BaseAddress is the base address of the NEURONdevice.
- * @param   RegOffset is the register offset from the base to write to.
- * @param   Data is the data written to the register.
- *
- * @return  None.
- *
- * @note
- * C-style signature:
- * 	void NEURON_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
- *
- */
-#define NEURON_mWriteReg(BaseAddress, RegOffset, Data) \
-  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/**
- *
- * Read a value from a NEURON register. A 32 bit read is performed.
- * If the component is implemented in a smaller width, only the least
- * significant data is read from the register. The most significant data
- * will be read as 0.
- *
- * @param   BaseAddress is the base address of the NEURON device.
- * @param   RegOffset is the register offset from the base to write to.
- *
- * @return  Data is the data from the register.
- *
- * @note
- * C-style signature:
- * 	u32 NEURON_mReadReg(u32 BaseAddress, unsigned RegOffset)
- *
- */
-#define NEURON_mReadReg(BaseAddress, RegOffset) \
-    Xil_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ****************************/
-/**
- *
- * Run a self-test on the driver/device. Note this may be a destructive test if
- * resets of the device are performed.
- *
- * If the hardware system is not built correctly, this function may never
- * return to the caller.
- *
- * @param   baseaddr_p is the base address of the NEURON instance to be worked on.
- *
- * @return
- *
- *    - XST_SUCCESS   if all self-test code passed
- *    - XST_FAILURE   if any self-test code failed
- *
- * @note    Caching must be turned off for this function to work.
- * @note    Self test may fail if data memory and device are not on the same bus.
- *
- */
-XStatus NEURON_Reg_SelfTest(void * baseaddr_p);
-
-#endif // NEURON_H

src/ip_repo/neuron_1.0/drivers/neuron_v1_0/src/neuron_selftest.c

@@ -1,60 +0,0 @@
-
-/***************************** Include Files *******************************/
-#include "neuron.h"
-#include "xparameters.h"
-#include "stdio.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ***************************/
-#define READ_WRITE_MUL_FACTOR 0x10
-
-/************************** Function Definitions ***************************/
-/**
- *
- * Run a self-test on the driver/device. Note this may be a destructive test if
- * resets of the device are performed.
- *
- * If the hardware system is not built correctly, this function may never
- * return to the caller.
- *
- * @param   baseaddr_p is the base address of the NEURONinstance to be worked on.
- *
- * @return
- *
- *    - XST_SUCCESS   if all self-test code passed
- *    - XST_FAILURE   if any self-test code failed
- *
- * @note    Caching must be turned off for this function to work.
- * @note    Self test may fail if data memory and device are not on the same bus.
- *
- */
-XStatus NEURON_Reg_SelfTest(void * baseaddr_p)
-{
-	u32 baseaddr;
-	int write_loop_index;
-	int read_loop_index;
-	int Index;
-
-	baseaddr = (u32) baseaddr_p;
-
-	xil_printf("******************************\n\r");
-	xil_printf("* User Peripheral Self Test\n\r");
-	xil_printf("******************************\n\n\r");
-
-	/*
-	 * Write to user logic slave module register(s) and read back
-	 */
-	xil_printf("User logic slave module test...\n\r");
-
-	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
-	  NEURON_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
-	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
-	  if ( NEURON_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
-	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
-	    return XST_FAILURE;
-	  }
-
-	xil_printf("   - slave register write/read passed\n\n\r");
-
-	return XST_SUCCESS;
-}

src/ip_repo/neuron_1.0/example_designs/bfm_design/design.tcl

@@ -1,88 +0,0 @@
-proc create_ipi_design { offsetfile design_name } {
-	create_bd_design $design_name
-	open_bd_design $design_name
-
-	# Create Clock and Reset Ports
-	set ACLK [ create_bd_port -dir I -type clk ACLK ]
-	set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
-	set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
-	set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $ARESETN
-	set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
-
-	# Create instance: neuron_0, and set properties
-	set neuron_0 [ create_bd_cell -type ip -vlnv user.org:user:neuron:1.0 neuron_0]
-
-	# Create instance: master_0, and set properties
-	set master_0 [ create_bd_cell -type ip -vlnv  xilinx.com:ip:axi_vip master_0]
-	set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
-
-	# Create interface connections
-	connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins neuron_0/S00_AXI]
-
-	# Create port connections
-	connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins neuron_0/S00_AXI_ACLK]
-	connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins neuron_0/S00_AXI_ARESETN]
-set_property target_simulator XSim [current_project]
-set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
-
-	# Auto assign address
-	assign_bd_address
-
-	# Copy all address to interface_address.vh file
-	set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
-	upvar 1 $offsetfile offset_file
-	set offset_file "${bd_path}/neuron_v1_0_tb_include.svh"
-	set fp [open $offset_file "w"]
-	puts $fp "`ifndef neuron_v1_0_tb_include_vh_"
-	puts $fp "`define neuron_v1_0_tb_include_vh_\n"
-	puts $fp "//Configuration current bd names"
-	puts $fp "`define BD_NAME ${design_name}"
-	puts $fp "`define BD_INST_NAME ${design_name}_i"
-	puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
-	puts $fp "//Configuration address parameters"
-
-	puts $fp "`endif"
-	close $fp
-}
-
-set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:neuron:1.0]]]]
-set test_bench_file ${ip_path}/example_designs/bfm_design/neuron_v1_0_tb.sv
-set interface_address_vh_file ""
-
-# Set IP Repository and Update IP Catalogue 
-set repo_paths [get_property ip_repo_paths [current_fileset]] 
-if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
-	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
-	update_ip_catalog
-}
-
-set design_name ""
-set all_bd {}
-set all_bd_files [get_files *.bd -quiet]
-foreach file $all_bd_files {
-set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
-set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
-lappend all_bd $bd_name
-}
-
-for { set i 1 } { 1 } { incr i } {
-	set design_name "neuron_v1_0_bfm_${i}"
-	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
-		break
-	}
-}
-
-create_ipi_design interface_address_vh_file ${design_name}
-validate_bd_design
-
-set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
-import_files -force -norecurse $wrapper_file
-
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
-import_files -fileset sim_1 -norecurse -force $test_bench_file
-remove_files -quiet -fileset sim_1 neuron_v1_0_tb_include.vh
-import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
-set_property top neuron_v1_0_tb [get_filesets sim_1]
-set_property top_lib {} [get_filesets sim_1]
-set_property top_file {} [get_filesets sim_1]
-launch_simulation -simset sim_1 -mode behavioral

src/ip_repo/neuron_1.0/example_designs/bfm_design/neuron_v1_0_tb.sv

@@ -1,197 +0,0 @@
-
-`timescale 1ns / 1ps
-`include "neuron_v1_0_tb_include.svh"
-
-import axi_vip_pkg::*;
-import neuron_v1_0_bfm_1_master_0_0_pkg::*;
-
-module neuron_v1_0_tb();
-
-
-xil_axi_uint                            error_cnt = 0;
-xil_axi_uint                            comparison_cnt = 0;
-axi_transaction                         wr_transaction;   
-axi_transaction                         rd_transaction;   
-axi_monitor_transaction                 mst_monitor_transaction;  
-axi_monitor_transaction                 master_moniter_transaction_queue[$];  
-xil_axi_uint                            master_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 mst_scb_transaction;  
-axi_monitor_transaction                 passthrough_monitor_transaction;  
-axi_monitor_transaction                 passthrough_master_moniter_transaction_queue[$];  
-xil_axi_uint                            passthrough_master_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 passthrough_mst_scb_transaction;  
-axi_monitor_transaction                 passthrough_slave_moniter_transaction_queue[$];  
-xil_axi_uint                            passthrough_slave_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 passthrough_slv_scb_transaction;  
-axi_monitor_transaction                 slv_monitor_transaction;  
-axi_monitor_transaction                 slave_moniter_transaction_queue[$];  
-xil_axi_uint                            slave_moniter_transaction_queue_size =0;  
-axi_monitor_transaction                 slv_scb_transaction;  
-xil_axi_uint                           mst_agent_verbosity = 0;  
-xil_axi_uint                           slv_agent_verbosity = 0;  
-xil_axi_uint                           passthrough_agent_verbosity = 0;  
-bit                                     clock;
-bit                                     reset;
-integer result_slave;  
-bit [31:0] S00_AXI_test_data[3:0]; 
- localparam LC_AXI_BURST_LENGTH = 8; 
- localparam LC_AXI_DATA_WIDTH = 32; 
-task automatic COMPARE_DATA; 
-  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected; 
-  input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual; 
-  begin 
-    if (expected === 'hx || actual === 'hx) begin 
-      $display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); 
- result_slave = 0;    $stop; 
-  end 
-  if (actual != expected) begin 
-    $display("TESTBENCH ERROR! Data expected is not equal to actual.",     " expected = 0x%h",expected,     " actual   = 0x%h",actual); 
-    result_slave = 0; 
-    $stop; 
-  end 
-  else  
-    begin 
-     $display("TESTBENCH Passed! Data expected is equal to actual.", 
-              " expected = 0x%h",expected,               " actual   = 0x%h",actual); 
-    end 
-  end 
-endtask 
-integer                                 i; 
-integer                                 j;  
-xil_axi_uint                            trans_cnt_before_switch = 48;  
-xil_axi_uint                            passthrough_cmd_switch_cnt = 0;  
-event                                   passthrough_mastermode_start_event;  
-event                                   passthrough_mastermode_end_event;  
-event                                   passthrough_slavemode_end_event;  
-xil_axi_uint                            mtestID;  
-xil_axi_ulong                           mtestADDR;  
-xil_axi_len_t                           mtestBurstLength;  
-xil_axi_size_t                          mtestDataSize;   
-xil_axi_burst_t                         mtestBurstType;   
-xil_axi_lock_t                          mtestLOCK;  
-xil_axi_cache_t                         mtestCacheType = 0;  
-xil_axi_prot_t                          mtestProtectionType = 3'b000;  
-xil_axi_region_t                        mtestRegion = 4'b000;  
-xil_axi_qos_t                           mtestQOS = 4'b000;  
-xil_axi_data_beat                       dbeat;  
-xil_axi_data_beat [255:0]               mtestWUSER;   
-xil_axi_data_beat                       mtestAWUSER = 'h0;  
-xil_axi_data_beat                       mtestARUSER = 0;  
-xil_axi_data_beat [255:0]               mtestRUSER;      
-xil_axi_uint                            mtestBUSER = 0;  
-xil_axi_resp_t                          mtestBresp;  
-xil_axi_resp_t[255:0]                   mtestRresp;  
-bit [63:0]                              mtestWDataL; 
-bit [63:0]                              mtestRDataL; 
-axi_transaction                         pss_wr_transaction;   
-axi_transaction                         pss_rd_transaction;   
-axi_transaction                         reactive_transaction;   
-axi_transaction                         rd_payload_transaction;  
-axi_transaction                         wr_rand;  
-axi_transaction                         rd_rand;  
-axi_transaction                         wr_reactive;  
-axi_transaction                         rd_reactive;  
-axi_transaction                         wr_reactive2;   
-axi_transaction                         rd_reactive2;  
-axi_ready_gen                           bready_gen;  
-axi_ready_gen                           rready_gen;  
-axi_ready_gen                           awready_gen;  
-axi_ready_gen                           wready_gen;  
-axi_ready_gen                           arready_gen;  
-axi_ready_gen                           bready_gen2;  
-axi_ready_gen                           rready_gen2;  
-axi_ready_gen                           awready_gen2;  
-axi_ready_gen                           wready_gen2;  
-axi_ready_gen                           arready_gen2;  
-xil_axi_payload_byte                    data_mem[xil_axi_ulong];  
-neuron_v1_0_bfm_1_master_0_0_mst_t          mst_agent_0;
-
-  `BD_WRAPPER DUT(
-      .ARESETN(reset), 
-      .ACLK(clock) 
-    ); 
-  
-initial begin
-     mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms  
-   mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE); 
-   mst_agent_0.set_agent_tag("Master VIP"); 
-   mst_agent_0.set_verbosity(mst_agent_verbosity); 
-   mst_agent_0.start_master(); 
-     $timeformat (-12, 1, " ps", 1);
-  end
-  initial begin
-    reset <= 1'b0;
-    #200ns;
-    reset <= 1'b1;
-    repeat (5) @(negedge clock); 
-  end
-  always #5 clock <= ~clock;
-  initial begin
-      S_AXI_TEST ( );
-
-      #1ns;
-      $finish;
-  end
-task automatic S_AXI_TEST;  
-begin   
-#1; 
-   $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method starts"); 
-   mtestID = 0; 
-   mtestADDR = 64'h00000000; 
-   mtestBurstLength = 0; 
-   mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
-   mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
-   mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
-   mtestCacheType = 0;  
-   mtestProtectionType = 0;  
-   mtestRegion = 0; 
-   mtestQOS = 0; 
-   result_slave = 1; 
-  mtestWDataL[31:0] = 32'h00000001; 
-  for(int i = 0; i < 4;i++) begin 
-  S00_AXI_test_data[i] <= mtestWDataL[31:0];   
-  mst_agent_0.AXI4LITE_WRITE_BURST( 
-  mtestADDR, 
-  mtestProtectionType, 
-  mtestWDataL, 
-  mtestBresp 
-  );   
-  mtestWDataL[31:0] = mtestWDataL[31:0] + 1; 
-  mtestADDR = mtestADDR + 64'h4; 
-  end 
-     $display("Sequential write transfers example similar to  AXI BFM WRITE_BURST method completes"); 
-     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method starts"); 
-     mtestID = 0; 
-     mtestADDR = 64'h00000000; 
-     mtestBurstLength = 0; 
-     mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); 
-     mtestBurstType = XIL_AXI_BURST_TYPE_INCR;  
-     mtestLOCK = XIL_AXI_ALOCK_NOLOCK;  
-     mtestCacheType = 0;  
-     mtestProtectionType = 0;  
-     mtestRegion = 0; 
-     mtestQOS = 0; 
- for(int i = 0; i < 4;i++) begin 
-   mst_agent_0.AXI4LITE_READ_BURST( 
-        mtestADDR, 
-        mtestProtectionType, 
-        mtestRDataL, 
-        mtestRresp 
-      ); 
-   mtestADDR = mtestADDR + 64'h4; 
-   COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL); 
- end 
-     $display("Sequential read transfers example similar to  AXI BFM READ_BURST method completes"); 
-     $display("Sequential read transfers example similar to  AXI VIP READ_BURST method completes"); 
-     $display("---------------------------------------------------------"); 
-     $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); 
-     if ( result_slave ) begin                    
-       $display("PTGEN_TEST: PASSED!");                  
-     end    else begin                                       
-       $display("PTGEN_TEST: FAILED!");                  
-     end                                
-     $display("---------------------------------------------------------"); 
-  end 
-endtask  
-
-endmodule

src/ip_repo/neuron_1.0/example_designs/debug_hw_design/design.tcl

@@ -1,118 +0,0 @@
-
-proc create_ipi_design { offsetfile design_name } {
-
-	create_bd_design $design_name
-	open_bd_design $design_name
-
-	# Create and configure Clock/Reset
-	create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
-	create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
-
-	#Constraints will be provided manually while pin planning.
-		create_bd_port -dir I -type rst reset_rtl
-		set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
-		connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
-		connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
-		set external_reset_port reset_rtl
-		create_bd_port -dir I -type clk clock_rtl
-		connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
-		set external_clock_port clock_rtl
-	
-	#Avoid IPI DRC, make clock port synchronous to reset
-	if { $external_clock_port ne "" && $external_reset_port ne "" } {
-		set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
-	}
-
-	# Connect other sys_reset pins
-	connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
-
-	# Create instance: neuron_0, and set properties
-	set neuron_0 [ create_bd_cell -type ip -vlnv user.org:user:neuron:1.0 neuron_0 ]
-
-	# Create instance: jtag_axi_0, and set properties
-	set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
-	set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
-	connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
-	# Create instance: axi_peri_interconnect, and set properties
-	set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
-	set_property -dict [ list CONFIG.NUM_SI {1}  ] $axi_peri_interconnect
-	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
-	connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
-
-	set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
-	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
-	# Connect all clock & reset of neuron_0 slave interfaces..
-	connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins neuron_0/S00_AXI]
-	connect_bd_net [get_bd_pins neuron_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
-	connect_bd_net [get_bd_pins neuron_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
-
-
-	# Auto assign address
-	assign_bd_address
-
-	# Copy all address to neuron_v1_0_include.tcl file
-	set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
-	upvar 1 $offsetfile offset_file
-	set offset_file "${bd_path}/neuron_v1_0_include.tcl"
-	set fp [open $offset_file "w"]
-	puts $fp "# Configuration address parameters"
-
-	set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_neuron_0_S00_AXI_* ]]
-	puts $fp "set s00_axi_addr ${offset}"
-
-	close $fp
-}
-
-# Set IP Repository and Update IP Catalogue 
-set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:neuron:1.0]]]]
-set hw_test_file ${ip_path}/example_designs/debug_hw_design/neuron_v1_0_hw_test.tcl
-
-set repo_paths [get_property ip_repo_paths [current_fileset]] 
-if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
-	set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
-	update_ip_catalog
-}
-
-set design_name ""
-set all_bd {}
-set all_bd_files [get_files *.bd -quiet]
-foreach file $all_bd_files {
-set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
-set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
-lappend all_bd $bd_name
-}
-
-for { set i 1 } { 1 } { incr i } {
-	set design_name "neuron_v1_0_hw_${i}"
-	if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
-		break
-	}
-}
-
-set intf_address_include_file ""
-create_ipi_design intf_address_include_file ${design_name}
-save_bd_design
-validate_bd_design
-
-set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
-import_files -force -norecurse $wrapper_file
-
-puts "-------------------------------------------------------------------------------------------------"
-puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
-puts "   please perform following steps to test design in targeted board."
-puts "1. Generate bitstream"
-puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
-puts "3. Download generated bitstream"
-puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
-puts "   to every interface present in the peripheral : xilinx.com:user:myip:1.0"
-puts "   : source -notrace ${hw_test_file}"
-puts "-------------------------------------------------------------------------------------------------"
-

src/ip_repo/neuron_1.0/example_designs/debug_hw_design/neuron_v1_0_hw_test.tcl

@@ -1,45 +0,0 @@
-# Runtime Tcl commands to interact with - neuron_v1_0
-
-# Sourcing design address info tcl
-set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
-source ${bd_path}/neuron_v1_0_include.tcl
-
-# jtag axi master interface hardware name, change as per your design.
-set jtag_axi_master hw_axi_1
-set ec 0
-
-# hw test script
-# Delete all previous axis transactions
-if { [llength [get_hw_axi_txns -quiet]] } {
-	delete_hw_axi_txn [get_hw_axi_txns -quiet]
-}
-
-
-# Test all lite slaves.
-set wdata_1 abcd1234
-
-# Test: S00_AXI
-# Create a write transaction at s00_axi_addr address
-create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
-# Create a read transaction at s00_axi_addr address
-create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
-# Initiate transactions
-run_hw_axi r_s00_axi_addr
-run_hw_axi w_s00_axi_addr
-run_hw_axi r_s00_axi_addr
-set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
-# Compare read data
-if { $rdata_tmp == $wdata_1 } {
-	puts "Data comparison test pass for - S00_AXI"
-} else {
-	puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
-	inc ec
-}
-
-# Check error flag
-if { $ec == 0 } {
-	 puts "PTGEN_TEST: PASSED!" 
-} else {
-	 puts "PTGEN_TEST: FAILED!" 
-}
-

src/ip_repo/neuron_1.0/hdl/neuron_v1_0.vhd

@@ -1,117 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity neuron_v1_0 is
-	generic (
-		-- Users to add parameters here
-
-		-- User parameters ends
-		-- Do not modify the parameters beyond this line
-
-
-		-- Parameters of Axi Slave Bus Interface S00_AXI
-		C_S00_AXI_DATA_WIDTH	: integer	:= 32;
-		C_S00_AXI_ADDR_WIDTH	: integer	:= 7
-	);
-	port (
-		-- Users to add ports here
-
-		-- User ports ends
-		-- Do not modify the ports beyond this line
-
-
-		-- Ports of Axi Slave Bus Interface S00_AXI
-		s00_axi_aclk	: in std_logic;
-		s00_axi_aresetn	: in std_logic;
-		s00_axi_awaddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
-		s00_axi_awprot	: in std_logic_vector(2 downto 0);
-		s00_axi_awvalid	: in std_logic;
-		s00_axi_awready	: out std_logic;
-		s00_axi_wdata	: in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
-		s00_axi_wstrb	: in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
-		s00_axi_wvalid	: in std_logic;
-		s00_axi_wready	: out std_logic;
-		s00_axi_bresp	: out std_logic_vector(1 downto 0);
-		s00_axi_bvalid	: out std_logic;
-		s00_axi_bready	: in std_logic;
-		s00_axi_araddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
-		s00_axi_arprot	: in std_logic_vector(2 downto 0);
-		s00_axi_arvalid	: in std_logic;
-		s00_axi_arready	: out std_logic;
-		s00_axi_rdata	: out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
-		s00_axi_rresp	: out std_logic_vector(1 downto 0);
-		s00_axi_rvalid	: out std_logic;
-		s00_axi_rready	: in std_logic
-	);
-end neuron_v1_0;
-
-architecture arch_imp of neuron_v1_0 is
-
-	-- component declaration
-	component neuron_v1_0_S00_AXI is
-		generic (
-		C_S_AXI_DATA_WIDTH	: integer	:= 32;
-		C_S_AXI_ADDR_WIDTH	: integer	:= 7
-		);
-		port (
-		S_AXI_ACLK	: in std_logic;
-		S_AXI_ARESETN	: in std_logic;
-		S_AXI_AWADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		S_AXI_AWPROT	: in std_logic_vector(2 downto 0);
-		S_AXI_AWVALID	: in std_logic;
-		S_AXI_AWREADY	: out std_logic;
-		S_AXI_WDATA	: in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		S_AXI_WSTRB	: in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-		S_AXI_WVALID	: in std_logic;
-		S_AXI_WREADY	: out std_logic;
-		S_AXI_BRESP	: out std_logic_vector(1 downto 0);
-		S_AXI_BVALID	: out std_logic;
-		S_AXI_BREADY	: in std_logic;
-		S_AXI_ARADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		S_AXI_ARPROT	: in std_logic_vector(2 downto 0);
-		S_AXI_ARVALID	: in std_logic;
-		S_AXI_ARREADY	: out std_logic;
-		S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		S_AXI_RRESP	: out std_logic_vector(1 downto 0);
-		S_AXI_RVALID	: out std_logic;
-		S_AXI_RREADY	: in std_logic
-		);
-	end component neuron_v1_0_S00_AXI;
-
-begin
-
--- Instantiation of Axi Bus Interface S00_AXI
-neuron_v1_0_S00_AXI_inst : neuron_v1_0_S00_AXI
-	generic map (
-		C_S_AXI_DATA_WIDTH	=> C_S00_AXI_DATA_WIDTH,
-		C_S_AXI_ADDR_WIDTH	=> C_S00_AXI_ADDR_WIDTH
-	)
-	port map (
-		S_AXI_ACLK	=> s00_axi_aclk,
-		S_AXI_ARESETN	=> s00_axi_aresetn,
-		S_AXI_AWADDR	=> s00_axi_awaddr,
-		S_AXI_AWPROT	=> s00_axi_awprot,
-		S_AXI_AWVALID	=> s00_axi_awvalid,
-		S_AXI_AWREADY	=> s00_axi_awready,
-		S_AXI_WDATA	=> s00_axi_wdata,
-		S_AXI_WSTRB	=> s00_axi_wstrb,
-		S_AXI_WVALID	=> s00_axi_wvalid,
-		S_AXI_WREADY	=> s00_axi_wready,
-		S_AXI_BRESP	=> s00_axi_bresp,
-		S_AXI_BVALID	=> s00_axi_bvalid,
-		S_AXI_BREADY	=> s00_axi_bready,
-		S_AXI_ARADDR	=> s00_axi_araddr,
-		S_AXI_ARPROT	=> s00_axi_arprot,
-		S_AXI_ARVALID	=> s00_axi_arvalid,
-		S_AXI_ARREADY	=> s00_axi_arready,
-		S_AXI_RDATA	=> s00_axi_rdata,
-		S_AXI_RRESP	=> s00_axi_rresp,
-		S_AXI_RVALID	=> s00_axi_rvalid,
-		S_AXI_RREADY	=> s00_axi_rready
-	);
-
-	-- Add user logic here
-	-- User logic ends
-
-end arch_imp;

src/ip_repo/neuron_1.0/hdl/neuron_v1_0_S00_AXI.vhd

@@ -1,812 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.myPackage.ALL;
-
-entity neuron_v1_0_S00_AXI is
-	generic (
-		-- Users to add parameters here
-
-		-- User parameters ends
-		-- Do not modify the parameters beyond this line
-
-		-- Width of S_AXI data bus
-		C_S_AXI_DATA_WIDTH	: integer	:= 32;
-		-- Width of S_AXI address bus
-		C_S_AXI_ADDR_WIDTH	: integer	:= 7
-	);
-	port (
-		-- Users to add ports here
-
-		-- User ports ends
-		-- Do not modify the ports beyond this line
-
-		-- Global Clock Signal
-		S_AXI_ACLK	: in std_logic;
-		-- Global Reset Signal. This Signal is Active LOW
-		S_AXI_ARESETN	: in std_logic;
-		-- Write address (issued by master, acceped by Slave)
-		S_AXI_AWADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		-- Write channel Protection type. This signal indicates the
-    		-- privilege and security level of the transaction, and whether
-    		-- the transaction is a data access or an instruction access.
-		S_AXI_AWPROT	: in std_logic_vector(2 downto 0);
-		-- Write address valid. This signal indicates that the master signaling
-    		-- valid write address and control information.
-		S_AXI_AWVALID	: in std_logic;
-		-- Write address ready. This signal indicates that the slave is ready
-    		-- to accept an address and associated control signals.
-		S_AXI_AWREADY	: out std_logic;
-		-- Write data (issued by master, acceped by Slave) 
-		S_AXI_WDATA	: in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		-- Write strobes. This signal indicates which byte lanes hold
-    		-- valid data. There is one write strobe bit for each eight
-    		-- bits of the write data bus.    
-		S_AXI_WSTRB	: in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-		-- Write valid. This signal indicates that valid write
-    		-- data and strobes are available.
-		S_AXI_WVALID	: in std_logic;
-		-- Write ready. This signal indicates that the slave
-    		-- can accept the write data.
-		S_AXI_WREADY	: out std_logic;
-		-- Write response. This signal indicates the status
-    		-- of the write transaction.
-		S_AXI_BRESP	: out std_logic_vector(1 downto 0);
-		-- Write response valid. This signal indicates that the channel
-    		-- is signaling a valid write response.
-		S_AXI_BVALID	: out std_logic;
-		-- Response ready. This signal indicates that the master
-    		-- can accept a write response.
-		S_AXI_BREADY	: in std_logic;
-		-- Read address (issued by master, acceped by Slave)
-		S_AXI_ARADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-		-- Protection type. This signal indicates the privilege
-    		-- and security level of the transaction, and whether the
-    		-- transaction is a data access or an instruction access.
-		S_AXI_ARPROT	: in std_logic_vector(2 downto 0);
-		-- Read address valid. This signal indicates that the channel
-    		-- is signaling valid read address and control information.
-		S_AXI_ARVALID	: in std_logic;
-		-- Read address ready. This signal indicates that the slave is
-    		-- ready to accept an address and associated control signals.
-		S_AXI_ARREADY	: out std_logic;
-		-- Read data (issued by slave)
-		S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-		-- Read response. This signal indicates the status of the
-    		-- read transfer.
-		S_AXI_RRESP	: out std_logic_vector(1 downto 0);
-		-- Read valid. This signal indicates that the channel is
-    		-- signaling the required read data.
-		S_AXI_RVALID	: out std_logic;
-		-- Read ready. This signal indicates that the master can
-    		-- accept the read data and response information.
-		S_AXI_RREADY	: in std_logic
-	);
-end neuron_v1_0_S00_AXI;
-
-architecture arch_imp of neuron_v1_0_S00_AXI is
-
-	-- AXI4LITE signals
-	signal axi_awaddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-	signal axi_awready	: std_logic;
-	signal axi_wready	: std_logic;
-	signal axi_bresp	: std_logic_vector(1 downto 0);
-	signal axi_bvalid	: std_logic;
-	signal axi_araddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-	signal axi_arready	: std_logic;
-	signal axi_rdata	: std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal axi_rresp	: std_logic_vector(1 downto 0);
-	signal axi_rvalid	: std_logic;
-
-	-- Example-specific design signals
-	-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-	-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-	-- ADDR_LSB = 2 for 32 bits (n downto 2)
-	-- ADDR_LSB = 3 for 64 bits (n downto 3)
-	constant ADDR_LSB  : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
-	constant OPT_MEM_ADDR_BITS : integer := 4;
-	------------------------------------------------
-	---- Signals for user logic register space example
-	--------------------------------------------------
-	---- Number of Slave Registers 32
-	signal slv_reg0	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg1	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg2	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg3	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg4	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg5	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg6	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg7	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg8	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg9	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg10	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg11	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg12	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg13	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg14	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg15	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg16	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg17	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg18	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg19	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg20	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg21	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg22	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg23	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg24	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg25	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg26	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg27	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg28	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg29	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg30	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg31	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal slv_reg_rden	: std_logic;
-	signal slv_reg_wren	: std_logic;
-	signal reg_data_out	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-	signal byte_index	: integer;
-	signal aw_en	: std_logic;
-	
-
-    component mac is
-     port ( 
-       inputs : in dataVector;
-       weights : in dataVector;
-       bias : in dataType;
-       outp : out dataType;
-       clk: in STD_LOGIC);
-    end component;
-    
-    component sigmoid is
-     port ( 
-       inp : in dataType;
-       clk : in std_logic;
-       outp : out dataType);
-    end component;
-    
-    signal var1 : dataType;
-    signal calc_outp: dataType;
-    signal inputs : dataVector;
-    signal weights : dataVector;
-
-begin
-	-- I/O Connections assignments
-
-	S_AXI_AWREADY	<= axi_awready;
-	S_AXI_WREADY	<= axi_wready;
-	S_AXI_BRESP	<= axi_bresp;
-	S_AXI_BVALID	<= axi_bvalid;
-	S_AXI_ARREADY	<= axi_arready;
-	S_AXI_RDATA	<= axi_rdata;
-	S_AXI_RRESP	<= axi_rresp;
-	S_AXI_RVALID	<= axi_rvalid;
-	-- Implement axi_awready generation
-	-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-	-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-	-- de-asserted when reset is low.
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_awready <= '0';
-	      aw_en <= '1';
-	    else
-	      if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-	        -- slave is ready to accept write address when
-	        -- there is a valid write address and write data
-	        -- on the write address and data bus. This design 
-	        -- expects no outstanding transactions. 
-	           axi_awready <= '1';
-	           aw_en <= '0';
-	        elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
-	           aw_en <= '1';
-	           axi_awready <= '0';
-	      else
-	        axi_awready <= '0';
-	      end if;
-	    end if;
-	  end if;
-	end process;
-
-	-- Implement axi_awaddr latching
-	-- This process is used to latch the address when both 
-	-- S_AXI_AWVALID and S_AXI_WVALID are valid. 
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_awaddr <= (others => '0');
-	    else
-	      if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-	        -- Write Address latching
-	        axi_awaddr <= S_AXI_AWADDR;
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement axi_wready generation
-	-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-	-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
-	-- de-asserted when reset is low. 
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_wready <= '0';
-	    else
-	      if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
-	          -- slave is ready to accept write data when 
-	          -- there is a valid write address and write data
-	          -- on the write address and data bus. This design 
-	          -- expects no outstanding transactions.           
-	          axi_wready <= '1';
-	      else
-	        axi_wready <= '0';
-	      end if;
-	    end if;
-	  end if;
-	end process; 
-
-	-- Implement memory mapped register select and write logic generation
-	-- The write data is accepted and written to memory mapped registers when
-	-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-	-- select byte enables of slave registers while writing.
-	-- These registers are cleared when reset (active low) is applied.
-	-- Slave register write enable is asserted when valid address and data are available
-	-- and the slave is ready to accept the write address and write data.
-	slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
-
-	process (S_AXI_ACLK)
-	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); 
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      slv_reg0 <= (others => '0');
-	      slv_reg1 <= (others => '0');
-	      slv_reg2 <= (others => '0');
-	      slv_reg3 <= (others => '0');
-	      slv_reg4 <= (others => '0');
-	      slv_reg5 <= (others => '0');
-	      slv_reg6 <= (others => '0');
-	      slv_reg7 <= (others => '0');
-	      slv_reg8 <= (others => '0');
-	      slv_reg9 <= (others => '0');
-	      slv_reg10 <= (others => '0');
-	      slv_reg11 <= (others => '0');
-	      slv_reg12 <= (others => '0');
-	      slv_reg13 <= (others => '0');
-	      slv_reg14 <= (others => '0');
-	      slv_reg15 <= (others => '0');
-	      slv_reg16 <= (others => '0');
-	      slv_reg17 <= (others => '0');
-	      slv_reg18 <= (others => '0');
-	      slv_reg19 <= (others => '0');
-	      slv_reg20 <= (others => '0');
-	      slv_reg21 <= (others => '0');
-	      slv_reg22 <= (others => '0');
-	      slv_reg23 <= (others => '0');
-	      slv_reg24 <= (others => '0');
-	      slv_reg25 <= (others => '0');
-	      slv_reg26 <= (others => '0');
-	      slv_reg27 <= (others => '0');
-	      slv_reg28 <= (others => '0');
-	      slv_reg29 <= (others => '0');
-	      slv_reg30 <= (others => '0');
-	      slv_reg31 <= (others => '0');
-	    else
-	      loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
-	      if (slv_reg_wren = '1') then
-	        case loc_addr is
-	          when b"00000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 0
-	                slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 1
-	                slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 2
-	                slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 3
-	                slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 4
-	                slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 5
-	                slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 6
-	                slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"00111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 7
-	                slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 8
-	                slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 9
-	                slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 10
-	                slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 11
-	                slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 12
-	                slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 13
-	                slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 14
-	                slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"01111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 15
-	                slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 16
-	                slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 17
-	                slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 18
-	                slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 19
-	                slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 20
-	                slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 21
-	                slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 22
-	                slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"10111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 23
-	                slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11000" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 24
-	                slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11001" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 25
-	                slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11010" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 26
-	                slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11011" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 27
-	                slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11100" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 28
-	                slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11101" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 29
-	                slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11110" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 30
-	                slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when b"11111" =>
-	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
-	                -- Respective byte enables are asserted as per write strobes                   
-	                -- slave registor 31
-	                slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-	              end if;
-	            end loop;
-	          when others =>
-	            slv_reg0 <= slv_reg0;
-	            slv_reg1 <= slv_reg1;
-	            slv_reg2 <= slv_reg2;
-	            slv_reg3 <= slv_reg3;
-	            slv_reg4 <= slv_reg4;
-	            slv_reg5 <= slv_reg5;
-	            slv_reg6 <= slv_reg6;
-	            slv_reg7 <= slv_reg7;
-	            slv_reg8 <= slv_reg8;
-	            slv_reg9 <= slv_reg9;
-	            slv_reg10 <= slv_reg10;
-	            slv_reg11 <= slv_reg11;
-	            slv_reg12 <= slv_reg12;
-	            slv_reg13 <= slv_reg13;
-	            slv_reg14 <= slv_reg14;
-	            slv_reg15 <= slv_reg15;
-	            slv_reg16 <= slv_reg16;
-	            slv_reg17 <= slv_reg17;
-	            slv_reg18 <= slv_reg18;
-	            slv_reg19 <= slv_reg19;
-	            slv_reg20 <= slv_reg20;
-	            slv_reg21 <= slv_reg21;
-	            slv_reg22 <= slv_reg22;
-	            slv_reg23 <= slv_reg23;
-	            slv_reg24 <= slv_reg24;
-	            slv_reg25 <= slv_reg25;
-	            slv_reg26 <= slv_reg26;
-	            slv_reg27 <= slv_reg27;
-	            slv_reg28 <= slv_reg28;
-	            slv_reg29 <= slv_reg29;
-	            slv_reg30 <= slv_reg30;
-	            slv_reg31 <= slv_reg31;
-	        end case;
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement write response logic generation
-	-- The write response and response valid signals are asserted by the slave 
-	-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
-	-- This marks the acceptance of address and indicates the status of 
-	-- write transaction.
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_bvalid  <= '0';
-	      axi_bresp   <= "00"; --need to work more on the responses
-	    else
-	      if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0'  ) then
-	        axi_bvalid <= '1';
-	        axi_bresp  <= "00"; 
-	      elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then   --check if bready is asserted while bvalid is high)
-	        axi_bvalid <= '0';                                 -- (there is a possibility that bready is always asserted high)
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement axi_arready generation
-	-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-	-- S_AXI_ARVALID is asserted. axi_awready is 
-	-- de-asserted when reset (active low) is asserted. 
-	-- The read address is also latched when S_AXI_ARVALID is 
-	-- asserted. axi_araddr is reset to zero on reset assertion.
-
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then 
-	    if S_AXI_ARESETN = '0' then
-	      axi_arready <= '0';
-	      axi_araddr  <= (others => '1');
-	    else
-	      if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-	        -- indicates that the slave has acceped the valid read address
-	        axi_arready <= '1';
-	        -- Read Address latching 
-	        axi_araddr  <= S_AXI_ARADDR;           
-	      else
-	        axi_arready <= '0';
-	      end if;
-	    end if;
-	  end if;                   
-	end process; 
-
-	-- Implement axi_arvalid generation
-	-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
-	-- S_AXI_ARVALID and axi_arready are asserted. The slave registers 
-	-- data are available on the axi_rdata bus at this instance. The 
-	-- assertion of axi_rvalid marks the validity of read data on the 
-	-- bus and axi_rresp indicates the status of read transaction.axi_rvalid 
-	-- is deasserted on reset (active low). axi_rresp and axi_rdata are 
-	-- cleared to zero on reset (active low).  
-	process (S_AXI_ACLK)
-	begin
-	  if rising_edge(S_AXI_ACLK) then
-	    if S_AXI_ARESETN = '0' then
-	      axi_rvalid <= '0';
-	      axi_rresp  <= "00";
-	    else
-	      if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-	        -- Valid read data is available at the read data bus
-	        axi_rvalid <= '1';
-	        axi_rresp  <= "00"; -- 'OKAY' response
-	      elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-	        -- Read data is accepted by the master
-	        axi_rvalid <= '0';
-	      end if;            
-	    end if;
-	  end if;
-	end process;
-
-	-- Implement memory mapped register select and read logic generation
-	-- Slave register read enable is asserted when valid address is available
-	-- and the slave is ready to accept the read address.
-	slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
-
-	process (calc_outp, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
-	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
-	begin
-	    -- Address decoding for reading registers
-	    loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
-	    case loc_addr is
-	      when b"00000" =>
-	        reg_data_out <= calc_outp;
-	      when b"00001" =>
-	        reg_data_out <= slv_reg1;
-	      when b"00010" =>
-	        reg_data_out <= slv_reg2;
-	      when b"00011" =>
-	        reg_data_out <= slv_reg3;
-	      when b"00100" =>
-	        reg_data_out <= slv_reg4;
-	      when b"00101" =>
-	        reg_data_out <= slv_reg5;
-	      when b"00110" =>
-	        reg_data_out <= slv_reg6;
-	      when b"00111" =>
-	        reg_data_out <= slv_reg7;
-	      when b"01000" =>
-	        reg_data_out <= slv_reg8;
-	      when b"01001" =>
-	        reg_data_out <= slv_reg9;
-	      when b"01010" =>
-	        reg_data_out <= slv_reg10;
-	      when b"01011" =>
-	        reg_data_out <= slv_reg11;
-	      when b"01100" =>
-	        reg_data_out <= slv_reg12;
-	      when b"01101" =>
-	        reg_data_out <= slv_reg13;
-	      when b"01110" =>
-	        reg_data_out <= slv_reg14;
-	      when b"01111" =>
-	        reg_data_out <= slv_reg15;
-	      when b"10000" =>
-	        reg_data_out <= slv_reg16;
-	      when b"10001" =>
-	        reg_data_out <= slv_reg17;
-	      when b"10010" =>
-	        reg_data_out <= slv_reg18;
-	      when b"10011" =>
-	        reg_data_out <= slv_reg19;
-	      when b"10100" =>
-	        reg_data_out <= slv_reg20;
-	      when b"10101" =>
-	        reg_data_out <= slv_reg21;
-	      when b"10110" =>
-	        reg_data_out <= slv_reg22;
-	      when b"10111" =>
-	        reg_data_out <= slv_reg23;
-	      when b"11000" =>
-	        reg_data_out <= slv_reg24;
-	      when b"11001" =>
-	        reg_data_out <= slv_reg25;
-	      when b"11010" =>
-	        reg_data_out <= slv_reg26;
-	      when b"11011" =>
-	        reg_data_out <= slv_reg27;
-	      when b"11100" =>
-	        reg_data_out <= slv_reg28;
-	      when b"11101" =>
-	        reg_data_out <= slv_reg29;
-	      when b"11110" =>
-	        reg_data_out <= slv_reg30;
-	      when b"11111" =>
-	        reg_data_out <= slv_reg31;
-	      when others =>
-	        reg_data_out  <= (others => '0');
-	    end case;
-	end process; 
-
-	-- Output register or memory read data
-	process( S_AXI_ACLK ) is
-	begin
-	  if (rising_edge (S_AXI_ACLK)) then
-	    if ( S_AXI_ARESETN = '0' ) then
-	      axi_rdata  <= (others => '0');
-	    else
-	      if (slv_reg_rden = '1') then
-	        -- When there is a valid read address (S_AXI_ARVALID) with 
-	        -- acceptance of read address by the slave (axi_arready), 
-	        -- output the read dada 
-	        -- Read address mux
-	          axi_rdata <= reg_data_out;     -- register read data
-	      end if;   
-	    end if;
-	  end if;
-	end process;
-
-
-	-- Add user logic here
-    mac1: mac port map (
-        inputs => inputs,
-        weights => weights,
-        bias => slv_reg20,
-        outp => var1,
-        clk => S_AXI_ACLK
-    );
-    
-    sig1: sigmoid port map (
-        inp => var1,
-        clk => S_AXI_ACLK,
-        outp => calc_outp
-    );
-    
-    inputs (0) <= slv_reg0;
-    weights(0) <= slv_reg1;
-    inputs (1) <= slv_reg2;
-    weights(1) <= slv_reg3;
-    inputs (2) <= slv_reg4;
-    weights(2) <= slv_reg5;
-    inputs (3) <= slv_reg6;
-    weights(3) <= slv_reg7;
-    inputs (4) <= slv_reg8;
-    weights(4) <= slv_reg9;
-    inputs (5) <= slv_reg10;
-    weights(5) <= slv_reg11;
-    inputs (6) <= slv_reg12;
-    weights(6) <= slv_reg13;
-    inputs (7) <= slv_reg14;
-    weights(7) <= slv_reg15;
-    inputs (8) <= slv_reg16;
-    weights(8) <= slv_reg17;
-    inputs (9) <= slv_reg18;
-    weights(9) <= slv_reg19;
-    
-	-- User logic ends
-
-end arch_imp;

src/ip_repo/neuron_1.0/src/globals.vhd

@@ -1,28 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.math_real.all;
-
-package myPackage is
-    
-    constant nNodes : integer := 10;
-    constant nBits : integer := 32;
-    subtype dataType is std_logic_vector(nBits-1 downto 0);
-    subtype dataTypeAdder is std_logic_vector(integer(ceil(log2(real(nBits)))) downto 0);
-    type dataVector is array(0 to nNodes-1) of std_logic_vector(nBits-1 downto 0);
-end myPackage;
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity globals is
---  Port ( );
-end globals;
-
-architecture Behavioral of globals is
-
-begin
-
-
-end Behavioral;

src/ip_repo/neuron_1.0/src/mac.vhd

@@ -1,42 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_arith.ALL;
-use IEEE.std_logic_textio.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.myPackage.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity mac is
-    Port ( inputs : in dataVector;
-           weights : in dataVector;
-           bias : in dataType;
-           outp : out dataType;
-           clk: in STD_LOGIC);
-end mac;
-
-architecture Behavioral of mac is
-
-begin
-
-MAIN: process(clk)
-    variable sum : dataType;
-begin
-    if rising_edge(clk) then
-        sum :=  bias;
-        for i in 0 to nNodes-1 loop
-            sum := sum + conv_integer(inputs(i)) * conv_integer(weights(i));
-        end loop;
-        
-        outp <= sum;
-    end if;
-end process;
-
-end Behavioral;

src/ip_repo/neuron_1.0/src/neuron.vhd

@@ -1,47 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity neuron is
-    Port (
-        inputs : in dataVector;
-        weights : in dataVector;
-        bias : in dataType;
-        clk : in std_logic;
-        outp : out dataType);
-end neuron;
-
-architecture Behavioral of neuron is 
-
-component mac is
- port ( 
-   inputs : in dataVector;
-   weights : in dataVector;
-   bias : in dataType;
-   outp : out dataType);
-end component;
-
-component sigmoid is
- port ( 
-   inp : in dataType;
-   clk : in std_logic;
-   outp : out dataType);
-end component;
-
-signal var1 : dataType;
-
-begin
-mac1: mac port map (
-    inputs => inputs,
-    weights => weights,
-    bias => bias,
-    outp => var1
-);
-
-sig1: sigmoid port map (
-    inp => var1,
-    clk => clk,
-    outp => outp
-);
-
-end Behavioral;

src/ip_repo/neuron_1.0/src/neuron4.vhd

@@ -1,61 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity neuron4 is
-    Port (
-        input0 : in std_logic_vector(nBits-1 downto 0);
-        input1 : in std_logic_vector(nBits-1 downto 0);
-        input2 : in std_logic_vector(nBits-1 downto 0);
-        input3 : in std_logic_vector(nBits-1 downto 0);
-        weight0 : in std_logic_vector(nBits-1 downto 0);
-        weight1 : in std_logic_vector(nBits-1 downto 0);
-        weight2 : in std_logic_vector(nBits-1 downto 0);
-        weight3 : in std_logic_vector(nBits-1 downto 0);
-        
-        bias : in std_logic_vector(nBits-1 downto 0);
-        clk : in std_logic;
-        outp : out std_logic_vector(nBits-1 downto 0));
-end neuron4;
-
-architecture Behavioral of neuron4 is 
-
-component mac is
- port ( 
-   inputs : in dataVector;
-   weights : in dataVector;
-   bias : in dataType;
-   outp : out dataType);
-end component;
-
-component sigmoid is
- port ( 
-   inp : in dataType;
-   clk : in std_logic;
-   outp : out dataType);
-end component;
-
-signal var1 : dataType;
-
-begin
-mac1: mac port map (
-    inputs(0) => input0,
-    inputs(1) => input1,
-    inputs(2) => input2,
-    inputs(3) => input3,
-    weights(0) => weight0,
-    weights(1) => weight1,
-    weights(2) => weight2,
-    weights(3) => weight3,
-    
-    bias => bias,
-    outp => var1
-);
-
-sig1: sigmoid port map (
-    inp => var1,
-    clk => clk,
-    outp => outp
-);
-
-end Behavioral;

src/ip_repo/neuron_1.0/xgui/neuron_v1_0.tcl

@@ -1,62 +0,0 @@
-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
-  ipgui::add_param $IPINST -name "Component_Name"
-  #Adding Page
-  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
-  set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox]
-  set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH}
-  set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}]
-  set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH}
-  ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
-  ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
-
-
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
-	# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
-	# Procedure called to validate C_S00_AXI_DATA_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
-	# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
-	# Procedure called to validate C_S00_AXI_ADDR_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
-	# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
-	# Procedure called to validate C_S00_AXI_BASEADDR
-	return true
-}
-
-proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
-	# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
-	# Procedure called to validate C_S00_AXI_HIGHADDR
-	return true
-}
-
-
-proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
-	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
-}
-
-proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
-	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
-}
-

src/ip_repo/neuron_packed/xgui/packaging_v1_0.tcl

@@ -1,25 +0,0 @@
-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
-  ipgui::add_param $IPINST -name "Component_Name"
-  #Adding Page
-  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
-  ipgui::add_param $IPINST -name "busWidth" -parent ${Page_0}
-
-
-}
-
-proc update_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
-	# Procedure called to update busWidth when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
-	# Procedure called to validate busWidth
-	return true
-}
-
-
-proc update_MODELPARAM_VALUE.busWidth { MODELPARAM_VALUE.busWidth PARAM_VALUE.busWidth } {
-	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.busWidth}] ${MODELPARAM_VALUE.busWidth}
-}
-

src/ip_repo/packaging/src/mac.vhd

@@ -1,42 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_arith.ALL;
-use IEEE.std_logic_textio.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use work.myPackage.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity mac is
-    Port ( inputs : in dataVector;
-           weights : in dataVector;
-           bias : in dataType;
-           outp : out dataType;
-           clk: in STD_LOGIC);
-end mac;
-
-architecture Behavioral of mac is
-
-begin
-
-MAIN: process(clk)
-    variable sum : dataType;
-begin
-    if rising_edge(clk) then
-        sum :=  bias;
-        for i in 0 to nNodes-1 loop
-            sum := signed(sum) + conv_integer(signed(inputs(i))) * conv_integer(signed(weights(i)));
-        end loop;
-        
-        outp <= sum;
-    end if;
-end process;
-
-end Behavioral;

src/ip_repo/packaging/src/neuron.vhd

@@ -1,61 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity neuron is
-    Port (
-        inputs : in dataVector;
-        weights : in dataVector;
-        bias : in dataType;
-        start : in std_logic;
-        finished : out std_logic;
-        clk : in std_logic;
-        outp : out dataType);
-end neuron;
-
-architecture Behavioral of neuron is 
-
-component mac is
- port ( 
-   inputs : in dataVector;
-   weights : in dataVector;
-   bias : in dataType;
-   outp : out dataType;
-   clk : in std_logic);
-end component;
-
-component relu is
- port ( 
-   inp : in dataType;
-   clk : in std_logic;
-   outp : out dataType);
-end component;
-
-signal var1 : dataType;
-
-signal macFinished: std_logic;
-
-begin
-mac1: mac port map (
-    inputs => inputs,
-    weights => weights,
-    bias => bias,
-    outp => var1,
-    clk => clk
-);
-
-relu1: relu port map (
-    inp => var1,
-    clk => clk,
-    outp => outp
-);
-
-timing : process(clk)
-begin
-    if(rising_edge(clk)) then
-        macFinished <= start;
-        finished <= macFinished;
-    end if;
-end process;
-
-end Behavioral;

src/ip_repo/packaging/src/parallelize.vhd

@@ -1,86 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.myPackage.ALL;
-
-entity parallelize is
-    generic(
-        busWidth : integer:=8);
-    Port ( clk : in STD_LOGIC;
-           rst : in STD_LOGIC;
-           start : in STD_LOGIC;
-           dataIn : in std_logic_vector(busWidth-1 downto 0);
-           ready: out std_logic;
-           dataOutReset : in std_logic;
-           dataOut : out std_logic_vector(busWidth-1 downto 0);
-           finished : out STD_LOGIC);
-end parallelize;
-
-architecture Behavioral of parallelize is
-
-constant parallelInWidth : integer := (2*nNodes+1) * nBits;
-constant parallelOutWidth : integer := nBits;
-
-component shiftIn is
-    generic(
-        inWidth : integer := busWidth;
-        outWidth : integer := parallelInWidth);
-    Port ( clk : in STD_LOGIC;
-           sync_reset : in STD_LOGIC;
-           dataIn : in std_logic_vector(inWidth-1 downto 0);
-           dataOut : out std_logic_vector(outWidth-1 downto 0);
-           finished : out STD_LOGIC);
-end component;
-component neuron is
-    Port (
-        inputs : in dataVector;
-        weights : in dataVector;
-        bias : in dataType;
-        start : in std_logic;
-        finished : out std_logic;
-        clk : in std_logic;
-        outp : out dataType);
-end component;
-component shiftOut is
-    generic(
-        inWidth : integer := parallelOutWidth;
-        outWidth : integer := busWidth);
-    Port ( clk : in STD_LOGIC;
-           sync_reset : in STD_LOGIC;
-           dataIn : in std_logic_vector(inWidth-1 downto 0);
-           dataOut : out std_logic_vector(outWidth-1 downto 0);
-           finished : out STD_LOGIC);
-end component;
-
-signal dataInStorage : std_logic_vector(parallelInWidth-1 downto 0);
-signal dataOutStorage : std_logic_vector(parallelOutWidth-1 downto 0);
-signal shiftInFinished : std_logic;
-
-begin
-
-shiftIn1: shiftIn port map (
-    clk         => clk,
-    sync_reset  => start,
-    dataIn      => dataIn,
-    dataOut     => dataInStorage,
-    finished    => shiftInFinished
-);
-
-neuron1: neuron port map (
-    inputs  => to_dataVector(dataInStorage(parallelInWidth-1 downto (nNodes+1) * nBits)),
-    weights => to_dataVector(dataInStorage((nNodes+1) * nBits-1 downto nBits)),
-    bias    => dataInStorage(nBits-1 downto 0),
-    clk     => clk,
-    outp    => dataOutStorage,
-    start   => shiftInFinished,
-    finished=> ready
-);
-
-shiftOut1 : shiftOut port map (
-    clk         => clk,
-    sync_reset  => dataOutReset,
-    dataIn      => dataOutStorage,
-    dataOut     => dataOut,
-    finished    => finished
-);
-
-end Behavioral;

src/ip_repo/packaging/src/relu.vhd

@@ -1,30 +0,0 @@
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.std_logic_signed.all;
-use IEEE.std_logic_arith.all;
-use IEEE.math_real.all;
-use work.myPackage.ALL;
-
-entity relu is
-    Port ( inp : in dataType;
-           outp : out dataType;
-           clk: in STD_LOGIC );
-end relu;
-
-architecture Behavioral of relu is
-
-begin
-    calc : process(clk)
-    begin
-        if(rising_edge(clk)) then
-            if(signed(inp) > 0) then
-                outp <= inp;
-            else
-                outp <= (others => '0');
-            end if;
-            
-        end if;
-    end process;
-end Behavioral;

src/ip_repo/packaging/src/shiftOut.vhd

@@ -1,62 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 06/03/2019 01:56:01 PM
--- Design Name: 
--- Module Name: shiftOut - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity shiftOut is
-    generic(
-        inWidth : integer := 32*4;
-        outWidth : integer := 32);
-    Port ( clk : in STD_LOGIC;
-           sync_reset : in STD_LOGIC;
-           dataIn : in std_logic_vector(inWidth-1 downto 0);
-           dataOut : out std_logic_vector(outWidth-1 downto 0);
-           finished : out STD_LOGIC);
-end shiftOut;
-
-architecture Behavioral of shiftOut is
-    signal dataIndex : integer range 0 to (inWidth / outWidth) := 0;
-begin
-
-p_s2p : process(clk, sync_reset)
-begin
-    if(sync_reset = '0') then
-        dataIndex <= 0;
-        finished <= '0';
-    elsif(rising_edge(clk)) then
-        if(dataIndex < inWidth/outWidth) then
-            
-        else
-            
-        end if;
-        if(dataIndex < inWidth/outWidth-1) then
-            finished <= '0';
-            dataIndex <= dataIndex + 1;
-        else
-            finished <= '1';
-            dataIndex <= dataIndex;
-        end if;
-    end if;
-end process;
-
-dataOut <= dataIn(inWidth - dataIndex * outWidth - 1 downto inWidth - dataIndex * outWidth - outWidth);
-end Behavioral;

src/ip_repo/packaging/xgui/packaging_v1_0.tcl

@@ -1,25 +0,0 @@
-# Definitional proc to organize widgets for parameters.
-proc init_gui { IPINST } {
-  ipgui::add_param $IPINST -name "Component_Name"
-  #Adding Page
-  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
-  ipgui::add_param $IPINST -name "busWidth" -parent ${Page_0}
-
-
-}
-
-proc update_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
-	# Procedure called to update busWidth when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.busWidth { PARAM_VALUE.busWidth } {
-	# Procedure called to validate busWidth
-	return true
-}
-
-
-proc update_MODELPARAM_VALUE.busWidth { MODELPARAM_VALUE.busWidth PARAM_VALUE.busWidth } {
-	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.busWidth}] ${MODELPARAM_VALUE.busWidth}
-}
-