added vivado float ip

src/hdl/conv2d.vhd

@@ -12,8 +12,6 @@ entity conv2d is
     Port ( clk : in STD_LOGIC;
            rst_n : in std_logic;
            start : in STD_LOGIC;
-           ready: out std_logic;
-           idle : out std_logic := '0';
            done : out std_logic := '0';
            
            srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
@@ -47,9 +45,15 @@ architecture Behavioral of conv2d is
         N: integer := kernelSize
     );
     Port (
+        clk: in std_logic;
+        rst_n: in std_logic;
         kernelValues: in register_file(0 to N*N-1);
         inputValues: in register_file(0 to N*N-1);
-        outputValue: out std_logic_vector(31 downto 0)
+        inputValid : in STD_LOGIC;
+        inputReady : out std_logic := '0';
+        outputData : out STD_LOGIC_VECTOR (31 downto 0);
+        outputValid : out std_logic;
+        outputReady : in std_logic
     );
     end component;
     
@@ -64,23 +68,35 @@ architecture Behavioral of conv2d is
         return ret;
     end function;
     
-    signal kernelOutput : std_logic_vector(busWidth-1 downto 0);
     signal inputBuffer : register_file(0 to regDepth-1);
     signal kernelValues : register_file(0 to kernelSize*kernelSize-1);
     signal dataIndex : integer range 0 to wordCount;
+    signal dataIndexOutput : integer range 0 to imageWidth*imageWidth-1;
     
     signal working : std_logic := '0';
     signal dstStalled_s : std_logic := '0';
     signal dstValid_s : std_logic := '0';
-    signal kernelComplete : std_logic := '0';
+    signal kernelValuesComplete : std_logic := '0';
+    
+    signal kernelInputValid_s : std_logic;
+    signal kernelInputReady_s : std_logic;
     
 begin
     kernel_5x5 : kernel_NxN port map (
+        clk => clk,
+        rst_n => rst_n,
+        
         kernelValues => kernelValues,
         inputValues => buffer_to_activations(inputBuffer),
-        outputValue => kernelOutput
+        
+        inputValid => kernelInputValid_s,
+        inputReady => kernelInputReady_s,
+        
+        outputData => dstData,
+        outputReady => dstReady,
+        outputValid => dstValid_s
     );
-    dstData <= kernelOutput;
+
     shiftInPixels: shiftIn port map (
         clk         => clk,
         ce          => dstValid_s,
@@ -92,40 +108,39 @@ begin
     
     setKernel : process(rst_n, clk) begin
         if rst_n = '0' then
-            kernelComplete <= '0';
+            kernelValuesComplete <= '0';
         elsif rising_edge(clk) then
             kernelValues <= kernelValues;
             if dataIndex < kernelSize * kernelSize then
                 kernelValues(dataIndex) <= srcData;
-                kernelComplete <= '0';
+                kernelValuesComplete <= '0';
             else
-                kernelComplete <= '1';
+                kernelValuesComplete <= '1';
             end if;        
         end if;
     end process;
     
-    dataPathStall : process(rst_n, clk)
+    dstValid <= dstValid_s;
     
-    begin
+    dataPathStall : process(rst_n, clk) begin
         if rst_n = '0' then
             dstStalled_s <= '0';
         elsif rising_edge(clk) then
-            if working = '1' and srcValid = '1' and dstReady = '0' then
+            if working = '1' and srcValid = '1' and kernelInputReady_s = '0' then
                 dstStalled_s <= '1';
-            elsif dstStalled_s = '1' and working = '1' and dstReady = '1' then
+            elsif dstStalled_s = '1' and working = '1' and kernelInputReady_s = '1' then
                 dstStalled_s <= '0';
             end if;
         end if;
     end process;
     
-    dstValid_s <= working and dstReady and (srcValid or dstStalled_s) and kernelComplete;
-    dstValid <= dstValid_s;
-    
-    srcRdy : process(dataIndex, working, dstReady, srcValid, start) begin
+    kernelInputValid_s <= working and kernelInputReady_s and (srcValid or dstStalled_s) and kernelValuesComplete;
+ 
+    srcRdy : process(dataIndex, working, kernelInputReady_s, srcValid, start) begin
         if (dataIndex = wordCount - 1 and srcValid = '1') or dataIndex = wordCount then
             srcReady <= '0';
         else
-            srcReady <= working and dstReady and not dstStalled_s and start;
+            srcReady <= working and kernelInputReady_s and not dstStalled_s and start;
         end if;
     end process;
     
@@ -144,29 +159,39 @@ begin
         end if;
     end process;
     
+    dataIndexOutputCounter : process(clk, rst_n) begin
+        if(rst_n = '0') then
+            dataIndexOutput <= 0;
+            done <= '0';
+        elsif(rising_edge(clk)) then
+            done <= '0';
+            if(start = '0') then
+                dataIndexOutput <= 0;
+            elsif dataIndexOutput = imageWidth*imageWidth - 1 then
+                dataIndexOutput <= 0;
+                done <= '1';
+            elsif dstValid_s = '1' then
+                dataIndexOutput <= dataIndexOutput + 1;
+            else
+                dataIndexOutput <= dataIndexOutput;
+            end if;
+        end if;
+    end process;
+    
     reset : process(rst_n, clk)
     begin
         if rst_n = '0' then
             working <= '0';
-            done <= '0';
         elsif rising_edge(clk) then
-            done <= '0';
             working <= '0';
-           
-            if dataIndex = wordCount - 1 and dstValid_s = '1' then
-                done <= '1';
-                working <= '1';
-            elsif dataIndex = wordCount then
+            if dataIndex = wordCount then
                 working <= '0';
             elsif start = '1' then
                 working <= '1';
             end if;
         end if;
     end process;
-    
-    idle <= rst_n and not working;
-    ready <= rst_n;
-    
+   
     
 
 end Behavioral;

src/hdl/conv2d_5x5_224p.vhd

@@ -32,8 +32,6 @@ architecture Behavioral of conv2d_5x5_224p is
     Port ( clk : in STD_LOGIC;
            rst_n : in std_logic;
            start : in STD_LOGIC;
-           ready: out std_logic;
-           idle : out std_logic := '0';
            done : out std_logic := '0';
            
            srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
@@ -61,8 +59,6 @@ begin
         dstReady => dstReady,
         
         start   => start,
-        ready   => ready,
-        idle    => idle,
         done    => done
     );
 end Behavioral;

src/hdl/kernel_5x5.vhd

@@ -3,36 +3,149 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use ieee.numeric_std.all;
 use work.myPackage.ALL;
-use work.float32.float_t;
-use work.float32.conv_float;
-use work.float32.conv_std_logic_vector;
-use work.float32."*";
-use work.float32."+";
 
 entity kernel_NxN is
     Generic(
         N: integer := 5
     );
     Port (
+        clk: in std_logic;
+        rst_n: in std_logic;
         kernelValues: in register_file(0 to N*N-1);
         inputValues: in register_file(0 to N*N-1);
-        outputValue: out std_logic_vector(31 downto 0)
+        inputValid : in STD_LOGIC;
+        inputReady : out std_logic := '0';
+        outputData : out STD_LOGIC_VECTOR (31 downto 0);
+        outputValid : out std_logic;
+        outputReady : in std_logic
     );
 end kernel_NxN;
 
 architecture Behavioral of kernel_NxN is
-
+    component fp_multiply_0 is
+      Port ( 
+        aclk : in STD_LOGIC;
+        aresetn : in STD_LOGIC;
+        s_axis_a_tvalid : in STD_LOGIC;
+        s_axis_a_tready : out STD_LOGIC;
+        s_axis_a_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+        s_axis_a_tlast : in STD_LOGIC;
+        s_axis_b_tvalid : in STD_LOGIC;
+        s_axis_b_tready : out STD_LOGIC;
+        s_axis_b_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+        m_axis_result_tvalid : out STD_LOGIC;
+        m_axis_result_tready : in STD_LOGIC;
+        m_axis_result_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+        m_axis_result_tlast : out STD_LOGIC
+      );
+    end component;
+    component fp_accumulator_0 is
+      Port ( 
+        aclk : in STD_LOGIC;
+        aresetn : in STD_LOGIC;
+        s_axis_a_tvalid : in STD_LOGIC;
+        s_axis_a_tready : out STD_LOGIC;
+        s_axis_a_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+        s_axis_a_tlast : in STD_LOGIC;
+        m_axis_result_tvalid : out STD_LOGIC;
+        m_axis_result_tready : in STD_LOGIC;
+        m_axis_result_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+        m_axis_result_tlast : out STD_LOGIC
+      );
+    end component;
+    
+    signal working : std_logic := '0';
+    
+    signal index_s : integer range 0 to N*N-1 := 0;
+    
+    signal macInput_s : std_logic_vector(31 downto 0);
+    signal macInputValid_s : std_logic := '0';
+    signal macInputReady_s : std_logic := '0';
+    signal macInputLast_s  : std_logic := '0';
+    
+    signal macKernel_s : std_logic_vector(31 downto 0);
+    
+    signal macOutput_s : std_logic_vector(31 downto 0);
+    signal macOutputValid_s : std_logic := '0';
+    signal macOutputReady_s : std_logic := '0';
+    signal macOutputLast_s  : std_logic := '0';
+    
+    signal macIntraData_s  : std_logic_vector(31 downto 0);
+    signal macIntraValid_s : std_logic;
+    signal macIntraReady_s : std_logic;
+    signal macIntraLast_s  : std_logic;
 begin
-    calc : process(kernelValues, inputValues)
-        variable sum : float_t;
-        variable product : float_t;
+    fp_mul_0 : fp_multiply_0 port map (
+        aclk => clk,
+        aresetn => rst_n,
+        s_axis_a_tvalid => macInputValid_s,
+        s_axis_a_tready => macInputReady_s,
+        s_axis_a_tdata => macInput_s,
+        s_axis_a_tlast => macInputLast_s,
+        s_axis_b_tvalid => macInputValid_s,
+        s_axis_b_tready => open,
+        s_axis_b_tdata => macKernel_s,
+        m_axis_result_tvalid => macIntraValid_s,
+        m_axis_result_tready => macIntraReady_s,
+        m_axis_result_tdata => macIntraData_s,
+        m_axis_result_tlast => macIntraLast_s
+    );
+    fp_acc_0 : fp_accumulator_0 port map (
+        aclk => clk,
+        aresetn => rst_n,
+        s_axis_a_tvalid => macIntraValid_s,
+        s_axis_a_tready => macIntraReady_s,
+        s_axis_a_tdata => macIntraData_s,
+        s_axis_a_tlast => macIntraLast_s,
+        m_axis_result_tvalid => macOutputValid_s,
+        m_axis_result_tready => macOutputReady_s,
+        m_axis_result_tdata => macOutput_s,
+        m_axis_result_tlast => macOutputLast_s
+    );
+    counter : process(rst_n, clk)
     begin
-        sum := conv_float(std_logic_vector(to_unsigned(0, 32)));
-        for i in integer range 0 to N*N-1 loop
-            product := conv_float(kernelValues(i)) * conv_float(inputValues(i));
-            sum := sum + product;
-        end loop;
-        outputValue <= conv_std_logic_vector(sum);
+        if rst_n = '0' then
+            index_s <= 0;
+            working <= '0';
+        elsif rising_edge(clk) then
+            if working = '0' and inputValid = '1' then
+                working <= '1';
+                index_s <= 0;
+            elsif index_s < N*N-1 and working = '1' and macInputValid_s = '1' then
+                working <= '1';
+                index_s <= index_s + 1;
+            elsif index_s = N*N-1 and working = '1' and macInputValid_s = '1' then
+                working <= '0';
+                index_s <= 0;
+            else
+                working <= working;
+                index_s <= index_s;
+            end if;
+        end if;
     end process;
+    
 
+    macInput_s <= inputValues(index_s);
+    macKernel_s <= kernelValues(index_s);
+    outputData <= macOutput_s;
+
+    
+    controlSignals : process(macOutputLast_s, macInputReady_s, working, index_s, outputReady, macOutputValid_s) begin
+        inputReady <= macInputReady_s and not working;
+        macInputValid_s <= macInputReady_s and working;
+        
+        if index_s = N*N-1 then
+            macInputLast_s <= '1';
+        else
+            macInputLast_s <= '0';
+        end if;
+        
+        macOutputReady_s <= outputReady;
+        if macOutputLast_s = '1' then
+            outputValid <= macOutputValid_s;
+        else
+            outputValid <= '0';
+        end if;
+        
+    end process;
 end Behavioral;

src/hdl/multiplex.vhd

@@ -31,10 +31,8 @@ entity multiplex is
         );
     Port ( clk : in STD_LOGIC;
            start : in STD_LOGIC;
-           ready: out std_logic;
            rst : in STD_LOGIC;
            done : out STD_LOGIC;
-           idle : out STD_LOGIC;
            
            moduleId : in STD_LOGIC_VECTOR (31 downto 0);
            
@@ -96,8 +94,6 @@ component conv2d_5x5_224p is
     Port ( clk : in STD_LOGIC;
            rst_n : in std_logic;
            start : in STD_LOGIC;
-           ready: out std_logic;
-           idle : out std_logic := '0';
            done : out std_logic := '0';
            
            srcData : in STD_LOGIC_VECTOR (busWidth-1 downto 0);
@@ -240,8 +236,6 @@ begin
         dstReady => muxDstReady,
         
         start   => muxStart(3),
-        ready   => muxReady(3),
-        idle    => muxIdle(3),
         done    => muxDone(3)
     );
     
@@ -276,10 +270,8 @@ begin
             end if;
         end loop;
         
-        ready <= muxReady(i);
         dstData <= muxDstData(i);
         done <= muxDone(i);
-        idle <= muxIdle(i);
         dstValid <= muxDstValid(i);
         srcReady <= muxSrcReady(i);
         

src/hdl/packaging.vhd

@@ -66,10 +66,8 @@ architecture Behavioral of packaging is
         Port (
            clk : in STD_LOGIC;
            start : in STD_LOGIC;
-           ready: out std_logic;
            rst : in STD_LOGIC;
            done : out STD_LOGIC;
-           idle : out STD_LOGIC;
            
            moduleId : in STD_LOGIC_VECTOR (31 downto 0);
            
@@ -114,9 +112,7 @@ architecture Behavioral of packaging is
     signal muxDstReady : std_logic;
     
     signal muxStart  : std_logic;
-    signal muxReady  : std_logic;
     signal muxDone   : std_logic;
-    signal muxIdle   : std_logic;
     
     signal muxControlsFIFO : std_logic;
     
@@ -133,9 +129,7 @@ begin
         clk => clk,
         rst => rst,
         start => muxStart,
-        ready  => muxReady,
         done => muxDone,
-        idle => muxIdle,
         
         moduleId => moduleId,
         
@@ -171,7 +165,7 @@ begin
             inputReadReady <= '0';
             csReset <= '0';
             csOutReset <= '0';
-            outHeaderCounter <= 3;
+            outHeaderCounter <= 0;
             muxStart <= '0';
             muxControlsFIFO <= '0';
             
@@ -287,15 +281,10 @@ begin
                         errorCode_s <= x"C";
                         outHeaderCounter <= outHeaderCounter;
                         outputWriteReady <= '1';
-                    elsif outHeaderCounter < 1 then
+                    else 
                         outHeaderCounter <= outHeaderCounter + 1;
                         state <= writeHeader;
                         outputWriteReady <= '1';
-                        outputStream_s <= moduleId;
-                    else
-                        state <= waitProcessing;
-                        muxStart <= '1';
-                        muxControlsFIFO <= '1';
                     end if;
 
                 when waitProcessing =>

tests/ImgToConv2dBin.py

@@ -58,5 +58,5 @@ with open("vivado_project/vhdl-modules.sim/sim_1/behav/xsim/input.txt", "w") as
 
 with open("vivado_project/vhdl-modules.sim/sim_1/behav/xsim/outputTimings.txt", "w") as inFile:
 
-	for i in range(4 + kernelSize**2 + pixels):
-		inFile.write("{:d} ns\n".format(0))
+	for i in range(4 + pixels):
+		inFile.write("{:d} ns\n".format(315))

tests/ioImg.py

@@ -38,9 +38,8 @@ def setPixel(img, txt, i, input):
   if re.match(r'[01]{32}', val, re.M):
     num = struct.unpack('!f',struct.pack('!i', int(val, 2)))[0]
 
-    if not input:
-      num = num/25
     if num > 255:
+      print(num)
       num = 255
     x = i % sizeWithBorder
     y = int(i / sizeWithBorder) % sizeWithBorder
@@ -48,17 +47,17 @@ def setPixel(img, txt, i, input):
 
 def main():
   with open("vivado_project/vhdl-modules.sim/sim_1/behav/xsim/input.txt", "r") as inFile:
-    #print("Input:")
+    print("Input:")
     i = 0
     for line in inFile:
-      if i < 3 or i >= 3 + pixels:
+      if i < 3+kernel**2 or i >= 3+kernel**2 + pixels:
         showHex(line, i)
       else:
         setPixel(imageIn, line, i-3, True)
       i += 1
 
   with open("vivado_project/vhdl-modules.sim/sim_1/behav/xsim/output.txt", "r") as outFile:
-    #print("Output:")
+    print("Output:")
     i = 0
     for line in outFile:
       if i < 3 or i >= 3 + pixels:

vhdl-modules.tcl

@@ -99,15 +99,15 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use
 set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
 set_property -name "simulator_language" -value "Mixed" -objects $obj
 set_property -name "target_language" -value "VHDL" -objects $obj
-set_property -name "webtalk.activehdl_export_sim" -value "6" -objects $obj
-set_property -name "webtalk.ies_export_sim" -value "6" -objects $obj
-set_property -name "webtalk.modelsim_export_sim" -value "6" -objects $obj
-set_property -name "webtalk.questa_export_sim" -value "6" -objects $obj
-set_property -name "webtalk.riviera_export_sim" -value "6" -objects $obj
-set_property -name "webtalk.vcs_export_sim" -value "6" -objects $obj
-set_property -name "webtalk.xcelium_export_sim" -value "5" -objects $obj
-set_property -name "webtalk.xsim_export_sim" -value "6" -objects $obj
-set_property -name "webtalk.xsim_launch_sim" -value "3" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "12" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "12" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "12" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "12" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "12" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "12" -objects $obj
+set_property -name "webtalk.xcelium_export_sim" -value "6" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "12" -objects $obj
+set_property -name "webtalk.xsim_launch_sim" -value "17" -objects $obj
 set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
 
 # Create 'sources_1' fileset (if not found)
@@ -149,9 +149,18 @@ set files [list \
  [file normalize "${origin_dir}/src/hdl/start_for_Loop_VConvH_proc_U0.vhd"] \
  [file normalize "${origin_dir}/src/hdl/packaging.vhd"] \
  [file normalize "${origin_dir}/src/testbench/tb_module_behav.wcfg"] \
+ [file normalize "${origin_dir}/vivado_project/vhdl-modules.srcs/sources_1/imports/src/complex_float.vhd"] \
 ]
 add_files -norecurse -fileset $obj $files
 
+# Add local files from the original project (-no_copy_sources specified)
+set files [list \
+ [file normalize "${origin_dir}/vivado_project/vhdl-modules.srcs/sources_1/ip/fp_accumulator_0/fp_accumulator_0.xci" ]\
+ [file normalize "${origin_dir}/vivado_project/vhdl-modules.srcs/sources_1/ip/fp_multiply_0/fp_multiply_0.xci" ]\
+ [file normalize "${origin_dir}/vivado_project/vhdl-modules.srcs/sources_1/bd/float_mac/hdl/float_mac_wrapper.vhd" ]\
+]
+set added_files [add_files -fileset sources_1 $files]
+
 # Set 'sources_1' fileset file properties for remote files
 set file "$origin_dir/src/hdl/Block_proc.vhd"
 set file [file normalize $file]
@@ -268,9 +277,27 @@ set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "VHDL" -objects $file_obj
 
+set file "$origin_dir/vivado_project/vhdl-modules.srcs/sources_1/imports/src/complex_float.vhd"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
 
 # Set 'sources_1' fileset file properties for local files
-# None
+set file "fp_accumulator_0/fp_accumulator_0.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+
+set file "fp_multiply_0/fp_multiply_0.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+
+set file "hdl/float_mac_wrapper.vhd"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+
 
 # Set 'sources_1' fileset properties
 set obj [get_filesets sources_1]
@@ -334,6 +361,12 @@ set obj [get_filesets utils_1]
 
 
 # Adding sources referenced in BDs, if not already added
+if { [get_files fp_accumulator_0.xci] == "" } {
+  import_files -quiet -fileset sources_1 c:/Users/johan/mlfpga/repos/vhdl-modules/vivado_project/vhdl-modules.srcs/sources_1/ip/fp_accumulator_0/fp_accumulator_0.xci
+}
+if { [get_files fp_multiply_0.xci] == "" } {
+  import_files -quiet -fileset sources_1 c:/Users/johan/mlfpga/repos/vhdl-modules/vivado_project/vhdl-modules.srcs/sources_1/ip/fp_multiply_0/fp_multiply_0.xci
+}
 if { [get_files Block_proc.vhd] == "" } {
   import_files -quiet -fileset sources_1 C:/Users/johan/mlfpga/repos/vhdl-modules/src/hdl/Block_proc.vhd
 }
@@ -814,62 +847,62 @@ preplace portBus sw_0 -pg 1 -y 1080 -defaultsOSRD
 preplace portBus eth_rxd_0 -pg 1 -y 830 -defaultsOSRD
 preplace inst fifo_input -pg 1 -lvl 4 -y 340 -defaultsOSRD
 preplace inst xlslice_0 -pg 1 -lvl 5 -y 820 -defaultsOSRD
-preplace inst xlconstant_0 -pg 1 -lvl 2 -y 1020 -defaultsOSRD
 preplace inst packaging_0 -pg 1 -lvl 3 -y 580 -defaultsOSRD
+preplace inst xlconstant_0 -pg 1 -lvl 2 -y 1020 -defaultsOSRD
 preplace inst xlconstant_1 -pg 1 -lvl 1 -y 680 -defaultsOSRD
 preplace inst fifo_output -pg 1 -lvl 4 -y 590 -defaultsOSRD
 preplace inst ethernet_transceiver2_0 -pg 1 -lvl 3 -y 1040 -defaultsOSRD
 preplace inst c_counter_binary_0 -pg 1 -lvl 5 -y 80 -defaultsOSRD
 preplace inst c_counter_binary_1 -pg 1 -lvl 5 -y 340 -defaultsOSRD
-preplace inst invert_reset_0 -pg 1 -lvl 3 -y 720 -defaultsOSRD
 preplace inst xlconcat_4 -pg 1 -lvl 6 -y 280 -defaultsOSRD
 preplace inst segment_0 -pg 1 -lvl 6 -y 140 -defaultsOSRD
-preplace inst clk_wiz_0 -pg 1 -lvl 2 -y 550 -defaultsOSRD
+preplace inst invert_reset_0 -pg 1 -lvl 3 -y 720 -defaultsOSRD
 preplace inst xlconcat_5 -pg 1 -lvl 2 -y 670 -defaultsOSRD
-preplace netloc ethernet_transceiver2_0_fifo_read 1 3 1 870
+preplace inst clk_wiz_0 -pg 1 -lvl 2 -y 550 -defaultsOSRD
+preplace netloc ethernet_transceiver2_0_fifo_read 1 3 1 900
 preplace netloc xlconstant_1_dout 1 1 1 NJ
-preplace netloc packaging_0_errorCode 1 3 3 860 720 1300J 260 NJ
+preplace netloc packaging_0_errorCode 1 3 3 830 200 NJ 200 1560J
 preplace netloc ethernet_transceiver2_0_led16_b 1 3 4 NJ 1070 NJ 1070 NJ 1070 NJ
-preplace netloc Net4 1 3 4 890J 950 NJ 950 NJ 950 NJ
-preplace netloc xlslice_1_Dout 1 3 2 850 740 1310
+preplace netloc Net4 1 3 4 NJ 970 NJ 970 NJ 970 1840J
+preplace netloc xlslice_1_Dout 1 3 2 870 460 1320
 preplace netloc Net5 1 3 4 NJ 1010 NJ 1010 NJ 1010 NJ
 preplace netloc packaging_0_outData 1 3 1 N
-preplace netloc c_counter_binary_1_Q 1 5 1 1510
-preplace netloc Net6 1 3 4 850J 1040 NJ 1040 NJ 1040 NJ
-preplace netloc fifo_input_dout 1 2 2 450 340 NJ
-preplace netloc ethernet_transceiver2_0_led16_r 1 3 4 NJ 1110 NJ 1110 NJ 1110 1800J
-preplace netloc xlconcat_5_dout 1 2 3 400 790 NJ 790 1290J
+preplace netloc c_counter_binary_1_Q 1 5 1 1540
+preplace netloc Net6 1 3 4 NJ 1050 NJ 1050 NJ 1050 1830J
+preplace netloc fifo_input_dout 1 2 2 460 340 NJ
+preplace netloc ethernet_transceiver2_0_led16_r 1 3 4 NJ 1110 NJ 1110 NJ 1110 1840J
+preplace netloc xlconcat_5_dout 1 2 3 410 790 830J 820 NJ
 preplace netloc sw_0_1 1 0 3 NJ 1080 NJ 1080 NJ
-preplace netloc ethernet_transceiver2_0_eth_refclk 1 3 4 880 760 NJ 760 NJ 760 NJ
-preplace netloc ethernet_transceiver2_0_led16_g 1 3 4 NJ 1090 NJ 1090 NJ 1090 1780J
-preplace netloc ethernet_transceiver2_0_fifo_write 1 3 1 820
-preplace netloc xlconstant_0_dout 1 2 1 390J
+preplace netloc ethernet_transceiver2_0_eth_refclk 1 3 4 910 760 NJ 760 NJ 760 NJ
+preplace netloc ethernet_transceiver2_0_led16_g 1 3 4 NJ 1090 1320J 1100 NJ 1100 NJ
+preplace netloc ethernet_transceiver2_0_fifo_write 1 3 1 860
+preplace netloc xlconstant_0_dout 1 2 1 400J
 preplace netloc segment_0_anodes 1 6 1 NJ
-preplace netloc packaging_0_inpRdEn 1 3 1 810
-preplace netloc ethernet_transceiver2_0_led17_b 1 3 4 NJ 1130 NJ 1130 NJ 1130 1790J
-preplace netloc c_counter_binary_0_Q 1 5 1 1530
-preplace netloc segment_0_cathodes 1 6 1 1770J
-preplace netloc fifo_output_overflow 1 4 1 1280
-preplace netloc ethernet_transceiver2_0_eth_mdc 1 3 4 890J 980 NJ 980 NJ 980 NJ
+preplace netloc packaging_0_inpRdEn 1 3 1 850
+preplace netloc ethernet_transceiver2_0_led17_b 1 3 4 NJ 1130 NJ 1130 NJ 1130 1830J
+preplace netloc c_counter_binary_0_Q 1 5 1 1560
+preplace netloc segment_0_cathodes 1 6 1 1830J
+preplace netloc fifo_output_overflow 1 4 1 1310
+preplace netloc ethernet_transceiver2_0_eth_mdc 1 3 4 NJ 990 NJ 990 1550J 980 NJ
 preplace netloc reset_rtl_0_1 1 0 2 NJ 540 NJ
-preplace netloc packaging_0_stateOut 1 3 3 840 750 NJ 750 1520J
-preplace netloc fifo_output_rd_data_count 1 1 4 190 460 NJ 460 NJ 460 1270
-preplace netloc fifo_input_empty 1 2 2 430 320 NJ
+preplace netloc packaging_0_stateOut 1 3 3 840 220 NJ 220 1550J
+preplace netloc fifo_output_rd_data_count 1 1 4 180 190 NJ 190 NJ 190 1300
+preplace netloc fifo_input_empty 1 2 2 440 320 NJ
 preplace netloc packaging_0_outWrEn 1 3 1 N
-preplace netloc fifo_output_full 1 2 2 440 480 840J
-preplace netloc ethernet_transceiver2_0_led17_r 1 3 4 NJ 1170 NJ 1170 NJ 1170 1770J
-preplace netloc Net1 1 3 4 NJ 910 NJ 910 NJ 910 1780J
-preplace netloc Net 1 3 4 NJ 890 NJ 890 NJ 890 1770J
+preplace netloc fifo_output_full 1 2 2 450 480 880J
+preplace netloc ethernet_transceiver2_0_led17_r 1 3 4 NJ 1170 NJ 1170 NJ 1170 1810J
+preplace netloc Net1 1 3 4 NJ 910 NJ 910 NJ 910 1830J
+preplace netloc Net 1 3 4 NJ 890 NJ 890 1540J 830 NJ
 preplace netloc xlconcat_4_dout 1 6 1 NJ
 preplace netloc fifo_input_overflow 1 4 1 N
-preplace netloc Net2 1 3 4 NJ 930 NJ 930 NJ 930 1790J
-preplace netloc clk_100MHz_1 1 0 2 NJ 570 180J
-preplace netloc xlslice_0_Dout 1 5 1 1530
-preplace netloc aresetn 1 2 1 410
-preplace netloc ethernet_transceiver2_0_led17_g 1 3 4 NJ 1150 NJ 1150 NJ 1150 1780J
-preplace netloc clk_wiz_clk_out1 1 2 4 420 780 830 730 1290 160 NJ
-preplace netloc Net3 1 3 4 840J 940 NJ 940 NJ 940 1800J
-levelinfo -pg 1 0 100 290 630 1080 1410 1650 1820 -top 0 -bot 1290
+preplace netloc Net2 1 3 4 920J 900 NJ 900 1560J 890 NJ
+preplace netloc xlslice_0_Dout 1 5 1 1550
+preplace netloc ethernet_transceiver2_0_led17_g 1 3 4 NJ 1150 NJ 1150 NJ 1150 1820J
+preplace netloc clk_wiz_clk_out1 1 2 4 430 470 890 210 1330 160 NJ
+preplace netloc clk_100MHz_1 1 0 2 20J 560 NJ
+preplace netloc aresetn 1 2 1 420
+preplace netloc Net3 1 3 4 NJ 950 NJ 950 NJ 950 1830J
+levelinfo -pg 1 0 100 300 650 1110 1440 1690 1860 -top 0 -bot 1290
 "
 }