possibly fixed LAYERED_METADATA error

vhdl-modules.tcl

@@ -322,6 +322,7 @@ set_property -name "file_type" -value "VHDL" -objects $file_obj
 # Set 'sim_1' fileset properties
 set obj [get_filesets sim_1]
 set_property -name "top" -value "tb_module" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
 set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
 
 # Set 'utils_1' fileset object
@@ -427,9 +428,10 @@ proc cr_bd_design_1 { parentCell } {
   if { $bCheckIPs == 1 } {
      set list_check_ips "\ 
   xilinx.com:ip:c_counter_binary:12.0\
+  xilinx.com:ip:clk_wiz:6.0\
   xilinx.com:user:ethernet_transceiver2:1.0\
   xilinx.com:ip:fifo_generator:13.2\
-  xilinx.com:ip:c_addsub:12.0\
+  xilinx.com:ip:util_vector_logic:2.0\
   xilinx.com:user:segment:1.0\
   xilinx.com:ip:xlconcat:2.1\
   xilinx.com:ip:xlconstant:1.1\
@@ -567,6 +569,15 @@ proc cr_bd_design_1 { parentCell } {
    CONFIG.SSET {false} \
  ] $c_counter_binary_1
 
+  # Create instance: clk_wiz_0, and set properties
+  set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
+  set_property -dict [ list \
+   CONFIG.ENABLE_CLOCK_MONITOR {false} \
+   CONFIG.PRIMITIVE {MMCM} \
+   CONFIG.RESET_PORT {resetn} \
+   CONFIG.RESET_TYPE {ACTIVE_LOW} \
+ ] $clk_wiz_0
+
   # Create instance: ethernet_transceiver2_0, and set properties
   set ethernet_transceiver2_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:ethernet_transceiver2:1.0 ethernet_transceiver2_0 ]
 
@@ -659,21 +670,13 @@ proc cr_bd_design_1 { parentCell } {
    CONFIG.Write_Data_Count_Width {9} \
  ] $fifo_output
 
-  # Create instance: negate_0, and set properties
-  set negate_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 negate_0 ]
+  # Create instance: invert_reset_0, and set properties
+  set invert_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 invert_reset_0 ]
   set_property -dict [ list \
-   CONFIG.A_Type {Unsigned} \
-   CONFIG.A_Width {1} \
-   CONFIG.Add_Mode {Add} \
-   CONFIG.B_Constant {true} \
-   CONFIG.B_Type {Unsigned} \
-   CONFIG.B_Value {1} \
-   CONFIG.B_Width {1} \
-   CONFIG.CE {false} \
-   CONFIG.Latency {1} \
-   CONFIG.Latency_Configuration {Automatic} \
-   CONFIG.Out_Width {1} \
- ] $negate_0
+   CONFIG.C_OPERATION {not} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_notgate.png} \
+ ] $invert_reset_0
 
   # Create instance: packaging_0, and set properties
   set block_name packaging
@@ -746,9 +749,11 @@ proc cr_bd_design_1 { parentCell } {
   connect_bd_net -net Net4 [get_bd_ports eth_rxerr_0] [get_bd_pins ethernet_transceiver2_0/eth_rxerr]
   connect_bd_net -net Net5 [get_bd_ports eth_mdio_0] [get_bd_pins ethernet_transceiver2_0/eth_mdio]
   connect_bd_net -net Net6 [get_bd_ports eth_rstn_0] [get_bd_pins ethernet_transceiver2_0/eth_rstn]
+  connect_bd_net -net aresetn [get_bd_pins clk_wiz_0/locked] [get_bd_pins ethernet_transceiver2_0/btn_reset] [get_bd_pins invert_reset_0/Op1] [get_bd_pins packaging_0/rst]
   connect_bd_net -net c_counter_binary_0_Q [get_bd_pins c_counter_binary_0/Q] [get_bd_pins segment_0/num2]
   connect_bd_net -net c_counter_binary_1_Q [get_bd_pins c_counter_binary_1/Q] [get_bd_pins segment_0/num1]
-  connect_bd_net -net clk_wiz_clk_out1 [get_bd_ports clk_100MHz] [get_bd_pins c_counter_binary_0/CLK] [get_bd_pins c_counter_binary_1/CLK] [get_bd_pins ethernet_transceiver2_0/clk100mhz] [get_bd_pins fifo_input/clk] [get_bd_pins fifo_output/wr_clk] [get_bd_pins negate_0/CLK] [get_bd_pins packaging_0/clk] [get_bd_pins segment_0/clk]
+  connect_bd_net -net clk_100MHz_1 [get_bd_ports clk_100MHz] [get_bd_pins clk_wiz_0/clk_in1]
+  connect_bd_net -net clk_wiz_clk_out1 [get_bd_pins c_counter_binary_0/CLK] [get_bd_pins c_counter_binary_1/CLK] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins ethernet_transceiver2_0/clk100mhz] [get_bd_pins fifo_input/clk] [get_bd_pins fifo_output/wr_clk] [get_bd_pins packaging_0/clk] [get_bd_pins segment_0/clk]
   connect_bd_net -net ethernet_transceiver2_0_eth_mdc [get_bd_ports eth_mdc_0] [get_bd_pins ethernet_transceiver2_0/eth_mdc]
   connect_bd_net -net ethernet_transceiver2_0_eth_refclk [get_bd_ports eth_refclk_0] [get_bd_pins ethernet_transceiver2_0/eth_refclk] [get_bd_pins fifo_output/rd_clk]
   connect_bd_net -net ethernet_transceiver2_0_led16_b [get_bd_ports led16_b_0] [get_bd_pins ethernet_transceiver2_0/led16_b]
@@ -768,7 +773,7 @@ proc cr_bd_design_1 { parentCell } {
   connect_bd_net -net packaging_0_outData [get_bd_pins fifo_output/din] [get_bd_pins packaging_0/outData]
   connect_bd_net -net packaging_0_outWrEn [get_bd_pins fifo_output/wr_en] [get_bd_pins packaging_0/outWrEn]
   connect_bd_net -net packaging_0_stateOut [get_bd_pins packaging_0/stateOut] [get_bd_pins xlconcat_4/In1]
-  connect_bd_net -net rst_clk_wiz_100M_peripheral_aresetn [get_bd_ports reset_rtl_0] [get_bd_pins ethernet_transceiver2_0/btn_reset] [get_bd_pins negate_0/A] [get_bd_pins packaging_0/rst]
+  connect_bd_net -net reset_rtl_0_1 [get_bd_ports reset_rtl_0] [get_bd_pins clk_wiz_0/resetn]
   connect_bd_net -net segment_0_anodes [get_bd_ports anodes_0] [get_bd_pins segment_0/anodes]
   connect_bd_net -net segment_0_cathodes [get_bd_ports cathodes_0] [get_bd_pins segment_0/cathodes]
   connect_bd_net -net sw_0_1 [get_bd_ports sw_0] [get_bd_pins ethernet_transceiver2_0/ip]
@@ -777,10 +782,96 @@ proc cr_bd_design_1 { parentCell } {
   connect_bd_net -net xlconstant_0_dout [get_bd_pins ethernet_transceiver2_0/udp_packet_checksum] [get_bd_pins xlconstant_0/dout]
   connect_bd_net -net xlconstant_1_dout [get_bd_pins xlconcat_5/In1] [get_bd_pins xlconstant_1/dout]
   connect_bd_net -net xlslice_0_Dout [get_bd_pins xlconcat_4/In2] [get_bd_pins xlslice_0/Dout]
-  connect_bd_net -net xlslice_1_Dout [get_bd_pins c_counter_binary_0/SCLR] [get_bd_pins c_counter_binary_1/SCLR] [get_bd_pins fifo_input/srst] [get_bd_pins fifo_output/rst] [get_bd_pins negate_0/S]
+  connect_bd_net -net xlslice_1_Dout [get_bd_pins c_counter_binary_0/SCLR] [get_bd_pins c_counter_binary_1/SCLR] [get_bd_pins fifo_input/srst] [get_bd_pins fifo_output/rst] [get_bd_pins invert_reset_0/Res]
 
   # Create address segments
 
+  # Perform GUI Layout
+  regenerate_bd_layout -layout_string {
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 6.8.11  2018-08-07 bk=1.4403 VDI=40 GEI=35 GUI=JA:9.0 non-TLS
+#  -string -flagsOSRD
+preplace port led17_r_0 -pg 1 -y 1220 -defaultsOSRD
+preplace port eth_txen_0 -pg 1 -y 920 -defaultsOSRD
+preplace port led17_g_0 -pg 1 -y 1190 -defaultsOSRD
+preplace port eth_rxerr_0 -pg 1 -y 950 -defaultsOSRD
+preplace port led16_r_0 -pg 1 -y 1130 -defaultsOSRD
+preplace port led17_b_0 -pg 1 -y 1160 -defaultsOSRD
+preplace port clk_100MHz -pg 1 -y 570 -defaultsOSRD
+preplace port eth_rstn_0 -pg 1 -y 1040 -defaultsOSRD
+preplace port led16_b_0 -pg 1 -y 1070 -defaultsOSRD
+preplace port eth_mdc_0 -pg 1 -y 980 -defaultsOSRD
+preplace port led16_g_0 -pg 1 -y 1100 -defaultsOSRD
+preplace port eth_refclk_0 -pg 1 -y 760 -defaultsOSRD
+preplace port eth_mdio_0 -pg 1 -y 1010 -defaultsOSRD
+preplace port reset_rtl_0 -pg 1 -y 540 -defaultsOSRD
+preplace port eth_crsdv_0 -pg 1 -y 890 -defaultsOSRD
+preplace portBus anodes_0 -pg 1 -y 130 -defaultsOSRD
+preplace portBus cathodes_0 -pg 1 -y 160 -defaultsOSRD
+preplace portBus eth_txd_0 -pg 1 -y 860 -defaultsOSRD
+preplace portBus led_0 -pg 1 -y 280 -defaultsOSRD
+preplace portBus sw_0 -pg 1 -y 1080 -defaultsOSRD
+preplace portBus eth_rxd_0 -pg 1 -y 830 -defaultsOSRD
+preplace inst fifo_input -pg 1 -lvl 4 -y 340 -defaultsOSRD
+preplace inst xlslice_0 -pg 1 -lvl 5 -y 820 -defaultsOSRD
+preplace inst xlconstant_0 -pg 1 -lvl 2 -y 1020 -defaultsOSRD
+preplace inst packaging_0 -pg 1 -lvl 3 -y 580 -defaultsOSRD
+preplace inst xlconstant_1 -pg 1 -lvl 1 -y 680 -defaultsOSRD
+preplace inst fifo_output -pg 1 -lvl 4 -y 590 -defaultsOSRD
+preplace inst ethernet_transceiver2_0 -pg 1 -lvl 3 -y 1040 -defaultsOSRD
+preplace inst c_counter_binary_0 -pg 1 -lvl 5 -y 80 -defaultsOSRD
+preplace inst c_counter_binary_1 -pg 1 -lvl 5 -y 340 -defaultsOSRD
+preplace inst invert_reset_0 -pg 1 -lvl 3 -y 720 -defaultsOSRD
+preplace inst xlconcat_4 -pg 1 -lvl 6 -y 280 -defaultsOSRD
+preplace inst segment_0 -pg 1 -lvl 6 -y 140 -defaultsOSRD
+preplace inst clk_wiz_0 -pg 1 -lvl 2 -y 550 -defaultsOSRD
+preplace inst xlconcat_5 -pg 1 -lvl 2 -y 670 -defaultsOSRD
+preplace netloc ethernet_transceiver2_0_fifo_read 1 3 1 870
+preplace netloc xlconstant_1_dout 1 1 1 NJ
+preplace netloc packaging_0_errorCode 1 3 3 860 720 1300J 260 NJ
+preplace netloc ethernet_transceiver2_0_led16_b 1 3 4 NJ 1070 NJ 1070 NJ 1070 NJ
+preplace netloc Net4 1 3 4 890J 950 NJ 950 NJ 950 NJ
+preplace netloc xlslice_1_Dout 1 3 2 850 740 1310
+preplace netloc Net5 1 3 4 NJ 1010 NJ 1010 NJ 1010 NJ
+preplace netloc packaging_0_outData 1 3 1 N
+preplace netloc c_counter_binary_1_Q 1 5 1 1510
+preplace netloc Net6 1 3 4 850J 1040 NJ 1040 NJ 1040 NJ
+preplace netloc fifo_input_dout 1 2 2 450 340 NJ
+preplace netloc ethernet_transceiver2_0_led16_r 1 3 4 NJ 1110 NJ 1110 NJ 1110 1800J
+preplace netloc xlconcat_5_dout 1 2 3 400 790 NJ 790 1290J
+preplace netloc sw_0_1 1 0 3 NJ 1080 NJ 1080 NJ
+preplace netloc ethernet_transceiver2_0_eth_refclk 1 3 4 880 760 NJ 760 NJ 760 NJ
+preplace netloc ethernet_transceiver2_0_led16_g 1 3 4 NJ 1090 NJ 1090 NJ 1090 1780J
+preplace netloc ethernet_transceiver2_0_fifo_write 1 3 1 820
+preplace netloc xlconstant_0_dout 1 2 1 390J
+preplace netloc segment_0_anodes 1 6 1 NJ
+preplace netloc packaging_0_inpRdEn 1 3 1 810
+preplace netloc ethernet_transceiver2_0_led17_b 1 3 4 NJ 1130 NJ 1130 NJ 1130 1790J
+preplace netloc c_counter_binary_0_Q 1 5 1 1530
+preplace netloc segment_0_cathodes 1 6 1 1770J
+preplace netloc fifo_output_overflow 1 4 1 1280
+preplace netloc ethernet_transceiver2_0_eth_mdc 1 3 4 890J 980 NJ 980 NJ 980 NJ
+preplace netloc reset_rtl_0_1 1 0 2 NJ 540 NJ
+preplace netloc packaging_0_stateOut 1 3 3 840 750 NJ 750 1520J
+preplace netloc fifo_output_rd_data_count 1 1 4 190 460 NJ 460 NJ 460 1270
+preplace netloc fifo_input_empty 1 2 2 430 320 NJ
+preplace netloc packaging_0_outWrEn 1 3 1 N
+preplace netloc fifo_output_full 1 2 2 440 480 840J
+preplace netloc ethernet_transceiver2_0_led17_r 1 3 4 NJ 1170 NJ 1170 NJ 1170 1770J
+preplace netloc Net1 1 3 4 NJ 910 NJ 910 NJ 910 1780J
+preplace netloc Net 1 3 4 NJ 890 NJ 890 NJ 890 1770J
+preplace netloc xlconcat_4_dout 1 6 1 NJ
+preplace netloc fifo_input_overflow 1 4 1 N
+preplace netloc Net2 1 3 4 NJ 930 NJ 930 NJ 930 1790J
+preplace netloc clk_100MHz_1 1 0 2 NJ 570 180J
+preplace netloc xlslice_0_Dout 1 5 1 1530
+preplace netloc aresetn 1 2 1 410
+preplace netloc ethernet_transceiver2_0_led17_g 1 3 4 NJ 1150 NJ 1150 NJ 1150 1780J
+preplace netloc clk_wiz_clk_out1 1 2 4 420 780 830 730 1290 160 NJ
+preplace netloc Net3 1 3 4 840J 940 NJ 940 NJ 940 1800J
+levelinfo -pg 1 0 100 290 630 1080 1410 1650 1820 -top 0 -bot 1290
+"
+}
 
   # Restore current instance
   current_bd_instance $oldCurInst