{
  "design": {
    "design_info": {
      "boundary_crc": "0x77B6D9CBCF9EBCA3",
      "device": "xc7a100tcsg324-1",
      "name": "design_1",
      "synth_flow_mode": "Hierarchical",
      "tool_version": "2018.3",
      "validated": "true"
    },
    "design_tree": {
      "fifo_output": "",
      "fifo_input": "",
      "xlconstant_0": "",
      "c_counter_binary_0": "",
      "c_counter_binary_1": "",
      "xlconcat_4": "",
      "segment_0": "",
      "negate_0": "",
      "xlconcat_5": "",
      "xlconstant_1": "",
      "xlslice_0": "",
      "ethernet_transceiver2_0": "",
      "packaging_0": ""
    },
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        "parameters": {
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            "value_src": "default"
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      },
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        "parameters": {
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            "value": "reset_rtl_0",
            "value_src": "default"
          },
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            "value": "design_1_clk_100MHz",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "100000000"
          },
          "INSERT_VIP": {
            "value": "0",
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            "value": "0.000",
            "value_src": "default"
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        "right": "0"
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        "left": "15",
        "right": "0",
        "parameters": {
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            "value_src": "ip_prop"
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      },
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        "right": "0"
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        "right": "7"
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      "cathodes_0": {
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        "right": "7"
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          "Almost_Full_Flag": {
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          "Programmable_Full_Type": {
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          "Read_Data_Count": {
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          "Read_Data_Count_Width": {
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          "Reset_Pin": {
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          "Underflow_Flag": {
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          "Use_Dout_Reset": {
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          "Valid_Flag": {
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          "Fifo_Implementation": {
            "value": "Common_Clock_Distributed_RAM"
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          "Performance_Options": {
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          "Programmable_Empty_Type": {
            "value": "No_Programmable_Empty_Threshold"
          },
          "Programmable_Full_Type": {
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          "Reset_Pin": {
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          "Reset_Type": {
            "value": "Synchronous_Reset"
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          "Underflow_Flag": {
            "value": "false"
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          "Use_Dout_Reset": {
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        "parameters": {
          "CONST_VAL": {
            "value": "0"
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          "CONST_WIDTH": {
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        "parameters": {
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          "Fb_Latency_Configuration": {
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          },
          "Final_Count_Value": {
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          "Latency_Configuration": {
            "value": "Automatic"
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        "parameters": {
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          "Fb_Latency_Configuration": {
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          "Final_Count_Value": {
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          "Latency_Configuration": {
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          "IN1_WIDTH": {
            "value": "4"
          },
          "IN2_WIDTH": {
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          "IN3_WIDTH": {
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          "IN4_WIDTH": {
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          "NUM_PORTS": {
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        "xci_name": "design_1_c_addsub_0_0",
        "parameters": {
          "A_Type": {
            "value": "Unsigned"
          },
          "A_Width": {
            "value": "1"
          },
          "Add_Mode": {
            "value": "Add"
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          "B_Constant": {
            "value": "true"
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          "B_Type": {
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          "B_Width": {
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          "CE": {
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          "Latency": {
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          "Latency_Configuration": {
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          "Out_Width": {
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          "IN1_WIDTH": {
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          "IN2_WIDTH": {
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          "IN3_WIDTH": {
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      "xlslice_0": {
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          "DIN_TO": {
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          "DIN_WIDTH": {
            "value": "16"
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          "boundary_crc": "0x0"
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            "direction": "I",
            "parameters": {
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                "value_src": "constant"
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                "value_src": "default_prop"
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                "value_src": "user_prop"
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          },
          "rst": {
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            "direction": "I",
            "parameters": {
              "POLARITY": {
                "value": "ACTIVE_LOW",
                "value_src": "user_prop"
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          "inputStream": {
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            "left": "31",
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          "inpRdEn": {
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          "outData": {
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          "outWrEn": {
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          "outputFull": {
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          "errorCode": {
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            "left": "3",
            "right": "0"
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          "stateOut": {
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    "interface_nets": {
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        "interface_ports": [
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          "ethernet_transceiver2_0/fifo_read"
        ]
      }
    },
    "nets": {
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          "c_counter_binary_0/CLK",
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          "negate_0/CLK",
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          "ethernet_transceiver2_0/clk100mhz",
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      "rst_clk_wiz_100M_peripheral_aresetn": {
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          "negate_0/A",
          "ethernet_transceiver2_0/btn_reset",
          "packaging_0/rst"
        ]
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      "segment_0_anodes": {
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          "anodes_0"
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      "segment_0_cathodes": {
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          "cathodes_0"
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          "ethernet_transceiver2_0/udp_packet_checksum"
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      "Net": {
        "ports": [
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          "ethernet_transceiver2_0/eth_rxd"
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      "Net1": {
        "ports": [
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      "Net2": {
        "ports": [
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        "ports": [
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        "ports": [
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          "ethernet_transceiver2_0/eth_rxerr"
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      "ethernet_transceiver2_0_eth_mdc": {
        "ports": [
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          "eth_mdc_0"
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      "Net5": {
        "ports": [
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          "ethernet_transceiver2_0/eth_mdio"
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      },
      "ethernet_transceiver2_0_eth_refclk": {
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          "eth_refclk_0",
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      "Net6": {
        "ports": [
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          "ethernet_transceiver2_0/eth_rstn"
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      "ethernet_transceiver2_0_led16_b": {
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      "ethernet_transceiver2_0_led16_g": {
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      "ethernet_transceiver2_0_led16_r": {
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      "ethernet_transceiver2_0_led17_b": {
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          "led17_b_0"
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      "ethernet_transceiver2_0_led17_g": {
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      "ethernet_transceiver2_0_led17_r": {
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          "fifo_output/rst"
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      "fifo_output_overflow": {
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      "sw_0_1": {
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          "ethernet_transceiver2_0/ip"
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      "packaging_0_inpRdEn": {
        "ports": [
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      "fifo_input_dout": {
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          "packaging_0/inputStream"
        ]
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      "fifo_input_empty": {
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          "packaging_0/inputEmpty"
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      },
      "fifo_output_full": {
        "ports": [
          "fifo_output/full",
          "packaging_0/outputFull"
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      "packaging_0_outData": {
        "ports": [
          "packaging_0/outData",
          "fifo_output/din"
        ]
      },
      "packaging_0_outWrEn": {
        "ports": [
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          "fifo_output/wr_en"
        ]
      },
      "packaging_0_errorCode": {
        "ports": [
          "packaging_0/errorCode",
          "xlconcat_4/In0"
        ]
      },
      "packaging_0_stateOut": {
        "ports": [
          "packaging_0/stateOut",
          "xlconcat_4/In1"
        ]
      }
    }
  }
}