-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.3
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity filter11x11_strm is
port (
    width : IN STD_LOGIC_VECTOR (31 downto 0);
    height : IN STD_LOGIC_VECTOR (31 downto 0);
    filt1 : IN STD_LOGIC_VECTOR (31 downto 0);
    filt2 : IN STD_LOGIC_VECTOR (31 downto 0);
    src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
    dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
    ap_clk : IN STD_LOGIC;
    ap_rst_n : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    src_V_TVALID : IN STD_LOGIC;
    src_V_TREADY : OUT STD_LOGIC;
    dst_V_TVALID : OUT STD_LOGIC;
    dst_V_TREADY : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    ap_idle : OUT STD_LOGIC );
end;


architecture behav of filter11x11_strm is 
    attribute CORE_GENERATION_INFO : STRING;
    attribute CORE_GENERATION_INFO of behav : architecture is
    "filter11x11_strm,hls_ip_2018_3,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7a100tcsg324-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.470000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=22,HLS_SYN_DSP=28,HLS_SYN_FF=3339,HLS_SYN_LUT=3643,HLS_VERSION=2018_3}";
    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_logic_0 : STD_LOGIC := '0';
    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
    constant ap_const_boolean_1 : BOOLEAN := true;

    signal ap_rst_n_inv : STD_LOGIC;
    signal filter11x11_strm_ent_U0_ap_start : STD_LOGIC;
    signal filter11x11_strm_ent_U0_start_full_n : STD_LOGIC;
    signal filter11x11_strm_ent_U0_ap_done : STD_LOGIC;
    signal filter11x11_strm_ent_U0_ap_continue : STD_LOGIC;
    signal filter11x11_strm_ent_U0_ap_idle : STD_LOGIC;
    signal filter11x11_strm_ent_U0_ap_ready : STD_LOGIC;
    signal filter11x11_strm_ent_U0_start_out : STD_LOGIC;
    signal filter11x11_strm_ent_U0_start_write : STD_LOGIC;
    signal filter11x11_strm_ent_U0_width_out_din : STD_LOGIC_VECTOR (31 downto 0);
    signal filter11x11_strm_ent_U0_width_out_write : STD_LOGIC;
    signal filter11x11_strm_ent_U0_width_out1_din : STD_LOGIC_VECTOR (31 downto 0);
    signal filter11x11_strm_ent_U0_width_out1_write : STD_LOGIC;
    signal filter11x11_strm_ent_U0_height_out_din : STD_LOGIC_VECTOR (31 downto 0);
    signal filter11x11_strm_ent_U0_height_out_write : STD_LOGIC;
    signal filter11x11_strm_ent_U0_height_out2_din : STD_LOGIC_VECTOR (31 downto 0);
    signal filter11x11_strm_ent_U0_height_out2_write : STD_LOGIC;
    signal filter11x11_strm_ent_U0_filt1_out_din : STD_LOGIC_VECTOR (31 downto 0);
    signal filter11x11_strm_ent_U0_filt1_out_write : STD_LOGIC;
    signal filter11x11_strm_ent_U0_filt1_out3_din : STD_LOGIC_VECTOR (31 downto 0);
    signal filter11x11_strm_ent_U0_filt1_out3_write : STD_LOGIC;
    signal filter11x11_strm_ent_U0_filt2_out_din : STD_LOGIC_VECTOR (31 downto 0);
    signal filter11x11_strm_ent_U0_filt2_out_write : STD_LOGIC;
    signal filter11x11_strm_ent_U0_filt2_out4_din : STD_LOGIC_VECTOR (31 downto 0);
    signal filter11x11_strm_ent_U0_filt2_out4_write : STD_LOGIC;
    signal Block_proc_U0_ap_start : STD_LOGIC;
    signal Block_proc_U0_ap_done : STD_LOGIC;
    signal Block_proc_U0_ap_continue : STD_LOGIC;
    signal Block_proc_U0_ap_idle : STD_LOGIC;
    signal Block_proc_U0_ap_ready : STD_LOGIC;
    signal Block_proc_U0_start_out : STD_LOGIC;
    signal Block_proc_U0_start_write : STD_LOGIC;
    signal Block_proc_U0_width_read : STD_LOGIC;
    signal Block_proc_U0_height_read : STD_LOGIC;
    signal Block_proc_U0_width_out_din : STD_LOGIC_VECTOR (31 downto 0);
    signal Block_proc_U0_width_out_write : STD_LOGIC;
    signal Block_proc_U0_height_out_din : STD_LOGIC_VECTOR (31 downto 0);
    signal Block_proc_U0_height_out_write : STD_LOGIC;
    signal Block_proc_U0_vconv_xlim_out_out_din : STD_LOGIC_VECTOR (31 downto 0);
    signal Block_proc_U0_vconv_xlim_out_out_write : STD_LOGIC;
    signal Loop_HConvH_proc6_U0_ap_start : STD_LOGIC;
    signal Loop_HConvH_proc6_U0_ap_done : STD_LOGIC;
    signal Loop_HConvH_proc6_U0_ap_continue : STD_LOGIC;
    signal Loop_HConvH_proc6_U0_ap_idle : STD_LOGIC;
    signal Loop_HConvH_proc6_U0_ap_ready : STD_LOGIC;
    signal Loop_HConvH_proc6_U0_height_read : STD_LOGIC;
    signal Loop_HConvH_proc6_U0_width_read : STD_LOGIC;
    signal Loop_HConvH_proc6_U0_src_V_TREADY : STD_LOGIC;
    signal Loop_HConvH_proc6_U0_filt1_read : STD_LOGIC;
    signal Loop_HConvH_proc6_U0_filt2_read : STD_LOGIC;
    signal Loop_HConvH_proc6_U0_hconv_V_din : STD_LOGIC_VECTOR (31 downto 0);
    signal Loop_HConvH_proc6_U0_hconv_V_write : STD_LOGIC;
    signal Loop_VConvH_proc_U0_ap_start : STD_LOGIC;
    signal Loop_VConvH_proc_U0_ap_done : STD_LOGIC;
    signal Loop_VConvH_proc_U0_ap_continue : STD_LOGIC;
    signal Loop_VConvH_proc_U0_ap_idle : STD_LOGIC;
    signal Loop_VConvH_proc_U0_ap_ready : STD_LOGIC;
    signal Loop_VConvH_proc_U0_height_read : STD_LOGIC;
    signal Loop_VConvH_proc_U0_vconv_xlim_loc_read : STD_LOGIC;
    signal Loop_VConvH_proc_U0_hconv_V_read : STD_LOGIC;
    signal Loop_VConvH_proc_U0_vconv_V_din : STD_LOGIC_VECTOR (31 downto 0);
    signal Loop_VConvH_proc_U0_vconv_V_write : STD_LOGIC;
    signal Loop_VConvH_proc_U0_filt1_read : STD_LOGIC;
    signal Loop_VConvH_proc_U0_filt2_read : STD_LOGIC;
    signal Loop_VConvH_proc_U0_height_out_din : STD_LOGIC_VECTOR (31 downto 0);
    signal Loop_VConvH_proc_U0_height_out_write : STD_LOGIC;
    signal Loop_VConvH_proc_U0_vconv_xlim_loc_out_din : STD_LOGIC_VECTOR (31 downto 0);
    signal Loop_VConvH_proc_U0_vconv_xlim_loc_out_write : STD_LOGIC;
    signal Loop_Border_proc_U0_ap_start : STD_LOGIC;
    signal Loop_Border_proc_U0_ap_done : STD_LOGIC;
    signal Loop_Border_proc_U0_ap_continue : STD_LOGIC;
    signal Loop_Border_proc_U0_ap_idle : STD_LOGIC;
    signal Loop_Border_proc_U0_ap_ready : STD_LOGIC;
    signal Loop_Border_proc_U0_width_read : STD_LOGIC;
    signal Loop_Border_proc_U0_height_read : STD_LOGIC;
    signal Loop_Border_proc_U0_dst_V_TDATA : STD_LOGIC_VECTOR (31 downto 0);
    signal Loop_Border_proc_U0_dst_V_TVALID : STD_LOGIC;
    signal Loop_Border_proc_U0_vconv_xlim_loc_read : STD_LOGIC;
    signal Loop_Border_proc_U0_vconv_V_read : STD_LOGIC;
    signal ap_sync_continue : STD_LOGIC;
    signal width_c_full_n : STD_LOGIC;
    signal width_c_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal width_c_empty_n : STD_LOGIC;
    signal width_c155_full_n : STD_LOGIC;
    signal width_c155_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal width_c155_empty_n : STD_LOGIC;
    signal height_c_full_n : STD_LOGIC;
    signal height_c_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal height_c_empty_n : STD_LOGIC;
    signal height_c156_full_n : STD_LOGIC;
    signal height_c156_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal height_c156_empty_n : STD_LOGIC;
    signal filt1_c_full_n : STD_LOGIC;
    signal filt1_c_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal filt1_c_empty_n : STD_LOGIC;
    signal filt1_c157_full_n : STD_LOGIC;
    signal filt1_c157_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal filt1_c157_empty_n : STD_LOGIC;
    signal filt2_c_full_n : STD_LOGIC;
    signal filt2_c_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal filt2_c_empty_n : STD_LOGIC;
    signal filt2_c158_full_n : STD_LOGIC;
    signal filt2_c158_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal filt2_c158_empty_n : STD_LOGIC;
    signal width_c159_full_n : STD_LOGIC;
    signal width_c159_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal width_c159_empty_n : STD_LOGIC;
    signal height_c160_full_n : STD_LOGIC;
    signal height_c160_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal height_c160_empty_n : STD_LOGIC;
    signal vconv_xlim_loc_c_full_n : STD_LOGIC;
    signal vconv_xlim_loc_c_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal vconv_xlim_loc_c_empty_n : STD_LOGIC;
    signal hconv_V_full_n : STD_LOGIC;
    signal hconv_V_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal hconv_V_empty_n : STD_LOGIC;
    signal vconv_V_full_n : STD_LOGIC;
    signal vconv_V_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal vconv_V_empty_n : STD_LOGIC;
    signal height_c161_full_n : STD_LOGIC;
    signal height_c161_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal height_c161_empty_n : STD_LOGIC;
    signal vconv_xlim_loc_c162_full_n : STD_LOGIC;
    signal vconv_xlim_loc_c162_dout : STD_LOGIC_VECTOR (31 downto 0);
    signal vconv_xlim_loc_c162_empty_n : STD_LOGIC;
    signal ap_sync_done : STD_LOGIC;
    signal ap_sync_ready : STD_LOGIC;
    signal ap_sync_reg_filter11x11_strm_ent_U0_ap_ready : STD_LOGIC := '0';
    signal ap_sync_filter11x11_strm_ent_U0_ap_ready : STD_LOGIC;
    signal filter11x11_strm_ent_U0_ap_ready_count : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready : STD_LOGIC := '0';
    signal ap_sync_Loop_HConvH_proc6_U0_ap_ready : STD_LOGIC;
    signal Loop_HConvH_proc6_U0_ap_ready_count : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal start_for_Block_proc_U0_din : STD_LOGIC_VECTOR (0 downto 0);
    signal start_for_Block_proc_U0_full_n : STD_LOGIC;
    signal start_for_Block_proc_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
    signal start_for_Block_proc_U0_empty_n : STD_LOGIC;
    signal start_for_Loop_VConvH_proc_U0_din : STD_LOGIC_VECTOR (0 downto 0);
    signal start_for_Loop_VConvH_proc_U0_full_n : STD_LOGIC;
    signal start_for_Loop_VConvH_proc_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
    signal start_for_Loop_VConvH_proc_U0_empty_n : STD_LOGIC;
    signal start_for_Loop_Border_proc_U0_din : STD_LOGIC_VECTOR (0 downto 0);
    signal start_for_Loop_Border_proc_U0_full_n : STD_LOGIC;
    signal start_for_Loop_Border_proc_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
    signal start_for_Loop_Border_proc_U0_empty_n : STD_LOGIC;
    signal Loop_HConvH_proc6_U0_start_full_n : STD_LOGIC;
    signal Loop_HConvH_proc6_U0_start_write : STD_LOGIC;
    signal Loop_VConvH_proc_U0_start_full_n : STD_LOGIC;
    signal Loop_VConvH_proc_U0_start_write : STD_LOGIC;
    signal Loop_Border_proc_U0_start_full_n : STD_LOGIC;
    signal Loop_Border_proc_U0_start_write : STD_LOGIC;

    component filter11x11_strm_ent IS
    port (
        ap_clk : IN STD_LOGIC;
        ap_rst : IN STD_LOGIC;
        ap_start : IN STD_LOGIC;
        start_full_n : IN STD_LOGIC;
        ap_done : OUT STD_LOGIC;
        ap_continue : IN STD_LOGIC;
        ap_idle : OUT STD_LOGIC;
        ap_ready : OUT STD_LOGIC;
        start_out : OUT STD_LOGIC;
        start_write : OUT STD_LOGIC;
        width : IN STD_LOGIC_VECTOR (31 downto 0);
        height : IN STD_LOGIC_VECTOR (31 downto 0);
        filt1 : IN STD_LOGIC_VECTOR (31 downto 0);
        filt2 : IN STD_LOGIC_VECTOR (31 downto 0);
        width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        width_out_full_n : IN STD_LOGIC;
        width_out_write : OUT STD_LOGIC;
        width_out1_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        width_out1_full_n : IN STD_LOGIC;
        width_out1_write : OUT STD_LOGIC;
        height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        height_out_full_n : IN STD_LOGIC;
        height_out_write : OUT STD_LOGIC;
        height_out2_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        height_out2_full_n : IN STD_LOGIC;
        height_out2_write : OUT STD_LOGIC;
        filt1_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        filt1_out_full_n : IN STD_LOGIC;
        filt1_out_write : OUT STD_LOGIC;
        filt1_out3_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        filt1_out3_full_n : IN STD_LOGIC;
        filt1_out3_write : OUT STD_LOGIC;
        filt2_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        filt2_out_full_n : IN STD_LOGIC;
        filt2_out_write : OUT STD_LOGIC;
        filt2_out4_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        filt2_out4_full_n : IN STD_LOGIC;
        filt2_out4_write : OUT STD_LOGIC );
    end component;


    component Block_proc IS
    port (
        ap_clk : IN STD_LOGIC;
        ap_rst : IN STD_LOGIC;
        ap_start : IN STD_LOGIC;
        start_full_n : IN STD_LOGIC;
        ap_done : OUT STD_LOGIC;
        ap_continue : IN STD_LOGIC;
        ap_idle : OUT STD_LOGIC;
        ap_ready : OUT STD_LOGIC;
        start_out : OUT STD_LOGIC;
        start_write : OUT STD_LOGIC;
        width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        width_empty_n : IN STD_LOGIC;
        width_read : OUT STD_LOGIC;
        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        height_empty_n : IN STD_LOGIC;
        height_read : OUT STD_LOGIC;
        width_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        width_out_full_n : IN STD_LOGIC;
        width_out_write : OUT STD_LOGIC;
        height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        height_out_full_n : IN STD_LOGIC;
        height_out_write : OUT STD_LOGIC;
        vconv_xlim_out_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        vconv_xlim_out_out_full_n : IN STD_LOGIC;
        vconv_xlim_out_out_write : OUT STD_LOGIC );
    end component;


    component Loop_HConvH_proc6 IS
    port (
        ap_clk : IN STD_LOGIC;
        ap_rst : IN STD_LOGIC;
        ap_start : IN STD_LOGIC;
        ap_done : OUT STD_LOGIC;
        ap_continue : IN STD_LOGIC;
        ap_idle : OUT STD_LOGIC;
        ap_ready : OUT STD_LOGIC;
        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        height_empty_n : IN STD_LOGIC;
        height_read : OUT STD_LOGIC;
        width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        width_empty_n : IN STD_LOGIC;
        width_read : OUT STD_LOGIC;
        src_V_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
        src_V_TVALID : IN STD_LOGIC;
        src_V_TREADY : OUT STD_LOGIC;
        filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        filt1_empty_n : IN STD_LOGIC;
        filt1_read : OUT STD_LOGIC;
        filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        filt2_empty_n : IN STD_LOGIC;
        filt2_read : OUT STD_LOGIC;
        hconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        hconv_V_full_n : IN STD_LOGIC;
        hconv_V_write : OUT STD_LOGIC );
    end component;


    component Loop_VConvH_proc IS
    port (
        ap_clk : IN STD_LOGIC;
        ap_rst : IN STD_LOGIC;
        ap_start : IN STD_LOGIC;
        ap_done : OUT STD_LOGIC;
        ap_continue : IN STD_LOGIC;
        ap_idle : OUT STD_LOGIC;
        ap_ready : OUT STD_LOGIC;
        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        height_empty_n : IN STD_LOGIC;
        height_read : OUT STD_LOGIC;
        vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        vconv_xlim_loc_empty_n : IN STD_LOGIC;
        vconv_xlim_loc_read : OUT STD_LOGIC;
        hconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        hconv_V_empty_n : IN STD_LOGIC;
        hconv_V_read : OUT STD_LOGIC;
        vconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        vconv_V_full_n : IN STD_LOGIC;
        vconv_V_write : OUT STD_LOGIC;
        filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        filt1_empty_n : IN STD_LOGIC;
        filt1_read : OUT STD_LOGIC;
        filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        filt2_empty_n : IN STD_LOGIC;
        filt2_read : OUT STD_LOGIC;
        height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        height_out_full_n : IN STD_LOGIC;
        height_out_write : OUT STD_LOGIC;
        vconv_xlim_loc_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
        vconv_xlim_loc_out_full_n : IN STD_LOGIC;
        vconv_xlim_loc_out_write : OUT STD_LOGIC );
    end component;


    component Loop_Border_proc IS
    port (
        ap_clk : IN STD_LOGIC;
        ap_rst : IN STD_LOGIC;
        ap_start : IN STD_LOGIC;
        ap_done : OUT STD_LOGIC;
        ap_continue : IN STD_LOGIC;
        ap_idle : OUT STD_LOGIC;
        ap_ready : OUT STD_LOGIC;
        width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        width_empty_n : IN STD_LOGIC;
        width_read : OUT STD_LOGIC;
        height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        height_empty_n : IN STD_LOGIC;
        height_read : OUT STD_LOGIC;
        dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
        dst_V_TVALID : OUT STD_LOGIC;
        dst_V_TREADY : IN STD_LOGIC;
        vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        vconv_xlim_loc_empty_n : IN STD_LOGIC;
        vconv_xlim_loc_read : OUT STD_LOGIC;
        vconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
        vconv_V_empty_n : IN STD_LOGIC;
        vconv_V_read : OUT STD_LOGIC );
    end component;


    component fifo_w32_d2_A IS
    port (
        clk : IN STD_LOGIC;
        reset : IN STD_LOGIC;
        if_read_ce : IN STD_LOGIC;
        if_write_ce : IN STD_LOGIC;
        if_din : IN STD_LOGIC_VECTOR (31 downto 0);
        if_full_n : OUT STD_LOGIC;
        if_write : IN STD_LOGIC;
        if_dout : OUT STD_LOGIC_VECTOR (31 downto 0);
        if_empty_n : OUT STD_LOGIC;
        if_read : IN STD_LOGIC );
    end component;


    component fifo_w32_d3_A IS
    port (
        clk : IN STD_LOGIC;
        reset : IN STD_LOGIC;
        if_read_ce : IN STD_LOGIC;
        if_write_ce : IN STD_LOGIC;
        if_din : IN STD_LOGIC_VECTOR (31 downto 0);
        if_full_n : OUT STD_LOGIC;
        if_write : IN STD_LOGIC;
        if_dout : OUT STD_LOGIC_VECTOR (31 downto 0);
        if_empty_n : OUT STD_LOGIC;
        if_read : IN STD_LOGIC );
    end component;


    component start_for_Block_proc_U0 IS
    port (
        clk : IN STD_LOGIC;
        reset : IN STD_LOGIC;
        if_read_ce : IN STD_LOGIC;
        if_write_ce : IN STD_LOGIC;
        if_din : IN STD_LOGIC_VECTOR (0 downto 0);
        if_full_n : OUT STD_LOGIC;
        if_write : IN STD_LOGIC;
        if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
        if_empty_n : OUT STD_LOGIC;
        if_read : IN STD_LOGIC );
    end component;


    component start_for_Loop_VConvH_proc_U0 IS
    port (
        clk : IN STD_LOGIC;
        reset : IN STD_LOGIC;
        if_read_ce : IN STD_LOGIC;
        if_write_ce : IN STD_LOGIC;
        if_din : IN STD_LOGIC_VECTOR (0 downto 0);
        if_full_n : OUT STD_LOGIC;
        if_write : IN STD_LOGIC;
        if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
        if_empty_n : OUT STD_LOGIC;
        if_read : IN STD_LOGIC );
    end component;


    component start_for_Loop_Border_proc_U0 IS
    port (
        clk : IN STD_LOGIC;
        reset : IN STD_LOGIC;
        if_read_ce : IN STD_LOGIC;
        if_write_ce : IN STD_LOGIC;
        if_din : IN STD_LOGIC_VECTOR (0 downto 0);
        if_full_n : OUT STD_LOGIC;
        if_write : IN STD_LOGIC;
        if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
        if_empty_n : OUT STD_LOGIC;
        if_read : IN STD_LOGIC );
    end component;



begin
    filter11x11_strm_ent_U0 : component filter11x11_strm_ent
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst_n_inv,
        ap_start => filter11x11_strm_ent_U0_ap_start,
        start_full_n => filter11x11_strm_ent_U0_start_full_n,
        ap_done => filter11x11_strm_ent_U0_ap_done,
        ap_continue => filter11x11_strm_ent_U0_ap_continue,
        ap_idle => filter11x11_strm_ent_U0_ap_idle,
        ap_ready => filter11x11_strm_ent_U0_ap_ready,
        start_out => filter11x11_strm_ent_U0_start_out,
        start_write => filter11x11_strm_ent_U0_start_write,
        width => width,
        height => height,
        filt1 => filt1,
        filt2 => filt2,
        width_out_din => filter11x11_strm_ent_U0_width_out_din,
        width_out_full_n => width_c_full_n,
        width_out_write => filter11x11_strm_ent_U0_width_out_write,
        width_out1_din => filter11x11_strm_ent_U0_width_out1_din,
        width_out1_full_n => width_c155_full_n,
        width_out1_write => filter11x11_strm_ent_U0_width_out1_write,
        height_out_din => filter11x11_strm_ent_U0_height_out_din,
        height_out_full_n => height_c_full_n,
        height_out_write => filter11x11_strm_ent_U0_height_out_write,
        height_out2_din => filter11x11_strm_ent_U0_height_out2_din,
        height_out2_full_n => height_c156_full_n,
        height_out2_write => filter11x11_strm_ent_U0_height_out2_write,
        filt1_out_din => filter11x11_strm_ent_U0_filt1_out_din,
        filt1_out_full_n => filt1_c_full_n,
        filt1_out_write => filter11x11_strm_ent_U0_filt1_out_write,
        filt1_out3_din => filter11x11_strm_ent_U0_filt1_out3_din,
        filt1_out3_full_n => filt1_c157_full_n,
        filt1_out3_write => filter11x11_strm_ent_U0_filt1_out3_write,
        filt2_out_din => filter11x11_strm_ent_U0_filt2_out_din,
        filt2_out_full_n => filt2_c_full_n,
        filt2_out_write => filter11x11_strm_ent_U0_filt2_out_write,
        filt2_out4_din => filter11x11_strm_ent_U0_filt2_out4_din,
        filt2_out4_full_n => filt2_c158_full_n,
        filt2_out4_write => filter11x11_strm_ent_U0_filt2_out4_write);

    Block_proc_U0 : component Block_proc
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst_n_inv,
        ap_start => Block_proc_U0_ap_start,
        start_full_n => start_for_Loop_Border_proc_U0_full_n,
        ap_done => Block_proc_U0_ap_done,
        ap_continue => Block_proc_U0_ap_continue,
        ap_idle => Block_proc_U0_ap_idle,
        ap_ready => Block_proc_U0_ap_ready,
        start_out => Block_proc_U0_start_out,
        start_write => Block_proc_U0_start_write,
        width_dout => width_c_dout,
        width_empty_n => width_c_empty_n,
        width_read => Block_proc_U0_width_read,
        height_dout => height_c_dout,
        height_empty_n => height_c_empty_n,
        height_read => Block_proc_U0_height_read,
        width_out_din => Block_proc_U0_width_out_din,
        width_out_full_n => width_c159_full_n,
        width_out_write => Block_proc_U0_width_out_write,
        height_out_din => Block_proc_U0_height_out_din,
        height_out_full_n => height_c160_full_n,
        height_out_write => Block_proc_U0_height_out_write,
        vconv_xlim_out_out_din => Block_proc_U0_vconv_xlim_out_out_din,
        vconv_xlim_out_out_full_n => vconv_xlim_loc_c_full_n,
        vconv_xlim_out_out_write => Block_proc_U0_vconv_xlim_out_out_write);

    Loop_HConvH_proc6_U0 : component Loop_HConvH_proc6
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst_n_inv,
        ap_start => Loop_HConvH_proc6_U0_ap_start,
        ap_done => Loop_HConvH_proc6_U0_ap_done,
        ap_continue => Loop_HConvH_proc6_U0_ap_continue,
        ap_idle => Loop_HConvH_proc6_U0_ap_idle,
        ap_ready => Loop_HConvH_proc6_U0_ap_ready,
        height_dout => height_c156_dout,
        height_empty_n => height_c156_empty_n,
        height_read => Loop_HConvH_proc6_U0_height_read,
        width_dout => width_c155_dout,
        width_empty_n => width_c155_empty_n,
        width_read => Loop_HConvH_proc6_U0_width_read,
        src_V_TDATA => src_V_TDATA,
        src_V_TVALID => src_V_TVALID,
        src_V_TREADY => Loop_HConvH_proc6_U0_src_V_TREADY,
        filt1_dout => filt1_c_dout,
        filt1_empty_n => filt1_c_empty_n,
        filt1_read => Loop_HConvH_proc6_U0_filt1_read,
        filt2_dout => filt2_c_dout,
        filt2_empty_n => filt2_c_empty_n,
        filt2_read => Loop_HConvH_proc6_U0_filt2_read,
        hconv_V_din => Loop_HConvH_proc6_U0_hconv_V_din,
        hconv_V_full_n => hconv_V_full_n,
        hconv_V_write => Loop_HConvH_proc6_U0_hconv_V_write);

    Loop_VConvH_proc_U0 : component Loop_VConvH_proc
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst_n_inv,
        ap_start => Loop_VConvH_proc_U0_ap_start,
        ap_done => Loop_VConvH_proc_U0_ap_done,
        ap_continue => Loop_VConvH_proc_U0_ap_continue,
        ap_idle => Loop_VConvH_proc_U0_ap_idle,
        ap_ready => Loop_VConvH_proc_U0_ap_ready,
        height_dout => height_c160_dout,
        height_empty_n => height_c160_empty_n,
        height_read => Loop_VConvH_proc_U0_height_read,
        vconv_xlim_loc_dout => vconv_xlim_loc_c_dout,
        vconv_xlim_loc_empty_n => vconv_xlim_loc_c_empty_n,
        vconv_xlim_loc_read => Loop_VConvH_proc_U0_vconv_xlim_loc_read,
        hconv_V_dout => hconv_V_dout,
        hconv_V_empty_n => hconv_V_empty_n,
        hconv_V_read => Loop_VConvH_proc_U0_hconv_V_read,
        vconv_V_din => Loop_VConvH_proc_U0_vconv_V_din,
        vconv_V_full_n => vconv_V_full_n,
        vconv_V_write => Loop_VConvH_proc_U0_vconv_V_write,
        filt1_dout => filt1_c157_dout,
        filt1_empty_n => filt1_c157_empty_n,
        filt1_read => Loop_VConvH_proc_U0_filt1_read,
        filt2_dout => filt2_c158_dout,
        filt2_empty_n => filt2_c158_empty_n,
        filt2_read => Loop_VConvH_proc_U0_filt2_read,
        height_out_din => Loop_VConvH_proc_U0_height_out_din,
        height_out_full_n => height_c161_full_n,
        height_out_write => Loop_VConvH_proc_U0_height_out_write,
        vconv_xlim_loc_out_din => Loop_VConvH_proc_U0_vconv_xlim_loc_out_din,
        vconv_xlim_loc_out_full_n => vconv_xlim_loc_c162_full_n,
        vconv_xlim_loc_out_write => Loop_VConvH_proc_U0_vconv_xlim_loc_out_write);

    Loop_Border_proc_U0 : component Loop_Border_proc
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst_n_inv,
        ap_start => Loop_Border_proc_U0_ap_start,
        ap_done => Loop_Border_proc_U0_ap_done,
        ap_continue => Loop_Border_proc_U0_ap_continue,
        ap_idle => Loop_Border_proc_U0_ap_idle,
        ap_ready => Loop_Border_proc_U0_ap_ready,
        width_dout => width_c159_dout,
        width_empty_n => width_c159_empty_n,
        width_read => Loop_Border_proc_U0_width_read,
        height_dout => height_c161_dout,
        height_empty_n => height_c161_empty_n,
        height_read => Loop_Border_proc_U0_height_read,
        dst_V_TDATA => Loop_Border_proc_U0_dst_V_TDATA,
        dst_V_TVALID => Loop_Border_proc_U0_dst_V_TVALID,
        dst_V_TREADY => dst_V_TREADY,
        vconv_xlim_loc_dout => vconv_xlim_loc_c162_dout,
        vconv_xlim_loc_empty_n => vconv_xlim_loc_c162_empty_n,
        vconv_xlim_loc_read => Loop_Border_proc_U0_vconv_xlim_loc_read,
        vconv_V_dout => vconv_V_dout,
        vconv_V_empty_n => vconv_V_empty_n,
        vconv_V_read => Loop_Border_proc_U0_vconv_V_read);

    width_c_U : component fifo_w32_d2_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => filter11x11_strm_ent_U0_width_out_din,
        if_full_n => width_c_full_n,
        if_write => filter11x11_strm_ent_U0_width_out_write,
        if_dout => width_c_dout,
        if_empty_n => width_c_empty_n,
        if_read => Block_proc_U0_width_read);

    width_c155_U : component fifo_w32_d2_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => filter11x11_strm_ent_U0_width_out1_din,
        if_full_n => width_c155_full_n,
        if_write => filter11x11_strm_ent_U0_width_out1_write,
        if_dout => width_c155_dout,
        if_empty_n => width_c155_empty_n,
        if_read => Loop_HConvH_proc6_U0_width_read);

    height_c_U : component fifo_w32_d2_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => filter11x11_strm_ent_U0_height_out_din,
        if_full_n => height_c_full_n,
        if_write => filter11x11_strm_ent_U0_height_out_write,
        if_dout => height_c_dout,
        if_empty_n => height_c_empty_n,
        if_read => Block_proc_U0_height_read);

    height_c156_U : component fifo_w32_d2_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => filter11x11_strm_ent_U0_height_out2_din,
        if_full_n => height_c156_full_n,
        if_write => filter11x11_strm_ent_U0_height_out2_write,
        if_dout => height_c156_dout,
        if_empty_n => height_c156_empty_n,
        if_read => Loop_HConvH_proc6_U0_height_read);

    filt1_c_U : component fifo_w32_d2_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => filter11x11_strm_ent_U0_filt1_out_din,
        if_full_n => filt1_c_full_n,
        if_write => filter11x11_strm_ent_U0_filt1_out_write,
        if_dout => filt1_c_dout,
        if_empty_n => filt1_c_empty_n,
        if_read => Loop_HConvH_proc6_U0_filt1_read);

    filt1_c157_U : component fifo_w32_d3_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => filter11x11_strm_ent_U0_filt1_out3_din,
        if_full_n => filt1_c157_full_n,
        if_write => filter11x11_strm_ent_U0_filt1_out3_write,
        if_dout => filt1_c157_dout,
        if_empty_n => filt1_c157_empty_n,
        if_read => Loop_VConvH_proc_U0_filt1_read);

    filt2_c_U : component fifo_w32_d2_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => filter11x11_strm_ent_U0_filt2_out_din,
        if_full_n => filt2_c_full_n,
        if_write => filter11x11_strm_ent_U0_filt2_out_write,
        if_dout => filt2_c_dout,
        if_empty_n => filt2_c_empty_n,
        if_read => Loop_HConvH_proc6_U0_filt2_read);

    filt2_c158_U : component fifo_w32_d3_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => filter11x11_strm_ent_U0_filt2_out4_din,
        if_full_n => filt2_c158_full_n,
        if_write => filter11x11_strm_ent_U0_filt2_out4_write,
        if_dout => filt2_c158_dout,
        if_empty_n => filt2_c158_empty_n,
        if_read => Loop_VConvH_proc_U0_filt2_read);

    width_c159_U : component fifo_w32_d3_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => Block_proc_U0_width_out_din,
        if_full_n => width_c159_full_n,
        if_write => Block_proc_U0_width_out_write,
        if_dout => width_c159_dout,
        if_empty_n => width_c159_empty_n,
        if_read => Loop_Border_proc_U0_width_read);

    height_c160_U : component fifo_w32_d2_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => Block_proc_U0_height_out_din,
        if_full_n => height_c160_full_n,
        if_write => Block_proc_U0_height_out_write,
        if_dout => height_c160_dout,
        if_empty_n => height_c160_empty_n,
        if_read => Loop_VConvH_proc_U0_height_read);

    vconv_xlim_loc_c_U : component fifo_w32_d2_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => Block_proc_U0_vconv_xlim_out_out_din,
        if_full_n => vconv_xlim_loc_c_full_n,
        if_write => Block_proc_U0_vconv_xlim_out_out_write,
        if_dout => vconv_xlim_loc_c_dout,
        if_empty_n => vconv_xlim_loc_c_empty_n,
        if_read => Loop_VConvH_proc_U0_vconv_xlim_loc_read);

    hconv_V_U : component fifo_w32_d2_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => Loop_HConvH_proc6_U0_hconv_V_din,
        if_full_n => hconv_V_full_n,
        if_write => Loop_HConvH_proc6_U0_hconv_V_write,
        if_dout => hconv_V_dout,
        if_empty_n => hconv_V_empty_n,
        if_read => Loop_VConvH_proc_U0_hconv_V_read);

    vconv_V_U : component fifo_w32_d2_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => Loop_VConvH_proc_U0_vconv_V_din,
        if_full_n => vconv_V_full_n,
        if_write => Loop_VConvH_proc_U0_vconv_V_write,
        if_dout => vconv_V_dout,
        if_empty_n => vconv_V_empty_n,
        if_read => Loop_Border_proc_U0_vconv_V_read);

    height_c161_U : component fifo_w32_d2_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => Loop_VConvH_proc_U0_height_out_din,
        if_full_n => height_c161_full_n,
        if_write => Loop_VConvH_proc_U0_height_out_write,
        if_dout => height_c161_dout,
        if_empty_n => height_c161_empty_n,
        if_read => Loop_Border_proc_U0_height_read);

    vconv_xlim_loc_c162_U : component fifo_w32_d2_A
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => Loop_VConvH_proc_U0_vconv_xlim_loc_out_din,
        if_full_n => vconv_xlim_loc_c162_full_n,
        if_write => Loop_VConvH_proc_U0_vconv_xlim_loc_out_write,
        if_dout => vconv_xlim_loc_c162_dout,
        if_empty_n => vconv_xlim_loc_c162_empty_n,
        if_read => Loop_Border_proc_U0_vconv_xlim_loc_read);

    start_for_Block_proc_U0_U : component start_for_Block_proc_U0
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => start_for_Block_proc_U0_din,
        if_full_n => start_for_Block_proc_U0_full_n,
        if_write => filter11x11_strm_ent_U0_start_write,
        if_dout => start_for_Block_proc_U0_dout,
        if_empty_n => start_for_Block_proc_U0_empty_n,
        if_read => Block_proc_U0_ap_ready);

    start_for_Loop_VConvH_proc_U0_U : component start_for_Loop_VConvH_proc_U0
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => start_for_Loop_VConvH_proc_U0_din,
        if_full_n => start_for_Loop_VConvH_proc_U0_full_n,
        if_write => filter11x11_strm_ent_U0_start_write,
        if_dout => start_for_Loop_VConvH_proc_U0_dout,
        if_empty_n => start_for_Loop_VConvH_proc_U0_empty_n,
        if_read => Loop_VConvH_proc_U0_ap_ready);

    start_for_Loop_Border_proc_U0_U : component start_for_Loop_Border_proc_U0
    port map (
        clk => ap_clk,
        reset => ap_rst_n_inv,
        if_read_ce => ap_const_logic_1,
        if_write_ce => ap_const_logic_1,
        if_din => start_for_Loop_Border_proc_U0_din,
        if_full_n => start_for_Loop_Border_proc_U0_full_n,
        if_write => Block_proc_U0_start_write,
        if_dout => start_for_Loop_Border_proc_U0_dout,
        if_empty_n => start_for_Loop_Border_proc_U0_empty_n,
        if_read => Loop_Border_proc_U0_ap_ready);





    ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst_n_inv = '1') then
                ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready <= ap_const_logic_0;
            else
                if (((ap_sync_ready and ap_start) = ap_const_logic_1)) then 
                    ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready <= ap_const_logic_0;
                else 
                    ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready <= ap_sync_Loop_HConvH_proc6_U0_ap_ready;
                end if; 
            end if;
        end if;
    end process;


    ap_sync_reg_filter11x11_strm_ent_U0_ap_ready_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst_n_inv = '1') then
                ap_sync_reg_filter11x11_strm_ent_U0_ap_ready <= ap_const_logic_0;
            else
                if (((ap_sync_ready and ap_start) = ap_const_logic_1)) then 
                    ap_sync_reg_filter11x11_strm_ent_U0_ap_ready <= ap_const_logic_0;
                else 
                    ap_sync_reg_filter11x11_strm_ent_U0_ap_ready <= ap_sync_filter11x11_strm_ent_U0_ap_ready;
                end if; 
            end if;
        end if;
    end process;


    Loop_HConvH_proc6_U0_ap_ready_count_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_0 = Loop_HConvH_proc6_U0_ap_ready) and (ap_sync_ready = ap_const_logic_1))) then 
                Loop_HConvH_proc6_U0_ap_ready_count <= std_logic_vector(unsigned(Loop_HConvH_proc6_U0_ap_ready_count) - unsigned(ap_const_lv2_1));
            elsif (((ap_const_logic_1 = Loop_HConvH_proc6_U0_ap_ready) and (ap_sync_ready = ap_const_logic_0))) then 
                Loop_HConvH_proc6_U0_ap_ready_count <= std_logic_vector(unsigned(Loop_HConvH_proc6_U0_ap_ready_count) + unsigned(ap_const_lv2_1));
            end if; 
        end if;
    end process;

    filter11x11_strm_ent_U0_ap_ready_count_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_sync_ready = ap_const_logic_1) and (filter11x11_strm_ent_U0_ap_ready = ap_const_logic_0))) then 
                filter11x11_strm_ent_U0_ap_ready_count <= std_logic_vector(unsigned(filter11x11_strm_ent_U0_ap_ready_count) - unsigned(ap_const_lv2_1));
            elsif (((ap_sync_ready = ap_const_logic_0) and (filter11x11_strm_ent_U0_ap_ready = ap_const_logic_1))) then 
                filter11x11_strm_ent_U0_ap_ready_count <= std_logic_vector(unsigned(filter11x11_strm_ent_U0_ap_ready_count) + unsigned(ap_const_lv2_1));
            end if; 
        end if;
    end process;
    Block_proc_U0_ap_continue <= ap_const_logic_1;
    Block_proc_U0_ap_start <= start_for_Block_proc_U0_empty_n;
    Loop_Border_proc_U0_ap_continue <= ap_const_logic_1;
    Loop_Border_proc_U0_ap_start <= start_for_Loop_Border_proc_U0_empty_n;
    Loop_Border_proc_U0_start_full_n <= ap_const_logic_1;
    Loop_Border_proc_U0_start_write <= ap_const_logic_0;
    Loop_HConvH_proc6_U0_ap_continue <= ap_const_logic_1;
    Loop_HConvH_proc6_U0_ap_start <= ((ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready xor ap_const_logic_1) and ap_start);
    Loop_HConvH_proc6_U0_start_full_n <= ap_const_logic_1;
    Loop_HConvH_proc6_U0_start_write <= ap_const_logic_0;
    Loop_VConvH_proc_U0_ap_continue <= ap_const_logic_1;
    Loop_VConvH_proc_U0_ap_start <= start_for_Loop_VConvH_proc_U0_empty_n;
    Loop_VConvH_proc_U0_start_full_n <= ap_const_logic_1;
    Loop_VConvH_proc_U0_start_write <= ap_const_logic_0;
    ap_done <= Loop_Border_proc_U0_ap_done;
    ap_idle <= (filter11x11_strm_ent_U0_ap_idle and Loop_VConvH_proc_U0_ap_idle and Loop_HConvH_proc6_U0_ap_idle and Loop_Border_proc_U0_ap_idle and Block_proc_U0_ap_idle);
    ap_ready <= ap_sync_ready;

    ap_rst_n_inv_assign_proc : process(ap_rst_n)
    begin
                ap_rst_n_inv <= not(ap_rst_n);
    end process;

    ap_sync_Loop_HConvH_proc6_U0_ap_ready <= (ap_sync_reg_Loop_HConvH_proc6_U0_ap_ready or Loop_HConvH_proc6_U0_ap_ready);
    ap_sync_continue <= ap_const_logic_1;
    ap_sync_done <= Loop_Border_proc_U0_ap_done;
    ap_sync_filter11x11_strm_ent_U0_ap_ready <= (filter11x11_strm_ent_U0_ap_ready or ap_sync_reg_filter11x11_strm_ent_U0_ap_ready);
    ap_sync_ready <= (ap_sync_filter11x11_strm_ent_U0_ap_ready and ap_sync_Loop_HConvH_proc6_U0_ap_ready);
    dst_V_TDATA <= Loop_Border_proc_U0_dst_V_TDATA;
    dst_V_TVALID <= Loop_Border_proc_U0_dst_V_TVALID;
    filter11x11_strm_ent_U0_ap_continue <= ap_const_logic_1;
    filter11x11_strm_ent_U0_ap_start <= ((ap_sync_reg_filter11x11_strm_ent_U0_ap_ready xor ap_const_logic_1) and ap_start);
    filter11x11_strm_ent_U0_start_full_n <= (start_for_Loop_VConvH_proc_U0_full_n and start_for_Block_proc_U0_full_n);
    src_V_TREADY <= Loop_HConvH_proc6_U0_src_V_TREADY;
    start_for_Block_proc_U0_din <= (0=>ap_const_logic_1, others=>'-');
    start_for_Loop_Border_proc_U0_din <= (0=>ap_const_logic_1, others=>'-');
    start_for_Loop_VConvH_proc_U0_din <= (0=>ap_const_logic_1, others=>'-');
end behav;
