-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.3
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity Loop_VConvH_proc is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_continue : IN STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
    height_empty_n : IN STD_LOGIC;
    height_read : OUT STD_LOGIC;
    vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
    vconv_xlim_loc_empty_n : IN STD_LOGIC;
    vconv_xlim_loc_read : OUT STD_LOGIC;
    hconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
    hconv_V_empty_n : IN STD_LOGIC;
    hconv_V_read : OUT STD_LOGIC;
    vconv_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
    vconv_V_full_n : IN STD_LOGIC;
    vconv_V_write : OUT STD_LOGIC;
    filt1_dout : IN STD_LOGIC_VECTOR (31 downto 0);
    filt1_empty_n : IN STD_LOGIC;
    filt1_read : OUT STD_LOGIC;
    filt2_dout : IN STD_LOGIC_VECTOR (31 downto 0);
    filt2_empty_n : IN STD_LOGIC;
    filt2_read : OUT STD_LOGIC;
    height_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
    height_out_full_n : IN STD_LOGIC;
    height_out_write : OUT STD_LOGIC;
    vconv_xlim_loc_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
    vconv_xlim_loc_out_full_n : IN STD_LOGIC;
    vconv_xlim_loc_out_write : OUT STD_LOGIC );
end;


architecture behav of Loop_VConvH_proc is 
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_logic_0 : STD_LOGIC := '0';
    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
    constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    constant ap_const_boolean_1 : BOOLEAN := true;
    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
    constant ap_const_boolean_0 : BOOLEAN := false;
    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
    constant ap_const_lv10_9 : STD_LOGIC_VECTOR (9 downto 0) := "0000001001";
    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";

    signal ap_done_reg : STD_LOGIC := '0';
    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
    attribute fsm_encoding : string;
    attribute fsm_encoding of ap_CS_fsm : signal is "none";
    signal ap_CS_fsm_state1 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
    signal linebuf_0_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_0_ce0 : STD_LOGIC;
    signal linebuf_0_q0 : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_0_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_0_ce1 : STD_LOGIC;
    signal linebuf_0_we1 : STD_LOGIC;
    signal linebuf_1_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_1_ce0 : STD_LOGIC;
    signal linebuf_1_q0 : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_1_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_1_ce1 : STD_LOGIC;
    signal linebuf_1_we1 : STD_LOGIC;
    signal linebuf_2_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_2_ce0 : STD_LOGIC;
    signal linebuf_2_q0 : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_2_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_2_ce1 : STD_LOGIC;
    signal linebuf_2_we1 : STD_LOGIC;
    signal linebuf_3_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_3_ce0 : STD_LOGIC;
    signal linebuf_3_q0 : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_3_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_3_ce1 : STD_LOGIC;
    signal linebuf_3_we1 : STD_LOGIC;
    signal linebuf_4_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_4_ce0 : STD_LOGIC;
    signal linebuf_4_q0 : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_4_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_4_ce1 : STD_LOGIC;
    signal linebuf_4_we1 : STD_LOGIC;
    signal linebuf_5_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_5_ce0 : STD_LOGIC;
    signal linebuf_5_q0 : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_5_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_5_ce1 : STD_LOGIC;
    signal linebuf_5_we1 : STD_LOGIC;
    signal linebuf_6_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_6_ce0 : STD_LOGIC;
    signal linebuf_6_q0 : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_6_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_6_ce1 : STD_LOGIC;
    signal linebuf_6_we1 : STD_LOGIC;
    signal linebuf_7_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_7_ce0 : STD_LOGIC;
    signal linebuf_7_q0 : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_7_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_7_ce1 : STD_LOGIC;
    signal linebuf_7_we1 : STD_LOGIC;
    signal linebuf_8_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_8_ce0 : STD_LOGIC;
    signal linebuf_8_q0 : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_8_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_8_ce1 : STD_LOGIC;
    signal linebuf_8_we1 : STD_LOGIC;
    signal linebuf_9_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_9_ce0 : STD_LOGIC;
    signal linebuf_9_q0 : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_9_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_9_ce1 : STD_LOGIC;
    signal linebuf_9_we1 : STD_LOGIC;
    signal height_blk_n : STD_LOGIC;
    signal vconv_xlim_loc_blk_n : STD_LOGIC;
    signal hconv_V_blk_n : STD_LOGIC;
    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
    signal ap_block_pp0_stage0 : BOOLEAN;
    signal exitcond_flatten_reg_532 : STD_LOGIC_VECTOR (0 downto 0);
    signal vconv_V_blk_n : STD_LOGIC;
    signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
    signal tmp_8_i_i_mid2_reg_541 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_8_i_i_mid2_reg_541_pp0_iter4_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal filt1_blk_n : STD_LOGIC;
    signal filt2_blk_n : STD_LOGIC;
    signal height_out_blk_n : STD_LOGIC;
    signal vconv_xlim_loc_out_blk_n : STD_LOGIC;
    signal indvar_flatten_reg_319 : STD_LOGIC_VECTOR (63 downto 0);
    signal col1_0_i_i_i_reg_330 : STD_LOGIC_VECTOR (9 downto 0);
    signal row2_0_i_i_i_reg_341 : STD_LOGIC_VECTOR (9 downto 0);
    signal height_read_reg_506 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_block_state1 : BOOLEAN;
    signal vconv_xlim_loc_read_reg_511 : STD_LOGIC_VECTOR (31 downto 0);
    signal filt1_read_reg_517 : STD_LOGIC_VECTOR (31 downto 0);
    signal filt2_read_reg_522 : STD_LOGIC_VECTOR (31 downto 0);
    signal bound_fu_358_p2 : STD_LOGIC_VECTOR (63 downto 0);
    signal bound_reg_527 : STD_LOGIC_VECTOR (63 downto 0);
    signal ap_CS_fsm_state2 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
    signal exitcond_flatten_fu_373_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
    signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
    signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
    signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
    signal ap_block_state8_pp0_stage0_iter5 : BOOLEAN;
    signal ap_block_pp0_stage0_11001 : BOOLEAN;
    signal exitcond_flatten_reg_532_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal exitcond_flatten_reg_532_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal exitcond_flatten_reg_532_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal indvar_flatten_next_fu_378_p2 : STD_LOGIC_VECTOR (63 downto 0);
    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
    signal tmp_8_i_i_mid2_fu_410_p3 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_8_i_i_mid2_reg_541_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_8_i_i_mid2_reg_541_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_8_i_i_mid2_reg_541_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal col1_0_i_i_i_mid2_fu_418_p3 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_0_addr_reg_550 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_1_addr_reg_556 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_2_addr_reg_562 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_3_addr_reg_568 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_4_addr_reg_574 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_5_addr_reg_580 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_6_addr_reg_586 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_7_addr_reg_592 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_8_addr_reg_598 : STD_LOGIC_VECTOR (9 downto 0);
    signal linebuf_9_addr_reg_604 : STD_LOGIC_VECTOR (9 downto 0);
    signal row_fu_440_p2 : STD_LOGIC_VECTOR (9 downto 0);
    signal tmp_1_reg_615 : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_5_load_reg_620 : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_5_load_reg_620_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_5_load_reg_620_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_8_load_reg_625 : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_8_load_reg_625_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
    signal linebuf_9_load_reg_630 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp2_fu_446_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp2_reg_635 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp2_reg_635_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp2_reg_635_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp2_reg_635_pp0_iter4_reg : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp3_fu_458_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp3_reg_640 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp3_reg_640_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp3_reg_640_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp3_reg_640_pp0_iter4_reg : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp7_fu_464_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp7_reg_645 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp7_reg_645_pp0_iter2_reg : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp7_reg_645_pp0_iter3_reg : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_30_9_i_i_fu_470_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_30_9_i_i_reg_650 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_30_i_i_fu_474_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_30_i_i_reg_655 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp8_fu_482_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp8_reg_660 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp5_fu_491_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp5_reg_665 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_block_pp0_stage0_subdone : BOOLEAN;
    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
    signal tmp_16_i_i_fu_426_p1 : STD_LOGIC_VECTOR (63 downto 0);
    signal ap_block_pp0_stage0_01001 : BOOLEAN;
    signal bound_fu_358_p0 : STD_LOGIC_VECTOR (31 downto 0);
    signal bound_fu_358_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal row2_0_i_cast_i_i_fu_364_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_11_i_i_fu_368_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal col_fu_392_p2 : STD_LOGIC_VECTOR (9 downto 0);
    signal tmp_8_i_i_fu_404_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_8_i_i_mid1_fu_398_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal row2_0_i_i_i_mid2_fu_384_p3 : STD_LOGIC_VECTOR (9 downto 0);
    signal tmp4_fu_452_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp9_fu_478_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp6_fu_487_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp1_fu_496_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state9 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
    signal ap_block_pp0 : BOOLEAN;
    signal ap_enable_operation_44 : BOOLEAN;
    signal ap_enable_state3_pp0_iter0_stage0 : BOOLEAN;
    signal ap_enable_operation_66 : BOOLEAN;
    signal ap_enable_state4_pp0_iter1_stage0 : BOOLEAN;
    signal ap_enable_operation_68 : BOOLEAN;
    signal ap_enable_operation_46 : BOOLEAN;
    signal ap_enable_operation_67 : BOOLEAN;
    signal ap_enable_operation_70 : BOOLEAN;
    signal ap_enable_operation_48 : BOOLEAN;
    signal ap_enable_operation_69 : BOOLEAN;
    signal ap_enable_operation_72 : BOOLEAN;
    signal ap_enable_operation_50 : BOOLEAN;
    signal ap_enable_operation_71 : BOOLEAN;
    signal ap_enable_operation_74 : BOOLEAN;
    signal ap_enable_operation_52 : BOOLEAN;
    signal ap_enable_operation_73 : BOOLEAN;
    signal ap_enable_operation_76 : BOOLEAN;
    signal ap_enable_operation_54 : BOOLEAN;
    signal ap_enable_operation_75 : BOOLEAN;
    signal ap_enable_operation_78 : BOOLEAN;
    signal ap_enable_operation_56 : BOOLEAN;
    signal ap_enable_operation_77 : BOOLEAN;
    signal ap_enable_operation_80 : BOOLEAN;
    signal ap_enable_operation_58 : BOOLEAN;
    signal ap_enable_operation_79 : BOOLEAN;
    signal ap_enable_operation_82 : BOOLEAN;
    signal ap_enable_operation_60 : BOOLEAN;
    signal ap_enable_operation_81 : BOOLEAN;
    signal ap_enable_operation_84 : BOOLEAN;
    signal ap_enable_operation_62 : BOOLEAN;
    signal ap_enable_operation_83 : BOOLEAN;
    signal ap_enable_operation_89 : BOOLEAN;
    signal ap_idle_pp0 : STD_LOGIC;
    signal ap_enable_pp0 : STD_LOGIC;
    signal bound_fu_358_p00 : STD_LOGIC_VECTOR (63 downto 0);
    signal bound_fu_358_p10 : STD_LOGIC_VECTOR (63 downto 0);

    component Loop_VConvH_proc_linebuf_0 IS
    generic (
        DataWidth : INTEGER;
        AddressRange : INTEGER;
        AddressWidth : INTEGER );
    port (
        clk : IN STD_LOGIC;
        reset : IN STD_LOGIC;
        address0 : IN STD_LOGIC_VECTOR (9 downto 0);
        ce0 : IN STD_LOGIC;
        q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
        address1 : IN STD_LOGIC_VECTOR (9 downto 0);
        ce1 : IN STD_LOGIC;
        we1 : IN STD_LOGIC;
        d1 : IN STD_LOGIC_VECTOR (31 downto 0) );
    end component;



begin
    linebuf_0_U : component Loop_VConvH_proc_linebuf_0
    generic map (
        DataWidth => 32,
        AddressRange => 672,
        AddressWidth => 10)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        address0 => linebuf_0_address0,
        ce0 => linebuf_0_ce0,
        q0 => linebuf_0_q0,
        address1 => linebuf_0_address1,
        ce1 => linebuf_0_ce1,
        we1 => linebuf_0_we1,
        d1 => linebuf_1_q0);

    linebuf_1_U : component Loop_VConvH_proc_linebuf_0
    generic map (
        DataWidth => 32,
        AddressRange => 672,
        AddressWidth => 10)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        address0 => linebuf_1_address0,
        ce0 => linebuf_1_ce0,
        q0 => linebuf_1_q0,
        address1 => linebuf_1_address1,
        ce1 => linebuf_1_ce1,
        we1 => linebuf_1_we1,
        d1 => linebuf_2_q0);

    linebuf_2_U : component Loop_VConvH_proc_linebuf_0
    generic map (
        DataWidth => 32,
        AddressRange => 672,
        AddressWidth => 10)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        address0 => linebuf_2_address0,
        ce0 => linebuf_2_ce0,
        q0 => linebuf_2_q0,
        address1 => linebuf_2_address1,
        ce1 => linebuf_2_ce1,
        we1 => linebuf_2_we1,
        d1 => linebuf_3_q0);

    linebuf_3_U : component Loop_VConvH_proc_linebuf_0
    generic map (
        DataWidth => 32,
        AddressRange => 672,
        AddressWidth => 10)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        address0 => linebuf_3_address0,
        ce0 => linebuf_3_ce0,
        q0 => linebuf_3_q0,
        address1 => linebuf_3_address1,
        ce1 => linebuf_3_ce1,
        we1 => linebuf_3_we1,
        d1 => linebuf_4_q0);

    linebuf_4_U : component Loop_VConvH_proc_linebuf_0
    generic map (
        DataWidth => 32,
        AddressRange => 672,
        AddressWidth => 10)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        address0 => linebuf_4_address0,
        ce0 => linebuf_4_ce0,
        q0 => linebuf_4_q0,
        address1 => linebuf_4_address1,
        ce1 => linebuf_4_ce1,
        we1 => linebuf_4_we1,
        d1 => linebuf_5_q0);

    linebuf_5_U : component Loop_VConvH_proc_linebuf_0
    generic map (
        DataWidth => 32,
        AddressRange => 672,
        AddressWidth => 10)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        address0 => linebuf_5_address0,
        ce0 => linebuf_5_ce0,
        q0 => linebuf_5_q0,
        address1 => linebuf_5_address1,
        ce1 => linebuf_5_ce1,
        we1 => linebuf_5_we1,
        d1 => linebuf_6_q0);

    linebuf_6_U : component Loop_VConvH_proc_linebuf_0
    generic map (
        DataWidth => 32,
        AddressRange => 672,
        AddressWidth => 10)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        address0 => linebuf_6_address0,
        ce0 => linebuf_6_ce0,
        q0 => linebuf_6_q0,
        address1 => linebuf_6_address1,
        ce1 => linebuf_6_ce1,
        we1 => linebuf_6_we1,
        d1 => linebuf_7_q0);

    linebuf_7_U : component Loop_VConvH_proc_linebuf_0
    generic map (
        DataWidth => 32,
        AddressRange => 672,
        AddressWidth => 10)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        address0 => linebuf_7_address0,
        ce0 => linebuf_7_ce0,
        q0 => linebuf_7_q0,
        address1 => linebuf_7_address1,
        ce1 => linebuf_7_ce1,
        we1 => linebuf_7_we1,
        d1 => linebuf_8_q0);

    linebuf_8_U : component Loop_VConvH_proc_linebuf_0
    generic map (
        DataWidth => 32,
        AddressRange => 672,
        AddressWidth => 10)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        address0 => linebuf_8_address0,
        ce0 => linebuf_8_ce0,
        q0 => linebuf_8_q0,
        address1 => linebuf_8_address1,
        ce1 => linebuf_8_ce1,
        we1 => linebuf_8_we1,
        d1 => linebuf_9_q0);

    linebuf_9_U : component Loop_VConvH_proc_linebuf_0
    generic map (
        DataWidth => 32,
        AddressRange => 672,
        AddressWidth => 10)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        address0 => linebuf_9_address0,
        ce0 => linebuf_9_ce0,
        q0 => linebuf_9_q0,
        address1 => linebuf_9_address1,
        ce1 => linebuf_9_ce1,
        we1 => linebuf_9_we1,
        d1 => hconv_V_dout);





    ap_CS_fsm_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_CS_fsm <= ap_ST_fsm_state1;
            else
                ap_CS_fsm <= ap_NS_fsm;
            end if;
        end if;
    end process;


    ap_done_reg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_done_reg <= ap_const_logic_0;
            else
                if ((ap_continue = ap_const_logic_1)) then 
                    ap_done_reg <= ap_const_logic_0;
                elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
                    ap_done_reg <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
            else
                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
            else
                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then 
                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
                    end if;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
            else
                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
            else
                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
            else
                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
                    ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
            else
                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
                    ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
                    ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    col1_0_i_i_i_reg_330_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
                col1_0_i_i_i_reg_330 <= col1_0_i_i_i_mid2_fu_418_p3;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
                col1_0_i_i_i_reg_330 <= ap_const_lv10_0;
            end if; 
        end if;
    end process;

    indvar_flatten_reg_319_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
                indvar_flatten_reg_319 <= indvar_flatten_next_fu_378_p2;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
                indvar_flatten_reg_319 <= ap_const_lv64_0;
            end if; 
        end if;
    end process;

    row2_0_i_i_i_reg_341_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then 
                row2_0_i_i_i_reg_341 <= row_fu_440_p2;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
                row2_0_i_i_i_reg_341 <= ap_const_lv10_0;
            end if; 
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
                bound_reg_527 <= bound_fu_358_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
                exitcond_flatten_reg_532 <= exitcond_flatten_fu_373_p2;
                exitcond_flatten_reg_532_pp0_iter1_reg <= exitcond_flatten_reg_532;
                tmp_8_i_i_mid2_reg_541_pp0_iter1_reg <= tmp_8_i_i_mid2_reg_541;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
                exitcond_flatten_reg_532_pp0_iter2_reg <= exitcond_flatten_reg_532_pp0_iter1_reg;
                exitcond_flatten_reg_532_pp0_iter3_reg <= exitcond_flatten_reg_532_pp0_iter2_reg;
                linebuf_5_load_reg_620_pp0_iter2_reg <= linebuf_5_load_reg_620;
                linebuf_5_load_reg_620_pp0_iter3_reg <= linebuf_5_load_reg_620_pp0_iter2_reg;
                linebuf_8_load_reg_625_pp0_iter2_reg <= linebuf_8_load_reg_625;
                tmp2_reg_635_pp0_iter2_reg <= tmp2_reg_635;
                tmp2_reg_635_pp0_iter3_reg <= tmp2_reg_635_pp0_iter2_reg;
                tmp2_reg_635_pp0_iter4_reg <= tmp2_reg_635_pp0_iter3_reg;
                tmp3_reg_640_pp0_iter2_reg <= tmp3_reg_640;
                tmp3_reg_640_pp0_iter3_reg <= tmp3_reg_640_pp0_iter2_reg;
                tmp3_reg_640_pp0_iter4_reg <= tmp3_reg_640_pp0_iter3_reg;
                tmp7_reg_645_pp0_iter2_reg <= tmp7_reg_645;
                tmp7_reg_645_pp0_iter3_reg <= tmp7_reg_645_pp0_iter2_reg;
                tmp_8_i_i_mid2_reg_541_pp0_iter2_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter1_reg;
                tmp_8_i_i_mid2_reg_541_pp0_iter3_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter2_reg;
                tmp_8_i_i_mid2_reg_541_pp0_iter4_reg <= tmp_8_i_i_mid2_reg_541_pp0_iter3_reg;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
                filt1_read_reg_517 <= filt1_dout;
                filt2_read_reg_522 <= filt2_dout;
                height_read_reg_506 <= height_dout;
                vconv_xlim_loc_read_reg_511 <= vconv_xlim_loc_dout;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_0))) then
                linebuf_0_addr_reg_550 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
                linebuf_1_addr_reg_556 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
                linebuf_2_addr_reg_562 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
                linebuf_3_addr_reg_568 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
                linebuf_4_addr_reg_574 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
                linebuf_5_addr_reg_580 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
                linebuf_6_addr_reg_586 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
                linebuf_7_addr_reg_592 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
                linebuf_8_addr_reg_598 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
                linebuf_9_addr_reg_604 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
                tmp_8_i_i_mid2_reg_541 <= tmp_8_i_i_mid2_fu_410_p3;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then
                linebuf_5_load_reg_620 <= linebuf_5_q0;
                linebuf_8_load_reg_625 <= linebuf_8_q0;
                linebuf_9_load_reg_630 <= linebuf_9_q0;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then
                tmp2_reg_635 <= tmp2_fu_446_p2;
                tmp3_reg_640 <= tmp3_fu_458_p2;
                tmp7_reg_645 <= tmp7_fu_464_p2;
                tmp_1_reg_615 <= hconv_V_dout;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter3_reg = ap_const_lv1_0))) then
                tmp5_reg_665 <= tmp5_fu_491_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter2_reg = ap_const_lv1_0))) then
                tmp8_reg_660 <= tmp8_fu_482_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (exitcond_flatten_reg_532_pp0_iter1_reg = ap_const_lv1_0))) then
                tmp_30_9_i_i_reg_650 <= tmp_30_9_i_i_fu_470_p2;
                tmp_30_i_i_reg_655 <= tmp_30_i_i_fu_474_p2;
            end if;
        end if;
    end process;

    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter5, exitcond_flatten_fu_373_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter4)
    begin
        case ap_CS_fsm is
            when ap_ST_fsm_state1 => 
                if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
                    ap_NS_fsm <= ap_ST_fsm_state2;
                else
                    ap_NS_fsm <= ap_ST_fsm_state1;
                end if;
            when ap_ST_fsm_state2 => 
                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
            when ap_ST_fsm_pp0_stage0 => 
                if ((not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) and not(((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1))))) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                elsif ((((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_flatten_fu_373_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)) or ((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1)))) then
                    ap_NS_fsm <= ap_ST_fsm_state9;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                end if;
            when ap_ST_fsm_state9 => 
                ap_NS_fsm <= ap_ST_fsm_state1;
            when others =>  
                ap_NS_fsm <= "XXXX";
        end case;
    end process;
    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
    ap_CS_fsm_state1 <= ap_CS_fsm(0);
    ap_CS_fsm_state2 <= ap_CS_fsm(1);
    ap_CS_fsm_state9 <= ap_CS_fsm(3);

    ap_block_pp0_assign_proc : process(ap_CS_fsm, ap_block_pp0_stage0_subdone)
    begin
                ap_block_pp0 <= ((ap_ST_fsm_pp0_stage0 = ap_CS_fsm) and (ap_const_boolean_1 = ap_block_pp0_stage0_subdone));
    end process;

        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp0_stage0_01001_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
    begin
                ap_block_pp0_stage0_01001 <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
    end process;


    ap_block_pp0_stage0_11001_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
    begin
                ap_block_pp0_stage0_11001 <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
    end process;


    ap_block_pp0_stage0_subdone_assign_proc : process(hconv_V_empty_n, vconv_V_full_n, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
    begin
                ap_block_pp0_stage0_subdone <= (((vconv_V_full_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1)) or ((hconv_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (exitcond_flatten_reg_532 = ap_const_lv1_0)));
    end process;


    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
    begin
                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
    end process;

        ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_state4_pp0_stage0_iter1_assign_proc : process(hconv_V_empty_n, exitcond_flatten_reg_532)
    begin
                ap_block_state4_pp0_stage0_iter1 <= ((hconv_V_empty_n = ap_const_logic_0) and (exitcond_flatten_reg_532 = ap_const_lv1_0));
    end process;

        ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
        ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
        ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_state8_pp0_stage0_iter5_assign_proc : process(vconv_V_full_n, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
    begin
                ap_block_state8_pp0_stage0_iter5 <= ((vconv_V_full_n = ap_const_logic_0) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1));
    end process;


    ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_flatten_fu_373_p2)
    begin
        if ((exitcond_flatten_fu_373_p2 = ap_const_lv1_1)) then 
            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
        else 
            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
        end if; 
    end process;


    ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state9)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
            ap_done <= ap_const_logic_1;
        else 
            ap_done <= ap_done_reg;
        end if; 
    end process;


    ap_enable_operation_44_assign_proc : process(exitcond_flatten_fu_373_p2)
    begin
                ap_enable_operation_44 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
    end process;


    ap_enable_operation_46_assign_proc : process(exitcond_flatten_fu_373_p2)
    begin
                ap_enable_operation_46 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
    end process;


    ap_enable_operation_48_assign_proc : process(exitcond_flatten_fu_373_p2)
    begin
                ap_enable_operation_48 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
    end process;


    ap_enable_operation_50_assign_proc : process(exitcond_flatten_fu_373_p2)
    begin
                ap_enable_operation_50 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
    end process;


    ap_enable_operation_52_assign_proc : process(exitcond_flatten_fu_373_p2)
    begin
                ap_enable_operation_52 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
    end process;


    ap_enable_operation_54_assign_proc : process(exitcond_flatten_fu_373_p2)
    begin
                ap_enable_operation_54 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
    end process;


    ap_enable_operation_56_assign_proc : process(exitcond_flatten_fu_373_p2)
    begin
                ap_enable_operation_56 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
    end process;


    ap_enable_operation_58_assign_proc : process(exitcond_flatten_fu_373_p2)
    begin
                ap_enable_operation_58 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
    end process;


    ap_enable_operation_60_assign_proc : process(exitcond_flatten_fu_373_p2)
    begin
                ap_enable_operation_60 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
    end process;


    ap_enable_operation_62_assign_proc : process(exitcond_flatten_fu_373_p2)
    begin
                ap_enable_operation_62 <= (exitcond_flatten_fu_373_p2 = ap_const_lv1_0);
    end process;


    ap_enable_operation_66_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_66 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_67_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_67 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_68_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_68 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_69_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_69 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_70_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_70 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_71_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_71 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_72_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_72 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_73_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_73 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_74_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_74 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_75_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_75 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_76_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_76 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_77_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_77 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_78_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_78 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_79_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_79 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_80_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_80 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_81_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_81 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_82_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_82 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_83_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_83 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_84_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_84 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;


    ap_enable_operation_89_assign_proc : process(exitcond_flatten_reg_532)
    begin
                ap_enable_operation_89 <= (exitcond_flatten_reg_532 = ap_const_lv1_0);
    end process;

    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);

    ap_enable_state3_pp0_iter0_stage0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0)
    begin
                ap_enable_state3_pp0_iter0_stage0 <= ((ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0));
    end process;


    ap_enable_state4_pp0_iter1_stage0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
    begin
                ap_enable_state4_pp0_iter1_stage0 <= ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0));
    end process;


    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
    begin
        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            ap_idle <= ap_const_logic_1;
        else 
            ap_idle <= ap_const_logic_0;
        end if; 
    end process;


    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4)
    begin
        if (((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then 
            ap_idle_pp0 <= ap_const_logic_1;
        else 
            ap_idle_pp0 <= ap_const_logic_0;
        end if; 
    end process;


    ap_ready_assign_proc : process(ap_CS_fsm_state9)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
            ap_ready <= ap_const_logic_1;
        else 
            ap_ready <= ap_const_logic_0;
        end if; 
    end process;

    bound_fu_358_p0 <= bound_fu_358_p00(32 - 1 downto 0);
    bound_fu_358_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(vconv_xlim_loc_read_reg_511),64));
    bound_fu_358_p1 <= bound_fu_358_p10(32 - 1 downto 0);
    bound_fu_358_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(height_read_reg_506),64));
    bound_fu_358_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_358_p0) * unsigned(bound_fu_358_p1), 64));
    col1_0_i_i_i_mid2_fu_418_p3 <= 
        col1_0_i_i_i_reg_330 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
        col_fu_392_p2;
    col_fu_392_p2 <= std_logic_vector(unsigned(col1_0_i_i_i_reg_330) + unsigned(ap_const_lv10_1));
    exitcond_flatten_fu_373_p2 <= "1" when (indvar_flatten_reg_319 = bound_reg_527) else "0";

    filt1_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt1_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            filt1_blk_n <= filt1_empty_n;
        else 
            filt1_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    filt1_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            filt1_read <= ap_const_logic_1;
        else 
            filt1_read <= ap_const_logic_0;
        end if; 
    end process;


    filt2_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, filt2_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            filt2_blk_n <= filt2_empty_n;
        else 
            filt2_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    filt2_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            filt2_read <= ap_const_logic_1;
        else 
            filt2_read <= ap_const_logic_0;
        end if; 
    end process;


    hconv_V_blk_n_assign_proc : process(hconv_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_flatten_reg_532)
    begin
        if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
            hconv_V_blk_n <= hconv_V_empty_n;
        else 
            hconv_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    hconv_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
            hconv_V_read <= ap_const_logic_1;
        else 
            hconv_V_read <= ap_const_logic_0;
        end if; 
    end process;


    height_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            height_blk_n <= height_empty_n;
        else 
            height_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    height_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_out_full_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            height_out_blk_n <= height_out_full_n;
        else 
            height_out_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    height_out_din <= height_dout;

    height_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            height_out_write <= ap_const_logic_1;
        else 
            height_out_write <= ap_const_logic_0;
        end if; 
    end process;


    height_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            height_read <= ap_const_logic_1;
        else 
            height_read <= ap_const_logic_0;
        end if; 
    end process;

    indvar_flatten_next_fu_378_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_319) + unsigned(ap_const_lv64_1));
    linebuf_0_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
    linebuf_0_address1 <= linebuf_0_addr_reg_550;

    linebuf_0_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_0_ce0 <= ap_const_logic_1;
        else 
            linebuf_0_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_0_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_0_ce1 <= ap_const_logic_1;
        else 
            linebuf_0_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_0_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
            linebuf_0_we1 <= ap_const_logic_1;
        else 
            linebuf_0_we1 <= ap_const_logic_0;
        end if; 
    end process;

    linebuf_1_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
    linebuf_1_address1 <= linebuf_1_addr_reg_556;

    linebuf_1_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_1_ce0 <= ap_const_logic_1;
        else 
            linebuf_1_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_1_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_1_ce1 <= ap_const_logic_1;
        else 
            linebuf_1_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_1_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
            linebuf_1_we1 <= ap_const_logic_1;
        else 
            linebuf_1_we1 <= ap_const_logic_0;
        end if; 
    end process;

    linebuf_2_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
    linebuf_2_address1 <= linebuf_2_addr_reg_562;

    linebuf_2_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_2_ce0 <= ap_const_logic_1;
        else 
            linebuf_2_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_2_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_2_ce1 <= ap_const_logic_1;
        else 
            linebuf_2_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_2_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
            linebuf_2_we1 <= ap_const_logic_1;
        else 
            linebuf_2_we1 <= ap_const_logic_0;
        end if; 
    end process;

    linebuf_3_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
    linebuf_3_address1 <= linebuf_3_addr_reg_568;

    linebuf_3_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_3_ce0 <= ap_const_logic_1;
        else 
            linebuf_3_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_3_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_3_ce1 <= ap_const_logic_1;
        else 
            linebuf_3_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_3_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
            linebuf_3_we1 <= ap_const_logic_1;
        else 
            linebuf_3_we1 <= ap_const_logic_0;
        end if; 
    end process;

    linebuf_4_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
    linebuf_4_address1 <= linebuf_4_addr_reg_574;

    linebuf_4_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_4_ce0 <= ap_const_logic_1;
        else 
            linebuf_4_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_4_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_4_ce1 <= ap_const_logic_1;
        else 
            linebuf_4_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_4_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
            linebuf_4_we1 <= ap_const_logic_1;
        else 
            linebuf_4_we1 <= ap_const_logic_0;
        end if; 
    end process;

    linebuf_5_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
    linebuf_5_address1 <= linebuf_5_addr_reg_580;

    linebuf_5_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_5_ce0 <= ap_const_logic_1;
        else 
            linebuf_5_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_5_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_5_ce1 <= ap_const_logic_1;
        else 
            linebuf_5_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_5_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
            linebuf_5_we1 <= ap_const_logic_1;
        else 
            linebuf_5_we1 <= ap_const_logic_0;
        end if; 
    end process;

    linebuf_6_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
    linebuf_6_address1 <= linebuf_6_addr_reg_586;

    linebuf_6_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_6_ce0 <= ap_const_logic_1;
        else 
            linebuf_6_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_6_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_6_ce1 <= ap_const_logic_1;
        else 
            linebuf_6_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_6_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
            linebuf_6_we1 <= ap_const_logic_1;
        else 
            linebuf_6_we1 <= ap_const_logic_0;
        end if; 
    end process;

    linebuf_7_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
    linebuf_7_address1 <= linebuf_7_addr_reg_592;

    linebuf_7_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_7_ce0 <= ap_const_logic_1;
        else 
            linebuf_7_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_7_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_7_ce1 <= ap_const_logic_1;
        else 
            linebuf_7_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_7_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
            linebuf_7_we1 <= ap_const_logic_1;
        else 
            linebuf_7_we1 <= ap_const_logic_0;
        end if; 
    end process;

    linebuf_8_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
    linebuf_8_address1 <= linebuf_8_addr_reg_598;

    linebuf_8_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_8_ce0 <= ap_const_logic_1;
        else 
            linebuf_8_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_8_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_8_ce1 <= ap_const_logic_1;
        else 
            linebuf_8_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_8_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
            linebuf_8_we1 <= ap_const_logic_1;
        else 
            linebuf_8_we1 <= ap_const_logic_0;
        end if; 
    end process;

    linebuf_9_address0 <= tmp_16_i_i_fu_426_p1(10 - 1 downto 0);
    linebuf_9_address1 <= linebuf_9_addr_reg_604;

    linebuf_9_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_9_ce0 <= ap_const_logic_1;
        else 
            linebuf_9_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_9_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            linebuf_9_ce1 <= ap_const_logic_1;
        else 
            linebuf_9_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    linebuf_9_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_flatten_reg_532, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_532 = ap_const_lv1_0))) then 
            linebuf_9_we1 <= ap_const_logic_1;
        else 
            linebuf_9_we1 <= ap_const_logic_0;
        end if; 
    end process;

    row2_0_i_cast_i_i_fu_364_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row2_0_i_i_i_reg_341),32));
    row2_0_i_i_i_mid2_fu_384_p3 <= 
        row2_0_i_i_i_reg_341 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
        ap_const_lv10_0;
    row_fu_440_p2 <= std_logic_vector(unsigned(row2_0_i_i_i_mid2_fu_384_p3) + unsigned(ap_const_lv10_1));
    tmp1_fu_496_p2 <= std_logic_vector(unsigned(tmp3_reg_640_pp0_iter4_reg) + unsigned(tmp2_reg_635_pp0_iter4_reg));
    tmp2_fu_446_p2 <= std_logic_vector(unsigned(linebuf_0_q0) + unsigned(linebuf_1_q0));
    tmp3_fu_458_p2 <= std_logic_vector(unsigned(tmp4_fu_452_p2) + unsigned(linebuf_2_q0));
    tmp4_fu_452_p2 <= std_logic_vector(unsigned(linebuf_3_q0) + unsigned(linebuf_4_q0));
    tmp5_fu_491_p2 <= std_logic_vector(unsigned(tmp8_reg_660) + unsigned(tmp6_fu_487_p2));
    tmp6_fu_487_p2 <= std_logic_vector(unsigned(tmp7_reg_645_pp0_iter3_reg) + unsigned(linebuf_5_load_reg_620_pp0_iter3_reg));
    tmp7_fu_464_p2 <= std_logic_vector(unsigned(linebuf_6_q0) + unsigned(linebuf_7_q0));
    tmp8_fu_482_p2 <= std_logic_vector(unsigned(tmp9_fu_478_p2) + unsigned(linebuf_8_load_reg_625_pp0_iter2_reg));
    tmp9_fu_478_p2 <= std_logic_vector(unsigned(tmp_30_9_i_i_reg_650) + unsigned(tmp_30_i_i_reg_655));
    tmp_11_i_i_fu_368_p2 <= "1" when (signed(row2_0_i_cast_i_i_fu_364_p1) < signed(vconv_xlim_loc_read_reg_511)) else "0";
    tmp_16_i_i_fu_426_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row2_0_i_i_i_mid2_fu_384_p3),64));
    tmp_30_9_i_i_fu_470_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt1_read_reg_517) * signed(linebuf_9_load_reg_630))), 32));
    tmp_30_i_i_fu_474_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(std_logic_vector(signed(filt2_read_reg_522) * signed(tmp_1_reg_615))), 32));
    tmp_8_i_i_fu_404_p2 <= "1" when (unsigned(col1_0_i_i_i_reg_330) > unsigned(ap_const_lv10_9)) else "0";
    tmp_8_i_i_mid1_fu_398_p2 <= "1" when (unsigned(col_fu_392_p2) > unsigned(ap_const_lv10_9)) else "0";
    tmp_8_i_i_mid2_fu_410_p3 <= 
        tmp_8_i_i_fu_404_p2 when (tmp_11_i_i_fu_368_p2(0) = '1') else 
        tmp_8_i_i_mid1_fu_398_p2;

    vconv_V_blk_n_assign_proc : process(vconv_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg)
    begin
        if (((ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
            vconv_V_blk_n <= vconv_V_full_n;
        else 
            vconv_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    vconv_V_din <= std_logic_vector(unsigned(tmp5_reg_665) + unsigned(tmp1_fu_496_p2));

    vconv_V_write_assign_proc : process(ap_enable_reg_pp0_iter5, tmp_8_i_i_mid2_reg_541_pp0_iter4_reg, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (tmp_8_i_i_mid2_reg_541_pp0_iter4_reg = ap_const_lv1_1))) then 
            vconv_V_write <= ap_const_logic_1;
        else 
            vconv_V_write <= ap_const_logic_0;
        end if; 
    end process;


    vconv_xlim_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            vconv_xlim_loc_blk_n <= vconv_xlim_loc_empty_n;
        else 
            vconv_xlim_loc_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    vconv_xlim_loc_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_out_full_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            vconv_xlim_loc_out_blk_n <= vconv_xlim_loc_out_full_n;
        else 
            vconv_xlim_loc_out_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    vconv_xlim_loc_out_din <= vconv_xlim_loc_dout;

    vconv_xlim_loc_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            vconv_xlim_loc_out_write <= ap_const_logic_1;
        else 
            vconv_xlim_loc_out_write <= ap_const_logic_0;
        end if; 
    end process;


    vconv_xlim_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n, vconv_xlim_loc_empty_n, filt1_empty_n, filt2_empty_n, height_out_full_n, vconv_xlim_loc_out_full_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (vconv_xlim_loc_out_full_n = ap_const_logic_0) or (height_out_full_n = ap_const_logic_0) or (filt2_empty_n = ap_const_logic_0) or (filt1_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            vconv_xlim_loc_read <= ap_const_logic_1;
        else 
            vconv_xlim_loc_read <= ap_const_logic_0;
        end if; 
    end process;

end behav;
