-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.3
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity Loop_Border_proc is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_continue : IN STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    width_dout : IN STD_LOGIC_VECTOR (31 downto 0);
    width_empty_n : IN STD_LOGIC;
    width_read : OUT STD_LOGIC;
    height_dout : IN STD_LOGIC_VECTOR (31 downto 0);
    height_empty_n : IN STD_LOGIC;
    height_read : OUT STD_LOGIC;
    dst_V_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
    dst_V_TVALID : OUT STD_LOGIC;
    dst_V_TREADY : IN STD_LOGIC;
    vconv_xlim_loc_dout : IN STD_LOGIC_VECTOR (31 downto 0);
    vconv_xlim_loc_empty_n : IN STD_LOGIC;
    vconv_xlim_loc_read : OUT STD_LOGIC;
    vconv_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
    vconv_V_empty_n : IN STD_LOGIC;
    vconv_V_read : OUT STD_LOGIC );
end;


architecture behav of Loop_Border_proc is 
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_logic_0 : STD_LOGIC := '0';
    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    constant ap_const_boolean_1 : BOOLEAN := true;
    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
    constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
    constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
    constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
    constant ap_const_boolean_0 : BOOLEAN := false;
    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
    constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
    constant ap_const_lv32_FFFFFFF5 : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111110101";
    constant ap_const_lv32_FFFFFFFA : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111010";
    constant ap_const_lv32_FFFFFFFB : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111011";
    constant ap_const_lv10_5 : STD_LOGIC_VECTOR (9 downto 0) := "0000000101";
    constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
    constant ap_const_lv10_6 : STD_LOGIC_VECTOR (9 downto 0) := "0000000110";
    constant ap_const_lv10_3FB : STD_LOGIC_VECTOR (9 downto 0) := "1111111011";
    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";

    signal ap_done_reg : STD_LOGIC := '0';
    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
    attribute fsm_encoding : string;
    attribute fsm_encoding of ap_CS_fsm : signal is "none";
    signal ap_CS_fsm_state1 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
    signal dst_V_1_data_out : STD_LOGIC_VECTOR (31 downto 0);
    signal dst_V_1_vld_in : STD_LOGIC;
    signal dst_V_1_vld_out : STD_LOGIC;
    signal dst_V_1_ack_in : STD_LOGIC;
    signal dst_V_1_ack_out : STD_LOGIC;
    signal dst_V_1_payload_A : STD_LOGIC_VECTOR (31 downto 0);
    signal dst_V_1_payload_B : STD_LOGIC_VECTOR (31 downto 0);
    signal dst_V_1_sel_rd : STD_LOGIC := '0';
    signal dst_V_1_sel_wr : STD_LOGIC := '0';
    signal dst_V_1_sel : STD_LOGIC;
    signal dst_V_1_load_A : STD_LOGIC;
    signal dst_V_1_load_B : STD_LOGIC;
    signal dst_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal dst_V_1_state_cmp_full : STD_LOGIC;
    signal width_blk_n : STD_LOGIC;
    signal height_blk_n : STD_LOGIC;
    signal dst_V_TDATA_blk_n : STD_LOGIC;
    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
    signal ap_block_pp0_stage0 : BOOLEAN;
    signal exitcond_flatten_reg_499 : STD_LOGIC_VECTOR (0 downto 0);
    signal exitcond_flatten_reg_499_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
    signal exitcond_flatten_reg_499_pp0_iter3_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal vconv_xlim_loc_blk_n : STD_LOGIC;
    signal vconv_V_blk_n : STD_LOGIC;
    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
    signal brmerge_mid2_reg_516 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_24_i_i_reg_525 : STD_LOGIC_VECTOR (0 downto 0);
    signal indvar_flatten_reg_145 : STD_LOGIC_VECTOR (63 downto 0);
    signal i6_0_i_i_i_reg_156 : STD_LOGIC_VECTOR (9 downto 0);
    signal j_0_i_i_i_reg_167 : STD_LOGIC_VECTOR (9 downto 0);
    signal width_read_reg_459 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_block_state1 : BOOLEAN;
    signal height_read_reg_467 : STD_LOGIC_VECTOR (31 downto 0);
    signal vconv_xlim_loc_read_reg_473 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_9_i_i_fu_178_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_9_i_i_reg_478 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state2 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
    signal tmp_i_i_fu_183_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_i_i_reg_483 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_7_i_i_fu_188_p2 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_7_i_i_reg_488 : STD_LOGIC_VECTOR (31 downto 0);
    signal bound_fu_199_p2 : STD_LOGIC_VECTOR (63 downto 0);
    signal bound_reg_494 : STD_LOGIC_VECTOR (63 downto 0);
    signal exitcond_flatten_fu_247_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
    signal ap_predicate_op59_read_state4 : BOOLEAN;
    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
    signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
    signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
    signal ap_block_state6_io : BOOLEAN;
    signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
    signal ap_block_state7_io : BOOLEAN;
    signal ap_block_pp0_stage0_11001 : BOOLEAN;
    signal exitcond_flatten_reg_499_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal indvar_flatten_next_fu_252_p2 : STD_LOGIC_VECTOR (63 downto 0);
    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
    signal j_0_i_i_i_mid2_fu_268_p3 : STD_LOGIC_VECTOR (9 downto 0);
    signal j_0_i_i_i_mid2_reg_508 : STD_LOGIC_VECTOR (9 downto 0);
    signal brmerge_mid2_fu_305_p3 : STD_LOGIC_VECTOR (0 downto 0);
    signal brmerge_mid2_reg_516_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal i6_0_i_i_i_mid2_fu_317_p3 : STD_LOGIC_VECTOR (9 downto 0);
    signal tmp_24_i_i_fu_325_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_28_i_i_fu_330_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_28_i_i_reg_529 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_28_i_i_reg_529_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_30_i_i_fu_335_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_30_i_i_reg_534 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_30_i_i_reg_534_pp0_iter1_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_30_i_i_reg_534_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal j_fu_340_p2 : STD_LOGIC_VECTOR (9 downto 0);
    signal tmp_27_i_i_fu_355_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_27_i_i_reg_544 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_29_i_i_fu_360_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_29_i_i_reg_549 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_29_i_i_reg_549_pp0_iter2_reg : STD_LOGIC_VECTOR (0 downto 0);
    signal borderbuf_q1 : STD_LOGIC_VECTOR (31 downto 0);
    signal pix_out_7_reg_560 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
    signal pix_out_8_fu_431_p3 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_block_pp0_stage0_subdone : BOOLEAN;
    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
    signal borderbuf_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal borderbuf_ce0 : STD_LOGIC;
    signal borderbuf_we0 : STD_LOGIC;
    signal borderbuf_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal borderbuf_ce1 : STD_LOGIC;
    signal tmp_26_i_i_fu_346_p1 : STD_LOGIC_VECTOR (63 downto 0);
    signal tmp_32_i_i_fu_370_p1 : STD_LOGIC_VECTOR (63 downto 0);
    signal r_edge_pix_fu_74 : STD_LOGIC_VECTOR (31 downto 0);
    signal pix_out_fu_78 : STD_LOGIC_VECTOR (31 downto 0);
    signal l_edge_pix_fu_391_p3 : STD_LOGIC_VECTOR (31 downto 0);
    signal pix_out_1_fu_82 : STD_LOGIC_VECTOR (31 downto 0);
    signal pix_in_2_l_edge_pix_s_fu_384_p3 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_block_pp0_stage0_01001 : BOOLEAN;
    signal bound_fu_199_p0 : STD_LOGIC_VECTOR (31 downto 0);
    signal bound_fu_199_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal i6_0_i_cast_i_i_mid1_fu_205_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal notrhs_fu_221_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal notlhs_fu_215_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_17_i_i_fu_209_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal brmerge_i_i_i_not_fu_226_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal j_0_i_cast_i_i_fu_238_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal i_fu_258_p2 : STD_LOGIC_VECTOR (9 downto 0);
    signal tmp_22_i_i_fu_242_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal i6_0_i_cast_i_i_fu_264_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal notrhs_mid1_fu_288_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal notlhs_mid1_fu_282_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_17_i_i_mid1_fu_276_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal brmerge_i_i_i_not_mi_fu_293_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal brmerge_fu_232_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal brmerge_mid1_fu_299_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal j_0_i_cast_i_i_mid2_s_fu_313_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal tmp_31_i_i_fu_365_p2 : STD_LOGIC_VECTOR (9 downto 0);
    signal sel_tmp_fu_414_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal sel_tmp1_fu_419_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal pix_out_3_fu_424_p3 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state8 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
    signal ap_idle_pp0 : STD_LOGIC;
    signal ap_enable_pp0 : STD_LOGIC;
    signal bound_fu_199_p00 : STD_LOGIC_VECTOR (63 downto 0);
    signal bound_fu_199_p10 : STD_LOGIC_VECTOR (63 downto 0);

    component Loop_Border_proc_borderbuf IS
    generic (
        DataWidth : INTEGER;
        AddressRange : INTEGER;
        AddressWidth : INTEGER );
    port (
        clk : IN STD_LOGIC;
        reset : IN STD_LOGIC;
        address0 : IN STD_LOGIC_VECTOR (9 downto 0);
        ce0 : IN STD_LOGIC;
        we0 : IN STD_LOGIC;
        d0 : IN STD_LOGIC_VECTOR (31 downto 0);
        address1 : IN STD_LOGIC_VECTOR (9 downto 0);
        ce1 : IN STD_LOGIC;
        q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
    end component;



begin
    borderbuf_U : component Loop_Border_proc_borderbuf
    generic map (
        DataWidth => 32,
        AddressRange => 662,
        AddressWidth => 10)
    port map (
        clk => ap_clk,
        reset => ap_rst,
        address0 => borderbuf_address0,
        ce0 => borderbuf_ce0,
        we0 => borderbuf_we0,
        d0 => vconv_V_dout,
        address1 => borderbuf_address1,
        ce1 => borderbuf_ce1,
        q1 => borderbuf_q1);





    ap_CS_fsm_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_CS_fsm <= ap_ST_fsm_state1;
            else
                ap_CS_fsm <= ap_NS_fsm;
            end if;
        end if;
    end process;


    ap_done_reg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_done_reg <= ap_const_logic_0;
            else
                if ((ap_continue = ap_const_logic_1)) then 
                    ap_done_reg <= ap_const_logic_0;
                elsif (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
                    ap_done_reg <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
            else
                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
            else
                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
                    if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then 
                        ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
                    elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then 
                        ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
                    end if;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
            else
                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
            else
                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
            else
                if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
                    ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
                elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
                    ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    dst_V_1_sel_rd_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                dst_V_1_sel_rd <= ap_const_logic_0;
            else
                if (((dst_V_1_ack_out = ap_const_logic_1) and (dst_V_1_vld_out = ap_const_logic_1))) then 
                                        dst_V_1_sel_rd <= not(dst_V_1_sel_rd);
                end if; 
            end if;
        end if;
    end process;


    dst_V_1_sel_wr_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                dst_V_1_sel_wr <= ap_const_logic_0;
            else
                if (((dst_V_1_ack_in = ap_const_logic_1) and (dst_V_1_vld_in = ap_const_logic_1))) then 
                                        dst_V_1_sel_wr <= not(dst_V_1_sel_wr);
                end if; 
            end if;
        end if;
    end process;


    dst_V_1_state_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                dst_V_1_state <= ap_const_lv2_0;
            else
                if ((((dst_V_1_state = ap_const_lv2_2) and (dst_V_1_vld_in = ap_const_logic_0)) or ((dst_V_1_state = ap_const_lv2_3) and (dst_V_1_vld_in = ap_const_logic_0) and (dst_V_1_ack_out = ap_const_logic_1)))) then 
                    dst_V_1_state <= ap_const_lv2_2;
                elsif ((((dst_V_1_state = ap_const_lv2_1) and (dst_V_1_ack_out = ap_const_logic_0)) or ((dst_V_1_state = ap_const_lv2_3) and (dst_V_1_ack_out = ap_const_logic_0) and (dst_V_1_vld_in = ap_const_logic_1)))) then 
                    dst_V_1_state <= ap_const_lv2_1;
                elsif (((not(((dst_V_1_vld_in = ap_const_logic_0) and (dst_V_1_ack_out = ap_const_logic_1))) and not(((dst_V_1_ack_out = ap_const_logic_0) and (dst_V_1_vld_in = ap_const_logic_1))) and (dst_V_1_state = ap_const_lv2_3)) or ((dst_V_1_state = ap_const_lv2_1) and (dst_V_1_ack_out = ap_const_logic_1)) or ((dst_V_1_state = ap_const_lv2_2) and (dst_V_1_vld_in = ap_const_logic_1)))) then 
                    dst_V_1_state <= ap_const_lv2_3;
                else 
                    dst_V_1_state <= ap_const_lv2_2;
                end if; 
            end if;
        end if;
    end process;


    i6_0_i_i_i_reg_156_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
                i6_0_i_i_i_reg_156 <= i6_0_i_i_i_mid2_fu_317_p3;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
                i6_0_i_i_i_reg_156 <= ap_const_lv10_0;
            end if; 
        end if;
    end process;

    indvar_flatten_reg_145_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
                indvar_flatten_reg_145 <= indvar_flatten_next_fu_252_p2;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
                indvar_flatten_reg_145 <= ap_const_lv64_0;
            end if; 
        end if;
    end process;

    j_0_i_i_i_reg_167_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
                j_0_i_i_i_reg_167 <= j_fu_340_p2;
            elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
                j_0_i_i_i_reg_167 <= ap_const_lv10_0;
            end if; 
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
                bound_reg_494 <= bound_fu_199_p2;
                tmp_7_i_i_reg_488 <= tmp_7_i_i_fu_188_p2;
                tmp_9_i_i_reg_478 <= tmp_9_i_i_fu_178_p2;
                tmp_i_i_reg_483 <= tmp_i_i_fu_183_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
                brmerge_mid2_reg_516 <= brmerge_mid2_fu_305_p3;
                j_0_i_i_i_mid2_reg_508 <= j_0_i_i_i_mid2_fu_268_p3;
                tmp_30_i_i_reg_534 <= tmp_30_i_i_fu_335_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
                brmerge_mid2_reg_516_pp0_iter1_reg <= brmerge_mid2_reg_516;
                exitcond_flatten_reg_499 <= exitcond_flatten_fu_247_p2;
                exitcond_flatten_reg_499_pp0_iter1_reg <= exitcond_flatten_reg_499;
                tmp_28_i_i_reg_529_pp0_iter1_reg <= tmp_28_i_i_reg_529;
                tmp_30_i_i_reg_534_pp0_iter1_reg <= tmp_30_i_i_reg_534;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((dst_V_1_load_A = ap_const_logic_1)) then
                dst_V_1_payload_A <= pix_out_8_fu_431_p3;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((dst_V_1_load_B = ap_const_logic_1)) then
                dst_V_1_payload_B <= pix_out_8_fu_431_p3;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
                exitcond_flatten_reg_499_pp0_iter2_reg <= exitcond_flatten_reg_499_pp0_iter1_reg;
                exitcond_flatten_reg_499_pp0_iter3_reg <= exitcond_flatten_reg_499_pp0_iter2_reg;
                tmp_29_i_i_reg_549_pp0_iter2_reg <= tmp_29_i_i_reg_549;
                tmp_30_i_i_reg_534_pp0_iter2_reg <= tmp_30_i_i_reg_534_pp0_iter1_reg;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
                height_read_reg_467 <= height_dout;
                vconv_xlim_loc_read_reg_473 <= vconv_xlim_loc_dout;
                width_read_reg_459 <= width_dout;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((brmerge_mid2_reg_516_pp0_iter1_reg = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
                pix_out_1_fu_82 <= pix_in_2_l_edge_pix_s_fu_384_p3;
                pix_out_fu_78 <= l_edge_pix_fu_391_p3;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((exitcond_flatten_reg_499_pp0_iter1_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
                pix_out_7_reg_560 <= borderbuf_q1;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
                r_edge_pix_fu_74 <= vconv_V_dout;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((brmerge_mid2_fu_305_p3 = ap_const_lv1_1) and (exitcond_flatten_fu_247_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
                tmp_24_i_i_reg_525 <= tmp_24_i_i_fu_325_p2;
                tmp_28_i_i_reg_529 <= tmp_28_i_i_fu_330_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
                tmp_27_i_i_reg_544 <= tmp_27_i_i_fu_355_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((exitcond_flatten_reg_499 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
                tmp_29_i_i_reg_549 <= tmp_29_i_i_fu_360_p2;
            end if;
        end if;
    end process;

    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, width_empty_n, height_empty_n, dst_V_1_ack_in, vconv_xlim_loc_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, exitcond_flatten_fu_247_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_CS_fsm_state8)
    begin
        case ap_CS_fsm is
            when ap_ST_fsm_state1 => 
                if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
                    ap_NS_fsm <= ap_ST_fsm_state2;
                else
                    ap_NS_fsm <= ap_ST_fsm_state1;
                end if;
            when ap_ST_fsm_state2 => 
                ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
            when ap_ST_fsm_pp0_stage0 => 
                if ((not(((exitcond_flatten_fu_247_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) and not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0))))) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                elsif ((((exitcond_flatten_fu_247_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0)))) then
                    ap_NS_fsm <= ap_ST_fsm_state8;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                end if;
            when ap_ST_fsm_state8 => 
                if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then
                    ap_NS_fsm <= ap_ST_fsm_state1;
                else
                    ap_NS_fsm <= ap_ST_fsm_state8;
                end if;
            when others =>  
                ap_NS_fsm <= "XXXX";
        end case;
    end process;
    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
    ap_CS_fsm_state1 <= ap_CS_fsm(0);
    ap_CS_fsm_state2 <= ap_CS_fsm(1);
    ap_CS_fsm_state8 <= ap_CS_fsm(3);
        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp0_stage0_01001_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4)
    begin
                ap_block_pp0_stage0_01001 <= ((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
    end process;


    ap_block_pp0_stage0_11001_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_state6_io, ap_block_state7_io)
    begin
                ap_block_pp0_stage0_11001 <= (((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state7_io) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state6_io) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)));
    end process;


    ap_block_pp0_stage0_subdone_assign_proc : process(vconv_V_empty_n, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_state6_io, ap_block_state7_io)
    begin
                ap_block_pp0_stage0_subdone <= (((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state7_io) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1)) or ((ap_const_boolean_1 = ap_block_state6_io) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1)));
    end process;


    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
    begin
                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
    end process;

        ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_state4_pp0_stage0_iter1_assign_proc : process(vconv_V_empty_n, ap_predicate_op59_read_state4)
    begin
                ap_block_state4_pp0_stage0_iter1 <= ((vconv_V_empty_n = ap_const_logic_0) and (ap_predicate_op59_read_state4 = ap_const_boolean_1));
    end process;

        ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_state6_io_assign_proc : process(dst_V_1_ack_in, exitcond_flatten_reg_499_pp0_iter2_reg)
    begin
                ap_block_state6_io <= ((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (dst_V_1_ack_in = ap_const_logic_0));
    end process;

        ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_state7_io_assign_proc : process(dst_V_1_ack_in, exitcond_flatten_reg_499_pp0_iter3_reg)
    begin
                ap_block_state7_io <= ((exitcond_flatten_reg_499_pp0_iter3_reg = ap_const_lv1_0) and (dst_V_1_ack_in = ap_const_logic_0));
    end process;

        ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_flatten_fu_247_p2)
    begin
        if ((exitcond_flatten_fu_247_p2 = ap_const_lv1_1)) then 
            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
        else 
            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
        end if; 
    end process;


    ap_done_assign_proc : process(ap_done_reg, dst_V_1_ack_in, ap_CS_fsm_state8)
    begin
        if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
            ap_done <= ap_const_logic_1;
        else 
            ap_done <= ap_done_reg;
        end if; 
    end process;

    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);

    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
    begin
        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            ap_idle <= ap_const_logic_1;
        else 
            ap_idle <= ap_const_logic_0;
        end if; 
    end process;


    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2)
    begin
        if (((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0))) then 
            ap_idle_pp0 <= ap_const_logic_1;
        else 
            ap_idle_pp0 <= ap_const_logic_0;
        end if; 
    end process;


    ap_predicate_op59_read_state4_assign_proc : process(brmerge_mid2_reg_516, tmp_24_i_i_reg_525)
    begin
                ap_predicate_op59_read_state4 <= ((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1));
    end process;


    ap_ready_assign_proc : process(dst_V_1_ack_in, ap_CS_fsm_state8)
    begin
        if (((dst_V_1_ack_in = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state8))) then 
            ap_ready <= ap_const_logic_1;
        else 
            ap_ready <= ap_const_logic_0;
        end if; 
    end process;

    borderbuf_address0 <= tmp_26_i_i_fu_346_p1(10 - 1 downto 0);
    borderbuf_address1 <= tmp_32_i_i_fu_370_p1(10 - 1 downto 0);

    borderbuf_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            borderbuf_ce0 <= ap_const_logic_1;
        else 
            borderbuf_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    borderbuf_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
    begin
        if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            borderbuf_ce1 <= ap_const_logic_1;
        else 
            borderbuf_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    borderbuf_we0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, brmerge_mid2_reg_516, tmp_24_i_i_reg_525, ap_block_pp0_stage0_11001)
    begin
        if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            borderbuf_we0 <= ap_const_logic_1;
        else 
            borderbuf_we0 <= ap_const_logic_0;
        end if; 
    end process;

    bound_fu_199_p0 <= bound_fu_199_p00(32 - 1 downto 0);
    bound_fu_199_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(width_read_reg_459),64));
    bound_fu_199_p1 <= bound_fu_199_p10(32 - 1 downto 0);
    bound_fu_199_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(height_read_reg_467),64));
    bound_fu_199_p2 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bound_fu_199_p0) * unsigned(bound_fu_199_p1), 64));
    brmerge_fu_232_p2 <= (tmp_17_i_i_fu_209_p2 or brmerge_i_i_i_not_fu_226_p2);
    brmerge_i_i_i_not_fu_226_p2 <= (notrhs_fu_221_p2 and notlhs_fu_215_p2);
    brmerge_i_i_i_not_mi_fu_293_p2 <= (notrhs_mid1_fu_288_p2 and notlhs_mid1_fu_282_p2);
    brmerge_mid1_fu_299_p2 <= (tmp_17_i_i_mid1_fu_276_p2 or brmerge_i_i_i_not_mi_fu_293_p2);
    brmerge_mid2_fu_305_p3 <= 
        brmerge_fu_232_p2 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
        brmerge_mid1_fu_299_p2;
    dst_V_1_ack_in <= dst_V_1_state(1);
    dst_V_1_ack_out <= dst_V_TREADY;

    dst_V_1_data_out_assign_proc : process(dst_V_1_payload_A, dst_V_1_payload_B, dst_V_1_sel)
    begin
        if ((dst_V_1_sel = ap_const_logic_1)) then 
            dst_V_1_data_out <= dst_V_1_payload_B;
        else 
            dst_V_1_data_out <= dst_V_1_payload_A;
        end if; 
    end process;

    dst_V_1_load_A <= (not(dst_V_1_sel_wr) and dst_V_1_state_cmp_full);
    dst_V_1_load_B <= (dst_V_1_state_cmp_full and dst_V_1_sel_wr);
    dst_V_1_sel <= dst_V_1_sel_rd;
    dst_V_1_state_cmp_full <= '0' when (dst_V_1_state = ap_const_lv2_1) else '1';

    dst_V_1_vld_in_assign_proc : process(ap_enable_reg_pp0_iter3, exitcond_flatten_reg_499_pp0_iter2_reg, ap_block_pp0_stage0_11001)
    begin
        if (((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1))) then 
            dst_V_1_vld_in <= ap_const_logic_1;
        else 
            dst_V_1_vld_in <= ap_const_logic_0;
        end if; 
    end process;

    dst_V_1_vld_out <= dst_V_1_state(0);
    dst_V_TDATA <= dst_V_1_data_out;

    dst_V_TDATA_blk_n_assign_proc : process(dst_V_1_state, ap_enable_reg_pp0_iter3, ap_block_pp0_stage0, exitcond_flatten_reg_499_pp0_iter2_reg, ap_enable_reg_pp0_iter4, exitcond_flatten_reg_499_pp0_iter3_reg)
    begin
        if ((((exitcond_flatten_reg_499_pp0_iter3_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((exitcond_flatten_reg_499_pp0_iter2_reg = ap_const_lv1_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0)))) then 
            dst_V_TDATA_blk_n <= dst_V_1_state(1);
        else 
            dst_V_TDATA_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    dst_V_TVALID <= dst_V_1_state(0);
    exitcond_flatten_fu_247_p2 <= "1" when (indvar_flatten_reg_145 = bound_reg_494) else "0";

    height_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, height_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            height_blk_n <= height_empty_n;
        else 
            height_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    height_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            height_read <= ap_const_logic_1;
        else 
            height_read <= ap_const_logic_0;
        end if; 
    end process;

    i6_0_i_cast_i_i_fu_264_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_fu_258_p2),32));
    i6_0_i_cast_i_i_mid1_fu_205_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i6_0_i_i_i_reg_156),32));
    i6_0_i_i_i_mid2_fu_317_p3 <= 
        i6_0_i_i_i_reg_156 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
        i_fu_258_p2;
    i_fu_258_p2 <= std_logic_vector(unsigned(i6_0_i_i_i_reg_156) + unsigned(ap_const_lv10_1));
    indvar_flatten_next_fu_252_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_145) + unsigned(ap_const_lv64_1));
    j_0_i_cast_i_i_fu_238_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_reg_167),32));
    j_0_i_cast_i_i_mid2_s_fu_313_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_mid2_fu_268_p3),32));
    j_0_i_i_i_mid2_fu_268_p3 <= 
        j_0_i_i_i_reg_167 when (tmp_22_i_i_fu_242_p2(0) = '1') else 
        ap_const_lv10_0;
    j_fu_340_p2 <= std_logic_vector(unsigned(j_0_i_i_i_mid2_fu_268_p3) + unsigned(ap_const_lv10_1));
    l_edge_pix_fu_391_p3 <= 
        r_edge_pix_fu_74 when (tmp_28_i_i_reg_529_pp0_iter1_reg(0) = '1') else 
        pix_out_fu_78;
    notlhs_fu_215_p2 <= "1" when (unsigned(i6_0_i_i_i_reg_156) > unsigned(ap_const_lv10_5)) else "0";
    notlhs_mid1_fu_282_p2 <= "1" when (unsigned(i_fu_258_p2) > unsigned(ap_const_lv10_5)) else "0";
    notrhs_fu_221_p2 <= "1" when (signed(i6_0_i_cast_i_i_mid1_fu_205_p1) < signed(tmp_7_i_i_reg_488)) else "0";
    notrhs_mid1_fu_288_p2 <= "1" when (signed(i6_0_i_cast_i_i_fu_264_p1) < signed(tmp_7_i_i_reg_488)) else "0";
    pix_in_2_l_edge_pix_s_fu_384_p3 <= 
        r_edge_pix_fu_74 when (tmp_27_i_i_reg_544(0) = '1') else 
        pix_out_1_fu_82;
    pix_out_3_fu_424_p3 <= 
        pix_out_7_reg_560 when (sel_tmp1_fu_419_p2(0) = '1') else 
        pix_out_fu_78;
    pix_out_8_fu_431_p3 <= 
        pix_out_1_fu_82 when (tmp_29_i_i_reg_549_pp0_iter2_reg(0) = '1') else 
        pix_out_3_fu_424_p3;
    sel_tmp1_fu_419_p2 <= (tmp_30_i_i_reg_534_pp0_iter2_reg and sel_tmp_fu_414_p2);
    sel_tmp_fu_414_p2 <= (tmp_29_i_i_reg_549_pp0_iter2_reg xor ap_const_lv1_1);
    tmp_17_i_i_fu_209_p2 <= "1" when (i6_0_i_i_i_reg_156 = ap_const_lv10_0) else "0";
    tmp_17_i_i_mid1_fu_276_p2 <= "1" when (i_fu_258_p2 = ap_const_lv10_0) else "0";
    tmp_22_i_i_fu_242_p2 <= "1" when (signed(j_0_i_cast_i_i_fu_238_p1) < signed(width_read_reg_459)) else "0";
    tmp_24_i_i_fu_325_p2 <= "1" when (signed(j_0_i_cast_i_i_mid2_s_fu_313_p1) < signed(vconv_xlim_loc_read_reg_473)) else "0";
    tmp_26_i_i_fu_346_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_i_i_mid2_reg_508),64));
    tmp_27_i_i_fu_355_p2 <= "1" when (j_0_i_i_i_mid2_reg_508 = ap_const_lv10_0) else "0";
    tmp_28_i_i_fu_330_p2 <= "1" when (j_0_i_cast_i_i_mid2_s_fu_313_p1 = tmp_9_i_i_reg_478) else "0";
    tmp_29_i_i_fu_360_p2 <= "1" when (unsigned(j_0_i_i_i_mid2_reg_508) < unsigned(ap_const_lv10_6)) else "0";
    tmp_30_i_i_fu_335_p2 <= "1" when (signed(j_0_i_cast_i_i_mid2_s_fu_313_p1) < signed(tmp_i_i_reg_483)) else "0";
    tmp_31_i_i_fu_365_p2 <= std_logic_vector(unsigned(j_0_i_i_i_mid2_reg_508) + unsigned(ap_const_lv10_3FB));
    tmp_32_i_i_fu_370_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_31_i_i_fu_365_p2),64));
    tmp_7_i_i_fu_188_p2 <= std_logic_vector(unsigned(height_read_reg_467) + unsigned(ap_const_lv32_FFFFFFFB));
    tmp_9_i_i_fu_178_p2 <= std_logic_vector(unsigned(width_read_reg_459) + unsigned(ap_const_lv32_FFFFFFF5));
    tmp_i_i_fu_183_p2 <= std_logic_vector(unsigned(width_read_reg_459) + unsigned(ap_const_lv32_FFFFFFFA));

    vconv_V_blk_n_assign_proc : process(vconv_V_empty_n, ap_block_pp0_stage0, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, brmerge_mid2_reg_516, tmp_24_i_i_reg_525)
    begin
        if (((tmp_24_i_i_reg_525 = ap_const_lv1_1) and (brmerge_mid2_reg_516 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
            vconv_V_blk_n <= vconv_V_empty_n;
        else 
            vconv_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    vconv_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_predicate_op59_read_state4, ap_block_pp0_stage0_11001)
    begin
        if (((ap_predicate_op59_read_state4 = ap_const_boolean_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            vconv_V_read <= ap_const_logic_1;
        else 
            vconv_V_read <= ap_const_logic_0;
        end if; 
    end process;


    vconv_xlim_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, vconv_xlim_loc_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            vconv_xlim_loc_blk_n <= vconv_xlim_loc_empty_n;
        else 
            vconv_xlim_loc_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    vconv_xlim_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            vconv_xlim_loc_read <= ap_const_logic_1;
        else 
            vconv_xlim_loc_read <= ap_const_logic_0;
        end if; 
    end process;


    width_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            width_blk_n <= width_empty_n;
        else 
            width_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    width_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, width_empty_n, height_empty_n, vconv_xlim_loc_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (height_empty_n = ap_const_logic_0) or (width_empty_n = ap_const_logic_0) or (vconv_xlim_loc_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            width_read <= ap_const_logic_1;
        else 
            width_read <= ap_const_logic_0;
        end if; 
    end process;

end behav;
