-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec  6 23:36:41 MST 2018
-- Date        : Mon Apr 20 19:37:36 2020
-- Host        : DESKTOP-L9P0FU6 running 64-bit Ubuntu 18.04.4 LTS
-- Command     : write_vhdl -force -mode funcsim -rename_top design_1_ethernet_transceiver2_0_0 -prefix
--               design_1_ethernet_transceiver2_0_0_ design_1_ethernet_transceiver2_0_0_sim_netlist.vhdl
-- Design      : design_1_ethernet_transceiver2_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_ethernet_transceiver2_0_0_clock_mod is
  port (
    clk50mhz : out STD_LOGIC;
    clk_out_shift : out STD_LOGIC;
    b_clk100mhz : in STD_LOGIC
  );
end design_1_ethernet_transceiver2_0_0_clock_mod;

architecture STRUCTURE of design_1_ethernet_transceiver2_0_0_clock_mod is
  signal \^clk50mhz\ : STD_LOGIC;
  signal \^clk_out_shift\ : STD_LOGIC;
  signal temp_clk_i_1_n_0 : STD_LOGIC;
  signal temp_clk_shift_i_1_n_0 : STD_LOGIC;
begin
  clk50mhz <= \^clk50mhz\;
  clk_out_shift <= \^clk_out_shift\;
temp_clk_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^clk50mhz\,
      O => temp_clk_i_1_n_0
    );
temp_clk_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => '1',
      D => temp_clk_i_1_n_0,
      Q => \^clk50mhz\,
      R => '0'
    );
temp_clk_shift_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^clk_out_shift\,
      O => temp_clk_shift_i_1_n_0
    );
temp_clk_shift_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk100mhz,
      CE => '1',
      D => temp_clk_shift_i_1_n_0,
      Q => \^clk_out_shift\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_ethernet_transceiver2_0_0_clock_mod2 is
  port (
    I : out STD_LOGIC;
    clk2_5mhz_shift : out STD_LOGIC;
    b_clk100mhz : in STD_LOGIC
  );
end design_1_ethernet_transceiver2_0_0_clock_mod2;

architecture STRUCTURE of design_1_ethernet_transceiver2_0_0_clock_mod2 is
  signal \^i\ : STD_LOGIC;
  signal \^clk2_5mhz_shift\ : STD_LOGIC;
  signal count10 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \count1[2]_i_1_n_0\ : STD_LOGIC;
  signal \count1[4]_i_1_n_0\ : STD_LOGIC;
  signal \count1[4]_i_2_n_0\ : STD_LOGIC;
  signal \count1_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \count2_inferred__0/i__n_0\ : STD_LOGIC;
  signal \count2_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal temp_clk1_i_1_n_0 : STD_LOGIC;
  signal temp_clk21_out : STD_LOGIC;
  signal temp_clk2_i_1_n_0 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count1[1]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \count1[2]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \count1[3]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \count1[4]_i_3\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \count2[0]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \count2[1]_i_1\ : label is "soft_lutpair1";
begin
  I <= \^i\;
  clk2_5mhz_shift <= \^clk2_5mhz_shift\;
\count1[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \count1_reg__0\(0),
      O => count10(0)
    );
\count1[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \count1_reg__0\(0),
      I1 => \count1_reg__0\(1),
      O => count10(1)
    );
\count1[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \count1_reg__0\(0),
      I1 => \count1_reg__0\(1),
      I2 => \count1_reg__0\(2),
      O => \count1[2]_i_1_n_0\
    );
\count1[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \count1_reg__0\(1),
      I1 => \count1_reg__0\(0),
      I2 => \count1_reg__0\(2),
      I3 => \count1_reg__0\(3),
      O => count10(3)
    );
\count1[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000080"
    )
        port map (
      I0 => \count1_reg__0\(4),
      I1 => \count1_reg__0\(0),
      I2 => \count1_reg__0\(1),
      I3 => \count1_reg__0\(3),
      I4 => \count1_reg__0\(2),
      O => \count1[4]_i_1_n_0\
    );
\count1[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"57"
    )
        port map (
      I0 => \count1_reg__0\(4),
      I1 => \count1_reg__0\(2),
      I2 => \count1_reg__0\(3),
      O => \count1[4]_i_2_n_0\
    );
\count1[4]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \count1_reg__0\(2),
      I1 => \count1_reg__0\(0),
      I2 => \count1_reg__0\(1),
      I3 => \count1_reg__0\(3),
      I4 => \count1_reg__0\(4),
      O => count10(4)
    );
\count1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => \count1[4]_i_2_n_0\,
      D => count10(0),
      Q => \count1_reg__0\(0),
      R => \count1[4]_i_1_n_0\
    );
\count1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => \count1[4]_i_2_n_0\,
      D => count10(1),
      Q => \count1_reg__0\(1),
      R => \count1[4]_i_1_n_0\
    );
\count1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => \count1[4]_i_2_n_0\,
      D => \count1[2]_i_1_n_0\,
      Q => \count1_reg__0\(2),
      R => \count1[4]_i_1_n_0\
    );
\count1_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => \count1[4]_i_2_n_0\,
      D => count10(3),
      Q => \count1_reg__0\(3),
      R => \count1[4]_i_1_n_0\
    );
\count1_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => \count1[4]_i_2_n_0\,
      D => count10(4),
      Q => \count1_reg__0\(4),
      R => \count1[4]_i_1_n_0\
    );
\count2[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0515"
    )
        port map (
      I0 => \count2_reg__0\(0),
      I1 => \count2_reg__0\(4),
      I2 => \count2_reg__0\(5),
      I3 => \count2_reg__0\(3),
      O => p_0_in(0)
    );
\count2[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"05150A2A"
    )
        port map (
      I0 => \count2_reg__0\(0),
      I1 => \count2_reg__0\(4),
      I2 => \count2_reg__0\(5),
      I3 => \count2_reg__0\(3),
      I4 => \count2_reg__0\(1),
      O => p_0_in(1)
    );
\count2[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"05150A2A0F3F0000"
    )
        port map (
      I0 => \count2_reg__0\(0),
      I1 => \count2_reg__0\(4),
      I2 => \count2_reg__0\(5),
      I3 => \count2_reg__0\(3),
      I4 => \count2_reg__0\(2),
      I5 => \count2_reg__0\(1),
      O => p_0_in(2)
    );
\count2[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"12303030"
    )
        port map (
      I0 => \count2_reg__0\(0),
      I1 => \count2_reg__0\(5),
      I2 => \count2_reg__0\(3),
      I3 => \count2_reg__0\(2),
      I4 => \count2_reg__0\(1),
      O => p_0_in(3)
    );
\count2[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"060C0C0C0C0C0C0C"
    )
        port map (
      I0 => \count2_reg__0\(0),
      I1 => \count2_reg__0\(4),
      I2 => \count2_reg__0\(5),
      I3 => \count2_reg__0\(3),
      I4 => \count2_reg__0\(2),
      I5 => \count2_reg__0\(1),
      O => p_0_in(4)
    );
\count2[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0810003000300030"
    )
        port map (
      I0 => \count2_reg__0\(0),
      I1 => \count2_reg__0\(4),
      I2 => \count2_reg__0\(5),
      I3 => \count2_reg__0\(3),
      I4 => \count2_reg__0\(2),
      I5 => \count2_reg__0\(1),
      O => p_0_in(5)
    );
\count2_inferred__0/i_\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"57"
    )
        port map (
      I0 => \count2_reg__0\(5),
      I1 => \count2_reg__0\(3),
      I2 => \count2_reg__0\(4),
      O => \count2_inferred__0/i__n_0\
    );
\count2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => \count2_inferred__0/i__n_0\,
      D => p_0_in(0),
      Q => \count2_reg__0\(0),
      R => '0'
    );
\count2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => \count2_inferred__0/i__n_0\,
      D => p_0_in(1),
      Q => \count2_reg__0\(1),
      R => '0'
    );
\count2_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => \count2_inferred__0/i__n_0\,
      D => p_0_in(2),
      Q => \count2_reg__0\(2),
      R => '0'
    );
\count2_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => \count2_inferred__0/i__n_0\,
      D => p_0_in(3),
      Q => \count2_reg__0\(3),
      R => '0'
    );
\count2_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => \count2_inferred__0/i__n_0\,
      D => p_0_in(4),
      Q => \count2_reg__0\(4),
      R => '0'
    );
\count2_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => \count2_inferred__0/i__n_0\,
      D => p_0_in(5),
      Q => \count2_reg__0\(5),
      R => '0'
    );
temp_clk1_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFFFFFFF10000000"
    )
        port map (
      I0 => \count1_reg__0\(2),
      I1 => \count1_reg__0\(3),
      I2 => \count1_reg__0\(1),
      I3 => \count1_reg__0\(0),
      I4 => \count1_reg__0\(4),
      I5 => \^i\,
      O => temp_clk1_i_1_n_0
    );
temp_clk1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => '1',
      D => temp_clk1_i_1_n_0,
      Q => \^i\,
      R => '0'
    );
temp_clk2_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => temp_clk21_out,
      I1 => \^clk2_5mhz_shift\,
      O => temp_clk2_i_1_n_0
    );
temp_clk2_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000800020"
    )
        port map (
      I0 => \count2_reg__0\(1),
      I1 => \count2_reg__0\(2),
      I2 => \count2_reg__0\(3),
      I3 => \count2_reg__0\(5),
      I4 => \count2_reg__0\(4),
      I5 => \count2_reg__0\(0),
      O => temp_clk21_out
    );
temp_clk2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => '1',
      D => temp_clk2_i_1_n_0,
      Q => \^clk2_5mhz_shift\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_ethernet_transceiver2_0_0_crc32_parallel is
  port (
    \state_reg[2]\ : out STD_LOGIC;
    \bit_count_reg[3]\ : out STD_LOGIC;
    \bit_count_reg[3]_0\ : out STD_LOGIC;
    \state_reg[1]\ : out STD_LOGIC;
    \txd_reg[0]\ : in STD_LOGIC;
    \txd_reg[0]_0\ : in STD_LOGIC;
    \txd_reg[0]_1\ : in STD_LOGIC;
    \txd_reg[0]_2\ : in STD_LOGIC;
    \txd_reg[0]_3\ : in STD_LOGIC;
    \txd[0]_i_2_0\ : in STD_LOGIC;
    \txd[0]_i_2_1\ : in STD_LOGIC;
    \txd[0]_i_2_2\ : in STD_LOGIC;
    \txd[1]_i_3\ : in STD_LOGIC;
    O : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \txd[1]_i_3_0\ : in STD_LOGIC;
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \txd[0]_i_7_0\ : in STD_LOGIC;
    start_crc : in STD_LOGIC;
    eth_txd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txd0 : in STD_LOGIC;
    b_clk100mhz : in STD_LOGIC;
    AS : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
end design_1_ethernet_transceiver2_0_0_crc32_parallel;

architecture STRUCTURE of design_1_ethernet_transceiver2_0_0_crc32_parallel is
  signal \^bit_count_reg[3]\ : STD_LOGIC;
  signal \^bit_count_reg[3]_0\ : STD_LOGIC;
  signal \crc32_temp[31]_i_1__0_n_0\ : STD_LOGIC;
  signal \crc32_temp_reg_n_0_[0]\ : STD_LOGIC;
  signal crc_calculated : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \edge_count_i_1__0_n_0\ : STD_LOGIC;
  signal edge_count_reg_n_0 : STD_LOGIC;
  signal p_0_in10_in : STD_LOGIC;
  signal p_0_in13_in : STD_LOGIC;
  signal p_0_in16_in : STD_LOGIC;
  signal p_0_in19_in : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC;
  signal p_0_in22_in : STD_LOGIC;
  signal p_0_in25_in : STD_LOGIC;
  signal p_0_in28_in : STD_LOGIC;
  signal p_0_in31_in : STD_LOGIC;
  signal p_0_in34_in : STD_LOGIC;
  signal p_0_in37_in : STD_LOGIC;
  signal p_0_in40_in : STD_LOGIC;
  signal p_0_in45_in : STD_LOGIC;
  signal p_0_in48_in : STD_LOGIC;
  signal p_0_in4_in : STD_LOGIC;
  signal p_0_in53_in : STD_LOGIC;
  signal p_0_in58_in : STD_LOGIC;
  signal p_0_in7_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 31 downto 14 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal p_1_in : STD_LOGIC;
  signal p_1_in56_in : STD_LOGIC;
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal p_59_in : STD_LOGIC;
  signal state : STD_LOGIC;
  signal \txd[0]_i_18_n_0\ : STD_LOGIC;
  signal \txd[0]_i_19_n_0\ : STD_LOGIC;
  signal \txd[0]_i_2_n_0\ : STD_LOGIC;
  signal \txd[0]_i_46_n_0\ : STD_LOGIC;
  signal \txd[0]_i_47_n_0\ : STD_LOGIC;
  signal \txd[0]_i_48_n_0\ : STD_LOGIC;
  signal \txd[0]_i_72_n_0\ : STD_LOGIC;
  signal \txd[0]_i_73_n_0\ : STD_LOGIC;
  signal \txd[0]_i_74_n_0\ : STD_LOGIC;
  signal \txd[0]_i_75_n_0\ : STD_LOGIC;
  signal \txd[0]_i_76_n_0\ : STD_LOGIC;
  signal \txd[0]_i_77_n_0\ : STD_LOGIC;
  signal \txd[0]_i_78_n_0\ : STD_LOGIC;
  signal \txd[0]_i_79_n_0\ : STD_LOGIC;
  signal \txd[0]_i_7_n_0\ : STD_LOGIC;
  signal \txd[1]_i_17_n_0\ : STD_LOGIC;
  signal \txd[1]_i_34_n_0\ : STD_LOGIC;
  signal \txd[1]_i_35_n_0\ : STD_LOGIC;
  signal \txd[1]_i_36_n_0\ : STD_LOGIC;
  signal \txd[1]_i_37_n_0\ : STD_LOGIC;
  signal \txd[1]_i_94_n_0\ : STD_LOGIC;
  signal \txd[1]_i_95_n_0\ : STD_LOGIC;
  signal \txd[1]_i_96_n_0\ : STD_LOGIC;
  signal \txd[1]_i_97_n_0\ : STD_LOGIC;
  signal \txd_reg[0]_i_54_n_0\ : STD_LOGIC;
  signal \txd_reg[0]_i_55_n_0\ : STD_LOGIC;
  signal \txd_reg[1]_i_14_n_0\ : STD_LOGIC;
  signal \txd_reg[1]_i_16_n_0\ : STD_LOGIC;
  signal \txd_reg[1]_i_66_n_0\ : STD_LOGIC;
  signal \txd_reg[1]_i_67_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \crc32_temp[0]_i_1__0\ : label is "soft_lutpair215";
  attribute SOFT_HLUTNM of \crc32_temp[13]_i_1__0\ : label is "soft_lutpair219";
  attribute SOFT_HLUTNM of \crc32_temp[14]_i_1__0\ : label is "soft_lutpair219";
  attribute SOFT_HLUTNM of \crc32_temp[15]_i_1__0\ : label is "soft_lutpair223";
  attribute SOFT_HLUTNM of \crc32_temp[17]_i_1__0\ : label is "soft_lutpair218";
  attribute SOFT_HLUTNM of \crc32_temp[18]_i_1__0\ : label is "soft_lutpair224";
  attribute SOFT_HLUTNM of \crc32_temp[19]_i_1__0\ : label is "soft_lutpair224";
  attribute SOFT_HLUTNM of \crc32_temp[20]_i_1__0\ : label is "soft_lutpair223";
  attribute SOFT_HLUTNM of \crc32_temp[21]_i_1__0\ : label is "soft_lutpair225";
  attribute SOFT_HLUTNM of \crc32_temp[24]_i_1__0\ : label is "soft_lutpair217";
  attribute SOFT_HLUTNM of \crc32_temp[25]_i_1__0\ : label is "soft_lutpair225";
  attribute SOFT_HLUTNM of \crc32_temp[26]_i_1__0\ : label is "soft_lutpair215";
  attribute SOFT_HLUTNM of \crc32_temp[27]_i_1__0\ : label is "soft_lutpair216";
  attribute SOFT_HLUTNM of \crc32_temp[27]_i_2__0\ : label is "soft_lutpair221";
  attribute SOFT_HLUTNM of \crc32_temp[28]_i_1__0\ : label is "soft_lutpair226";
  attribute SOFT_HLUTNM of \crc32_temp[29]_i_1__0\ : label is "soft_lutpair226";
  attribute SOFT_HLUTNM of \crc32_temp[30]_i_1__0\ : label is "soft_lutpair227";
  attribute SOFT_HLUTNM of \crc32_temp[31]_i_2__0\ : label is "soft_lutpair227";
  attribute SOFT_HLUTNM of \crc32_temp[3]_i_1__0\ : label is "soft_lutpair216";
  attribute SOFT_HLUTNM of \crc32_temp[6]_i_1__0\ : label is "soft_lutpair217";
  attribute SOFT_HLUTNM of \crc32_temp[9]_i_1__0\ : label is "soft_lutpair218";
  attribute SOFT_HLUTNM of \txd[0]_i_1\ : label is "soft_lutpair221";
  attribute SOFT_HLUTNM of \txd[0]_i_72\ : label is "soft_lutpair222";
  attribute SOFT_HLUTNM of \txd[0]_i_73\ : label is "soft_lutpair220";
  attribute SOFT_HLUTNM of \txd[0]_i_74\ : label is "soft_lutpair220";
  attribute SOFT_HLUTNM of \txd[0]_i_75\ : label is "soft_lutpair222";
begin
  \bit_count_reg[3]\ <= \^bit_count_reg[3]\;
  \bit_count_reg[3]_0\ <= \^bit_count_reg[3]_0\;
\crc32_temp[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"666F"
    )
        port map (
      I0 => eth_txd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => start_crc,
      O => \p_1_in__0\(0)
    );
\crc32_temp[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99669F6F"
    )
        port map (
      I0 => eth_txd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_0_in22_in,
      I4 => start_crc,
      O => \p_1_in__0\(10)
    );
\crc32_temp[11]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"669999666F9F9F6F"
    )
        port map (
      I0 => eth_txd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_59_in,
      I4 => p_0_in25_in,
      I5 => start_crc,
      O => \p_1_in__0\(11)
    );
\crc32_temp[12]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"669999666F9F9F6F"
    )
        port map (
      I0 => eth_txd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_59_in,
      I4 => p_0_in28_in,
      I5 => start_crc,
      O => \p_1_in__0\(12)
    );
\crc32_temp[13]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3C7D"
    )
        port map (
      I0 => state,
      I1 => p_59_in,
      I2 => p_0_in31_in,
      I3 => start_crc,
      O => \p_1_in__0\(13)
    );
\crc32_temp[14]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(14),
      I2 => start_crc,
      O => \p_1_in__0\(14)
    );
\crc32_temp[15]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(15),
      I2 => start_crc,
      O => \p_1_in__0\(15)
    );
\crc32_temp[16]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99669F6F"
    )
        port map (
      I0 => eth_txd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_0_in34_in,
      I4 => start_crc,
      O => \p_1_in__0\(16)
    );
\crc32_temp[17]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3C7D"
    )
        port map (
      I0 => state,
      I1 => p_59_in,
      I2 => p_0_in37_in,
      I3 => start_crc,
      O => \p_1_in__0\(17)
    );
\crc32_temp[18]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(18),
      I2 => start_crc,
      O => \p_1_in__0\(18)
    );
\crc32_temp[19]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(19),
      I2 => start_crc,
      O => \p_1_in__0\(19)
    );
\crc32_temp[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99669F6F"
    )
        port map (
      I0 => eth_txd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_59_in,
      I4 => start_crc,
      O => \p_1_in__0\(1)
    );
\crc32_temp[20]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(20),
      I2 => start_crc,
      O => \p_1_in__0\(20)
    );
\crc32_temp[21]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(21),
      I2 => start_crc,
      O => \p_1_in__0\(21)
    );
\crc32_temp[22]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99669F6F"
    )
        port map (
      I0 => eth_txd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_0_in40_in,
      I4 => start_crc,
      O => \p_1_in__0\(22)
    );
\crc32_temp[23]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"669999666F9F9F6F"
    )
        port map (
      I0 => eth_txd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_59_in,
      I4 => p_0_in45_in,
      I5 => start_crc,
      O => \p_1_in__0\(23)
    );
\crc32_temp[24]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3C7D"
    )
        port map (
      I0 => state,
      I1 => p_59_in,
      I2 => p_0_in48_in,
      I3 => start_crc,
      O => \p_1_in__0\(24)
    );
\crc32_temp[25]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(25),
      I2 => start_crc,
      O => \p_1_in__0\(25)
    );
\crc32_temp[26]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99669F6F"
    )
        port map (
      I0 => eth_txd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_0_in53_in,
      I4 => start_crc,
      O => \p_1_in__0\(26)
    );
\crc32_temp[27]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3C7D"
    )
        port map (
      I0 => state,
      I1 => p_59_in,
      I2 => p_0_in58_in,
      I3 => start_crc,
      O => \p_1_in__0\(27)
    );
\crc32_temp[27]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => eth_txd(0),
      I1 => p_1_in56_in,
      O => p_59_in
    );
\crc32_temp[28]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(28),
      I2 => start_crc,
      O => \p_1_in__0\(28)
    );
\crc32_temp[29]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(29),
      I2 => start_crc,
      O => \p_1_in__0\(29)
    );
\crc32_temp[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"669999666F9F9F6F"
    )
        port map (
      I0 => eth_txd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_59_in,
      I4 => \crc32_temp_reg_n_0_[0]\,
      I5 => start_crc,
      O => \p_1_in__0\(2)
    );
\crc32_temp[30]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(30),
      I2 => start_crc,
      O => \p_1_in__0\(30)
    );
\crc32_temp[31]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4F"
    )
        port map (
      I0 => edge_count_reg_n_0,
      I1 => start_crc,
      I2 => state,
      O => \crc32_temp[31]_i_1__0_n_0\
    );
\crc32_temp[31]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(31),
      I2 => start_crc,
      O => \p_1_in__0\(31)
    );
\crc32_temp[3]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3C7D"
    )
        port map (
      I0 => state,
      I1 => p_59_in,
      I2 => p_0_in1_in,
      I3 => start_crc,
      O => \p_1_in__0\(3)
    );
\crc32_temp[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99669F6F"
    )
        port map (
      I0 => eth_txd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_0_in4_in,
      I4 => start_crc,
      O => \p_1_in__0\(4)
    );
\crc32_temp[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"669999666F9F9F6F"
    )
        port map (
      I0 => eth_txd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_59_in,
      I4 => p_0_in7_in,
      I5 => start_crc,
      O => \p_1_in__0\(5)
    );
\crc32_temp[6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3C7D"
    )
        port map (
      I0 => state,
      I1 => p_59_in,
      I2 => p_0_in10_in,
      I3 => start_crc,
      O => \p_1_in__0\(6)
    );
\crc32_temp[7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99669F6F"
    )
        port map (
      I0 => eth_txd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_0_in13_in,
      I4 => start_crc,
      O => \p_1_in__0\(7)
    );
\crc32_temp[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"669999666F9F9F6F"
    )
        port map (
      I0 => eth_txd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_59_in,
      I4 => p_0_in16_in,
      I5 => start_crc,
      O => \p_1_in__0\(8)
    );
\crc32_temp[9]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3C7D"
    )
        port map (
      I0 => state,
      I1 => p_59_in,
      I2 => p_0_in19_in,
      I3 => start_crc,
      O => \p_1_in__0\(9)
    );
\crc32_temp_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(0),
      PRE => AS(0),
      Q => \crc32_temp_reg_n_0_[0]\
    );
\crc32_temp_reg[10]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(10),
      PRE => AS(0),
      Q => p_0_in28_in
    );
\crc32_temp_reg[11]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(11),
      PRE => AS(0),
      Q => p_0_in31_in
    );
\crc32_temp_reg[12]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(12),
      PRE => AS(0),
      Q => \p_0_in__0\(14)
    );
\crc32_temp_reg[13]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(13),
      PRE => AS(0),
      Q => \p_0_in__0\(15)
    );
\crc32_temp_reg[14]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(14),
      PRE => AS(0),
      Q => p_0_in34_in
    );
\crc32_temp_reg[15]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(15),
      PRE => AS(0),
      Q => p_0_in37_in
    );
\crc32_temp_reg[16]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(16),
      PRE => AS(0),
      Q => \p_0_in__0\(18)
    );
\crc32_temp_reg[17]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(17),
      PRE => AS(0),
      Q => \p_0_in__0\(19)
    );
\crc32_temp_reg[18]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(18),
      PRE => AS(0),
      Q => \p_0_in__0\(20)
    );
\crc32_temp_reg[19]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(19),
      PRE => AS(0),
      Q => \p_0_in__0\(21)
    );
\crc32_temp_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(1),
      PRE => AS(0),
      Q => p_0_in1_in
    );
\crc32_temp_reg[20]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(20),
      PRE => AS(0),
      Q => p_0_in40_in
    );
\crc32_temp_reg[21]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(21),
      PRE => AS(0),
      Q => p_0_in45_in
    );
\crc32_temp_reg[22]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(22),
      PRE => AS(0),
      Q => p_0_in48_in
    );
\crc32_temp_reg[23]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(23),
      PRE => AS(0),
      Q => \p_0_in__0\(25)
    );
\crc32_temp_reg[24]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(24),
      PRE => AS(0),
      Q => p_0_in53_in
    );
\crc32_temp_reg[25]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(25),
      PRE => AS(0),
      Q => p_0_in58_in
    );
\crc32_temp_reg[26]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(26),
      PRE => AS(0),
      Q => \p_0_in__0\(28)
    );
\crc32_temp_reg[27]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(27),
      PRE => AS(0),
      Q => \p_0_in__0\(29)
    );
\crc32_temp_reg[28]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(28),
      PRE => AS(0),
      Q => \p_0_in__0\(30)
    );
\crc32_temp_reg[29]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(29),
      PRE => AS(0),
      Q => \p_0_in__0\(31)
    );
\crc32_temp_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(2),
      PRE => AS(0),
      Q => p_0_in4_in
    );
\crc32_temp_reg[30]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(30),
      PRE => AS(0),
      Q => p_1_in
    );
\crc32_temp_reg[31]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(31),
      PRE => AS(0),
      Q => p_1_in56_in
    );
\crc32_temp_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(3),
      PRE => AS(0),
      Q => p_0_in7_in
    );
\crc32_temp_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(4),
      PRE => AS(0),
      Q => p_0_in10_in
    );
\crc32_temp_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(5),
      PRE => AS(0),
      Q => p_0_in13_in
    );
\crc32_temp_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(6),
      PRE => AS(0),
      Q => p_0_in16_in
    );
\crc32_temp_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(7),
      PRE => AS(0),
      Q => p_0_in19_in
    );
\crc32_temp_reg[8]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(8),
      PRE => AS(0),
      Q => p_0_in22_in
    );
\crc32_temp_reg[9]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1__0_n_0\,
      D => \p_1_in__0\(9),
      PRE => AS(0),
      Q => p_0_in25_in
    );
\crc[0]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \crc32_temp_reg_n_0_[0]\,
      O => \p_0_in__1\(0)
    );
\crc[10]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in28_in,
      O => \p_0_in__1\(10)
    );
\crc[11]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in31_in,
      O => \p_0_in__1\(11)
    );
\crc[12]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(14),
      O => \p_0_in__1\(12)
    );
\crc[13]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(15),
      O => \p_0_in__1\(13)
    );
\crc[14]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in34_in,
      O => \p_0_in__1\(14)
    );
\crc[15]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in37_in,
      O => \p_0_in__1\(15)
    );
\crc[16]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(18),
      O => \p_0_in__1\(16)
    );
\crc[17]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(19),
      O => \p_0_in__1\(17)
    );
\crc[18]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(20),
      O => \p_0_in__1\(18)
    );
\crc[19]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(21),
      O => \p_0_in__1\(19)
    );
\crc[1]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in1_in,
      O => \p_0_in__1\(1)
    );
\crc[20]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in40_in,
      O => \p_0_in__1\(20)
    );
\crc[21]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in45_in,
      O => \p_0_in__1\(21)
    );
\crc[22]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in48_in,
      O => \p_0_in__1\(22)
    );
\crc[23]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(25),
      O => \p_0_in__1\(23)
    );
\crc[24]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in53_in,
      O => \p_0_in__1\(24)
    );
\crc[25]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in58_in,
      O => \p_0_in__1\(25)
    );
\crc[26]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(28),
      O => \p_0_in__1\(26)
    );
\crc[27]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(29),
      O => \p_0_in__1\(27)
    );
\crc[28]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(30),
      O => \p_0_in__1\(28)
    );
\crc[29]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(31),
      O => \p_0_in__1\(29)
    );
\crc[2]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in4_in,
      O => \p_0_in__1\(2)
    );
\crc[30]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_1_in,
      O => \p_0_in__1\(30)
    );
\crc[31]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_1_in56_in,
      O => \p_0_in__1\(31)
    );
\crc[3]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in7_in,
      O => \p_0_in__1\(3)
    );
\crc[4]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in10_in,
      O => \p_0_in__1\(4)
    );
\crc[5]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in13_in,
      O => \p_0_in__1\(5)
    );
\crc[6]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in16_in,
      O => \p_0_in__1\(6)
    );
\crc[7]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in19_in,
      O => \p_0_in__1\(7)
    );
\crc[8]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in22_in,
      O => \p_0_in__1\(8)
    );
\crc[9]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in25_in,
      O => \p_0_in__1\(9)
    );
\crc_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(0),
      Q => crc_calculated(0),
      R => '0'
    );
\crc_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(10),
      Q => crc_calculated(10),
      R => '0'
    );
\crc_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(11),
      Q => crc_calculated(11),
      R => '0'
    );
\crc_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(12),
      Q => crc_calculated(12),
      R => '0'
    );
\crc_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(13),
      Q => crc_calculated(13),
      R => '0'
    );
\crc_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(14),
      Q => crc_calculated(14),
      R => '0'
    );
\crc_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(15),
      Q => crc_calculated(15),
      R => '0'
    );
\crc_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(16),
      Q => crc_calculated(16),
      R => '0'
    );
\crc_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(17),
      Q => crc_calculated(17),
      R => '0'
    );
\crc_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(18),
      Q => crc_calculated(18),
      R => '0'
    );
\crc_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(19),
      Q => crc_calculated(19),
      R => '0'
    );
\crc_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(1),
      Q => crc_calculated(1),
      R => '0'
    );
\crc_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(20),
      Q => crc_calculated(20),
      R => '0'
    );
\crc_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(21),
      Q => crc_calculated(21),
      R => '0'
    );
\crc_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(22),
      Q => crc_calculated(22),
      R => '0'
    );
\crc_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(23),
      Q => crc_calculated(23),
      R => '0'
    );
\crc_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(24),
      Q => crc_calculated(24),
      R => '0'
    );
\crc_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(25),
      Q => crc_calculated(25),
      R => '0'
    );
\crc_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(26),
      Q => crc_calculated(26),
      R => '0'
    );
\crc_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(27),
      Q => crc_calculated(27),
      R => '0'
    );
\crc_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(28),
      Q => crc_calculated(28),
      R => '0'
    );
\crc_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(29),
      Q => crc_calculated(29),
      R => '0'
    );
\crc_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(2),
      Q => crc_calculated(2),
      R => '0'
    );
\crc_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(30),
      Q => crc_calculated(30),
      R => '0'
    );
\crc_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(31),
      Q => crc_calculated(31),
      R => '0'
    );
\crc_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(3),
      Q => crc_calculated(3),
      R => '0'
    );
\crc_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(4),
      Q => crc_calculated(4),
      R => '0'
    );
\crc_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(5),
      Q => crc_calculated(5),
      R => '0'
    );
\crc_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(6),
      Q => crc_calculated(6),
      R => '0'
    );
\crc_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(7),
      Q => crc_calculated(7),
      R => '0'
    );
\crc_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(8),
      Q => crc_calculated(8),
      R => '0'
    );
\crc_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(9),
      Q => crc_calculated(9),
      R => '0'
    );
\edge_count_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => start_crc,
      I1 => edge_count_reg_n_0,
      O => \edge_count_i_1__0_n_0\
    );
edge_count_reg: unisim.vcomponents.FDCE
     port map (
      C => b_clk100mhz,
      CE => '1',
      CLR => AS(0),
      D => \edge_count_i_1__0_n_0\,
      Q => edge_count_reg_n_0
    );
state_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => '1',
      CLR => AS(0),
      D => start_crc,
      Q => state
    );
\txd[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => txd0,
      I1 => eth_txd(0),
      I2 => \txd[0]_i_2_n_0\,
      O => \state_reg[1]\
    );
\txd[0]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF02FFFF"
    )
        port map (
      I0 => CO(0),
      I1 => Q(3),
      I2 => Q(2),
      I3 => \txd[0]_i_7_0\,
      I4 => \^bit_count_reg[3]_0\,
      O => \txd[0]_i_18_n_0\
    );
\txd[0]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFB800B8"
    )
        port map (
      I0 => \txd[0]_i_46_n_0\,
      I1 => O(1),
      I2 => \txd[0]_i_47_n_0\,
      I3 => O(2),
      I4 => \txd[0]_i_48_n_0\,
      I5 => \txd[1]_i_3_0\,
      O => \txd[0]_i_19_n_0\
    );
\txd[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF0000FFA2"
    )
        port map (
      I0 => \txd_reg[0]\,
      I1 => \txd_reg[0]_0\,
      I2 => \txd_reg[0]_1\,
      I3 => \txd_reg[0]_2\,
      I4 => \txd_reg[0]_3\,
      I5 => \txd[0]_i_7_n_0\,
      O => \txd[0]_i_2_n_0\
    );
\txd[0]_i_46\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => crc_calculated(13),
      I1 => crc_calculated(15),
      I2 => O(0),
      I3 => crc_calculated(9),
      I4 => Q(0),
      I5 => crc_calculated(11),
      O => \txd[0]_i_46_n_0\
    );
\txd[0]_i_47\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => crc_calculated(5),
      I1 => crc_calculated(7),
      I2 => O(0),
      I3 => crc_calculated(1),
      I4 => Q(0),
      I5 => crc_calculated(3),
      O => \txd[0]_i_47_n_0\
    );
\txd[0]_i_48\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \txd[0]_i_72_n_0\,
      I1 => \txd[0]_i_73_n_0\,
      I2 => O(1),
      I3 => \txd[0]_i_74_n_0\,
      I4 => O(0),
      I5 => \txd[0]_i_75_n_0\,
      O => \txd[0]_i_48_n_0\
    );
\txd[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF54FF54545454"
    )
        port map (
      I0 => \txd[0]_i_2_0\,
      I1 => \txd[0]_i_2_1\,
      I2 => \txd[0]_i_2_2\,
      I3 => \txd[0]_i_18_n_0\,
      I4 => \txd[0]_i_19_n_0\,
      I5 => \txd[1]_i_3\,
      O => \txd[0]_i_7_n_0\
    );
\txd[0]_i_72\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => crc_calculated(29),
      I1 => Q(0),
      I2 => crc_calculated(31),
      O => \txd[0]_i_72_n_0\
    );
\txd[0]_i_73\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => crc_calculated(25),
      I1 => Q(0),
      I2 => crc_calculated(27),
      O => \txd[0]_i_73_n_0\
    );
\txd[0]_i_74\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => crc_calculated(21),
      I1 => Q(0),
      I2 => crc_calculated(23),
      O => \txd[0]_i_74_n_0\
    );
\txd[0]_i_75\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => crc_calculated(17),
      I1 => Q(0),
      I2 => crc_calculated(19),
      O => \txd[0]_i_75_n_0\
    );
\txd[0]_i_76\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => crc_calculated(25),
      I1 => crc_calculated(27),
      I2 => Q(1),
      I3 => crc_calculated(29),
      I4 => Q(0),
      I5 => crc_calculated(31),
      O => \txd[0]_i_76_n_0\
    );
\txd[0]_i_77\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => crc_calculated(17),
      I1 => crc_calculated(19),
      I2 => Q(1),
      I3 => crc_calculated(21),
      I4 => Q(0),
      I5 => crc_calculated(23),
      O => \txd[0]_i_77_n_0\
    );
\txd[0]_i_78\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => crc_calculated(9),
      I1 => crc_calculated(11),
      I2 => Q(1),
      I3 => crc_calculated(13),
      I4 => Q(0),
      I5 => crc_calculated(15),
      O => \txd[0]_i_78_n_0\
    );
\txd[0]_i_79\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => crc_calculated(1),
      I1 => crc_calculated(3),
      I2 => Q(1),
      I3 => crc_calculated(5),
      I4 => Q(0),
      I5 => crc_calculated(7),
      O => \txd[0]_i_79_n_0\
    );
\txd[1]_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF02FFFF"
    )
        port map (
      I0 => CO(0),
      I1 => Q(3),
      I2 => Q(2),
      I3 => \txd[0]_i_7_0\,
      I4 => \^bit_count_reg[3]\,
      O => \txd[1]_i_17_n_0\
    );
\txd[1]_i_34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => crc_calculated(4),
      I1 => crc_calculated(6),
      I2 => O(0),
      I3 => crc_calculated(0),
      I4 => Q(0),
      I5 => crc_calculated(2),
      O => \txd[1]_i_34_n_0\
    );
\txd[1]_i_35\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => crc_calculated(12),
      I1 => crc_calculated(14),
      I2 => O(0),
      I3 => crc_calculated(8),
      I4 => Q(0),
      I5 => crc_calculated(10),
      O => \txd[1]_i_35_n_0\
    );
\txd[1]_i_36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => crc_calculated(20),
      I1 => crc_calculated(22),
      I2 => O(0),
      I3 => crc_calculated(16),
      I4 => Q(0),
      I5 => crc_calculated(18),
      O => \txd[1]_i_36_n_0\
    );
\txd[1]_i_37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => crc_calculated(28),
      I1 => crc_calculated(30),
      I2 => O(0),
      I3 => crc_calculated(24),
      I4 => Q(0),
      I5 => crc_calculated(26),
      O => \txd[1]_i_37_n_0\
    );
\txd[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0A080008AAAAAAAA"
    )
        port map (
      I0 => \txd[1]_i_3\,
      I1 => \txd_reg[1]_i_14_n_0\,
      I2 => \txd[1]_i_3_0\,
      I3 => O(2),
      I4 => \txd_reg[1]_i_16_n_0\,
      I5 => \txd[1]_i_17_n_0\,
      O => \state_reg[2]\
    );
\txd[1]_i_94\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => crc_calculated(24),
      I1 => crc_calculated(26),
      I2 => Q(1),
      I3 => crc_calculated(28),
      I4 => Q(0),
      I5 => crc_calculated(30),
      O => \txd[1]_i_94_n_0\
    );
\txd[1]_i_95\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => crc_calculated(16),
      I1 => crc_calculated(18),
      I2 => Q(1),
      I3 => crc_calculated(20),
      I4 => Q(0),
      I5 => crc_calculated(22),
      O => \txd[1]_i_95_n_0\
    );
\txd[1]_i_96\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => crc_calculated(8),
      I1 => crc_calculated(10),
      I2 => Q(1),
      I3 => crc_calculated(12),
      I4 => Q(0),
      I5 => crc_calculated(14),
      O => \txd[1]_i_96_n_0\
    );
\txd[1]_i_97\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => crc_calculated(0),
      I1 => crc_calculated(2),
      I2 => Q(1),
      I3 => crc_calculated(4),
      I4 => Q(0),
      I5 => crc_calculated(6),
      O => \txd[1]_i_97_n_0\
    );
\txd_reg[0]_i_36\: unisim.vcomponents.MUXF8
     port map (
      I0 => \txd_reg[0]_i_54_n_0\,
      I1 => \txd_reg[0]_i_55_n_0\,
      O => \^bit_count_reg[3]_0\,
      S => Q(3)
    );
\txd_reg[0]_i_54\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txd[0]_i_76_n_0\,
      I1 => \txd[0]_i_77_n_0\,
      O => \txd_reg[0]_i_54_n_0\,
      S => Q(2)
    );
\txd_reg[0]_i_55\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txd[0]_i_78_n_0\,
      I1 => \txd[0]_i_79_n_0\,
      O => \txd_reg[0]_i_55_n_0\,
      S => Q(2)
    );
\txd_reg[1]_i_14\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txd[1]_i_34_n_0\,
      I1 => \txd[1]_i_35_n_0\,
      O => \txd_reg[1]_i_14_n_0\,
      S => O(1)
    );
\txd_reg[1]_i_16\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txd[1]_i_36_n_0\,
      I1 => \txd[1]_i_37_n_0\,
      O => \txd_reg[1]_i_16_n_0\,
      S => O(1)
    );
\txd_reg[1]_i_33\: unisim.vcomponents.MUXF8
     port map (
      I0 => \txd_reg[1]_i_66_n_0\,
      I1 => \txd_reg[1]_i_67_n_0\,
      O => \^bit_count_reg[3]\,
      S => Q(3)
    );
\txd_reg[1]_i_66\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txd[1]_i_94_n_0\,
      I1 => \txd[1]_i_95_n_0\,
      O => \txd_reg[1]_i_66_n_0\,
      S => Q(2)
    );
\txd_reg[1]_i_67\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txd[1]_i_96_n_0\,
      I1 => \txd[1]_i_97_n_0\,
      O => \txd_reg[1]_i_67_n_0\,
      S => Q(2)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_ethernet_transceiver2_0_0_crc32_parallel_0 is
  port (
    CO : out STD_LOGIC_VECTOR ( 0 to 0 );
    \state_reg[3]\ : out STD_LOGIC;
    crc_rx : in STD_LOGIC_VECTOR ( 31 downto 0 );
    rst_ram_reg : in STD_LOGIC;
    rst_ram_reg_0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_ram_reg_1 : in STD_LOGIC;
    rst_ram_reg_2 : in STD_LOGIC;
    state_reg_0 : in STD_LOGIC;
    eth_rxd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    b_clk100mhz : in STD_LOGIC;
    udp_datasum_done14_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_ethernet_transceiver2_0_0_crc32_parallel_0 : entity is "crc32_parallel";
end design_1_ethernet_transceiver2_0_0_crc32_parallel_0;

architecture STRUCTURE of design_1_ethernet_transceiver2_0_0_crc32_parallel_0 is
  signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \crc32_temp[31]_i_1_n_0\ : STD_LOGIC;
  signal \crc32_temp_reg_n_0_[0]\ : STD_LOGIC;
  signal crc_calculated : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal edge_count_i_1_n_0 : STD_LOGIC;
  signal edge_count_reg_n_0 : STD_LOGIC;
  signal p_0_in10_in : STD_LOGIC;
  signal p_0_in13_in : STD_LOGIC;
  signal p_0_in16_in : STD_LOGIC;
  signal p_0_in19_in : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC;
  signal p_0_in22_in : STD_LOGIC;
  signal p_0_in25_in : STD_LOGIC;
  signal p_0_in28_in : STD_LOGIC;
  signal p_0_in31_in : STD_LOGIC;
  signal p_0_in34_in : STD_LOGIC;
  signal p_0_in37_in : STD_LOGIC;
  signal p_0_in40_in : STD_LOGIC;
  signal p_0_in45_in : STD_LOGIC;
  signal p_0_in48_in : STD_LOGIC;
  signal p_0_in4_in : STD_LOGIC;
  signal p_0_in53_in : STD_LOGIC;
  signal p_0_in58_in : STD_LOGIC;
  signal p_0_in7_in : STD_LOGIC;
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 31 downto 14 );
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal p_1_in : STD_LOGIC;
  signal p_1_in56_in : STD_LOGIC;
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal p_59_in : STD_LOGIC;
  signal rst_ram_i_10_n_0 : STD_LOGIC;
  signal rst_ram_i_11_n_0 : STD_LOGIC;
  signal rst_ram_i_12_n_0 : STD_LOGIC;
  signal rst_ram_i_13_n_0 : STD_LOGIC;
  signal rst_ram_i_14_n_0 : STD_LOGIC;
  signal rst_ram_i_15_n_0 : STD_LOGIC;
  signal rst_ram_i_16_n_0 : STD_LOGIC;
  signal rst_ram_i_17_n_0 : STD_LOGIC;
  signal rst_ram_i_6_n_0 : STD_LOGIC;
  signal rst_ram_i_7_n_0 : STD_LOGIC;
  signal rst_ram_i_8_n_0 : STD_LOGIC;
  signal rst_ram_reg_i_3_n_2 : STD_LOGIC;
  signal rst_ram_reg_i_3_n_3 : STD_LOGIC;
  signal rst_ram_reg_i_5_n_0 : STD_LOGIC;
  signal rst_ram_reg_i_5_n_1 : STD_LOGIC;
  signal rst_ram_reg_i_5_n_2 : STD_LOGIC;
  signal rst_ram_reg_i_5_n_3 : STD_LOGIC;
  signal rst_ram_reg_i_9_n_0 : STD_LOGIC;
  signal rst_ram_reg_i_9_n_1 : STD_LOGIC;
  signal rst_ram_reg_i_9_n_2 : STD_LOGIC;
  signal rst_ram_reg_i_9_n_3 : STD_LOGIC;
  signal state : STD_LOGIC;
  signal NLW_rst_ram_reg_i_3_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
  signal NLW_rst_ram_reg_i_3_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_rst_ram_reg_i_5_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_rst_ram_reg_i_9_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \crc32_temp[0]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \crc32_temp[10]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \crc32_temp[13]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \crc32_temp[14]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \crc32_temp[15]_i_1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \crc32_temp[17]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \crc32_temp[18]_i_1\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \crc32_temp[19]_i_1\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \crc32_temp[20]_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \crc32_temp[21]_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \crc32_temp[24]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \crc32_temp[25]_i_1\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \crc32_temp[27]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \crc32_temp[27]_i_2\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \crc32_temp[28]_i_1\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \crc32_temp[29]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \crc32_temp[30]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \crc32_temp[31]_i_2\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \crc32_temp[3]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \crc32_temp[6]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \crc32_temp[9]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \crc[31]_i_1\ : label is "soft_lutpair13";
begin
  CO(0) <= \^co\(0);
\crc32_temp[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"666F"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => state_reg_0,
      O => \p_1_in__0\(0)
    );
\crc32_temp[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99669F6F"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_0_in22_in,
      I4 => state_reg_0,
      O => \p_1_in__0\(10)
    );
\crc32_temp[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"669999666F9F9F6F"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_59_in,
      I4 => p_0_in25_in,
      I5 => state_reg_0,
      O => \p_1_in__0\(11)
    );
\crc32_temp[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"669999666F9F9F6F"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_59_in,
      I4 => p_0_in28_in,
      I5 => state_reg_0,
      O => \p_1_in__0\(12)
    );
\crc32_temp[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3C7D"
    )
        port map (
      I0 => state,
      I1 => p_59_in,
      I2 => p_0_in31_in,
      I3 => state_reg_0,
      O => \p_1_in__0\(13)
    );
\crc32_temp[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(14),
      I2 => state_reg_0,
      O => \p_1_in__0\(14)
    );
\crc32_temp[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(15),
      I2 => state_reg_0,
      O => \p_1_in__0\(15)
    );
\crc32_temp[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99669F6F"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_0_in34_in,
      I4 => state_reg_0,
      O => \p_1_in__0\(16)
    );
\crc32_temp[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3C7D"
    )
        port map (
      I0 => state,
      I1 => p_59_in,
      I2 => p_0_in37_in,
      I3 => state_reg_0,
      O => \p_1_in__0\(17)
    );
\crc32_temp[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(18),
      I2 => state_reg_0,
      O => \p_1_in__0\(18)
    );
\crc32_temp[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(19),
      I2 => state_reg_0,
      O => \p_1_in__0\(19)
    );
\crc32_temp[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99669F6F"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_59_in,
      I4 => state_reg_0,
      O => \p_1_in__0\(1)
    );
\crc32_temp[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(20),
      I2 => state_reg_0,
      O => \p_1_in__0\(20)
    );
\crc32_temp[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(21),
      I2 => state_reg_0,
      O => \p_1_in__0\(21)
    );
\crc32_temp[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99669F6F"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_0_in40_in,
      I4 => state_reg_0,
      O => \p_1_in__0\(22)
    );
\crc32_temp[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"669999666F9F9F6F"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_59_in,
      I4 => p_0_in45_in,
      I5 => state_reg_0,
      O => \p_1_in__0\(23)
    );
\crc32_temp[24]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3C7D"
    )
        port map (
      I0 => state,
      I1 => p_59_in,
      I2 => p_0_in48_in,
      I3 => state_reg_0,
      O => \p_1_in__0\(24)
    );
\crc32_temp[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(25),
      I2 => state_reg_0,
      O => \p_1_in__0\(25)
    );
\crc32_temp[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99669F6F"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_0_in53_in,
      I4 => state_reg_0,
      O => \p_1_in__0\(26)
    );
\crc32_temp[27]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3C7D"
    )
        port map (
      I0 => state,
      I1 => p_59_in,
      I2 => p_0_in58_in,
      I3 => state_reg_0,
      O => \p_1_in__0\(27)
    );
\crc32_temp[27]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => p_1_in56_in,
      O => p_59_in
    );
\crc32_temp[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(28),
      I2 => state_reg_0,
      O => \p_1_in__0\(28)
    );
\crc32_temp[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(29),
      I2 => state_reg_0,
      O => \p_1_in__0\(29)
    );
\crc32_temp[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"669999666F9F9F6F"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_59_in,
      I4 => \crc32_temp_reg_n_0_[0]\,
      I5 => state_reg_0,
      O => \p_1_in__0\(2)
    );
\crc32_temp[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(30),
      I2 => state_reg_0,
      O => \p_1_in__0\(30)
    );
\crc32_temp[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4F"
    )
        port map (
      I0 => edge_count_reg_n_0,
      I1 => state_reg_0,
      I2 => state,
      O => \crc32_temp[31]_i_1_n_0\
    );
\crc32_temp[31]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => state,
      I1 => \p_0_in__0\(31),
      I2 => state_reg_0,
      O => \p_1_in__0\(31)
    );
\crc32_temp[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3C7D"
    )
        port map (
      I0 => state,
      I1 => p_59_in,
      I2 => p_0_in1_in,
      I3 => state_reg_0,
      O => \p_1_in__0\(3)
    );
\crc32_temp[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99669F6F"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_0_in4_in,
      I4 => state_reg_0,
      O => \p_1_in__0\(4)
    );
\crc32_temp[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"669999666F9F9F6F"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_59_in,
      I4 => p_0_in7_in,
      I5 => state_reg_0,
      O => \p_1_in__0\(5)
    );
\crc32_temp[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3C7D"
    )
        port map (
      I0 => state,
      I1 => p_59_in,
      I2 => p_0_in10_in,
      I3 => state_reg_0,
      O => \p_1_in__0\(6)
    );
\crc32_temp[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99669F6F"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_0_in13_in,
      I4 => state_reg_0,
      O => \p_1_in__0\(7)
    );
\crc32_temp[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"669999666F9F9F6F"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => p_1_in,
      I2 => state,
      I3 => p_59_in,
      I4 => p_0_in16_in,
      I5 => state_reg_0,
      O => \p_1_in__0\(8)
    );
\crc32_temp[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3C7D"
    )
        port map (
      I0 => state,
      I1 => p_59_in,
      I2 => p_0_in19_in,
      I3 => state_reg_0,
      O => \p_1_in__0\(9)
    );
\crc32_temp_reg[0]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(0),
      PRE => udp_datasum_done14_out,
      Q => \crc32_temp_reg_n_0_[0]\
    );
\crc32_temp_reg[10]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(10),
      PRE => udp_datasum_done14_out,
      Q => p_0_in28_in
    );
\crc32_temp_reg[11]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(11),
      PRE => udp_datasum_done14_out,
      Q => p_0_in31_in
    );
\crc32_temp_reg[12]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(12),
      PRE => udp_datasum_done14_out,
      Q => \p_0_in__0\(14)
    );
\crc32_temp_reg[13]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(13),
      PRE => udp_datasum_done14_out,
      Q => \p_0_in__0\(15)
    );
\crc32_temp_reg[14]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(14),
      PRE => udp_datasum_done14_out,
      Q => p_0_in34_in
    );
\crc32_temp_reg[15]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(15),
      PRE => udp_datasum_done14_out,
      Q => p_0_in37_in
    );
\crc32_temp_reg[16]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(16),
      PRE => udp_datasum_done14_out,
      Q => \p_0_in__0\(18)
    );
\crc32_temp_reg[17]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(17),
      PRE => udp_datasum_done14_out,
      Q => \p_0_in__0\(19)
    );
\crc32_temp_reg[18]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(18),
      PRE => udp_datasum_done14_out,
      Q => \p_0_in__0\(20)
    );
\crc32_temp_reg[19]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(19),
      PRE => udp_datasum_done14_out,
      Q => \p_0_in__0\(21)
    );
\crc32_temp_reg[1]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(1),
      PRE => udp_datasum_done14_out,
      Q => p_0_in1_in
    );
\crc32_temp_reg[20]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(20),
      PRE => udp_datasum_done14_out,
      Q => p_0_in40_in
    );
\crc32_temp_reg[21]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(21),
      PRE => udp_datasum_done14_out,
      Q => p_0_in45_in
    );
\crc32_temp_reg[22]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(22),
      PRE => udp_datasum_done14_out,
      Q => p_0_in48_in
    );
\crc32_temp_reg[23]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(23),
      PRE => udp_datasum_done14_out,
      Q => \p_0_in__0\(25)
    );
\crc32_temp_reg[24]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(24),
      PRE => udp_datasum_done14_out,
      Q => p_0_in53_in
    );
\crc32_temp_reg[25]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(25),
      PRE => udp_datasum_done14_out,
      Q => p_0_in58_in
    );
\crc32_temp_reg[26]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(26),
      PRE => udp_datasum_done14_out,
      Q => \p_0_in__0\(28)
    );
\crc32_temp_reg[27]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(27),
      PRE => udp_datasum_done14_out,
      Q => \p_0_in__0\(29)
    );
\crc32_temp_reg[28]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(28),
      PRE => udp_datasum_done14_out,
      Q => \p_0_in__0\(30)
    );
\crc32_temp_reg[29]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(29),
      PRE => udp_datasum_done14_out,
      Q => \p_0_in__0\(31)
    );
\crc32_temp_reg[2]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(2),
      PRE => udp_datasum_done14_out,
      Q => p_0_in4_in
    );
\crc32_temp_reg[30]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(30),
      PRE => udp_datasum_done14_out,
      Q => p_1_in
    );
\crc32_temp_reg[31]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(31),
      PRE => udp_datasum_done14_out,
      Q => p_1_in56_in
    );
\crc32_temp_reg[3]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(3),
      PRE => udp_datasum_done14_out,
      Q => p_0_in7_in
    );
\crc32_temp_reg[4]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(4),
      PRE => udp_datasum_done14_out,
      Q => p_0_in10_in
    );
\crc32_temp_reg[5]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(5),
      PRE => udp_datasum_done14_out,
      Q => p_0_in13_in
    );
\crc32_temp_reg[6]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(6),
      PRE => udp_datasum_done14_out,
      Q => p_0_in16_in
    );
\crc32_temp_reg[7]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(7),
      PRE => udp_datasum_done14_out,
      Q => p_0_in19_in
    );
\crc32_temp_reg[8]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(8),
      PRE => udp_datasum_done14_out,
      Q => p_0_in22_in
    );
\crc32_temp_reg[9]\: unisim.vcomponents.FDPE
     port map (
      C => b_clk100mhz,
      CE => \crc32_temp[31]_i_1_n_0\,
      D => \p_1_in__0\(9),
      PRE => udp_datasum_done14_out,
      Q => p_0_in25_in
    );
\crc[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \crc32_temp_reg_n_0_[0]\,
      O => \p_0_in__1\(0)
    );
\crc[10]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in28_in,
      O => \p_0_in__1\(10)
    );
\crc[11]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in31_in,
      O => \p_0_in__1\(11)
    );
\crc[12]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(14),
      O => \p_0_in__1\(12)
    );
\crc[13]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(15),
      O => \p_0_in__1\(13)
    );
\crc[14]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in34_in,
      O => \p_0_in__1\(14)
    );
\crc[15]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in37_in,
      O => \p_0_in__1\(15)
    );
\crc[16]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(18),
      O => \p_0_in__1\(16)
    );
\crc[17]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(19),
      O => \p_0_in__1\(17)
    );
\crc[18]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(20),
      O => \p_0_in__1\(18)
    );
\crc[19]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(21),
      O => \p_0_in__1\(19)
    );
\crc[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in1_in,
      O => \p_0_in__1\(1)
    );
\crc[20]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in40_in,
      O => \p_0_in__1\(20)
    );
\crc[21]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in45_in,
      O => \p_0_in__1\(21)
    );
\crc[22]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in48_in,
      O => \p_0_in__1\(22)
    );
\crc[23]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(25),
      O => \p_0_in__1\(23)
    );
\crc[24]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in53_in,
      O => \p_0_in__1\(24)
    );
\crc[25]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in58_in,
      O => \p_0_in__1\(25)
    );
\crc[26]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(28),
      O => \p_0_in__1\(26)
    );
\crc[27]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(29),
      O => \p_0_in__1\(27)
    );
\crc[28]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(30),
      O => \p_0_in__1\(28)
    );
\crc[29]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \p_0_in__0\(31),
      O => \p_0_in__1\(29)
    );
\crc[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in4_in,
      O => \p_0_in__1\(2)
    );
\crc[30]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_1_in,
      O => \p_0_in__1\(30)
    );
\crc[31]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_1_in56_in,
      O => \p_0_in__1\(31)
    );
\crc[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in7_in,
      O => \p_0_in__1\(3)
    );
\crc[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in10_in,
      O => \p_0_in__1\(4)
    );
\crc[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in13_in,
      O => \p_0_in__1\(5)
    );
\crc[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in16_in,
      O => \p_0_in__1\(6)
    );
\crc[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in19_in,
      O => \p_0_in__1\(7)
    );
\crc[8]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in22_in,
      O => \p_0_in__1\(8)
    );
\crc[9]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in25_in,
      O => \p_0_in__1\(9)
    );
\crc_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(0),
      Q => crc_calculated(0),
      R => '0'
    );
\crc_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(10),
      Q => crc_calculated(10),
      R => '0'
    );
\crc_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(11),
      Q => crc_calculated(11),
      R => '0'
    );
\crc_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(12),
      Q => crc_calculated(12),
      R => '0'
    );
\crc_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(13),
      Q => crc_calculated(13),
      R => '0'
    );
\crc_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(14),
      Q => crc_calculated(14),
      R => '0'
    );
\crc_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(15),
      Q => crc_calculated(15),
      R => '0'
    );
\crc_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(16),
      Q => crc_calculated(16),
      R => '0'
    );
\crc_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(17),
      Q => crc_calculated(17),
      R => '0'
    );
\crc_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(18),
      Q => crc_calculated(18),
      R => '0'
    );
\crc_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(19),
      Q => crc_calculated(19),
      R => '0'
    );
\crc_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(1),
      Q => crc_calculated(1),
      R => '0'
    );
\crc_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(20),
      Q => crc_calculated(20),
      R => '0'
    );
\crc_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(21),
      Q => crc_calculated(21),
      R => '0'
    );
\crc_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(22),
      Q => crc_calculated(22),
      R => '0'
    );
\crc_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(23),
      Q => crc_calculated(23),
      R => '0'
    );
\crc_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(24),
      Q => crc_calculated(24),
      R => '0'
    );
\crc_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(25),
      Q => crc_calculated(25),
      R => '0'
    );
\crc_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(26),
      Q => crc_calculated(26),
      R => '0'
    );
\crc_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(27),
      Q => crc_calculated(27),
      R => '0'
    );
\crc_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(28),
      Q => crc_calculated(28),
      R => '0'
    );
\crc_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(29),
      Q => crc_calculated(29),
      R => '0'
    );
\crc_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(2),
      Q => crc_calculated(2),
      R => '0'
    );
\crc_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(30),
      Q => crc_calculated(30),
      R => '0'
    );
\crc_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(31),
      Q => crc_calculated(31),
      R => '0'
    );
\crc_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(3),
      Q => crc_calculated(3),
      R => '0'
    );
\crc_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(4),
      Q => crc_calculated(4),
      R => '0'
    );
\crc_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(5),
      Q => crc_calculated(5),
      R => '0'
    );
\crc_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(6),
      Q => crc_calculated(6),
      R => '0'
    );
\crc_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(7),
      Q => crc_calculated(7),
      R => '0'
    );
\crc_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(8),
      Q => crc_calculated(8),
      R => '0'
    );
\crc_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => edge_count_reg_n_0,
      D => \p_0_in__1\(9),
      Q => crc_calculated(9),
      R => '0'
    );
edge_count_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => state_reg_0,
      I1 => edge_count_reg_n_0,
      O => edge_count_i_1_n_0
    );
edge_count_reg: unisim.vcomponents.FDCE
     port map (
      C => b_clk100mhz,
      CE => '1',
      CLR => udp_datasum_done14_out,
      D => edge_count_i_1_n_0,
      Q => edge_count_reg_n_0
    );
rst_ram_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02A2FFFF02A20000"
    )
        port map (
      I0 => rst_ram_reg,
      I1 => rst_ram_reg_0,
      I2 => Q(0),
      I3 => \^co\(0),
      I4 => rst_ram_reg_1,
      I5 => rst_ram_reg_2,
      O => \state_reg[3]\
    );
rst_ram_i_10: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crc_rx(21),
      I1 => crc_calculated(21),
      I2 => crc_rx(22),
      I3 => crc_calculated(22),
      I4 => crc_calculated(23),
      I5 => crc_rx(23),
      O => rst_ram_i_10_n_0
    );
rst_ram_i_11: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crc_rx(18),
      I1 => crc_calculated(18),
      I2 => crc_rx(19),
      I3 => crc_calculated(19),
      I4 => crc_calculated(20),
      I5 => crc_rx(20),
      O => rst_ram_i_11_n_0
    );
rst_ram_i_12: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crc_rx(17),
      I1 => crc_calculated(17),
      I2 => crc_rx(15),
      I3 => crc_calculated(15),
      I4 => crc_calculated(16),
      I5 => crc_rx(16),
      O => rst_ram_i_12_n_0
    );
rst_ram_i_13: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crc_rx(12),
      I1 => crc_calculated(12),
      I2 => crc_rx(13),
      I3 => crc_calculated(13),
      I4 => crc_calculated(14),
      I5 => crc_rx(14),
      O => rst_ram_i_13_n_0
    );
rst_ram_i_14: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crc_rx(9),
      I1 => crc_calculated(9),
      I2 => crc_rx(10),
      I3 => crc_calculated(10),
      I4 => crc_calculated(11),
      I5 => crc_rx(11),
      O => rst_ram_i_14_n_0
    );
rst_ram_i_15: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crc_rx(6),
      I1 => crc_calculated(6),
      I2 => crc_rx(7),
      I3 => crc_calculated(7),
      I4 => crc_calculated(8),
      I5 => crc_rx(8),
      O => rst_ram_i_15_n_0
    );
rst_ram_i_16: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crc_rx(3),
      I1 => crc_calculated(3),
      I2 => crc_rx(4),
      I3 => crc_calculated(4),
      I4 => crc_calculated(5),
      I5 => crc_rx(5),
      O => rst_ram_i_16_n_0
    );
rst_ram_i_17: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crc_rx(2),
      I1 => crc_calculated(2),
      I2 => crc_rx(0),
      I3 => crc_calculated(0),
      I4 => crc_calculated(1),
      I5 => crc_rx(1),
      O => rst_ram_i_17_n_0
    );
rst_ram_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => crc_calculated(31),
      I1 => crc_rx(31),
      I2 => crc_calculated(30),
      I3 => crc_rx(30),
      O => rst_ram_i_6_n_0
    );
rst_ram_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crc_rx(27),
      I1 => crc_calculated(27),
      I2 => crc_rx(28),
      I3 => crc_calculated(28),
      I4 => crc_calculated(29),
      I5 => crc_rx(29),
      O => rst_ram_i_7_n_0
    );
rst_ram_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => crc_rx(24),
      I1 => crc_calculated(24),
      I2 => crc_rx(25),
      I3 => crc_calculated(25),
      I4 => crc_calculated(26),
      I5 => crc_rx(26),
      O => rst_ram_i_8_n_0
    );
rst_ram_reg_i_3: unisim.vcomponents.CARRY4
     port map (
      CI => rst_ram_reg_i_5_n_0,
      CO(3) => NLW_rst_ram_reg_i_3_CO_UNCONNECTED(3),
      CO(2) => \^co\(0),
      CO(1) => rst_ram_reg_i_3_n_2,
      CO(0) => rst_ram_reg_i_3_n_3,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_rst_ram_reg_i_3_O_UNCONNECTED(3 downto 0),
      S(3) => '0',
      S(2) => rst_ram_i_6_n_0,
      S(1) => rst_ram_i_7_n_0,
      S(0) => rst_ram_i_8_n_0
    );
rst_ram_reg_i_5: unisim.vcomponents.CARRY4
     port map (
      CI => rst_ram_reg_i_9_n_0,
      CO(3) => rst_ram_reg_i_5_n_0,
      CO(2) => rst_ram_reg_i_5_n_1,
      CO(1) => rst_ram_reg_i_5_n_2,
      CO(0) => rst_ram_reg_i_5_n_3,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_rst_ram_reg_i_5_O_UNCONNECTED(3 downto 0),
      S(3) => rst_ram_i_10_n_0,
      S(2) => rst_ram_i_11_n_0,
      S(1) => rst_ram_i_12_n_0,
      S(0) => rst_ram_i_13_n_0
    );
rst_ram_reg_i_9: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => rst_ram_reg_i_9_n_0,
      CO(2) => rst_ram_reg_i_9_n_1,
      CO(1) => rst_ram_reg_i_9_n_2,
      CO(0) => rst_ram_reg_i_9_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_rst_ram_reg_i_9_O_UNCONNECTED(3 downto 0),
      S(3) => rst_ram_i_14_n_0,
      S(2) => rst_ram_i_15_n_0,
      S(1) => rst_ram_i_16_n_0,
      S(0) => rst_ram_i_17_n_0
    );
state_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => '1',
      CLR => udp_datasum_done14_out,
      D => state_reg_0,
      Q => state
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_ethernet_transceiver2_0_0_debounce_switch is
  port (
    db_sw : out STD_LOGIC;
    po_counter0 : out STD_LOGIC;
    clear : out STD_LOGIC;
    send_countdown0 : out STD_LOGIC;
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    db_sw_reg_0 : out STD_LOGIC;
    btn_reset : in STD_LOGIC;
    b_clk100mhz : in STD_LOGIC;
    \po_counter_reg[0]\ : in STD_LOGIC;
    \po_counter_reg[0]_0\ : in STD_LOGIC;
    state : in STD_LOGIC_VECTOR ( 0 to 0 );
    \send_countdown_reg[0]\ : in STD_LOGIC;
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    \init_proc__0\ : in STD_LOGIC
  );
end design_1_ethernet_transceiver2_0_0_debounce_switch;

architecture STRUCTURE of design_1_ethernet_transceiver2_0_0_debounce_switch is
  signal \FSM_sequential_state[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_state[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_state[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_state[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_state[2]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_state[2]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_sequential_state[2]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_sequential_state[2]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_sequential_state[2]_i_7_n_0\ : STD_LOGIC;
  signal \^db_sw\ : STD_LOGIC;
  signal db_sw_i_1_n_0 : STD_LOGIC;
  signal in9 : STD_LOGIC_VECTOR ( 21 downto 1 );
  signal \minusOp_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \minusOp_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \minusOp_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \minusOp_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \minusOp_carry__0_n_0\ : STD_LOGIC;
  signal \minusOp_carry__0_n_1\ : STD_LOGIC;
  signal \minusOp_carry__0_n_2\ : STD_LOGIC;
  signal \minusOp_carry__0_n_3\ : STD_LOGIC;
  signal \minusOp_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \minusOp_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \minusOp_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \minusOp_carry__1_i_4_n_0\ : STD_LOGIC;
  signal \minusOp_carry__1_n_0\ : STD_LOGIC;
  signal \minusOp_carry__1_n_1\ : STD_LOGIC;
  signal \minusOp_carry__1_n_2\ : STD_LOGIC;
  signal \minusOp_carry__1_n_3\ : STD_LOGIC;
  signal \minusOp_carry__2_i_1_n_0\ : STD_LOGIC;
  signal \minusOp_carry__2_i_2_n_0\ : STD_LOGIC;
  signal \minusOp_carry__2_i_3_n_0\ : STD_LOGIC;
  signal \minusOp_carry__2_i_4_n_0\ : STD_LOGIC;
  signal \minusOp_carry__2_n_0\ : STD_LOGIC;
  signal \minusOp_carry__2_n_1\ : STD_LOGIC;
  signal \minusOp_carry__2_n_2\ : STD_LOGIC;
  signal \minusOp_carry__2_n_3\ : STD_LOGIC;
  signal \minusOp_carry__3_i_1_n_0\ : STD_LOGIC;
  signal \minusOp_carry__3_i_2_n_0\ : STD_LOGIC;
  signal \minusOp_carry__3_i_3_n_0\ : STD_LOGIC;
  signal \minusOp_carry__3_i_4_n_0\ : STD_LOGIC;
  signal \minusOp_carry__3_n_0\ : STD_LOGIC;
  signal \minusOp_carry__3_n_1\ : STD_LOGIC;
  signal \minusOp_carry__3_n_2\ : STD_LOGIC;
  signal \minusOp_carry__3_n_3\ : STD_LOGIC;
  signal \minusOp_carry__4_i_1_n_0\ : STD_LOGIC;
  signal minusOp_carry_i_1_n_0 : STD_LOGIC;
  signal minusOp_carry_i_2_n_0 : STD_LOGIC;
  signal minusOp_carry_i_3_n_0 : STD_LOGIC;
  signal minusOp_carry_i_4_n_0 : STD_LOGIC;
  signal minusOp_carry_n_0 : STD_LOGIC;
  signal minusOp_carry_n_1 : STD_LOGIC;
  signal minusOp_carry_n_2 : STD_LOGIC;
  signal minusOp_carry_n_3 : STD_LOGIC;
  signal \state__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal sw : STD_LOGIC;
  signal timer : STD_LOGIC;
  signal \timer[0]_i_1_n_0\ : STD_LOGIC;
  signal \timer[10]_i_1_n_0\ : STD_LOGIC;
  signal \timer[11]_i_1_n_0\ : STD_LOGIC;
  signal \timer[12]_i_1_n_0\ : STD_LOGIC;
  signal \timer[13]_i_1_n_0\ : STD_LOGIC;
  signal \timer[14]_i_1_n_0\ : STD_LOGIC;
  signal \timer[15]_i_1_n_0\ : STD_LOGIC;
  signal \timer[16]_i_1_n_0\ : STD_LOGIC;
  signal \timer[17]_i_1_n_0\ : STD_LOGIC;
  signal \timer[18]_i_1_n_0\ : STD_LOGIC;
  signal \timer[19]_i_1_n_0\ : STD_LOGIC;
  signal \timer[1]_i_1_n_0\ : STD_LOGIC;
  signal \timer[20]_i_1_n_0\ : STD_LOGIC;
  signal \timer[21]_i_1_n_0\ : STD_LOGIC;
  signal \timer[21]_i_3_n_0\ : STD_LOGIC;
  signal \timer[2]_i_1_n_0\ : STD_LOGIC;
  signal \timer[3]_i_1_n_0\ : STD_LOGIC;
  signal \timer[4]_i_1_n_0\ : STD_LOGIC;
  signal \timer[5]_i_1_n_0\ : STD_LOGIC;
  signal \timer[6]_i_1_n_0\ : STD_LOGIC;
  signal \timer[7]_i_1_n_0\ : STD_LOGIC;
  signal \timer[8]_i_1_n_0\ : STD_LOGIC;
  signal \timer[9]_i_1_n_0\ : STD_LOGIC;
  signal \timer_reg_n_0_[0]\ : STD_LOGIC;
  signal \timer_reg_n_0_[10]\ : STD_LOGIC;
  signal \timer_reg_n_0_[11]\ : STD_LOGIC;
  signal \timer_reg_n_0_[12]\ : STD_LOGIC;
  signal \timer_reg_n_0_[13]\ : STD_LOGIC;
  signal \timer_reg_n_0_[14]\ : STD_LOGIC;
  signal \timer_reg_n_0_[15]\ : STD_LOGIC;
  signal \timer_reg_n_0_[16]\ : STD_LOGIC;
  signal \timer_reg_n_0_[17]\ : STD_LOGIC;
  signal \timer_reg_n_0_[18]\ : STD_LOGIC;
  signal \timer_reg_n_0_[19]\ : STD_LOGIC;
  signal \timer_reg_n_0_[1]\ : STD_LOGIC;
  signal \timer_reg_n_0_[20]\ : STD_LOGIC;
  signal \timer_reg_n_0_[21]\ : STD_LOGIC;
  signal \timer_reg_n_0_[2]\ : STD_LOGIC;
  signal \timer_reg_n_0_[3]\ : STD_LOGIC;
  signal \timer_reg_n_0_[4]\ : STD_LOGIC;
  signal \timer_reg_n_0_[5]\ : STD_LOGIC;
  signal \timer_reg_n_0_[6]\ : STD_LOGIC;
  signal \timer_reg_n_0_[7]\ : STD_LOGIC;
  signal \timer_reg_n_0_[8]\ : STD_LOGIC;
  signal \timer_reg_n_0_[9]\ : STD_LOGIC;
  signal \NLW_minusOp_carry__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_minusOp_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[0]\ : label is "zero:011,wait1:100,one:001,init:000,wait0:010";
  attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[1]\ : label is "zero:011,wait1:100,one:001,init:000,wait0:010";
  attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[2]\ : label is "zero:011,wait1:100,one:001,init:000,wait0:010";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \datacm_send[10]_i_1\ : label is "soft_lutpair343";
  attribute SOFT_HLUTNM of eth_rstn_i_2 : label is "soft_lutpair343";
  attribute SOFT_HLUTNM of init_proc_i_1 : label is "soft_lutpair331";
  attribute SOFT_HLUTNM of \po_counter[0]_i_1\ : label is "soft_lutpair331";
  attribute SOFT_HLUTNM of \timer[0]_i_1\ : label is "soft_lutpair336";
  attribute SOFT_HLUTNM of \timer[10]_i_1\ : label is "soft_lutpair338";
  attribute SOFT_HLUTNM of \timer[11]_i_1\ : label is "soft_lutpair333";
  attribute SOFT_HLUTNM of \timer[12]_i_1\ : label is "soft_lutpair334";
  attribute SOFT_HLUTNM of \timer[13]_i_1\ : label is "soft_lutpair337";
  attribute SOFT_HLUTNM of \timer[14]_i_1\ : label is "soft_lutpair337";
  attribute SOFT_HLUTNM of \timer[15]_i_1\ : label is "soft_lutpair336";
  attribute SOFT_HLUTNM of \timer[16]_i_1\ : label is "soft_lutpair335";
  attribute SOFT_HLUTNM of \timer[17]_i_1\ : label is "soft_lutpair332";
  attribute SOFT_HLUTNM of \timer[18]_i_1\ : label is "soft_lutpair335";
  attribute SOFT_HLUTNM of \timer[19]_i_1\ : label is "soft_lutpair334";
  attribute SOFT_HLUTNM of \timer[1]_i_1\ : label is "soft_lutpair338";
  attribute SOFT_HLUTNM of \timer[20]_i_1\ : label is "soft_lutpair333";
  attribute SOFT_HLUTNM of \timer[21]_i_3\ : label is "soft_lutpair332";
  attribute SOFT_HLUTNM of \timer[2]_i_1\ : label is "soft_lutpair342";
  attribute SOFT_HLUTNM of \timer[3]_i_1\ : label is "soft_lutpair342";
  attribute SOFT_HLUTNM of \timer[4]_i_1\ : label is "soft_lutpair341";
  attribute SOFT_HLUTNM of \timer[5]_i_1\ : label is "soft_lutpair341";
  attribute SOFT_HLUTNM of \timer[6]_i_1\ : label is "soft_lutpair339";
  attribute SOFT_HLUTNM of \timer[7]_i_1\ : label is "soft_lutpair340";
  attribute SOFT_HLUTNM of \timer[8]_i_1\ : label is "soft_lutpair340";
  attribute SOFT_HLUTNM of \timer[9]_i_1\ : label is "soft_lutpair339";
begin
  db_sw <= \^db_sw\;
\FSM_sequential_state[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000990F"
    )
        port map (
      I0 => sw,
      I1 => btn_reset,
      I2 => \state__0\(1),
      I3 => \state__0\(0),
      I4 => \state__0\(2),
      O => \FSM_sequential_state[0]_i_1_n_0\
    );
\FSM_sequential_state[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"090F060509000605"
    )
        port map (
      I0 => btn_reset,
      I1 => sw,
      I2 => \state__0\(2),
      I3 => \state__0\(0),
      I4 => \state__0\(1),
      I5 => \FSM_sequential_state[2]_i_3_n_0\,
      O => \FSM_sequential_state[1]_i_1_n_0\
    );
\FSM_sequential_state[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1F"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(0),
      I2 => \state__0\(2),
      O => \FSM_sequential_state[2]_i_1_n_0\
    );
\FSM_sequential_state[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA3CAA00AA00AA00"
    )
        port map (
      I0 => \FSM_sequential_state[2]_i_3_n_0\,
      I1 => sw,
      I2 => btn_reset,
      I3 => \state__0\(2),
      I4 => \state__0\(0),
      I5 => \state__0\(1),
      O => \FSM_sequential_state[2]_i_2_n_0\
    );
\FSM_sequential_state[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_sequential_state[2]_i_4_n_0\,
      I1 => \FSM_sequential_state[2]_i_5_n_0\,
      I2 => \timer_reg_n_0_[3]\,
      I3 => \timer_reg_n_0_[2]\,
      I4 => \timer_reg_n_0_[5]\,
      I5 => \timer_reg_n_0_[4]\,
      O => \FSM_sequential_state[2]_i_3_n_0\
    );
\FSM_sequential_state[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_sequential_state[2]_i_6_n_0\,
      I1 => \timer_reg_n_0_[11]\,
      I2 => \timer_reg_n_0_[10]\,
      I3 => \timer_reg_n_0_[13]\,
      I4 => \timer_reg_n_0_[12]\,
      I5 => \FSM_sequential_state[2]_i_7_n_0\,
      O => \FSM_sequential_state[2]_i_4_n_0\
    );
\FSM_sequential_state[2]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \timer_reg_n_0_[7]\,
      I1 => \timer_reg_n_0_[6]\,
      I2 => \timer_reg_n_0_[9]\,
      I3 => \timer_reg_n_0_[8]\,
      O => \FSM_sequential_state[2]_i_5_n_0\
    );
\FSM_sequential_state[2]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \timer_reg_n_0_[15]\,
      I1 => \timer_reg_n_0_[14]\,
      I2 => \timer_reg_n_0_[17]\,
      I3 => \timer_reg_n_0_[16]\,
      O => \FSM_sequential_state[2]_i_6_n_0\
    );
\FSM_sequential_state[2]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \timer_reg_n_0_[20]\,
      I1 => \timer_reg_n_0_[21]\,
      I2 => \timer_reg_n_0_[18]\,
      I3 => \timer_reg_n_0_[19]\,
      I4 => \timer_reg_n_0_[1]\,
      I5 => \timer_reg_n_0_[0]\,
      O => \FSM_sequential_state[2]_i_7_n_0\
    );
\FSM_sequential_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => \FSM_sequential_state[2]_i_1_n_0\,
      D => \FSM_sequential_state[0]_i_1_n_0\,
      Q => \state__0\(0),
      R => '0'
    );
\FSM_sequential_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => \FSM_sequential_state[2]_i_1_n_0\,
      D => \FSM_sequential_state[1]_i_1_n_0\,
      Q => \state__0\(1),
      R => '0'
    );
\FSM_sequential_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => \FSM_sequential_state[2]_i_1_n_0\,
      D => \FSM_sequential_state[2]_i_2_n_0\,
      Q => \state__0\(2),
      R => '0'
    );
\datacm_send[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^db_sw\,
      I1 => CO(0),
      O => SR(0)
    );
db_sw_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"07170604"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(0),
      I2 => \state__0\(2),
      I3 => \FSM_sequential_state[2]_i_3_n_0\,
      I4 => btn_reset,
      O => db_sw_i_1_n_0
    );
db_sw_reg: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => \FSM_sequential_state[2]_i_1_n_0\,
      D => db_sw_i_1_n_0,
      Q => \^db_sw\,
      R => '0'
    );
eth_rstn_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^db_sw\,
      O => clear
    );
init_proc_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4000"
    )
        port map (
      I0 => \po_counter_reg[0]\,
      I1 => \^db_sw\,
      I2 => state(0),
      I3 => \po_counter_reg[0]_0\,
      I4 => \init_proc__0\,
      O => db_sw_reg_0
    );
minusOp_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => minusOp_carry_n_0,
      CO(2) => minusOp_carry_n_1,
      CO(1) => minusOp_carry_n_2,
      CO(0) => minusOp_carry_n_3,
      CYINIT => \timer_reg_n_0_[0]\,
      DI(3) => \timer_reg_n_0_[4]\,
      DI(2) => \timer_reg_n_0_[3]\,
      DI(1) => \timer_reg_n_0_[2]\,
      DI(0) => \timer_reg_n_0_[1]\,
      O(3 downto 0) => in9(4 downto 1),
      S(3) => minusOp_carry_i_1_n_0,
      S(2) => minusOp_carry_i_2_n_0,
      S(1) => minusOp_carry_i_3_n_0,
      S(0) => minusOp_carry_i_4_n_0
    );
\minusOp_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => minusOp_carry_n_0,
      CO(3) => \minusOp_carry__0_n_0\,
      CO(2) => \minusOp_carry__0_n_1\,
      CO(1) => \minusOp_carry__0_n_2\,
      CO(0) => \minusOp_carry__0_n_3\,
      CYINIT => '0',
      DI(3) => \timer_reg_n_0_[8]\,
      DI(2) => \timer_reg_n_0_[7]\,
      DI(1) => \timer_reg_n_0_[6]\,
      DI(0) => \timer_reg_n_0_[5]\,
      O(3 downto 0) => in9(8 downto 5),
      S(3) => \minusOp_carry__0_i_1_n_0\,
      S(2) => \minusOp_carry__0_i_2_n_0\,
      S(1) => \minusOp_carry__0_i_3_n_0\,
      S(0) => \minusOp_carry__0_i_4_n_0\
    );
\minusOp_carry__0_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[8]\,
      O => \minusOp_carry__0_i_1_n_0\
    );
\minusOp_carry__0_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[7]\,
      O => \minusOp_carry__0_i_2_n_0\
    );
\minusOp_carry__0_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[6]\,
      O => \minusOp_carry__0_i_3_n_0\
    );
\minusOp_carry__0_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[5]\,
      O => \minusOp_carry__0_i_4_n_0\
    );
\minusOp_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \minusOp_carry__0_n_0\,
      CO(3) => \minusOp_carry__1_n_0\,
      CO(2) => \minusOp_carry__1_n_1\,
      CO(1) => \minusOp_carry__1_n_2\,
      CO(0) => \minusOp_carry__1_n_3\,
      CYINIT => '0',
      DI(3) => \timer_reg_n_0_[12]\,
      DI(2) => \timer_reg_n_0_[11]\,
      DI(1) => \timer_reg_n_0_[10]\,
      DI(0) => \timer_reg_n_0_[9]\,
      O(3 downto 0) => in9(12 downto 9),
      S(3) => \minusOp_carry__1_i_1_n_0\,
      S(2) => \minusOp_carry__1_i_2_n_0\,
      S(1) => \minusOp_carry__1_i_3_n_0\,
      S(0) => \minusOp_carry__1_i_4_n_0\
    );
\minusOp_carry__1_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[12]\,
      O => \minusOp_carry__1_i_1_n_0\
    );
\minusOp_carry__1_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[11]\,
      O => \minusOp_carry__1_i_2_n_0\
    );
\minusOp_carry__1_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[10]\,
      O => \minusOp_carry__1_i_3_n_0\
    );
\minusOp_carry__1_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[9]\,
      O => \minusOp_carry__1_i_4_n_0\
    );
\minusOp_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \minusOp_carry__1_n_0\,
      CO(3) => \minusOp_carry__2_n_0\,
      CO(2) => \minusOp_carry__2_n_1\,
      CO(1) => \minusOp_carry__2_n_2\,
      CO(0) => \minusOp_carry__2_n_3\,
      CYINIT => '0',
      DI(3) => \timer_reg_n_0_[16]\,
      DI(2) => \timer_reg_n_0_[15]\,
      DI(1) => \timer_reg_n_0_[14]\,
      DI(0) => \timer_reg_n_0_[13]\,
      O(3 downto 0) => in9(16 downto 13),
      S(3) => \minusOp_carry__2_i_1_n_0\,
      S(2) => \minusOp_carry__2_i_2_n_0\,
      S(1) => \minusOp_carry__2_i_3_n_0\,
      S(0) => \minusOp_carry__2_i_4_n_0\
    );
\minusOp_carry__2_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[16]\,
      O => \minusOp_carry__2_i_1_n_0\
    );
\minusOp_carry__2_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[15]\,
      O => \minusOp_carry__2_i_2_n_0\
    );
\minusOp_carry__2_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[14]\,
      O => \minusOp_carry__2_i_3_n_0\
    );
\minusOp_carry__2_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[13]\,
      O => \minusOp_carry__2_i_4_n_0\
    );
\minusOp_carry__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \minusOp_carry__2_n_0\,
      CO(3) => \minusOp_carry__3_n_0\,
      CO(2) => \minusOp_carry__3_n_1\,
      CO(1) => \minusOp_carry__3_n_2\,
      CO(0) => \minusOp_carry__3_n_3\,
      CYINIT => '0',
      DI(3) => \timer_reg_n_0_[20]\,
      DI(2) => \timer_reg_n_0_[19]\,
      DI(1) => \timer_reg_n_0_[18]\,
      DI(0) => \timer_reg_n_0_[17]\,
      O(3 downto 0) => in9(20 downto 17),
      S(3) => \minusOp_carry__3_i_1_n_0\,
      S(2) => \minusOp_carry__3_i_2_n_0\,
      S(1) => \minusOp_carry__3_i_3_n_0\,
      S(0) => \minusOp_carry__3_i_4_n_0\
    );
\minusOp_carry__3_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[20]\,
      O => \minusOp_carry__3_i_1_n_0\
    );
\minusOp_carry__3_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[19]\,
      O => \minusOp_carry__3_i_2_n_0\
    );
\minusOp_carry__3_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[18]\,
      O => \minusOp_carry__3_i_3_n_0\
    );
\minusOp_carry__3_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[17]\,
      O => \minusOp_carry__3_i_4_n_0\
    );
\minusOp_carry__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \minusOp_carry__3_n_0\,
      CO(3 downto 0) => \NLW_minusOp_carry__4_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_minusOp_carry__4_O_UNCONNECTED\(3 downto 1),
      O(0) => in9(21),
      S(3 downto 1) => B"000",
      S(0) => \minusOp_carry__4_i_1_n_0\
    );
\minusOp_carry__4_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[21]\,
      O => \minusOp_carry__4_i_1_n_0\
    );
minusOp_carry_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[4]\,
      O => minusOp_carry_i_1_n_0
    );
minusOp_carry_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[3]\,
      O => minusOp_carry_i_2_n_0
    );
minusOp_carry_i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[2]\,
      O => minusOp_carry_i_3_n_0
    );
minusOp_carry_i_4: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \timer_reg_n_0_[1]\,
      O => minusOp_carry_i_4_n_0
    );
\po_counter[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7000"
    )
        port map (
      I0 => \po_counter_reg[0]\,
      I1 => \po_counter_reg[0]_0\,
      I2 => \^db_sw\,
      I3 => state(0),
      O => po_counter0
    );
\send_countdown[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^db_sw\,
      I1 => \send_countdown_reg[0]\,
      O => send_countdown0
    );
sw_reg: unisim.vcomponents.FDRE
     port map (
      C => b_clk100mhz,
      CE => '1',
      D => btn_reset,
      Q => sw,
      R => '0'
    );
\timer[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"07"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => \timer_reg_n_0_[0]\,
      O => \timer[0]_i_1_n_0\
    );
\timer[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(10),
      O => \timer[10]_i_1_n_0\
    );
\timer[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(11),
      O => \timer[11]_i_1_n_0\
    );
\timer[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(12),
      O => \timer[12]_i_1_n_0\
    );
\timer[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(13),
      O => \timer[13]_i_1_n_0\
    );
\timer[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(14),
      O => \timer[14]_i_1_n_0\
    );
\timer[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(15),
      O => \timer[15]_i_1_n_0\
    );
\timer[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(16),
      O => \timer[16]_i_1_n_0\
    );
\timer[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(17),
      O => \timer[17]_i_1_n_0\
    );
\timer[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(18),
      O => \timer[18]_i_1_n_0\
    );
\timer[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(19),
      O => \timer[19]_i_1_n_0\
    );
\timer[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(1),
      O => \timer[1]_i_1_n_0\
    );
\timer[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(20),
      O => \timer[20]_i_1_n_0\
    );
\timer[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(0),
      I2 => \state__0\(2),
      O => \timer[21]_i_1_n_0\
    );
\timer[21]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"020B"
    )
        port map (
      I0 => \FSM_sequential_state[2]_i_3_n_0\,
      I1 => \state__0\(1),
      I2 => \state__0\(0),
      I3 => \state__0\(2),
      O => timer
    );
\timer[21]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(21),
      O => \timer[21]_i_3_n_0\
    );
\timer[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(2),
      O => \timer[2]_i_1_n_0\
    );
\timer[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(3),
      O => \timer[3]_i_1_n_0\
    );
\timer[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(4),
      O => \timer[4]_i_1_n_0\
    );
\timer[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(5),
      O => \timer[5]_i_1_n_0\
    );
\timer[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(6),
      O => \timer[6]_i_1_n_0\
    );
\timer[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(7),
      O => \timer[7]_i_1_n_0\
    );
\timer[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(8),
      O => \timer[8]_i_1_n_0\
    );
\timer[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"70"
    )
        port map (
      I0 => \state__0\(1),
      I1 => \state__0\(2),
      I2 => in9(9),
      O => \timer[9]_i_1_n_0\
    );
\timer_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[0]_i_1_n_0\,
      Q => \timer_reg_n_0_[0]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[10]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[10]_i_1_n_0\,
      Q => \timer_reg_n_0_[10]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[11]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[11]_i_1_n_0\,
      Q => \timer_reg_n_0_[11]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[12]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[12]_i_1_n_0\,
      Q => \timer_reg_n_0_[12]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[13]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[13]_i_1_n_0\,
      Q => \timer_reg_n_0_[13]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[14]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[14]_i_1_n_0\,
      Q => \timer_reg_n_0_[14]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[15]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[15]_i_1_n_0\,
      Q => \timer_reg_n_0_[15]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[16]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[16]_i_1_n_0\,
      Q => \timer_reg_n_0_[16]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[17]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[17]_i_1_n_0\,
      Q => \timer_reg_n_0_[17]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[18]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[18]_i_1_n_0\,
      Q => \timer_reg_n_0_[18]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[19]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[19]_i_1_n_0\,
      Q => \timer_reg_n_0_[19]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[1]_i_1_n_0\,
      Q => \timer_reg_n_0_[1]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[20]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[20]_i_1_n_0\,
      Q => \timer_reg_n_0_[20]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[21]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[21]_i_3_n_0\,
      Q => \timer_reg_n_0_[21]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[2]_i_1_n_0\,
      Q => \timer_reg_n_0_[2]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[3]_i_1_n_0\,
      Q => \timer_reg_n_0_[3]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[4]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[4]_i_1_n_0\,
      Q => \timer_reg_n_0_[4]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[5]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[5]_i_1_n_0\,
      Q => \timer_reg_n_0_[5]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[6]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[6]_i_1_n_0\,
      Q => \timer_reg_n_0_[6]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[7]_i_1_n_0\,
      Q => \timer_reg_n_0_[7]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[8]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[8]_i_1_n_0\,
      Q => \timer_reg_n_0_[8]\,
      S => \timer[21]_i_1_n_0\
    );
\timer_reg[9]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk100mhz,
      CE => timer,
      D => \timer[9]_i_1_n_0\,
      Q => \timer_reg_n_0_[9]\,
      S => \timer[21]_i_1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_ethernet_transceiver2_0_0_led1 is
  port (
    led16_b : out STD_LOGIC;
    led16_g : out STD_LOGIC;
    led16_r : out STD_LOGIC;
    led17_b : out STD_LOGIC;
    led17_g : out STD_LOGIC;
    led17_r : out STD_LOGIC;
    CLK : in STD_LOGIC;
    led17_g_reg_0 : in STD_LOGIC;
    send_arp_reply : in STD_LOGIC;
    udp_packet_recieved : in STD_LOGIC
  );
end design_1_ethernet_transceiver2_0_0_led1;

architecture STRUCTURE of design_1_ethernet_transceiver2_0_0_led1 is
  signal \count_arp[0]_i_1_n_0\ : STD_LOGIC;
  signal \count_arp[1]_i_1_n_0\ : STD_LOGIC;
  signal \count_arp_reg_n_0_[0]\ : STD_LOGIC;
  signal \count_arp_reg_n_0_[1]\ : STD_LOGIC;
  signal \count_eth[0]_i_1_n_0\ : STD_LOGIC;
  signal \count_eth[1]_i_1_n_0\ : STD_LOGIC;
  signal \count_eth_reg_n_0_[0]\ : STD_LOGIC;
  signal \count_eth_reg_n_0_[1]\ : STD_LOGIC;
  signal led16_b_i_1_n_0 : STD_LOGIC;
  signal led16_g_i_1_n_0 : STD_LOGIC;
  signal led16_r_i_1_n_0 : STD_LOGIC;
  signal led17_b_i_1_n_0 : STD_LOGIC;
  signal led17_g_i_1_n_0 : STD_LOGIC;
  signal led17_r_i_1_n_0 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \count_arp[0]_i_1\ : label is "soft_lutpair319";
  attribute SOFT_HLUTNM of \count_arp[1]_i_1\ : label is "soft_lutpair319";
  attribute SOFT_HLUTNM of \count_eth[0]_i_1\ : label is "soft_lutpair318";
  attribute SOFT_HLUTNM of \count_eth[1]_i_1\ : label is "soft_lutpair318";
  attribute SOFT_HLUTNM of led16_b_i_1 : label is "soft_lutpair321";
  attribute SOFT_HLUTNM of led16_r_i_1 : label is "soft_lutpair321";
  attribute SOFT_HLUTNM of led17_b_i_1 : label is "soft_lutpair320";
  attribute SOFT_HLUTNM of led17_r_i_1 : label is "soft_lutpair320";
begin
\count_arp[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BC"
    )
        port map (
      I0 => \count_arp_reg_n_0_[1]\,
      I1 => send_arp_reply,
      I2 => \count_arp_reg_n_0_[0]\,
      O => \count_arp[0]_i_1_n_0\
    );
\count_arp[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \count_arp_reg_n_0_[0]\,
      I1 => send_arp_reply,
      I2 => \count_arp_reg_n_0_[1]\,
      O => \count_arp[1]_i_1_n_0\
    );
\count_arp_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      CLR => led17_g_reg_0,
      D => \count_arp[0]_i_1_n_0\,
      Q => \count_arp_reg_n_0_[0]\
    );
\count_arp_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      CLR => led17_g_reg_0,
      D => \count_arp[1]_i_1_n_0\,
      Q => \count_arp_reg_n_0_[1]\
    );
\count_eth[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BC"
    )
        port map (
      I0 => \count_eth_reg_n_0_[1]\,
      I1 => udp_packet_recieved,
      I2 => \count_eth_reg_n_0_[0]\,
      O => \count_eth[0]_i_1_n_0\
    );
\count_eth[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \count_eth_reg_n_0_[0]\,
      I1 => udp_packet_recieved,
      I2 => \count_eth_reg_n_0_[1]\,
      O => \count_eth[1]_i_1_n_0\
    );
\count_eth_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      CLR => led17_g_reg_0,
      D => \count_eth[0]_i_1_n_0\,
      Q => \count_eth_reg_n_0_[0]\
    );
\count_eth_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      CLR => led17_g_reg_0,
      D => \count_eth[1]_i_1_n_0\,
      Q => \count_eth_reg_n_0_[1]\
    );
led16_b_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \count_arp_reg_n_0_[0]\,
      I1 => \count_arp_reg_n_0_[1]\,
      O => led16_b_i_1_n_0
    );
led16_b_reg: unisim.vcomponents.FDCE
     port map (
      C => CLK,
      CE => '1',
      CLR => led17_g_reg_0,
      D => led16_b_i_1_n_0,
      Q => led16_b
    );
led16_g_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \count_arp_reg_n_0_[1]\,
      I1 => \count_arp_reg_n_0_[0]\,
      O => led16_g_i_1_n_0
    );
led16_g_reg: unisim.vcomponents.FDCE
     port map (
      C => CLK,
      CE => '1',
      CLR => led17_g_reg_0,
      D => led16_g_i_1_n_0,
      Q => led16_g
    );
led16_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \count_arp_reg_n_0_[0]\,
      I1 => \count_arp_reg_n_0_[1]\,
      O => led16_r_i_1_n_0
    );
led16_r_reg: unisim.vcomponents.FDCE
     port map (
      C => CLK,
      CE => '1',
      CLR => led17_g_reg_0,
      D => led16_r_i_1_n_0,
      Q => led16_r
    );
led17_b_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \count_eth_reg_n_0_[0]\,
      I1 => \count_eth_reg_n_0_[1]\,
      O => led17_b_i_1_n_0
    );
led17_b_reg: unisim.vcomponents.FDCE
     port map (
      C => CLK,
      CE => '1',
      CLR => led17_g_reg_0,
      D => led17_b_i_1_n_0,
      Q => led17_b
    );
led17_g_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \count_eth_reg_n_0_[1]\,
      I1 => \count_eth_reg_n_0_[0]\,
      O => led17_g_i_1_n_0
    );
led17_g_reg: unisim.vcomponents.FDCE
     port map (
      C => CLK,
      CE => '1',
      CLR => led17_g_reg_0,
      D => led17_g_i_1_n_0,
      Q => led17_g
    );
led17_r_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \count_eth_reg_n_0_[0]\,
      I1 => \count_eth_reg_n_0_[1]\,
      O => led17_r_i_1_n_0
    );
led17_r_reg: unisim.vcomponents.FDCE
     port map (
      C => CLK,
      CE => '1',
      CLR => led17_g_reg_0,
      D => led17_r_i_1_n_0,
      Q => led17_r
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_ethernet_transceiver2_0_0_md_interface is
  port (
    led : out STD_LOGIC_VECTOR ( 15 downto 0 );
    eth_mdio : inout STD_LOGIC;
    b_clk2_5mhz_shift : in STD_LOGIC;
    state_reg_0 : in STD_LOGIC;
    eth_rstn : in STD_LOGIC
  );
end design_1_ethernet_transceiver2_0_0_md_interface;

architecture STRUCTURE of design_1_ethernet_transceiver2_0_0_md_interface is
  signal counter : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \counter[0]_i_1_n_0\ : STD_LOGIC;
  signal \counter[1]_i_1_n_0\ : STD_LOGIC;
  signal \counter[2]_i_1_n_0\ : STD_LOGIC;
  signal \counter[3]_i_1_n_0\ : STD_LOGIC;
  signal \counter[4]_i_1_n_0\ : STD_LOGIC;
  signal \counter[5]_i_1_n_0\ : STD_LOGIC;
  signal \counter[5]_i_2_n_0\ : STD_LOGIC;
  signal eth_mdio_INST_0_i_1_n_0 : STD_LOGIC;
  signal \^led\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal mdio_prime_i_1_n_0 : STD_LOGIC;
  signal mdio_prime_i_2_n_0 : STD_LOGIC;
  signal mdio_prime_i_3_n_0 : STD_LOGIC;
  signal mdio_prime_reg_n_0 : STD_LOGIC;
  signal \reg_data[0]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[0]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[10]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[10]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[11]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[11]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[12]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[12]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[12]_i_3_n_0\ : STD_LOGIC;
  signal \reg_data[13]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[13]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[13]_i_3_n_0\ : STD_LOGIC;
  signal \reg_data[14]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[14]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[14]_i_3_n_0\ : STD_LOGIC;
  signal \reg_data[15]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[15]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[15]_i_3_n_0\ : STD_LOGIC;
  signal \reg_data[1]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[1]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[2]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[2]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[3]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[3]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[4]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[4]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[5]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[5]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[6]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[6]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[7]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[7]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[8]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[8]_i_2_n_0\ : STD_LOGIC;
  signal \reg_data[9]_i_1_n_0\ : STD_LOGIC;
  signal \reg_data[9]_i_2_n_0\ : STD_LOGIC;
  signal state_i_1_n_0 : STD_LOGIC;
  signal state_i_2_n_0 : STD_LOGIC;
  signal state_reg_n_0 : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of PULLUP_MDIO : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \counter[0]_i_1\ : label is "soft_lutpair328";
  attribute SOFT_HLUTNM of \counter[1]_i_1\ : label is "soft_lutpair328";
  attribute SOFT_HLUTNM of \counter[2]_i_1\ : label is "soft_lutpair326";
  attribute SOFT_HLUTNM of \counter[3]_i_1\ : label is "soft_lutpair326";
  attribute SOFT_HLUTNM of \counter[5]_i_2\ : label is "soft_lutpair330";
  attribute SOFT_HLUTNM of eth_mdio_INST_0_i_1 : label is "soft_lutpair327";
  attribute SOFT_HLUTNM of mdio_prime_i_1 : label is "soft_lutpair327";
  attribute SOFT_HLUTNM of \reg_data[10]_i_2\ : label is "soft_lutpair323";
  attribute SOFT_HLUTNM of \reg_data[13]_i_2\ : label is "soft_lutpair325";
  attribute SOFT_HLUTNM of \reg_data[13]_i_3\ : label is "soft_lutpair329";
  attribute SOFT_HLUTNM of \reg_data[14]_i_3\ : label is "soft_lutpair329";
  attribute SOFT_HLUTNM of \reg_data[15]_i_2\ : label is "soft_lutpair322";
  attribute SOFT_HLUTNM of \reg_data[15]_i_3\ : label is "soft_lutpair330";
  attribute SOFT_HLUTNM of \reg_data[5]_i_2\ : label is "soft_lutpair324";
  attribute SOFT_HLUTNM of \reg_data[6]_i_2\ : label is "soft_lutpair323";
  attribute SOFT_HLUTNM of \reg_data[7]_i_2\ : label is "soft_lutpair322";
  attribute SOFT_HLUTNM of \reg_data[9]_i_2\ : label is "soft_lutpair324";
  attribute SOFT_HLUTNM of state_i_2 : label is "soft_lutpair325";
begin
  led(15 downto 0) <= \^led\(15 downto 0);
PULLUP_MDIO: unisim.vcomponents.PULLUP
     port map (
      O => eth_mdio
    );
\counter[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => state_reg_n_0,
      I1 => counter(0),
      O => \counter[0]_i_1_n_0\
    );
\counter[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => state_reg_n_0,
      I1 => counter(0),
      I2 => counter(1),
      O => \counter[1]_i_1_n_0\
    );
\counter[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => state_reg_n_0,
      I1 => counter(1),
      I2 => counter(0),
      I3 => counter(2),
      O => \counter[2]_i_1_n_0\
    );
\counter[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAA8000"
    )
        port map (
      I0 => state_reg_n_0,
      I1 => counter(0),
      I2 => counter(1),
      I3 => counter(2),
      I4 => counter(3),
      O => \counter[3]_i_1_n_0\
    );
\counter[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => state_reg_n_0,
      I1 => counter(0),
      I2 => counter(1),
      I3 => counter(2),
      I4 => counter(3),
      I5 => counter(4),
      O => \counter[4]_i_1_n_0\
    );
\counter[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAA80000000"
    )
        port map (
      I0 => state_reg_n_0,
      I1 => counter(3),
      I2 => counter(2),
      I3 => \counter[5]_i_2_n_0\,
      I4 => counter(4),
      I5 => counter(5),
      O => \counter[5]_i_1_n_0\
    );
\counter[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => counter(1),
      I1 => counter(0),
      O => \counter[5]_i_2_n_0\
    );
\counter_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      CLR => state_reg_0,
      D => \counter[0]_i_1_n_0\,
      Q => counter(0)
    );
\counter_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      CLR => state_reg_0,
      D => \counter[1]_i_1_n_0\,
      Q => counter(1)
    );
\counter_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      CLR => state_reg_0,
      D => \counter[2]_i_1_n_0\,
      Q => counter(2)
    );
\counter_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      CLR => state_reg_0,
      D => \counter[3]_i_1_n_0\,
      Q => counter(3)
    );
\counter_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      CLR => state_reg_0,
      D => \counter[4]_i_1_n_0\,
      Q => counter(4)
    );
\counter_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      CLR => state_reg_0,
      D => \counter[5]_i_1_n_0\,
      Q => counter(5)
    );
eth_mdio_INST_0: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => mdio_prime_reg_n_0,
      I1 => eth_mdio_INST_0_i_1_n_0,
      O => eth_mdio
    );
eth_mdio_INST_0_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => mdio_prime_reg_n_0,
      O => eth_mdio_INST_0_i_1_n_0
    );
mdio_prime_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEA002A"
    )
        port map (
      I0 => mdio_prime_i_2_n_0,
      I1 => counter(4),
      I2 => counter(5),
      I3 => mdio_prime_i_3_n_0,
      I4 => mdio_prime_reg_n_0,
      O => mdio_prime_i_1_n_0
    );
mdio_prime_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44454504FFFFFFFF"
    )
        port map (
      I0 => counter(4),
      I1 => counter(3),
      I2 => counter(2),
      I3 => counter(1),
      I4 => counter(0),
      I5 => counter(5),
      O => mdio_prime_i_2_n_0
    );
mdio_prime_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rstn,
      I1 => state_reg_n_0,
      O => mdio_prime_i_3_n_0
    );
mdio_prime_reg: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => mdio_prime_i_1_n_0,
      Q => mdio_prime_reg_n_0,
      R => '0'
    );
\reg_data[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[0]_i_2_n_0\,
      I1 => \^led\(0),
      I2 => eth_mdio,
      O => \reg_data[0]_i_1_n_0\
    );
\reg_data[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008000000"
    )
        port map (
      I0 => counter(2),
      I1 => counter(3),
      I2 => state_i_2_n_0,
      I3 => counter(1),
      I4 => counter(0),
      I5 => \reg_data[12]_i_3_n_0\,
      O => \reg_data[0]_i_2_n_0\
    );
\reg_data[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[10]_i_2_n_0\,
      I1 => \^led\(10),
      I2 => eth_mdio,
      O => \reg_data[10]_i_1_n_0\
    );
\reg_data[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08000000"
    )
        port map (
      I0 => \reg_data[14]_i_3_n_0\,
      I1 => counter(2),
      I2 => counter(3),
      I3 => counter(4),
      I4 => counter(5),
      O => \reg_data[10]_i_2_n_0\
    );
\reg_data[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[11]_i_2_n_0\,
      I1 => \^led\(11),
      I2 => eth_mdio,
      O => \reg_data[11]_i_1_n_0\
    );
\reg_data[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08000000"
    )
        port map (
      I0 => \reg_data[15]_i_3_n_0\,
      I1 => counter(2),
      I2 => counter(3),
      I3 => counter(4),
      I4 => counter(5),
      O => \reg_data[11]_i_2_n_0\
    );
\reg_data[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[12]_i_2_n_0\,
      I1 => \^led\(12),
      I2 => eth_mdio,
      O => \reg_data[12]_i_1_n_0\
    );
\reg_data[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => counter(3),
      I1 => state_i_2_n_0,
      I2 => counter(2),
      I3 => \reg_data[12]_i_3_n_0\,
      I4 => counter(1),
      I5 => counter(0),
      O => \reg_data[12]_i_2_n_0\
    );
\reg_data[12]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55555557"
    )
        port map (
      I0 => counter(5),
      I1 => counter(3),
      I2 => counter(4),
      I3 => counter(1),
      I4 => counter(2),
      I5 => mdio_prime_i_3_n_0,
      O => \reg_data[12]_i_3_n_0\
    );
\reg_data[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[13]_i_2_n_0\,
      I1 => \^led\(13),
      I2 => eth_mdio,
      O => \reg_data[13]_i_1_n_0\
    );
\reg_data[13]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00400000"
    )
        port map (
      I0 => counter(3),
      I1 => counter(4),
      I2 => counter(5),
      I3 => counter(2),
      I4 => \reg_data[13]_i_3_n_0\,
      O => \reg_data[13]_i_2_n_0\
    );
\reg_data[13]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => counter(1),
      I1 => counter(0),
      I2 => \reg_data[12]_i_3_n_0\,
      O => \reg_data[13]_i_3_n_0\
    );
\reg_data[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[14]_i_2_n_0\,
      I1 => \^led\(14),
      I2 => eth_mdio,
      O => \reg_data[14]_i_1_n_0\
    );
\reg_data[14]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00400000"
    )
        port map (
      I0 => counter(3),
      I1 => counter(4),
      I2 => counter(5),
      I3 => counter(2),
      I4 => \reg_data[14]_i_3_n_0\,
      O => \reg_data[14]_i_2_n_0\
    );
\reg_data[14]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => counter(0),
      I1 => counter(1),
      I2 => \reg_data[12]_i_3_n_0\,
      O => \reg_data[14]_i_3_n_0\
    );
\reg_data[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[15]_i_2_n_0\,
      I1 => \^led\(15),
      I2 => eth_mdio,
      O => \reg_data[15]_i_1_n_0\
    );
\reg_data[15]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00400000"
    )
        port map (
      I0 => counter(3),
      I1 => counter(4),
      I2 => counter(5),
      I3 => counter(2),
      I4 => \reg_data[15]_i_3_n_0\,
      O => \reg_data[15]_i_2_n_0\
    );
\reg_data[15]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => counter(0),
      I1 => counter(1),
      I2 => \reg_data[12]_i_3_n_0\,
      O => \reg_data[15]_i_3_n_0\
    );
\reg_data[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[1]_i_2_n_0\,
      I1 => \^led\(1),
      I2 => eth_mdio,
      O => \reg_data[1]_i_1_n_0\
    );
\reg_data[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \reg_data[12]_i_3_n_0\,
      I1 => state_i_2_n_0,
      I2 => counter(3),
      I3 => counter(2),
      I4 => counter(1),
      I5 => counter(0),
      O => \reg_data[1]_i_2_n_0\
    );
\reg_data[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[2]_i_2_n_0\,
      I1 => \^led\(2),
      I2 => eth_mdio,
      O => \reg_data[2]_i_1_n_0\
    );
\reg_data[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000100000000000"
    )
        port map (
      I0 => \reg_data[12]_i_3_n_0\,
      I1 => state_i_2_n_0,
      I2 => counter(3),
      I3 => counter(2),
      I4 => counter(1),
      I5 => counter(0),
      O => \reg_data[2]_i_2_n_0\
    );
\reg_data[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[3]_i_2_n_0\,
      I1 => \^led\(3),
      I2 => eth_mdio,
      O => \reg_data[3]_i_1_n_0\
    );
\reg_data[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => \reg_data[12]_i_3_n_0\,
      I1 => state_i_2_n_0,
      I2 => counter(3),
      I3 => counter(2),
      I4 => counter(1),
      I5 => counter(0),
      O => \reg_data[3]_i_2_n_0\
    );
\reg_data[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[4]_i_2_n_0\,
      I1 => \^led\(4),
      I2 => eth_mdio,
      O => \reg_data[4]_i_1_n_0\
    );
\reg_data[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \reg_data[12]_i_3_n_0\,
      I1 => counter(1),
      I2 => counter(0),
      I3 => state_i_2_n_0,
      I4 => counter(3),
      I5 => counter(2),
      O => \reg_data[4]_i_2_n_0\
    );
\reg_data[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[5]_i_2_n_0\,
      I1 => \^led\(5),
      I2 => eth_mdio,
      O => \reg_data[5]_i_1_n_0\
    );
\reg_data[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \reg_data[13]_i_3_n_0\,
      I1 => counter(4),
      I2 => counter(5),
      I3 => counter(3),
      I4 => counter(2),
      O => \reg_data[5]_i_2_n_0\
    );
\reg_data[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[6]_i_2_n_0\,
      I1 => \^led\(6),
      I2 => eth_mdio,
      O => \reg_data[6]_i_1_n_0\
    );
\reg_data[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \reg_data[14]_i_3_n_0\,
      I1 => counter(4),
      I2 => counter(5),
      I3 => counter(3),
      I4 => counter(2),
      O => \reg_data[6]_i_2_n_0\
    );
\reg_data[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[7]_i_2_n_0\,
      I1 => \^led\(7),
      I2 => eth_mdio,
      O => \reg_data[7]_i_1_n_0\
    );
\reg_data[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00008000"
    )
        port map (
      I0 => \reg_data[15]_i_3_n_0\,
      I1 => counter(4),
      I2 => counter(5),
      I3 => counter(3),
      I4 => counter(2),
      O => \reg_data[7]_i_2_n_0\
    );
\reg_data[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[8]_i_2_n_0\,
      I1 => \^led\(8),
      I2 => eth_mdio,
      O => \reg_data[8]_i_1_n_0\
    );
\reg_data[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000004000"
    )
        port map (
      I0 => \reg_data[12]_i_3_n_0\,
      I1 => counter(1),
      I2 => counter(0),
      I3 => counter(2),
      I4 => counter(3),
      I5 => state_i_2_n_0,
      O => \reg_data[8]_i_2_n_0\
    );
\reg_data[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => \reg_data[9]_i_2_n_0\,
      I1 => \^led\(9),
      I2 => eth_mdio,
      O => \reg_data[9]_i_1_n_0\
    );
\reg_data[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08000000"
    )
        port map (
      I0 => \reg_data[13]_i_3_n_0\,
      I1 => counter(2),
      I2 => counter(3),
      I3 => counter(4),
      I4 => counter(5),
      O => \reg_data[9]_i_2_n_0\
    );
\reg_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[0]_i_1_n_0\,
      Q => \^led\(0),
      R => '0'
    );
\reg_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[10]_i_1_n_0\,
      Q => \^led\(10),
      R => '0'
    );
\reg_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[11]_i_1_n_0\,
      Q => \^led\(11),
      R => '0'
    );
\reg_data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[12]_i_1_n_0\,
      Q => \^led\(12),
      R => '0'
    );
\reg_data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[13]_i_1_n_0\,
      Q => \^led\(13),
      R => '0'
    );
\reg_data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[14]_i_1_n_0\,
      Q => \^led\(14),
      R => '0'
    );
\reg_data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[15]_i_1_n_0\,
      Q => \^led\(15),
      R => '0'
    );
\reg_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[1]_i_1_n_0\,
      Q => \^led\(1),
      R => '0'
    );
\reg_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[2]_i_1_n_0\,
      Q => \^led\(2),
      R => '0'
    );
\reg_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[3]_i_1_n_0\,
      Q => \^led\(3),
      R => '0'
    );
\reg_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[4]_i_1_n_0\,
      Q => \^led\(4),
      R => '0'
    );
\reg_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[5]_i_1_n_0\,
      Q => \^led\(5),
      R => '0'
    );
\reg_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[6]_i_1_n_0\,
      Q => \^led\(6),
      R => '0'
    );
\reg_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[7]_i_1_n_0\,
      Q => \^led\(7),
      R => '0'
    );
\reg_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[8]_i_1_n_0\,
      Q => \^led\(8),
      R => '0'
    );
\reg_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      D => \reg_data[9]_i_1_n_0\,
      Q => \^led\(9),
      R => '0'
    );
state_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7FFFFFFFFFFFFF"
    )
        port map (
      I0 => state_reg_n_0,
      I1 => counter(2),
      I2 => counter(3),
      I3 => state_i_2_n_0,
      I4 => counter(1),
      I5 => counter(0),
      O => state_i_1_n_0
    );
state_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => counter(5),
      I1 => counter(4),
      O => state_i_2_n_0
    );
state_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk2_5mhz_shift,
      CE => '1',
      CLR => state_reg_0,
      D => state_i_1_n_0,
      Q => state_reg_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_ethernet_transceiver2_0_0_eth_receiver is
  port (
    send_arp_reply : out STD_LOGIC;
    udp_packet_recieved : out STD_LOGIC;
    udp_send_data_valid : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
    send_arp_reply_reg_0 : out STD_LOGIC;
    we_ram_reg_0 : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \data_to_ram_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \pc_mac_reg[47]_0\ : out STD_LOGIC_VECTOR ( 47 downto 0 );
    \pc_port_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \addr_count_reg[1]_0\ : in STD_LOGIC;
    ip : in STD_LOGIC_VECTOR ( 4 downto 0 );
    eth_crsdv : in STD_LOGIC;
    eth_rxerr : in STD_LOGIC;
    eth_rstn : in STD_LOGIC;
    eth_rxd : in STD_LOGIC_VECTOR ( 1 downto 0 );
    udp_send_data_valid17_out : in STD_LOGIC;
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    sent_arp_response : in STD_LOGIC;
    arp_response_pending : in STD_LOGIC;
    fifo_write_enable : in STD_LOGIC;
    \state_reg[3]_0\ : in STD_LOGIC;
    \crc_rx_reg[30]_0\ : in STD_LOGIC;
    \crc_rx_reg[30]_1\ : in STD_LOGIC;
    b_clk100mhz : in STD_LOGIC
  );
end design_1_ethernet_transceiver2_0_0_eth_receiver;

architecture STRUCTURE of design_1_ethernet_transceiver2_0_0_eth_receiver is
  signal \FSM_onehot_sip[2]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_sudp[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_sudp[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_sudp[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_s_ram[1]_i_1_n_0\ : STD_LOGIC;
  signal L : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal RSTA : STD_LOGIC;
  signal RSTP : STD_LOGIC;
  signal addr_count : STD_LOGIC;
  signal \addr_count[0]_i_1_n_0\ : STD_LOGIC;
  signal \addr_count[1]_i_1_n_0\ : STD_LOGIC;
  signal arp_request_expected : STD_LOGIC;
  signal arp_request_expected2 : STD_LOGIC;
  signal arp_request_expected_i_1_n_0 : STD_LOGIC;
  signal arp_request_expected_i_2_n_0 : STD_LOGIC;
  signal bit_count2 : STD_LOGIC;
  signal \bit_count[0]_i_1_n_0\ : STD_LOGIC;
  signal \bit_count[0]_rep_i_1_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_10_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_11_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_12_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_13_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_14_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_15_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_1_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_2_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_3_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_4_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_5_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_6_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_7_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_8_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_9_n_0\ : STD_LOGIC;
  signal \bit_count[1]_rep_i_1_n_0\ : STD_LOGIC;
  signal \bit_count_reg[0]_rep_n_0\ : STD_LOGIC;
  signal \bit_count_reg[1]_rep_n_0\ : STD_LOGIC;
  signal byte_count0 : STD_LOGIC;
  signal \byte_count[0]_i_1_n_0\ : STD_LOGIC;
  signal \byte_count[0]_i_2_n_0\ : STD_LOGIC;
  signal \byte_count[0]_i_3_n_0\ : STD_LOGIC;
  signal \byte_count[0]_rep_i_1__0_n_0\ : STD_LOGIC;
  signal \byte_count[0]_rep_i_1__1_n_0\ : STD_LOGIC;
  signal \byte_count[0]_rep_i_1_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_10_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_11_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_12__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_13_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_14_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_15_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_16_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_17_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_18_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_19_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_1_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_20_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_21_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_3_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_4_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_5_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_6_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_7_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_8_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_9_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_10_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_11_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_12_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_13_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_14_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_15_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_16_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_17_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_18_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_19_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_20_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_21_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_22_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_23_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_24_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_25_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_2_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_3_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_4_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_5_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_7_n_0\ : STD_LOGIC;
  signal \byte_count[1]_i_8_n_0\ : STD_LOGIC;
  signal \byte_count[1]_rep_i_1_n_0\ : STD_LOGIC;
  signal \byte_count[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte_count[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte_count[4]_i_1_n_0\ : STD_LOGIC;
  signal \byte_count[5]_i_1_n_0\ : STD_LOGIC;
  signal \byte_count[6]_i_1_n_0\ : STD_LOGIC;
  signal \byte_count[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \byte_count[8]_i_1_n_0\ : STD_LOGIC;
  signal \byte_count[9]_i_1_n_0\ : STD_LOGIC;
  signal byte_count_extra0 : STD_LOGIC;
  signal \byte_count_extra[0]_i_1_n_0\ : STD_LOGIC;
  signal \byte_count_extra[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte_count_extra[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte_count_extra[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte_count_extra[4]_i_1_n_0\ : STD_LOGIC;
  signal \byte_count_extra[4]_i_2_n_0\ : STD_LOGIC;
  signal \byte_count_extra[5]_i_10_n_0\ : STD_LOGIC;
  signal \byte_count_extra[5]_i_11_n_0\ : STD_LOGIC;
  signal \byte_count_extra[5]_i_12_n_0\ : STD_LOGIC;
  signal \byte_count_extra[5]_i_13_n_0\ : STD_LOGIC;
  signal \byte_count_extra[5]_i_14_n_0\ : STD_LOGIC;
  signal \byte_count_extra[5]_i_15_n_0\ : STD_LOGIC;
  signal \byte_count_extra[5]_i_2_n_0\ : STD_LOGIC;
  signal \byte_count_extra[5]_i_3_n_0\ : STD_LOGIC;
  signal \byte_count_extra[5]_i_5_n_0\ : STD_LOGIC;
  signal \byte_count_extra[5]_i_6_n_0\ : STD_LOGIC;
  signal \byte_count_extra[5]_i_7_n_0\ : STD_LOGIC;
  signal \byte_count_extra[5]_i_8_n_0\ : STD_LOGIC;
  signal \byte_count_extra[5]_i_9_n_0\ : STD_LOGIC;
  signal \byte_count_extra_reg[5]_i_4_n_0\ : STD_LOGIC;
  signal \byte_count_extra_reg[5]_i_4_n_1\ : STD_LOGIC;
  signal \byte_count_extra_reg[5]_i_4_n_2\ : STD_LOGIC;
  signal \byte_count_extra_reg[5]_i_4_n_3\ : STD_LOGIC;
  signal \byte_count_extra_reg_n_0_[0]\ : STD_LOGIC;
  signal \byte_count_extra_reg_n_0_[1]\ : STD_LOGIC;
  signal \byte_count_extra_reg_n_0_[2]\ : STD_LOGIC;
  signal \byte_count_extra_reg_n_0_[3]\ : STD_LOGIC;
  signal \byte_count_extra_reg_n_0_[4]\ : STD_LOGIC;
  signal \byte_count_extra_reg_n_0_[5]\ : STD_LOGIC;
  signal \byte_count_reg[0]_rep__0_n_0\ : STD_LOGIC;
  signal \byte_count_reg[0]_rep__1_n_0\ : STD_LOGIC;
  signal \byte_count_reg[0]_rep_n_0\ : STD_LOGIC;
  signal \byte_count_reg[1]_i_6_n_3\ : STD_LOGIC;
  signal \byte_count_reg[1]_i_9_n_0\ : STD_LOGIC;
  signal \byte_count_reg[1]_i_9_n_1\ : STD_LOGIC;
  signal \byte_count_reg[1]_i_9_n_2\ : STD_LOGIC;
  signal \byte_count_reg[1]_i_9_n_3\ : STD_LOGIC;
  signal \byte_count_reg[1]_rep_n_0\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[0]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[10]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[1]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[2]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[3]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[4]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[5]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[6]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[7]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[8]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[9]\ : STD_LOGIC;
  signal \byte_read_done[0]_i_1_n_0\ : STD_LOGIC;
  signal \byte_read_done[0]_i_2_n_0\ : STD_LOGIC;
  signal \byte_read_done[0]_i_3_n_0\ : STD_LOGIC;
  signal \byte_read_done[0]_i_4_n_0\ : STD_LOGIC;
  signal \byte_read_done[10]_i_1_n_0\ : STD_LOGIC;
  signal \byte_read_done[10]_i_2_n_0\ : STD_LOGIC;
  signal \byte_read_done[10]_i_3_n_0\ : STD_LOGIC;
  signal \byte_read_done[10]_i_4_n_0\ : STD_LOGIC;
  signal \byte_read_done[10]_i_5_n_0\ : STD_LOGIC;
  signal \byte_read_done[11]_i_1_n_0\ : STD_LOGIC;
  signal \byte_read_done[11]_i_2_n_0\ : STD_LOGIC;
  signal \byte_read_done[11]_i_3_n_0\ : STD_LOGIC;
  signal \byte_read_done[11]_i_4_n_0\ : STD_LOGIC;
  signal \byte_read_done[11]_i_5_n_0\ : STD_LOGIC;
  signal \byte_read_done[11]_i_6_n_0\ : STD_LOGIC;
  signal \byte_read_done[12]_i_1_n_0\ : STD_LOGIC;
  signal \byte_read_done[12]_i_2_n_0\ : STD_LOGIC;
  signal \byte_read_done[12]_i_3_n_0\ : STD_LOGIC;
  signal \byte_read_done[12]_i_4_n_0\ : STD_LOGIC;
  signal \byte_read_done[12]_i_5_n_0\ : STD_LOGIC;
  signal \byte_read_done[12]_i_6_n_0\ : STD_LOGIC;
  signal \byte_read_done[13]_i_1_n_0\ : STD_LOGIC;
  signal \byte_read_done[13]_i_2_n_0\ : STD_LOGIC;
  signal \byte_read_done[13]_i_3_n_0\ : STD_LOGIC;
  signal \byte_read_done[13]_i_4_n_0\ : STD_LOGIC;
  signal \byte_read_done[13]_i_5_n_0\ : STD_LOGIC;
  signal \byte_read_done[13]_i_6_n_0\ : STD_LOGIC;
  signal \byte_read_done[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte_read_done[1]_i_2_n_0\ : STD_LOGIC;
  signal \byte_read_done[1]_i_3_n_0\ : STD_LOGIC;
  signal \byte_read_done[1]_i_4_n_0\ : STD_LOGIC;
  signal \byte_read_done[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte_read_done[2]_i_2_n_0\ : STD_LOGIC;
  signal \byte_read_done[2]_i_3_n_0\ : STD_LOGIC;
  signal \byte_read_done[2]_i_4_n_0\ : STD_LOGIC;
  signal \byte_read_done[3]_i_10_n_0\ : STD_LOGIC;
  signal \byte_read_done[3]_i_11_n_0\ : STD_LOGIC;
  signal \byte_read_done[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte_read_done[3]_i_2_n_0\ : STD_LOGIC;
  signal \byte_read_done[3]_i_3_n_0\ : STD_LOGIC;
  signal \byte_read_done[3]_i_4_n_0\ : STD_LOGIC;
  signal \byte_read_done[3]_i_5_n_0\ : STD_LOGIC;
  signal \byte_read_done[3]_i_6_n_0\ : STD_LOGIC;
  signal \byte_read_done[3]_i_7_n_0\ : STD_LOGIC;
  signal \byte_read_done[3]_i_8_n_0\ : STD_LOGIC;
  signal \byte_read_done[3]_i_9_n_0\ : STD_LOGIC;
  signal \byte_read_done[5]_i_1_n_0\ : STD_LOGIC;
  signal \byte_read_done[5]_i_2_n_0\ : STD_LOGIC;
  signal \byte_read_done[5]_i_3_n_0\ : STD_LOGIC;
  signal \byte_read_done[5]_i_4_n_0\ : STD_LOGIC;
  signal \byte_read_done[6]_i_1_n_0\ : STD_LOGIC;
  signal \byte_read_done[6]_i_2_n_0\ : STD_LOGIC;
  signal \byte_read_done[6]_i_3_n_0\ : STD_LOGIC;
  signal \byte_read_done[6]_i_4_n_0\ : STD_LOGIC;
  signal \byte_read_done[6]_i_5_n_0\ : STD_LOGIC;
  signal \byte_read_done[6]_i_6_n_0\ : STD_LOGIC;
  signal \byte_read_done[7]_i_1_n_0\ : STD_LOGIC;
  signal \byte_read_done[7]_i_2_n_0\ : STD_LOGIC;
  signal \byte_read_done[7]_i_3_n_0\ : STD_LOGIC;
  signal \byte_read_done[7]_i_4_n_0\ : STD_LOGIC;
  signal \byte_read_done[8]_i_1_n_0\ : STD_LOGIC;
  signal \byte_read_done[8]_i_2_n_0\ : STD_LOGIC;
  signal \byte_read_done[8]_i_3_n_0\ : STD_LOGIC;
  signal \byte_read_done[8]_i_4_n_0\ : STD_LOGIC;
  signal \byte_read_done[9]_i_1_n_0\ : STD_LOGIC;
  signal \byte_read_done[9]_i_2_n_0\ : STD_LOGIC;
  signal \byte_read_done[9]_i_3_n_0\ : STD_LOGIC;
  signal \byte_read_done[9]_i_4_n_0\ : STD_LOGIC;
  signal \byte_read_done_reg_n_0_[0]\ : STD_LOGIC;
  signal \byte_read_done_reg_n_0_[10]\ : STD_LOGIC;
  signal \byte_read_done_reg_n_0_[11]\ : STD_LOGIC;
  signal \byte_read_done_reg_n_0_[1]\ : STD_LOGIC;
  signal \byte_read_done_reg_n_0_[2]\ : STD_LOGIC;
  signal \byte_read_done_reg_n_0_[5]\ : STD_LOGIC;
  signal \byte_read_done_reg_n_0_[6]\ : STD_LOGIC;
  signal \byte_read_done_reg_n_0_[8]\ : STD_LOGIC;
  signal \byte_read_done_reg_n_0_[9]\ : STD_LOGIC;
  signal \bytes00[0]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[10]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[10]_i_2_n_0\ : STD_LOGIC;
  signal \bytes00[11]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[11]_i_2_n_0\ : STD_LOGIC;
  signal \bytes00[11]_i_3_n_0\ : STD_LOGIC;
  signal \bytes00[12]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[12]_i_2_n_0\ : STD_LOGIC;
  signal \bytes00[13]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[13]_i_2_n_0\ : STD_LOGIC;
  signal \bytes00[13]_i_3_n_0\ : STD_LOGIC;
  signal \bytes00[14]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[14]_i_2_n_0\ : STD_LOGIC;
  signal \bytes00[15]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[15]_i_2_n_0\ : STD_LOGIC;
  signal \bytes00[15]_i_3_n_0\ : STD_LOGIC;
  signal \bytes00[15]_i_4_n_0\ : STD_LOGIC;
  signal \bytes00[15]_i_5_n_0\ : STD_LOGIC;
  signal \bytes00[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytes00[2]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[3]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[3]_i_2_n_0\ : STD_LOGIC;
  signal \bytes00[4]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[5]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[5]_i_2_n_0\ : STD_LOGIC;
  signal \bytes00[6]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[7]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[7]_i_2_n_0\ : STD_LOGIC;
  signal \bytes00[7]_i_3_n_0\ : STD_LOGIC;
  signal \bytes00[7]_i_4_n_0\ : STD_LOGIC;
  signal \bytes00[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[8]_i_2_n_0\ : STD_LOGIC;
  signal \bytes00[9]_i_1_n_0\ : STD_LOGIC;
  signal \bytes00[9]_i_2_n_0\ : STD_LOGIC;
  signal \bytes00[9]_i_3_n_0\ : STD_LOGIC;
  signal \bytes00_reg_n_0_[0]\ : STD_LOGIC;
  signal \bytes00_reg_n_0_[12]\ : STD_LOGIC;
  signal \bytes00_reg_n_0_[13]\ : STD_LOGIC;
  signal \bytes00_reg_n_0_[14]\ : STD_LOGIC;
  signal \bytes00_reg_n_0_[15]\ : STD_LOGIC;
  signal \bytes00_reg_n_0_[1]\ : STD_LOGIC;
  signal \bytes00_reg_n_0_[2]\ : STD_LOGIC;
  signal \bytes00_reg_n_0_[3]\ : STD_LOGIC;
  signal \bytes00_reg_n_0_[4]\ : STD_LOGIC;
  signal \bytes00_reg_n_0_[5]\ : STD_LOGIC;
  signal \bytes00_reg_n_0_[6]\ : STD_LOGIC;
  signal \bytes00_reg_n_0_[7]\ : STD_LOGIC;
  signal bytes01 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \bytes01[0]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[10]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[10]_i_2_n_0\ : STD_LOGIC;
  signal \bytes01[11]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[11]_i_2_n_0\ : STD_LOGIC;
  signal \bytes01[11]_i_3_n_0\ : STD_LOGIC;
  signal \bytes01[12]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[12]_i_2_n_0\ : STD_LOGIC;
  signal \bytes01[13]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[13]_i_2_n_0\ : STD_LOGIC;
  signal \bytes01[13]_i_3_n_0\ : STD_LOGIC;
  signal \bytes01[14]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[14]_i_2_n_0\ : STD_LOGIC;
  signal \bytes01[15]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[15]_i_2_n_0\ : STD_LOGIC;
  signal \bytes01[15]_i_3_n_0\ : STD_LOGIC;
  signal \bytes01[15]_i_4_n_0\ : STD_LOGIC;
  signal \bytes01[15]_i_5_n_0\ : STD_LOGIC;
  signal \bytes01[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytes01[2]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[3]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[3]_i_2_n_0\ : STD_LOGIC;
  signal \bytes01[4]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[5]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[5]_i_2_n_0\ : STD_LOGIC;
  signal \bytes01[6]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[7]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[7]_i_2_n_0\ : STD_LOGIC;
  signal \bytes01[7]_i_3_n_0\ : STD_LOGIC;
  signal \bytes01[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[8]_i_2_n_0\ : STD_LOGIC;
  signal \bytes01[9]_i_1_n_0\ : STD_LOGIC;
  signal \bytes01[9]_i_2_n_0\ : STD_LOGIC;
  signal \bytes01[9]_i_3_n_0\ : STD_LOGIC;
  signal bytes02 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \bytes02[0]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[10]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[11]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[11]_i_2_n_0\ : STD_LOGIC;
  signal \bytes02[12]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[13]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[13]_i_2_n_0\ : STD_LOGIC;
  signal \bytes02[13]_i_3_n_0\ : STD_LOGIC;
  signal \bytes02[14]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[15]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[15]_i_2_n_0\ : STD_LOGIC;
  signal \bytes02[15]_i_3_n_0\ : STD_LOGIC;
  signal \bytes02[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytes02[2]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[3]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[3]_i_2_n_0\ : STD_LOGIC;
  signal \bytes02[4]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[5]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[5]_i_2_n_0\ : STD_LOGIC;
  signal \bytes02[6]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[7]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[7]_i_2_n_0\ : STD_LOGIC;
  signal \bytes02[7]_i_3_n_0\ : STD_LOGIC;
  signal \bytes02[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[9]_i_1_n_0\ : STD_LOGIC;
  signal \bytes02[9]_i_2_n_0\ : STD_LOGIC;
  signal bytes03 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \bytes03[0]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[10]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[10]_i_2_n_0\ : STD_LOGIC;
  signal \bytes03[11]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[11]_i_2_n_0\ : STD_LOGIC;
  signal \bytes03[11]_i_3_n_0\ : STD_LOGIC;
  signal \bytes03[12]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[12]_i_2_n_0\ : STD_LOGIC;
  signal \bytes03[13]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[13]_i_2_n_0\ : STD_LOGIC;
  signal \bytes03[13]_i_3_n_0\ : STD_LOGIC;
  signal \bytes03[13]_i_4_n_0\ : STD_LOGIC;
  signal \bytes03[13]_i_5_n_0\ : STD_LOGIC;
  signal \bytes03[14]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[14]_i_2_n_0\ : STD_LOGIC;
  signal \bytes03[15]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[15]_i_2_n_0\ : STD_LOGIC;
  signal \bytes03[15]_i_3_n_0\ : STD_LOGIC;
  signal \bytes03[15]_i_4_n_0\ : STD_LOGIC;
  signal \bytes03[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytes03[2]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[3]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[3]_i_2_n_0\ : STD_LOGIC;
  signal \bytes03[4]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[5]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[5]_i_2_n_0\ : STD_LOGIC;
  signal \bytes03[6]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[7]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[7]_i_2_n_0\ : STD_LOGIC;
  signal \bytes03[7]_i_3_n_0\ : STD_LOGIC;
  signal \bytes03[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[8]_i_2_n_0\ : STD_LOGIC;
  signal \bytes03[9]_i_1_n_0\ : STD_LOGIC;
  signal \bytes03[9]_i_2_n_0\ : STD_LOGIC;
  signal \bytes03[9]_i_3_n_0\ : STD_LOGIC;
  signal bytes04 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \bytes04[0]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[10]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[10]_i_2_n_0\ : STD_LOGIC;
  signal \bytes04[11]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[11]_i_2_n_0\ : STD_LOGIC;
  signal \bytes04[11]_i_3_n_0\ : STD_LOGIC;
  signal \bytes04[12]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[12]_i_2_n_0\ : STD_LOGIC;
  signal \bytes04[13]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[13]_i_2_n_0\ : STD_LOGIC;
  signal \bytes04[13]_i_3_n_0\ : STD_LOGIC;
  signal \bytes04[14]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[14]_i_2_n_0\ : STD_LOGIC;
  signal \bytes04[15]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[15]_i_2_n_0\ : STD_LOGIC;
  signal \bytes04[15]_i_3_n_0\ : STD_LOGIC;
  signal \bytes04[15]_i_4_n_0\ : STD_LOGIC;
  signal \bytes04[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytes04[2]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[3]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[3]_i_2_n_0\ : STD_LOGIC;
  signal \bytes04[4]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[5]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[5]_i_2_n_0\ : STD_LOGIC;
  signal \bytes04[6]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[7]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[7]_i_2_n_0\ : STD_LOGIC;
  signal \bytes04[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[8]_i_2_n_0\ : STD_LOGIC;
  signal \bytes04[9]_i_1_n_0\ : STD_LOGIC;
  signal \bytes04[9]_i_2_n_0\ : STD_LOGIC;
  signal \bytes04[9]_i_3_n_0\ : STD_LOGIC;
  signal bytes05 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \bytes05[0]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[10]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[11]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[11]_i_2_n_0\ : STD_LOGIC;
  signal \bytes05[11]_i_3_n_0\ : STD_LOGIC;
  signal \bytes05[12]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[13]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[13]_i_2_n_0\ : STD_LOGIC;
  signal \bytes05[13]_i_3_n_0\ : STD_LOGIC;
  signal \bytes05[14]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[15]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[15]_i_2_n_0\ : STD_LOGIC;
  signal \bytes05[15]_i_3_n_0\ : STD_LOGIC;
  signal \bytes05[15]_i_4_n_0\ : STD_LOGIC;
  signal \bytes05[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytes05[2]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[3]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[3]_i_2_n_0\ : STD_LOGIC;
  signal \bytes05[4]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[5]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[5]_i_2_n_0\ : STD_LOGIC;
  signal \bytes05[6]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[7]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[7]_i_2_n_0\ : STD_LOGIC;
  signal \bytes05[7]_i_3_n_0\ : STD_LOGIC;
  signal \bytes05[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[9]_i_1_n_0\ : STD_LOGIC;
  signal \bytes05[9]_i_2_n_0\ : STD_LOGIC;
  signal \bytes05[9]_i_3_n_0\ : STD_LOGIC;
  signal bytes06 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \bytes06[0]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[10]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[11]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[11]_i_2_n_0\ : STD_LOGIC;
  signal \bytes06[12]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[13]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[13]_i_2_n_0\ : STD_LOGIC;
  signal \bytes06[13]_i_3_n_0\ : STD_LOGIC;
  signal \bytes06[13]_i_4_n_0\ : STD_LOGIC;
  signal \bytes06[13]_i_5_n_0\ : STD_LOGIC;
  signal \bytes06[14]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[15]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[15]_i_2_n_0\ : STD_LOGIC;
  signal \bytes06[15]_i_3_n_0\ : STD_LOGIC;
  signal \bytes06[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytes06[2]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[3]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[3]_i_2_n_0\ : STD_LOGIC;
  signal \bytes06[4]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[5]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[5]_i_2_n_0\ : STD_LOGIC;
  signal \bytes06[6]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[7]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[7]_i_2_n_0\ : STD_LOGIC;
  signal \bytes06[7]_i_3_n_0\ : STD_LOGIC;
  signal \bytes06[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[9]_i_1_n_0\ : STD_LOGIC;
  signal \bytes06[9]_i_2_n_0\ : STD_LOGIC;
  signal bytes07 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \bytes07[0]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[10]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[10]_i_2_n_0\ : STD_LOGIC;
  signal \bytes07[11]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[11]_i_2_n_0\ : STD_LOGIC;
  signal \bytes07[11]_i_3_n_0\ : STD_LOGIC;
  signal \bytes07[11]_i_4_n_0\ : STD_LOGIC;
  signal \bytes07[12]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[12]_i_2_n_0\ : STD_LOGIC;
  signal \bytes07[13]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[13]_i_2_n_0\ : STD_LOGIC;
  signal \bytes07[13]_i_3_n_0\ : STD_LOGIC;
  signal \bytes07[13]_i_4_n_0\ : STD_LOGIC;
  signal \bytes07[14]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[14]_i_2_n_0\ : STD_LOGIC;
  signal \bytes07[15]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[15]_i_2_n_0\ : STD_LOGIC;
  signal \bytes07[15]_i_3_n_0\ : STD_LOGIC;
  signal \bytes07[15]_i_4_n_0\ : STD_LOGIC;
  signal \bytes07[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytes07[2]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[3]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[3]_i_2_n_0\ : STD_LOGIC;
  signal \bytes07[4]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[5]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[5]_i_2_n_0\ : STD_LOGIC;
  signal \bytes07[5]_i_3_n_0\ : STD_LOGIC;
  signal \bytes07[6]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[7]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[7]_i_2_n_0\ : STD_LOGIC;
  signal \bytes07[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[8]_i_2_n_0\ : STD_LOGIC;
  signal \bytes07[9]_i_1_n_0\ : STD_LOGIC;
  signal \bytes07[9]_i_2_n_0\ : STD_LOGIC;
  signal \bytes07[9]_i_3_n_0\ : STD_LOGIC;
  signal \bytes07[9]_i_4_n_0\ : STD_LOGIC;
  signal bytes08 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \bytes08[0]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[10]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[10]_i_2_n_0\ : STD_LOGIC;
  signal \bytes08[11]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[11]_i_2_n_0\ : STD_LOGIC;
  signal \bytes08[11]_i_3_n_0\ : STD_LOGIC;
  signal \bytes08[11]_i_4_n_0\ : STD_LOGIC;
  signal \bytes08[12]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[12]_i_2_n_0\ : STD_LOGIC;
  signal \bytes08[13]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[13]_i_2_n_0\ : STD_LOGIC;
  signal \bytes08[13]_i_3_n_0\ : STD_LOGIC;
  signal \bytes08[13]_i_4_n_0\ : STD_LOGIC;
  signal \bytes08[14]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[14]_i_2_n_0\ : STD_LOGIC;
  signal \bytes08[15]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[15]_i_2_n_0\ : STD_LOGIC;
  signal \bytes08[15]_i_3_n_0\ : STD_LOGIC;
  signal \bytes08[15]_i_4_n_0\ : STD_LOGIC;
  signal \bytes08[15]_i_5_n_0\ : STD_LOGIC;
  signal \bytes08[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytes08[2]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[3]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[3]_i_2_n_0\ : STD_LOGIC;
  signal \bytes08[4]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[5]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[5]_i_2_n_0\ : STD_LOGIC;
  signal \bytes08[6]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[7]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[7]_i_2_n_0\ : STD_LOGIC;
  signal \bytes08[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[8]_i_2_n_0\ : STD_LOGIC;
  signal \bytes08[9]_i_1_n_0\ : STD_LOGIC;
  signal \bytes08[9]_i_2_n_0\ : STD_LOGIC;
  signal \bytes08[9]_i_3_n_0\ : STD_LOGIC;
  signal \bytes08[9]_i_4_n_0\ : STD_LOGIC;
  signal bytes09 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \bytes09[0]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[10]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[10]_i_2_n_0\ : STD_LOGIC;
  signal \bytes09[11]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[11]_i_2_n_0\ : STD_LOGIC;
  signal \bytes09[11]_i_3_n_0\ : STD_LOGIC;
  signal \bytes09[12]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[12]_i_2_n_0\ : STD_LOGIC;
  signal \bytes09[13]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[13]_i_2_n_0\ : STD_LOGIC;
  signal \bytes09[13]_i_3_n_0\ : STD_LOGIC;
  signal \bytes09[14]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[15]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[15]_i_2_n_0\ : STD_LOGIC;
  signal \bytes09[15]_i_3_n_0\ : STD_LOGIC;
  signal \bytes09[15]_i_4_n_0\ : STD_LOGIC;
  signal \bytes09[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytes09[2]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[3]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[3]_i_2_n_0\ : STD_LOGIC;
  signal \bytes09[4]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[5]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[5]_i_2_n_0\ : STD_LOGIC;
  signal \bytes09[6]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[7]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[7]_i_2_n_0\ : STD_LOGIC;
  signal \bytes09[7]_i_3_n_0\ : STD_LOGIC;
  signal \bytes09[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[8]_i_2_n_0\ : STD_LOGIC;
  signal \bytes09[9]_i_1_n_0\ : STD_LOGIC;
  signal \bytes09[9]_i_2_n_0\ : STD_LOGIC;
  signal \bytes09[9]_i_3_n_0\ : STD_LOGIC;
  signal bytes10 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \bytes10[0]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[10]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[11]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[11]_i_2_n_0\ : STD_LOGIC;
  signal \bytes10[11]_i_3_n_0\ : STD_LOGIC;
  signal \bytes10[12]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[13]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[13]_i_2_n_0\ : STD_LOGIC;
  signal \bytes10[13]_i_3_n_0\ : STD_LOGIC;
  signal \bytes10[13]_i_4_n_0\ : STD_LOGIC;
  signal \bytes10[14]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[14]_i_2_n_0\ : STD_LOGIC;
  signal \bytes10[15]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[15]_i_2_n_0\ : STD_LOGIC;
  signal \bytes10[15]_i_3_n_0\ : STD_LOGIC;
  signal \bytes10[15]_i_4_n_0\ : STD_LOGIC;
  signal \bytes10[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytes10[2]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[3]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[3]_i_2_n_0\ : STD_LOGIC;
  signal \bytes10[4]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[5]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[5]_i_2_n_0\ : STD_LOGIC;
  signal \bytes10[5]_i_3_n_0\ : STD_LOGIC;
  signal \bytes10[6]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[7]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[7]_i_2_n_0\ : STD_LOGIC;
  signal \bytes10[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[9]_i_1_n_0\ : STD_LOGIC;
  signal \bytes10[9]_i_2_n_0\ : STD_LOGIC;
  signal \bytes10[9]_i_3_n_0\ : STD_LOGIC;
  signal bytes11 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \bytes11[0]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[10]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[11]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[11]_i_2_n_0\ : STD_LOGIC;
  signal \bytes11[11]_i_3_n_0\ : STD_LOGIC;
  signal \bytes11[12]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[13]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[13]_i_2_n_0\ : STD_LOGIC;
  signal \bytes11[13]_i_3_n_0\ : STD_LOGIC;
  signal \bytes11[14]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[14]_i_2_n_0\ : STD_LOGIC;
  signal \bytes11[15]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[15]_i_2_n_0\ : STD_LOGIC;
  signal \bytes11[15]_i_3_n_0\ : STD_LOGIC;
  signal \bytes11[15]_i_4_n_0\ : STD_LOGIC;
  signal \bytes11[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytes11[1]_i_3_n_0\ : STD_LOGIC;
  signal \bytes11[2]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[3]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[3]_i_2_n_0\ : STD_LOGIC;
  signal \bytes11[3]_i_3_n_0\ : STD_LOGIC;
  signal \bytes11[4]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[5]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[5]_i_2_n_0\ : STD_LOGIC;
  signal \bytes11[5]_i_3_n_0\ : STD_LOGIC;
  signal \bytes11[6]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[7]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[7]_i_2_n_0\ : STD_LOGIC;
  signal \bytes11[7]_i_3_n_0\ : STD_LOGIC;
  signal \bytes11[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[9]_i_1_n_0\ : STD_LOGIC;
  signal \bytes11[9]_i_2_n_0\ : STD_LOGIC;
  signal \bytes11[9]_i_3_n_0\ : STD_LOGIC;
  signal bytes12 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \bytes12[0]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[10]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[10]_i_2_n_0\ : STD_LOGIC;
  signal \bytes12[11]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[11]_i_2_n_0\ : STD_LOGIC;
  signal \bytes12[11]_i_3_n_0\ : STD_LOGIC;
  signal \bytes12[12]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[12]_i_2_n_0\ : STD_LOGIC;
  signal \bytes12[13]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[13]_i_2_n_0\ : STD_LOGIC;
  signal \bytes12[13]_i_3_n_0\ : STD_LOGIC;
  signal \bytes12[13]_i_4_n_0\ : STD_LOGIC;
  signal \bytes12[14]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[15]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[15]_i_2_n_0\ : STD_LOGIC;
  signal \bytes12[15]_i_3_n_0\ : STD_LOGIC;
  signal \bytes12[15]_i_4_n_0\ : STD_LOGIC;
  signal \bytes12[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytes12[2]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[3]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[3]_i_2_n_0\ : STD_LOGIC;
  signal \bytes12[4]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[5]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[5]_i_2_n_0\ : STD_LOGIC;
  signal \bytes12[5]_i_3_n_0\ : STD_LOGIC;
  signal \bytes12[6]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[7]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[7]_i_2_n_0\ : STD_LOGIC;
  signal \bytes12[7]_i_3_n_0\ : STD_LOGIC;
  signal \bytes12[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[8]_i_2_n_0\ : STD_LOGIC;
  signal \bytes12[9]_i_1_n_0\ : STD_LOGIC;
  signal \bytes12[9]_i_2_n_0\ : STD_LOGIC;
  signal \bytes12[9]_i_3_n_0\ : STD_LOGIC;
  signal bytes13 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \bytes13[0]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[10]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[11]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[11]_i_2_n_0\ : STD_LOGIC;
  signal \bytes13[12]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[13]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[13]_i_2_n_0\ : STD_LOGIC;
  signal \bytes13[14]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[14]_i_2_n_0\ : STD_LOGIC;
  signal \bytes13[15]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[15]_i_2_n_0\ : STD_LOGIC;
  signal \bytes13[15]_i_3_n_0\ : STD_LOGIC;
  signal \bytes13[15]_i_4_n_0\ : STD_LOGIC;
  signal \bytes13[15]_i_5_n_0\ : STD_LOGIC;
  signal \bytes13[1]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[1]_i_2_n_0\ : STD_LOGIC;
  signal \bytes13[2]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[3]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[3]_i_2_n_0\ : STD_LOGIC;
  signal \bytes13[4]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[5]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[5]_i_2_n_0\ : STD_LOGIC;
  signal \bytes13[6]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[7]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[7]_i_2_n_0\ : STD_LOGIC;
  signal \bytes13[7]_i_3_n_0\ : STD_LOGIC;
  signal \bytes13[8]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[9]_i_1_n_0\ : STD_LOGIC;
  signal \bytes13[9]_i_2_n_0\ : STD_LOGIC;
  signal crc_checker_n_1 : STD_LOGIC;
  signal crc_pass0 : STD_LOGIC;
  signal crc_pass_i_1_n_0 : STD_LOGIC;
  signal crc_pass_i_2_n_0 : STD_LOGIC;
  signal crc_pass_reg_n_0 : STD_LOGIC;
  signal crc_rx : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \crc_rx[0]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[0]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[10]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[10]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[10]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[11]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[11]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[12]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[12]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[12]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[13]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[13]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[14]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[14]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[14]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[15]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[15]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[16]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[16]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[17]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[17]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[17]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[18]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[18]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[18]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[19]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[19]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[1]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[1]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[1]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[20]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[20]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[20]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[21]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[21]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[22]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[22]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[22]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[23]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[23]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[23]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[24]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[24]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[25]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[25]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[25]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[26]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[26]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[27]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[27]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[27]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[28]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[28]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[29]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[29]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[29]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[2]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[2]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[2]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[30]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[30]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[31]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[31]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[31]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[3]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[3]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[4]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[4]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[4]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[5]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[5]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[6]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[6]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[6]_i_3_n_0\ : STD_LOGIC;
  signal \crc_rx[7]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[7]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[8]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[8]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx[9]_i_1_n_0\ : STD_LOGIC;
  signal \crc_rx[9]_i_2_n_0\ : STD_LOGIC;
  signal data_counter_max : STD_LOGIC;
  signal data_counter_max0 : STD_LOGIC_VECTOR ( 10 downto 2 );
  signal data_counter_max2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \data_counter_max[10]_i_3_n_0\ : STD_LOGIC;
  signal \data_counter_max[5]_i_2_n_0\ : STD_LOGIC;
  signal \data_counter_max[5]_i_3_n_0\ : STD_LOGIC;
  signal \data_counter_max[5]_i_4_n_0\ : STD_LOGIC;
  signal \data_counter_max[5]_i_5_n_0\ : STD_LOGIC;
  signal \data_counter_max[5]_i_6_n_0\ : STD_LOGIC;
  signal \data_counter_max[5]_i_7_n_0\ : STD_LOGIC;
  signal \data_counter_max[5]_i_8_n_0\ : STD_LOGIC;
  signal \data_counter_max[9]_i_2_n_0\ : STD_LOGIC;
  signal \data_counter_max[9]_i_3_n_0\ : STD_LOGIC;
  signal \data_counter_max[9]_i_4_n_0\ : STD_LOGIC;
  signal \data_counter_max[9]_i_5_n_0\ : STD_LOGIC;
  signal \data_counter_max_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \data_counter_max_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \data_counter_max_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \data_counter_max_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \data_counter_max_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \data_counter_max_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \data_counter_max_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \data_counter_max_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[0]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[10]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[1]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[2]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[3]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[4]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[5]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[6]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[7]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[8]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[9]\ : STD_LOGIC;
  signal data_to_ram : STD_LOGIC;
  signal data_to_ram0 : STD_LOGIC;
  signal \data_to_ram[0]_i_1_n_0\ : STD_LOGIC;
  signal \data_to_ram[1]_i_1_n_0\ : STD_LOGIC;
  signal \data_to_ram[2]_i_1_n_0\ : STD_LOGIC;
  signal \data_to_ram[3]_i_1_n_0\ : STD_LOGIC;
  signal \data_to_ram[4]_i_1_n_0\ : STD_LOGIC;
  signal \data_to_ram[5]_i_1_n_0\ : STD_LOGIC;
  signal \data_to_ram[6]_i_1_n_0\ : STD_LOGIC;
  signal \data_to_ram[7]_i_3_n_0\ : STD_LOGIC;
  signal dest_mac : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal \dest_mac[0]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[10]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[11]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[11]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[12]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[12]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[12]_i_3_n_0\ : STD_LOGIC;
  signal \dest_mac[12]_i_4_n_0\ : STD_LOGIC;
  signal \dest_mac[13]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[13]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[14]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[15]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[15]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[15]_i_3_n_0\ : STD_LOGIC;
  signal \dest_mac[15]_i_4_n_0\ : STD_LOGIC;
  signal \dest_mac[16]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[17]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[17]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[18]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[19]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[19]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[1]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[1]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[20]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[21]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[21]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[22]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[23]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[23]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[23]_i_3_n_0\ : STD_LOGIC;
  signal \dest_mac[23]_i_4_n_0\ : STD_LOGIC;
  signal \dest_mac[24]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[25]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[25]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[26]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[27]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[27]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[28]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[29]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[29]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[2]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[30]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[31]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[31]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[31]_i_3_n_0\ : STD_LOGIC;
  signal \dest_mac[31]_i_4_n_0\ : STD_LOGIC;
  signal \dest_mac[31]_i_5_n_0\ : STD_LOGIC;
  signal \dest_mac[32]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[32]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[33]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[33]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[33]_i_3_n_0\ : STD_LOGIC;
  signal \dest_mac[34]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[34]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[35]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[35]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[35]_i_3_n_0\ : STD_LOGIC;
  signal \dest_mac[36]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[36]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[37]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[37]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[37]_i_3_n_0\ : STD_LOGIC;
  signal \dest_mac[38]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[38]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[39]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[39]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[39]_i_3_n_0\ : STD_LOGIC;
  signal \dest_mac[39]_i_4_n_0\ : STD_LOGIC;
  signal \dest_mac[3]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[3]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[40]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[40]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[41]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[41]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[41]_i_3_n_0\ : STD_LOGIC;
  signal \dest_mac[41]_i_4_n_0\ : STD_LOGIC;
  signal \dest_mac[42]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[42]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[43]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[43]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[43]_i_3_n_0\ : STD_LOGIC;
  signal \dest_mac[43]_i_4_n_0\ : STD_LOGIC;
  signal \dest_mac[44]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[44]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[45]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[45]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[45]_i_3_n_0\ : STD_LOGIC;
  signal \dest_mac[45]_i_4_n_0\ : STD_LOGIC;
  signal \dest_mac[46]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[46]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[47]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[47]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[47]_i_3_n_0\ : STD_LOGIC;
  signal \dest_mac[47]_i_4_n_0\ : STD_LOGIC;
  signal \dest_mac[47]_i_5_n_0\ : STD_LOGIC;
  signal \dest_mac[47]_i_6_n_0\ : STD_LOGIC;
  signal \dest_mac[47]_i_7_n_0\ : STD_LOGIC;
  signal \dest_mac[4]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[5]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[5]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[6]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[7]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[7]_i_2_n_0\ : STD_LOGIC;
  signal \dest_mac[8]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[9]_i_1_n_0\ : STD_LOGIC;
  signal \dest_mac[9]_i_2_n_0\ : STD_LOGIC;
  signal edge_count_data0 : STD_LOGIC;
  signal \edge_count_data__0\ : STD_LOGIC;
  signal edge_count_data_i_1_n_0 : STD_LOGIC;
  signal edge_count_header : STD_LOGIC;
  signal edge_count_header1 : STD_LOGIC;
  signal edge_count_header_i_1_n_0 : STD_LOGIC;
  signal edge_count_header_reg_n_0 : STD_LOGIC;
  signal eth_prot_type : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \eth_prot_type[0]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[10]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[10]_i_2_n_0\ : STD_LOGIC;
  signal \eth_prot_type[11]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[11]_i_2_n_0\ : STD_LOGIC;
  signal \eth_prot_type[11]_i_3_n_0\ : STD_LOGIC;
  signal \eth_prot_type[11]_i_4_n_0\ : STD_LOGIC;
  signal \eth_prot_type[12]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[12]_i_2_n_0\ : STD_LOGIC;
  signal \eth_prot_type[13]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[13]_i_2_n_0\ : STD_LOGIC;
  signal \eth_prot_type[13]_i_3_n_0\ : STD_LOGIC;
  signal \eth_prot_type[13]_i_4_n_0\ : STD_LOGIC;
  signal \eth_prot_type[13]_i_5_n_0\ : STD_LOGIC;
  signal \eth_prot_type[14]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[15]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[15]_i_2_n_0\ : STD_LOGIC;
  signal \eth_prot_type[15]_i_3_n_0\ : STD_LOGIC;
  signal \eth_prot_type[15]_i_4_n_0\ : STD_LOGIC;
  signal \eth_prot_type[15]_i_5_n_0\ : STD_LOGIC;
  signal \eth_prot_type[1]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[1]_i_2_n_0\ : STD_LOGIC;
  signal \eth_prot_type[2]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[3]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[3]_i_2_n_0\ : STD_LOGIC;
  signal \eth_prot_type[4]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[5]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[5]_i_2_n_0\ : STD_LOGIC;
  signal \eth_prot_type[6]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[7]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[7]_i_2_n_0\ : STD_LOGIC;
  signal \eth_prot_type[7]_i_3_n_0\ : STD_LOGIC;
  signal \eth_prot_type[7]_i_4_n_0\ : STD_LOGIC;
  signal \eth_prot_type[7]_i_5_n_0\ : STD_LOGIC;
  signal \eth_prot_type[8]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[8]_i_2_n_0\ : STD_LOGIC;
  signal \eth_prot_type[9]_i_1_n_0\ : STD_LOGIC;
  signal \eth_prot_type[9]_i_2_n_0\ : STD_LOGIC;
  signal \eth_prot_type[9]_i_3_n_0\ : STD_LOGIC;
  signal \eth_prot_type[9]_i_4_n_0\ : STD_LOGIC;
  signal eth_protocol_expected : STD_LOGIC;
  signal eth_protocol_expected_i_10_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_11_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_13_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_14_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_15_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_16_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_17_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_18_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_19_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_1_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_20_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_21_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_22_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_24_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_25_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_26_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_27_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_28_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_29_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_2_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_31_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_32_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_33_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_34_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_35_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_36_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_37_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_38_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_3_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_4_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_5_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_6_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_8_n_0 : STD_LOGIC;
  signal eth_protocol_expected_i_9_n_0 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_12_n_0 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_12_n_1 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_12_n_2 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_12_n_3 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_23_n_0 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_23_n_1 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_23_n_2 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_23_n_3 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_30_n_0 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_30_n_1 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_30_n_2 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_30_n_3 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_7_n_1 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_7_n_2 : STD_LOGIC;
  signal eth_protocol_expected_reg_i_7_n_3 : STD_LOGIC;
  signal flags_offset : STD_LOGIC;
  signal \flags_offset_reg_n_0_[0]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[10]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[11]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[12]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[13]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[14]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[15]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[1]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[2]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[3]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[4]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[5]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[6]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[7]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[8]\ : STD_LOGIC;
  signal \flags_offset_reg_n_0_[9]\ : STD_LOGIC;
  signal identification : STD_LOGIC;
  signal \identification[15]_i_1_n_0\ : STD_LOGIC;
  signal \identification_reg_n_0_[0]\ : STD_LOGIC;
  signal \identification_reg_n_0_[10]\ : STD_LOGIC;
  signal \identification_reg_n_0_[11]\ : STD_LOGIC;
  signal \identification_reg_n_0_[12]\ : STD_LOGIC;
  signal \identification_reg_n_0_[13]\ : STD_LOGIC;
  signal \identification_reg_n_0_[14]\ : STD_LOGIC;
  signal \identification_reg_n_0_[15]\ : STD_LOGIC;
  signal \identification_reg_n_0_[1]\ : STD_LOGIC;
  signal \identification_reg_n_0_[2]\ : STD_LOGIC;
  signal \identification_reg_n_0_[3]\ : STD_LOGIC;
  signal \identification_reg_n_0_[4]\ : STD_LOGIC;
  signal \identification_reg_n_0_[5]\ : STD_LOGIC;
  signal \identification_reg_n_0_[6]\ : STD_LOGIC;
  signal \identification_reg_n_0_[7]\ : STD_LOGIC;
  signal \identification_reg_n_0_[8]\ : STD_LOGIC;
  signal \identification_reg_n_0_[9]\ : STD_LOGIC;
  signal ip_extra_options : STD_LOGIC;
  signal ip_extra_options_i_1_n_0 : STD_LOGIC;
  signal ip_hcs_calc : STD_LOGIC;
  signal \ip_hcs_calc[15]_i_1_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc__0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal ip_hcs_calc_extra : STD_LOGIC;
  signal \ip_hcs_calc_extra[0]_i_10_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[0]_i_11_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[0]_i_3_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[0]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[0]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[0]_i_6_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[0]_i_7_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[0]_i_8_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[0]_i_9_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[12]_i_2_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[12]_i_3_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[12]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[12]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[12]_i_6_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[12]_i_7_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[12]_i_8_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[12]_i_9_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[16]_i_2_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[16]_i_3_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[16]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[16]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[20]_i_2_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[20]_i_3_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[20]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[20]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[4]_i_2_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[4]_i_3_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[4]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[4]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[4]_i_6_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[4]_i_7_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[4]_i_8_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[4]_i_9_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[8]_i_2_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[8]_i_3_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[8]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[8]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[8]_i_6_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[8]_i_7_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[8]_i_8_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra[8]_i_9_n_0\ : STD_LOGIC;
  signal ip_hcs_calc_extra_reg : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal \ip_hcs_calc_extra_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[0]_i_2_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[0]_i_2_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[0]_i_2_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[0]_i_2_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[16]_i_1_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[16]_i_1_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[20]_i_1_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[20]_i_1_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[20]_i_1_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[20]_i_1_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[20]_i_1_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[20]_i_1_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[20]_i_1_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_extra_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal ip_hcs_calc_temp1 : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_10_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_11_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_15_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_17_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_18_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_19_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_20_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_21_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_22_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_23_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_24_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_25_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_26_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_27_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_28_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_29_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_2_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_30_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_31_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_32_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_33_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_34_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_35_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_36_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_37_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_38_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_39_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_3_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_40_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_41_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_42_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_43_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_44_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_45_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_46_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_47_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_48_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_49_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_50_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_51_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_52_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_53_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_6_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_7_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_8_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[11]_i_9_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_10_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_11_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_12_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_17_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_18_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_19_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_20_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_21_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_22_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_23_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_24_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_25_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_26_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_27_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_28_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_29_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_2_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_30_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_31_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_32_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_33_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_34_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_35_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_36_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_37_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_38_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_39_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_3_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_40_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_41_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_42_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_43_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_44_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_45_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_46_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_47_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_48_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_49_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_50_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_51_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_6_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_7_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_8_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[15]_i_9_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_13_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_17_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_19_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_20_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_21_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_22_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_23_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_24_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_25_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_26_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_27_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_28_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_29_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_2_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_30_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_31_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_32_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_33_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_34_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_35_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_36_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_37_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_38_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_39_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_3_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_40_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_41_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_42_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_43_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_44_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_45_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_46_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_47_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_48_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_49_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_50_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_51_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_52_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_53_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_54_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_55_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_56_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_6_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_7_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_8_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[19]_i_9_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_10_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_11_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_12_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_13_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_14_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_15_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_16_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_17_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_18_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_19_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_1_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_6_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_7_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_8_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[23]_i_9_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_10_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_11_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_12_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_13_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_14_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_15_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_16_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_17_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_18_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_2_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_3_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_6_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_7_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_8_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[3]_i_9_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_10_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_11_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_15_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_16_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_17_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_18_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_19_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_20_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_21_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_22_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_23_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_24_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_25_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_26_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_27_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_28_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_29_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_2_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_30_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_31_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_32_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_33_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_34_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_35_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_36_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_37_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_38_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_39_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_3_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_40_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_41_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_6_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_7_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_8_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1[7]_i_9_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_12_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_12_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_12_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_12_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_12_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_12_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_12_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_12_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_13_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_13_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_13_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_13_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_13_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_13_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_13_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_13_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_14_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_14_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_14_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_14_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_14_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_14_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_14_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_14_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_16_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_16_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_16_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_16_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_16_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_16_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_16_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_16_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_1_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_1_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_1_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_1_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_1_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[11]_i_1_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_13_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_13_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_13_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_13_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_13_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_13_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_13_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_13_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_14_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_14_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_14_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_14_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_14_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_14_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_14_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_14_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_15_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_15_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_15_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_15_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_15_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_15_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_15_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_15_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_16_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_16_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_16_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_16_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_16_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_16_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_16_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_16_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_10_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_10_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_11_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_11_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_12_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_12_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_14_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_14_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_14_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_14_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_14_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_14_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_14_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_14_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_15_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_15_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_15_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_15_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_15_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_15_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_15_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_15_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_16_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_16_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_16_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_16_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_16_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_16_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_16_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_16_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_18_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_18_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_18_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_18_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_18_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_18_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_18_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_18_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_1_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_1_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_1_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_1_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_1_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_1_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_1_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[19]_i_1_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_2_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_2_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_2_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_2_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_2_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_2_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_2_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_3_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_3_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_3_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_3_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_3_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_3_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_3_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_4_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_4_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_4_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_4_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_4_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_4_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[23]_i_4_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_1_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_1_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_1_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_1_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_1_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_1_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_1_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_1_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_5_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_5_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_5_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_5_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_5_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_5_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[3]_i_5_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_12_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_12_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_12_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_12_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_12_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_12_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_12_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_12_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_13_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_13_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_13_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_13_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_13_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_13_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_13_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_13_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_14_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_14_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_14_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_14_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_14_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_14_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_14_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_14_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[0]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[10]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[11]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[12]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[13]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[14]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[15]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[16]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[17]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[18]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[19]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[1]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[20]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[21]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[22]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[23]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[2]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[3]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[4]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[5]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[6]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[7]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[8]\ : STD_LOGIC;
  signal \ip_hcs_calc_temp1_reg_n_0_[9]\ : STD_LOGIC;
  signal ip_hcs_calc_temp2 : STD_LOGIC;
  signal \ip_hcs_calc_temp2[11]_i_10_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[11]_i_3_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[11]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[11]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[11]_i_6_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[11]_i_7_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[11]_i_8_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[11]_i_9_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[15]_i_10_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[15]_i_1_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[15]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[15]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[15]_i_6_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[15]_i_7_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[15]_i_8_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[15]_i_9_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[3]_i_3_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[3]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[3]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[3]_i_6_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[3]_i_7_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[3]_i_8_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[3]_i_9_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[7]_i_10_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[7]_i_3_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[7]_i_4_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[7]_i_5_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[7]_i_6_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[7]_i_7_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[7]_i_8_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2[7]_i_9_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2__0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \ip_hcs_calc_temp2_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2_reg[11]_i_2_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2_reg[11]_i_2_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2_reg[11]_i_2_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2_reg[15]_i_3_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2_reg[15]_i_3_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2_reg[15]_i_3_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2_reg[3]_i_2_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2_reg[3]_i_2_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2_reg[3]_i_2_n_3\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \ip_hcs_calc_temp2_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal ip_hcs_done : STD_LOGIC;
  signal ip_hcs_done_i_1_n_0 : STD_LOGIC;
  signal ip_header_checksum : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \ip_header_checksum[15]_i_1_n_0\ : STD_LOGIC;
  signal \ip_header_length_reg_n_0_[0]\ : STD_LOGIC;
  signal \ip_header_length_reg_n_0_[1]\ : STD_LOGIC;
  signal \ip_header_length_reg_n_0_[2]\ : STD_LOGIC;
  signal \ip_header_length_reg_n_0_[3]\ : STD_LOGIC;
  signal ip_header_options1 : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal ip_header_options2 : STD_LOGIC_VECTOR ( 5 downto 3 );
  signal \ip_header_options[0]_i_1_n_0\ : STD_LOGIC;
  signal \ip_header_options[1]_i_1_n_0\ : STD_LOGIC;
  signal \ip_header_options[2]_i_1_n_0\ : STD_LOGIC;
  signal \ip_header_options[3]_i_1_n_0\ : STD_LOGIC;
  signal \ip_header_options[3]_i_2_n_0\ : STD_LOGIC;
  signal \ip_header_options[4]_i_1_n_0\ : STD_LOGIC;
  signal \ip_header_options[5]_i_1_n_0\ : STD_LOGIC;
  signal \ip_header_options[5]_i_2_n_0\ : STD_LOGIC;
  signal \ip_header_options[6]_i_1_n_0\ : STD_LOGIC;
  signal \ip_header_options[6]_i_2_n_0\ : STD_LOGIC;
  signal \ip_header_options[7]_i_10_n_0\ : STD_LOGIC;
  signal \ip_header_options[7]_i_11_n_0\ : STD_LOGIC;
  signal \ip_header_options[7]_i_12_n_0\ : STD_LOGIC;
  signal \ip_header_options[7]_i_13_n_0\ : STD_LOGIC;
  signal \ip_header_options[7]_i_1_n_0\ : STD_LOGIC;
  signal \ip_header_options[7]_i_2_n_0\ : STD_LOGIC;
  signal \ip_header_options[7]_i_3_n_0\ : STD_LOGIC;
  signal \ip_header_options[7]_i_4_n_0\ : STD_LOGIC;
  signal \ip_header_options[7]_i_5_n_0\ : STD_LOGIC;
  signal \ip_header_options[7]_i_8_n_0\ : STD_LOGIC;
  signal \ip_header_options[7]_i_9_n_0\ : STD_LOGIC;
  signal \ip_header_options_reg[7]_i_6_n_3\ : STD_LOGIC;
  signal \ip_header_options_reg[7]_i_7_n_0\ : STD_LOGIC;
  signal \ip_header_options_reg[7]_i_7_n_1\ : STD_LOGIC;
  signal \ip_header_options_reg[7]_i_7_n_2\ : STD_LOGIC;
  signal \ip_header_options_reg[7]_i_7_n_3\ : STD_LOGIC;
  signal \ip_header_options_reg_n_0_[0]\ : STD_LOGIC;
  signal \ip_header_options_reg_n_0_[1]\ : STD_LOGIC;
  signal \ip_header_options_reg_n_0_[2]\ : STD_LOGIC;
  signal \ip_header_options_reg_n_0_[3]\ : STD_LOGIC;
  signal \ip_header_options_reg_n_0_[4]\ : STD_LOGIC;
  signal \ip_header_options_reg_n_0_[5]\ : STD_LOGIC;
  signal \ip_header_options_reg_n_0_[6]\ : STD_LOGIC;
  signal \ip_header_options_reg_n_0_[7]\ : STD_LOGIC;
  signal ip_options_count_max : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal ip_options_count_max0 : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \ip_options_count_max[3]_i_1_n_0\ : STD_LOGIC;
  signal \ip_options_count_max[5]_i_2_n_0\ : STD_LOGIC;
  signal ip_total_length : STD_LOGIC_VECTOR ( 15 downto 2 );
  signal \not\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal p_0_in : STD_LOGIC;
  signal p_0_in57_in : STD_LOGIC;
  signal p_171_in : STD_LOGIC;
  signal p_1_in65_in : STD_LOGIC;
  signal read_eth_header_done : STD_LOGIC;
  signal read_eth_header_done0 : STD_LOGIC;
  signal read_eth_header_done_i_1_n_0 : STD_LOGIC;
  signal read_eth_header_done_i_2_n_0 : STD_LOGIC;
  signal read_frame_done_i_1_n_0 : STD_LOGIC;
  signal read_frame_done_i_2_n_0 : STD_LOGIC;
  signal read_frame_done_i_3_n_0 : STD_LOGIC;
  signal read_frame_done_reg_n_0 : STD_LOGIC;
  signal rst_ram_i_2_n_0 : STD_LOGIC;
  signal rst_ram_i_4_n_0 : STD_LOGIC;
  signal rst_ram_reg_n_0 : STD_LOGIC;
  signal s_ram : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \^send_arp_reply\ : STD_LOGIC;
  signal send_arp_reply_i_1_n_0 : STD_LOGIC;
  signal send_ethernet_protocol_i_1_n_0 : STD_LOGIC;
  signal sip : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \sip[0]_i_1_n_0\ : STD_LOGIC;
  signal \sip[1]_i_1_n_0\ : STD_LOGIC;
  signal source_ip : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \source_ip[0]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[10]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[11]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[12]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[13]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[14]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[15]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[16]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[17]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[18]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[19]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[1]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[20]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[21]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[22]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[23]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[24]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[25]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[26]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[27]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[28]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[29]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[2]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[30]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[31]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[31]_i_2_n_0\ : STD_LOGIC;
  signal \source_ip[3]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[4]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[5]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[6]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[7]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[8]_i_1_n_0\ : STD_LOGIC;
  signal \source_ip[9]_i_1_n_0\ : STD_LOGIC;
  signal source_mac : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal \source_mac[0]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[10]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[11]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[11]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[12]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[13]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[13]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[14]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[15]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[15]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[15]_i_3_n_0\ : STD_LOGIC;
  signal \source_mac[16]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[17]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[17]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[18]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[19]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[19]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[1]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[1]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[20]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[21]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[21]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[22]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[23]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[23]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[23]_i_3_n_0\ : STD_LOGIC;
  signal \source_mac[24]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[25]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[25]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[26]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[27]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[27]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[28]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[29]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[29]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[2]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[30]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[30]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[31]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[31]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[31]_i_3_n_0\ : STD_LOGIC;
  signal \source_mac[31]_i_4_n_0\ : STD_LOGIC;
  signal \source_mac[31]_i_5_n_0\ : STD_LOGIC;
  signal \source_mac[32]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[33]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[33]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[33]_i_3_n_0\ : STD_LOGIC;
  signal \source_mac[34]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[35]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[35]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[35]_i_3_n_0\ : STD_LOGIC;
  signal \source_mac[36]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[37]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[37]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[37]_i_3_n_0\ : STD_LOGIC;
  signal \source_mac[38]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[38]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[39]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[39]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[39]_i_3_n_0\ : STD_LOGIC;
  signal \source_mac[39]_i_4_n_0\ : STD_LOGIC;
  signal \source_mac[3]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[3]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[40]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[41]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[41]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[41]_i_3_n_0\ : STD_LOGIC;
  signal \source_mac[42]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[43]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[43]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[43]_i_3_n_0\ : STD_LOGIC;
  signal \source_mac[44]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[45]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[45]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[45]_i_3_n_0\ : STD_LOGIC;
  signal \source_mac[45]_i_4_n_0\ : STD_LOGIC;
  signal \source_mac[46]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[47]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[47]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[47]_i_3_n_0\ : STD_LOGIC;
  signal \source_mac[47]_i_4_n_0\ : STD_LOGIC;
  signal \source_mac[47]_i_5_n_0\ : STD_LOGIC;
  signal \source_mac[4]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[5]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[5]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[6]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[7]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[7]_i_2_n_0\ : STD_LOGIC;
  signal \source_mac[7]_i_3_n_0\ : STD_LOGIC;
  signal \source_mac[8]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[9]_i_1_n_0\ : STD_LOGIC;
  signal \source_mac[9]_i_2_n_0\ : STD_LOGIC;
  signal source_port : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \source_port[15]_i_1_n_0\ : STD_LOGIC;
  signal start_crc0 : STD_LOGIC;
  signal start_crc024_in : STD_LOGIC;
  signal start_crc1 : STD_LOGIC;
  signal start_crc2 : STD_LOGIC;
  signal start_crc277_in : STD_LOGIC;
  signal start_crc_i_1_n_0 : STD_LOGIC;
  signal start_crc_i_2_n_0 : STD_LOGIC;
  signal start_crc_i_4_n_0 : STD_LOGIC;
  signal start_crc_i_5_n_0 : STD_LOGIC;
  signal start_crc_i_6_n_0 : STD_LOGIC;
  signal start_crc_reg_n_0 : STD_LOGIC;
  signal state : STD_LOGIC;
  signal \state[0]_i_10_n_0\ : STD_LOGIC;
  signal \state[0]_i_11_n_0\ : STD_LOGIC;
  signal \state[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \state[0]_i_3_n_0\ : STD_LOGIC;
  signal \state[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \state[0]_i_5_n_0\ : STD_LOGIC;
  signal \state[0]_i_6_n_0\ : STD_LOGIC;
  signal \state[0]_i_7_n_0\ : STD_LOGIC;
  signal \state[0]_i_8_n_0\ : STD_LOGIC;
  signal \state[0]_i_9_n_0\ : STD_LOGIC;
  signal \state[1]_i_10_n_0\ : STD_LOGIC;
  signal \state[1]_i_11_n_0\ : STD_LOGIC;
  signal \state[1]_i_12_n_0\ : STD_LOGIC;
  signal \state[1]_i_13_n_0\ : STD_LOGIC;
  signal \state[1]_i_14_n_0\ : STD_LOGIC;
  signal \state[1]_i_15_n_0\ : STD_LOGIC;
  signal \state[1]_i_16_n_0\ : STD_LOGIC;
  signal \state[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \state[1]_i_2_n_0\ : STD_LOGIC;
  signal \state[1]_i_3_n_0\ : STD_LOGIC;
  signal \state[1]_i_4_n_0\ : STD_LOGIC;
  signal \state[1]_i_5_n_0\ : STD_LOGIC;
  signal \state[1]_i_6_n_0\ : STD_LOGIC;
  signal \state[1]_i_7_n_0\ : STD_LOGIC;
  signal \state[1]_i_9_n_0\ : STD_LOGIC;
  signal \state[1]_rep_i_1__0_n_0\ : STD_LOGIC;
  signal \state[1]_rep_i_1__1_n_0\ : STD_LOGIC;
  signal \state[1]_rep_i_1_n_0\ : STD_LOGIC;
  signal \state[2]_i_10_n_0\ : STD_LOGIC;
  signal \state[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \state[2]_i_2_n_0\ : STD_LOGIC;
  signal \state[2]_i_3_n_0\ : STD_LOGIC;
  signal \state[2]_i_4_n_0\ : STD_LOGIC;
  signal \state[2]_i_5__0_n_0\ : STD_LOGIC;
  signal \state[2]_i_6_n_0\ : STD_LOGIC;
  signal \state[2]_i_7_n_0\ : STD_LOGIC;
  signal \state[2]_i_8_n_0\ : STD_LOGIC;
  signal \state[2]_i_9__0_n_0\ : STD_LOGIC;
  signal \state[3]_i_10_n_0\ : STD_LOGIC;
  signal \state[3]_i_13_n_0\ : STD_LOGIC;
  signal \state[3]_i_14_n_0\ : STD_LOGIC;
  signal \state[3]_i_15_n_0\ : STD_LOGIC;
  signal \state[3]_i_16_n_0\ : STD_LOGIC;
  signal \state[3]_i_18_n_0\ : STD_LOGIC;
  signal \state[3]_i_19_n_0\ : STD_LOGIC;
  signal \state[3]_i_20_n_0\ : STD_LOGIC;
  signal \state[3]_i_21_n_0\ : STD_LOGIC;
  signal \state[3]_i_22_n_0\ : STD_LOGIC;
  signal \state[3]_i_23_n_0\ : STD_LOGIC;
  signal \state[3]_i_24_n_0\ : STD_LOGIC;
  signal \state[3]_i_25_n_0\ : STD_LOGIC;
  signal \state[3]_i_26_n_0\ : STD_LOGIC;
  signal \state[3]_i_27_n_0\ : STD_LOGIC;
  signal \state[3]_i_28_n_0\ : STD_LOGIC;
  signal \state[3]_i_29_n_0\ : STD_LOGIC;
  signal \state[3]_i_2_n_0\ : STD_LOGIC;
  signal \state[3]_i_30_n_0\ : STD_LOGIC;
  signal \state[3]_i_31_n_0\ : STD_LOGIC;
  signal \state[3]_i_32_n_0\ : STD_LOGIC;
  signal \state[3]_i_33_n_0\ : STD_LOGIC;
  signal \state[3]_i_34_n_0\ : STD_LOGIC;
  signal \state[3]_i_35_n_0\ : STD_LOGIC;
  signal \state[3]_i_36_n_0\ : STD_LOGIC;
  signal \state[3]_i_37_n_0\ : STD_LOGIC;
  signal \state[3]_i_38_n_0\ : STD_LOGIC;
  signal \state[3]_i_3_n_0\ : STD_LOGIC;
  signal \state[3]_i_4_n_0\ : STD_LOGIC;
  signal \state[3]_i_5_n_0\ : STD_LOGIC;
  signal \state[3]_i_6_n_0\ : STD_LOGIC;
  signal \state[3]_i_7_n_0\ : STD_LOGIC;
  signal \state[3]_i_8_n_0\ : STD_LOGIC;
  signal \state[3]_i_9_n_0\ : STD_LOGIC;
  signal \state_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \state_reg[1]_i_8_n_1\ : STD_LOGIC;
  signal \state_reg[1]_i_8_n_2\ : STD_LOGIC;
  signal \state_reg[1]_i_8_n_3\ : STD_LOGIC;
  signal \state_reg[1]_rep__0_n_0\ : STD_LOGIC;
  signal \state_reg[1]_rep__1_n_0\ : STD_LOGIC;
  signal \state_reg[1]_rep_n_0\ : STD_LOGIC;
  signal \state_reg[3]_i_11_n_3\ : STD_LOGIC;
  signal \state_reg[3]_i_12_n_1\ : STD_LOGIC;
  signal \state_reg[3]_i_12_n_2\ : STD_LOGIC;
  signal \state_reg[3]_i_12_n_3\ : STD_LOGIC;
  signal \state_reg[3]_i_17_n_0\ : STD_LOGIC;
  signal \state_reg[3]_i_17_n_1\ : STD_LOGIC;
  signal \state_reg[3]_i_17_n_2\ : STD_LOGIC;
  signal \state_reg[3]_i_17_n_3\ : STD_LOGIC;
  signal \state_reg_n_0_[0]\ : STD_LOGIC;
  signal \state_reg_n_0_[1]\ : STD_LOGIC;
  signal \state_reg_n_0_[2]\ : STD_LOGIC;
  signal \state_reg_n_0_[3]\ : STD_LOGIC;
  signal stop_crc_i_1_n_0 : STD_LOGIC;
  signal stop_crc_i_2_n_0 : STD_LOGIC;
  signal stop_crc_i_3_n_0 : STD_LOGIC;
  signal stop_crc_i_4_n_0 : STD_LOGIC;
  signal temp_data : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \temp_data[0]_i_1_n_0\ : STD_LOGIC;
  signal \temp_data[1]_i_1_n_0\ : STD_LOGIC;
  signal \temp_data[1]_i_2_n_0\ : STD_LOGIC;
  signal \temp_data[2]_i_1_n_0\ : STD_LOGIC;
  signal \temp_data[3]_i_1_n_0\ : STD_LOGIC;
  signal \temp_data[3]_i_2_n_0\ : STD_LOGIC;
  signal \temp_data[4]_i_1_n_0\ : STD_LOGIC;
  signal \temp_data[4]_i_2_n_0\ : STD_LOGIC;
  signal \temp_data[5]_i_1_n_0\ : STD_LOGIC;
  signal \temp_data[5]_i_2_n_0\ : STD_LOGIC;
  signal \temp_data[5]_i_3_n_0\ : STD_LOGIC;
  signal \temp_data[5]_i_4_n_0\ : STD_LOGIC;
  signal \temp_data[6]_i_1_n_0\ : STD_LOGIC;
  signal \temp_data[6]_i_2_n_0\ : STD_LOGIC;
  signal \temp_data[7]_i_1_n_0\ : STD_LOGIC;
  signal \temp_data[7]_i_2_n_0\ : STD_LOGIC;
  signal \temp_data[7]_i_3_n_0\ : STD_LOGIC;
  signal \udp_data_sum[0]_i_3_n_0\ : STD_LOGIC;
  signal \udp_data_sum[0]_i_4_n_0\ : STD_LOGIC;
  signal \udp_data_sum[0]_i_5_n_0\ : STD_LOGIC;
  signal \udp_data_sum[0]_i_6_n_0\ : STD_LOGIC;
  signal \udp_data_sum[12]_i_2_n_0\ : STD_LOGIC;
  signal \udp_data_sum[12]_i_3_n_0\ : STD_LOGIC;
  signal \udp_data_sum[12]_i_4_n_0\ : STD_LOGIC;
  signal \udp_data_sum[12]_i_5_n_0\ : STD_LOGIC;
  signal \udp_data_sum[4]_i_2_n_0\ : STD_LOGIC;
  signal \udp_data_sum[4]_i_3_n_0\ : STD_LOGIC;
  signal \udp_data_sum[4]_i_4_n_0\ : STD_LOGIC;
  signal \udp_data_sum[4]_i_5_n_0\ : STD_LOGIC;
  signal \udp_data_sum[8]_i_2_n_0\ : STD_LOGIC;
  signal \udp_data_sum[8]_i_3_n_0\ : STD_LOGIC;
  signal \udp_data_sum[8]_i_4_n_0\ : STD_LOGIC;
  signal \udp_data_sum[8]_i_5_n_0\ : STD_LOGIC;
  signal udp_data_sum_reg : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal \udp_data_sum_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \udp_data_sum_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \udp_data_sum_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \udp_data_sum_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \udp_data_sum_reg[0]_i_2_n_4\ : STD_LOGIC;
  signal \udp_data_sum_reg[0]_i_2_n_5\ : STD_LOGIC;
  signal \udp_data_sum_reg[0]_i_2_n_6\ : STD_LOGIC;
  signal \udp_data_sum_reg[0]_i_2_n_7\ : STD_LOGIC;
  signal \udp_data_sum_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \udp_data_sum_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \udp_data_sum_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \udp_data_sum_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \udp_data_sum_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \udp_data_sum_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \udp_data_sum_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \udp_data_sum_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \udp_data_sum_reg[16]_i_1_n_0\ : STD_LOGIC;
  signal \udp_data_sum_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \udp_data_sum_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \udp_data_sum_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \udp_data_sum_reg[16]_i_1_n_4\ : STD_LOGIC;
  signal \udp_data_sum_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \udp_data_sum_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \udp_data_sum_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \udp_data_sum_reg[20]_i_1_n_1\ : STD_LOGIC;
  signal \udp_data_sum_reg[20]_i_1_n_2\ : STD_LOGIC;
  signal \udp_data_sum_reg[20]_i_1_n_3\ : STD_LOGIC;
  signal \udp_data_sum_reg[20]_i_1_n_4\ : STD_LOGIC;
  signal \udp_data_sum_reg[20]_i_1_n_5\ : STD_LOGIC;
  signal \udp_data_sum_reg[20]_i_1_n_6\ : STD_LOGIC;
  signal \udp_data_sum_reg[20]_i_1_n_7\ : STD_LOGIC;
  signal \udp_data_sum_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \udp_data_sum_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \udp_data_sum_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \udp_data_sum_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \udp_data_sum_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \udp_data_sum_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \udp_data_sum_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \udp_data_sum_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \udp_data_sum_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \udp_data_sum_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \udp_data_sum_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \udp_data_sum_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \udp_data_sum_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \udp_data_sum_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \udp_data_sum_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \udp_data_sum_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal udp_datasum_done14_out : STD_LOGIC;
  signal udp_datasum_done_i_1_n_0 : STD_LOGIC;
  signal udp_datasum_done_reg_n_0 : STD_LOGIC;
  signal udp_hcs_calc : STD_LOGIC;
  signal \udp_hcs_calc[15]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc__0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal udp_hcs_calc_temp1 : STD_LOGIC;
  signal \udp_hcs_calc_temp1[11]_i_2_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[11]_i_3_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[11]_i_4_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[11]_i_5_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[15]_i_2_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[15]_i_3_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[15]_i_4_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[15]_i_5_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[19]_i_2_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[19]_i_3_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[19]_i_4_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[19]_i_5_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[23]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[23]_i_2_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[23]_i_4_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[23]_i_5_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[23]_i_6_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[23]_i_7_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[3]_i_2_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[3]_i_3_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[3]_i_4_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[3]_i_5_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[7]_i_2_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[7]_i_3_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[7]_i_4_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1[7]_i_5_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[11]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[11]_i_1_n_1\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[11]_i_1_n_4\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[11]_i_1_n_5\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[11]_i_1_n_6\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[11]_i_1_n_7\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[19]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[19]_i_1_n_1\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[19]_i_1_n_2\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[19]_i_1_n_3\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[19]_i_1_n_4\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[19]_i_1_n_5\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[19]_i_1_n_6\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[19]_i_1_n_7\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[23]_i_3_n_1\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[23]_i_3_n_2\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[23]_i_3_n_3\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[23]_i_3_n_4\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[23]_i_3_n_5\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[23]_i_3_n_6\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[23]_i_3_n_7\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[3]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[3]_i_1_n_1\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[3]_i_1_n_2\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[3]_i_1_n_3\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[3]_i_1_n_4\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[3]_i_1_n_5\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[3]_i_1_n_6\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[3]_i_1_n_7\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[0]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[10]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[11]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[12]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[13]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[14]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[15]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[16]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[17]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[18]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[19]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[1]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[20]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[21]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[22]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[23]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[2]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[3]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[4]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[5]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[6]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[7]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[8]\ : STD_LOGIC;
  signal \udp_hcs_calc_temp1_reg_n_0_[9]\ : STD_LOGIC;
  signal udp_hcs_calc_temp2 : STD_LOGIC;
  signal \udp_hcs_calc_temp2[0]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[10]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[11]_i_10_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[11]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[11]_i_3_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[11]_i_4_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[11]_i_5_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[11]_i_6_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[11]_i_7_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[11]_i_8_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[11]_i_9_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[12]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[13]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[14]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[15]_i_10_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[15]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[15]_i_2_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[15]_i_4_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[15]_i_5_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[15]_i_6_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[15]_i_7_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[15]_i_8_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[15]_i_9_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[1]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[2]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[3]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[3]_i_3_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[3]_i_4_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[3]_i_5_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[3]_i_6_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[3]_i_7_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[3]_i_8_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[3]_i_9_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[4]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[5]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[6]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[7]_i_10_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[7]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[7]_i_3_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[7]_i_4_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[7]_i_5_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[7]_i_6_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[7]_i_7_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[7]_i_8_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[7]_i_9_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[8]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2[9]_i_1_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2__0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \udp_hcs_calc_temp2_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[11]_i_2_n_1\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[11]_i_2_n_2\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[11]_i_2_n_3\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[11]_i_2_n_4\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[11]_i_2_n_5\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[11]_i_2_n_6\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[11]_i_2_n_7\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[15]_i_3_n_1\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[15]_i_3_n_2\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[15]_i_3_n_3\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[15]_i_3_n_4\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[15]_i_3_n_5\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[15]_i_3_n_6\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[15]_i_3_n_7\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[3]_i_2_n_1\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[3]_i_2_n_2\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[3]_i_2_n_3\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[3]_i_2_n_4\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[3]_i_2_n_5\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[3]_i_2_n_6\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[3]_i_2_n_7\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[7]_i_2_n_1\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[7]_i_2_n_2\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[7]_i_2_n_3\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[7]_i_2_n_4\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[7]_i_2_n_5\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[7]_i_2_n_6\ : STD_LOGIC;
  signal \udp_hcs_calc_temp2_reg[7]_i_2_n_7\ : STD_LOGIC;
  signal udp_hcs_done : STD_LOGIC;
  signal udp_hcs_done_i_1_n_0 : STD_LOGIC;
  signal udp_length : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \udp_length[15]_i_1_n_0\ : STD_LOGIC;
  signal udp_presum : STD_LOGIC;
  signal udp_presum0 : STD_LOGIC;
  signal \udp_presum[11]_i_10_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_11_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_12_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_16_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_17_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_18_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_19_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_20_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_21_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_22_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_23_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_24_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_25_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_26_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_27_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_28_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_29_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_2_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_30_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_31_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_32_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_33_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_34_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_35_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_36_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_37_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_38_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_39_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_3_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_40_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_41_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_42_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_43_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_44_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_45_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_4_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_5_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_6_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_7_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_8_n_0\ : STD_LOGIC;
  signal \udp_presum[11]_i_9_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_10_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_11_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_12_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_16_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_17_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_18_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_19_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_20_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_21_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_22_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_23_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_24_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_25_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_26_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_27_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_28_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_29_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_2_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_30_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_31_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_32_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_33_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_34_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_35_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_36_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_37_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_38_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_39_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_3_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_40_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_41_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_42_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_4_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_5_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_6_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_7_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_8_n_0\ : STD_LOGIC;
  signal \udp_presum[15]_i_9_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_15_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_16_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_17_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_18_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_19_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_20_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_21_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_22_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_23_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_24_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_25_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_26_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_27_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_28_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_29_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_2_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_30_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_31_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_32_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_33_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_34_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_35_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_36_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_37_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_38_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_39_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_3_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_40_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_4_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_5_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_6_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_7_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_8_n_0\ : STD_LOGIC;
  signal \udp_presum[19]_i_9_n_0\ : STD_LOGIC;
  signal \udp_presum[23]_i_6_n_0\ : STD_LOGIC;
  signal \udp_presum[3]_i_10_n_0\ : STD_LOGIC;
  signal \udp_presum[3]_i_11_n_0\ : STD_LOGIC;
  signal \udp_presum[3]_i_12_n_0\ : STD_LOGIC;
  signal \udp_presum[3]_i_2_n_0\ : STD_LOGIC;
  signal \udp_presum[3]_i_3_n_0\ : STD_LOGIC;
  signal \udp_presum[3]_i_4_n_0\ : STD_LOGIC;
  signal \udp_presum[3]_i_5_n_0\ : STD_LOGIC;
  signal \udp_presum[3]_i_6_n_0\ : STD_LOGIC;
  signal \udp_presum[3]_i_7_n_0\ : STD_LOGIC;
  signal \udp_presum[3]_i_8_n_0\ : STD_LOGIC;
  signal \udp_presum[3]_i_9_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_10_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_14_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_15_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_16_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_17_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_18_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_19_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_20_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_21_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_22_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_23_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_24_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_25_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_26_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_27_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_28_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_29_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_2_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_30_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_31_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_32_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_33_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_34_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_35_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_36_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_37_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_38_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_39_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_3_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_40_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_41_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_42_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_4_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_5_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_6_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_7_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_8_n_0\ : STD_LOGIC;
  signal \udp_presum[7]_i_9_n_0\ : STD_LOGIC;
  signal udp_presum_done : STD_LOGIC;
  signal udp_presum_done_i_1_n_0 : STD_LOGIC;
  signal \udp_presum_reg[11]_i_13_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_13_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_13_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_13_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_13_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_13_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_13_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_13_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_14_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_14_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_14_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_14_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_14_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_14_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_14_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_14_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_15_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_15_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_15_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_15_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_15_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_15_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_15_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_15_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_1_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_1_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_1_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_1_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_1_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[11]_i_1_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_13_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_13_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_13_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_13_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_13_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_13_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_13_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_13_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_14_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_14_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_14_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_14_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_14_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_14_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_14_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_14_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_15_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_15_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_15_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_15_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_15_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_15_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_15_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_15_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_10_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_10_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_11_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_11_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_12_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_12_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_12_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_12_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_12_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_12_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_12_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_12_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_13_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_13_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_13_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_13_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_13_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_13_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_13_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_13_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_14_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_14_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_14_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_14_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_14_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_14_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_14_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_14_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_1_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_1_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_1_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_1_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_1_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_1_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_1_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[19]_i_1_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_3_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_3_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_3_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_3_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_3_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_3_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_3_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_4_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_4_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_4_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_4_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_4_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_4_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_4_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_5_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_5_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_5_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_5_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_5_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_5_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_5_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[23]_i_5_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[3]_i_1_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[3]_i_1_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[3]_i_1_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[3]_i_1_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[3]_i_1_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[3]_i_1_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[3]_i_1_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[3]_i_1_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_11_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_11_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_11_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_11_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_11_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_11_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_11_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_11_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_12_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_12_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_12_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_12_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_12_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_12_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_12_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_12_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_13_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_13_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_13_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_13_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_13_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_13_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_13_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_13_n_7\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_1_n_0\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_1_n_1\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_1_n_2\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_1_n_3\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_1_n_4\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_1_n_5\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_1_n_6\ : STD_LOGIC;
  signal \udp_presum_reg[7]_i_1_n_7\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[0]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[10]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[11]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[12]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[13]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[14]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[15]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[16]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[17]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[18]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[19]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[1]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[20]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[21]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[22]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[23]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[2]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[3]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[4]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[5]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[6]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[7]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[8]\ : STD_LOGIC;
  signal \udp_presum_reg_n_0_[9]\ : STD_LOGIC;
  signal udp_send_data_valid_i_19_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_20_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_2_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_3_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_6_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_7_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_8_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_9_n_0 : STD_LOGIC;
  signal unknown_request1_i_1_n_0 : STD_LOGIC;
  signal unknown_request1_reg_n_0 : STD_LOGIC;
  signal unknown_request2 : STD_LOGIC;
  signal unknown_request20 : STD_LOGIC;
  signal unknown_request2_i_10_n_0 : STD_LOGIC;
  signal unknown_request2_i_11_n_0 : STD_LOGIC;
  signal unknown_request2_i_12_n_0 : STD_LOGIC;
  signal unknown_request2_i_13_n_0 : STD_LOGIC;
  signal unknown_request2_i_14_n_0 : STD_LOGIC;
  signal unknown_request2_i_15_n_0 : STD_LOGIC;
  signal unknown_request2_i_17_n_0 : STD_LOGIC;
  signal unknown_request2_i_18_n_0 : STD_LOGIC;
  signal unknown_request2_i_19_n_0 : STD_LOGIC;
  signal unknown_request2_i_1_n_0 : STD_LOGIC;
  signal unknown_request2_i_20_n_0 : STD_LOGIC;
  signal unknown_request2_i_21_n_0 : STD_LOGIC;
  signal unknown_request2_i_22_n_0 : STD_LOGIC;
  signal unknown_request2_i_23_n_0 : STD_LOGIC;
  signal unknown_request2_i_24_n_0 : STD_LOGIC;
  signal unknown_request2_i_4_n_0 : STD_LOGIC;
  signal unknown_request2_i_6_n_0 : STD_LOGIC;
  signal unknown_request2_i_7_n_0 : STD_LOGIC;
  signal unknown_request2_i_9_n_0 : STD_LOGIC;
  signal unknown_request2_reg_i_16_n_0 : STD_LOGIC;
  signal unknown_request2_reg_i_16_n_1 : STD_LOGIC;
  signal unknown_request2_reg_i_16_n_2 : STD_LOGIC;
  signal unknown_request2_reg_i_16_n_3 : STD_LOGIC;
  signal unknown_request2_reg_i_2_n_2 : STD_LOGIC;
  signal unknown_request2_reg_i_2_n_3 : STD_LOGIC;
  signal unknown_request2_reg_i_3_n_2 : STD_LOGIC;
  signal unknown_request2_reg_i_3_n_3 : STD_LOGIC;
  signal unknown_request2_reg_i_5_n_0 : STD_LOGIC;
  signal unknown_request2_reg_i_5_n_1 : STD_LOGIC;
  signal unknown_request2_reg_i_5_n_2 : STD_LOGIC;
  signal unknown_request2_reg_i_5_n_3 : STD_LOGIC;
  signal unknown_request2_reg_i_8_n_0 : STD_LOGIC;
  signal unknown_request2_reg_i_8_n_1 : STD_LOGIC;
  signal unknown_request2_reg_i_8_n_2 : STD_LOGIC;
  signal unknown_request2_reg_i_8_n_3 : STD_LOGIC;
  signal unknown_request3_i_1_n_0 : STD_LOGIC;
  signal unknown_request3_i_2_n_0 : STD_LOGIC;
  signal unknown_request3_i_3_n_0 : STD_LOGIC;
  signal unknown_request3_i_4_n_0 : STD_LOGIC;
  signal unknown_request3_i_5_n_0 : STD_LOGIC;
  signal unknown_request3_reg_n_0 : STD_LOGIC;
  signal unknown_request4_i_1_n_0 : STD_LOGIC;
  signal unknown_request4_i_2_n_0 : STD_LOGIC;
  signal unknown_request4_i_3_n_0 : STD_LOGIC;
  signal unknown_request4_i_4_n_0 : STD_LOGIC;
  signal unknown_request4_i_5_n_0 : STD_LOGIC;
  signal unknown_request4_reg_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_10_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_11_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_12_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_13_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_14_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_15_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_16_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_17_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_18_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_19_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_1_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_20_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_21_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_3_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_4_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_6_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_7_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_8_n_0 : STD_LOGIC;
  signal valid_data_byte_read_i_9_n_0 : STD_LOGIC;
  signal valid_data_byte_read_reg_i_2_n_3 : STD_LOGIC;
  signal valid_data_byte_read_reg_i_5_n_0 : STD_LOGIC;
  signal valid_data_byte_read_reg_i_5_n_1 : STD_LOGIC;
  signal valid_data_byte_read_reg_i_5_n_2 : STD_LOGIC;
  signal valid_data_byte_read_reg_i_5_n_3 : STD_LOGIC;
  signal valid_data_byte_read_reg_n_0 : STD_LOGIC;
  signal we_ram_i_1_n_0 : STD_LOGIC;
  signal wrt_addr_ram : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal wrt_enable_ram : STD_LOGIC;
  signal zero_counter : STD_LOGIC_VECTOR ( 4 to 4 );
  signal \zero_counter[0]_i_1_n_0\ : STD_LOGIC;
  signal \zero_counter[1]_i_1_n_0\ : STD_LOGIC;
  signal \zero_counter[2]_i_1_n_0\ : STD_LOGIC;
  signal \zero_counter[3]_i_1_n_0\ : STD_LOGIC;
  signal \zero_counter[4]_i_1_n_0\ : STD_LOGIC;
  signal \zero_counter[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \zero_counter[4]_i_4_n_0\ : STD_LOGIC;
  signal \zero_counter[4]_i_5_n_0\ : STD_LOGIC;
  signal \zero_counter[4]_i_6_n_0\ : STD_LOGIC;
  signal \zero_counter[4]_i_7_n_0\ : STD_LOGIC;
  signal \zero_counter[4]_i_8_n_0\ : STD_LOGIC;
  signal \zero_counter[4]_i_9_n_0\ : STD_LOGIC;
  signal \zero_counter_reg_n_0_[0]\ : STD_LOGIC;
  signal \zero_counter_reg_n_0_[1]\ : STD_LOGIC;
  signal \zero_counter_reg_n_0_[2]\ : STD_LOGIC;
  signal \zero_counter_reg_n_0_[3]\ : STD_LOGIC;
  signal \zero_counter_reg_n_0_[4]\ : STD_LOGIC;
  signal \NLW_byte_count_extra_reg[5]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_byte_count_reg[1]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_byte_count_reg[1]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_byte_count_reg[1]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_data_counter_max_reg[10]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_data_counter_max_reg[10]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal NLW_eth_protocol_expected_reg_i_12_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_eth_protocol_expected_reg_i_23_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_eth_protocol_expected_reg_i_30_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_eth_protocol_expected_reg_i_7_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_ip_hcs_calc_extra_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_ip_hcs_calc_temp1_reg[19]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_ip_hcs_calc_temp1_reg[19]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_ip_hcs_calc_temp1_reg[19]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_ip_hcs_calc_temp1_reg[19]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_ip_hcs_calc_temp1_reg[19]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_ip_hcs_calc_temp1_reg[19]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_ip_hcs_calc_temp1_reg[23]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_ip_hcs_calc_temp1_reg[23]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_ip_hcs_calc_temp2_reg[15]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_ip_header_options_reg[7]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_ip_header_options_reg[7]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_ip_header_options_reg[7]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_state_reg[1]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_state_reg[3]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_state_reg[3]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_state_reg[3]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_state_reg[3]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udp_data_sum_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_udp_hcs_calc_temp1_reg[23]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_udp_hcs_calc_temp2_reg[15]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_udp_presum_reg[19]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udp_presum_reg[19]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_udp_presum_reg[19]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_udp_presum_reg[19]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_udp_presum_reg[23]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_udp_presum_reg[23]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal NLW_unknown_request2_reg_i_16_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_unknown_request2_reg_i_2_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_unknown_request2_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_unknown_request2_reg_i_3_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
  signal NLW_unknown_request2_reg_i_3_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_unknown_request2_reg_i_5_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_unknown_request2_reg_i_8_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_valid_data_byte_read_reg_i_2_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_valid_data_byte_read_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_valid_data_byte_read_reg_i_5_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_sip_reg[0]\ : label is "sip1:001,sip2:010,sip3:100,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_sip_reg[1]\ : label is "sip1:001,sip2:010,sip3:100,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_sip_reg[2]\ : label is "sip1:001,sip2:010,sip3:100,";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_sudp[0]_i_1\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \FSM_onehot_sudp[1]_i_1\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \FSM_onehot_sudp[2]_i_1\ : label is "soft_lutpair77";
  attribute FSM_ENCODED_STATES of \FSM_onehot_sudp_reg[0]\ : label is "sudp1:001,sudp2:010,sudp3:100,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_sudp_reg[1]\ : label is "sudp1:001,sudp2:010,sudp3:100,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_sudp_reg[2]\ : label is "sudp1:001,sudp2:010,sudp3:100,";
  attribute SOFT_HLUTNM of \FSM_sequential_s_ram[1]_i_1\ : label is "soft_lutpair16";
  attribute FSM_ENCODED_STATES of \FSM_sequential_s_ram_reg[1]\ : label is "s_ram2:01,s_ram3:01,s_ram1:00,s_ram4:10";
  attribute SOFT_HLUTNM of \addr_count[1]_i_1\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \addr_count[1]_i_2\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \bit_count[1]_i_3\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \bit_count[1]_i_4\ : label is "soft_lutpair34";
  attribute ORIG_CELL_NAME : string;
  attribute ORIG_CELL_NAME of \bit_count_reg[0]\ : label is "bit_count_reg[0]";
  attribute ORIG_CELL_NAME of \bit_count_reg[0]_rep\ : label is "bit_count_reg[0]";
  attribute ORIG_CELL_NAME of \bit_count_reg[1]\ : label is "bit_count_reg[1]";
  attribute ORIG_CELL_NAME of \bit_count_reg[1]_rep\ : label is "bit_count_reg[1]";
  attribute SOFT_HLUTNM of \byte_count[0]_i_3\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \byte_count[10]_i_11\ : label is "soft_lutpair196";
  attribute SOFT_HLUTNM of \byte_count[10]_i_14\ : label is "soft_lutpair129";
  attribute SOFT_HLUTNM of \byte_count[10]_i_17\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \byte_count[10]_i_18\ : label is "soft_lutpair138";
  attribute SOFT_HLUTNM of \byte_count[10]_i_21\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \byte_count[10]_i_5\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of \byte_count[10]_i_8\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \byte_count[1]_i_22\ : label is "soft_lutpair151";
  attribute SOFT_HLUTNM of \byte_count[1]_i_23\ : label is "soft_lutpair133";
  attribute SOFT_HLUTNM of \byte_count[1]_i_24\ : label is "soft_lutpair133";
  attribute SOFT_HLUTNM of \byte_count[1]_i_5\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \byte_count[1]_i_7\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \byte_count[2]_i_1\ : label is "soft_lutpair131";
  attribute SOFT_HLUTNM of \byte_count[3]_i_1\ : label is "soft_lutpair131";
  attribute SOFT_HLUTNM of \byte_count[4]_i_1\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \byte_count[7]_i_1__0\ : label is "soft_lutpair151";
  attribute SOFT_HLUTNM of \byte_count[8]_i_1\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \byte_count[9]_i_1\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \byte_count_extra[0]_i_1\ : label is "soft_lutpair152";
  attribute SOFT_HLUTNM of \byte_count_extra[1]_i_1\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \byte_count_extra[2]_i_1\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \byte_count_extra[4]_i_2\ : label is "soft_lutpair145";
  attribute SOFT_HLUTNM of \byte_count_extra[5]_i_5\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \byte_count_extra[5]_i_8\ : label is "soft_lutpair74";
  attribute ORIG_CELL_NAME of \byte_count_reg[0]\ : label is "byte_count_reg[0]";
  attribute ORIG_CELL_NAME of \byte_count_reg[0]_rep\ : label is "byte_count_reg[0]";
  attribute ORIG_CELL_NAME of \byte_count_reg[0]_rep__0\ : label is "byte_count_reg[0]";
  attribute ORIG_CELL_NAME of \byte_count_reg[0]_rep__1\ : label is "byte_count_reg[0]";
  attribute ORIG_CELL_NAME of \byte_count_reg[1]\ : label is "byte_count_reg[1]";
  attribute ORIG_CELL_NAME of \byte_count_reg[1]_rep\ : label is "byte_count_reg[1]";
  attribute SOFT_HLUTNM of \byte_read_done[0]_i_2\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \byte_read_done[0]_i_3\ : label is "soft_lutpair206";
  attribute SOFT_HLUTNM of \byte_read_done[10]_i_2\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \byte_read_done[10]_i_3\ : label is "soft_lutpair199";
  attribute SOFT_HLUTNM of \byte_read_done[10]_i_5\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \byte_read_done[11]_i_3\ : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \byte_read_done[11]_i_4\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \byte_read_done[11]_i_5\ : label is "soft_lutpair198";
  attribute SOFT_HLUTNM of \byte_read_done[12]_i_2\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \byte_read_done[12]_i_4\ : label is "soft_lutpair197";
  attribute SOFT_HLUTNM of \byte_read_done[13]_i_3\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \byte_read_done[13]_i_5\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \byte_read_done[13]_i_6\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \byte_read_done[1]_i_2\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \byte_read_done[1]_i_3\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \byte_read_done[2]_i_3\ : label is "soft_lutpair205";
  attribute SOFT_HLUTNM of \byte_read_done[3]_i_10\ : label is "soft_lutpair140";
  attribute SOFT_HLUTNM of \byte_read_done[3]_i_11\ : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \byte_read_done[3]_i_2\ : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of \byte_read_done[3]_i_5\ : label is "soft_lutpair204";
  attribute SOFT_HLUTNM of \byte_read_done[3]_i_8\ : label is "soft_lutpair140";
  attribute SOFT_HLUTNM of \byte_read_done[3]_i_9\ : label is "soft_lutpair146";
  attribute SOFT_HLUTNM of \byte_read_done[5]_i_2\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \byte_read_done[5]_i_3\ : label is "soft_lutpair203";
  attribute SOFT_HLUTNM of \byte_read_done[6]_i_3\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \byte_read_done[6]_i_4\ : label is "soft_lutpair202";
  attribute SOFT_HLUTNM of \byte_read_done[7]_i_4\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \byte_read_done[8]_i_2\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \byte_read_done[8]_i_3\ : label is "soft_lutpair201";
  attribute SOFT_HLUTNM of \byte_read_done[9]_i_2\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \byte_read_done[9]_i_3\ : label is "soft_lutpair200";
  attribute SOFT_HLUTNM of \bytes00[10]_i_2\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \bytes00[11]_i_3\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \bytes00[12]_i_2\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \bytes00[13]_i_3\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \bytes00[14]_i_2\ : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \bytes00[15]_i_3\ : label is "soft_lutpair184";
  attribute SOFT_HLUTNM of \bytes00[15]_i_5\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \bytes00[1]_i_2\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \bytes00[3]_i_2\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \bytes00[7]_i_2\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \bytes00[7]_i_4\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \bytes00[8]_i_2\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \bytes01[10]_i_2\ : label is "soft_lutpair134";
  attribute SOFT_HLUTNM of \bytes01[11]_i_2\ : label is "soft_lutpair135";
  attribute SOFT_HLUTNM of \bytes01[12]_i_2\ : label is "soft_lutpair134";
  attribute SOFT_HLUTNM of \bytes01[13]_i_2\ : label is "soft_lutpair135";
  attribute SOFT_HLUTNM of \bytes01[14]_i_2\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \bytes01[15]_i_2\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \bytes01[8]_i_2\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \bytes01[9]_i_2\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \bytes02[11]_i_2\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \bytes02[13]_i_2\ : label is "soft_lutpair188";
  attribute SOFT_HLUTNM of \bytes02[13]_i_3\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \bytes02[15]_i_2\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \bytes02[1]_i_2\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \bytes02[3]_i_2\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \bytes02[5]_i_2\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \bytes02[7]_i_2\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \bytes02[9]_i_2\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \bytes03[10]_i_2\ : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of \bytes03[11]_i_3\ : label is "soft_lutpair124";
  attribute SOFT_HLUTNM of \bytes03[12]_i_2\ : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \bytes03[13]_i_3\ : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \bytes03[13]_i_4\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \bytes03[13]_i_5\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \bytes03[14]_i_2\ : label is "soft_lutpair172";
  attribute SOFT_HLUTNM of \bytes03[15]_i_2\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \bytes03[15]_i_3\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \bytes03[7]_i_3\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \bytes03[8]_i_2\ : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of \bytes03[9]_i_3\ : label is "soft_lutpair124";
  attribute SOFT_HLUTNM of \bytes04[10]_i_2\ : label is "soft_lutpair138";
  attribute SOFT_HLUTNM of \bytes04[11]_i_3\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \bytes04[12]_i_2\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \bytes04[13]_i_3\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \bytes04[14]_i_2\ : label is "soft_lutpair176";
  attribute SOFT_HLUTNM of \bytes04[15]_i_3\ : label is "soft_lutpair189";
  attribute SOFT_HLUTNM of \bytes04[15]_i_4\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \bytes04[8]_i_2\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \bytes04[9]_i_3\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \bytes05[11]_i_2\ : label is "soft_lutpair148";
  attribute SOFT_HLUTNM of \bytes05[13]_i_2\ : label is "soft_lutpair147";
  attribute SOFT_HLUTNM of \bytes05[15]_i_2\ : label is "soft_lutpair148";
  attribute SOFT_HLUTNM of \bytes05[9]_i_2\ : label is "soft_lutpair147";
  attribute SOFT_HLUTNM of \bytes06[13]_i_5\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \bytes06[15]_i_2\ : label is "soft_lutpair202";
  attribute SOFT_HLUTNM of \bytes06[7]_i_2\ : label is "soft_lutpair201";
  attribute SOFT_HLUTNM of \bytes07[10]_i_2\ : label is "soft_lutpair178";
  attribute SOFT_HLUTNM of \bytes07[11]_i_3\ : label is "soft_lutpair189";
  attribute SOFT_HLUTNM of \bytes07[12]_i_2\ : label is "soft_lutpair177";
  attribute SOFT_HLUTNM of \bytes07[13]_i_3\ : label is "soft_lutpair188";
  attribute SOFT_HLUTNM of \bytes07[14]_i_2\ : label is "soft_lutpair177";
  attribute SOFT_HLUTNM of \bytes07[15]_i_2\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \bytes07[15]_i_3\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \bytes07[1]_i_2\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \bytes07[3]_i_2\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \bytes07[5]_i_2\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \bytes07[8]_i_2\ : label is "soft_lutpair181";
  attribute SOFT_HLUTNM of \bytes07[9]_i_3\ : label is "soft_lutpair190";
  attribute SOFT_HLUTNM of \bytes08[10]_i_2\ : label is "soft_lutpair183";
  attribute SOFT_HLUTNM of \bytes08[11]_i_2\ : label is "soft_lutpair192";
  attribute SOFT_HLUTNM of \bytes08[11]_i_3\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \bytes08[12]_i_2\ : label is "soft_lutpair180";
  attribute SOFT_HLUTNM of \bytes08[13]_i_2\ : label is "soft_lutpair191";
  attribute SOFT_HLUTNM of \bytes08[13]_i_3\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \bytes08[14]_i_2\ : label is "soft_lutpair178";
  attribute SOFT_HLUTNM of \bytes08[15]_i_2\ : label is "soft_lutpair190";
  attribute SOFT_HLUTNM of \bytes08[15]_i_3\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \bytes08[8]_i_2\ : label is "soft_lutpair182";
  attribute SOFT_HLUTNM of \bytes08[9]_i_2\ : label is "soft_lutpair193";
  attribute SOFT_HLUTNM of \bytes08[9]_i_3\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \bytes09[10]_i_2\ : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of \bytes09[11]_i_2\ : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of \bytes09[12]_i_2\ : label is "soft_lutpair128";
  attribute SOFT_HLUTNM of \bytes09[13]_i_2\ : label is "soft_lutpair129";
  attribute SOFT_HLUTNM of \bytes09[15]_i_2\ : label is "soft_lutpair128";
  attribute SOFT_HLUTNM of \bytes09[8]_i_2\ : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of \bytes09[9]_i_2\ : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of \bytes10[11]_i_2\ : label is "soft_lutpair150";
  attribute SOFT_HLUTNM of \bytes10[13]_i_2\ : label is "soft_lutpair170";
  attribute SOFT_HLUTNM of \bytes10[14]_i_2\ : label is "soft_lutpair181";
  attribute SOFT_HLUTNM of \bytes10[15]_i_3\ : label is "soft_lutpair192";
  attribute SOFT_HLUTNM of \bytes10[9]_i_2\ : label is "soft_lutpair150";
  attribute SOFT_HLUTNM of \bytes11[13]_i_2\ : label is "soft_lutpair208";
  attribute SOFT_HLUTNM of \bytes11[14]_i_2\ : label is "soft_lutpair176";
  attribute SOFT_HLUTNM of \bytes11[15]_i_2\ : label is "soft_lutpair194";
  attribute SOFT_HLUTNM of \bytes11[15]_i_3\ : label is "soft_lutpair207";
  attribute SOFT_HLUTNM of \bytes11[1]_i_2\ : label is "soft_lutpair204";
  attribute SOFT_HLUTNM of \bytes11[3]_i_2\ : label is "soft_lutpair205";
  attribute SOFT_HLUTNM of \bytes11[5]_i_2\ : label is "soft_lutpair206";
  attribute SOFT_HLUTNM of \bytes11[7]_i_2\ : label is "soft_lutpair207";
  attribute SOFT_HLUTNM of \bytes11[9]_i_2\ : label is "soft_lutpair208";
  attribute SOFT_HLUTNM of \bytes12[10]_i_2\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \bytes12[11]_i_2\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \bytes12[12]_i_2\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \bytes12[13]_i_2\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \bytes12[15]_i_2\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \bytes12[2]_i_1\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \bytes12[8]_i_2\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \bytes12[9]_i_2\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \bytes13[14]_i_2\ : label is "soft_lutpair179";
  attribute SOFT_HLUTNM of \bytes13[15]_i_2\ : label is "soft_lutpair169";
  attribute SOFT_HLUTNM of \bytes13[15]_i_5\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \bytes13[7]_i_3\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of crc_pass_i_1 : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of crc_pass_i_2 : label is "soft_lutpair139";
  attribute SOFT_HLUTNM of \crc_rx[0]_i_2\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \crc_rx[16]_i_2\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \crc_rx[17]_i_1\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of \crc_rx[1]_i_1\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \crc_rx[1]_i_2\ : label is "soft_lutpair196";
  attribute SOFT_HLUTNM of \crc_rx[24]_i_2\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \crc_rx[25]_i_1\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \crc_rx[25]_i_2\ : label is "soft_lutpair197";
  attribute SOFT_HLUTNM of \crc_rx[26]_i_2\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \crc_rx[27]_i_1\ : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \crc_rx[27]_i_2\ : label is "soft_lutpair198";
  attribute SOFT_HLUTNM of \crc_rx[28]_i_2\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \crc_rx[29]_i_1\ : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of \crc_rx[29]_i_2\ : label is "soft_lutpair199";
  attribute SOFT_HLUTNM of \crc_rx[30]_i_3\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \crc_rx[31]_i_1\ : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of \crc_rx[31]_i_2\ : label is "soft_lutpair200";
  attribute SOFT_HLUTNM of \crc_rx[9]_i_1\ : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \data_to_ram[0]_i_1\ : label is "soft_lutpair209";
  attribute SOFT_HLUTNM of \data_to_ram[1]_i_1\ : label is "soft_lutpair210";
  attribute SOFT_HLUTNM of \data_to_ram[2]_i_1\ : label is "soft_lutpair211";
  attribute SOFT_HLUTNM of \data_to_ram[3]_i_1\ : label is "soft_lutpair212";
  attribute SOFT_HLUTNM of \data_to_ram[4]_i_1\ : label is "soft_lutpair212";
  attribute SOFT_HLUTNM of \data_to_ram[5]_i_1\ : label is "soft_lutpair211";
  attribute SOFT_HLUTNM of \data_to_ram[6]_i_1\ : label is "soft_lutpair210";
  attribute SOFT_HLUTNM of \data_to_ram[7]_i_3\ : label is "soft_lutpair209";
  attribute SOFT_HLUTNM of \dest_mac[12]_i_2\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \dest_mac[12]_i_3\ : label is "soft_lutpair171";
  attribute SOFT_HLUTNM of \dest_mac[12]_i_4\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \dest_mac[15]_i_2\ : label is "soft_lutpair142";
  attribute SOFT_HLUTNM of \dest_mac[15]_i_4\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \dest_mac[31]_i_2\ : label is "soft_lutpair137";
  attribute SOFT_HLUTNM of \dest_mac[31]_i_5\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \dest_mac[39]_i_4\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \dest_mac[40]_i_2\ : label is "soft_lutpair175";
  attribute SOFT_HLUTNM of \dest_mac[41]_i_2\ : label is "soft_lutpair175";
  attribute SOFT_HLUTNM of \dest_mac[42]_i_2\ : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of \dest_mac[43]_i_2\ : label is "soft_lutpair186";
  attribute SOFT_HLUTNM of \dest_mac[43]_i_4\ : label is "soft_lutpair149";
  attribute SOFT_HLUTNM of \dest_mac[44]_i_2\ : label is "soft_lutpair173";
  attribute SOFT_HLUTNM of \dest_mac[45]_i_2\ : label is "soft_lutpair173";
  attribute SOFT_HLUTNM of \dest_mac[45]_i_4\ : label is "soft_lutpair149";
  attribute SOFT_HLUTNM of \dest_mac[46]_i_2\ : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of \dest_mac[47]_i_2\ : label is "soft_lutpair185";
  attribute SOFT_HLUTNM of \dest_mac[47]_i_3\ : label is "soft_lutpair142";
  attribute SOFT_HLUTNM of \dest_mac[47]_i_6\ : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \dest_mac[47]_i_7\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of edge_count_data_i_1 : label is "soft_lutpair132";
  attribute SOFT_HLUTNM of \eth_prot_type[10]_i_2\ : label is "soft_lutpair171";
  attribute SOFT_HLUTNM of \eth_prot_type[11]_i_2\ : label is "soft_lutpair186";
  attribute SOFT_HLUTNM of \eth_prot_type[12]_i_2\ : label is "soft_lutpair172";
  attribute SOFT_HLUTNM of \eth_prot_type[13]_i_2\ : label is "soft_lutpair185";
  attribute SOFT_HLUTNM of \eth_prot_type[15]_i_4\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \eth_prot_type[15]_i_5\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of \eth_prot_type[7]_i_2\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \eth_prot_type[7]_i_3\ : label is "soft_lutpair136";
  attribute SOFT_HLUTNM of \eth_prot_type[7]_i_5\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \eth_prot_type[8]_i_2\ : label is "soft_lutpair174";
  attribute SOFT_HLUTNM of \eth_prot_type[9]_i_2\ : label is "soft_lutpair187";
  attribute SOFT_HLUTNM of fifo_we_i_1 : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \fifo_write[15]_i_1\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \fifo_write[23]_i_1\ : label is "soft_lutpair144";
  attribute SOFT_HLUTNM of \fifo_write[7]_i_1\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[11]_i_10\ : label is "soft_lutpair160";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[11]_i_11\ : label is "soft_lutpair161";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[11]_i_15\ : label is "soft_lutpair162";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[11]_i_17\ : label is "soft_lutpair163";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[11]_i_18\ : label is "soft_lutpair160";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[11]_i_19\ : label is "soft_lutpair161";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[11]_i_20\ : label is "soft_lutpair162";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[11]_i_21\ : label is "soft_lutpair163";
  attribute HLUTNM : string;
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_22\ : label is "lutpair39";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_25\ : label is "lutpair38";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_26\ : label is "lutpair40";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_27\ : label is "lutpair39";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_30\ : label is "lutpair17";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_33\ : label is "lutpair16";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_34\ : label is "lutpair18";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_35\ : label is "lutpair17";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_38\ : label is "lutpair28";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_41\ : label is "lutpair27";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_42\ : label is "lutpair29";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_43\ : label is "lutpair28";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_46\ : label is "lutpair6";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_47\ : label is "lutpair5";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_48\ : label is "lutpair4";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_49\ : label is "lutpair3";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_50\ : label is "lutpair7";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_51\ : label is "lutpair6";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_52\ : label is "lutpair5";
  attribute HLUTNM of \ip_hcs_calc_temp1[11]_i_53\ : label is "lutpair4";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[15]_i_10\ : label is "soft_lutpair158";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[15]_i_12\ : label is "soft_lutpair159";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[15]_i_18\ : label is "soft_lutpair158";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[15]_i_19\ : label is "soft_lutpair159";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_20\ : label is "lutpair43";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_21\ : label is "lutpair42";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_22\ : label is "lutpair41";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_23\ : label is "lutpair40";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_24\ : label is "lutpair44";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_25\ : label is "lutpair43";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_26\ : label is "lutpair42";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_27\ : label is "lutpair41";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_28\ : label is "lutpair21";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_29\ : label is "lutpair20";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_30\ : label is "lutpair19";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_31\ : label is "lutpair18";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_32\ : label is "lutpair22";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_33\ : label is "lutpair21";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_34\ : label is "lutpair20";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_35\ : label is "lutpair19";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_36\ : label is "lutpair32";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_37\ : label is "lutpair31";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_38\ : label is "lutpair30";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_39\ : label is "lutpair29";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_40\ : label is "lutpair33";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_41\ : label is "lutpair32";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_42\ : label is "lutpair31";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_43\ : label is "lutpair30";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_44\ : label is "lutpair10";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_45\ : label is "lutpair9";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_46\ : label is "lutpair8";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_47\ : label is "lutpair7";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_48\ : label is "lutpair11";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_49\ : label is "lutpair10";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_50\ : label is "lutpair9";
  attribute HLUTNM of \ip_hcs_calc_temp1[15]_i_51\ : label is "lutpair8";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[19]_i_17\ : label is "soft_lutpair156";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[19]_i_19\ : label is "soft_lutpair157";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[19]_i_20\ : label is "soft_lutpair156";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[19]_i_21\ : label is "soft_lutpair157";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_25\ : label is "lutpair47";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_26\ : label is "lutpair46";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_27\ : label is "lutpair45";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_28\ : label is "lutpair44";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_30\ : label is "lutpair47";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_31\ : label is "lutpair46";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_32\ : label is "lutpair45";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_33\ : label is "lutpair25";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_34\ : label is "lutpair24";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_35\ : label is "lutpair23";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_36\ : label is "lutpair22";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_38\ : label is "lutpair25";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_39\ : label is "lutpair24";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_40\ : label is "lutpair23";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_41\ : label is "lutpair36";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_42\ : label is "lutpair35";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_43\ : label is "lutpair34";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_44\ : label is "lutpair33";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_46\ : label is "lutpair36";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_47\ : label is "lutpair35";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_48\ : label is "lutpair34";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_49\ : label is "lutpair14";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_50\ : label is "lutpair13";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_51\ : label is "lutpair12";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_52\ : label is "lutpair11";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_54\ : label is "lutpair14";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_55\ : label is "lutpair13";
  attribute HLUTNM of \ip_hcs_calc_temp1[19]_i_56\ : label is "lutpair12";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[3]_i_10\ : label is "soft_lutpair168";
  attribute HLUTNM of \ip_hcs_calc_temp1[3]_i_11\ : label is "lutpair2";
  attribute HLUTNM of \ip_hcs_calc_temp1[3]_i_12\ : label is "lutpair1";
  attribute HLUTNM of \ip_hcs_calc_temp1[3]_i_13\ : label is "lutpair0";
  attribute HLUTNM of \ip_hcs_calc_temp1[3]_i_14\ : label is "lutpair3";
  attribute HLUTNM of \ip_hcs_calc_temp1[3]_i_15\ : label is "lutpair2";
  attribute HLUTNM of \ip_hcs_calc_temp1[3]_i_16\ : label is "lutpair1";
  attribute HLUTNM of \ip_hcs_calc_temp1[3]_i_17\ : label is "lutpair0";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[3]_i_18\ : label is "soft_lutpair168";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[7]_i_10\ : label is "soft_lutpair164";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[7]_i_11\ : label is "soft_lutpair165";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[7]_i_15\ : label is "soft_lutpair166";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[7]_i_16\ : label is "soft_lutpair167";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[7]_i_17\ : label is "soft_lutpair164";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[7]_i_18\ : label is "soft_lutpair165";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[7]_i_19\ : label is "soft_lutpair166";
  attribute SOFT_HLUTNM of \ip_hcs_calc_temp1[7]_i_20\ : label is "soft_lutpair167";
  attribute HLUTNM of \ip_hcs_calc_temp1[7]_i_21\ : label is "lutpair37";
  attribute HLUTNM of \ip_hcs_calc_temp1[7]_i_24\ : label is "lutpair38";
  attribute HLUTNM of \ip_hcs_calc_temp1[7]_i_25\ : label is "lutpair37";
  attribute HLUTNM of \ip_hcs_calc_temp1[7]_i_28\ : label is "lutpair15";
  attribute HLUTNM of \ip_hcs_calc_temp1[7]_i_31\ : label is "lutpair16";
  attribute HLUTNM of \ip_hcs_calc_temp1[7]_i_32\ : label is "lutpair15";
  attribute HLUTNM of \ip_hcs_calc_temp1[7]_i_35\ : label is "lutpair26";
  attribute HLUTNM of \ip_hcs_calc_temp1[7]_i_38\ : label is "lutpair27";
  attribute HLUTNM of \ip_hcs_calc_temp1[7]_i_39\ : label is "lutpair26";
  attribute HLUTNM of \ip_hcs_calc_temp2[3]_i_3\ : label is "lutpair50";
  attribute HLUTNM of \ip_hcs_calc_temp2[3]_i_4\ : label is "lutpair49";
  attribute HLUTNM of \ip_hcs_calc_temp2[3]_i_5\ : label is "lutpair48";
  attribute HLUTNM of \ip_hcs_calc_temp2[3]_i_6\ : label is "lutpair51";
  attribute HLUTNM of \ip_hcs_calc_temp2[3]_i_7\ : label is "lutpair50";
  attribute HLUTNM of \ip_hcs_calc_temp2[3]_i_8\ : label is "lutpair49";
  attribute HLUTNM of \ip_hcs_calc_temp2[3]_i_9\ : label is "lutpair48";
  attribute HLUTNM of \ip_hcs_calc_temp2[7]_i_10\ : label is "lutpair52";
  attribute HLUTNM of \ip_hcs_calc_temp2[7]_i_3\ : label is "lutpair54";
  attribute HLUTNM of \ip_hcs_calc_temp2[7]_i_4\ : label is "lutpair53";
  attribute HLUTNM of \ip_hcs_calc_temp2[7]_i_5\ : label is "lutpair52";
  attribute HLUTNM of \ip_hcs_calc_temp2[7]_i_6\ : label is "lutpair51";
  attribute HLUTNM of \ip_hcs_calc_temp2[7]_i_8\ : label is "lutpair54";
  attribute HLUTNM of \ip_hcs_calc_temp2[7]_i_9\ : label is "lutpair53";
  attribute SOFT_HLUTNM of \ip_header_options[3]_i_2\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \ip_header_options[6]_i_2\ : label is "soft_lutpair174";
  attribute SOFT_HLUTNM of \ip_header_options[7]_i_13\ : label is "soft_lutpair203";
  attribute SOFT_HLUTNM of \ip_header_options[7]_i_2\ : label is "soft_lutpair187";
  attribute SOFT_HLUTNM of \ip_header_options[7]_i_4\ : label is "soft_lutpair145";
  attribute SOFT_HLUTNM of \ip_options_count_max[2]_i_1\ : label is "soft_lutpair195";
  attribute SOFT_HLUTNM of \ip_options_count_max[3]_i_1\ : label is "soft_lutpair195";
  attribute SOFT_HLUTNM of \ip_options_count_max[4]_i_1\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \ip_options_count_max[5]_i_2\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of read_eth_header_done_i_3 : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of read_frame_done_i_2 : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of rst_ram_i_4 : label is "soft_lutpair139";
  attribute SOFT_HLUTNM of send_arp_reply_i_1 : label is "soft_lutpair130";
  attribute SOFT_HLUTNM of \sip[0]_i_1\ : label is "soft_lutpair214";
  attribute SOFT_HLUTNM of \sip[1]_i_1\ : label is "soft_lutpair214";
  attribute SOFT_HLUTNM of \source_ip[0]_i_1\ : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of \source_ip[10]_i_1\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \source_ip[11]_i_1\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \source_ip[12]_i_1\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \source_ip[13]_i_1\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \source_ip[14]_i_1\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \source_ip[15]_i_1\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \source_ip[16]_i_1\ : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of \source_ip[17]_i_1\ : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of \source_ip[18]_i_1\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \source_ip[19]_i_1\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \source_ip[1]_i_1\ : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of \source_ip[20]_i_1\ : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \source_ip[21]_i_1\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \source_ip[22]_i_1\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \source_ip[23]_i_1\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \source_ip[24]_i_1\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \source_ip[25]_i_1\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \source_ip[26]_i_1\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \source_ip[27]_i_1\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \source_ip[28]_i_1\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \source_ip[29]_i_1\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \source_ip[2]_i_1\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \source_ip[30]_i_1\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \source_ip[31]_i_2\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \source_ip[3]_i_1\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \source_ip[4]_i_1\ : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \source_ip[5]_i_1\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \source_ip[6]_i_1\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \source_ip[7]_i_1\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \source_ip[8]_i_1\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \source_ip[9]_i_1\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \source_mac[15]_i_3\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \source_mac[23]_i_2\ : label is "soft_lutpair143";
  attribute SOFT_HLUTNM of \source_mac[30]_i_2\ : label is "soft_lutpair182";
  attribute SOFT_HLUTNM of \source_mac[31]_i_2\ : label is "soft_lutpair193";
  attribute SOFT_HLUTNM of \source_mac[31]_i_3\ : label is "soft_lutpair152";
  attribute SOFT_HLUTNM of \source_mac[33]_i_2\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \source_mac[35]_i_2\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \source_mac[37]_i_2\ : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of \source_mac[38]_i_2\ : label is "soft_lutpair183";
  attribute SOFT_HLUTNM of \source_mac[39]_i_2\ : label is "soft_lutpair194";
  attribute SOFT_HLUTNM of \source_mac[39]_i_3\ : label is "soft_lutpair143";
  attribute SOFT_HLUTNM of \source_mac[41]_i_2\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \source_mac[43]_i_2\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \source_mac[45]_i_2\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \source_mac[45]_i_4\ : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of \source_mac[47]_i_4\ : label is "soft_lutpair213";
  attribute SOFT_HLUTNM of \source_mac[7]_i_2\ : label is "soft_lutpair146";
  attribute SOFT_HLUTNM of start_crc_i_5 : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \state[0]_i_3\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of \state[0]_i_4__0\ : label is "soft_lutpair136";
  attribute SOFT_HLUTNM of \state[0]_i_9\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \state[1]_i_2\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \state[1]_i_6\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \state[2]_i_4\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \state[2]_i_6\ : label is "soft_lutpair169";
  attribute SOFT_HLUTNM of \state[2]_i_7\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \state[2]_i_8\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \state[2]_i_9__0\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \state[3]_i_10\ : label is "soft_lutpair137";
  attribute SOFT_HLUTNM of \state[3]_i_14\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \state[3]_i_15\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of \state[3]_i_16\ : label is "soft_lutpair213";
  attribute SOFT_HLUTNM of \state[3]_i_38\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \state[3]_i_6\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \state[3]_i_7\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \state[3]_i_8\ : label is "soft_lutpair17";
  attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
  attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
  attribute ORIG_CELL_NAME of \state_reg[1]_rep__0\ : label is "state_reg[1]";
  attribute ORIG_CELL_NAME of \state_reg[1]_rep__1\ : label is "state_reg[1]";
  attribute SOFT_HLUTNM of stop_crc_i_1 : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of stop_crc_i_2 : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of stop_crc_i_4 : label is "soft_lutpair184";
  attribute SOFT_HLUTNM of \temp_data[4]_i_2\ : label is "soft_lutpair180";
  attribute SOFT_HLUTNM of \temp_data[5]_i_3\ : label is "soft_lutpair191";
  attribute SOFT_HLUTNM of \temp_data[5]_i_4\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \temp_data[6]_i_2\ : label is "soft_lutpair179";
  attribute SOFT_HLUTNM of \temp_data[7]_i_3\ : label is "soft_lutpair170";
  attribute SOFT_HLUTNM of udp_datasum_done_i_1 : label is "soft_lutpair132";
  attribute HLUTNM of \udp_hcs_calc_temp2[3]_i_3\ : label is "lutpair59";
  attribute HLUTNM of \udp_hcs_calc_temp2[3]_i_4\ : label is "lutpair58";
  attribute HLUTNM of \udp_hcs_calc_temp2[3]_i_5\ : label is "lutpair57";
  attribute HLUTNM of \udp_hcs_calc_temp2[3]_i_6\ : label is "lutpair60";
  attribute HLUTNM of \udp_hcs_calc_temp2[3]_i_7\ : label is "lutpair59";
  attribute HLUTNM of \udp_hcs_calc_temp2[3]_i_8\ : label is "lutpair58";
  attribute HLUTNM of \udp_hcs_calc_temp2[3]_i_9\ : label is "lutpair57";
  attribute HLUTNM of \udp_hcs_calc_temp2[7]_i_10\ : label is "lutpair61";
  attribute HLUTNM of \udp_hcs_calc_temp2[7]_i_3\ : label is "lutpair63";
  attribute HLUTNM of \udp_hcs_calc_temp2[7]_i_4\ : label is "lutpair62";
  attribute HLUTNM of \udp_hcs_calc_temp2[7]_i_5\ : label is "lutpair61";
  attribute HLUTNM of \udp_hcs_calc_temp2[7]_i_6\ : label is "lutpair60";
  attribute HLUTNM of \udp_hcs_calc_temp2[7]_i_8\ : label is "lutpair63";
  attribute HLUTNM of \udp_hcs_calc_temp2[7]_i_9\ : label is "lutpair62";
  attribute SOFT_HLUTNM of udp_hcs_done_i_1 : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \udp_presum[11]_i_11\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \udp_presum[11]_i_16\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \udp_presum[11]_i_18\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \udp_presum[11]_i_20\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \udp_presum[11]_i_21\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \udp_presum[11]_i_22\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \udp_presum[11]_i_23\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \udp_presum[11]_i_24\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \udp_presum[15]_i_11\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \udp_presum[15]_i_16\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \udp_presum[15]_i_18\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \udp_presum[15]_i_20\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \udp_presum[15]_i_21\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \udp_presum[15]_i_22\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \udp_presum[15]_i_23\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \udp_presum[15]_i_24\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \udp_presum[19]_i_16\ : label is "soft_lutpair153";
  attribute SOFT_HLUTNM of \udp_presum[19]_i_17\ : label is "soft_lutpair153";
  attribute SOFT_HLUTNM of \udp_presum[19]_i_18\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \udp_presum[19]_i_20\ : label is "soft_lutpair28";
  attribute HLUTNM of \udp_presum[19]_i_30\ : label is "lutpair55";
  attribute HLUTNM of \udp_presum[19]_i_35\ : label is "lutpair55";
  attribute SOFT_HLUTNM of \udp_presum[3]_i_10\ : label is "soft_lutpair155";
  attribute SOFT_HLUTNM of \udp_presum[3]_i_11\ : label is "soft_lutpair155";
  attribute HLUTNM of \udp_presum[3]_i_4\ : label is "lutpair56";
  attribute HLUTNM of \udp_presum[3]_i_9\ : label is "lutpair56";
  attribute SOFT_HLUTNM of \udp_presum[7]_i_15\ : label is "soft_lutpair154";
  attribute SOFT_HLUTNM of \udp_presum[7]_i_16\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \udp_presum[7]_i_17\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \udp_presum[7]_i_21\ : label is "soft_lutpair154";
  attribute SOFT_HLUTNM of udp_presum_done_i_1 : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of unknown_request2_i_4 : label is "soft_lutpair130";
  attribute SOFT_HLUTNM of valid_data_byte_read_i_18 : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of valid_data_byte_read_i_19 : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of valid_data_byte_read_i_20 : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of valid_data_byte_read_i_21 : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of valid_data_byte_read_i_4 : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of we_ram_i_1 : label is "soft_lutpair144";
  attribute SOFT_HLUTNM of \zero_counter[1]_i_1\ : label is "soft_lutpair141";
  attribute SOFT_HLUTNM of \zero_counter[2]_i_1\ : label is "soft_lutpair141";
  attribute SOFT_HLUTNM of \zero_counter[3]_i_1\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \zero_counter[4]_i_3__0\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \zero_counter[4]_i_8\ : label is "soft_lutpair95";
begin
  Q(31 downto 0) <= \^q\(31 downto 0);
  send_arp_reply <= \^send_arp_reply\;
\FSM_onehot_sip[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => eth_protocol_expected,
      I1 => arp_request_expected,
      I2 => \byte_read_done_reg_n_0_[9]\,
      O => ip_hcs_calc_temp1
    );
\FSM_onehot_sip[2]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => eth_protocol_expected,
      I1 => arp_request_expected,
      I2 => \byte_read_done_reg_n_0_[9]\,
      I3 => ip_hcs_done,
      O => edge_count_header1
    );
\FSM_onehot_sip[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => ip_hcs_calc,
      I1 => ip_hcs_calc_temp2,
      O => \FSM_onehot_sip[2]_i_3_n_0\
    );
\FSM_onehot_sip_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_header1,
      D => '0',
      Q => edge_count_header,
      S => ip_hcs_calc_temp1
    );
\FSM_onehot_sip_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_header1,
      D => edge_count_header,
      Q => ip_hcs_calc_temp2,
      R => ip_hcs_calc_temp1
    );
\FSM_onehot_sip_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_header1,
      D => \FSM_onehot_sip[2]_i_3_n_0\,
      Q => ip_hcs_calc,
      R => ip_hcs_calc_temp1
    );
\FSM_onehot_sudp[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8FFF"
    )
        port map (
      I0 => udp_hcs_calc_temp1,
      I1 => udp_hcs_done,
      I2 => udp_presum_done,
      I3 => udp_datasum_done_reg_n_0,
      O => \FSM_onehot_sudp[0]_i_1_n_0\
    );
\FSM_onehot_sudp[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8000000"
    )
        port map (
      I0 => udp_hcs_calc_temp2,
      I1 => udp_hcs_done,
      I2 => udp_hcs_calc_temp1,
      I3 => udp_presum_done,
      I4 => udp_datasum_done_reg_n_0,
      O => \FSM_onehot_sudp[1]_i_1_n_0\
    );
\FSM_onehot_sudp[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BA000000"
    )
        port map (
      I0 => udp_hcs_calc,
      I1 => udp_hcs_done,
      I2 => udp_hcs_calc_temp2,
      I3 => udp_presum_done,
      I4 => udp_datasum_done_reg_n_0,
      O => \FSM_onehot_sudp[2]_i_1_n_0\
    );
\FSM_onehot_sudp_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_sudp[0]_i_1_n_0\,
      Q => udp_hcs_calc_temp1,
      R => '0'
    );
\FSM_onehot_sudp_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_sudp[1]_i_1_n_0\,
      Q => udp_hcs_calc_temp2,
      R => '0'
    );
\FSM_onehot_sudp_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_sudp[2]_i_1_n_0\,
      Q => udp_hcs_calc,
      R => '0'
    );
\FSM_sequential_s_ram[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01010100"
    )
        port map (
      I0 => valid_data_byte_read_reg_n_0,
      I1 => wrt_enable_ram,
      I2 => s_ram(1),
      I3 => rst_ram_reg_n_0,
      I4 => read_frame_done_reg_n_0,
      O => \FSM_sequential_s_ram[1]_i_1_n_0\
    );
\FSM_sequential_s_ram_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \FSM_sequential_s_ram[1]_i_1_n_0\,
      Q => s_ram(1),
      R => '0'
    );
\addr_count[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA00005555AA02"
    )
        port map (
      I0 => wrt_addr_ram(0),
      I1 => rst_ram_reg_n_0,
      I2 => read_frame_done_reg_n_0,
      I3 => valid_data_byte_read_reg_n_0,
      I4 => wrt_enable_ram,
      I5 => s_ram(1),
      O => \addr_count[0]_i_1_n_0\
    );
\addr_count[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6A006A22"
    )
        port map (
      I0 => wrt_addr_ram(1),
      I1 => addr_count,
      I2 => wrt_addr_ram(0),
      I3 => wrt_enable_ram,
      I4 => s_ram(1),
      O => \addr_count[1]_i_1_n_0\
    );
\addr_count[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FF54"
    )
        port map (
      I0 => valid_data_byte_read_reg_n_0,
      I1 => read_frame_done_reg_n_0,
      I2 => rst_ram_reg_n_0,
      I3 => wrt_enable_ram,
      I4 => s_ram(1),
      O => addr_count
    );
\addr_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \addr_count[0]_i_1_n_0\,
      Q => wrt_addr_ram(0),
      R => '0'
    );
\addr_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \addr_count[1]_i_1_n_0\,
      Q => wrt_addr_ram(1),
      R => '0'
    );
arp_request_expected_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => read_eth_header_done,
      I1 => arp_request_expected_i_2_n_0,
      O => arp_request_expected_i_1_n_0
    );
arp_request_expected_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000004000000"
    )
        port map (
      I0 => eth_protocol_expected_i_4_n_0,
      I1 => eth_prot_type(11),
      I2 => eth_prot_type(3),
      I3 => eth_prot_type(1),
      I4 => eth_prot_type(2),
      I5 => eth_protocol_expected_i_2_n_0,
      O => arp_request_expected_i_2_n_0
    );
arp_request_expected_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => arp_request_expected_i_1_n_0,
      Q => arp_request_expected,
      R => '0'
    );
arp_response_pending_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \^send_arp_reply\,
      I1 => sent_arp_response,
      I2 => arp_response_pending,
      O => send_arp_reply_reg_0
    );
\bit_count[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF08FF0000"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \bit_count[1]_i_2_n_0\,
      I3 => \bit_count[1]_i_4_n_0\,
      I4 => \bit_count[1]_i_5_n_0\,
      I5 => \bit_count_reg[0]_rep_n_0\,
      O => \bit_count[0]_i_1_n_0\
    );
\bit_count[0]_rep_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFF08FF0000"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \bit_count[1]_i_2_n_0\,
      I3 => \bit_count[1]_i_4_n_0\,
      I4 => \bit_count[1]_i_5_n_0\,
      I5 => \bit_count_reg[0]_rep_n_0\,
      O => \bit_count[0]_rep_i_1_n_0\
    );
\bit_count[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"004FFFFF4F000000"
    )
        port map (
      I0 => \bit_count[1]_i_2_n_0\,
      I1 => \bit_count[1]_i_3_n_0\,
      I2 => \bit_count[1]_i_4_n_0\,
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => \bit_count[1]_i_5_n_0\,
      I5 => ip_header_options1(2),
      O => \bit_count[1]_i_1_n_0\
    );
\bit_count[1]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF4FFF7FF"
    )
        port map (
      I0 => start_crc277_in,
      I1 => \state_reg_n_0_[0]\,
      I2 => \state_reg[1]_rep_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => bit_count2,
      I5 => \byte_read_done[6]_i_2_n_0\,
      O => \bit_count[1]_i_10_n_0\
    );
\bit_count[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444044440440044"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \byte_read_done[3]_i_3_n_0\,
      I4 => start_crc277_in,
      I5 => bit_count2,
      O => \bit_count[1]_i_11_n_0\
    );
\bit_count[1]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFDFDFFFDFDFDFDF"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg[1]_rep_n_0\,
      I3 => \bytes03[13]_i_5_n_0\,
      I4 => \bit_count[1]_i_15_n_0\,
      I5 => \state[3]_i_8_n_0\,
      O => \bit_count[1]_i_12_n_0\
    );
\bit_count[1]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[3]\,
      O => \bit_count[1]_i_13_n_0\
    );
\bit_count[1]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000022200000000"
    )
        port map (
      I0 => \byte_read_done[6]_i_2_n_0\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_read_done[12]_i_5_n_0\,
      I5 => \byte_count_reg_n_0_[4]\,
      O => \bit_count[1]_i_14_n_0\
    );
\bit_count[1]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555555575557555D"
    )
        port map (
      I0 => \byte_read_done[3]_i_6_n_0\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_read_done[12]_i_5_n_0\,
      I4 => \byte_count_reg_n_0_[2]\,
      I5 => \byte_count_reg_n_0_[1]\,
      O => \bit_count[1]_i_15_n_0\
    );
\bit_count[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8BBB8B8B8BBB8BBB"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \bit_count[1]_i_6_n_0\,
      I4 => \bit_count[1]_i_7_n_0\,
      I5 => \bit_count[1]_i_8_n_0\,
      O => \bit_count[1]_i_2_n_0\
    );
\bit_count[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \state_reg_n_0_[0]\,
      O => \bit_count[1]_i_3_n_0\
    );
\bit_count[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F700F7F7"
    )
        port map (
      I0 => \bit_count[1]_i_9_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \bit_count[1]_i_10_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      O => \bit_count[1]_i_4_n_0\
    );
\bit_count[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8A8A8AAAAAAAAAA"
    )
        port map (
      I0 => \byte_count[10]_i_11_n_0\,
      I1 => \bit_count[1]_i_11_n_0\,
      I2 => \state[3]_i_4_n_0\,
      I3 => \state[3]_i_10_n_0\,
      I4 => \state_reg_n_0_[2]\,
      I5 => \bit_count[1]_i_12_n_0\,
      O => \bit_count[1]_i_5_n_0\
    );
\bit_count[1]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"007F007F00FF007F"
    )
        port map (
      I0 => \state[2]_i_9__0_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \byte_read_done[3]_i_6_n_0\,
      I3 => \byte_read_done[6]_i_2_n_0\,
      I4 => \bit_count[1]_i_13_n_0\,
      I5 => \dest_mac[39]_i_4_n_0\,
      O => \bit_count[1]_i_6_n_0\
    );
\bit_count[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \bytes04[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_2_n_0\,
      I2 => \byte_read_done[2]_i_2_n_0\,
      I3 => \bytes05[15]_i_2_n_0\,
      I4 => \bit_count[1]_i_14_n_0\,
      I5 => \state[0]_i_11_n_0\,
      O => \bit_count[1]_i_7_n_0\
    );
\bit_count[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0101050404040C04"
    )
        port map (
      I0 => \byte_read_done[6]_i_2_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_read_done[12]_i_5_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg_n_0_[2]\,
      I5 => \byte_count_reg_n_0_[3]\,
      O => \bit_count[1]_i_8_n_0\
    );
\bit_count[1]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"202000002020FF00"
    )
        port map (
      I0 => start_crc2,
      I1 => \byte_read_done[6]_i_2_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => start_crc_i_2_n_0,
      I4 => \state_reg_n_0_[2]\,
      I5 => \byte_count[10]_i_17_n_0\,
      O => \bit_count[1]_i_9_n_0\
    );
\bit_count[1]_rep_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"004FFFFF4F000000"
    )
        port map (
      I0 => \bit_count[1]_i_2_n_0\,
      I1 => \bit_count[1]_i_3_n_0\,
      I2 => \bit_count[1]_i_4_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count[1]_i_5_n_0\,
      I5 => ip_header_options1(2),
      O => \bit_count[1]_rep_i_1_n_0\
    );
\bit_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bit_count[0]_i_1_n_0\,
      Q => ip_header_options1(1),
      R => '0'
    );
\bit_count_reg[0]_rep\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bit_count[0]_rep_i_1_n_0\,
      Q => \bit_count_reg[0]_rep_n_0\,
      R => '0'
    );
\bit_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bit_count[1]_i_1_n_0\,
      Q => ip_header_options1(2),
      R => '0'
    );
\bit_count_reg[1]_rep\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bit_count[1]_rep_i_1_n_0\,
      Q => \bit_count_reg[1]_rep_n_0\,
      R => '0'
    );
\byte_count[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FFEFEFEF00"
    )
        port map (
      I0 => \byte_count[0]_i_2_n_0\,
      I1 => \byte_count[0]_i_3_n_0\,
      I2 => \byte_count[1]_i_3_n_0\,
      I3 => \byte_count[10]_i_9_n_0\,
      I4 => \byte_count[1]_i_4_n_0\,
      I5 => \byte_count_reg_n_0_[0]\,
      O => \byte_count[0]_i_1_n_0\
    );
\byte_count[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0404440400004000"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \byte_read_done[3]_i_3_n_0\,
      I4 => start_crc024_in,
      I5 => start_crc_i_2_n_0,
      O => \byte_count[0]_i_2_n_0\
    );
\byte_count[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \byte_read_done[3]_i_3_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \state_reg_n_0_[0]\,
      I4 => start_crc1,
      O => \byte_count[0]_i_3_n_0\
    );
\byte_count[0]_rep_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FFEFEFEF00"
    )
        port map (
      I0 => \byte_count[0]_i_2_n_0\,
      I1 => \byte_count[0]_i_3_n_0\,
      I2 => \byte_count[1]_i_3_n_0\,
      I3 => \byte_count[10]_i_9_n_0\,
      I4 => \byte_count[1]_i_4_n_0\,
      I5 => \byte_count_reg_n_0_[0]\,
      O => \byte_count[0]_rep_i_1_n_0\
    );
\byte_count[0]_rep_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FFEFEFEF00"
    )
        port map (
      I0 => \byte_count[0]_i_2_n_0\,
      I1 => \byte_count[0]_i_3_n_0\,
      I2 => \byte_count[1]_i_3_n_0\,
      I3 => \byte_count[10]_i_9_n_0\,
      I4 => \byte_count[1]_i_4_n_0\,
      I5 => \byte_count_reg_n_0_[0]\,
      O => \byte_count[0]_rep_i_1__0_n_0\
    );
\byte_count[0]_rep_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000FFEFEFEF00"
    )
        port map (
      I0 => \byte_count[0]_i_2_n_0\,
      I1 => \byte_count[0]_i_3_n_0\,
      I2 => \byte_count[1]_i_3_n_0\,
      I3 => \byte_count[10]_i_9_n_0\,
      I4 => \byte_count[1]_i_4_n_0\,
      I5 => \byte_count_reg_n_0_[0]\,
      O => \byte_count[0]_rep_i_1__1_n_0\
    );
\byte_count[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA88880080"
    )
        port map (
      I0 => \byte_count[10]_i_4_n_0\,
      I1 => \byte_count[10]_i_5_n_0\,
      I2 => \byte_count[10]_i_6_n_0\,
      I3 => \byte_count[10]_i_7_n_0\,
      I4 => \byte_count[10]_i_8_n_0\,
      I5 => \byte_count[10]_i_9_n_0\,
      O => \byte_count[10]_i_1_n_0\
    );
\byte_count[10]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B000A0A0BBBBAAAA"
    )
        port map (
      I0 => \byte_count[10]_i_20_n_0\,
      I1 => \state[3]_i_7_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \byte_count[10]_i_18_n_0\,
      I4 => \state_reg_n_0_[0]\,
      I5 => \state[1]_i_6_n_0\,
      O => \byte_count[10]_i_10_n_0\
    );
\byte_count[10]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \state_reg_n_0_[3]\,
      O => \byte_count[10]_i_11_n_0\
    );
\byte_count[10]_i_12__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \byte_count_reg_n_0_[4]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg[0]_rep__1_n_0\,
      I5 => \byte_count_reg_n_0_[5]\,
      O => \byte_count[10]_i_12__0_n_0\
    );
\byte_count[10]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0220232002202020"
    )
        port map (
      I0 => \byte_read_done[6]_i_2_n_0\,
      I1 => \byte_read_done[12]_i_5_n_0\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[2]\,
      I5 => \byte_count_reg_n_0_[1]\,
      O => \byte_count[10]_i_13_n_0\
    );
\byte_count[10]_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => \byte_read_done[5]_i_2_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      O => \byte_count[10]_i_14_n_0\
    );
\byte_count[10]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00010000FFFFFFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_read_done[12]_i_5_n_0\,
      I3 => \byte_count_reg_n_0_[4]\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => \byte_read_done[3]_i_6_n_0\,
      O => \byte_count[10]_i_15_n_0\
    );
\byte_count[10]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAEAAAEAAAA"
    )
        port map (
      I0 => \byte_read_done[3]_i_2_n_0\,
      I1 => \byte_read_done[6]_i_2_n_0\,
      I2 => \source_mac[47]_i_4_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg_n_0_[2]\,
      I5 => \byte_count_reg_n_0_[3]\,
      O => \byte_count[10]_i_16_n_0\
    );
\byte_count[10]_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEEEEEEE"
    )
        port map (
      I0 => \byte_read_done[12]_i_5_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[1]\,
      O => \byte_count[10]_i_17_n_0\
    );
\byte_count[10]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => start_crc277_in,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      O => \byte_count[10]_i_18_n_0\
    );
\byte_count[10]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFAFAF3F00"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => start_crc2,
      I2 => \byte_read_done[6]_i_2_n_0\,
      I3 => \byte_read_done[3]_i_3_n_0\,
      I4 => \state_reg_n_0_[0]\,
      I5 => \byte_count[10]_i_21_n_0\,
      O => \byte_count[10]_i_19_n_0\
    );
\byte_count[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55550000DFDD0000"
    )
        port map (
      I0 => \byte_count[10]_i_10_n_0\,
      I1 => \byte_count[10]_i_8_n_0\,
      I2 => \byte_count[10]_i_7_n_0\,
      I3 => \byte_count[10]_i_6_n_0\,
      I4 => \byte_count[10]_i_11_n_0\,
      I5 => \state_reg_n_0_[2]\,
      O => byte_count0
    );
\byte_count[10]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"77777F777F777F77"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \byte_read_done[3]_i_3_n_0\,
      I4 => \byte_read_done[6]_i_2_n_0\,
      I5 => start_crc2,
      O => \byte_count[10]_i_20_n_0\
    );
\byte_count[10]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \state_reg_n_0_[2]\,
      O => \byte_count[10]_i_21_n_0\
    );
\byte_count[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[10]\,
      I1 => \byte_count_reg_n_0_[8]\,
      I2 => \byte_count_reg_n_0_[9]\,
      I3 => \byte_count[10]_i_12__0_n_0\,
      I4 => \byte_count_reg_n_0_[7]\,
      I5 => \byte_count_reg_n_0_[6]\,
      O => \byte_count[10]_i_3_n_0\
    );
\byte_count[10]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAEAAA"
    )
        port map (
      I0 => \byte_count[1]_i_3_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_read_done[3]_i_4_n_0\,
      I5 => \byte_count[1]_i_2_n_0\,
      O => \byte_count[10]_i_4_n_0\
    );
\byte_count[10]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \byte_count[10]_i_11_n_0\,
      I1 => \state_reg_n_0_[2]\,
      O => \byte_count[10]_i_5_n_0\
    );
\byte_count[10]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFDDDDDDFD"
    )
        port map (
      I0 => valid_data_byte_read_i_3_n_0,
      I1 => \state[3]_i_7_n_0\,
      I2 => \byte_count[10]_i_13_n_0\,
      I3 => \byte_count[10]_i_14_n_0\,
      I4 => \byte_count[10]_i_15_n_0\,
      I5 => \byte_count[10]_i_16_n_0\,
      O => \byte_count[10]_i_6_n_0\
    );
\byte_count[10]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000F700FFFFFFFF"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \byte_count[10]_i_17_n_0\,
      I3 => start_crc_i_2_n_0,
      I4 => \state_reg_n_0_[0]\,
      I5 => \state_reg[1]_rep_n_0\,
      O => \byte_count[10]_i_7_n_0\
    );
\byte_count[10]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"07"
    )
        port map (
      I0 => start_crc_i_2_n_0,
      I1 => \state_reg_n_0_[0]\,
      I2 => \state_reg[1]_rep_n_0\,
      O => \byte_count[10]_i_8_n_0\
    );
\byte_count[10]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00808888AAAAAAAA"
    )
        port map (
      I0 => \byte_count[10]_i_11_n_0\,
      I1 => \state[1]_i_6_n_0\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \byte_count[10]_i_18_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => \byte_count[10]_i_19_n_0\,
      O => \byte_count[10]_i_9_n_0\
    );
\byte_count[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"454545FF8A8A8A00"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \byte_count[1]_i_2_n_0\,
      I2 => \byte_count[1]_i_3_n_0\,
      I3 => \byte_count[10]_i_9_n_0\,
      I4 => \byte_count[1]_i_4_n_0\,
      I5 => \byte_count_reg[1]_rep_n_0\,
      O => \byte_count[1]_i_1_n_0\
    );
\byte_count[1]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6AAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[10]\,
      I1 => \byte_count_reg_n_0_[8]\,
      I2 => \byte_count_reg_n_0_[9]\,
      I3 => \byte_count[1]_i_22_n_0\,
      I4 => \state[0]_i_9_n_0\,
      O => \byte_count[1]_i_10_n_0\
    );
\byte_count[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFFFF80"
    )
        port map (
      I0 => \byte_count_reg_n_0_[6]\,
      I1 => \byte_count_reg_n_0_[7]\,
      I2 => \byte_count[10]_i_12__0_n_0\,
      I3 => \byte_count_reg_n_0_[9]\,
      I4 => \byte_count_reg_n_0_[8]\,
      I5 => \state[0]_i_9_n_0\,
      O => \byte_count[1]_i_11_n_0\
    );
\byte_count[1]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40001555"
    )
        port map (
      I0 => \state[0]_i_9_n_0\,
      I1 => \byte_count[1]_i_22_n_0\,
      I2 => \byte_count_reg_n_0_[9]\,
      I3 => \byte_count_reg_n_0_[8]\,
      I4 => \byte_count_reg_n_0_[10]\,
      O => \byte_count[1]_i_12_n_0\
    );
\byte_count[1]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2888888881111111"
    )
        port map (
      I0 => \byte_count_reg_n_0_[9]\,
      I1 => \byte_count_reg_n_0_[8]\,
      I2 => \byte_count_reg_n_0_[6]\,
      I3 => \byte_count_reg_n_0_[7]\,
      I4 => \byte_count[10]_i_12__0_n_0\,
      I5 => \state[0]_i_9_n_0\,
      O => \byte_count[1]_i_13_n_0\
    );
\byte_count[1]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"007E"
    )
        port map (
      I0 => \byte_count_reg_n_0_[7]\,
      I1 => \byte_count_reg_n_0_[6]\,
      I2 => \byte_count[10]_i_12__0_n_0\,
      I3 => \state[0]_i_9_n_0\,
      O => \byte_count[1]_i_14_n_0\
    );
\byte_count[1]_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7E6A007E"
    )
        port map (
      I0 => \byte_count_reg_n_0_[5]\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_read_done[7]_i_4_n_0\,
      I3 => \byte_count[1]_i_23_n_0\,
      I4 => \zero_counter_reg_n_0_[4]\,
      O => \byte_count[1]_i_15_n_0\
    );
\byte_count[1]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00007F8078007FF8"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg[0]_rep__1_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count[1]_i_24_n_0\,
      I5 => \byte_count[1]_i_25_n_0\,
      O => \byte_count[1]_i_16_n_0\
    );
\byte_count[1]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"12D8"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \zero_counter_reg_n_0_[0]\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      O => \byte_count[1]_i_17_n_0\
    );
\byte_count[1]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2881"
    )
        port map (
      I0 => \byte_count_reg_n_0_[7]\,
      I1 => \byte_count_reg_n_0_[6]\,
      I2 => \byte_count[10]_i_12__0_n_0\,
      I3 => \state[0]_i_9_n_0\,
      O => \byte_count[1]_i_18_n_0\
    );
\byte_count[1]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"60090990"
    )
        port map (
      I0 => \byte_count_reg_n_0_[5]\,
      I1 => \state[0]_i_9_n_0\,
      I2 => \state[3]_i_38_n_0\,
      I3 => \byte_count_reg_n_0_[4]\,
      I4 => \byte_read_done[7]_i_4_n_0\,
      O => \byte_count[1]_i_19_n_0\
    );
\byte_count[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBBFB0000"
    )
        port map (
      I0 => \byte_count[1]_i_5_n_0\,
      I1 => \byte_count_reg[0]_rep__0_n_0\,
      I2 => \state[2]_i_5__0_n_0\,
      I3 => start_crc024_in,
      I4 => \byte_count[0]_i_2_n_0\,
      I5 => \byte_count[0]_i_3_n_0\,
      O => \byte_count[1]_i_2_n_0\
    );
\byte_count[1]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0690900990099009"
    )
        port map (
      I0 => \byte_count[1]_i_24_n_0\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count[1]_i_25_n_0\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \byte_count_reg[0]_rep__1_n_0\,
      O => \byte_count[1]_i_20_n_0\
    );
\byte_count[1]_i_21\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6006"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \zero_counter_reg_n_0_[0]\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      O => \byte_count[1]_i_21_n_0\
    );
\byte_count[1]_i_22\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \byte_count[10]_i_12__0_n_0\,
      I1 => \byte_count_reg_n_0_[7]\,
      I2 => \byte_count_reg_n_0_[6]\,
      O => \byte_count[1]_i_22_n_0\
    );
\byte_count[1]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[2]\,
      I1 => \zero_counter_reg_n_0_[0]\,
      I2 => \zero_counter_reg_n_0_[1]\,
      I3 => \zero_counter_reg_n_0_[3]\,
      O => \byte_count[1]_i_23_n_0\
    );
\byte_count[1]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[3]\,
      I1 => \zero_counter_reg_n_0_[2]\,
      I2 => \zero_counter_reg_n_0_[0]\,
      I3 => \zero_counter_reg_n_0_[1]\,
      O => \byte_count[1]_i_24_n_0\
    );
\byte_count[1]_i_25\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[2]\,
      I1 => \zero_counter_reg_n_0_[1]\,
      I2 => \zero_counter_reg_n_0_[0]\,
      O => \byte_count[1]_i_25_n_0\
    );
\byte_count[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0075FFFFFFFFFFFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_3_n_0\,
      I1 => \byte_count[1]_i_7_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \state_reg_n_0_[0]\,
      I5 => \state_reg[1]_rep_n_0\,
      O => \byte_count[1]_i_3_n_0\
    );
\byte_count[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA0000A8AA"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \byte_count[1]_i_8_n_0\,
      I2 => \state[3]_i_7_n_0\,
      I3 => valid_data_byte_read_i_3_n_0,
      I4 => \byte_count[10]_i_7_n_0\,
      I5 => \byte_count[10]_i_8_n_0\,
      O => \byte_count[1]_i_4_n_0\
    );
\byte_count[1]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFBF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[4]\,
      I4 => \byte_read_done[12]_i_5_n_0\,
      O => \byte_count[1]_i_5_n_0\
    );
\byte_count[1]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFBFFFFF"
    )
        port map (
      I0 => \byte_read_done[12]_i_5_n_0\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[1]\,
      O => \byte_count[1]_i_7_n_0\
    );
\byte_count[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFAAFFEABFAABFAA"
    )
        port map (
      I0 => \byte_read_done[2]_i_2_n_0\,
      I1 => \byte_read_done[3]_i_6_n_0\,
      I2 => \state[2]_i_9__0_n_0\,
      I3 => \byte_read_done[6]_i_2_n_0\,
      I4 => \byte_read_done[5]_i_2_n_0\,
      I5 => \byte_count[10]_i_13_n_0\,
      O => \byte_count[1]_i_8_n_0\
    );
\byte_count[1]_rep_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"454545FF8A8A8A00"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \byte_count[1]_i_2_n_0\,
      I2 => \byte_count[1]_i_3_n_0\,
      I3 => \byte_count[10]_i_9_n_0\,
      I4 => \byte_count[1]_i_4_n_0\,
      I5 => \byte_count_reg[1]_rep_n_0\,
      O => \byte_count[1]_rep_i_1_n_0\
    );
\byte_count[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      O => \byte_count[2]_i_1_n_0\
    );
\byte_count[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      O => \byte_count[3]_i_1_n_0\
    );
\byte_count[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[4]\,
      I1 => \byte_count_reg[0]_rep__1_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[3]\,
      O => \byte_count[4]_i_1_n_0\
    );
\byte_count[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[5]\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \byte_count_reg[0]_rep__1_n_0\,
      O => \byte_count[5]_i_1_n_0\
    );
\byte_count[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[6]\,
      I1 => \byte_count_reg_n_0_[5]\,
      I2 => \state[3]_i_6_n_0\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => \byte_count_reg_n_0_[4]\,
      O => \byte_count[6]_i_1_n_0\
    );
\byte_count[7]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \byte_count_reg_n_0_[7]\,
      I1 => \byte_count[10]_i_12__0_n_0\,
      I2 => \byte_count_reg_n_0_[6]\,
      O => \byte_count[7]_i_1__0_n_0\
    );
\byte_count[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => \byte_count[10]_i_12__0_n_0\,
      I1 => \byte_count_reg_n_0_[7]\,
      I2 => \byte_count_reg_n_0_[6]\,
      I3 => \byte_count_reg_n_0_[8]\,
      O => \byte_count[8]_i_1_n_0\
    );
\byte_count[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => \byte_count_reg_n_0_[6]\,
      I1 => \byte_count_reg_n_0_[7]\,
      I2 => \byte_count[10]_i_12__0_n_0\,
      I3 => \byte_count_reg_n_0_[8]\,
      I4 => \byte_count_reg_n_0_[9]\,
      O => \byte_count[9]_i_1_n_0\
    );
\byte_count_extra[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \byte_count_extra_reg_n_0_[0]\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \byte_count_extra_reg[5]_i_4_n_0\,
      O => \byte_count_extra[0]_i_1_n_0\
    );
\byte_count_extra[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6000"
    )
        port map (
      I0 => \byte_count_extra_reg_n_0_[1]\,
      I1 => \byte_count_extra_reg_n_0_[0]\,
      I2 => \byte_count_extra_reg[5]_i_4_n_0\,
      I3 => \state_reg_n_0_[2]\,
      O => \byte_count_extra[1]_i_1_n_0\
    );
\byte_count_extra[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08808080"
    )
        port map (
      I0 => \byte_count_extra_reg[5]_i_4_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \byte_count_extra_reg_n_0_[2]\,
      I3 => \byte_count_extra_reg_n_0_[1]\,
      I4 => \byte_count_extra_reg_n_0_[0]\,
      O => \byte_count_extra[2]_i_1_n_0\
    );
\byte_count_extra[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880808080808080"
    )
        port map (
      I0 => \byte_count_extra_reg[5]_i_4_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \byte_count_extra_reg_n_0_[3]\,
      I3 => \byte_count_extra_reg_n_0_[0]\,
      I4 => \byte_count_extra_reg_n_0_[1]\,
      I5 => \byte_count_extra_reg_n_0_[2]\,
      O => \byte_count_extra[3]_i_1_n_0\
    );
\byte_count_extra[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880808080808080"
    )
        port map (
      I0 => \byte_count_extra_reg[5]_i_4_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \byte_count_extra_reg_n_0_[4]\,
      I3 => \byte_count_extra_reg_n_0_[2]\,
      I4 => \byte_count_extra[4]_i_2_n_0\,
      I5 => \byte_count_extra_reg_n_0_[3]\,
      O => \byte_count_extra[4]_i_1_n_0\
    );
\byte_count_extra[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \byte_count_extra_reg_n_0_[1]\,
      I1 => \byte_count_extra_reg_n_0_[0]\,
      O => \byte_count_extra[4]_i_2_n_0\
    );
\byte_count_extra[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \byte_count_extra[5]_i_3_n_0\,
      O => byte_count_extra0
    );
\byte_count_extra[5]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4147"
    )
        port map (
      I0 => \byte_count_extra_reg_n_0_[3]\,
      I1 => ip_options_count_max(3),
      I2 => ip_options_count_max(2),
      I3 => \byte_count_extra_reg_n_0_[2]\,
      O => \byte_count_extra[5]_i_10_n_0\
    );
\byte_count_extra[5]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \byte_count_extra_reg_n_0_[0]\,
      I1 => \byte_count_extra_reg_n_0_[1]\,
      O => \byte_count_extra[5]_i_11_n_0\
    );
\byte_count_extra[5]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => ip_options_count_max(5),
      I1 => ip_options_count_max(4),
      I2 => ip_options_count_max(3),
      I3 => ip_options_count_max(2),
      O => \byte_count_extra[5]_i_12_n_0\
    );
\byte_count_extra[5]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9090900609090990"
    )
        port map (
      I0 => ip_options_count_max(5),
      I1 => \byte_count_extra_reg_n_0_[5]\,
      I2 => ip_options_count_max(4),
      I3 => ip_options_count_max(3),
      I4 => ip_options_count_max(2),
      I5 => \byte_count_extra_reg_n_0_[4]\,
      O => \byte_count_extra[5]_i_13_n_0\
    );
\byte_count_extra[5]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0690"
    )
        port map (
      I0 => ip_options_count_max(3),
      I1 => \byte_count_extra_reg_n_0_[3]\,
      I2 => ip_options_count_max(2),
      I3 => \byte_count_extra_reg_n_0_[2]\,
      O => \byte_count_extra[5]_i_14_n_0\
    );
\byte_count_extra[5]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \byte_count_extra_reg_n_0_[1]\,
      I1 => \byte_count_extra_reg_n_0_[0]\,
      O => \byte_count_extra[5]_i_15_n_0\
    );
\byte_count_extra[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08808080"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \byte_count_extra_reg[5]_i_4_n_0\,
      I2 => \byte_count_extra_reg_n_0_[5]\,
      I3 => \byte_count_extra_reg_n_0_[4]\,
      I4 => \byte_count_extra[5]_i_5_n_0\,
      O => \byte_count_extra[5]_i_2_n_0\
    );
\byte_count_extra[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDF0000FFDFFFDF"
    )
        port map (
      I0 => \byte_count_extra[5]_i_6_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \byte_read_done[6]_i_2_n_0\,
      I3 => \state[3]_i_13_n_0\,
      I4 => \byte_count_extra[5]_i_7_n_0\,
      I5 => \byte_count_extra[5]_i_8_n_0\,
      O => \byte_count_extra[5]_i_3_n_0\
    );
\byte_count_extra[5]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \byte_count_extra_reg_n_0_[2]\,
      I1 => \byte_count_extra_reg_n_0_[1]\,
      I2 => \byte_count_extra_reg_n_0_[0]\,
      I3 => \byte_count_extra_reg_n_0_[3]\,
      O => \byte_count_extra[5]_i_5_n_0\
    );
\byte_count_extra[5]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \byte_read_done[3]_i_3_n_0\,
      I2 => \state_reg[1]_rep__1_n_0\,
      O => \byte_count_extra[5]_i_6_n_0\
    );
\byte_count_extra[5]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFABFF"
    )
        port map (
      I0 => \state[3]_i_15_n_0\,
      I1 => \byte_read_done[3]_i_6_n_0\,
      I2 => \byte_read_done[6]_i_2_n_0\,
      I3 => \bytes03[7]_i_3_n_0\,
      I4 => \source_mac[47]_i_4_n_0\,
      I5 => \byte_read_done[1]_i_4_n_0\,
      O => \byte_count_extra[5]_i_7_n_0\
    );
\byte_count_extra[5]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \state[2]_i_9__0_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => ip_extra_options,
      I4 => \dest_mac[12]_i_4_n_0\,
      O => \byte_count_extra[5]_i_8_n_0\
    );
\byte_count_extra[5]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55540001DDD54443"
    )
        port map (
      I0 => \byte_count_extra_reg_n_0_[5]\,
      I1 => ip_options_count_max(4),
      I2 => ip_options_count_max(3),
      I3 => ip_options_count_max(2),
      I4 => ip_options_count_max(5),
      I5 => \byte_count_extra_reg_n_0_[4]\,
      O => \byte_count_extra[5]_i_9_n_0\
    );
\byte_count_extra_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count_extra0,
      D => \byte_count_extra[0]_i_1_n_0\,
      Q => \byte_count_extra_reg_n_0_[0]\,
      R => '0'
    );
\byte_count_extra_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count_extra0,
      D => \byte_count_extra[1]_i_1_n_0\,
      Q => \byte_count_extra_reg_n_0_[1]\,
      R => '0'
    );
\byte_count_extra_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count_extra0,
      D => \byte_count_extra[2]_i_1_n_0\,
      Q => \byte_count_extra_reg_n_0_[2]\,
      R => '0'
    );
\byte_count_extra_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count_extra0,
      D => \byte_count_extra[3]_i_1_n_0\,
      Q => \byte_count_extra_reg_n_0_[3]\,
      R => '0'
    );
\byte_count_extra_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count_extra0,
      D => \byte_count_extra[4]_i_1_n_0\,
      Q => \byte_count_extra_reg_n_0_[4]\,
      R => '0'
    );
\byte_count_extra_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count_extra0,
      D => \byte_count_extra[5]_i_2_n_0\,
      Q => \byte_count_extra_reg_n_0_[5]\,
      R => '0'
    );
\byte_count_extra_reg[5]_i_4\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \byte_count_extra_reg[5]_i_4_n_0\,
      CO(2) => \byte_count_extra_reg[5]_i_4_n_1\,
      CO(1) => \byte_count_extra_reg[5]_i_4_n_2\,
      CO(0) => \byte_count_extra_reg[5]_i_4_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => \byte_count_extra[5]_i_9_n_0\,
      DI(1) => \byte_count_extra[5]_i_10_n_0\,
      DI(0) => \byte_count_extra[5]_i_11_n_0\,
      O(3 downto 0) => \NLW_byte_count_extra_reg[5]_i_4_O_UNCONNECTED\(3 downto 0),
      S(3) => \byte_count_extra[5]_i_12_n_0\,
      S(2) => \byte_count_extra[5]_i_13_n_0\,
      S(1) => \byte_count_extra[5]_i_14_n_0\,
      S(0) => \byte_count_extra[5]_i_15_n_0\
    );
\byte_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_count[0]_i_1_n_0\,
      Q => \byte_count_reg_n_0_[0]\,
      R => '0'
    );
\byte_count_reg[0]_rep\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_count[0]_rep_i_1_n_0\,
      Q => \byte_count_reg[0]_rep_n_0\,
      R => '0'
    );
\byte_count_reg[0]_rep__0\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_count[0]_rep_i_1__0_n_0\,
      Q => \byte_count_reg[0]_rep__0_n_0\,
      R => '0'
    );
\byte_count_reg[0]_rep__1\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_count[0]_rep_i_1__1_n_0\,
      Q => \byte_count_reg[0]_rep__1_n_0\,
      R => '0'
    );
\byte_count_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count0,
      D => \byte_count[10]_i_3_n_0\,
      Q => \byte_count_reg_n_0_[10]\,
      R => \byte_count[10]_i_1_n_0\
    );
\byte_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_count[1]_i_1_n_0\,
      Q => \byte_count_reg_n_0_[1]\,
      R => '0'
    );
\byte_count_reg[1]_i_6\: unisim.vcomponents.CARRY4
     port map (
      CI => \byte_count_reg[1]_i_9_n_0\,
      CO(3 downto 2) => \NLW_byte_count_reg[1]_i_6_CO_UNCONNECTED\(3 downto 2),
      CO(1) => start_crc024_in,
      CO(0) => \byte_count_reg[1]_i_6_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \byte_count[1]_i_10_n_0\,
      DI(0) => \byte_count[1]_i_11_n_0\,
      O(3 downto 0) => \NLW_byte_count_reg[1]_i_6_O_UNCONNECTED\(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => \byte_count[1]_i_12_n_0\,
      S(0) => \byte_count[1]_i_13_n_0\
    );
\byte_count_reg[1]_i_9\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \byte_count_reg[1]_i_9_n_0\,
      CO(2) => \byte_count_reg[1]_i_9_n_1\,
      CO(1) => \byte_count_reg[1]_i_9_n_2\,
      CO(0) => \byte_count_reg[1]_i_9_n_3\,
      CYINIT => '0',
      DI(3) => \byte_count[1]_i_14_n_0\,
      DI(2) => \byte_count[1]_i_15_n_0\,
      DI(1) => \byte_count[1]_i_16_n_0\,
      DI(0) => \byte_count[1]_i_17_n_0\,
      O(3 downto 0) => \NLW_byte_count_reg[1]_i_9_O_UNCONNECTED\(3 downto 0),
      S(3) => \byte_count[1]_i_18_n_0\,
      S(2) => \byte_count[1]_i_19_n_0\,
      S(1) => \byte_count[1]_i_20_n_0\,
      S(0) => \byte_count[1]_i_21_n_0\
    );
\byte_count_reg[1]_rep\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_count[1]_rep_i_1_n_0\,
      Q => \byte_count_reg[1]_rep_n_0\,
      R => '0'
    );
\byte_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count0,
      D => \byte_count[2]_i_1_n_0\,
      Q => \byte_count_reg_n_0_[2]\,
      R => \byte_count[10]_i_1_n_0\
    );
\byte_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count0,
      D => \byte_count[3]_i_1_n_0\,
      Q => \byte_count_reg_n_0_[3]\,
      R => \byte_count[10]_i_1_n_0\
    );
\byte_count_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count0,
      D => \byte_count[4]_i_1_n_0\,
      Q => \byte_count_reg_n_0_[4]\,
      R => \byte_count[10]_i_1_n_0\
    );
\byte_count_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count0,
      D => \byte_count[5]_i_1_n_0\,
      Q => \byte_count_reg_n_0_[5]\,
      R => \byte_count[10]_i_1_n_0\
    );
\byte_count_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count0,
      D => \byte_count[6]_i_1_n_0\,
      Q => \byte_count_reg_n_0_[6]\,
      R => \byte_count[10]_i_1_n_0\
    );
\byte_count_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count0,
      D => \byte_count[7]_i_1__0_n_0\,
      Q => \byte_count_reg_n_0_[7]\,
      R => \byte_count[10]_i_1_n_0\
    );
\byte_count_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count0,
      D => \byte_count[8]_i_1_n_0\,
      Q => \byte_count_reg_n_0_[8]\,
      R => \byte_count[10]_i_1_n_0\
    );
\byte_count_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => byte_count0,
      D => \byte_count[9]_i_1_n_0\,
      Q => \byte_count_reg_n_0_[9]\,
      R => \byte_count[10]_i_1_n_0\
    );
\byte_read_done[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \byte_read_done[3]_i_3_n_0\,
      I1 => \byte_read_done[0]_i_2_n_0\,
      I2 => \state[3]_i_7_n_0\,
      I3 => \byte_read_done[11]_i_3_n_0\,
      I4 => \byte_read_done[0]_i_3_n_0\,
      I5 => \byte_read_done_reg_n_0_[0]\,
      O => \byte_read_done[0]_i_1_n_0\
    );
\byte_read_done[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      O => \byte_read_done[0]_i_2_n_0\
    );
\byte_read_done[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \byte_read_done[0]_i_4_n_0\,
      O => \byte_read_done[0]_i_3_n_0\
    );
\byte_read_done[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAA2AAAAAAAAA"
    )
        port map (
      I0 => \byte_read_done[13]_i_5_n_0\,
      I1 => \bytes03[7]_i_3_n_0\,
      I2 => \byte_read_done[6]_i_2_n_0\,
      I3 => \byte_count_reg[1]_rep_n_0\,
      I4 => \byte_read_done[3]_i_4_n_0\,
      I5 => \byte_read_done[3]_i_3_n_0\,
      O => \byte_read_done[0]_i_4_n_0\
    );
\byte_read_done[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => \byte_read_done[10]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \byte_read_done[12]_i_3_n_0\,
      I4 => \byte_read_done[10]_i_3_n_0\,
      I5 => \byte_read_done_reg_n_0_[10]\,
      O => \byte_read_done[10]_i_1_n_0\
    );
\byte_read_done[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFDFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[4]\,
      I4 => \byte_read_done[12]_i_5_n_0\,
      O => \byte_read_done[10]_i_2_n_0\
    );
\byte_read_done[10]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \byte_read_done[10]_i_4_n_0\,
      O => \byte_read_done[10]_i_3_n_0\
    );
\byte_read_done[10]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_read_done[13]_i_5_n_0\,
      I1 => \byte_read_done[10]_i_5_n_0\,
      I2 => \byte_read_done[9]_i_2_n_0\,
      I3 => \byte_read_done[11]_i_3_n_0\,
      I4 => \state_reg_n_0_[0]\,
      I5 => \bytes10[15]_i_4_n_0\,
      O => \byte_read_done[10]_i_4_n_0\
    );
\byte_read_done[10]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFDFFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_read_done[12]_i_5_n_0\,
      I4 => \byte_count_reg[0]_rep__1_n_0\,
      O => \byte_read_done[10]_i_5_n_0\
    );
\byte_read_done[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \byte_read_done[13]_i_3_n_0\,
      I1 => \byte_read_done[11]_i_2_n_0\,
      I2 => \byte_read_done[11]_i_3_n_0\,
      I3 => \byte_read_done[11]_i_4_n_0\,
      I4 => \byte_read_done[11]_i_5_n_0\,
      I5 => \byte_read_done_reg_n_0_[11]\,
      O => \byte_read_done[11]_i_1_n_0\
    );
\byte_read_done[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000800000"
    )
        port map (
      I0 => \byte_read_done[6]_i_2_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[4]\,
      I5 => \byte_read_done[12]_i_5_n_0\,
      O => \byte_read_done[11]_i_2_n_0\
    );
\byte_read_done[11]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \state_reg[1]_rep_n_0\,
      O => \byte_read_done[11]_i_3_n_0\
    );
\byte_read_done[11]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFDDD"
    )
        port map (
      I0 => \byte_count_reg_n_0_[4]\,
      I1 => \byte_read_done[12]_i_5_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[3]\,
      O => \byte_read_done[11]_i_4_n_0\
    );
\byte_read_done[11]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \byte_read_done[11]_i_6_n_0\,
      O => \byte_read_done[11]_i_5_n_0\
    );
\byte_read_done[11]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_read_done[13]_i_5_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg[1]_rep_n_0\,
      I3 => \byte_count_reg[0]_rep_n_0\,
      I4 => \state_reg_n_0_[0]\,
      I5 => \byte_read_done[11]_i_2_n_0\,
      O => \byte_read_done[11]_i_6_n_0\
    );
\byte_read_done[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => \byte_read_done[12]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \byte_read_done[12]_i_3_n_0\,
      I4 => \byte_read_done[12]_i_4_n_0\,
      I5 => p_1_in65_in,
      O => \byte_read_done[12]_i_1_n_0\
    );
\byte_read_done[12]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFFFF"
    )
        port map (
      I0 => \byte_read_done[12]_i_5_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[4]\,
      O => \byte_read_done[12]_i_2_n_0\
    );
\byte_read_done[12]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFFFFFFFDFFFDFF"
    )
        port map (
      I0 => \state_reg[1]_rep__0_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \byte_count[10]_i_16_n_0\,
      I3 => \byte_read_done[3]_i_3_n_0\,
      I4 => \byte_read_done[3]_i_4_n_0\,
      I5 => \byte_read_done[6]_i_2_n_0\,
      O => \byte_read_done[12]_i_3_n_0\
    );
\byte_read_done[12]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \byte_read_done[12]_i_6_n_0\,
      O => \byte_read_done[12]_i_4_n_0\
    );
\byte_read_done[12]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \byte_count_reg_n_0_[8]\,
      I1 => \byte_count_reg_n_0_[9]\,
      I2 => \byte_count_reg_n_0_[10]\,
      I3 => \byte_count_reg_n_0_[6]\,
      I4 => \byte_count_reg_n_0_[7]\,
      I5 => \byte_count_reg_n_0_[5]\,
      O => \byte_read_done[12]_i_5_n_0\
    );
\byte_read_done[12]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA2AAAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_read_done[13]_i_5_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \dest_mac[23]_i_2_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \byte_read_done[9]_i_2_n_0\,
      I5 => \bytes12[15]_i_2_n_0\,
      O => \byte_read_done[12]_i_6_n_0\
    );
\byte_read_done[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDFD0020"
    )
        port map (
      I0 => eth_rstn,
      I1 => \byte_read_done[13]_i_2_n_0\,
      I2 => \byte_read_done[13]_i_3_n_0\,
      I3 => \byte_read_done[13]_i_4_n_0\,
      I4 => p_0_in57_in,
      O => \byte_read_done[13]_i_1_n_0\
    );
\byte_read_done[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA2AAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_read_done[13]_i_5_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \byte_read_done[11]_i_3_n_0\,
      I3 => \byte_count[1]_i_7_n_0\,
      I4 => \byte_read_done[6]_i_2_n_0\,
      I5 => \byte_count_reg[0]_rep_n_0\,
      O => \byte_read_done[13]_i_2_n_0\
    );
\byte_read_done[13]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F700"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => \byte_read_done[3]_i_3_n_0\,
      I4 => \byte_count[10]_i_16_n_0\,
      O => \byte_read_done[13]_i_3_n_0\
    );
\byte_read_done[13]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \byte_count[1]_i_7_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \byte_read_done[12]_i_2_n_0\,
      I4 => \byte_read_done[6]_i_2_n_0\,
      I5 => \byte_read_done[13]_i_6_n_0\,
      O => \byte_read_done[13]_i_4_n_0\
    );
\byte_read_done[13]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FAAAAFFC"
    )
        port map (
      I0 => \byte_read_done[3]_i_3_n_0\,
      I1 => \state_reg_n_0_[3]\,
      I2 => \state_reg[1]_rep_n_0\,
      I3 => \state_reg_n_0_[0]\,
      I4 => \state_reg_n_0_[2]\,
      O => \byte_read_done[13]_i_5_n_0\
    );
\byte_read_done[13]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBFFFFFF"
    )
        port map (
      I0 => \byte_read_done[12]_i_5_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[1]\,
      O => \byte_read_done[13]_i_6_n_0\
    );
\byte_read_done[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \byte_read_done[1]_i_2_n_0\,
      I1 => \state[3]_i_7_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \byte_read_done[1]_i_3_n_0\,
      I5 => \byte_read_done_reg_n_0_[1]\,
      O => \byte_read_done[1]_i_1_n_0\
    );
\byte_read_done[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22222220"
    )
        port map (
      I0 => \byte_read_done[3]_i_3_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[2]\,
      O => \byte_read_done[1]_i_2_n_0\
    );
\byte_read_done[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"57550000"
    )
        port map (
      I0 => \byte_read_done[13]_i_5_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => read_frame_done_i_3_n_0,
      I3 => \byte_read_done[1]_i_4_n_0\,
      I4 => eth_rstn,
      O => \byte_read_done[1]_i_3_n_0\
    );
\byte_read_done[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4040404040404000"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => \byte_count_reg_n_0_[1]\,
      O => \byte_read_done[1]_i_4_n_0\
    );
\byte_read_done[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \byte_read_done[2]_i_2_n_0\,
      I1 => \byte_read_done[3]_i_3_n_0\,
      I2 => \state[3]_i_7_n_0\,
      I3 => \byte_read_done[11]_i_3_n_0\,
      I4 => \byte_read_done[2]_i_3_n_0\,
      I5 => \byte_read_done_reg_n_0_[2]\,
      O => \byte_read_done[2]_i_1_n_0\
    );
\byte_read_done[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000020000"
    )
        port map (
      I0 => \byte_read_done[6]_i_2_n_0\,
      I1 => \byte_read_done[12]_i_5_n_0\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg_n_0_[2]\,
      I5 => \byte_count_reg_n_0_[3]\,
      O => \byte_read_done[2]_i_2_n_0\
    );
\byte_read_done[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \byte_read_done[2]_i_4_n_0\,
      O => \byte_read_done[2]_i_3_n_0\
    );
\byte_read_done[2]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA2AAAAAAAAAA"
    )
        port map (
      I0 => \byte_read_done[13]_i_5_n_0\,
      I1 => \byte_read_done[2]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \bit_count[1]_i_3_n_0\,
      I4 => \byte_read_done[10]_i_5_n_0\,
      I5 => \byte_read_done[3]_i_11_n_0\,
      O => \byte_read_done[2]_i_4_n_0\
    );
\byte_read_done[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \byte_read_done[3]_i_2_n_0\,
      I1 => \byte_read_done[3]_i_3_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => \byte_read_done[11]_i_3_n_0\,
      I4 => \byte_read_done[3]_i_5_n_0\,
      I5 => p_0_in,
      O => \byte_read_done[3]_i_1_n_0\
    );
\byte_read_done[3]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \byte_count_reg_n_0_[4]\,
      I1 => \byte_count_reg_n_0_[6]\,
      I2 => \byte_count_reg_n_0_[7]\,
      I3 => \byte_count_reg_n_0_[5]\,
      O => \byte_read_done[3]_i_10_n_0\
    );
\byte_read_done[3]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \state_reg_n_0_[2]\,
      O => \byte_read_done[3]_i_11_n_0\
    );
\byte_read_done[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_6_n_0\,
      O => \byte_read_done[3]_i_2_n_0\
    );
\byte_read_done[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => start_crc_i_2_n_0,
      I1 => unknown_request2,
      I2 => unknown_request3_reg_n_0,
      I3 => unknown_request4_reg_n_0,
      I4 => unknown_request1_reg_n_0,
      O => \byte_read_done[3]_i_3_n_0\
    );
\byte_read_done[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \byte_read_done[12]_i_5_n_0\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_count_reg_n_0_[2]\,
      O => \byte_read_done[3]_i_4_n_0\
    );
\byte_read_done[3]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \byte_read_done[3]_i_7_n_0\,
      O => \byte_read_done[3]_i_5_n_0\
    );
\byte_read_done[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \byte_read_done[3]_i_8_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_read_done[3]_i_9_n_0\,
      I3 => \byte_count_reg_n_0_[10]\,
      I4 => \byte_count_reg_n_0_[9]\,
      I5 => \byte_count_reg_n_0_[8]\,
      O => \byte_read_done[3]_i_6_n_0\
    );
\byte_read_done[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA2AAAAAAAAAAA"
    )
        port map (
      I0 => \byte_read_done[13]_i_5_n_0\,
      I1 => \byte_read_done[3]_i_2_n_0\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \dest_mac[23]_i_2_n_0\,
      I4 => \byte_read_done[3]_i_10_n_0\,
      I5 => \byte_read_done[3]_i_11_n_0\,
      O => \byte_read_done[3]_i_7_n_0\
    );
\byte_read_done[3]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \byte_count_reg_n_0_[5]\,
      I1 => \byte_count_reg_n_0_[7]\,
      I2 => \byte_count_reg_n_0_[6]\,
      O => \byte_read_done[3]_i_8_n_0\
    );
\byte_read_done[3]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[1]\,
      O => \byte_read_done[3]_i_9_n_0\
    );
\byte_read_done[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \bit_count_reg[1]_rep_n_0\,
      I1 => ip_header_options1(1),
      I2 => \byte_read_done[5]_i_2_n_0\,
      I3 => \byte_read_done[12]_i_3_n_0\,
      I4 => \byte_read_done[5]_i_3_n_0\,
      I5 => \byte_read_done_reg_n_0_[5]\,
      O => \byte_read_done[5]_i_1_n_0\
    );
\byte_read_done[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[4]\,
      I4 => \byte_read_done[12]_i_5_n_0\,
      O => \byte_read_done[5]_i_2_n_0\
    );
\byte_read_done[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \byte_read_done[5]_i_4_n_0\,
      O => \byte_read_done[5]_i_3_n_0\
    );
\byte_read_done[5]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_read_done[13]_i_5_n_0\,
      I1 => \byte_count_reg[0]_rep_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => ip_header_options1(1),
      I4 => \byte_read_done[5]_i_2_n_0\,
      I5 => \byte_read_done[6]_i_6_n_0\,
      O => \byte_read_done[5]_i_4_n_0\
    );
\byte_read_done[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004FFFF00040000"
    )
        port map (
      I0 => \byte_count_reg[1]_rep_n_0\,
      I1 => \byte_read_done[6]_i_2_n_0\,
      I2 => \byte_read_done[6]_i_3_n_0\,
      I3 => \byte_read_done[12]_i_3_n_0\,
      I4 => \byte_read_done[6]_i_4_n_0\,
      I5 => \byte_read_done_reg_n_0_[6]\,
      O => \byte_read_done[6]_i_1_n_0\
    );
\byte_read_done[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \bit_count_reg[1]_rep_n_0\,
      I1 => ip_header_options1(1),
      O => \byte_read_done[6]_i_2_n_0\
    );
\byte_read_done[6]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \byte_read_done[12]_i_5_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      O => \byte_read_done[6]_i_3_n_0\
    );
\byte_read_done[6]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \byte_read_done[6]_i_5_n_0\,
      O => \byte_read_done[6]_i_4_n_0\
    );
\byte_read_done[6]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAA2AAAAAA"
    )
        port map (
      I0 => \byte_read_done[13]_i_5_n_0\,
      I1 => \byte_read_done[6]_i_6_n_0\,
      I2 => \byte_read_done[6]_i_3_n_0\,
      I3 => \byte_read_done[6]_i_2_n_0\,
      I4 => \byte_count_reg[0]_rep__1_n_0\,
      I5 => \byte_count_reg[1]_rep_n_0\,
      O => \byte_read_done[6]_i_5_n_0\
    );
\byte_read_done[6]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0020002000200000"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \byte_read_done[11]_i_3_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => \state[3]_i_14_n_0\,
      I4 => \state[2]_i_9__0_n_0\,
      I5 => \byte_read_done[6]_i_2_n_0\,
      O => \byte_read_done[6]_i_6_n_0\
    );
\byte_read_done[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDFD0020"
    )
        port map (
      I0 => eth_rstn,
      I1 => \byte_read_done[7]_i_2_n_0\,
      I2 => \byte_read_done[7]_i_3_n_0\,
      I3 => \byte_read_done[12]_i_3_n_0\,
      I4 => p_171_in,
      O => \byte_read_done[7]_i_1_n_0\
    );
\byte_read_done[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_read_done[13]_i_5_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => \bit_count[1]_i_3_n_0\,
      I4 => \byte_read_done[7]_i_4_n_0\,
      I5 => \byte_read_done[7]_i_3_n_0\,
      O => \byte_read_done[7]_i_2_n_0\
    );
\byte_read_done[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => \byte_read_done[12]_i_5_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_read_done[6]_i_2_n_0\,
      I5 => \byte_count_reg_n_0_[1]\,
      O => \byte_read_done[7]_i_3_n_0\
    );
\byte_read_done[7]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      O => \byte_read_done[7]_i_4_n_0\
    );
\byte_read_done[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => \byte_read_done[8]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \byte_read_done[12]_i_3_n_0\,
      I4 => \byte_read_done[8]_i_3_n_0\,
      I5 => \byte_read_done_reg_n_0_[8]\,
      O => \byte_read_done[8]_i_1_n_0\
    );
\byte_read_done[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFD"
    )
        port map (
      I0 => \byte_count_reg_n_0_[4]\,
      I1 => \byte_read_done[12]_i_5_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[1]\,
      O => \byte_read_done[8]_i_2_n_0\
    );
\byte_read_done[8]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \byte_read_done[8]_i_4_n_0\,
      O => \byte_read_done[8]_i_3_n_0\
    );
\byte_read_done[8]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA2AAAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_read_done[13]_i_5_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \dest_mac[23]_i_2_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \byte_read_done[6]_i_3_n_0\,
      I5 => \bytes08[15]_i_4_n_0\,
      O => \byte_read_done[8]_i_4_n_0\
    );
\byte_read_done[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => \byte_read_done[9]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \byte_read_done[12]_i_3_n_0\,
      I4 => \byte_read_done[9]_i_3_n_0\,
      I5 => \byte_read_done_reg_n_0_[9]\,
      O => \byte_read_done[9]_i_1_n_0\
    );
\byte_read_done[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFEFFFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_read_done[12]_i_5_n_0\,
      I4 => \byte_count_reg_n_0_[4]\,
      O => \byte_read_done[9]_i_2_n_0\
    );
\byte_read_done[9]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \byte_read_done[9]_i_4_n_0\,
      O => \byte_read_done[9]_i_3_n_0\
    );
\byte_read_done[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_read_done[13]_i_5_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg[1]_rep_n_0\,
      I3 => \byte_count_reg_n_0_[0]\,
      I4 => \state_reg_n_0_[0]\,
      I5 => \bytes09[15]_i_2_n_0\,
      O => \byte_read_done[9]_i_4_n_0\
    );
\byte_read_done_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_read_done[0]_i_1_n_0\,
      Q => \byte_read_done_reg_n_0_[0]\,
      R => '0'
    );
\byte_read_done_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_read_done[10]_i_1_n_0\,
      Q => \byte_read_done_reg_n_0_[10]\,
      R => '0'
    );
\byte_read_done_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_read_done[11]_i_1_n_0\,
      Q => \byte_read_done_reg_n_0_[11]\,
      R => '0'
    );
\byte_read_done_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_read_done[12]_i_1_n_0\,
      Q => p_1_in65_in,
      R => '0'
    );
\byte_read_done_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_read_done[13]_i_1_n_0\,
      Q => p_0_in57_in,
      R => '0'
    );
\byte_read_done_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_read_done[1]_i_1_n_0\,
      Q => \byte_read_done_reg_n_0_[1]\,
      R => '0'
    );
\byte_read_done_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_read_done[2]_i_1_n_0\,
      Q => \byte_read_done_reg_n_0_[2]\,
      R => '0'
    );
\byte_read_done_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_read_done[3]_i_1_n_0\,
      Q => p_0_in,
      R => '0'
    );
\byte_read_done_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_read_done[5]_i_1_n_0\,
      Q => \byte_read_done_reg_n_0_[5]\,
      R => '0'
    );
\byte_read_done_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_read_done[6]_i_1_n_0\,
      Q => \byte_read_done_reg_n_0_[6]\,
      R => '0'
    );
\byte_read_done_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_read_done[7]_i_1_n_0\,
      Q => p_171_in,
      R => '0'
    );
\byte_read_done_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_read_done[8]_i_1_n_0\,
      Q => \byte_read_done_reg_n_0_[8]\,
      R => '0'
    );
\byte_read_done_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \byte_read_done[9]_i_1_n_0\,
      Q => \byte_read_done_reg_n_0_[9]\,
      R => '0'
    );
\bytes00[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes00[8]_i_2_n_0\,
      I3 => \bytes00[1]_i_2_n_0\,
      I4 => \bytes00_reg_n_0_[0]\,
      O => \bytes00[0]_i_1_n_0\
    );
\bytes00[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes00[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes00[10]_i_2_n_0\,
      I5 => data_counter_max2(2),
      O => \bytes00[10]_i_1_n_0\
    );
\bytes00[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFFFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => eth_rxd(0),
      O => \bytes00[10]_i_2_n_0\
    );
\bytes00[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes00[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes00[11]_i_3_n_0\,
      I5 => data_counter_max2(3),
      O => \bytes00[11]_i_1_n_0\
    );
\bytes00[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bit_count_reg[0]_rep_n_0\,
      I5 => \bytes00[15]_i_5_n_0\,
      O => \bytes00[11]_i_2_n_0\
    );
\bytes00[11]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFFFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => eth_rxd(1),
      O => \bytes00[11]_i_3_n_0\
    );
\bytes00[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes00[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes00[12]_i_2_n_0\,
      I5 => \bytes00_reg_n_0_[12]\,
      O => \bytes00[12]_i_1_n_0\
    );
\bytes00[12]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFFFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => eth_rxd(0),
      O => \bytes00[12]_i_2_n_0\
    );
\bytes00[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes00[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes00[13]_i_3_n_0\,
      I5 => \bytes00_reg_n_0_[13]\,
      O => \bytes00[13]_i_1_n_0\
    );
\bytes00[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => ip_header_options1(2),
      I5 => \bytes00[15]_i_5_n_0\,
      O => \bytes00[13]_i_2_n_0\
    );
\bytes00[13]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFFFFFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => eth_rxd(1),
      O => \bytes00[13]_i_3_n_0\
    );
\bytes00[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes00[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes00[14]_i_2_n_0\,
      I5 => \bytes00_reg_n_0_[14]\,
      O => \bytes00[14]_i_1_n_0\
    );
\bytes00[14]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \byte_read_done[0]_i_2_n_0\,
      O => \bytes00[14]_i_2_n_0\
    );
\bytes00[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes00[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes00[15]_i_3_n_0\,
      I5 => \bytes00_reg_n_0_[15]\,
      O => \bytes00[15]_i_1_n_0\
    );
\bytes00[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA2AAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes00[15]_i_5_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => \byte_count_reg[1]_rep_n_0\,
      I4 => ip_header_options1(1),
      I5 => \bit_count_reg[1]_rep_n_0\,
      O => \bytes00[15]_i_2_n_0\
    );
\bytes00[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \byte_read_done[0]_i_2_n_0\,
      O => \bytes00[15]_i_3_n_0\
    );
\bytes00[15]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \state_reg_n_0_[3]\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \state_reg[1]_rep_n_0\,
      O => \bytes00[15]_i_4_n_0\
    );
\bytes00[15]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => \byte_read_done[3]_i_3_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \state_reg_n_0_[0]\,
      I4 => \byte_count_reg[0]_rep__1_n_0\,
      O => \bytes00[15]_i_5_n_0\
    );
\bytes00[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes00[9]_i_3_n_0\,
      I3 => \bytes00[1]_i_2_n_0\,
      I4 => \bytes00_reg_n_0_[1]\,
      O => \bytes00[1]_i_1_n_0\
    );
\bytes00[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55570000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes00[7]_i_3_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => eth_rstn,
      O => \bytes00[1]_i_2_n_0\
    );
\bytes00[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes00[10]_i_2_n_0\,
      I3 => \bytes00[3]_i_2_n_0\,
      I4 => \bytes00_reg_n_0_[2]\,
      O => \bytes00[2]_i_1_n_0\
    );
\bytes00[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes00[11]_i_3_n_0\,
      I3 => \bytes00[3]_i_2_n_0\,
      I4 => \bytes00_reg_n_0_[3]\,
      O => \bytes00[3]_i_1_n_0\
    );
\bytes00[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55750000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes00[7]_i_3_n_0\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => eth_rstn,
      O => \bytes00[3]_i_2_n_0\
    );
\bytes00[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes00[12]_i_2_n_0\,
      I3 => \bytes00[5]_i_2_n_0\,
      I4 => \bytes00_reg_n_0_[4]\,
      O => \bytes00[4]_i_1_n_0\
    );
\bytes00[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes00[13]_i_3_n_0\,
      I3 => \bytes00[5]_i_2_n_0\,
      I4 => \bytes00_reg_n_0_[5]\,
      O => \bytes00[5]_i_1_n_0\
    );
\bytes00[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55750000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes00[7]_i_3_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => eth_rstn,
      O => \bytes00[5]_i_2_n_0\
    );
\bytes00[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes00[14]_i_2_n_0\,
      I3 => \bytes00[7]_i_2_n_0\,
      I4 => \bytes00_reg_n_0_[6]\,
      O => \bytes00[6]_i_1_n_0\
    );
\bytes00[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes00[15]_i_3_n_0\,
      I3 => \bytes00[7]_i_2_n_0\,
      I4 => \bytes00_reg_n_0_[7]\,
      O => \bytes00[7]_i_1_n_0\
    );
\bytes00[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"75550000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes00[7]_i_3_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => ip_header_options1(1),
      I4 => eth_rstn,
      O => \bytes00[7]_i_2_n_0\
    );
\bytes00[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFFFFFFFFFF"
    )
        port map (
      I0 => \bytes00[7]_i_4_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \state_reg_n_0_[0]\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => \byte_count_reg[0]_rep__0_n_0\,
      O => \bytes00[7]_i_3_n_0\
    );
\bytes00[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \byte_count_reg[1]_rep_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      O => \bytes00[7]_i_4_n_0\
    );
\bytes00[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes00[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes00[8]_i_2_n_0\,
      I5 => data_counter_max2(0),
      O => \bytes00[8]_i_1_n_0\
    );
\bytes00[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => eth_rxd(0),
      O => \bytes00[8]_i_2_n_0\
    );
\bytes00[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes00[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes00[9]_i_3_n_0\,
      I5 => data_counter_max2(1),
      O => \bytes00[9]_i_1_n_0\
    );
\bytes00[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA8AAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => ip_header_options1(2),
      I5 => \bytes00[15]_i_5_n_0\,
      O => \bytes00[9]_i_2_n_0\
    );
\bytes00[9]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEFFFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => eth_rxd(1),
      O => \bytes00[9]_i_3_n_0\
    );
\bytes00_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[0]_i_1_n_0\,
      Q => \bytes00_reg_n_0_[0]\,
      R => '0'
    );
\bytes00_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[10]_i_1_n_0\,
      Q => data_counter_max2(2),
      R => '0'
    );
\bytes00_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[11]_i_1_n_0\,
      Q => data_counter_max2(3),
      R => '0'
    );
\bytes00_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[12]_i_1_n_0\,
      Q => \bytes00_reg_n_0_[12]\,
      R => '0'
    );
\bytes00_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[13]_i_1_n_0\,
      Q => \bytes00_reg_n_0_[13]\,
      R => '0'
    );
\bytes00_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[14]_i_1_n_0\,
      Q => \bytes00_reg_n_0_[14]\,
      R => '0'
    );
\bytes00_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[15]_i_1_n_0\,
      Q => \bytes00_reg_n_0_[15]\,
      R => '0'
    );
\bytes00_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[1]_i_1_n_0\,
      Q => \bytes00_reg_n_0_[1]\,
      R => '0'
    );
\bytes00_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[2]_i_1_n_0\,
      Q => \bytes00_reg_n_0_[2]\,
      R => '0'
    );
\bytes00_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[3]_i_1_n_0\,
      Q => \bytes00_reg_n_0_[3]\,
      R => '0'
    );
\bytes00_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[4]_i_1_n_0\,
      Q => \bytes00_reg_n_0_[4]\,
      R => '0'
    );
\bytes00_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[5]_i_1_n_0\,
      Q => \bytes00_reg_n_0_[5]\,
      R => '0'
    );
\bytes00_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[6]_i_1_n_0\,
      Q => \bytes00_reg_n_0_[6]\,
      R => '0'
    );
\bytes00_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[7]_i_1_n_0\,
      Q => \bytes00_reg_n_0_[7]\,
      R => '0'
    );
\bytes00_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[8]_i_1_n_0\,
      Q => data_counter_max2(0),
      R => '0'
    );
\bytes00_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes00[9]_i_1_n_0\,
      Q => data_counter_max2(1),
      R => '0'
    );
\bytes01[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[8]_i_2_n_0\,
      I3 => \bytes01[1]_i_2_n_0\,
      I4 => bytes01(0),
      O => \bytes01[0]_i_1_n_0\
    );
\bytes01[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[10]_i_2_n_0\,
      I3 => \bytes01[11]_i_3_n_0\,
      I4 => bytes01(10),
      O => \bytes01[10]_i_1_n_0\
    );
\bytes01[10]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \bytes01[15]_i_4_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => eth_rxd(0),
      O => \bytes01[10]_i_2_n_0\
    );
\bytes01[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[11]_i_2_n_0\,
      I3 => \bytes01[11]_i_3_n_0\,
      I4 => bytes01(11),
      O => \bytes01[11]_i_1_n_0\
    );
\bytes01[11]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \bytes01[15]_i_4_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => eth_rxd(1),
      O => \bytes01[11]_i_2_n_0\
    );
\bytes01[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5755555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes01[15]_i_4_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => \bytes01[15]_i_5_n_0\,
      I5 => eth_rstn,
      O => \bytes01[11]_i_3_n_0\
    );
\bytes01[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[12]_i_2_n_0\,
      I3 => \bytes01[13]_i_3_n_0\,
      I4 => bytes01(12),
      O => \bytes01[12]_i_1_n_0\
    );
\bytes01[12]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \bytes01[15]_i_4_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => eth_rxd(0),
      O => \bytes01[12]_i_2_n_0\
    );
\bytes01[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[13]_i_2_n_0\,
      I3 => \bytes01[13]_i_3_n_0\,
      I4 => bytes01(13),
      O => \bytes01[13]_i_1_n_0\
    );
\bytes01[13]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \bytes01[15]_i_4_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => eth_rxd(1),
      O => \bytes01[13]_i_2_n_0\
    );
\bytes01[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5755555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes01[15]_i_4_n_0\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bytes01[15]_i_5_n_0\,
      I5 => eth_rstn,
      O => \bytes01[13]_i_3_n_0\
    );
\bytes01[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[14]_i_2_n_0\,
      I3 => \bytes01[15]_i_3_n_0\,
      I4 => bytes01(14),
      O => \bytes01[14]_i_1_n_0\
    );
\bytes01[14]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7FF"
    )
        port map (
      I0 => \bit_count_reg[0]_rep_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bytes01[15]_i_4_n_0\,
      I3 => eth_rxd(0),
      O => \bytes01[14]_i_2_n_0\
    );
\bytes01[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[15]_i_2_n_0\,
      I3 => \bytes01[15]_i_3_n_0\,
      I4 => bytes01(15),
      O => \bytes01[15]_i_1_n_0\
    );
\bytes01[15]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F7FF"
    )
        port map (
      I0 => \bit_count_reg[0]_rep_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bytes01[15]_i_4_n_0\,
      I3 => eth_rxd(1),
      O => \bytes01[15]_i_2_n_0\
    );
\bytes01[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555D55500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes01[15]_i_5_n_0\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bytes01[15]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes01[15]_i_3_n_0\
    );
\bytes01[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFEF"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg_n_0_[7]\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[4]\,
      I5 => \byte_count_reg_n_0_[3]\,
      O => \bytes01[15]_i_4_n_0\
    );
\bytes01[15]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000FE0000"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_read_done[3]_i_4_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => \bytes03[13]_i_4_n_0\,
      O => \bytes01[15]_i_5_n_0\
    );
\bytes01[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[9]_i_2_n_0\,
      I3 => \bytes01[1]_i_2_n_0\,
      I4 => bytes01(1),
      O => \bytes01[1]_i_1_n_0\
    );
\bytes01[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555700000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes01[7]_i_3_n_0\,
      I2 => \bytes01[15]_i_4_n_0\,
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => ip_header_options1(2),
      I5 => eth_rstn,
      O => \bytes01[1]_i_2_n_0\
    );
\bytes01[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[10]_i_2_n_0\,
      I3 => \bytes01[3]_i_2_n_0\,
      I4 => bytes01(2),
      O => \bytes01[2]_i_1_n_0\
    );
\bytes01[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[11]_i_2_n_0\,
      I3 => \bytes01[3]_i_2_n_0\,
      I4 => bytes01(3),
      O => \bytes01[3]_i_1_n_0\
    );
\bytes01[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes01[7]_i_3_n_0\,
      I2 => \bytes01[15]_i_4_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bit_count_reg[0]_rep_n_0\,
      I5 => eth_rstn,
      O => \bytes01[3]_i_2_n_0\
    );
\bytes01[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[12]_i_2_n_0\,
      I3 => \bytes01[5]_i_2_n_0\,
      I4 => bytes01(4),
      O => \bytes01[4]_i_1_n_0\
    );
\bytes01[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[13]_i_2_n_0\,
      I3 => \bytes01[5]_i_2_n_0\,
      I4 => bytes01(5),
      O => \bytes01[5]_i_1_n_0\
    );
\bytes01[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes01[7]_i_3_n_0\,
      I2 => \bytes01[15]_i_4_n_0\,
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => ip_header_options1(2),
      I5 => eth_rstn,
      O => \bytes01[5]_i_2_n_0\
    );
\bytes01[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[14]_i_2_n_0\,
      I3 => \bytes01[7]_i_2_n_0\,
      I4 => bytes01(6),
      O => \bytes01[6]_i_1_n_0\
    );
\bytes01[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[15]_i_2_n_0\,
      I3 => \bytes01[7]_i_2_n_0\,
      I4 => bytes01(7),
      O => \bytes01[7]_i_1_n_0\
    );
\bytes01[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555755500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes01[7]_i_3_n_0\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bytes01[15]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes01[7]_i_2_n_0\
    );
\bytes01[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF5557FFFFFFFF"
    )
        port map (
      I0 => \bytes03[7]_i_3_n_0\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_read_done[3]_i_4_n_0\,
      I5 => \byte_read_done[3]_i_3_n_0\,
      O => \bytes01[7]_i_3_n_0\
    );
\bytes01[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[8]_i_2_n_0\,
      I3 => \bytes01[9]_i_3_n_0\,
      I4 => bytes01(8),
      O => \bytes01[8]_i_1_n_0\
    );
\bytes01[8]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => \bytes01[15]_i_4_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => eth_rxd(0),
      O => \bytes01[8]_i_2_n_0\
    );
\bytes01[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes01[9]_i_2_n_0\,
      I3 => \bytes01[9]_i_3_n_0\,
      I4 => bytes01(9),
      O => \bytes01[9]_i_1_n_0\
    );
\bytes01[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => \bytes01[15]_i_4_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => eth_rxd(1),
      O => \bytes01[9]_i_2_n_0\
    );
\bytes01[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes01[15]_i_4_n_0\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bytes01[15]_i_5_n_0\,
      I5 => eth_rstn,
      O => \bytes01[9]_i_3_n_0\
    );
\bytes01_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[0]_i_1_n_0\,
      Q => bytes01(0),
      R => '0'
    );
\bytes01_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[10]_i_1_n_0\,
      Q => bytes01(10),
      R => '0'
    );
\bytes01_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[11]_i_1_n_0\,
      Q => bytes01(11),
      R => '0'
    );
\bytes01_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[12]_i_1_n_0\,
      Q => bytes01(12),
      R => '0'
    );
\bytes01_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[13]_i_1_n_0\,
      Q => bytes01(13),
      R => '0'
    );
\bytes01_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[14]_i_1_n_0\,
      Q => bytes01(14),
      R => '0'
    );
\bytes01_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[15]_i_1_n_0\,
      Q => bytes01(15),
      R => '0'
    );
\bytes01_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[1]_i_1_n_0\,
      Q => bytes01(1),
      R => '0'
    );
\bytes01_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[2]_i_1_n_0\,
      Q => bytes01(2),
      R => '0'
    );
\bytes01_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[3]_i_1_n_0\,
      Q => bytes01(3),
      R => '0'
    );
\bytes01_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[4]_i_1_n_0\,
      Q => bytes01(4),
      R => '0'
    );
\bytes01_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[5]_i_1_n_0\,
      Q => bytes01(5),
      R => '0'
    );
\bytes01_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[6]_i_1_n_0\,
      Q => bytes01(6),
      R => '0'
    );
\bytes01_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[7]_i_1_n_0\,
      Q => bytes01(7),
      R => '0'
    );
\bytes01_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[8]_i_1_n_0\,
      Q => bytes01(8),
      R => '0'
    );
\bytes01_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes01[9]_i_1_n_0\,
      Q => bytes01(9),
      R => '0'
    );
\bytes02[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FFFF00020000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \dest_mac[12]_i_3_n_0\,
      I4 => \bytes02[1]_i_2_n_0\,
      I5 => bytes02(0),
      O => \bytes02[0]_i_1_n_0\
    );
\bytes02[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => \dest_mac[12]_i_3_n_0\,
      I4 => \bytes02[11]_i_2_n_0\,
      I5 => bytes02(10),
      O => \bytes02[10]_i_1_n_0\
    );
\bytes02[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bytes02[13]_i_2_n_0\,
      I4 => \bytes02[11]_i_2_n_0\,
      I5 => bytes02(11),
      O => \bytes02[11]_i_1_n_0\
    );
\bytes02[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55750000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes02[15]_i_3_n_0\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => eth_rstn,
      O => \bytes02[11]_i_2_n_0\
    );
\bytes02[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \dest_mac[12]_i_3_n_0\,
      I4 => \bytes02[13]_i_3_n_0\,
      I5 => bytes02(12),
      O => \bytes02[12]_i_1_n_0\
    );
\bytes02[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes02[13]_i_2_n_0\,
      I4 => \bytes02[13]_i_3_n_0\,
      I5 => bytes02(13),
      O => \bytes02[13]_i_1_n_0\
    );
\bytes02[13]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \dest_mac[12]_i_4_n_0\,
      O => \bytes02[13]_i_2_n_0\
    );
\bytes02[13]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55750000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes02[15]_i_3_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => eth_rstn,
      O => \bytes02[13]_i_3_n_0\
    );
\bytes02[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \dest_mac[12]_i_3_n_0\,
      I4 => \bytes02[15]_i_2_n_0\,
      I5 => bytes02(14),
      O => \bytes02[14]_i_1_n_0\
    );
\bytes02[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010FFFF00100000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \dest_mac[47]_i_2_n_0\,
      I3 => \dest_mac[15]_i_2_n_0\,
      I4 => \bytes02[15]_i_2_n_0\,
      I5 => bytes02(15),
      O => \bytes02[15]_i_1_n_0\
    );
\bytes02[15]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"75550000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes02[15]_i_3_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => eth_rstn,
      O => \bytes02[15]_i_2_n_0\
    );
\bytes02[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFDFFFFFFFFFFFFF"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \byte_count_reg[0]_rep_n_0\,
      I4 => \dest_mac[12]_i_4_n_0\,
      I5 => \byte_read_done[3]_i_3_n_0\,
      O => \bytes02[15]_i_3_n_0\
    );
\bytes02[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FFFF00020000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes02[13]_i_2_n_0\,
      I4 => \bytes02[1]_i_2_n_0\,
      I5 => bytes02(1),
      O => \bytes02[1]_i_1_n_0\
    );
\bytes02[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55570000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes02[7]_i_3_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => eth_rstn,
      O => \bytes02[1]_i_2_n_0\
    );
\bytes02[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => \dest_mac[12]_i_3_n_0\,
      I4 => \bytes02[3]_i_2_n_0\,
      I5 => bytes02(2),
      O => \bytes02[2]_i_1_n_0\
    );
\bytes02[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bytes02[13]_i_2_n_0\,
      I4 => \bytes02[3]_i_2_n_0\,
      I5 => bytes02(3),
      O => \bytes02[3]_i_1_n_0\
    );
\bytes02[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55750000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes02[7]_i_3_n_0\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => eth_rstn,
      O => \bytes02[3]_i_2_n_0\
    );
\bytes02[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \dest_mac[12]_i_3_n_0\,
      I4 => \bytes02[5]_i_2_n_0\,
      I5 => bytes02(4),
      O => \bytes02[4]_i_1_n_0\
    );
\bytes02[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes02[13]_i_2_n_0\,
      I4 => \bytes02[5]_i_2_n_0\,
      I5 => bytes02(5),
      O => \bytes02[5]_i_1_n_0\
    );
\bytes02[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55750000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes02[7]_i_3_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => eth_rstn,
      O => \bytes02[5]_i_2_n_0\
    );
\bytes02[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \dest_mac[12]_i_3_n_0\,
      I4 => \bytes02[7]_i_2_n_0\,
      I5 => bytes02(6),
      O => \bytes02[6]_i_1_n_0\
    );
\bytes02[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes02[13]_i_2_n_0\,
      I4 => \bytes02[7]_i_2_n_0\,
      I5 => bytes02(7),
      O => \bytes02[7]_i_1_n_0\
    );
\bytes02[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"75550000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes02[7]_i_3_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => eth_rstn,
      O => \bytes02[7]_i_2_n_0\
    );
\bytes02[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF7FFFFFFF"
    )
        port map (
      I0 => \dest_mac[12]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_3_n_0\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      I4 => \state_reg[1]_rep_n_0\,
      I5 => \state_reg_n_0_[2]\,
      O => \bytes02[7]_i_3_n_0\
    );
\bytes02[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FFFF00020000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \dest_mac[12]_i_3_n_0\,
      I4 => \bytes02[9]_i_2_n_0\,
      I5 => bytes02(8),
      O => \bytes02[8]_i_1_n_0\
    );
\bytes02[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FFFF00020000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes02[13]_i_2_n_0\,
      I4 => \bytes02[9]_i_2_n_0\,
      I5 => bytes02(9),
      O => \bytes02[9]_i_1_n_0\
    );
\bytes02[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55570000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes02[15]_i_3_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => eth_rstn,
      O => \bytes02[9]_i_2_n_0\
    );
\bytes02_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[0]_i_1_n_0\,
      Q => bytes02(0),
      R => '0'
    );
\bytes02_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[10]_i_1_n_0\,
      Q => bytes02(10),
      R => '0'
    );
\bytes02_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[11]_i_1_n_0\,
      Q => bytes02(11),
      R => '0'
    );
\bytes02_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[12]_i_1_n_0\,
      Q => bytes02(12),
      R => '0'
    );
\bytes02_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[13]_i_1_n_0\,
      Q => bytes02(13),
      R => '0'
    );
\bytes02_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[14]_i_1_n_0\,
      Q => bytes02(14),
      R => '0'
    );
\bytes02_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[15]_i_1_n_0\,
      Q => bytes02(15),
      R => '0'
    );
\bytes02_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[1]_i_1_n_0\,
      Q => bytes02(1),
      R => '0'
    );
\bytes02_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[2]_i_1_n_0\,
      Q => bytes02(2),
      R => '0'
    );
\bytes02_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[3]_i_1_n_0\,
      Q => bytes02(3),
      R => '0'
    );
\bytes02_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[4]_i_1_n_0\,
      Q => bytes02(4),
      R => '0'
    );
\bytes02_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[5]_i_1_n_0\,
      Q => bytes02(5),
      R => '0'
    );
\bytes02_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[6]_i_1_n_0\,
      Q => bytes02(6),
      R => '0'
    );
\bytes02_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[7]_i_1_n_0\,
      Q => bytes02(7),
      R => '0'
    );
\bytes02_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[8]_i_1_n_0\,
      Q => bytes02(8),
      R => '0'
    );
\bytes02_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes02[9]_i_1_n_0\,
      Q => bytes02(9),
      R => '0'
    );
\bytes03[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes03[1]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes03[8]_i_2_n_0\,
      I5 => bytes03(0),
      O => \bytes03[0]_i_1_n_0\
    );
\bytes03[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes03[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes03[10]_i_2_n_0\,
      I5 => bytes03(10),
      O => \bytes03[10]_i_1_n_0\
    );
\bytes03[10]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_6_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => eth_rxd(0),
      O => \bytes03[10]_i_2_n_0\
    );
\bytes03[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes03[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes03[11]_i_3_n_0\,
      I5 => bytes03(11),
      O => \bytes03[11]_i_1_n_0\
    );
\bytes03[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAA8AA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_6_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => \bytes03[13]_i_4_n_0\,
      I5 => \bytes03[13]_i_5_n_0\,
      O => \bytes03[11]_i_2_n_0\
    );
\bytes03[11]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_6_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => eth_rxd(1),
      O => \bytes03[11]_i_3_n_0\
    );
\bytes03[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes03[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes03[12]_i_2_n_0\,
      I5 => bytes03(12),
      O => \bytes03[12]_i_1_n_0\
    );
\bytes03[12]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_6_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => eth_rxd(0),
      O => \bytes03[12]_i_2_n_0\
    );
\bytes03[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes03[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes03[13]_i_3_n_0\,
      I5 => bytes03(13),
      O => \bytes03[13]_i_1_n_0\
    );
\bytes03[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAA8AA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_6_n_0\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bytes03[13]_i_4_n_0\,
      I5 => \bytes03[13]_i_5_n_0\,
      O => \bytes03[13]_i_2_n_0\
    );
\bytes03[13]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_6_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => eth_rxd(1),
      O => \bytes03[13]_i_3_n_0\
    );
\bytes03[13]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep_n_0\,
      O => \bytes03[13]_i_4_n_0\
    );
\bytes03[13]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1F"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      O => \bytes03[13]_i_5_n_0\
    );
\bytes03[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes03[14]_i_2_n_0\,
      I3 => \bytes03[15]_i_3_n_0\,
      I4 => bytes03(14),
      O => \bytes03[14]_i_1_n_0\
    );
\bytes03[14]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \byte_read_done[3]_i_2_n_0\,
      O => \bytes03[14]_i_2_n_0\
    );
\bytes03[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes03[15]_i_2_n_0\,
      I3 => \bytes03[15]_i_3_n_0\,
      I4 => bytes03(15),
      O => \bytes03[15]_i_1_n_0\
    );
\bytes03[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \byte_read_done[3]_i_2_n_0\,
      O => \bytes03[15]_i_2_n_0\
    );
\bytes03[15]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D500"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes03[15]_i_4_n_0\,
      I2 => \byte_read_done[3]_i_2_n_0\,
      I3 => eth_rstn,
      O => \bytes03[15]_i_3_n_0\
    );
\bytes03[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \byte_count_reg[0]_rep_n_0\,
      I4 => \byte_read_done[3]_i_6_n_0\,
      I5 => \bytes03[13]_i_5_n_0\,
      O => \bytes03[15]_i_4_n_0\
    );
\bytes03[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes03[1]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes03[9]_i_3_n_0\,
      I5 => bytes03(1),
      O => \bytes03[1]_i_1_n_0\
    );
\bytes03[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAA8AA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_6_n_0\,
      I2 => \bytes03[13]_i_5_n_0\,
      I3 => \bytes03[7]_i_3_n_0\,
      I4 => \bit_count_reg[0]_rep_n_0\,
      I5 => ip_header_options1(2),
      O => \bytes03[1]_i_2_n_0\
    );
\bytes03[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes03[3]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes03[10]_i_2_n_0\,
      I5 => bytes03(2),
      O => \bytes03[2]_i_1_n_0\
    );
\bytes03[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes03[3]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes03[11]_i_3_n_0\,
      I5 => bytes03(3),
      O => \bytes03[3]_i_1_n_0\
    );
\bytes03[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA8AAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_6_n_0\,
      I2 => \bytes03[13]_i_5_n_0\,
      I3 => \bytes03[7]_i_3_n_0\,
      I4 => ip_header_options1(2),
      I5 => \bit_count_reg[0]_rep_n_0\,
      O => \bytes03[3]_i_2_n_0\
    );
\bytes03[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes03[5]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes03[12]_i_2_n_0\,
      I5 => bytes03(4),
      O => \bytes03[4]_i_1_n_0\
    );
\bytes03[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes03[5]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes03[13]_i_3_n_0\,
      I5 => bytes03(5),
      O => \bytes03[5]_i_1_n_0\
    );
\bytes03[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA8AAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_6_n_0\,
      I2 => \bytes03[13]_i_5_n_0\,
      I3 => \bytes03[7]_i_3_n_0\,
      I4 => \bit_count_reg[0]_rep_n_0\,
      I5 => ip_header_options1(2),
      O => \bytes03[5]_i_2_n_0\
    );
\bytes03[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes03[7]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes03[14]_i_2_n_0\,
      I5 => bytes03(6),
      O => \bytes03[6]_i_1_n_0\
    );
\bytes03[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes03[7]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes03[15]_i_2_n_0\,
      I5 => bytes03(7),
      O => \bytes03[7]_i_1_n_0\
    );
\bytes03[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8AAAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_6_n_0\,
      I2 => \bytes03[13]_i_5_n_0\,
      I3 => \bytes03[7]_i_3_n_0\,
      I4 => ip_header_options1(1),
      I5 => \bit_count_reg[1]_rep_n_0\,
      O => \bytes03[7]_i_2_n_0\
    );
\bytes03[7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4000"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg_n_0_[0]\,
      O => \bytes03[7]_i_3_n_0\
    );
\bytes03[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes03[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes03[8]_i_2_n_0\,
      I5 => bytes03(8),
      O => \bytes03[8]_i_1_n_0\
    );
\bytes03[8]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_6_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => eth_rxd(0),
      O => \bytes03[8]_i_2_n_0\
    );
\bytes03[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes03[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes03[9]_i_3_n_0\,
      I5 => bytes03(9),
      O => \bytes03[9]_i_1_n_0\
    );
\bytes03[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA8"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_6_n_0\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bytes03[13]_i_4_n_0\,
      I5 => \bytes03[13]_i_5_n_0\,
      O => \bytes03[9]_i_2_n_0\
    );
\bytes03[9]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_6_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => eth_rxd(1),
      O => \bytes03[9]_i_3_n_0\
    );
\bytes03_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[0]_i_1_n_0\,
      Q => bytes03(0),
      R => '0'
    );
\bytes03_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[10]_i_1_n_0\,
      Q => bytes03(10),
      R => '0'
    );
\bytes03_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[11]_i_1_n_0\,
      Q => bytes03(11),
      R => '0'
    );
\bytes03_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[12]_i_1_n_0\,
      Q => bytes03(12),
      R => '0'
    );
\bytes03_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[13]_i_1_n_0\,
      Q => bytes03(13),
      R => '0'
    );
\bytes03_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[14]_i_1_n_0\,
      Q => bytes03(14),
      R => '0'
    );
\bytes03_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[15]_i_1_n_0\,
      Q => bytes03(15),
      R => '0'
    );
\bytes03_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[1]_i_1_n_0\,
      Q => bytes03(1),
      R => '0'
    );
\bytes03_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[2]_i_1_n_0\,
      Q => bytes03(2),
      R => '0'
    );
\bytes03_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[3]_i_1_n_0\,
      Q => bytes03(3),
      R => '0'
    );
\bytes03_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[4]_i_1_n_0\,
      Q => bytes03(4),
      R => '0'
    );
\bytes03_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[5]_i_1_n_0\,
      Q => bytes03(5),
      R => '0'
    );
\bytes03_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[6]_i_1_n_0\,
      Q => bytes03(6),
      R => '0'
    );
\bytes03_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[7]_i_1_n_0\,
      Q => bytes03(7),
      R => '0'
    );
\bytes03_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[8]_i_1_n_0\,
      Q => bytes03(8),
      R => '0'
    );
\bytes03_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes03[9]_i_1_n_0\,
      Q => bytes03(9),
      R => '0'
    );
\bytes04[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes04[1]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes04[8]_i_2_n_0\,
      I5 => bytes04(0),
      O => \bytes04[0]_i_1_n_0\
    );
\bytes04[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes04[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes04[10]_i_2_n_0\,
      I5 => bytes04(10),
      O => \bytes04[10]_i_1_n_0\
    );
\bytes04[10]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \bit_count_reg[1]_rep_n_0\,
      I1 => ip_header_options1(1),
      I2 => \state[2]_i_9__0_n_0\,
      I3 => eth_rxd(0),
      O => \bytes04[10]_i_2_n_0\
    );
\bytes04[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes04[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes04[11]_i_3_n_0\,
      I5 => bytes04(11),
      O => \bytes04[11]_i_1_n_0\
    );
\bytes04[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \state[2]_i_9__0_n_0\,
      I4 => \dest_mac[39]_i_4_n_0\,
      I5 => \bytes00[15]_i_5_n_0\,
      O => \bytes04[11]_i_2_n_0\
    );
\bytes04[11]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \bit_count_reg[1]_rep_n_0\,
      I1 => ip_header_options1(1),
      I2 => \state[2]_i_9__0_n_0\,
      I3 => eth_rxd(1),
      O => \bytes04[11]_i_3_n_0\
    );
\bytes04[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes04[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes04[12]_i_2_n_0\,
      I5 => bytes04(12),
      O => \bytes04[12]_i_1_n_0\
    );
\bytes04[12]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \state[2]_i_9__0_n_0\,
      I3 => eth_rxd(0),
      O => \bytes04[12]_i_2_n_0\
    );
\bytes04[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes04[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes04[13]_i_3_n_0\,
      I5 => bytes04(13),
      O => \bytes04[13]_i_1_n_0\
    );
\bytes04[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \state[2]_i_9__0_n_0\,
      I4 => \dest_mac[39]_i_4_n_0\,
      I5 => \bytes00[15]_i_5_n_0\,
      O => \bytes04[13]_i_2_n_0\
    );
\bytes04[13]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \state[2]_i_9__0_n_0\,
      I3 => eth_rxd(1),
      O => \bytes04[13]_i_3_n_0\
    );
\bytes04[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes04[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes04[14]_i_2_n_0\,
      I5 => bytes04(14),
      O => \bytes04[14]_i_1_n_0\
    );
\bytes04[14]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes04[15]_i_4_n_0\,
      O => \bytes04[14]_i_2_n_0\
    );
\bytes04[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes04[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes04[15]_i_3_n_0\,
      I5 => bytes04(15),
      O => \bytes04[15]_i_1_n_0\
    );
\bytes04[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2AAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \dest_mac[39]_i_4_n_0\,
      I2 => \bytes00[15]_i_5_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => \state[2]_i_9__0_n_0\,
      O => \bytes04[15]_i_2_n_0\
    );
\bytes04[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes04[15]_i_4_n_0\,
      O => \bytes04[15]_i_3_n_0\
    );
\bytes04[15]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \state[2]_i_9__0_n_0\,
      O => \bytes04[15]_i_4_n_0\
    );
\bytes04[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes04[1]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes04[9]_i_3_n_0\,
      I5 => bytes04(1),
      O => \bytes04[1]_i_1_n_0\
    );
\bytes04[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2AAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \dest_mac[39]_i_4_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \bytes03[7]_i_3_n_0\,
      I4 => \source_mac[33]_i_2_n_0\,
      I5 => \state[2]_i_9__0_n_0\,
      O => \bytes04[1]_i_2_n_0\
    );
\bytes04[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes04[3]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes04[10]_i_2_n_0\,
      I5 => bytes04(2),
      O => \bytes04[2]_i_1_n_0\
    );
\bytes04[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes04[3]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes04[11]_i_3_n_0\,
      I5 => bytes04(3),
      O => \bytes04[3]_i_1_n_0\
    );
\bytes04[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2AAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \dest_mac[39]_i_4_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \bytes03[7]_i_3_n_0\,
      I4 => \source_mac[35]_i_2_n_0\,
      I5 => \state[2]_i_9__0_n_0\,
      O => \bytes04[3]_i_2_n_0\
    );
\bytes04[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes04[5]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes04[12]_i_2_n_0\,
      I5 => bytes04(4),
      O => \bytes04[4]_i_1_n_0\
    );
\bytes04[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes04[5]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes04[13]_i_3_n_0\,
      I5 => bytes04(5),
      O => \bytes04[5]_i_1_n_0\
    );
\bytes04[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2AAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \dest_mac[39]_i_4_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \bytes03[7]_i_3_n_0\,
      I4 => \source_mac[37]_i_2_n_0\,
      I5 => \state[2]_i_9__0_n_0\,
      O => \bytes04[5]_i_2_n_0\
    );
\bytes04[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes04[14]_i_2_n_0\,
      I3 => \bytes04[7]_i_2_n_0\,
      I4 => bytes04(6),
      O => \bytes04[6]_i_1_n_0\
    );
\bytes04[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes04[15]_i_3_n_0\,
      I3 => \bytes04[7]_i_2_n_0\,
      I4 => bytes04(7),
      O => \bytes04[7]_i_1_n_0\
    );
\bytes04[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D555555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \dest_mac[39]_i_4_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \bytes03[7]_i_3_n_0\,
      I4 => \bytes04[15]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes04[7]_i_2_n_0\
    );
\bytes04[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes04[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes04[8]_i_2_n_0\,
      I5 => bytes04(8),
      O => \bytes04[8]_i_1_n_0\
    );
\bytes04[8]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \state[2]_i_9__0_n_0\,
      I3 => eth_rxd(0),
      O => \bytes04[8]_i_2_n_0\
    );
\bytes04[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes04[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes04[9]_i_3_n_0\,
      I5 => bytes04(9),
      O => \bytes04[9]_i_1_n_0\
    );
\bytes04[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \state[2]_i_9__0_n_0\,
      I4 => \dest_mac[39]_i_4_n_0\,
      I5 => \bytes00[15]_i_5_n_0\,
      O => \bytes04[9]_i_2_n_0\
    );
\bytes04[9]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \state[2]_i_9__0_n_0\,
      I3 => eth_rxd(1),
      O => \bytes04[9]_i_3_n_0\
    );
\bytes04_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[0]_i_1_n_0\,
      Q => bytes04(0),
      R => '0'
    );
\bytes04_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[10]_i_1_n_0\,
      Q => bytes04(10),
      R => '0'
    );
\bytes04_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[11]_i_1_n_0\,
      Q => bytes04(11),
      R => '0'
    );
\bytes04_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[12]_i_1_n_0\,
      Q => bytes04(12),
      R => '0'
    );
\bytes04_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[13]_i_1_n_0\,
      Q => bytes04(13),
      R => '0'
    );
\bytes04_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[14]_i_1_n_0\,
      Q => bytes04(14),
      R => '0'
    );
\bytes04_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[15]_i_1_n_0\,
      Q => bytes04(15),
      R => '0'
    );
\bytes04_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[1]_i_1_n_0\,
      Q => bytes04(1),
      R => '0'
    );
\bytes04_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[2]_i_1_n_0\,
      Q => bytes04(2),
      R => '0'
    );
\bytes04_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[3]_i_1_n_0\,
      Q => bytes04(3),
      R => '0'
    );
\bytes04_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[4]_i_1_n_0\,
      Q => bytes04(4),
      R => '0'
    );
\bytes04_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[5]_i_1_n_0\,
      Q => bytes04(5),
      R => '0'
    );
\bytes04_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[6]_i_1_n_0\,
      Q => bytes04(6),
      R => '0'
    );
\bytes04_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[7]_i_1_n_0\,
      Q => bytes04(7),
      R => '0'
    );
\bytes04_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[8]_i_1_n_0\,
      Q => bytes04(8),
      R => '0'
    );
\bytes04_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes04[9]_i_1_n_0\,
      Q => bytes04(9),
      R => '0'
    );
\bytes05[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes05[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[1]_i_2_n_0\,
      I5 => bytes05(0),
      O => \bytes05[0]_i_1_n_0\
    );
\bytes05[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes05[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[11]_i_3_n_0\,
      I5 => bytes05(10),
      O => \bytes05[10]_i_1_n_0\
    );
\bytes05[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes05[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[11]_i_3_n_0\,
      I5 => bytes05(11),
      O => \bytes05[11]_i_1_n_0\
    );
\bytes05[11]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \byte_read_done[5]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      O => \bytes05[11]_i_2_n_0\
    );
\bytes05[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5D55555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[5]_i_2_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bytes05[15]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes05[11]_i_3_n_0\
    );
\bytes05[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes05[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[13]_i_3_n_0\,
      I5 => bytes05(12),
      O => \bytes05[12]_i_1_n_0\
    );
\bytes05[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes05[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[13]_i_3_n_0\,
      I5 => bytes05(13),
      O => \bytes05[13]_i_1_n_0\
    );
\bytes05[13]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \byte_read_done[5]_i_2_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      O => \bytes05[13]_i_2_n_0\
    );
\bytes05[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5D55555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[5]_i_2_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \bytes05[15]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes05[13]_i_3_n_0\
    );
\bytes05[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes05[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[15]_i_3_n_0\,
      I5 => bytes05(14),
      O => \bytes05[14]_i_1_n_0\
    );
\bytes05[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes05[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[15]_i_3_n_0\,
      I5 => bytes05(15),
      O => \bytes05[15]_i_1_n_0\
    );
\bytes05[15]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \byte_read_done[5]_i_2_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      O => \bytes05[15]_i_2_n_0\
    );
\bytes05[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D555555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes05[15]_i_4_n_0\,
      I2 => \byte_read_done[5]_i_2_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rstn,
      O => \bytes05[15]_i_3_n_0\
    );
\bytes05[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000020202000"
    )
        port map (
      I0 => \byte_read_done[5]_i_2_n_0\,
      I1 => \bytes04[15]_i_4_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_read_done[3]_i_4_n_0\,
      I5 => \bytes03[13]_i_4_n_0\,
      O => \bytes05[15]_i_4_n_0\
    );
\bytes05[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes05[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[1]_i_2_n_0\,
      I5 => bytes05(1),
      O => \bytes05[1]_i_1_n_0\
    );
\bytes05[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555557500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes05[7]_i_3_n_0\,
      I2 => \byte_read_done[5]_i_2_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rstn,
      O => \bytes05[1]_i_2_n_0\
    );
\bytes05[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes05[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[3]_i_2_n_0\,
      I5 => bytes05(2),
      O => \bytes05[2]_i_1_n_0\
    );
\bytes05[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes05[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[3]_i_2_n_0\,
      I5 => bytes05(3),
      O => \bytes05[3]_i_1_n_0\
    );
\bytes05[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5575555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes05[7]_i_3_n_0\,
      I2 => \byte_read_done[5]_i_2_n_0\,
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => ip_header_options1(1),
      I5 => eth_rstn,
      O => \bytes05[3]_i_2_n_0\
    );
\bytes05[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes05[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[5]_i_2_n_0\,
      I5 => bytes05(4),
      O => \bytes05[4]_i_1_n_0\
    );
\bytes05[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes05[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[5]_i_2_n_0\,
      I5 => bytes05(5),
      O => \bytes05[5]_i_1_n_0\
    );
\bytes05[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5575555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes05[7]_i_3_n_0\,
      I2 => \byte_read_done[5]_i_2_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rstn,
      O => \bytes05[5]_i_2_n_0\
    );
\bytes05[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes05[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[7]_i_2_n_0\,
      I5 => bytes05(6),
      O => \bytes05[6]_i_1_n_0\
    );
\bytes05[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes05[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[7]_i_2_n_0\,
      I5 => bytes05(7),
      O => \bytes05[7]_i_1_n_0\
    );
\bytes05[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7555555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes05[7]_i_3_n_0\,
      I2 => \byte_read_done[5]_i_2_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rstn,
      O => \bytes05[7]_i_2_n_0\
    );
\bytes05[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFDFDFFFFFFFFFFF"
    )
        port map (
      I0 => \bytes03[7]_i_3_n_0\,
      I1 => \bytes04[15]_i_4_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_read_done[3]_i_4_n_0\,
      I5 => \byte_read_done[5]_i_2_n_0\,
      O => \bytes05[7]_i_3_n_0\
    );
\bytes05[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes05[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[9]_i_3_n_0\,
      I5 => bytes05(8),
      O => \bytes05[8]_i_1_n_0\
    );
\bytes05[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes05[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes05[9]_i_3_n_0\,
      I5 => bytes05(9),
      O => \bytes05[9]_i_1_n_0\
    );
\bytes05[9]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \byte_read_done[5]_i_2_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      O => \bytes05[9]_i_2_n_0\
    );
\bytes05[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555D555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[5]_i_2_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \bytes05[15]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes05[9]_i_3_n_0\
    );
\bytes05_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[0]_i_1_n_0\,
      Q => bytes05(0),
      R => '0'
    );
\bytes05_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[10]_i_1_n_0\,
      Q => bytes05(10),
      R => '0'
    );
\bytes05_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[11]_i_1_n_0\,
      Q => bytes05(11),
      R => '0'
    );
\bytes05_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[12]_i_1_n_0\,
      Q => bytes05(12),
      R => '0'
    );
\bytes05_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[13]_i_1_n_0\,
      Q => bytes05(13),
      R => '0'
    );
\bytes05_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[14]_i_1_n_0\,
      Q => bytes05(14),
      R => '0'
    );
\bytes05_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[15]_i_1_n_0\,
      Q => bytes05(15),
      R => '0'
    );
\bytes05_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[1]_i_1_n_0\,
      Q => bytes05(1),
      R => '0'
    );
\bytes05_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[2]_i_1_n_0\,
      Q => bytes05(2),
      R => '0'
    );
\bytes05_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[3]_i_1_n_0\,
      Q => bytes05(3),
      R => '0'
    );
\bytes05_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[4]_i_1_n_0\,
      Q => bytes05(4),
      R => '0'
    );
\bytes05_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[5]_i_1_n_0\,
      Q => bytes05(5),
      R => '0'
    );
\bytes05_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[6]_i_1_n_0\,
      Q => bytes05(6),
      R => '0'
    );
\bytes05_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[7]_i_1_n_0\,
      Q => bytes05(7),
      R => '0'
    );
\bytes05_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[8]_i_1_n_0\,
      Q => bytes05(8),
      R => '0'
    );
\bytes05_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes05[9]_i_1_n_0\,
      Q => bytes05(9),
      R => '0'
    );
\bytes06[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes06[1]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \eth_prot_type[8]_i_2_n_0\,
      I5 => bytes06(0),
      O => \bytes06[0]_i_1_n_0\
    );
\bytes06[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes06[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \eth_prot_type[10]_i_2_n_0\,
      I5 => bytes06(10),
      O => \bytes06[10]_i_1_n_0\
    );
\bytes06[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes06[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \eth_prot_type[11]_i_2_n_0\,
      I5 => bytes06(11),
      O => \bytes06[11]_i_1_n_0\
    );
\bytes06[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAA8A"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes06[13]_i_3_n_0\,
      I2 => \source_mac[35]_i_2_n_0\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      I4 => \byte_count_reg[1]_rep_n_0\,
      I5 => \byte_read_done[6]_i_3_n_0\,
      O => \bytes06[11]_i_2_n_0\
    );
\bytes06[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes06[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \eth_prot_type[12]_i_2_n_0\,
      I5 => bytes06(12),
      O => \bytes06[12]_i_1_n_0\
    );
\bytes06[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes06[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \eth_prot_type[13]_i_2_n_0\,
      I5 => bytes06(13),
      O => \bytes06[13]_i_1_n_0\
    );
\bytes06[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAA8A"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes06[13]_i_3_n_0\,
      I2 => \source_mac[37]_i_2_n_0\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      I4 => \byte_count_reg[1]_rep_n_0\,
      I5 => \byte_read_done[6]_i_3_n_0\,
      O => \bytes06[13]_i_2_n_0\
    );
\bytes06[13]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFD"
    )
        port map (
      I0 => \state[2]_i_9__0_n_0\,
      I1 => \bytes06[13]_i_4_n_0\,
      I2 => \state[3]_i_14_n_0\,
      I3 => \bytes06[13]_i_5_n_0\,
      I4 => \byte_read_done[5]_i_2_n_0\,
      O => \bytes06[13]_i_3_n_0\
    );
\bytes06[13]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFFFFFF"
    )
        port map (
      I0 => unknown_request1_reg_n_0,
      I1 => unknown_request4_reg_n_0,
      I2 => unknown_request3_reg_n_0,
      I3 => unknown_request2,
      I4 => start_crc_i_2_n_0,
      I5 => \byte_read_done[3]_i_4_n_0\,
      O => \bytes06[13]_i_4_n_0\
    );
\bytes06[13]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      O => \bytes06[13]_i_5_n_0\
    );
\bytes06[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \eth_prot_type[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes06[15]_i_2_n_0\,
      I5 => bytes06(14),
      O => \bytes06[14]_i_1_n_0\
    );
\bytes06[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \eth_prot_type[15]_i_2_n_0\,
      I1 => eth_rxd(1),
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes06[15]_i_2_n_0\,
      I5 => bytes06(15),
      O => \bytes06[15]_i_1_n_0\
    );
\bytes06[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes06[15]_i_3_n_0\,
      O => \bytes06[15]_i_2_n_0\
    );
\bytes06[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAA8A"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes06[13]_i_3_n_0\,
      I2 => \byte_read_done[6]_i_2_n_0\,
      I3 => \byte_count_reg[0]_rep__0_n_0\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \byte_read_done[6]_i_3_n_0\,
      O => \bytes06[15]_i_3_n_0\
    );
\bytes06[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes06[1]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \eth_prot_type[9]_i_2_n_0\,
      I5 => bytes06(1),
      O => \bytes06[1]_i_1_n_0\
    );
\bytes06[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA8AAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes06[13]_i_3_n_0\,
      I2 => \byte_count[1]_i_5_n_0\,
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => ip_header_options1(1),
      I5 => \byte_count_reg[0]_rep_n_0\,
      O => \bytes06[1]_i_2_n_0\
    );
\bytes06[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes06[3]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \eth_prot_type[10]_i_2_n_0\,
      I5 => bytes06(2),
      O => \bytes06[2]_i_1_n_0\
    );
\bytes06[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes06[3]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \eth_prot_type[11]_i_2_n_0\,
      I5 => bytes06(3),
      O => \bytes06[3]_i_1_n_0\
    );
\bytes06[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA8AAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes06[13]_i_3_n_0\,
      I2 => \byte_count[1]_i_5_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => \byte_count_reg[0]_rep_n_0\,
      O => \bytes06[3]_i_2_n_0\
    );
\bytes06[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes06[5]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \eth_prot_type[12]_i_2_n_0\,
      I5 => bytes06(4),
      O => \bytes06[4]_i_1_n_0\
    );
\bytes06[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes06[5]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \eth_prot_type[13]_i_2_n_0\,
      I5 => bytes06(5),
      O => \bytes06[5]_i_1_n_0\
    );
\bytes06[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA8AAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes06[13]_i_3_n_0\,
      I2 => \byte_count[1]_i_5_n_0\,
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => ip_header_options1(1),
      I5 => \byte_count_reg[0]_rep__0_n_0\,
      O => \bytes06[5]_i_2_n_0\
    );
\bytes06[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \eth_prot_type[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes06[7]_i_2_n_0\,
      I5 => bytes06(6),
      O => \bytes06[6]_i_1_n_0\
    );
\bytes06[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => \eth_prot_type[15]_i_2_n_0\,
      I1 => eth_rxd(1),
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes06[7]_i_2_n_0\,
      I5 => bytes06(7),
      O => \bytes06[7]_i_1_n_0\
    );
\bytes06[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes06[7]_i_3_n_0\,
      O => \bytes06[7]_i_2_n_0\
    );
\bytes06[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAA8AAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes06[13]_i_3_n_0\,
      I2 => \byte_read_done[6]_i_3_n_0\,
      I3 => \byte_read_done[6]_i_2_n_0\,
      I4 => \byte_count_reg[0]_rep__0_n_0\,
      I5 => \byte_count_reg_n_0_[1]\,
      O => \bytes06[7]_i_3_n_0\
    );
\bytes06[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes06[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \eth_prot_type[8]_i_2_n_0\,
      I5 => bytes06(8),
      O => \bytes06[8]_i_1_n_0\
    );
\bytes06[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes06[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \eth_prot_type[9]_i_2_n_0\,
      I5 => bytes06(9),
      O => \bytes06[9]_i_1_n_0\
    );
\bytes06[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAA8A"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes06[13]_i_3_n_0\,
      I2 => \source_mac[33]_i_2_n_0\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      I4 => \byte_count_reg[1]_rep_n_0\,
      I5 => \byte_read_done[6]_i_3_n_0\,
      O => \bytes06[9]_i_2_n_0\
    );
\bytes06_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[0]_i_1_n_0\,
      Q => bytes06(0),
      R => '0'
    );
\bytes06_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[10]_i_1_n_0\,
      Q => bytes06(10),
      R => '0'
    );
\bytes06_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[11]_i_1_n_0\,
      Q => bytes06(11),
      R => '0'
    );
\bytes06_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[12]_i_1_n_0\,
      Q => bytes06(12),
      R => '0'
    );
\bytes06_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[13]_i_1_n_0\,
      Q => bytes06(13),
      R => '0'
    );
\bytes06_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[14]_i_1_n_0\,
      Q => bytes06(14),
      R => '0'
    );
\bytes06_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[15]_i_1_n_0\,
      Q => bytes06(15),
      R => '0'
    );
\bytes06_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[1]_i_1_n_0\,
      Q => bytes06(1),
      R => '0'
    );
\bytes06_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[2]_i_1_n_0\,
      Q => bytes06(2),
      R => '0'
    );
\bytes06_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[3]_i_1_n_0\,
      Q => bytes06(3),
      R => '0'
    );
\bytes06_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[4]_i_1_n_0\,
      Q => bytes06(4),
      R => '0'
    );
\bytes06_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[5]_i_1_n_0\,
      Q => bytes06(5),
      R => '0'
    );
\bytes06_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[6]_i_1_n_0\,
      Q => bytes06(6),
      R => '0'
    );
\bytes06_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[7]_i_1_n_0\,
      Q => bytes06(7),
      R => '0'
    );
\bytes06_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[8]_i_1_n_0\,
      Q => bytes06(8),
      R => '0'
    );
\bytes06_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes06[9]_i_1_n_0\,
      Q => bytes06(9),
      R => '0'
    );
\bytes07[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes07[8]_i_2_n_0\,
      I3 => \bytes07[1]_i_2_n_0\,
      I4 => bytes07(0),
      O => \bytes07[0]_i_1_n_0\
    );
\bytes07[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes07[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes07[10]_i_2_n_0\,
      I5 => bytes07(10),
      O => \bytes07[10]_i_1_n_0\
    );
\bytes07[10]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes07[11]_i_4_n_0\,
      O => \bytes07[10]_i_2_n_0\
    );
\bytes07[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes07[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes07[11]_i_3_n_0\,
      I5 => bytes07(11),
      O => \bytes07[11]_i_1_n_0\
    );
\bytes07[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA2AAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[6]_i_3_n_0\,
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => ip_header_options1(1),
      I5 => \bytes07[15]_i_4_n_0\,
      O => \bytes07[11]_i_2_n_0\
    );
\bytes07[11]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes07[11]_i_4_n_0\,
      O => \bytes07[11]_i_3_n_0\
    );
\bytes07[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_read_done[12]_i_5_n_0\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[2]\,
      I5 => \source_mac[35]_i_2_n_0\,
      O => \bytes07[11]_i_4_n_0\
    );
\bytes07[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes07[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes07[12]_i_2_n_0\,
      I5 => bytes07(12),
      O => \bytes07[12]_i_1_n_0\
    );
\bytes07[12]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes07[13]_i_4_n_0\,
      O => \bytes07[12]_i_2_n_0\
    );
\bytes07[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes07[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes07[13]_i_3_n_0\,
      I5 => bytes07(13),
      O => \bytes07[13]_i_1_n_0\
    );
\bytes07[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA2AAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[6]_i_3_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => \bytes07[15]_i_4_n_0\,
      O => \bytes07[13]_i_2_n_0\
    );
\bytes07[13]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes07[13]_i_4_n_0\,
      O => \bytes07[13]_i_3_n_0\
    );
\bytes07[13]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_read_done[12]_i_5_n_0\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[2]\,
      I5 => \source_mac[37]_i_2_n_0\,
      O => \bytes07[13]_i_4_n_0\
    );
\bytes07[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes07[14]_i_2_n_0\,
      I3 => \bytes07[15]_i_3_n_0\,
      I4 => bytes07(14),
      O => \bytes07[14]_i_1_n_0\
    );
\bytes07[14]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \byte_read_done[7]_i_3_n_0\,
      O => \bytes07[14]_i_2_n_0\
    );
\bytes07[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes07[15]_i_2_n_0\,
      I3 => \bytes07[15]_i_3_n_0\,
      I4 => bytes07(15),
      O => \bytes07[15]_i_1_n_0\
    );
\bytes07[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \byte_read_done[7]_i_3_n_0\,
      O => \bytes07[15]_i_2_n_0\
    );
\bytes07[15]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D500"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes07[15]_i_4_n_0\,
      I2 => \byte_read_done[7]_i_3_n_0\,
      I3 => eth_rstn,
      O => \bytes07[15]_i_3_n_0\
    );
\bytes07[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000004000000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => \byte_count[10]_i_15_n_0\,
      O => \bytes07[15]_i_4_n_0\
    );
\bytes07[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes07[9]_i_3_n_0\,
      I3 => \bytes07[1]_i_2_n_0\,
      I4 => bytes07(1),
      O => \bytes07[1]_i_1_n_0\
    );
\bytes07[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55570000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes07[5]_i_3_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => ip_header_options1(1),
      I4 => eth_rstn,
      O => \bytes07[1]_i_2_n_0\
    );
\bytes07[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes07[10]_i_2_n_0\,
      I3 => \bytes07[3]_i_2_n_0\,
      I4 => bytes07(2),
      O => \bytes07[2]_i_1_n_0\
    );
\bytes07[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes07[11]_i_3_n_0\,
      I3 => \bytes07[3]_i_2_n_0\,
      I4 => bytes07(3),
      O => \bytes07[3]_i_1_n_0\
    );
\bytes07[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55750000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes07[5]_i_3_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => eth_rstn,
      O => \bytes07[3]_i_2_n_0\
    );
\bytes07[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes07[12]_i_2_n_0\,
      I3 => \bytes07[5]_i_2_n_0\,
      I4 => bytes07(4),
      O => \bytes07[4]_i_1_n_0\
    );
\bytes07[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes07[13]_i_3_n_0\,
      I3 => \bytes07[5]_i_2_n_0\,
      I4 => bytes07(5),
      O => \bytes07[5]_i_1_n_0\
    );
\bytes07[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55750000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes07[5]_i_3_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => ip_header_options1(1),
      I4 => eth_rstn,
      O => \bytes07[5]_i_2_n_0\
    );
\bytes07[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \byte_count_reg[1]_rep_n_0\,
      I1 => \byte_read_done[6]_i_3_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \dest_mac[23]_i_2_n_0\,
      I4 => \state_reg_n_0_[0]\,
      I5 => \byte_read_done[3]_i_3_n_0\,
      O => \bytes07[5]_i_3_n_0\
    );
\bytes07[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes07[7]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes07[14]_i_2_n_0\,
      I5 => bytes07(6),
      O => \bytes07[6]_i_1_n_0\
    );
\bytes07[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes07[7]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes07[15]_i_2_n_0\,
      I5 => bytes07(7),
      O => \bytes07[7]_i_1_n_0\
    );
\bytes07[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2AAAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[6]_i_3_n_0\,
      I3 => \bytes03[7]_i_3_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => \byte_read_done[6]_i_2_n_0\,
      O => \bytes07[7]_i_2_n_0\
    );
\bytes07[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes07[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes07[8]_i_2_n_0\,
      I5 => bytes07(8),
      O => \bytes07[8]_i_1_n_0\
    );
\bytes07[8]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes07[9]_i_4_n_0\,
      O => \bytes07[8]_i_2_n_0\
    );
\bytes07[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes07[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes07[9]_i_3_n_0\,
      I5 => bytes07(9),
      O => \bytes07[9]_i_1_n_0\
    );
\bytes07[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA2AAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[6]_i_3_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => \bytes07[15]_i_4_n_0\,
      O => \bytes07[9]_i_2_n_0\
    );
\bytes07[9]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes07[9]_i_4_n_0\,
      O => \bytes07[9]_i_3_n_0\
    );
\bytes07[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_read_done[12]_i_5_n_0\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[2]\,
      I5 => \source_mac[33]_i_2_n_0\,
      O => \bytes07[9]_i_4_n_0\
    );
\bytes07_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[0]_i_1_n_0\,
      Q => bytes07(0),
      R => '0'
    );
\bytes07_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[10]_i_1_n_0\,
      Q => bytes07(10),
      R => '0'
    );
\bytes07_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[11]_i_1_n_0\,
      Q => bytes07(11),
      R => '0'
    );
\bytes07_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[12]_i_1_n_0\,
      Q => bytes07(12),
      R => '0'
    );
\bytes07_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[13]_i_1_n_0\,
      Q => bytes07(13),
      R => '0'
    );
\bytes07_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[14]_i_1_n_0\,
      Q => bytes07(14),
      R => '0'
    );
\bytes07_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[15]_i_1_n_0\,
      Q => bytes07(15),
      R => '0'
    );
\bytes07_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[1]_i_1_n_0\,
      Q => bytes07(1),
      R => '0'
    );
\bytes07_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[2]_i_1_n_0\,
      Q => bytes07(2),
      R => '0'
    );
\bytes07_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[3]_i_1_n_0\,
      Q => bytes07(3),
      R => '0'
    );
\bytes07_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[4]_i_1_n_0\,
      Q => bytes07(4),
      R => '0'
    );
\bytes07_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[5]_i_1_n_0\,
      Q => bytes07(5),
      R => '0'
    );
\bytes07_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[6]_i_1_n_0\,
      Q => bytes07(6),
      R => '0'
    );
\bytes07_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[7]_i_1_n_0\,
      Q => bytes07(7),
      R => '0'
    );
\bytes07_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[8]_i_1_n_0\,
      Q => bytes07(8),
      R => '0'
    );
\bytes07_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes07[9]_i_1_n_0\,
      Q => bytes07(9),
      R => '0'
    );
\bytes08[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes08[1]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes08[8]_i_2_n_0\,
      I5 => bytes08(0),
      O => \bytes08[0]_i_1_n_0\
    );
\bytes08[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes08[10]_i_2_n_0\,
      I3 => \bytes08[11]_i_3_n_0\,
      I4 => bytes08(10),
      O => \bytes08[10]_i_1_n_0\
    );
\bytes08[10]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes08[11]_i_4_n_0\,
      O => \bytes08[10]_i_2_n_0\
    );
\bytes08[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes08[11]_i_2_n_0\,
      I3 => \bytes08[11]_i_3_n_0\,
      I4 => bytes08(11),
      O => \bytes08[11]_i_1_n_0\
    );
\bytes08[11]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes08[11]_i_4_n_0\,
      O => \bytes08[11]_i_2_n_0\
    );
\bytes08[11]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55750000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes08[15]_i_5_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => eth_rstn,
      O => \bytes08[11]_i_3_n_0\
    );
\bytes08[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFFFFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_read_done[12]_i_5_n_0\,
      I4 => \byte_count_reg_n_0_[4]\,
      I5 => \source_mac[35]_i_2_n_0\,
      O => \bytes08[11]_i_4_n_0\
    );
\bytes08[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes08[12]_i_2_n_0\,
      I3 => \bytes08[13]_i_3_n_0\,
      I4 => bytes08(12),
      O => \bytes08[12]_i_1_n_0\
    );
\bytes08[12]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes08[13]_i_4_n_0\,
      O => \bytes08[12]_i_2_n_0\
    );
\bytes08[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes08[13]_i_2_n_0\,
      I3 => \bytes08[13]_i_3_n_0\,
      I4 => bytes08(13),
      O => \bytes08[13]_i_1_n_0\
    );
\bytes08[13]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes08[13]_i_4_n_0\,
      O => \bytes08[13]_i_2_n_0\
    );
\bytes08[13]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55750000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes08[15]_i_5_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => ip_header_options1(1),
      I4 => eth_rstn,
      O => \bytes08[13]_i_3_n_0\
    );
\bytes08[13]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFFFFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_read_done[12]_i_5_n_0\,
      I4 => \byte_count_reg_n_0_[4]\,
      I5 => \source_mac[37]_i_2_n_0\,
      O => \bytes08[13]_i_4_n_0\
    );
\bytes08[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes08[14]_i_2_n_0\,
      I3 => \bytes08[15]_i_3_n_0\,
      I4 => bytes08(14),
      O => \bytes08[14]_i_1_n_0\
    );
\bytes08[14]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes08[15]_i_4_n_0\,
      O => \bytes08[14]_i_2_n_0\
    );
\bytes08[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes08[15]_i_2_n_0\,
      I3 => \bytes08[15]_i_3_n_0\,
      I4 => bytes08(15),
      O => \bytes08[15]_i_1_n_0\
    );
\bytes08[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes08[15]_i_4_n_0\,
      O => \bytes08[15]_i_2_n_0\
    );
\bytes08[15]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"75550000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes08[15]_i_5_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => ip_header_options1(1),
      I4 => eth_rstn,
      O => \bytes08[15]_i_3_n_0\
    );
\bytes08[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \byte_read_done[6]_i_2_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_read_done[12]_i_5_n_0\,
      I5 => \byte_count_reg_n_0_[4]\,
      O => \bytes08[15]_i_4_n_0\
    );
\bytes08[15]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFBFF"
    )
        port map (
      I0 => \byte_read_done[8]_i_2_n_0\,
      I1 => \byte_read_done[3]_i_3_n_0\,
      I2 => \byte_read_done[11]_i_3_n_0\,
      I3 => \state_reg_n_0_[0]\,
      I4 => \byte_count_reg[0]_rep__0_n_0\,
      I5 => \byte_read_done[7]_i_3_n_0\,
      O => \bytes08[15]_i_5_n_0\
    );
\bytes08[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes08[1]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes08[9]_i_2_n_0\,
      I5 => bytes08(1),
      O => \bytes08[1]_i_1_n_0\
    );
\bytes08[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA8AAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[8]_i_2_n_0\,
      I2 => \source_mac[33]_i_2_n_0\,
      I3 => \byte_read_done[3]_i_3_n_0\,
      I4 => \bytes03[7]_i_3_n_0\,
      I5 => \byte_read_done[7]_i_3_n_0\,
      O => \bytes08[1]_i_2_n_0\
    );
\bytes08[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes08[3]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes08[10]_i_2_n_0\,
      I5 => bytes08(2),
      O => \bytes08[2]_i_1_n_0\
    );
\bytes08[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes08[3]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes08[11]_i_2_n_0\,
      I5 => bytes08(3),
      O => \bytes08[3]_i_1_n_0\
    );
\bytes08[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA8AAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[8]_i_2_n_0\,
      I2 => \source_mac[35]_i_2_n_0\,
      I3 => \byte_read_done[3]_i_3_n_0\,
      I4 => \bytes03[7]_i_3_n_0\,
      I5 => \byte_read_done[7]_i_3_n_0\,
      O => \bytes08[3]_i_2_n_0\
    );
\bytes08[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes08[5]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes08[12]_i_2_n_0\,
      I5 => bytes08(4),
      O => \bytes08[4]_i_1_n_0\
    );
\bytes08[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes08[5]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes08[13]_i_2_n_0\,
      I5 => bytes08(5),
      O => \bytes08[5]_i_1_n_0\
    );
\bytes08[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA8AAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[8]_i_2_n_0\,
      I2 => \source_mac[37]_i_2_n_0\,
      I3 => \byte_read_done[3]_i_3_n_0\,
      I4 => \bytes03[7]_i_3_n_0\,
      I5 => \byte_read_done[7]_i_3_n_0\,
      O => \bytes08[5]_i_2_n_0\
    );
\bytes08[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes08[7]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes08[14]_i_2_n_0\,
      I5 => bytes08(6),
      O => \bytes08[6]_i_1_n_0\
    );
\bytes08[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes08[7]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes08[15]_i_2_n_0\,
      I5 => bytes08(7),
      O => \bytes08[7]_i_1_n_0\
    );
\bytes08[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA8AAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[8]_i_2_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \bytes03[7]_i_3_n_0\,
      I4 => \byte_read_done[7]_i_3_n_0\,
      I5 => \byte_read_done[6]_i_2_n_0\,
      O => \bytes08[7]_i_2_n_0\
    );
\bytes08[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes08[8]_i_2_n_0\,
      I3 => \bytes08[9]_i_3_n_0\,
      I4 => bytes08(8),
      O => \bytes08[8]_i_1_n_0\
    );
\bytes08[8]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes08[9]_i_4_n_0\,
      O => \bytes08[8]_i_2_n_0\
    );
\bytes08[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes08[9]_i_2_n_0\,
      I3 => \bytes08[9]_i_3_n_0\,
      I4 => bytes08(9),
      O => \bytes08[9]_i_1_n_0\
    );
\bytes08[9]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes08[9]_i_4_n_0\,
      O => \bytes08[9]_i_2_n_0\
    );
\bytes08[9]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55570000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes08[15]_i_5_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => ip_header_options1(1),
      I4 => eth_rstn,
      O => \bytes08[9]_i_3_n_0\
    );
\bytes08[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFFFFFFFFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_read_done[12]_i_5_n_0\,
      I4 => \byte_count_reg_n_0_[4]\,
      I5 => \source_mac[33]_i_2_n_0\,
      O => \bytes08[9]_i_4_n_0\
    );
\bytes08_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[0]_i_1_n_0\,
      Q => bytes08(0),
      R => '0'
    );
\bytes08_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[10]_i_1_n_0\,
      Q => bytes08(10),
      R => '0'
    );
\bytes08_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[11]_i_1_n_0\,
      Q => bytes08(11),
      R => '0'
    );
\bytes08_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[12]_i_1_n_0\,
      Q => bytes08(12),
      R => '0'
    );
\bytes08_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[13]_i_1_n_0\,
      Q => bytes08(13),
      R => '0'
    );
\bytes08_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[14]_i_1_n_0\,
      Q => bytes08(14),
      R => '0'
    );
\bytes08_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[15]_i_1_n_0\,
      Q => bytes08(15),
      R => '0'
    );
\bytes08_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[1]_i_1_n_0\,
      Q => bytes08(1),
      R => '0'
    );
\bytes08_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[2]_i_1_n_0\,
      Q => bytes08(2),
      R => '0'
    );
\bytes08_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[3]_i_1_n_0\,
      Q => bytes08(3),
      R => '0'
    );
\bytes08_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[4]_i_1_n_0\,
      Q => bytes08(4),
      R => '0'
    );
\bytes08_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[5]_i_1_n_0\,
      Q => bytes08(5),
      R => '0'
    );
\bytes08_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[6]_i_1_n_0\,
      Q => bytes08(6),
      R => '0'
    );
\bytes08_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[7]_i_1_n_0\,
      Q => bytes08(7),
      R => '0'
    );
\bytes08_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[8]_i_1_n_0\,
      Q => bytes08(8),
      R => '0'
    );
\bytes08_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes08[9]_i_1_n_0\,
      Q => bytes08(9),
      R => '0'
    );
\bytes09[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes09[8]_i_2_n_0\,
      I3 => \bytes09[1]_i_2_n_0\,
      I4 => bytes09(0),
      O => \bytes09[0]_i_1_n_0\
    );
\bytes09[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes09[10]_i_2_n_0\,
      I3 => \bytes09[11]_i_3_n_0\,
      I4 => bytes09(10),
      O => \bytes09[10]_i_1_n_0\
    );
\bytes09[10]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \byte_read_done[9]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => eth_rxd(0),
      O => \bytes09[10]_i_2_n_0\
    );
\bytes09[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes09[11]_i_2_n_0\,
      I3 => \bytes09[11]_i_3_n_0\,
      I4 => bytes09(11),
      O => \bytes09[11]_i_1_n_0\
    );
\bytes09[11]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \byte_read_done[9]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => eth_rxd(1),
      O => \bytes09[11]_i_2_n_0\
    );
\bytes09[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5755555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[9]_i_2_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bytes09[15]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes09[11]_i_3_n_0\
    );
\bytes09[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes09[12]_i_2_n_0\,
      I3 => \bytes09[13]_i_3_n_0\,
      I4 => bytes09(12),
      O => \bytes09[12]_i_1_n_0\
    );
\bytes09[12]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \byte_read_done[9]_i_2_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => eth_rxd(0),
      O => \bytes09[12]_i_2_n_0\
    );
\bytes09[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes09[13]_i_2_n_0\,
      I3 => \bytes09[13]_i_3_n_0\,
      I4 => bytes09(13),
      O => \bytes09[13]_i_1_n_0\
    );
\bytes09[13]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \byte_read_done[9]_i_2_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => eth_rxd(1),
      O => \bytes09[13]_i_2_n_0\
    );
\bytes09[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5755555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[9]_i_2_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \bytes09[15]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes09[13]_i_3_n_0\
    );
\bytes09[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes09[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes09[15]_i_3_n_0\,
      I5 => bytes09(14),
      O => \bytes09[14]_i_1_n_0\
    );
\bytes09[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes09[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes09[15]_i_3_n_0\,
      I5 => bytes09(15),
      O => \bytes09[15]_i_1_n_0\
    );
\bytes09[15]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[9]_i_2_n_0\,
      O => \bytes09[15]_i_2_n_0\
    );
\bytes09[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555D55500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes09[15]_i_4_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \byte_read_done[9]_i_2_n_0\,
      I5 => eth_rstn,
      O => \bytes09[15]_i_3_n_0\
    );
\bytes09[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008880"
    )
        port map (
      I0 => \bytes13[15]_i_5_n_0\,
      I1 => \byte_read_done[3]_i_3_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_read_done[3]_i_4_n_0\,
      I4 => \bytes08[15]_i_4_n_0\,
      I5 => \byte_read_done[9]_i_2_n_0\,
      O => \bytes09[15]_i_4_n_0\
    );
\bytes09[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes09[9]_i_2_n_0\,
      I3 => \bytes09[1]_i_2_n_0\,
      I4 => bytes09(1),
      O => \bytes09[1]_i_1_n_0\
    );
\bytes09[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555700000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes09[7]_i_3_n_0\,
      I2 => \byte_read_done[9]_i_2_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rstn,
      O => \bytes09[1]_i_2_n_0\
    );
\bytes09[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes09[10]_i_2_n_0\,
      I3 => \bytes09[3]_i_2_n_0\,
      I4 => bytes09(2),
      O => \bytes09[2]_i_1_n_0\
    );
\bytes09[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes09[11]_i_2_n_0\,
      I3 => \bytes09[3]_i_2_n_0\,
      I4 => bytes09(3),
      O => \bytes09[3]_i_1_n_0\
    );
\bytes09[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes09[7]_i_3_n_0\,
      I2 => \byte_read_done[9]_i_2_n_0\,
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => ip_header_options1(1),
      I5 => eth_rstn,
      O => \bytes09[3]_i_2_n_0\
    );
\bytes09[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes09[12]_i_2_n_0\,
      I3 => \bytes09[5]_i_2_n_0\,
      I4 => bytes09(4),
      O => \bytes09[4]_i_1_n_0\
    );
\bytes09[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg_n_0_[0]\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes09[13]_i_2_n_0\,
      I3 => \bytes09[5]_i_2_n_0\,
      I4 => bytes09(5),
      O => \bytes09[5]_i_1_n_0\
    );
\bytes09[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes09[7]_i_3_n_0\,
      I2 => \byte_read_done[9]_i_2_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rstn,
      O => \bytes09[5]_i_2_n_0\
    );
\bytes09[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes09[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes09[7]_i_2_n_0\,
      I5 => bytes09(6),
      O => \bytes09[6]_i_1_n_0\
    );
\bytes09[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes09[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep__1_n_0\,
      I4 => \bytes09[7]_i_2_n_0\,
      I5 => bytes09(7),
      O => \bytes09[7]_i_1_n_0\
    );
\bytes09[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555755500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes09[7]_i_3_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \byte_read_done[9]_i_2_n_0\,
      I5 => eth_rstn,
      O => \bytes09[7]_i_2_n_0\
    );
\bytes09[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFBBBF"
    )
        port map (
      I0 => \bytes13[7]_i_3_n_0\,
      I1 => \byte_read_done[3]_i_3_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_read_done[3]_i_4_n_0\,
      I4 => \bytes08[15]_i_4_n_0\,
      I5 => \byte_read_done[9]_i_2_n_0\,
      O => \bytes09[7]_i_3_n_0\
    );
\bytes09[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes09[8]_i_2_n_0\,
      I3 => \bytes09[9]_i_3_n_0\,
      I4 => bytes09(8),
      O => \bytes09[8]_i_1_n_0\
    );
\bytes09[8]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => \byte_read_done[9]_i_2_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => eth_rxd(0),
      O => \bytes09[8]_i_2_n_0\
    );
\bytes09[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__1_n_0\,
      I2 => \bytes09[9]_i_2_n_0\,
      I3 => \bytes09[9]_i_3_n_0\,
      I4 => bytes09(9),
      O => \bytes09[9]_i_1_n_0\
    );
\bytes09[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => \byte_read_done[9]_i_2_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => eth_rxd(1),
      O => \bytes09[9]_i_2_n_0\
    );
\bytes09[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[9]_i_2_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \bytes09[15]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes09[9]_i_3_n_0\
    );
\bytes09_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[0]_i_1_n_0\,
      Q => bytes09(0),
      R => '0'
    );
\bytes09_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[10]_i_1_n_0\,
      Q => bytes09(10),
      R => '0'
    );
\bytes09_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[11]_i_1_n_0\,
      Q => bytes09(11),
      R => '0'
    );
\bytes09_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[12]_i_1_n_0\,
      Q => bytes09(12),
      R => '0'
    );
\bytes09_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[13]_i_1_n_0\,
      Q => bytes09(13),
      R => '0'
    );
\bytes09_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[14]_i_1_n_0\,
      Q => bytes09(14),
      R => '0'
    );
\bytes09_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[15]_i_1_n_0\,
      Q => bytes09(15),
      R => '0'
    );
\bytes09_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[1]_i_1_n_0\,
      Q => bytes09(1),
      R => '0'
    );
\bytes09_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[2]_i_1_n_0\,
      Q => bytes09(2),
      R => '0'
    );
\bytes09_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[3]_i_1_n_0\,
      Q => bytes09(3),
      R => '0'
    );
\bytes09_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[4]_i_1_n_0\,
      Q => bytes09(4),
      R => '0'
    );
\bytes09_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[5]_i_1_n_0\,
      Q => bytes09(5),
      R => '0'
    );
\bytes09_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[6]_i_1_n_0\,
      Q => bytes09(6),
      R => '0'
    );
\bytes09_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[7]_i_1_n_0\,
      Q => bytes09(7),
      R => '0'
    );
\bytes09_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[8]_i_1_n_0\,
      Q => bytes09(8),
      R => '0'
    );
\bytes09_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes09[9]_i_1_n_0\,
      Q => bytes09(9),
      R => '0'
    );
\bytes10[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes10[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes10[1]_i_2_n_0\,
      I5 => bytes10(0),
      O => \bytes10[0]_i_1_n_0\
    );
\bytes10[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes10[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes10[11]_i_3_n_0\,
      I5 => bytes10(10),
      O => \bytes10[10]_i_1_n_0\
    );
\bytes10[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes10[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes10[11]_i_3_n_0\,
      I5 => bytes10(11),
      O => \bytes10[11]_i_1_n_0\
    );
\bytes10[11]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \bit_count_reg[1]_rep_n_0\,
      I1 => ip_header_options1(1),
      I2 => \byte_read_done[10]_i_2_n_0\,
      O => \bytes10[11]_i_2_n_0\
    );
\bytes10[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5575555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \byte_read_done[10]_i_2_n_0\,
      I4 => \bytes10[13]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes10[11]_i_3_n_0\
    );
\bytes10[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes10[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes10[13]_i_3_n_0\,
      I5 => bytes10(12),
      O => \bytes10[12]_i_1_n_0\
    );
\bytes10[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes10[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes10[13]_i_3_n_0\,
      I5 => bytes10(13),
      O => \bytes10[13]_i_1_n_0\
    );
\bytes10[13]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[10]_i_2_n_0\,
      O => \bytes10[13]_i_2_n_0\
    );
\bytes10[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555D5500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes10[13]_i_4_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \byte_read_done[10]_i_2_n_0\,
      I5 => eth_rstn,
      O => \bytes10[13]_i_3_n_0\
    );
\bytes10[13]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00100000"
    )
        port map (
      I0 => \byte_read_done[10]_i_2_n_0\,
      I1 => \bytes09[15]_i_2_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \bytes03[13]_i_4_n_0\,
      I4 => \byte_read_done[3]_i_4_n_0\,
      O => \bytes10[13]_i_4_n_0\
    );
\bytes10[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes10[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \bytes10[14]_i_2_n_0\,
      I5 => bytes10(14),
      O => \bytes10[14]_i_1_n_0\
    );
\bytes10[14]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes10[15]_i_4_n_0\,
      O => \bytes10[14]_i_2_n_0\
    );
\bytes10[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDDFDD00000200"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes10[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \bytes10[15]_i_3_n_0\,
      I5 => bytes10(15),
      O => \bytes10[15]_i_1_n_0\
    );
\bytes10[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA2AAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \bytes03[13]_i_4_n_0\,
      I3 => \byte_read_done[3]_i_3_n_0\,
      I4 => \bytes09[15]_i_2_n_0\,
      I5 => \bytes10[15]_i_4_n_0\,
      O => \bytes10[15]_i_2_n_0\
    );
\bytes10[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes10[15]_i_4_n_0\,
      O => \bytes10[15]_i_3_n_0\
    );
\bytes10[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => \byte_read_done[6]_i_2_n_0\,
      I1 => \byte_read_done[12]_i_5_n_0\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \byte_count_reg_n_0_[2]\,
      O => \bytes10[15]_i_4_n_0\
    );
\bytes10[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes10[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes10[1]_i_2_n_0\,
      I5 => bytes10(1),
      O => \bytes10[1]_i_1_n_0\
    );
\bytes10[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555700000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes10[5]_i_3_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \byte_read_done[10]_i_2_n_0\,
      I5 => eth_rstn,
      O => \bytes10[1]_i_2_n_0\
    );
\bytes10[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes10[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes10[3]_i_2_n_0\,
      I5 => bytes10(2),
      O => \bytes10[2]_i_1_n_0\
    );
\bytes10[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes10[11]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes10[3]_i_2_n_0\,
      I5 => bytes10(3),
      O => \bytes10[3]_i_1_n_0\
    );
\bytes10[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555575500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes10[5]_i_3_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => ip_header_options1(1),
      I4 => \byte_read_done[10]_i_2_n_0\,
      I5 => eth_rstn,
      O => \bytes10[3]_i_2_n_0\
    );
\bytes10[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes10[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes10[5]_i_2_n_0\,
      I5 => bytes10(4),
      O => \bytes10[4]_i_1_n_0\
    );
\bytes10[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes10[13]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes10[5]_i_2_n_0\,
      I5 => bytes10(5),
      O => \bytes10[5]_i_1_n_0\
    );
\bytes10[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555575500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes10[5]_i_3_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \byte_read_done[10]_i_2_n_0\,
      I5 => eth_rstn,
      O => \bytes10[5]_i_2_n_0\
    );
\bytes10[5]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFFFFFF"
    )
        port map (
      I0 => \byte_read_done[10]_i_2_n_0\,
      I1 => \bytes09[15]_i_2_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \bytes03[7]_i_3_n_0\,
      I4 => \byte_read_done[3]_i_4_n_0\,
      O => \bytes10[5]_i_3_n_0\
    );
\bytes10[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes10[7]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \bytes10[14]_i_2_n_0\,
      I5 => bytes10(6),
      O => \bytes10[6]_i_1_n_0\
    );
\bytes10[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes10[7]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes10[15]_i_3_n_0\,
      I5 => bytes10(7),
      O => \bytes10[7]_i_1_n_0\
    );
\bytes10[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA2AAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \bytes03[7]_i_3_n_0\,
      I3 => \byte_read_done[3]_i_3_n_0\,
      I4 => \bytes09[15]_i_2_n_0\,
      I5 => \bytes10[15]_i_4_n_0\,
      O => \bytes10[7]_i_2_n_0\
    );
\bytes10[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes10[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes10[9]_i_3_n_0\,
      I5 => bytes10(8),
      O => \bytes10[8]_i_1_n_0\
    );
\bytes10[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes10[9]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \bytes10[9]_i_3_n_0\,
      I5 => bytes10(9),
      O => \bytes10[9]_i_1_n_0\
    );
\bytes10[9]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[10]_i_2_n_0\,
      O => \bytes10[9]_i_2_n_0\
    );
\bytes10[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \byte_read_done[10]_i_2_n_0\,
      I4 => \bytes10[13]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes10[9]_i_3_n_0\
    );
\bytes10_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[0]_i_1_n_0\,
      Q => bytes10(0),
      R => '0'
    );
\bytes10_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[10]_i_1_n_0\,
      Q => bytes10(10),
      R => '0'
    );
\bytes10_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[11]_i_1_n_0\,
      Q => bytes10(11),
      R => '0'
    );
\bytes10_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[12]_i_1_n_0\,
      Q => bytes10(12),
      R => '0'
    );
\bytes10_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[13]_i_1_n_0\,
      Q => bytes10(13),
      R => '0'
    );
\bytes10_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[14]_i_1_n_0\,
      Q => bytes10(14),
      R => '0'
    );
\bytes10_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[15]_i_1_n_0\,
      Q => bytes10(15),
      R => '0'
    );
\bytes10_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[1]_i_1_n_0\,
      Q => bytes10(1),
      R => '0'
    );
\bytes10_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[2]_i_1_n_0\,
      Q => bytes10(2),
      R => '0'
    );
\bytes10_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[3]_i_1_n_0\,
      Q => bytes10(3),
      R => '0'
    );
\bytes10_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[4]_i_1_n_0\,
      Q => bytes10(4),
      R => '0'
    );
\bytes10_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[5]_i_1_n_0\,
      Q => bytes10(5),
      R => '0'
    );
\bytes10_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[6]_i_1_n_0\,
      Q => bytes10(6),
      R => '0'
    );
\bytes10_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[7]_i_1_n_0\,
      Q => bytes10(7),
      R => '0'
    );
\bytes10_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[8]_i_1_n_0\,
      Q => bytes10(8),
      R => '0'
    );
\bytes10_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes10[9]_i_1_n_0\,
      Q => bytes10(9),
      R => '0'
    );
\bytes11[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FFFF00020000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes11[14]_i_2_n_0\,
      I4 => \bytes11[1]_i_2_n_0\,
      I5 => bytes11(0),
      O => \bytes11[0]_i_1_n_0\
    );
\bytes11[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bytes11[14]_i_2_n_0\,
      I4 => \bytes11[11]_i_2_n_0\,
      I5 => bytes11(10),
      O => \bytes11[10]_i_1_n_0\
    );
\bytes11[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bytes11[15]_i_2_n_0\,
      I4 => \bytes11[11]_i_2_n_0\,
      I5 => bytes11(11),
      O => \bytes11[11]_i_1_n_0\
    );
\bytes11[11]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes11[11]_i_3_n_0\,
      O => \bytes11[11]_i_2_n_0\
    );
\bytes11[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAA2AAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \source_mac[35]_i_2_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \dest_mac[39]_i_4_n_0\,
      I4 => \byte_read_done[13]_i_6_n_0\,
      I5 => \bytes03[13]_i_4_n_0\,
      O => \bytes11[11]_i_3_n_0\
    );
\bytes11[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes11[14]_i_2_n_0\,
      I4 => \bytes11[13]_i_2_n_0\,
      I5 => bytes11(12),
      O => \bytes11[12]_i_1_n_0\
    );
\bytes11[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes11[15]_i_2_n_0\,
      I4 => \bytes11[13]_i_2_n_0\,
      I5 => bytes11(13),
      O => \bytes11[13]_i_1_n_0\
    );
\bytes11[13]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes11[13]_i_3_n_0\,
      O => \bytes11[13]_i_2_n_0\
    );
\bytes11[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAA2AAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \source_mac[37]_i_2_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \dest_mac[39]_i_4_n_0\,
      I4 => \byte_read_done[13]_i_6_n_0\,
      I5 => \bytes03[13]_i_4_n_0\,
      O => \bytes11[13]_i_3_n_0\
    );
\bytes11[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes11[14]_i_2_n_0\,
      I4 => \bytes11[15]_i_3_n_0\,
      I5 => bytes11(14),
      O => \bytes11[14]_i_1_n_0\
    );
\bytes11[14]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \byte_read_done[13]_i_6_n_0\,
      O => \bytes11[14]_i_2_n_0\
    );
\bytes11[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes11[15]_i_2_n_0\,
      I4 => \bytes11[15]_i_3_n_0\,
      I5 => bytes11(15),
      O => \bytes11[15]_i_1_n_0\
    );
\bytes11[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \byte_read_done[13]_i_6_n_0\,
      O => \bytes11[15]_i_2_n_0\
    );
\bytes11[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes11[15]_i_4_n_0\,
      O => \bytes11[15]_i_3_n_0\
    );
\bytes11[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8AAAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[13]_i_6_n_0\,
      I2 => \bytes03[13]_i_4_n_0\,
      I3 => \byte_read_done[6]_i_2_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => \dest_mac[39]_i_4_n_0\,
      O => \bytes11[15]_i_4_n_0\
    );
\bytes11[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FFFF00020000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes11[15]_i_2_n_0\,
      I4 => \bytes11[1]_i_2_n_0\,
      I5 => bytes11(1),
      O => \bytes11[1]_i_1_n_0\
    );
\bytes11[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes11[1]_i_3_n_0\,
      O => \bytes11[1]_i_2_n_0\
    );
\bytes11[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[13]_i_6_n_0\,
      I2 => \bytes03[7]_i_3_n_0\,
      I3 => \source_mac[33]_i_2_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => \dest_mac[39]_i_4_n_0\,
      O => \bytes11[1]_i_3_n_0\
    );
\bytes11[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bytes11[14]_i_2_n_0\,
      I4 => \bytes11[3]_i_2_n_0\,
      I5 => bytes11(2),
      O => \bytes11[2]_i_1_n_0\
    );
\bytes11[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => \bytes11[15]_i_2_n_0\,
      I4 => \bytes11[3]_i_2_n_0\,
      I5 => bytes11(3),
      O => \bytes11[3]_i_1_n_0\
    );
\bytes11[3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes11[3]_i_3_n_0\,
      O => \bytes11[3]_i_2_n_0\
    );
\bytes11[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[13]_i_6_n_0\,
      I2 => \bytes03[7]_i_3_n_0\,
      I3 => \source_mac[35]_i_2_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => \dest_mac[39]_i_4_n_0\,
      O => \bytes11[3]_i_3_n_0\
    );
\bytes11[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes11[14]_i_2_n_0\,
      I4 => \bytes11[5]_i_2_n_0\,
      I5 => bytes11(4),
      O => \bytes11[4]_i_1_n_0\
    );
\bytes11[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes11[15]_i_2_n_0\,
      I4 => \bytes11[5]_i_2_n_0\,
      I5 => bytes11(5),
      O => \bytes11[5]_i_1_n_0\
    );
\bytes11[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes11[5]_i_3_n_0\,
      O => \bytes11[5]_i_2_n_0\
    );
\bytes11[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[13]_i_6_n_0\,
      I2 => \bytes03[7]_i_3_n_0\,
      I3 => \source_mac[37]_i_2_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => \dest_mac[39]_i_4_n_0\,
      O => \bytes11[5]_i_3_n_0\
    );
\bytes11[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes11[14]_i_2_n_0\,
      I4 => \bytes11[7]_i_2_n_0\,
      I5 => bytes11(6),
      O => \bytes11[6]_i_1_n_0\
    );
\bytes11[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes11[15]_i_2_n_0\,
      I4 => \bytes11[7]_i_2_n_0\,
      I5 => bytes11(7),
      O => \bytes11[7]_i_1_n_0\
    );
\bytes11[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes11[7]_i_3_n_0\,
      O => \bytes11[7]_i_2_n_0\
    );
\bytes11[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[13]_i_6_n_0\,
      I2 => \bytes03[7]_i_3_n_0\,
      I3 => \byte_read_done[6]_i_2_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => \dest_mac[39]_i_4_n_0\,
      O => \bytes11[7]_i_3_n_0\
    );
\bytes11[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FFFF00020000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes11[14]_i_2_n_0\,
      I4 => \bytes11[9]_i_2_n_0\,
      I5 => bytes11(8),
      O => \bytes11[8]_i_1_n_0\
    );
\bytes11[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FFFF00020000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \bytes11[15]_i_2_n_0\,
      I4 => \bytes11[9]_i_2_n_0\,
      I5 => bytes11(9),
      O => \bytes11[9]_i_1_n_0\
    );
\bytes11[9]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \bytes11[9]_i_3_n_0\,
      O => \bytes11[9]_i_2_n_0\
    );
\bytes11[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAA2AAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \source_mac[33]_i_2_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \dest_mac[39]_i_4_n_0\,
      I4 => \byte_read_done[13]_i_6_n_0\,
      I5 => \bytes03[13]_i_4_n_0\,
      O => \bytes11[9]_i_3_n_0\
    );
\bytes11_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[0]_i_1_n_0\,
      Q => bytes11(0),
      R => '0'
    );
\bytes11_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[10]_i_1_n_0\,
      Q => bytes11(10),
      R => '0'
    );
\bytes11_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[11]_i_1_n_0\,
      Q => bytes11(11),
      R => '0'
    );
\bytes11_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[12]_i_1_n_0\,
      Q => bytes11(12),
      R => '0'
    );
\bytes11_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[13]_i_1_n_0\,
      Q => bytes11(13),
      R => '0'
    );
\bytes11_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[14]_i_1_n_0\,
      Q => bytes11(14),
      R => '0'
    );
\bytes11_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[15]_i_1_n_0\,
      Q => bytes11(15),
      R => '0'
    );
\bytes11_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[1]_i_1_n_0\,
      Q => bytes11(1),
      R => '0'
    );
\bytes11_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[2]_i_1_n_0\,
      Q => bytes11(2),
      R => '0'
    );
\bytes11_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[3]_i_1_n_0\,
      Q => bytes11(3),
      R => '0'
    );
\bytes11_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[4]_i_1_n_0\,
      Q => bytes11(4),
      R => '0'
    );
\bytes11_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[5]_i_1_n_0\,
      Q => bytes11(5),
      R => '0'
    );
\bytes11_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[6]_i_1_n_0\,
      Q => bytes11(6),
      R => '0'
    );
\bytes11_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[7]_i_1_n_0\,
      Q => bytes11(7),
      R => '0'
    );
\bytes11_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[8]_i_1_n_0\,
      Q => bytes11(8),
      R => '0'
    );
\bytes11_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes11[9]_i_1_n_0\,
      Q => bytes11(9),
      R => '0'
    );
\bytes12[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes12[8]_i_2_n_0\,
      I3 => \bytes12[1]_i_2_n_0\,
      I4 => bytes12(0),
      O => \bytes12[0]_i_1_n_0\
    );
\bytes12[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \bytes12[10]_i_2_n_0\,
      I3 => \bytes12[11]_i_3_n_0\,
      I4 => bytes12(10),
      O => \bytes12[10]_i_1_n_0\
    );
\bytes12[10]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \bit_count_reg[1]_rep_n_0\,
      I1 => ip_header_options1(1),
      I2 => \byte_read_done[12]_i_2_n_0\,
      I3 => eth_rxd(0),
      O => \bytes12[10]_i_2_n_0\
    );
\bytes12[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \bytes12[11]_i_2_n_0\,
      I3 => \bytes12[11]_i_3_n_0\,
      I4 => bytes12(11),
      O => \bytes12[11]_i_1_n_0\
    );
\bytes12[11]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => \bit_count_reg[1]_rep_n_0\,
      I1 => ip_header_options1(1),
      I2 => \byte_read_done[12]_i_2_n_0\,
      I3 => eth_rxd(1),
      O => \bytes12[11]_i_2_n_0\
    );
\bytes12[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5575555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \byte_read_done[12]_i_2_n_0\,
      I4 => \bytes12[13]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes12[11]_i_3_n_0\
    );
\bytes12[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \bytes12[12]_i_2_n_0\,
      I3 => \bytes12[13]_i_3_n_0\,
      I4 => bytes12(12),
      O => \bytes12[12]_i_1_n_0\
    );
\bytes12[12]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[12]_i_2_n_0\,
      I3 => eth_rxd(0),
      O => \bytes12[12]_i_2_n_0\
    );
\bytes12[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \bytes12[13]_i_2_n_0\,
      I3 => \bytes12[13]_i_3_n_0\,
      I4 => bytes12(13),
      O => \bytes12[13]_i_1_n_0\
    );
\bytes12[13]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBFF"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[12]_i_2_n_0\,
      I3 => eth_rxd(1),
      O => \bytes12[13]_i_2_n_0\
    );
\bytes12[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555D5500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes12[13]_i_4_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \byte_read_done[12]_i_2_n_0\,
      I5 => eth_rstn,
      O => \bytes12[13]_i_3_n_0\
    );
\bytes12[13]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001000000000"
    )
        port map (
      I0 => \byte_read_done[12]_i_2_n_0\,
      I1 => \state[3]_i_14_n_0\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => \byte_read_done[11]_i_2_n_0\,
      I4 => \bytes03[13]_i_4_n_0\,
      I5 => \byte_read_done[3]_i_4_n_0\,
      O => \bytes12[13]_i_4_n_0\
    );
\bytes12[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes12[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \bytes12[15]_i_3_n_0\,
      I5 => bytes12(14),
      O => \bytes12[14]_i_1_n_0\
    );
\bytes12[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes12[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \bytes12[15]_i_3_n_0\,
      I5 => bytes12(15),
      O => \bytes12[15]_i_1_n_0\
    );
\bytes12[15]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[12]_i_2_n_0\,
      O => \bytes12[15]_i_2_n_0\
    );
\bytes12[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555755500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes12[15]_i_4_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \byte_read_done[12]_i_2_n_0\,
      I5 => eth_rstn,
      O => \bytes12[15]_i_3_n_0\
    );
\bytes12[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFDFFFDFFFDFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \bytes03[13]_i_4_n_0\,
      I2 => \byte_read_done[11]_i_2_n_0\,
      I3 => \byte_read_done[3]_i_3_n_0\,
      I4 => \state[2]_i_7_n_0\,
      I5 => \byte_count_reg_n_0_[2]\,
      O => \bytes12[15]_i_4_n_0\
    );
\bytes12[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \bytes12[9]_i_2_n_0\,
      I3 => \bytes12[1]_i_2_n_0\,
      I4 => bytes12(1),
      O => \bytes12[1]_i_1_n_0\
    );
\bytes12[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555700000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes12[5]_i_3_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \byte_read_done[12]_i_2_n_0\,
      I5 => eth_rstn,
      O => \bytes12[1]_i_2_n_0\
    );
\bytes12[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \bytes12[10]_i_2_n_0\,
      I3 => \bytes12[3]_i_2_n_0\,
      I4 => bytes12(2),
      O => \bytes12[2]_i_1_n_0\
    );
\bytes12[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \bytes12[11]_i_2_n_0\,
      I3 => \bytes12[3]_i_2_n_0\,
      I4 => bytes12(3),
      O => \bytes12[3]_i_1_n_0\
    );
\bytes12[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555575500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes12[5]_i_3_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => ip_header_options1(1),
      I4 => \byte_read_done[12]_i_2_n_0\,
      I5 => eth_rstn,
      O => \bytes12[3]_i_2_n_0\
    );
\bytes12[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \bytes12[12]_i_2_n_0\,
      I3 => \bytes12[5]_i_2_n_0\,
      I4 => bytes12(4),
      O => \bytes12[4]_i_1_n_0\
    );
\bytes12[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \bytes12[13]_i_2_n_0\,
      I3 => \bytes12[5]_i_2_n_0\,
      I4 => bytes12(5),
      O => \bytes12[5]_i_1_n_0\
    );
\bytes12[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555575500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes12[5]_i_3_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \byte_read_done[12]_i_2_n_0\,
      I5 => eth_rstn,
      O => \bytes12[5]_i_2_n_0\
    );
\bytes12[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFBFFFFF"
    )
        port map (
      I0 => \byte_read_done[12]_i_2_n_0\,
      I1 => \bytes03[7]_i_3_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => \state[3]_i_14_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => \byte_read_done[11]_i_2_n_0\,
      O => \bytes12[5]_i_3_n_0\
    );
\bytes12[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \bytes12[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \bytes12[7]_i_2_n_0\,
      I5 => bytes12(6),
      O => \bytes12[6]_i_1_n_0\
    );
\bytes12[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \bytes12[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \bytes12[7]_i_2_n_0\,
      I5 => bytes12(7),
      O => \bytes12[7]_i_1_n_0\
    );
\bytes12[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555755500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes12[7]_i_3_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \byte_read_done[12]_i_2_n_0\,
      I5 => eth_rstn,
      O => \bytes12[7]_i_2_n_0\
    );
\bytes12[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBBBFFFFFFFFFFFF"
    )
        port map (
      I0 => \byte_read_done[11]_i_2_n_0\,
      I1 => \byte_read_done[3]_i_3_n_0\,
      I2 => \state[2]_i_7_n_0\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_read_done[3]_i_4_n_0\,
      I5 => \bytes03[7]_i_3_n_0\,
      O => \bytes12[7]_i_3_n_0\
    );
\bytes12[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \bytes12[8]_i_2_n_0\,
      I3 => \bytes12[9]_i_3_n_0\,
      I4 => bytes12(8),
      O => \bytes12[8]_i_1_n_0\
    );
\bytes12[8]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[12]_i_2_n_0\,
      I3 => eth_rxd(0),
      O => \bytes12[8]_i_2_n_0\
    );
\bytes12[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \bytes12[9]_i_2_n_0\,
      I3 => \bytes12[9]_i_3_n_0\,
      I4 => bytes12(9),
      O => \bytes12[9]_i_1_n_0\
    );
\bytes12[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEFF"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[12]_i_2_n_0\,
      I3 => eth_rxd(1),
      O => \bytes12[9]_i_2_n_0\
    );
\bytes12[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \byte_read_done[12]_i_2_n_0\,
      I4 => \bytes12[13]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes12[9]_i_3_n_0\
    );
\bytes12_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[0]_i_1_n_0\,
      Q => bytes12(0),
      R => '0'
    );
\bytes12_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[10]_i_1_n_0\,
      Q => bytes12(10),
      R => '0'
    );
\bytes12_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[11]_i_1_n_0\,
      Q => bytes12(11),
      R => '0'
    );
\bytes12_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[12]_i_1_n_0\,
      Q => bytes12(12),
      R => '0'
    );
\bytes12_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[13]_i_1_n_0\,
      Q => bytes12(13),
      R => '0'
    );
\bytes12_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[14]_i_1_n_0\,
      Q => bytes12(14),
      R => '0'
    );
\bytes12_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[15]_i_1_n_0\,
      Q => bytes12(15),
      R => '0'
    );
\bytes12_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[1]_i_1_n_0\,
      Q => bytes12(1),
      R => '0'
    );
\bytes12_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[2]_i_1_n_0\,
      Q => bytes12(2),
      R => '0'
    );
\bytes12_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[3]_i_1_n_0\,
      Q => bytes12(3),
      R => '0'
    );
\bytes12_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[4]_i_1_n_0\,
      Q => bytes12(4),
      R => '0'
    );
\bytes12_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[5]_i_1_n_0\,
      Q => bytes12(5),
      R => '0'
    );
\bytes12_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[6]_i_1_n_0\,
      Q => bytes12(6),
      R => '0'
    );
\bytes12_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[7]_i_1_n_0\,
      Q => bytes12(7),
      R => '0'
    );
\bytes12_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[8]_i_1_n_0\,
      Q => bytes12(8),
      R => '0'
    );
\bytes12_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes12[9]_i_1_n_0\,
      Q => bytes12(9),
      R => '0'
    );
\bytes13[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FFFF00020000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bytes13[14]_i_2_n_0\,
      I4 => \bytes13[1]_i_2_n_0\,
      I5 => bytes13(0),
      O => \bytes13[0]_i_1_n_0\
    );
\bytes13[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \bytes13[14]_i_2_n_0\,
      I4 => \bytes13[11]_i_2_n_0\,
      I5 => bytes13(10),
      O => \bytes13[10]_i_1_n_0\
    );
\bytes13[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \bytes13[15]_i_2_n_0\,
      I4 => \bytes13[11]_i_2_n_0\,
      I5 => bytes13(11),
      O => \bytes13[11]_i_1_n_0\
    );
\bytes13[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5575555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bytes13[15]_i_4_n_0\,
      I4 => \bytes13[15]_i_5_n_0\,
      I5 => eth_rstn,
      O => \bytes13[11]_i_2_n_0\
    );
\bytes13[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bytes13[14]_i_2_n_0\,
      I4 => \bytes13[13]_i_2_n_0\,
      I5 => bytes13(12),
      O => \bytes13[12]_i_1_n_0\
    );
\bytes13[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bytes13[15]_i_2_n_0\,
      I4 => \bytes13[13]_i_2_n_0\,
      I5 => bytes13(13),
      O => \bytes13[13]_i_1_n_0\
    );
\bytes13[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5575555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \bytes13[15]_i_4_n_0\,
      I4 => \bytes13[15]_i_5_n_0\,
      I5 => eth_rstn,
      O => \bytes13[13]_i_2_n_0\
    );
\bytes13[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bytes13[14]_i_2_n_0\,
      I4 => \bytes13[15]_i_3_n_0\,
      I5 => bytes13(14),
      O => \bytes13[14]_i_1_n_0\
    );
\bytes13[14]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \byte_count[1]_i_7_n_0\,
      O => \bytes13[14]_i_2_n_0\
    );
\bytes13[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bytes13[15]_i_2_n_0\,
      I4 => \bytes13[15]_i_3_n_0\,
      I5 => bytes13(15),
      O => \bytes13[15]_i_1_n_0\
    );
\bytes13[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \byte_count[1]_i_7_n_0\,
      O => \bytes13[15]_i_2_n_0\
    );
\bytes13[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55D5555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \bytes13[15]_i_4_n_0\,
      I4 => \bytes13[15]_i_5_n_0\,
      I5 => eth_rstn,
      O => \bytes13[15]_i_3_n_0\
    );
\bytes13[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFF7FFFFFF"
    )
        port map (
      I0 => \byte_read_done[3]_i_3_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[4]\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => \byte_read_done[12]_i_5_n_0\,
      O => \bytes13[15]_i_4_n_0\
    );
\bytes13[15]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000400"
    )
        port map (
      I0 => \bit_count[1]_i_15_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \state_reg_n_0_[0]\,
      I4 => \byte_count_reg[0]_rep_n_0\,
      O => \bytes13[15]_i_5_n_0\
    );
\bytes13[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FFFF00020000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bytes13[15]_i_2_n_0\,
      I4 => \bytes13[1]_i_2_n_0\,
      I5 => bytes13(1),
      O => \bytes13[1]_i_1_n_0\
    );
\bytes13[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555700000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes13[7]_i_3_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \bytes13[15]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes13[1]_i_2_n_0\
    );
\bytes13[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \bytes13[14]_i_2_n_0\,
      I4 => \bytes13[3]_i_2_n_0\,
      I5 => bytes13(2),
      O => \bytes13[2]_i_1_n_0\
    );
\bytes13[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \bytes13[15]_i_2_n_0\,
      I4 => \bytes13[3]_i_2_n_0\,
      I5 => bytes13(3),
      O => \bytes13[3]_i_1_n_0\
    );
\bytes13[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555575500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes13[7]_i_3_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bytes13[15]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes13[3]_i_2_n_0\
    );
\bytes13[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bytes13[14]_i_2_n_0\,
      I4 => \bytes13[5]_i_2_n_0\,
      I5 => bytes13(4),
      O => \bytes13[4]_i_1_n_0\
    );
\bytes13[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bytes13[15]_i_2_n_0\,
      I4 => \bytes13[5]_i_2_n_0\,
      I5 => bytes13(5),
      O => \bytes13[5]_i_1_n_0\
    );
\bytes13[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555575500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes13[7]_i_3_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \bytes13[15]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes13[5]_i_2_n_0\
    );
\bytes13[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bytes13[14]_i_2_n_0\,
      I4 => \bytes13[7]_i_2_n_0\,
      I5 => bytes13(6),
      O => \bytes13[6]_i_1_n_0\
    );
\bytes13[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \dest_mac[23]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bytes13[15]_i_2_n_0\,
      I4 => \bytes13[7]_i_2_n_0\,
      I5 => bytes13(7),
      O => \bytes13[7]_i_1_n_0\
    );
\bytes13[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555755500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \bytes13[7]_i_3_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \bytes13[15]_i_4_n_0\,
      I5 => eth_rstn,
      O => \bytes13[7]_i_2_n_0\
    );
\bytes13[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFBFFF"
    )
        port map (
      I0 => \bit_count[1]_i_15_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \state_reg_n_0_[2]\,
      O => \bytes13[7]_i_3_n_0\
    );
\bytes13[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FFFF00020000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bytes13[14]_i_2_n_0\,
      I4 => \bytes13[9]_i_2_n_0\,
      I5 => bytes13(8),
      O => \bytes13[8]_i_1_n_0\
    );
\bytes13[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0002FFFF00020000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \bytes13[15]_i_2_n_0\,
      I4 => \bytes13[9]_i_2_n_0\,
      I5 => bytes13(9),
      O => \bytes13[9]_i_1_n_0\
    );
\bytes13[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5557555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => ip_header_options1(1),
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \bytes13[15]_i_4_n_0\,
      I4 => \bytes13[15]_i_5_n_0\,
      I5 => eth_rstn,
      O => \bytes13[9]_i_2_n_0\
    );
\bytes13_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[0]_i_1_n_0\,
      Q => bytes13(0),
      R => '0'
    );
\bytes13_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[10]_i_1_n_0\,
      Q => bytes13(10),
      R => '0'
    );
\bytes13_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[11]_i_1_n_0\,
      Q => bytes13(11),
      R => '0'
    );
\bytes13_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[12]_i_1_n_0\,
      Q => bytes13(12),
      R => '0'
    );
\bytes13_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[13]_i_1_n_0\,
      Q => bytes13(13),
      R => '0'
    );
\bytes13_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[14]_i_1_n_0\,
      Q => bytes13(14),
      R => '0'
    );
\bytes13_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[15]_i_1_n_0\,
      Q => bytes13(15),
      R => '0'
    );
\bytes13_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[1]_i_1_n_0\,
      Q => bytes13(1),
      R => '0'
    );
\bytes13_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[2]_i_1_n_0\,
      Q => bytes13(2),
      R => '0'
    );
\bytes13_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[3]_i_1_n_0\,
      Q => bytes13(3),
      R => '0'
    );
\bytes13_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[4]_i_1_n_0\,
      Q => bytes13(4),
      R => '0'
    );
\bytes13_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[5]_i_1_n_0\,
      Q => bytes13(5),
      R => '0'
    );
\bytes13_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[6]_i_1_n_0\,
      Q => bytes13(6),
      R => '0'
    );
\bytes13_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[7]_i_1_n_0\,
      Q => bytes13(7),
      R => '0'
    );
\bytes13_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[8]_i_1_n_0\,
      Q => bytes13(8),
      R => '0'
    );
\bytes13_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \bytes13[9]_i_1_n_0\,
      Q => bytes13(9),
      R => '0'
    );
crc_checker: entity work.design_1_ethernet_transceiver2_0_0_crc32_parallel_0
     port map (
      CO(0) => crc_pass0,
      Q(0) => \state_reg_n_0_[3]\,
      b_clk100mhz => b_clk100mhz,
      crc_rx(31 downto 0) => crc_rx(31 downto 0),
      eth_rxd(1 downto 0) => eth_rxd(1 downto 0),
      rst_ram_reg => rst_ram_i_2_n_0,
      rst_ram_reg_0 => \state[2]_i_5__0_n_0\,
      rst_ram_reg_1 => rst_ram_i_4_n_0,
      rst_ram_reg_2 => rst_ram_reg_n_0,
      \state_reg[3]\ => crc_checker_n_1,
      state_reg_0 => start_crc_reg_n_0,
      udp_datasum_done14_out => udp_datasum_done14_out
    );
crc_pass_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFF80008"
    )
        port map (
      I0 => crc_pass0,
      I1 => \state_reg_n_0_[3]\,
      I2 => \state_reg[1]_rep_n_0\,
      I3 => crc_pass_i_2_n_0,
      I4 => crc_pass_reg_n_0,
      O => crc_pass_i_1_n_0
    );
crc_pass_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \state_reg_n_0_[0]\,
      I2 => eth_rstn,
      O => crc_pass_i_2_n_0
    );
crc_pass_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => crc_pass_i_1_n_0,
      Q => crc_pass_reg_n_0,
      R => '0'
    );
\crc_rx[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02A2FFFF02A20000"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \crc_rx_reg[30]_0\,
      I2 => \crc_rx[0]_i_2_n_0\,
      I3 => \crc_rx_reg[30]_1\,
      I4 => \crc_rx[1]_i_2_n_0\,
      I5 => crc_rx(0),
      O => \crc_rx[0]_i_1_n_0\
    );
\crc_rx[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00800000"
    )
        port map (
      I0 => \bit_count_reg[0]_rep_n_0\,
      I1 => ip_header_options1(2),
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \byte_read_done[3]_i_4_n_0\,
      I4 => \byte_count_reg[1]_rep_n_0\,
      O => \crc_rx[0]_i_2_n_0\
    );
\crc_rx[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \crc_rx[11]_i_2_n_0\,
      I2 => \crc_rx[10]_i_2_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \crc_rx[10]_i_3_n_0\,
      I5 => crc_rx(10),
      O => \crc_rx[10]_i_1_n_0\
    );
\crc_rx[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00040000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rxd(0),
      O => \crc_rx[10]_i_2_n_0\
    );
\crc_rx[10]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000040000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rxd(1),
      O => \crc_rx[10]_i_3_n_0\
    );
\crc_rx[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF8F0080"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => eth_rstn,
      I3 => \crc_rx[11]_i_2_n_0\,
      I4 => crc_rx(11),
      O => \crc_rx[11]_i_1_n_0\
    );
\crc_rx[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_count_reg[0]_rep__1_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \byte_read_done[3]_i_4_n_0\,
      I4 => \source_mac[37]_i_2_n_0\,
      I5 => \crc_rx[23]_i_3_n_0\,
      O => \crc_rx[11]_i_2_n_0\
    );
\crc_rx[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \crc_rx[13]_i_2_n_0\,
      I2 => \crc_rx[12]_i_2_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \crc_rx[12]_i_3_n_0\,
      I5 => crc_rx(12),
      O => \crc_rx[12]_i_1_n_0\
    );
\crc_rx[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00040000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => ip_header_options1(1),
      I5 => eth_rxd(0),
      O => \crc_rx[12]_i_2_n_0\
    );
\crc_rx[12]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000040000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => ip_header_options1(1),
      I5 => eth_rxd(1),
      O => \crc_rx[12]_i_3_n_0\
    );
\crc_rx[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF8F0080"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => eth_rstn,
      I3 => \crc_rx[13]_i_2_n_0\,
      I4 => crc_rx(13),
      O => \crc_rx[13]_i_1_n_0\
    );
\crc_rx[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_count_reg[0]_rep__0_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \byte_read_done[3]_i_4_n_0\,
      I4 => \source_mac[35]_i_2_n_0\,
      I5 => \crc_rx[23]_i_3_n_0\,
      O => \crc_rx[13]_i_2_n_0\
    );
\crc_rx[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \crc_rx[15]_i_2_n_0\,
      I2 => \crc_rx[14]_i_2_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \crc_rx[14]_i_3_n_0\,
      I5 => crc_rx(14),
      O => \crc_rx[14]_i_1_n_0\
    );
\crc_rx[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000004"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rxd(0),
      O => \crc_rx[14]_i_2_n_0\
    );
\crc_rx[14]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rxd(1),
      O => \crc_rx[14]_i_3_n_0\
    );
\crc_rx[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF8F0080"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => eth_rstn,
      I3 => \crc_rx[15]_i_2_n_0\,
      I4 => crc_rx(15),
      O => \crc_rx[15]_i_1_n_0\
    );
\crc_rx[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_count_reg[0]_rep__0_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \byte_read_done[3]_i_4_n_0\,
      I4 => \source_mac[33]_i_2_n_0\,
      I5 => \crc_rx[23]_i_3_n_0\,
      O => \crc_rx[15]_i_2_n_0\
    );
\crc_rx[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02A2FFFF02A20000"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \crc_rx_reg[30]_0\,
      I2 => \crc_rx[16]_i_2_n_0\,
      I3 => \crc_rx_reg[30]_1\,
      I4 => \crc_rx[17]_i_2_n_0\,
      I5 => crc_rx(16),
      O => \crc_rx[16]_i_1_n_0\
    );
\crc_rx[16]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080000"
    )
        port map (
      I0 => \bit_count_reg[0]_rep_n_0\,
      I1 => ip_header_options1(2),
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \byte_read_done[3]_i_4_n_0\,
      I4 => \byte_count_reg[0]_rep__0_n_0\,
      O => \crc_rx[16]_i_2_n_0\
    );
\crc_rx[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => \crc_rx[17]_i_2_n_0\,
      I3 => crc_rx(17),
      O => \crc_rx[17]_i_1_n_0\
    );
\crc_rx[17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"555D555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_count_reg[0]_rep__0_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \byte_read_done[3]_i_4_n_0\,
      I4 => \crc_rx[17]_i_3_n_0\,
      I5 => eth_rstn,
      O => \crc_rx[17]_i_2_n_0\
    );
\crc_rx[17]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4000000000000000"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \state_reg_n_0_[0]\,
      I5 => \state_reg_n_0_[2]\,
      O => \crc_rx[17]_i_3_n_0\
    );
\crc_rx[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \crc_rx[19]_i_2_n_0\,
      I2 => \crc_rx[18]_i_2_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \crc_rx[18]_i_3_n_0\,
      I5 => crc_rx(18),
      O => \crc_rx[18]_i_1_n_0\
    );
\crc_rx[18]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00100000"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rxd(0),
      O => \crc_rx[18]_i_2_n_0\
    );
\crc_rx[18]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000100000"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rxd(1),
      O => \crc_rx[18]_i_3_n_0\
    );
\crc_rx[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF8F0080"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => eth_rstn,
      I3 => \crc_rx[19]_i_2_n_0\,
      I4 => crc_rx(19),
      O => \crc_rx[19]_i_1_n_0\
    );
\crc_rx[19]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8AAAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \byte_count_reg[0]_rep__0_n_0\,
      I4 => \source_mac[37]_i_2_n_0\,
      I5 => \crc_rx[23]_i_3_n_0\,
      O => \crc_rx[19]_i_2_n_0\
    );
\crc_rx[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => \crc_rx[1]_i_2_n_0\,
      I3 => crc_rx(1),
      O => \crc_rx[1]_i_1_n_0\
    );
\crc_rx[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \crc_rx[1]_i_3_n_0\,
      O => \crc_rx[1]_i_2_n_0\
    );
\crc_rx[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \state[3]_i_6_n_0\,
      I3 => \byte_read_done[6]_i_2_n_0\,
      I4 => \bit_count[1]_i_3_n_0\,
      I5 => \state_reg_n_0_[2]\,
      O => \crc_rx[1]_i_3_n_0\
    );
\crc_rx[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \crc_rx[21]_i_2_n_0\,
      I2 => \crc_rx[20]_i_2_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \crc_rx[20]_i_3_n_0\,
      I5 => crc_rx(20),
      O => \crc_rx[20]_i_1_n_0\
    );
\crc_rx[20]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00100000"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => ip_header_options1(1),
      I5 => eth_rxd(0),
      O => \crc_rx[20]_i_2_n_0\
    );
\crc_rx[20]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000100000"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => ip_header_options1(1),
      I5 => eth_rxd(1),
      O => \crc_rx[20]_i_3_n_0\
    );
\crc_rx[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF8F0080"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => eth_rstn,
      I3 => \crc_rx[21]_i_2_n_0\,
      I4 => crc_rx(21),
      O => \crc_rx[21]_i_1_n_0\
    );
\crc_rx[21]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8AAAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \byte_count_reg[0]_rep__0_n_0\,
      I4 => \source_mac[35]_i_2_n_0\,
      I5 => \crc_rx[23]_i_3_n_0\,
      O => \crc_rx[21]_i_2_n_0\
    );
\crc_rx[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \crc_rx[23]_i_2_n_0\,
      I2 => \crc_rx[22]_i_2_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \crc_rx[22]_i_3_n_0\,
      I5 => crc_rx(22),
      O => \crc_rx[22]_i_1_n_0\
    );
\crc_rx[22]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000010"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rxd(0),
      O => \crc_rx[22]_i_2_n_0\
    );
\crc_rx[22]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rxd(1),
      O => \crc_rx[22]_i_3_n_0\
    );
\crc_rx[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF8F0080"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => eth_rstn,
      I3 => \crc_rx[23]_i_2_n_0\,
      I4 => crc_rx(23),
      O => \crc_rx[23]_i_1_n_0\
    );
\crc_rx[23]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8AAAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \byte_count_reg[0]_rep__0_n_0\,
      I4 => \source_mac[33]_i_2_n_0\,
      I5 => \crc_rx[23]_i_3_n_0\,
      O => \crc_rx[23]_i_2_n_0\
    );
\crc_rx[23]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1500000000000000"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => ip_header_options1(1),
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \state_reg_n_0_[0]\,
      I5 => \state_reg_n_0_[2]\,
      O => \crc_rx[23]_i_3_n_0\
    );
\crc_rx[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02A2FFFF02A20000"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \crc_rx_reg[30]_0\,
      I2 => \crc_rx[24]_i_2_n_0\,
      I3 => \crc_rx_reg[30]_1\,
      I4 => \crc_rx[25]_i_2_n_0\,
      I5 => crc_rx(24),
      O => \crc_rx[24]_i_1_n_0\
    );
\crc_rx[24]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01000000"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[0]_rep__0_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => ip_header_options1(2),
      O => \crc_rx[24]_i_2_n_0\
    );
\crc_rx[25]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => \crc_rx[25]_i_2_n_0\,
      I3 => crc_rx(25),
      O => \crc_rx[25]_i_1_n_0\
    );
\crc_rx[25]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \crc_rx[25]_i_3_n_0\,
      O => \crc_rx[25]_i_2_n_0\
    );
\crc_rx[25]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \byte_read_done[6]_i_2_n_0\,
      I3 => \bit_count[1]_i_3_n_0\,
      I4 => \state_reg_n_0_[2]\,
      I5 => \eth_prot_type[15]_i_5_n_0\,
      O => \crc_rx[25]_i_3_n_0\
    );
\crc_rx[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02A2FFFF02A20000"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \crc_rx_reg[30]_0\,
      I2 => \crc_rx[26]_i_2_n_0\,
      I3 => \crc_rx_reg[30]_1\,
      I4 => \crc_rx[27]_i_2_n_0\,
      I5 => crc_rx(26),
      O => \crc_rx[26]_i_1_n_0\
    );
\crc_rx[26]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[0]_rep__0_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => ip_header_options1(2),
      O => \crc_rx[26]_i_2_n_0\
    );
\crc_rx[27]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => \crc_rx[27]_i_2_n_0\,
      I3 => crc_rx(27),
      O => \crc_rx[27]_i_1_n_0\
    );
\crc_rx[27]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \crc_rx[27]_i_3_n_0\,
      O => \crc_rx[27]_i_2_n_0\
    );
\crc_rx[27]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \byte_count_reg[1]_rep_n_0\,
      I4 => \source_mac[37]_i_2_n_0\,
      I5 => \crc_rx[23]_i_3_n_0\,
      O => \crc_rx[27]_i_3_n_0\
    );
\crc_rx[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02A2FFFF02A20000"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \crc_rx_reg[30]_0\,
      I2 => \crc_rx[28]_i_2_n_0\,
      I3 => \crc_rx_reg[30]_1\,
      I4 => \crc_rx[29]_i_2_n_0\,
      I5 => crc_rx(28),
      O => \crc_rx[28]_i_1_n_0\
    );
\crc_rx[28]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[0]_rep__0_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bit_count_reg[0]_rep_n_0\,
      O => \crc_rx[28]_i_2_n_0\
    );
\crc_rx[29]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => \crc_rx[29]_i_2_n_0\,
      I3 => crc_rx(29),
      O => \crc_rx[29]_i_1_n_0\
    );
\crc_rx[29]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \crc_rx[29]_i_3_n_0\,
      O => \crc_rx[29]_i_2_n_0\
    );
\crc_rx[29]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \byte_count_reg[1]_rep_n_0\,
      I4 => \source_mac[35]_i_2_n_0\,
      I5 => \crc_rx[23]_i_3_n_0\,
      O => \crc_rx[29]_i_3_n_0\
    );
\crc_rx[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \crc_rx[3]_i_2_n_0\,
      I2 => \crc_rx[2]_i_2_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \crc_rx[2]_i_3_n_0\,
      I5 => crc_rx(2),
      O => \crc_rx[2]_i_1_n_0\
    );
\crc_rx[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00080000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rxd(0),
      O => \crc_rx[2]_i_2_n_0\
    );
\crc_rx[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000080000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rxd(1),
      O => \crc_rx[2]_i_3_n_0\
    );
\crc_rx[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02A2FFFF02A20000"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \crc_rx_reg[30]_0\,
      I2 => \crc_rx[30]_i_3_n_0\,
      I3 => \crc_rx_reg[30]_1\,
      I4 => \crc_rx[31]_i_2_n_0\,
      I5 => crc_rx(30),
      O => \crc_rx[30]_i_1_n_0\
    );
\crc_rx[30]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg[0]_rep__0_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => ip_header_options1(2),
      O => \crc_rx[30]_i_3_n_0\
    );
\crc_rx[31]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => \crc_rx[31]_i_2_n_0\,
      I3 => crc_rx(31),
      O => \crc_rx[31]_i_1_n_0\
    );
\crc_rx[31]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => \crc_rx[31]_i_3_n_0\,
      O => \crc_rx[31]_i_2_n_0\
    );
\crc_rx[31]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA2AAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \crc_rx[23]_i_3_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => \byte_count_reg[0]_rep__0_n_0\,
      I4 => \byte_count_reg[1]_rep_n_0\,
      I5 => \source_mac[33]_i_2_n_0\,
      O => \crc_rx[31]_i_3_n_0\
    );
\crc_rx[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF8F0080"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => eth_rstn,
      I3 => \crc_rx[3]_i_2_n_0\,
      I4 => crc_rx(3),
      O => \crc_rx[3]_i_1_n_0\
    );
\crc_rx[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA2AAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_count_reg[0]_rep__0_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \byte_read_done[3]_i_4_n_0\,
      I4 => \source_mac[37]_i_2_n_0\,
      I5 => \crc_rx[23]_i_3_n_0\,
      O => \crc_rx[3]_i_2_n_0\
    );
\crc_rx[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \crc_rx[5]_i_2_n_0\,
      I2 => \crc_rx[4]_i_2_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \crc_rx[4]_i_3_n_0\,
      I5 => crc_rx(4),
      O => \crc_rx[4]_i_1_n_0\
    );
\crc_rx[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00080000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => ip_header_options1(1),
      I5 => eth_rxd(0),
      O => \crc_rx[4]_i_2_n_0\
    );
\crc_rx[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000080000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__0_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => ip_header_options1(1),
      I5 => eth_rxd(1),
      O => \crc_rx[4]_i_3_n_0\
    );
\crc_rx[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF8F0080"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => eth_rstn,
      I3 => \crc_rx[5]_i_2_n_0\,
      I4 => crc_rx(5),
      O => \crc_rx[5]_i_1_n_0\
    );
\crc_rx[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA2AAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_count_reg[0]_rep__0_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \byte_read_done[3]_i_4_n_0\,
      I4 => \source_mac[35]_i_2_n_0\,
      I5 => \crc_rx[23]_i_3_n_0\,
      O => \crc_rx[5]_i_2_n_0\
    );
\crc_rx[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \crc_rx[7]_i_2_n_0\,
      I2 => \crc_rx[6]_i_2_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \crc_rx[6]_i_3_n_0\,
      I5 => crc_rx(6),
      O => \crc_rx[6]_i_1_n_0\
    );
\crc_rx[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000008"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rxd(0),
      O => \crc_rx[6]_i_2_n_0\
    );
\crc_rx[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => eth_rxd(1),
      O => \crc_rx[6]_i_3_n_0\
    );
\crc_rx[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF8F0080"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => eth_rstn,
      I3 => \crc_rx[7]_i_2_n_0\,
      I4 => crc_rx(7),
      O => \crc_rx[7]_i_1_n_0\
    );
\crc_rx[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA2AAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_count_reg[0]_rep__1_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \byte_read_done[3]_i_4_n_0\,
      I4 => \source_mac[33]_i_2_n_0\,
      I5 => \crc_rx[23]_i_3_n_0\,
      O => \crc_rx[7]_i_2_n_0\
    );
\crc_rx[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"02A2FFFF02A20000"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \crc_rx_reg[30]_0\,
      I2 => \crc_rx[8]_i_2_n_0\,
      I3 => \crc_rx_reg[30]_1\,
      I4 => \crc_rx[9]_i_2_n_0\,
      I5 => crc_rx(8),
      O => \crc_rx[8]_i_1_n_0\
    );
\crc_rx[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000800"
    )
        port map (
      I0 => \bit_count_reg[0]_rep_n_0\,
      I1 => ip_header_options1(2),
      I2 => \byte_read_done[3]_i_4_n_0\,
      I3 => \byte_count_reg[1]_rep_n_0\,
      I4 => \byte_count_reg[0]_rep__1_n_0\,
      O => \crc_rx[8]_i_2_n_0\
    );
\crc_rx[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F80"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rxd(0),
      I2 => \crc_rx[9]_i_2_n_0\,
      I3 => crc_rx(9),
      O => \crc_rx[9]_i_1_n_0\
    );
\crc_rx[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5575555500000000"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_read_done[3]_i_4_n_0\,
      I2 => \byte_count_reg[1]_rep_n_0\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      I4 => \crc_rx[17]_i_3_n_0\,
      I5 => eth_rstn,
      O => \crc_rx[9]_i_2_n_0\
    );
\crc_rx_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[0]_i_1_n_0\,
      Q => crc_rx(0),
      R => '0'
    );
\crc_rx_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[10]_i_1_n_0\,
      Q => crc_rx(10),
      R => '0'
    );
\crc_rx_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[11]_i_1_n_0\,
      Q => crc_rx(11),
      R => '0'
    );
\crc_rx_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[12]_i_1_n_0\,
      Q => crc_rx(12),
      R => '0'
    );
\crc_rx_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[13]_i_1_n_0\,
      Q => crc_rx(13),
      R => '0'
    );
\crc_rx_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[14]_i_1_n_0\,
      Q => crc_rx(14),
      R => '0'
    );
\crc_rx_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[15]_i_1_n_0\,
      Q => crc_rx(15),
      R => '0'
    );
\crc_rx_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[16]_i_1_n_0\,
      Q => crc_rx(16),
      R => '0'
    );
\crc_rx_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[17]_i_1_n_0\,
      Q => crc_rx(17),
      R => '0'
    );
\crc_rx_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[18]_i_1_n_0\,
      Q => crc_rx(18),
      R => '0'
    );
\crc_rx_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[19]_i_1_n_0\,
      Q => crc_rx(19),
      R => '0'
    );
\crc_rx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[1]_i_1_n_0\,
      Q => crc_rx(1),
      R => '0'
    );
\crc_rx_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[20]_i_1_n_0\,
      Q => crc_rx(20),
      R => '0'
    );
\crc_rx_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[21]_i_1_n_0\,
      Q => crc_rx(21),
      R => '0'
    );
\crc_rx_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[22]_i_1_n_0\,
      Q => crc_rx(22),
      R => '0'
    );
\crc_rx_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[23]_i_1_n_0\,
      Q => crc_rx(23),
      R => '0'
    );
\crc_rx_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[24]_i_1_n_0\,
      Q => crc_rx(24),
      R => '0'
    );
\crc_rx_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[25]_i_1_n_0\,
      Q => crc_rx(25),
      R => '0'
    );
\crc_rx_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[26]_i_1_n_0\,
      Q => crc_rx(26),
      R => '0'
    );
\crc_rx_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[27]_i_1_n_0\,
      Q => crc_rx(27),
      R => '0'
    );
\crc_rx_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[28]_i_1_n_0\,
      Q => crc_rx(28),
      R => '0'
    );
\crc_rx_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[29]_i_1_n_0\,
      Q => crc_rx(29),
      R => '0'
    );
\crc_rx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[2]_i_1_n_0\,
      Q => crc_rx(2),
      R => '0'
    );
\crc_rx_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[30]_i_1_n_0\,
      Q => crc_rx(30),
      R => '0'
    );
\crc_rx_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[31]_i_1_n_0\,
      Q => crc_rx(31),
      R => '0'
    );
\crc_rx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[3]_i_1_n_0\,
      Q => crc_rx(3),
      R => '0'
    );
\crc_rx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[4]_i_1_n_0\,
      Q => crc_rx(4),
      R => '0'
    );
\crc_rx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[5]_i_1_n_0\,
      Q => crc_rx(5),
      R => '0'
    );
\crc_rx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[6]_i_1_n_0\,
      Q => crc_rx(6),
      R => '0'
    );
\crc_rx_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[7]_i_1_n_0\,
      Q => crc_rx(7),
      R => '0'
    );
\crc_rx_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[8]_i_1_n_0\,
      Q => crc_rx(8),
      R => '0'
    );
\crc_rx_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \crc_rx[9]_i_1_n_0\,
      Q => crc_rx(9),
      R => '0'
    );
\data_counter_max[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \byte_read_done_reg_n_0_[1]\,
      I1 => arp_request_expected,
      I2 => eth_protocol_expected,
      O => data_counter_max
    );
\data_counter_max[10]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => bytes01(10),
      O => \data_counter_max[10]_i_3_n_0\
    );
\data_counter_max[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => bytes01(4),
      I1 => data_counter_max2(2),
      O => \data_counter_max[5]_i_2_n_0\
    );
\data_counter_max[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => bytes01(3),
      I1 => data_counter_max2(1),
      O => \data_counter_max[5]_i_3_n_0\
    );
\data_counter_max[5]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => bytes01(2),
      I1 => data_counter_max2(0),
      O => \data_counter_max[5]_i_4_n_0\
    );
\data_counter_max[5]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D22D"
    )
        port map (
      I0 => data_counter_max2(2),
      I1 => bytes01(4),
      I2 => data_counter_max2(3),
      I3 => bytes01(5),
      O => \data_counter_max[5]_i_5_n_0\
    );
\data_counter_max[5]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D22D"
    )
        port map (
      I0 => data_counter_max2(1),
      I1 => bytes01(3),
      I2 => data_counter_max2(2),
      I3 => bytes01(4),
      O => \data_counter_max[5]_i_6_n_0\
    );
\data_counter_max[5]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D22D"
    )
        port map (
      I0 => data_counter_max2(0),
      I1 => bytes01(2),
      I2 => data_counter_max2(1),
      I3 => bytes01(3),
      O => \data_counter_max[5]_i_7_n_0\
    );
\data_counter_max[5]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => bytes01(2),
      I1 => data_counter_max2(0),
      O => \data_counter_max[5]_i_8_n_0\
    );
\data_counter_max[9]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => bytes01(9),
      O => \data_counter_max[9]_i_2_n_0\
    );
\data_counter_max[9]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => bytes01(8),
      O => \data_counter_max[9]_i_3_n_0\
    );
\data_counter_max[9]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => bytes01(7),
      O => \data_counter_max[9]_i_4_n_0\
    );
\data_counter_max[9]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2D"
    )
        port map (
      I0 => data_counter_max2(3),
      I1 => bytes01(5),
      I2 => bytes01(6),
      O => \data_counter_max[9]_i_5_n_0\
    );
\data_counter_max_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(0),
      Q => \data_counter_max_reg_n_0_[0]\,
      R => data_counter_max
    );
\data_counter_max_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => data_counter_max0(10),
      Q => \data_counter_max_reg_n_0_[10]\,
      R => data_counter_max
    );
\data_counter_max_reg[10]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \data_counter_max_reg[9]_i_1_n_0\,
      CO(3 downto 0) => \NLW_data_counter_max_reg[10]_i_2_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_data_counter_max_reg[10]_i_2_O_UNCONNECTED\(3 downto 1),
      O(0) => data_counter_max0(10),
      S(3 downto 1) => B"000",
      S(0) => \data_counter_max[10]_i_3_n_0\
    );
\data_counter_max_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(1),
      Q => \data_counter_max_reg_n_0_[1]\,
      R => data_counter_max
    );
\data_counter_max_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => data_counter_max0(2),
      Q => \data_counter_max_reg_n_0_[2]\,
      R => data_counter_max
    );
\data_counter_max_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => data_counter_max0(3),
      Q => \data_counter_max_reg_n_0_[3]\,
      R => data_counter_max
    );
\data_counter_max_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => data_counter_max0(4),
      Q => \data_counter_max_reg_n_0_[4]\,
      R => data_counter_max
    );
\data_counter_max_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => data_counter_max0(5),
      Q => \data_counter_max_reg_n_0_[5]\,
      R => data_counter_max
    );
\data_counter_max_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \data_counter_max_reg[5]_i_1_n_0\,
      CO(2) => \data_counter_max_reg[5]_i_1_n_1\,
      CO(1) => \data_counter_max_reg[5]_i_1_n_2\,
      CO(0) => \data_counter_max_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \data_counter_max[5]_i_2_n_0\,
      DI(2) => \data_counter_max[5]_i_3_n_0\,
      DI(1) => \data_counter_max[5]_i_4_n_0\,
      DI(0) => '0',
      O(3 downto 0) => data_counter_max0(5 downto 2),
      S(3) => \data_counter_max[5]_i_5_n_0\,
      S(2) => \data_counter_max[5]_i_6_n_0\,
      S(1) => \data_counter_max[5]_i_7_n_0\,
      S(0) => \data_counter_max[5]_i_8_n_0\
    );
\data_counter_max_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => data_counter_max0(6),
      Q => \data_counter_max_reg_n_0_[6]\,
      R => data_counter_max
    );
\data_counter_max_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => data_counter_max0(7),
      Q => \data_counter_max_reg_n_0_[7]\,
      R => data_counter_max
    );
\data_counter_max_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => data_counter_max0(8),
      Q => \data_counter_max_reg_n_0_[8]\,
      R => data_counter_max
    );
\data_counter_max_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => data_counter_max0(9),
      Q => \data_counter_max_reg_n_0_[9]\,
      R => data_counter_max
    );
\data_counter_max_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \data_counter_max_reg[5]_i_1_n_0\,
      CO(3) => \data_counter_max_reg[9]_i_1_n_0\,
      CO(2) => \data_counter_max_reg[9]_i_1_n_1\,
      CO(1) => \data_counter_max_reg[9]_i_1_n_2\,
      CO(0) => \data_counter_max_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => bytes01(9 downto 6),
      O(3 downto 0) => data_counter_max0(9 downto 6),
      S(3) => \data_counter_max[9]_i_2_n_0\,
      S(2) => \data_counter_max[9]_i_3_n_0\,
      S(1) => \data_counter_max[9]_i_4_n_0\,
      S(0) => \data_counter_max[9]_i_5_n_0\
    );
\data_to_ram[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => valid_data_byte_read_reg_n_0,
      I1 => temp_data(0),
      O => \data_to_ram[0]_i_1_n_0\
    );
\data_to_ram[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => valid_data_byte_read_reg_n_0,
      I1 => temp_data(1),
      O => \data_to_ram[1]_i_1_n_0\
    );
\data_to_ram[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => valid_data_byte_read_reg_n_0,
      I1 => temp_data(2),
      O => \data_to_ram[2]_i_1_n_0\
    );
\data_to_ram[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => valid_data_byte_read_reg_n_0,
      I1 => temp_data(3),
      O => \data_to_ram[3]_i_1_n_0\
    );
\data_to_ram[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => valid_data_byte_read_reg_n_0,
      I1 => temp_data(4),
      O => \data_to_ram[4]_i_1_n_0\
    );
\data_to_ram[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => valid_data_byte_read_reg_n_0,
      I1 => temp_data(5),
      O => \data_to_ram[5]_i_1_n_0\
    );
\data_to_ram[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => valid_data_byte_read_reg_n_0,
      I1 => temp_data(6),
      O => \data_to_ram[6]_i_1_n_0\
    );
\data_to_ram[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => s_ram(1),
      I1 => wrt_enable_ram,
      O => data_to_ram0
    );
\data_to_ram[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"03030302"
    )
        port map (
      I0 => valid_data_byte_read_reg_n_0,
      I1 => wrt_enable_ram,
      I2 => s_ram(1),
      I3 => rst_ram_reg_n_0,
      I4 => read_frame_done_reg_n_0,
      O => data_to_ram
    );
\data_to_ram[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => valid_data_byte_read_reg_n_0,
      I1 => temp_data(7),
      O => \data_to_ram[7]_i_3_n_0\
    );
\data_to_ram_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => data_to_ram,
      D => \data_to_ram[0]_i_1_n_0\,
      Q => \data_to_ram_reg[7]_0\(0),
      R => data_to_ram0
    );
\data_to_ram_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => data_to_ram,
      D => \data_to_ram[1]_i_1_n_0\,
      Q => \data_to_ram_reg[7]_0\(1),
      R => data_to_ram0
    );
\data_to_ram_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => data_to_ram,
      D => \data_to_ram[2]_i_1_n_0\,
      Q => \data_to_ram_reg[7]_0\(2),
      R => data_to_ram0
    );
\data_to_ram_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => data_to_ram,
      D => \data_to_ram[3]_i_1_n_0\,
      Q => \data_to_ram_reg[7]_0\(3),
      R => data_to_ram0
    );
\data_to_ram_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => data_to_ram,
      D => \data_to_ram[4]_i_1_n_0\,
      Q => \data_to_ram_reg[7]_0\(4),
      R => data_to_ram0
    );
\data_to_ram_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => data_to_ram,
      D => \data_to_ram[5]_i_1_n_0\,
      Q => \data_to_ram_reg[7]_0\(5),
      R => data_to_ram0
    );
\data_to_ram_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => data_to_ram,
      D => \data_to_ram[6]_i_1_n_0\,
      Q => \data_to_ram_reg[7]_0\(6),
      R => data_to_ram0
    );
\data_to_ram_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => data_to_ram,
      D => \data_to_ram[7]_i_3_n_0\,
      Q => \data_to_ram_reg[7]_0\(7),
      R => data_to_ram0
    );
\dest_mac[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880FFFF08800000"
    )
        port map (
      I0 => \dest_mac[32]_i_2_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \dest_mac[1]_i_2_n_0\,
      I5 => dest_mac(0),
      O => \dest_mac[0]_i_1_n_0\
    );
\dest_mac[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010FFFF00100000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \dest_mac[42]_i_2_n_0\,
      I3 => \dest_mac[15]_i_2_n_0\,
      I4 => \dest_mac[11]_i_2_n_0\,
      I5 => dest_mac(10),
      O => \dest_mac[10]_i_1_n_0\
    );
\dest_mac[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010FFFF00100000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \dest_mac[43]_i_2_n_0\,
      I3 => \dest_mac[15]_i_2_n_0\,
      I4 => \dest_mac[11]_i_2_n_0\,
      I5 => dest_mac(11),
      O => \dest_mac[11]_i_1_n_0\
    );
\dest_mac[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000002"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \dest_mac[43]_i_4_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \dest_mac[15]_i_4_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[11]_i_2_n_0\
    );
\dest_mac[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[12]_i_2_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \dest_mac[12]_i_3_n_0\,
      I4 => \dest_mac[13]_i_2_n_0\,
      I5 => dest_mac(12),
      O => \dest_mac[12]_i_1_n_0\
    );
\dest_mac[12]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \byte_count_reg[0]_rep_n_0\,
      O => \dest_mac[12]_i_2_n_0\
    );
\dest_mac[12]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \dest_mac[12]_i_4_n_0\,
      O => \dest_mac[12]_i_3_n_0\
    );
\dest_mac[12]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[4]\,
      I4 => \byte_read_done[12]_i_5_n_0\,
      O => \dest_mac[12]_i_4_n_0\
    );
\dest_mac[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010FFFF00100000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \dest_mac[45]_i_2_n_0\,
      I3 => \dest_mac[15]_i_2_n_0\,
      I4 => \dest_mac[13]_i_2_n_0\,
      I5 => dest_mac(13),
      O => \dest_mac[13]_i_1_n_0\
    );
\dest_mac[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000200"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \byte_count_reg[0]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \dest_mac[45]_i_4_n_0\,
      I4 => \dest_mac[15]_i_4_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[13]_i_2_n_0\
    );
\dest_mac[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010FFFF00100000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \dest_mac[46]_i_2_n_0\,
      I3 => \dest_mac[15]_i_2_n_0\,
      I4 => \dest_mac[15]_i_3_n_0\,
      I5 => dest_mac(14),
      O => \dest_mac[14]_i_1_n_0\
    );
\dest_mac[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010FFFF00100000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \dest_mac[47]_i_2_n_0\,
      I3 => \dest_mac[15]_i_2_n_0\,
      I4 => \dest_mac[15]_i_3_n_0\,
      I5 => dest_mac(15),
      O => \dest_mac[15]_i_1_n_0\
    );
\dest_mac[15]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9F"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \state_reg[1]_rep_n_0\,
      O => \dest_mac[15]_i_2_n_0\
    );
\dest_mac[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000002"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \dest_mac[47]_i_5_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \dest_mac[15]_i_4_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[15]_i_3_n_0\
    );
\dest_mac[15]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFD7FF"
    )
        port map (
      I0 => \state[2]_i_7_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => start_crc_i_2_n_0,
      I4 => \state_reg_n_0_[0]\,
      O => \dest_mac[15]_i_4_n_0\
    );
\dest_mac[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[40]_i_2_n_0\,
      I1 => \dest_mac[23]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \dest_mac[17]_i_2_n_0\,
      I5 => dest_mac(16),
      O => \dest_mac[16]_i_1_n_0\
    );
\dest_mac[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[41]_i_2_n_0\,
      I1 => \dest_mac[23]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \dest_mac[17]_i_2_n_0\,
      I5 => dest_mac(17),
      O => \dest_mac[17]_i_1_n_0\
    );
\dest_mac[17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040004000404444"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \byte_count[10]_i_11_n_0\,
      I2 => \dest_mac[41]_i_4_n_0\,
      I3 => \dest_mac[23]_i_4_n_0\,
      I4 => \state_reg[1]_rep_n_0\,
      I5 => \state_reg_n_0_[0]\,
      O => \dest_mac[17]_i_2_n_0\
    );
\dest_mac[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[42]_i_2_n_0\,
      I1 => \dest_mac[23]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \dest_mac[19]_i_2_n_0\,
      I5 => dest_mac(18),
      O => \dest_mac[18]_i_1_n_0\
    );
\dest_mac[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[43]_i_2_n_0\,
      I1 => \dest_mac[23]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \dest_mac[19]_i_2_n_0\,
      I5 => dest_mac(19),
      O => \dest_mac[19]_i_1_n_0\
    );
\dest_mac[19]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000400044444"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \byte_count[10]_i_11_n_0\,
      I2 => \dest_mac[43]_i_4_n_0\,
      I3 => \dest_mac[23]_i_4_n_0\,
      I4 => \state_reg[1]_rep_n_0\,
      I5 => \state_reg_n_0_[0]\,
      O => \dest_mac[19]_i_2_n_0\
    );
\dest_mac[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880FFFF08800000"
    )
        port map (
      I0 => \dest_mac[33]_i_2_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \dest_mac[1]_i_2_n_0\,
      I5 => dest_mac(1),
      O => \dest_mac[1]_i_1_n_0\
    );
\dest_mac[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000800"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \dest_mac[41]_i_4_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      I4 => \dest_mac[15]_i_4_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[1]_i_2_n_0\
    );
\dest_mac[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[44]_i_2_n_0\,
      I1 => \dest_mac[23]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \dest_mac[21]_i_2_n_0\,
      I5 => dest_mac(20),
      O => \dest_mac[20]_i_1_n_0\
    );
\dest_mac[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[45]_i_2_n_0\,
      I1 => \dest_mac[23]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \dest_mac[21]_i_2_n_0\,
      I5 => dest_mac(21),
      O => \dest_mac[21]_i_1_n_0\
    );
\dest_mac[21]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040004000404444"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \byte_count[10]_i_11_n_0\,
      I2 => \dest_mac[45]_i_4_n_0\,
      I3 => \dest_mac[23]_i_4_n_0\,
      I4 => \state_reg[1]_rep_n_0\,
      I5 => \state_reg_n_0_[0]\,
      O => \dest_mac[21]_i_2_n_0\
    );
\dest_mac[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[46]_i_2_n_0\,
      I1 => \dest_mac[23]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \dest_mac[23]_i_3_n_0\,
      I5 => dest_mac(22),
      O => \dest_mac[22]_i_1_n_0\
    );
\dest_mac[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[47]_i_2_n_0\,
      I1 => \dest_mac[23]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \dest_mac[23]_i_3_n_0\,
      I5 => dest_mac(23),
      O => \dest_mac[23]_i_1_n_0\
    );
\dest_mac[23]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \byte_count_reg[0]_rep__1_n_0\,
      O => \dest_mac[23]_i_2_n_0\
    );
\dest_mac[23]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000400044444"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \byte_count[10]_i_11_n_0\,
      I2 => \dest_mac[47]_i_5_n_0\,
      I3 => \dest_mac[23]_i_4_n_0\,
      I4 => \state_reg[1]_rep_n_0\,
      I5 => \state_reg_n_0_[0]\,
      O => \dest_mac[23]_i_3_n_0\
    );
\dest_mac[23]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFDFFFFFFFFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \dest_mac[31]_i_5_n_0\,
      I4 => \source_mac[47]_i_4_n_0\,
      I5 => \byte_count_reg[0]_rep__1_n_0\,
      O => \dest_mac[23]_i_4_n_0\
    );
\dest_mac[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[40]_i_2_n_0\,
      I1 => \dest_mac[31]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \byte_count_reg[1]_rep_n_0\,
      I4 => \dest_mac[25]_i_2_n_0\,
      I5 => dest_mac(24),
      O => \dest_mac[24]_i_1_n_0\
    );
\dest_mac[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[41]_i_2_n_0\,
      I1 => \dest_mac[31]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \byte_count_reg[1]_rep_n_0\,
      I4 => \dest_mac[25]_i_2_n_0\,
      I5 => dest_mac(25),
      O => \dest_mac[25]_i_1_n_0\
    );
\dest_mac[25]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040004000404444"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \byte_count[10]_i_11_n_0\,
      I2 => \dest_mac[41]_i_4_n_0\,
      I3 => \dest_mac[31]_i_4_n_0\,
      I4 => \state_reg[1]_rep_n_0\,
      I5 => \state_reg_n_0_[0]\,
      O => \dest_mac[25]_i_2_n_0\
    );
\dest_mac[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[42]_i_2_n_0\,
      I1 => \dest_mac[31]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \byte_count_reg[1]_rep_n_0\,
      I4 => \dest_mac[27]_i_2_n_0\,
      I5 => dest_mac(26),
      O => \dest_mac[26]_i_1_n_0\
    );
\dest_mac[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[43]_i_2_n_0\,
      I1 => \dest_mac[31]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \byte_count_reg[1]_rep_n_0\,
      I4 => \dest_mac[27]_i_2_n_0\,
      I5 => dest_mac(27),
      O => \dest_mac[27]_i_1_n_0\
    );
\dest_mac[27]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000400044444"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \byte_count[10]_i_11_n_0\,
      I2 => \dest_mac[43]_i_4_n_0\,
      I3 => \dest_mac[31]_i_4_n_0\,
      I4 => \state_reg[1]_rep_n_0\,
      I5 => \state_reg_n_0_[0]\,
      O => \dest_mac[27]_i_2_n_0\
    );
\dest_mac[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[44]_i_2_n_0\,
      I1 => \dest_mac[31]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \byte_count_reg[1]_rep_n_0\,
      I4 => \dest_mac[29]_i_2_n_0\,
      I5 => dest_mac(28),
      O => \dest_mac[28]_i_1_n_0\
    );
\dest_mac[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[45]_i_2_n_0\,
      I1 => \dest_mac[31]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \byte_count_reg[1]_rep_n_0\,
      I4 => \dest_mac[29]_i_2_n_0\,
      I5 => dest_mac(29),
      O => \dest_mac[29]_i_1_n_0\
    );
\dest_mac[29]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040004000404444"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \byte_count[10]_i_11_n_0\,
      I2 => \dest_mac[45]_i_4_n_0\,
      I3 => \dest_mac[31]_i_4_n_0\,
      I4 => \state_reg[1]_rep_n_0\,
      I5 => \state_reg_n_0_[0]\,
      O => \dest_mac[29]_i_2_n_0\
    );
\dest_mac[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880FFFF08800000"
    )
        port map (
      I0 => \dest_mac[34]_i_2_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \dest_mac[3]_i_2_n_0\,
      I5 => dest_mac(2),
      O => \dest_mac[2]_i_1_n_0\
    );
\dest_mac[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[46]_i_2_n_0\,
      I1 => \dest_mac[31]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \byte_count_reg[1]_rep_n_0\,
      I4 => \dest_mac[31]_i_3_n_0\,
      I5 => dest_mac(30),
      O => \dest_mac[30]_i_1_n_0\
    );
\dest_mac[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \dest_mac[47]_i_2_n_0\,
      I1 => \dest_mac[31]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      I3 => \byte_count_reg[1]_rep_n_0\,
      I4 => \dest_mac[31]_i_3_n_0\,
      I5 => dest_mac(31),
      O => \dest_mac[31]_i_1_n_0\
    );
\dest_mac[31]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[2]\,
      O => \dest_mac[31]_i_2_n_0\
    );
\dest_mac[31]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004000400044444"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \byte_count[10]_i_11_n_0\,
      I2 => \dest_mac[47]_i_5_n_0\,
      I3 => \dest_mac[31]_i_4_n_0\,
      I4 => \state_reg[1]_rep_n_0\,
      I5 => \state_reg_n_0_[0]\,
      O => \dest_mac[31]_i_3_n_0\
    );
\dest_mac[31]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFBFFFF"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \dest_mac[31]_i_5_n_0\,
      I5 => \source_mac[47]_i_4_n_0\,
      O => \dest_mac[31]_i_4_n_0\
    );
\dest_mac[31]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => start_crc_i_2_n_0,
      I1 => \state_reg_n_0_[0]\,
      O => \dest_mac[31]_i_5_n_0\
    );
\dest_mac[32]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8200FFFF82000000"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \dest_mac[32]_i_2_n_0\,
      I4 => \dest_mac[33]_i_3_n_0\,
      I5 => dest_mac(32),
      O => \dest_mac[32]_i_1_n_0\
    );
\dest_mac[32]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \dest_mac[39]_i_4_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bit_count_reg[0]_rep_n_0\,
      I5 => eth_rxd(0),
      O => \dest_mac[32]_i_2_n_0\
    );
\dest_mac[33]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8200FFFF82000000"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \dest_mac[33]_i_2_n_0\,
      I4 => \dest_mac[33]_i_3_n_0\,
      I5 => dest_mac(33),
      O => \dest_mac[33]_i_1_n_0\
    );
\dest_mac[33]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \dest_mac[39]_i_4_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bit_count_reg[0]_rep_n_0\,
      I5 => eth_rxd(1),
      O => \dest_mac[33]_i_2_n_0\
    );
\dest_mac[33]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00800000"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \dest_mac[47]_i_6_n_0\,
      I2 => \dest_mac[41]_i_4_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg[0]_rep__1_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[33]_i_3_n_0\
    );
\dest_mac[34]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8200FFFF82000000"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \dest_mac[34]_i_2_n_0\,
      I4 => \dest_mac[35]_i_3_n_0\,
      I5 => dest_mac(34),
      O => \dest_mac[34]_i_1_n_0\
    );
\dest_mac[34]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => \dest_mac[39]_i_4_n_0\,
      I5 => eth_rxd(0),
      O => \dest_mac[34]_i_2_n_0\
    );
\dest_mac[35]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8200FFFF82000000"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \dest_mac[35]_i_2_n_0\,
      I4 => \dest_mac[35]_i_3_n_0\,
      I5 => dest_mac(35),
      O => \dest_mac[35]_i_1_n_0\
    );
\dest_mac[35]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002000000000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => ip_header_options1(2),
      I4 => \dest_mac[39]_i_4_n_0\,
      I5 => eth_rxd(1),
      O => \dest_mac[35]_i_2_n_0\
    );
\dest_mac[35]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00080000"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \dest_mac[47]_i_6_n_0\,
      I2 => \dest_mac[43]_i_4_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg[0]_rep__1_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[35]_i_3_n_0\
    );
\dest_mac[36]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8200FFFF82000000"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \dest_mac[36]_i_2_n_0\,
      I4 => \dest_mac[37]_i_3_n_0\,
      I5 => dest_mac(36),
      O => \dest_mac[36]_i_1_n_0\
    );
\dest_mac[36]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \dest_mac[39]_i_4_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bit_count_reg[0]_rep_n_0\,
      I5 => eth_rxd(0),
      O => \dest_mac[36]_i_2_n_0\
    );
\dest_mac[37]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8200FFFF82000000"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \dest_mac[37]_i_2_n_0\,
      I4 => \dest_mac[37]_i_3_n_0\,
      I5 => dest_mac(37),
      O => \dest_mac[37]_i_1_n_0\
    );
\dest_mac[37]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \dest_mac[39]_i_4_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bit_count_reg[0]_rep_n_0\,
      I5 => eth_rxd(1),
      O => \dest_mac[37]_i_2_n_0\
    );
\dest_mac[37]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00800000"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \dest_mac[47]_i_6_n_0\,
      I2 => \dest_mac[45]_i_4_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg[0]_rep__1_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[37]_i_3_n_0\
    );
\dest_mac[38]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8200FFFF82000000"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \dest_mac[38]_i_2_n_0\,
      I4 => \dest_mac[39]_i_3_n_0\,
      I5 => dest_mac(38),
      O => \dest_mac[38]_i_1_n_0\
    );
\dest_mac[38]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => ip_header_options1(2),
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => \dest_mac[39]_i_4_n_0\,
      I5 => eth_rxd(0),
      O => \dest_mac[38]_i_2_n_0\
    );
\dest_mac[39]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8200FFFF82000000"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \dest_mac[39]_i_2_n_0\,
      I4 => \dest_mac[39]_i_3_n_0\,
      I5 => dest_mac(39),
      O => \dest_mac[39]_i_1_n_0\
    );
\dest_mac[39]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000200000000000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => ip_header_options1(2),
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => \dest_mac[39]_i_4_n_0\,
      I5 => eth_rxd(1),
      O => \dest_mac[39]_i_2_n_0\
    );
\dest_mac[39]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00080000"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \dest_mac[47]_i_6_n_0\,
      I2 => \dest_mac[47]_i_5_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg[0]_rep__1_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[39]_i_3_n_0\
    );
\dest_mac[39]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFEEE"
    )
        port map (
      I0 => \byte_read_done[12]_i_5_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[3]\,
      O => \dest_mac[39]_i_4_n_0\
    );
\dest_mac[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880FFFF08800000"
    )
        port map (
      I0 => \dest_mac[35]_i_2_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \dest_mac[3]_i_2_n_0\,
      I5 => dest_mac(3),
      O => \dest_mac[3]_i_1_n_0\
    );
\dest_mac[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000200"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \dest_mac[43]_i_4_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      I4 => \dest_mac[15]_i_4_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[3]_i_2_n_0\
    );
\dest_mac[40]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200FFFF02000000"
    )
        port map (
      I0 => \dest_mac[47]_i_3_n_0\,
      I1 => \byte_count_reg[0]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \dest_mac[40]_i_2_n_0\,
      I4 => \dest_mac[41]_i_3_n_0\,
      I5 => dest_mac(40),
      O => \dest_mac[40]_i_1_n_0\
    );
\dest_mac[40]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dest_mac[41]_i_4_n_0\,
      I1 => eth_rxd(0),
      O => \dest_mac[40]_i_2_n_0\
    );
\dest_mac[41]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200FFFF02000000"
    )
        port map (
      I0 => \dest_mac[47]_i_3_n_0\,
      I1 => \byte_count_reg[0]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \dest_mac[41]_i_2_n_0\,
      I4 => \dest_mac[41]_i_3_n_0\,
      I5 => dest_mac(41),
      O => \dest_mac[41]_i_1_n_0\
    );
\dest_mac[41]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dest_mac[41]_i_4_n_0\,
      I1 => eth_rxd(1),
      O => \dest_mac[41]_i_2_n_0\
    );
\dest_mac[41]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00080000"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \dest_mac[47]_i_6_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \dest_mac[41]_i_4_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[41]_i_3_n_0\
    );
\dest_mac[41]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \bit_count_reg[0]_rep_n_0\,
      I1 => ip_header_options1(2),
      I2 => \dest_mac[39]_i_4_n_0\,
      O => \dest_mac[41]_i_4_n_0\
    );
\dest_mac[42]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200FFFF02000000"
    )
        port map (
      I0 => \dest_mac[47]_i_3_n_0\,
      I1 => \byte_count_reg[0]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \dest_mac[42]_i_2_n_0\,
      I4 => \dest_mac[43]_i_3_n_0\,
      I5 => dest_mac(42),
      O => \dest_mac[42]_i_1_n_0\
    );
\dest_mac[42]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \dest_mac[43]_i_4_n_0\,
      O => \dest_mac[42]_i_2_n_0\
    );
\dest_mac[43]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200FFFF02000000"
    )
        port map (
      I0 => \dest_mac[47]_i_3_n_0\,
      I1 => \byte_count_reg[0]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \dest_mac[43]_i_2_n_0\,
      I4 => \dest_mac[43]_i_3_n_0\,
      I5 => dest_mac(43),
      O => \dest_mac[43]_i_1_n_0\
    );
\dest_mac[43]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \dest_mac[43]_i_4_n_0\,
      O => \dest_mac[43]_i_2_n_0\
    );
\dest_mac[43]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000008"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \dest_mac[47]_i_6_n_0\,
      I2 => \dest_mac[43]_i_4_n_0\,
      I3 => \byte_count_reg[0]_rep_n_0\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[43]_i_3_n_0\
    );
\dest_mac[43]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \dest_mac[39]_i_4_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      O => \dest_mac[43]_i_4_n_0\
    );
\dest_mac[44]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \dest_mac[47]_i_3_n_0\,
      I1 => \dest_mac[44]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \dest_mac[45]_i_3_n_0\,
      I5 => dest_mac(44),
      O => \dest_mac[44]_i_1_n_0\
    );
\dest_mac[44]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dest_mac[45]_i_4_n_0\,
      I1 => eth_rxd(0),
      O => \dest_mac[44]_i_2_n_0\
    );
\dest_mac[45]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200FFFF02000000"
    )
        port map (
      I0 => \dest_mac[47]_i_3_n_0\,
      I1 => \byte_count_reg[0]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \dest_mac[45]_i_2_n_0\,
      I4 => \dest_mac[45]_i_3_n_0\,
      I5 => dest_mac(45),
      O => \dest_mac[45]_i_1_n_0\
    );
\dest_mac[45]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \dest_mac[45]_i_4_n_0\,
      I1 => eth_rxd(1),
      O => \dest_mac[45]_i_2_n_0\
    );
\dest_mac[45]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00080000"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \dest_mac[47]_i_6_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \dest_mac[45]_i_4_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[45]_i_3_n_0\
    );
\dest_mac[45]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \bit_count_reg[0]_rep_n_0\,
      I1 => ip_header_options1(2),
      I2 => \dest_mac[39]_i_4_n_0\,
      O => \dest_mac[45]_i_4_n_0\
    );
\dest_mac[46]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200FFFF02000000"
    )
        port map (
      I0 => \dest_mac[47]_i_3_n_0\,
      I1 => \byte_count_reg[0]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \dest_mac[46]_i_2_n_0\,
      I4 => \dest_mac[47]_i_4_n_0\,
      I5 => dest_mac(46),
      O => \dest_mac[46]_i_1_n_0\
    );
\dest_mac[46]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \dest_mac[47]_i_5_n_0\,
      O => \dest_mac[46]_i_2_n_0\
    );
\dest_mac[47]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000FFFF10000000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \dest_mac[47]_i_2_n_0\,
      I3 => \dest_mac[47]_i_3_n_0\,
      I4 => \dest_mac[47]_i_4_n_0\,
      I5 => dest_mac(47),
      O => \dest_mac[47]_i_1_n_0\
    );
\dest_mac[47]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \dest_mac[47]_i_5_n_0\,
      O => \dest_mac[47]_i_2_n_0\
    );
\dest_mac[47]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"90"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \state_reg[1]_rep_n_0\,
      O => \dest_mac[47]_i_3_n_0\
    );
\dest_mac[47]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00020000"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \dest_mac[47]_i_5_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \dest_mac[47]_i_6_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[47]_i_4_n_0\
    );
\dest_mac[47]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEAFFFFFFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[4]\,
      I4 => \byte_read_done[12]_i_5_n_0\,
      I5 => \byte_read_done[6]_i_2_n_0\,
      O => \dest_mac[47]_i_5_n_0\
    );
\dest_mac[47]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => start_crc_i_2_n_0,
      O => \dest_mac[47]_i_6_n_0\
    );
\dest_mac[47]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \state_reg_n_0_[0]\,
      O => \dest_mac[47]_i_7_n_0\
    );
\dest_mac[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880FFFF08800000"
    )
        port map (
      I0 => \dest_mac[36]_i_2_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \dest_mac[5]_i_2_n_0\,
      I5 => dest_mac(4),
      O => \dest_mac[4]_i_1_n_0\
    );
\dest_mac[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880FFFF08800000"
    )
        port map (
      I0 => \dest_mac[37]_i_2_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \dest_mac[5]_i_2_n_0\,
      I5 => dest_mac(5),
      O => \dest_mac[5]_i_1_n_0\
    );
\dest_mac[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000800"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \dest_mac[45]_i_4_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      I4 => \dest_mac[15]_i_4_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[5]_i_2_n_0\
    );
\dest_mac[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880FFFF08800000"
    )
        port map (
      I0 => \dest_mac[38]_i_2_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \dest_mac[7]_i_2_n_0\,
      I5 => dest_mac(6),
      O => \dest_mac[6]_i_1_n_0\
    );
\dest_mac[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0880FFFF08800000"
    )
        port map (
      I0 => \dest_mac[39]_i_2_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \dest_mac[7]_i_2_n_0\,
      I5 => dest_mac(7),
      O => \dest_mac[7]_i_1_n_0\
    );
\dest_mac[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000200"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \dest_mac[47]_i_5_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      I4 => \dest_mac[15]_i_4_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[7]_i_2_n_0\
    );
\dest_mac[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010FFFF00100000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \dest_mac[40]_i_2_n_0\,
      I3 => \dest_mac[15]_i_2_n_0\,
      I4 => \dest_mac[9]_i_2_n_0\,
      I5 => dest_mac(8),
      O => \dest_mac[8]_i_1_n_0\
    );
\dest_mac[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0010FFFF00100000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \dest_mac[41]_i_2_n_0\,
      I3 => \dest_mac[15]_i_2_n_0\,
      I4 => \dest_mac[9]_i_2_n_0\,
      I5 => dest_mac(9),
      O => \dest_mac[9]_i_1_n_0\
    );
\dest_mac[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00000200"
    )
        port map (
      I0 => \byte_count[10]_i_5_n_0\,
      I1 => \byte_count_reg[0]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \dest_mac[41]_i_4_n_0\,
      I4 => \dest_mac[15]_i_4_n_0\,
      I5 => \dest_mac[47]_i_7_n_0\,
      O => \dest_mac[9]_i_2_n_0\
    );
\dest_mac_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[0]_i_1_n_0\,
      Q => dest_mac(0),
      R => '0'
    );
\dest_mac_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[10]_i_1_n_0\,
      Q => dest_mac(10),
      R => '0'
    );
\dest_mac_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[11]_i_1_n_0\,
      Q => dest_mac(11),
      R => '0'
    );
\dest_mac_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[12]_i_1_n_0\,
      Q => dest_mac(12),
      R => '0'
    );
\dest_mac_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[13]_i_1_n_0\,
      Q => dest_mac(13),
      R => '0'
    );
\dest_mac_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[14]_i_1_n_0\,
      Q => dest_mac(14),
      R => '0'
    );
\dest_mac_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[15]_i_1_n_0\,
      Q => dest_mac(15),
      R => '0'
    );
\dest_mac_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[16]_i_1_n_0\,
      Q => dest_mac(16),
      R => '0'
    );
\dest_mac_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[17]_i_1_n_0\,
      Q => dest_mac(17),
      R => '0'
    );
\dest_mac_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[18]_i_1_n_0\,
      Q => dest_mac(18),
      R => '0'
    );
\dest_mac_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[19]_i_1_n_0\,
      Q => dest_mac(19),
      R => '0'
    );
\dest_mac_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[1]_i_1_n_0\,
      Q => dest_mac(1),
      R => '0'
    );
\dest_mac_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[20]_i_1_n_0\,
      Q => dest_mac(20),
      R => '0'
    );
\dest_mac_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[21]_i_1_n_0\,
      Q => dest_mac(21),
      R => '0'
    );
\dest_mac_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[22]_i_1_n_0\,
      Q => dest_mac(22),
      R => '0'
    );
\dest_mac_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[23]_i_1_n_0\,
      Q => dest_mac(23),
      R => '0'
    );
\dest_mac_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[24]_i_1_n_0\,
      Q => dest_mac(24),
      R => '0'
    );
\dest_mac_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[25]_i_1_n_0\,
      Q => dest_mac(25),
      R => '0'
    );
\dest_mac_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[26]_i_1_n_0\,
      Q => dest_mac(26),
      R => '0'
    );
\dest_mac_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[27]_i_1_n_0\,
      Q => dest_mac(27),
      R => '0'
    );
\dest_mac_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[28]_i_1_n_0\,
      Q => dest_mac(28),
      R => '0'
    );
\dest_mac_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[29]_i_1_n_0\,
      Q => dest_mac(29),
      R => '0'
    );
\dest_mac_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[2]_i_1_n_0\,
      Q => dest_mac(2),
      R => '0'
    );
\dest_mac_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[30]_i_1_n_0\,
      Q => dest_mac(30),
      R => '0'
    );
\dest_mac_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[31]_i_1_n_0\,
      Q => dest_mac(31),
      R => '0'
    );
\dest_mac_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[32]_i_1_n_0\,
      Q => dest_mac(32),
      R => '0'
    );
\dest_mac_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[33]_i_1_n_0\,
      Q => dest_mac(33),
      R => '0'
    );
\dest_mac_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[34]_i_1_n_0\,
      Q => dest_mac(34),
      R => '0'
    );
\dest_mac_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[35]_i_1_n_0\,
      Q => dest_mac(35),
      R => '0'
    );
\dest_mac_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[36]_i_1_n_0\,
      Q => dest_mac(36),
      R => '0'
    );
\dest_mac_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[37]_i_1_n_0\,
      Q => dest_mac(37),
      R => '0'
    );
\dest_mac_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[38]_i_1_n_0\,
      Q => dest_mac(38),
      R => '0'
    );
\dest_mac_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[39]_i_1_n_0\,
      Q => dest_mac(39),
      R => '0'
    );
\dest_mac_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[3]_i_1_n_0\,
      Q => dest_mac(3),
      R => '0'
    );
\dest_mac_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[40]_i_1_n_0\,
      Q => dest_mac(40),
      R => '0'
    );
\dest_mac_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[41]_i_1_n_0\,
      Q => dest_mac(41),
      R => '0'
    );
\dest_mac_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[42]_i_1_n_0\,
      Q => dest_mac(42),
      R => '0'
    );
\dest_mac_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[43]_i_1_n_0\,
      Q => dest_mac(43),
      R => '0'
    );
\dest_mac_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[44]_i_1_n_0\,
      Q => dest_mac(44),
      R => '0'
    );
\dest_mac_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[45]_i_1_n_0\,
      Q => dest_mac(45),
      R => '0'
    );
\dest_mac_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[46]_i_1_n_0\,
      Q => dest_mac(46),
      R => '0'
    );
\dest_mac_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[47]_i_1_n_0\,
      Q => dest_mac(47),
      R => '0'
    );
\dest_mac_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[4]_i_1_n_0\,
      Q => dest_mac(4),
      R => '0'
    );
\dest_mac_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[5]_i_1_n_0\,
      Q => dest_mac(5),
      R => '0'
    );
\dest_mac_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[6]_i_1_n_0\,
      Q => dest_mac(6),
      R => '0'
    );
\dest_mac_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[7]_i_1_n_0\,
      Q => dest_mac(7),
      R => '0'
    );
\dest_mac_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[8]_i_1_n_0\,
      Q => dest_mac(8),
      R => '0'
    );
\dest_mac_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \dest_mac[9]_i_1_n_0\,
      Q => dest_mac(9),
      R => '0'
    );
edge_count_data_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0060"
    )
        port map (
      I0 => \edge_count_data__0\,
      I1 => valid_data_byte_read_reg_n_0,
      I2 => start_crc_reg_n_0,
      I3 => udp_datasum_done14_out,
      O => edge_count_data_i_1_n_0
    );
edge_count_data_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => edge_count_data_i_1_n_0,
      Q => \edge_count_data__0\,
      R => '0'
    );
edge_count_header_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F3FFFFFF08000000"
    )
        port map (
      I0 => ip_extra_options,
      I1 => edge_count_header,
      I2 => ip_hcs_done,
      I3 => \byte_read_done_reg_n_0_[9]\,
      I4 => identification,
      I5 => edge_count_header_reg_n_0,
      O => edge_count_header_i_1_n_0
    );
edge_count_header_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => edge_count_header_i_1_n_0,
      Q => edge_count_header_reg_n_0,
      R => '0'
    );
\eth_prot_type[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \eth_prot_type[8]_i_2_n_0\,
      I3 => \eth_prot_type[1]_i_2_n_0\,
      I4 => eth_prot_type(0),
      O => \eth_prot_type[0]_i_1_n_0\
    );
\eth_prot_type[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \eth_prot_type[10]_i_2_n_0\,
      I3 => \eth_prot_type[11]_i_3_n_0\,
      I4 => eth_prot_type(10),
      O => \eth_prot_type[10]_i_1_n_0\
    );
\eth_prot_type[10]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \eth_prot_type[11]_i_4_n_0\,
      O => \eth_prot_type[10]_i_2_n_0\
    );
\eth_prot_type[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \eth_prot_type[11]_i_2_n_0\,
      I3 => \eth_prot_type[11]_i_3_n_0\,
      I4 => eth_prot_type(11),
      O => \eth_prot_type[11]_i_1_n_0\
    );
\eth_prot_type[11]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \eth_prot_type[11]_i_4_n_0\,
      O => \eth_prot_type[11]_i_2_n_0\
    );
\eth_prot_type[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000800AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \eth_prot_type[15]_i_4_n_0\,
      I2 => \eth_prot_type[13]_i_5_n_0\,
      I3 => \bit_count_reg[0]_rep_n_0\,
      I4 => ip_header_options1(2),
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \eth_prot_type[11]_i_3_n_0\
    );
\eth_prot_type[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFFFFFF"
    )
        port map (
      I0 => \byte_read_done[12]_i_5_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \source_mac[35]_i_2_n_0\,
      O => \eth_prot_type[11]_i_4_n_0\
    );
\eth_prot_type[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \eth_prot_type[12]_i_2_n_0\,
      I3 => \eth_prot_type[13]_i_3_n_0\,
      I4 => eth_prot_type(12),
      O => \eth_prot_type[12]_i_1_n_0\
    );
\eth_prot_type[12]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \eth_prot_type[13]_i_4_n_0\,
      O => \eth_prot_type[12]_i_2_n_0\
    );
\eth_prot_type[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \eth_prot_type[13]_i_2_n_0\,
      I3 => \eth_prot_type[13]_i_3_n_0\,
      I4 => eth_prot_type(13),
      O => \eth_prot_type[13]_i_1_n_0\
    );
\eth_prot_type[13]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \eth_prot_type[13]_i_4_n_0\,
      O => \eth_prot_type[13]_i_2_n_0\
    );
\eth_prot_type[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000800AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \eth_prot_type[15]_i_4_n_0\,
      I2 => \eth_prot_type[13]_i_5_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bit_count_reg[0]_rep_n_0\,
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \eth_prot_type[13]_i_3_n_0\
    );
\eth_prot_type[13]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFFFFFF"
    )
        port map (
      I0 => \byte_read_done[12]_i_5_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \source_mac[37]_i_2_n_0\,
      O => \eth_prot_type[13]_i_4_n_0\
    );
\eth_prot_type[13]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF7"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_read_done[12]_i_5_n_0\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \byte_count_reg[0]_rep__1_n_0\,
      O => \eth_prot_type[13]_i_5_n_0\
    );
\eth_prot_type[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \eth_prot_type[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \eth_prot_type[15]_i_3_n_0\,
      I5 => eth_prot_type(14),
      O => \eth_prot_type[14]_i_1_n_0\
    );
\eth_prot_type[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \eth_prot_type[15]_i_2_n_0\,
      I1 => eth_rxd(1),
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \eth_prot_type[15]_i_3_n_0\,
      I5 => eth_prot_type(15),
      O => \eth_prot_type[15]_i_1_n_0\
    );
\eth_prot_type[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \byte_read_done[12]_i_5_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_read_done[6]_i_2_n_0\,
      I5 => \byte_count_reg_n_0_[1]\,
      O => \eth_prot_type[15]_i_2_n_0\
    );
\eth_prot_type[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08000000AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \eth_prot_type[15]_i_4_n_0\,
      I2 => \byte_read_done[6]_i_3_n_0\,
      I3 => \eth_prot_type[15]_i_5_n_0\,
      I4 => \byte_read_done[6]_i_2_n_0\,
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \eth_prot_type[15]_i_3_n_0\
    );
\eth_prot_type[15]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEEE0000"
    )
        port map (
      I0 => \byte_count_reg_n_0_[4]\,
      I1 => \byte_read_done[12]_i_5_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => start_crc_i_2_n_0,
      O => \eth_prot_type[15]_i_4_n_0\
    );
\eth_prot_type[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      O => \eth_prot_type[15]_i_5_n_0\
    );
\eth_prot_type[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \eth_prot_type[9]_i_2_n_0\,
      I3 => \eth_prot_type[1]_i_2_n_0\,
      I4 => eth_prot_type(1),
      O => \eth_prot_type[1]_i_1_n_0\
    );
\eth_prot_type[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008000AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \eth_prot_type[15]_i_4_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \source_mac[33]_i_2_n_0\,
      I4 => \byte_count[1]_i_5_n_0\,
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \eth_prot_type[1]_i_2_n_0\
    );
\eth_prot_type[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \eth_prot_type[10]_i_2_n_0\,
      I3 => \eth_prot_type[3]_i_2_n_0\,
      I4 => eth_prot_type(2),
      O => \eth_prot_type[2]_i_1_n_0\
    );
\eth_prot_type[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \eth_prot_type[11]_i_2_n_0\,
      I3 => \eth_prot_type[3]_i_2_n_0\,
      I4 => eth_prot_type(3),
      O => \eth_prot_type[3]_i_1_n_0\
    );
\eth_prot_type[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008000AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \eth_prot_type[15]_i_4_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \source_mac[35]_i_2_n_0\,
      I4 => \byte_count[1]_i_5_n_0\,
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \eth_prot_type[3]_i_2_n_0\
    );
\eth_prot_type[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \eth_prot_type[12]_i_2_n_0\,
      I3 => \eth_prot_type[5]_i_2_n_0\,
      I4 => eth_prot_type(4),
      O => \eth_prot_type[4]_i_1_n_0\
    );
\eth_prot_type[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08FF0800"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \eth_prot_type[13]_i_2_n_0\,
      I3 => \eth_prot_type[5]_i_2_n_0\,
      I4 => eth_prot_type(5),
      O => \eth_prot_type[5]_i_1_n_0\
    );
\eth_prot_type[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00008000AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \eth_prot_type[15]_i_4_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \source_mac[37]_i_2_n_0\,
      I4 => \byte_count[1]_i_5_n_0\,
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \eth_prot_type[5]_i_2_n_0\
    );
\eth_prot_type[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \eth_prot_type[15]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \eth_prot_type[7]_i_2_n_0\,
      I5 => eth_prot_type(6),
      O => \eth_prot_type[6]_i_1_n_0\
    );
\eth_prot_type[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => \eth_prot_type[15]_i_2_n_0\,
      I1 => eth_rxd(1),
      I2 => \byte_count_reg[0]_rep_n_0\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \eth_prot_type[7]_i_2_n_0\,
      I5 => eth_prot_type(7),
      O => \eth_prot_type[7]_i_1_n_0\
    );
\eth_prot_type[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \byte_count[10]_i_11_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \eth_prot_type[7]_i_3_n_0\,
      O => \eth_prot_type[7]_i_2_n_0\
    );
\eth_prot_type[7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A8AA"
    )
        port map (
      I0 => \state_reg[1]_rep__0_n_0\,
      I1 => read_eth_header_done_i_2_n_0,
      I2 => \eth_prot_type[7]_i_4_n_0\,
      I3 => start_crc_i_2_n_0,
      O => \eth_prot_type[7]_i_3_n_0\
    );
\eth_prot_type[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFD"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \byte_count_reg_n_0_[9]\,
      I2 => \byte_count_reg_n_0_[10]\,
      I3 => \byte_count_reg_n_0_[8]\,
      I4 => \byte_read_done[3]_i_8_n_0\,
      I5 => \eth_prot_type[7]_i_5_n_0\,
      O => \eth_prot_type[7]_i_4_n_0\
    );
\eth_prot_type[7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FDFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      O => \eth_prot_type[7]_i_5_n_0\
    );
\eth_prot_type[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \eth_prot_type[8]_i_2_n_0\,
      I3 => \eth_prot_type[9]_i_3_n_0\,
      I4 => eth_prot_type(8),
      O => \eth_prot_type[8]_i_1_n_0\
    );
\eth_prot_type[8]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \eth_prot_type[9]_i_4_n_0\,
      O => \eth_prot_type[8]_i_2_n_0\
    );
\eth_prot_type[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"04FF0400"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \eth_prot_type[9]_i_2_n_0\,
      I3 => \eth_prot_type[9]_i_3_n_0\,
      I4 => eth_prot_type(9),
      O => \eth_prot_type[9]_i_1_n_0\
    );
\eth_prot_type[9]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \eth_prot_type[9]_i_4_n_0\,
      O => \eth_prot_type[9]_i_2_n_0\
    );
\eth_prot_type[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000008AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \eth_prot_type[15]_i_4_n_0\,
      I2 => \eth_prot_type[13]_i_5_n_0\,
      I3 => ip_header_options1(2),
      I4 => \bit_count_reg[0]_rep_n_0\,
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \eth_prot_type[9]_i_3_n_0\
    );
\eth_prot_type[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFFFFFFFFFF"
    )
        port map (
      I0 => \byte_read_done[12]_i_5_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \source_mac[33]_i_2_n_0\,
      O => \eth_prot_type[9]_i_4_n_0\
    );
\eth_prot_type_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[0]_i_1_n_0\,
      Q => eth_prot_type(0),
      R => '0'
    );
\eth_prot_type_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[10]_i_1_n_0\,
      Q => eth_prot_type(10),
      R => '0'
    );
\eth_prot_type_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[11]_i_1_n_0\,
      Q => eth_prot_type(11),
      R => '0'
    );
\eth_prot_type_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[12]_i_1_n_0\,
      Q => eth_prot_type(12),
      R => '0'
    );
\eth_prot_type_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[13]_i_1_n_0\,
      Q => eth_prot_type(13),
      R => '0'
    );
\eth_prot_type_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[14]_i_1_n_0\,
      Q => eth_prot_type(14),
      R => '0'
    );
\eth_prot_type_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[15]_i_1_n_0\,
      Q => eth_prot_type(15),
      R => '0'
    );
\eth_prot_type_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[1]_i_1_n_0\,
      Q => eth_prot_type(1),
      R => '0'
    );
\eth_prot_type_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[2]_i_1_n_0\,
      Q => eth_prot_type(2),
      R => '0'
    );
\eth_prot_type_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[3]_i_1_n_0\,
      Q => eth_prot_type(3),
      R => '0'
    );
\eth_prot_type_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[4]_i_1_n_0\,
      Q => eth_prot_type(4),
      R => '0'
    );
\eth_prot_type_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[5]_i_1_n_0\,
      Q => eth_prot_type(5),
      R => '0'
    );
\eth_prot_type_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[6]_i_1_n_0\,
      Q => eth_prot_type(6),
      R => '0'
    );
\eth_prot_type_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[7]_i_1_n_0\,
      Q => eth_prot_type(7),
      R => '0'
    );
\eth_prot_type_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[8]_i_1_n_0\,
      Q => eth_prot_type(8),
      R => '0'
    );
\eth_prot_type_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \eth_prot_type[9]_i_1_n_0\,
      Q => eth_prot_type(9),
      R => '0'
    );
eth_protocol_expected_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => read_eth_header_done,
      I1 => eth_protocol_expected_i_2_n_0,
      I2 => eth_prot_type(2),
      I3 => eth_prot_type(1),
      I4 => eth_protocol_expected_i_3_n_0,
      I5 => eth_protocol_expected_i_4_n_0,
      O => eth_protocol_expected_i_1_n_0
    );
eth_protocol_expected_i_10: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => dest_mac(25),
      I1 => dest_mac(26),
      I2 => dest_mac(29),
      I3 => dest_mac(28),
      I4 => dest_mac(8),
      I5 => dest_mac(6),
      O => eth_protocol_expected_i_10_n_0
    );
eth_protocol_expected_i_11: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBFFFFFFF"
    )
        port map (
      I0 => eth_protocol_expected_i_21_n_0,
      I1 => dest_mac(24),
      I2 => dest_mac(34),
      I3 => dest_mac(33),
      I4 => dest_mac(16),
      I5 => eth_protocol_expected_i_22_n_0,
      O => eth_protocol_expected_i_11_n_0
    );
eth_protocol_expected_i_13: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => dest_mac(46),
      I1 => dest_mac(47),
      I2 => dest_mac(45),
      O => eth_protocol_expected_i_13_n_0
    );
eth_protocol_expected_i_14: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => dest_mac(43),
      I1 => dest_mac(44),
      I2 => dest_mac(42),
      O => eth_protocol_expected_i_14_n_0
    );
eth_protocol_expected_i_15: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => dest_mac(40),
      I1 => dest_mac(41),
      I2 => dest_mac(39),
      O => eth_protocol_expected_i_15_n_0
    );
eth_protocol_expected_i_16: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => dest_mac(38),
      I1 => dest_mac(36),
      I2 => dest_mac(37),
      O => eth_protocol_expected_i_16_n_0
    );
eth_protocol_expected_i_17: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => dest_mac(9),
      I1 => dest_mac(10),
      I2 => dest_mac(11),
      O => eth_protocol_expected_i_17_n_0
    );
eth_protocol_expected_i_18: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => dest_mac(12),
      I1 => dest_mac(13),
      I2 => dest_mac(14),
      O => eth_protocol_expected_i_18_n_0
    );
eth_protocol_expected_i_19: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => dest_mac(42),
      I1 => dest_mac(44),
      I2 => dest_mac(46),
      I3 => dest_mac(4),
      O => eth_protocol_expected_i_19_n_0
    );
eth_protocol_expected_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => eth_prot_type(9),
      I1 => eth_prot_type(15),
      I2 => eth_prot_type(5),
      I3 => eth_prot_type(14),
      I4 => eth_protocol_expected_i_5_n_0,
      I5 => eth_protocol_expected_i_6_n_0,
      O => eth_protocol_expected_i_2_n_0
    );
eth_protocol_expected_i_20: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => dest_mac(3),
      I1 => dest_mac(19),
      I2 => dest_mac(1),
      I3 => dest_mac(23),
      I4 => eth_protocol_expected_i_28_n_0,
      O => eth_protocol_expected_i_20_n_0
    );
eth_protocol_expected_i_21: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => dest_mac(37),
      I1 => dest_mac(40),
      I2 => dest_mac(32),
      I3 => dest_mac(39),
      O => eth_protocol_expected_i_21_n_0
    );
eth_protocol_expected_i_22: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7FFF"
    )
        port map (
      I0 => dest_mac(47),
      I1 => dest_mac(41),
      I2 => dest_mac(15),
      I3 => dest_mac(7),
      I4 => eth_protocol_expected_i_29_n_0,
      O => eth_protocol_expected_i_22_n_0
    );
eth_protocol_expected_i_24: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => dest_mac(34),
      I1 => dest_mac(35),
      I2 => dest_mac(33),
      O => eth_protocol_expected_i_24_n_0
    );
eth_protocol_expected_i_25: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => dest_mac(31),
      I1 => dest_mac(32),
      I2 => dest_mac(30),
      O => eth_protocol_expected_i_25_n_0
    );
eth_protocol_expected_i_26: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => dest_mac(27),
      I1 => dest_mac(28),
      I2 => dest_mac(29),
      O => eth_protocol_expected_i_26_n_0
    );
eth_protocol_expected_i_27: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => dest_mac(25),
      I1 => dest_mac(26),
      I2 => dest_mac(24),
      O => eth_protocol_expected_i_27_n_0
    );
eth_protocol_expected_i_28: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => dest_mac(17),
      I1 => dest_mac(38),
      I2 => dest_mac(43),
      I3 => dest_mac(35),
      O => eth_protocol_expected_i_28_n_0
    );
eth_protocol_expected_i_29: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => dest_mac(21),
      I1 => dest_mac(0),
      I2 => dest_mac(20),
      I3 => dest_mac(27),
      O => eth_protocol_expected_i_29_n_0
    );
eth_protocol_expected_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => eth_prot_type(3),
      I1 => eth_prot_type(11),
      O => eth_protocol_expected_i_3_n_0
    );
eth_protocol_expected_i_31: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => dest_mac(22),
      I1 => dest_mac(23),
      I2 => dest_mac(21),
      O => eth_protocol_expected_i_31_n_0
    );
eth_protocol_expected_i_32: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => dest_mac(19),
      I1 => dest_mac(20),
      I2 => dest_mac(18),
      O => eth_protocol_expected_i_32_n_0
    );
eth_protocol_expected_i_33: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => dest_mac(15),
      I1 => dest_mac(16),
      I2 => dest_mac(17),
      O => eth_protocol_expected_i_33_n_0
    );
eth_protocol_expected_i_34: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => dest_mac(12),
      I1 => dest_mac(13),
      I2 => dest_mac(14),
      O => eth_protocol_expected_i_34_n_0
    );
eth_protocol_expected_i_35: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => dest_mac(9),
      I1 => dest_mac(10),
      I2 => dest_mac(11),
      O => eth_protocol_expected_i_35_n_0
    );
eth_protocol_expected_i_36: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => dest_mac(7),
      I1 => dest_mac(6),
      I2 => dest_mac(8),
      O => eth_protocol_expected_i_36_n_0
    );
eth_protocol_expected_i_37: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00009009"
    )
        port map (
      I0 => ip(3),
      I1 => dest_mac(3),
      I2 => dest_mac(4),
      I3 => ip(4),
      I4 => dest_mac(5),
      O => eth_protocol_expected_i_37_n_0
    );
eth_protocol_expected_i_38: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => ip(2),
      I1 => dest_mac(2),
      I2 => dest_mac(1),
      I3 => ip(1),
      I4 => dest_mac(0),
      I5 => ip(0),
      O => eth_protocol_expected_i_38_n_0
    );
eth_protocol_expected_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55555455"
    )
        port map (
      I0 => arp_request_expected2,
      I1 => eth_protocol_expected_i_8_n_0,
      I2 => eth_protocol_expected_i_9_n_0,
      I3 => eth_protocol_expected_i_10_n_0,
      I4 => eth_protocol_expected_i_11_n_0,
      O => eth_protocol_expected_i_4_n_0
    );
eth_protocol_expected_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => eth_prot_type(0),
      I1 => eth_prot_type(4),
      I2 => eth_prot_type(13),
      I3 => eth_prot_type(10),
      O => eth_protocol_expected_i_5_n_0
    );
eth_protocol_expected_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => eth_prot_type(12),
      I1 => eth_prot_type(8),
      I2 => eth_prot_type(7),
      I3 => eth_prot_type(6),
      O => eth_protocol_expected_i_6_n_0
    );
eth_protocol_expected_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => eth_protocol_expected_i_17_n_0,
      I1 => dest_mac(22),
      I2 => dest_mac(31),
      I3 => dest_mac(5),
      I4 => dest_mac(30),
      I5 => eth_protocol_expected_i_18_n_0,
      O => eth_protocol_expected_i_8_n_0
    );
eth_protocol_expected_i_9: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFBFFFFFFF"
    )
        port map (
      I0 => eth_protocol_expected_i_19_n_0,
      I1 => dest_mac(45),
      I2 => dest_mac(2),
      I3 => dest_mac(18),
      I4 => dest_mac(36),
      I5 => eth_protocol_expected_i_20_n_0,
      O => eth_protocol_expected_i_9_n_0
    );
eth_protocol_expected_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => eth_protocol_expected_i_1_n_0,
      Q => eth_protocol_expected,
      R => '0'
    );
eth_protocol_expected_reg_i_12: unisim.vcomponents.CARRY4
     port map (
      CI => eth_protocol_expected_reg_i_23_n_0,
      CO(3) => eth_protocol_expected_reg_i_12_n_0,
      CO(2) => eth_protocol_expected_reg_i_12_n_1,
      CO(1) => eth_protocol_expected_reg_i_12_n_2,
      CO(0) => eth_protocol_expected_reg_i_12_n_3,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_eth_protocol_expected_reg_i_12_O_UNCONNECTED(3 downto 0),
      S(3) => eth_protocol_expected_i_24_n_0,
      S(2) => eth_protocol_expected_i_25_n_0,
      S(1) => eth_protocol_expected_i_26_n_0,
      S(0) => eth_protocol_expected_i_27_n_0
    );
eth_protocol_expected_reg_i_23: unisim.vcomponents.CARRY4
     port map (
      CI => eth_protocol_expected_reg_i_30_n_0,
      CO(3) => eth_protocol_expected_reg_i_23_n_0,
      CO(2) => eth_protocol_expected_reg_i_23_n_1,
      CO(1) => eth_protocol_expected_reg_i_23_n_2,
      CO(0) => eth_protocol_expected_reg_i_23_n_3,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_eth_protocol_expected_reg_i_23_O_UNCONNECTED(3 downto 0),
      S(3) => eth_protocol_expected_i_31_n_0,
      S(2) => eth_protocol_expected_i_32_n_0,
      S(1) => eth_protocol_expected_i_33_n_0,
      S(0) => eth_protocol_expected_i_34_n_0
    );
eth_protocol_expected_reg_i_30: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => eth_protocol_expected_reg_i_30_n_0,
      CO(2) => eth_protocol_expected_reg_i_30_n_1,
      CO(1) => eth_protocol_expected_reg_i_30_n_2,
      CO(0) => eth_protocol_expected_reg_i_30_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_eth_protocol_expected_reg_i_30_O_UNCONNECTED(3 downto 0),
      S(3) => eth_protocol_expected_i_35_n_0,
      S(2) => eth_protocol_expected_i_36_n_0,
      S(1) => eth_protocol_expected_i_37_n_0,
      S(0) => eth_protocol_expected_i_38_n_0
    );
eth_protocol_expected_reg_i_7: unisim.vcomponents.CARRY4
     port map (
      CI => eth_protocol_expected_reg_i_12_n_0,
      CO(3) => arp_request_expected2,
      CO(2) => eth_protocol_expected_reg_i_7_n_1,
      CO(1) => eth_protocol_expected_reg_i_7_n_2,
      CO(0) => eth_protocol_expected_reg_i_7_n_3,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_eth_protocol_expected_reg_i_7_O_UNCONNECTED(3 downto 0),
      S(3) => eth_protocol_expected_i_13_n_0,
      S(2) => eth_protocol_expected_i_14_n_0,
      S(1) => eth_protocol_expected_i_15_n_0,
      S(0) => eth_protocol_expected_i_16_n_0
    );
fifo_we_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => wrt_enable_ram,
      I1 => fifo_write_enable,
      I2 => wrt_addr_ram(1),
      I3 => wrt_addr_ram(0),
      O => we_ram_reg_0
    );
\fifo_write[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => wrt_addr_ram(1),
      I1 => wrt_enable_ram,
      I2 => wrt_addr_ram(0),
      O => E(1)
    );
\fifo_write[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => wrt_addr_ram(0),
      I1 => wrt_addr_ram(1),
      I2 => wrt_enable_ram,
      O => E(2)
    );
\fifo_write[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => wrt_addr_ram(1),
      I1 => wrt_enable_ram,
      I2 => wrt_addr_ram(0),
      O => E(3)
    );
\fifo_write[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => wrt_enable_ram,
      I1 => wrt_addr_ram(0),
      I2 => wrt_addr_ram(1),
      O => E(0)
    );
\flags_offset[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => arp_request_expected,
      I1 => eth_protocol_expected,
      I2 => p_0_in,
      O => flags_offset
    );
\flags_offset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(0),
      Q => \flags_offset_reg_n_0_[0]\,
      R => flags_offset
    );
\flags_offset_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(10),
      Q => \flags_offset_reg_n_0_[10]\,
      R => flags_offset
    );
\flags_offset_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(11),
      Q => \flags_offset_reg_n_0_[11]\,
      R => flags_offset
    );
\flags_offset_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(12),
      Q => \flags_offset_reg_n_0_[12]\,
      R => flags_offset
    );
\flags_offset_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(13),
      Q => \flags_offset_reg_n_0_[13]\,
      R => flags_offset
    );
\flags_offset_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(14),
      Q => \flags_offset_reg_n_0_[14]\,
      R => flags_offset
    );
\flags_offset_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(15),
      Q => \flags_offset_reg_n_0_[15]\,
      R => flags_offset
    );
\flags_offset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(1),
      Q => \flags_offset_reg_n_0_[1]\,
      R => flags_offset
    );
\flags_offset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(2),
      Q => \flags_offset_reg_n_0_[2]\,
      R => flags_offset
    );
\flags_offset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(3),
      Q => \flags_offset_reg_n_0_[3]\,
      R => flags_offset
    );
\flags_offset_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(4),
      Q => \flags_offset_reg_n_0_[4]\,
      R => flags_offset
    );
\flags_offset_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(5),
      Q => \flags_offset_reg_n_0_[5]\,
      R => flags_offset
    );
\flags_offset_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(6),
      Q => \flags_offset_reg_n_0_[6]\,
      R => flags_offset
    );
\flags_offset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(7),
      Q => \flags_offset_reg_n_0_[7]\,
      R => flags_offset
    );
\flags_offset_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(8),
      Q => \flags_offset_reg_n_0_[8]\,
      R => flags_offset
    );
\flags_offset_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes03(9),
      Q => \flags_offset_reg_n_0_[9]\,
      R => flags_offset
    );
\identification[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => arp_request_expected,
      I1 => eth_protocol_expected,
      I2 => \byte_read_done_reg_n_0_[2]\,
      O => \identification[15]_i_1_n_0\
    );
\identification[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_protocol_expected,
      I1 => arp_request_expected,
      O => identification
    );
\identification_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(0),
      Q => \identification_reg_n_0_[0]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(10),
      Q => \identification_reg_n_0_[10]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(11),
      Q => \identification_reg_n_0_[11]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(12),
      Q => \identification_reg_n_0_[12]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(13),
      Q => \identification_reg_n_0_[13]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(14),
      Q => \identification_reg_n_0_[14]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(15),
      Q => \identification_reg_n_0_[15]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(1),
      Q => \identification_reg_n_0_[1]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(2),
      Q => \identification_reg_n_0_[2]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(3),
      Q => \identification_reg_n_0_[3]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(4),
      Q => \identification_reg_n_0_[4]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(5),
      Q => \identification_reg_n_0_[5]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(6),
      Q => \identification_reg_n_0_[6]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(7),
      Q => \identification_reg_n_0_[7]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(8),
      Q => \identification_reg_n_0_[8]\,
      R => \identification[15]_i_1_n_0\
    );
\identification_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => identification,
      D => bytes02(9),
      Q => \identification_reg_n_0_[9]\,
      R => \identification[15]_i_1_n_0\
    );
ip_extra_options_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000F80000000000"
    )
        port map (
      I0 => \ip_header_length_reg_n_0_[1]\,
      I1 => \ip_header_length_reg_n_0_[2]\,
      I2 => \ip_header_length_reg_n_0_[3]\,
      I3 => eth_protocol_expected,
      I4 => arp_request_expected,
      I5 => \byte_read_done_reg_n_0_[0]\,
      O => ip_extra_options_i_1_n_0
    );
ip_extra_options_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => ip_extra_options_i_1_n_0,
      Q => ip_extra_options,
      R => '0'
    );
\ip_hcs_calc[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => ip_hcs_calc,
      I1 => ip_hcs_done,
      O => \ip_hcs_calc[15]_i_1_n_0\
    );
\ip_hcs_calc_extra[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFE000000000000"
    )
        port map (
      I0 => \ip_hcs_calc_extra[0]_i_3_n_0\,
      I1 => \ip_header_options_reg_n_0_[1]\,
      I2 => \ip_header_options_reg_n_0_[4]\,
      I3 => \ip_header_options_reg_n_0_[2]\,
      I4 => \sip[0]_i_1_n_0\,
      I5 => edge_count_header1,
      O => ip_hcs_calc_extra
    );
\ip_hcs_calc_extra[0]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7800"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[1]\,
      I2 => ip_hcs_calc_extra_reg(1),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[0]_i_10_n_0\
    );
\ip_hcs_calc_extra[0]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7800"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[0]\,
      I2 => ip_hcs_calc_extra_reg(0),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[0]_i_11_n_0\
    );
\ip_hcs_calc_extra[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFD"
    )
        port map (
      I0 => ip_extra_options,
      I1 => \ip_header_options_reg_n_0_[6]\,
      I2 => \ip_header_options_reg_n_0_[3]\,
      I3 => \ip_header_options_reg_n_0_[5]\,
      I4 => \ip_header_options_reg_n_0_[0]\,
      I5 => \ip_header_options_reg_n_0_[7]\,
      O => \ip_hcs_calc_extra[0]_i_3_n_0\
    );
\ip_hcs_calc_extra[0]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[3]\,
      I1 => ip_extra_options,
      I2 => edge_count_header_reg_n_0,
      O => \ip_hcs_calc_extra[0]_i_4_n_0\
    );
\ip_hcs_calc_extra[0]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[2]\,
      I1 => ip_extra_options,
      I2 => edge_count_header_reg_n_0,
      O => \ip_hcs_calc_extra[0]_i_5_n_0\
    );
\ip_hcs_calc_extra[0]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[1]\,
      I1 => ip_extra_options,
      I2 => edge_count_header_reg_n_0,
      O => \ip_hcs_calc_extra[0]_i_6_n_0\
    );
\ip_hcs_calc_extra[0]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[0]\,
      I1 => ip_extra_options,
      I2 => edge_count_header_reg_n_0,
      O => \ip_hcs_calc_extra[0]_i_7_n_0\
    );
\ip_hcs_calc_extra[0]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7800"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[3]\,
      I2 => ip_hcs_calc_extra_reg(3),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[0]_i_8_n_0\
    );
\ip_hcs_calc_extra[0]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7800"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[2]\,
      I2 => ip_hcs_calc_extra_reg(2),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[0]_i_9_n_0\
    );
\ip_hcs_calc_extra[12]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[7]\,
      I1 => edge_count_header_reg_n_0,
      I2 => ip_extra_options,
      O => \ip_hcs_calc_extra[12]_i_2_n_0\
    );
\ip_hcs_calc_extra[12]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[6]\,
      I1 => edge_count_header_reg_n_0,
      I2 => ip_extra_options,
      O => \ip_hcs_calc_extra[12]_i_3_n_0\
    );
\ip_hcs_calc_extra[12]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[5]\,
      I1 => edge_count_header_reg_n_0,
      I2 => ip_extra_options,
      O => \ip_hcs_calc_extra[12]_i_4_n_0\
    );
\ip_hcs_calc_extra[12]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[4]\,
      I1 => edge_count_header_reg_n_0,
      I2 => ip_extra_options,
      O => \ip_hcs_calc_extra[12]_i_5_n_0\
    );
\ip_hcs_calc_extra[12]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B400"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[7]\,
      I2 => ip_hcs_calc_extra_reg(15),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[12]_i_6_n_0\
    );
\ip_hcs_calc_extra[12]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B400"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[6]\,
      I2 => ip_hcs_calc_extra_reg(14),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[12]_i_7_n_0\
    );
\ip_hcs_calc_extra[12]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B400"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[5]\,
      I2 => ip_hcs_calc_extra_reg(13),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[12]_i_8_n_0\
    );
\ip_hcs_calc_extra[12]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B400"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[4]\,
      I2 => ip_hcs_calc_extra_reg(12),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[12]_i_9_n_0\
    );
\ip_hcs_calc_extra[16]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_extra_options,
      I1 => ip_hcs_calc_extra_reg(19),
      O => \ip_hcs_calc_extra[16]_i_2_n_0\
    );
\ip_hcs_calc_extra[16]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_extra_options,
      I1 => ip_hcs_calc_extra_reg(18),
      O => \ip_hcs_calc_extra[16]_i_3_n_0\
    );
\ip_hcs_calc_extra[16]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_extra_options,
      I1 => ip_hcs_calc_extra_reg(17),
      O => \ip_hcs_calc_extra[16]_i_4_n_0\
    );
\ip_hcs_calc_extra[16]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_extra_options,
      I1 => ip_hcs_calc_extra_reg(16),
      O => \ip_hcs_calc_extra[16]_i_5_n_0\
    );
\ip_hcs_calc_extra[20]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_extra_options,
      I1 => ip_hcs_calc_extra_reg(23),
      O => \ip_hcs_calc_extra[20]_i_2_n_0\
    );
\ip_hcs_calc_extra[20]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_extra_options,
      I1 => ip_hcs_calc_extra_reg(22),
      O => \ip_hcs_calc_extra[20]_i_3_n_0\
    );
\ip_hcs_calc_extra[20]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_extra_options,
      I1 => ip_hcs_calc_extra_reg(21),
      O => \ip_hcs_calc_extra[20]_i_4_n_0\
    );
\ip_hcs_calc_extra[20]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_extra_options,
      I1 => ip_hcs_calc_extra_reg(20),
      O => \ip_hcs_calc_extra[20]_i_5_n_0\
    );
\ip_hcs_calc_extra[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[7]\,
      I1 => ip_extra_options,
      I2 => edge_count_header_reg_n_0,
      O => \ip_hcs_calc_extra[4]_i_2_n_0\
    );
\ip_hcs_calc_extra[4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[6]\,
      I1 => ip_extra_options,
      I2 => edge_count_header_reg_n_0,
      O => \ip_hcs_calc_extra[4]_i_3_n_0\
    );
\ip_hcs_calc_extra[4]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[5]\,
      I1 => ip_extra_options,
      I2 => edge_count_header_reg_n_0,
      O => \ip_hcs_calc_extra[4]_i_4_n_0\
    );
\ip_hcs_calc_extra[4]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[4]\,
      I1 => ip_extra_options,
      I2 => edge_count_header_reg_n_0,
      O => \ip_hcs_calc_extra[4]_i_5_n_0\
    );
\ip_hcs_calc_extra[4]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7800"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[7]\,
      I2 => ip_hcs_calc_extra_reg(7),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[4]_i_6_n_0\
    );
\ip_hcs_calc_extra[4]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7800"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[6]\,
      I2 => ip_hcs_calc_extra_reg(6),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[4]_i_7_n_0\
    );
\ip_hcs_calc_extra[4]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7800"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[5]\,
      I2 => ip_hcs_calc_extra_reg(5),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[4]_i_8_n_0\
    );
\ip_hcs_calc_extra[4]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7800"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[4]\,
      I2 => ip_hcs_calc_extra_reg(4),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[4]_i_9_n_0\
    );
\ip_hcs_calc_extra[8]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[3]\,
      I1 => edge_count_header_reg_n_0,
      I2 => ip_extra_options,
      O => \ip_hcs_calc_extra[8]_i_2_n_0\
    );
\ip_hcs_calc_extra[8]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[2]\,
      I1 => edge_count_header_reg_n_0,
      I2 => ip_extra_options,
      O => \ip_hcs_calc_extra[8]_i_3_n_0\
    );
\ip_hcs_calc_extra[8]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[1]\,
      I1 => edge_count_header_reg_n_0,
      I2 => ip_extra_options,
      O => \ip_hcs_calc_extra[8]_i_4_n_0\
    );
\ip_hcs_calc_extra[8]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \ip_header_options_reg_n_0_[0]\,
      I1 => edge_count_header_reg_n_0,
      I2 => ip_extra_options,
      O => \ip_hcs_calc_extra[8]_i_5_n_0\
    );
\ip_hcs_calc_extra[8]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B400"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[3]\,
      I2 => ip_hcs_calc_extra_reg(11),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[8]_i_6_n_0\
    );
\ip_hcs_calc_extra[8]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B400"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[2]\,
      I2 => ip_hcs_calc_extra_reg(10),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[8]_i_7_n_0\
    );
\ip_hcs_calc_extra[8]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B400"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[1]\,
      I2 => ip_hcs_calc_extra_reg(9),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[8]_i_8_n_0\
    );
\ip_hcs_calc_extra[8]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B400"
    )
        port map (
      I0 => edge_count_header_reg_n_0,
      I1 => \ip_header_options_reg_n_0_[0]\,
      I2 => ip_hcs_calc_extra_reg(8),
      I3 => ip_extra_options,
      O => \ip_hcs_calc_extra[8]_i_9_n_0\
    );
\ip_hcs_calc_extra_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[0]_i_2_n_7\,
      Q => ip_hcs_calc_extra_reg(0),
      R => '0'
    );
\ip_hcs_calc_extra_reg[0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \ip_hcs_calc_extra_reg[0]_i_2_n_0\,
      CO(2) => \ip_hcs_calc_extra_reg[0]_i_2_n_1\,
      CO(1) => \ip_hcs_calc_extra_reg[0]_i_2_n_2\,
      CO(0) => \ip_hcs_calc_extra_reg[0]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_extra[0]_i_4_n_0\,
      DI(2) => \ip_hcs_calc_extra[0]_i_5_n_0\,
      DI(1) => \ip_hcs_calc_extra[0]_i_6_n_0\,
      DI(0) => \ip_hcs_calc_extra[0]_i_7_n_0\,
      O(3) => \ip_hcs_calc_extra_reg[0]_i_2_n_4\,
      O(2) => \ip_hcs_calc_extra_reg[0]_i_2_n_5\,
      O(1) => \ip_hcs_calc_extra_reg[0]_i_2_n_6\,
      O(0) => \ip_hcs_calc_extra_reg[0]_i_2_n_7\,
      S(3) => \ip_hcs_calc_extra[0]_i_8_n_0\,
      S(2) => \ip_hcs_calc_extra[0]_i_9_n_0\,
      S(1) => \ip_hcs_calc_extra[0]_i_10_n_0\,
      S(0) => \ip_hcs_calc_extra[0]_i_11_n_0\
    );
\ip_hcs_calc_extra_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[8]_i_1_n_5\,
      Q => ip_hcs_calc_extra_reg(10),
      R => '0'
    );
\ip_hcs_calc_extra_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[8]_i_1_n_4\,
      Q => ip_hcs_calc_extra_reg(11),
      R => '0'
    );
\ip_hcs_calc_extra_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[12]_i_1_n_7\,
      Q => ip_hcs_calc_extra_reg(12),
      R => '0'
    );
\ip_hcs_calc_extra_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_extra_reg[8]_i_1_n_0\,
      CO(3) => \ip_hcs_calc_extra_reg[12]_i_1_n_0\,
      CO(2) => \ip_hcs_calc_extra_reg[12]_i_1_n_1\,
      CO(1) => \ip_hcs_calc_extra_reg[12]_i_1_n_2\,
      CO(0) => \ip_hcs_calc_extra_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_extra[12]_i_2_n_0\,
      DI(2) => \ip_hcs_calc_extra[12]_i_3_n_0\,
      DI(1) => \ip_hcs_calc_extra[12]_i_4_n_0\,
      DI(0) => \ip_hcs_calc_extra[12]_i_5_n_0\,
      O(3) => \ip_hcs_calc_extra_reg[12]_i_1_n_4\,
      O(2) => \ip_hcs_calc_extra_reg[12]_i_1_n_5\,
      O(1) => \ip_hcs_calc_extra_reg[12]_i_1_n_6\,
      O(0) => \ip_hcs_calc_extra_reg[12]_i_1_n_7\,
      S(3) => \ip_hcs_calc_extra[12]_i_6_n_0\,
      S(2) => \ip_hcs_calc_extra[12]_i_7_n_0\,
      S(1) => \ip_hcs_calc_extra[12]_i_8_n_0\,
      S(0) => \ip_hcs_calc_extra[12]_i_9_n_0\
    );
\ip_hcs_calc_extra_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[12]_i_1_n_6\,
      Q => ip_hcs_calc_extra_reg(13),
      R => '0'
    );
\ip_hcs_calc_extra_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[12]_i_1_n_5\,
      Q => ip_hcs_calc_extra_reg(14),
      R => '0'
    );
\ip_hcs_calc_extra_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[12]_i_1_n_4\,
      Q => ip_hcs_calc_extra_reg(15),
      R => '0'
    );
\ip_hcs_calc_extra_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[16]_i_1_n_7\,
      Q => ip_hcs_calc_extra_reg(16),
      R => '0'
    );
\ip_hcs_calc_extra_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_extra_reg[12]_i_1_n_0\,
      CO(3) => \ip_hcs_calc_extra_reg[16]_i_1_n_0\,
      CO(2) => \ip_hcs_calc_extra_reg[16]_i_1_n_1\,
      CO(1) => \ip_hcs_calc_extra_reg[16]_i_1_n_2\,
      CO(0) => \ip_hcs_calc_extra_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \ip_hcs_calc_extra_reg[16]_i_1_n_4\,
      O(2) => \ip_hcs_calc_extra_reg[16]_i_1_n_5\,
      O(1) => \ip_hcs_calc_extra_reg[16]_i_1_n_6\,
      O(0) => \ip_hcs_calc_extra_reg[16]_i_1_n_7\,
      S(3) => \ip_hcs_calc_extra[16]_i_2_n_0\,
      S(2) => \ip_hcs_calc_extra[16]_i_3_n_0\,
      S(1) => \ip_hcs_calc_extra[16]_i_4_n_0\,
      S(0) => \ip_hcs_calc_extra[16]_i_5_n_0\
    );
\ip_hcs_calc_extra_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[16]_i_1_n_6\,
      Q => ip_hcs_calc_extra_reg(17),
      R => '0'
    );
\ip_hcs_calc_extra_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[16]_i_1_n_5\,
      Q => ip_hcs_calc_extra_reg(18),
      R => '0'
    );
\ip_hcs_calc_extra_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[16]_i_1_n_4\,
      Q => ip_hcs_calc_extra_reg(19),
      R => '0'
    );
\ip_hcs_calc_extra_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[0]_i_2_n_6\,
      Q => ip_hcs_calc_extra_reg(1),
      R => '0'
    );
\ip_hcs_calc_extra_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[20]_i_1_n_7\,
      Q => ip_hcs_calc_extra_reg(20),
      R => '0'
    );
\ip_hcs_calc_extra_reg[20]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_extra_reg[16]_i_1_n_0\,
      CO(3) => \NLW_ip_hcs_calc_extra_reg[20]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \ip_hcs_calc_extra_reg[20]_i_1_n_1\,
      CO(1) => \ip_hcs_calc_extra_reg[20]_i_1_n_2\,
      CO(0) => \ip_hcs_calc_extra_reg[20]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \ip_hcs_calc_extra_reg[20]_i_1_n_4\,
      O(2) => \ip_hcs_calc_extra_reg[20]_i_1_n_5\,
      O(1) => \ip_hcs_calc_extra_reg[20]_i_1_n_6\,
      O(0) => \ip_hcs_calc_extra_reg[20]_i_1_n_7\,
      S(3) => \ip_hcs_calc_extra[20]_i_2_n_0\,
      S(2) => \ip_hcs_calc_extra[20]_i_3_n_0\,
      S(1) => \ip_hcs_calc_extra[20]_i_4_n_0\,
      S(0) => \ip_hcs_calc_extra[20]_i_5_n_0\
    );
\ip_hcs_calc_extra_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[20]_i_1_n_6\,
      Q => ip_hcs_calc_extra_reg(21),
      R => '0'
    );
\ip_hcs_calc_extra_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[20]_i_1_n_5\,
      Q => ip_hcs_calc_extra_reg(22),
      R => '0'
    );
\ip_hcs_calc_extra_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[20]_i_1_n_4\,
      Q => ip_hcs_calc_extra_reg(23),
      R => '0'
    );
\ip_hcs_calc_extra_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[0]_i_2_n_5\,
      Q => ip_hcs_calc_extra_reg(2),
      R => '0'
    );
\ip_hcs_calc_extra_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[0]_i_2_n_4\,
      Q => ip_hcs_calc_extra_reg(3),
      R => '0'
    );
\ip_hcs_calc_extra_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[4]_i_1_n_7\,
      Q => ip_hcs_calc_extra_reg(4),
      R => '0'
    );
\ip_hcs_calc_extra_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_extra_reg[0]_i_2_n_0\,
      CO(3) => \ip_hcs_calc_extra_reg[4]_i_1_n_0\,
      CO(2) => \ip_hcs_calc_extra_reg[4]_i_1_n_1\,
      CO(1) => \ip_hcs_calc_extra_reg[4]_i_1_n_2\,
      CO(0) => \ip_hcs_calc_extra_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_extra[4]_i_2_n_0\,
      DI(2) => \ip_hcs_calc_extra[4]_i_3_n_0\,
      DI(1) => \ip_hcs_calc_extra[4]_i_4_n_0\,
      DI(0) => \ip_hcs_calc_extra[4]_i_5_n_0\,
      O(3) => \ip_hcs_calc_extra_reg[4]_i_1_n_4\,
      O(2) => \ip_hcs_calc_extra_reg[4]_i_1_n_5\,
      O(1) => \ip_hcs_calc_extra_reg[4]_i_1_n_6\,
      O(0) => \ip_hcs_calc_extra_reg[4]_i_1_n_7\,
      S(3) => \ip_hcs_calc_extra[4]_i_6_n_0\,
      S(2) => \ip_hcs_calc_extra[4]_i_7_n_0\,
      S(1) => \ip_hcs_calc_extra[4]_i_8_n_0\,
      S(0) => \ip_hcs_calc_extra[4]_i_9_n_0\
    );
\ip_hcs_calc_extra_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[4]_i_1_n_6\,
      Q => ip_hcs_calc_extra_reg(5),
      R => '0'
    );
\ip_hcs_calc_extra_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[4]_i_1_n_5\,
      Q => ip_hcs_calc_extra_reg(6),
      R => '0'
    );
\ip_hcs_calc_extra_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[4]_i_1_n_4\,
      Q => ip_hcs_calc_extra_reg(7),
      R => '0'
    );
\ip_hcs_calc_extra_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[8]_i_1_n_7\,
      Q => ip_hcs_calc_extra_reg(8),
      R => '0'
    );
\ip_hcs_calc_extra_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_extra_reg[4]_i_1_n_0\,
      CO(3) => \ip_hcs_calc_extra_reg[8]_i_1_n_0\,
      CO(2) => \ip_hcs_calc_extra_reg[8]_i_1_n_1\,
      CO(1) => \ip_hcs_calc_extra_reg[8]_i_1_n_2\,
      CO(0) => \ip_hcs_calc_extra_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_extra[8]_i_2_n_0\,
      DI(2) => \ip_hcs_calc_extra[8]_i_3_n_0\,
      DI(1) => \ip_hcs_calc_extra[8]_i_4_n_0\,
      DI(0) => \ip_hcs_calc_extra[8]_i_5_n_0\,
      O(3) => \ip_hcs_calc_extra_reg[8]_i_1_n_4\,
      O(2) => \ip_hcs_calc_extra_reg[8]_i_1_n_5\,
      O(1) => \ip_hcs_calc_extra_reg[8]_i_1_n_6\,
      O(0) => \ip_hcs_calc_extra_reg[8]_i_1_n_7\,
      S(3) => \ip_hcs_calc_extra[8]_i_6_n_0\,
      S(2) => \ip_hcs_calc_extra[8]_i_7_n_0\,
      S(1) => \ip_hcs_calc_extra[8]_i_8_n_0\,
      S(0) => \ip_hcs_calc_extra[8]_i_9_n_0\
    );
\ip_hcs_calc_extra_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => ip_hcs_calc_extra,
      D => \ip_hcs_calc_extra_reg[8]_i_1_n_6\,
      Q => ip_hcs_calc_extra_reg(9),
      R => '0'
    );
\ip_hcs_calc_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(0),
      Q => \ip_hcs_calc__0\(0),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[10]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(10),
      Q => \ip_hcs_calc__0\(10),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[11]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(11),
      Q => \ip_hcs_calc__0\(11),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[12]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(12),
      Q => \ip_hcs_calc__0\(12),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[13]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(13),
      Q => \ip_hcs_calc__0\(13),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[14]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(14),
      Q => \ip_hcs_calc__0\(14),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[15]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(15),
      Q => \ip_hcs_calc__0\(15),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(1),
      Q => \ip_hcs_calc__0\(1),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(2),
      Q => \ip_hcs_calc__0\(2),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(3),
      Q => \ip_hcs_calc__0\(3),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[4]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(4),
      Q => \ip_hcs_calc__0\(4),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[5]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(5),
      Q => \ip_hcs_calc__0\(5),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[6]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(6),
      Q => \ip_hcs_calc__0\(6),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(7),
      Q => \ip_hcs_calc__0\(7),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[8]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(8),
      Q => \ip_hcs_calc__0\(8),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_reg[9]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc[15]_i_1_n_0\,
      D => \ip_hcs_calc_temp2__0\(9),
      Q => \ip_hcs_calc__0\(9),
      S => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1[11]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[15]_i_15_n_5\,
      I1 => \ip_hcs_calc_temp1_reg[15]_i_14_n_5\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_13_n_5\,
      O => \ip_hcs_calc_temp1[11]_i_10_n_0\
    );
\ip_hcs_calc_temp1[11]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[15]_i_15_n_6\,
      I1 => \ip_hcs_calc_temp1_reg[15]_i_14_n_6\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_13_n_6\,
      O => \ip_hcs_calc_temp1[11]_i_11_n_0\
    );
\ip_hcs_calc_temp1[11]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[15]_i_15_n_7\,
      I1 => \ip_hcs_calc_temp1_reg[15]_i_14_n_7\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_13_n_7\,
      O => \ip_hcs_calc_temp1[11]_i_15_n_0\
    );
\ip_hcs_calc_temp1[11]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[11]_i_14_n_4\,
      I1 => \ip_hcs_calc_temp1_reg[11]_i_13_n_4\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_12_n_4\,
      O => \ip_hcs_calc_temp1[11]_i_17_n_0\
    );
\ip_hcs_calc_temp1[11]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[15]_i_13_n_5\,
      I1 => \ip_hcs_calc_temp1_reg[15]_i_14_n_5\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_15_n_5\,
      O => \ip_hcs_calc_temp1[11]_i_18_n_0\
    );
\ip_hcs_calc_temp1[11]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[15]_i_13_n_6\,
      I1 => \ip_hcs_calc_temp1_reg[15]_i_14_n_6\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_15_n_6\,
      O => \ip_hcs_calc_temp1[11]_i_19_n_0\
    );
\ip_hcs_calc_temp1[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[15]_i_13_n_6\,
      I1 => \ip_hcs_calc_temp1_reg[15]_i_14_n_6\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_15_n_6\,
      I3 => \ip_hcs_calc_temp1_reg[15]_i_16_n_5\,
      I4 => \ip_hcs_calc_temp1[11]_i_10_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_2_n_0\
    );
\ip_hcs_calc_temp1[11]_i_20\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[15]_i_13_n_7\,
      I1 => \ip_hcs_calc_temp1_reg[15]_i_14_n_7\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_15_n_7\,
      O => \ip_hcs_calc_temp1[11]_i_20_n_0\
    );
\ip_hcs_calc_temp1[11]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[11]_i_12_n_4\,
      I1 => \ip_hcs_calc_temp1_reg[11]_i_13_n_4\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_14_n_4\,
      O => \ip_hcs_calc_temp1[11]_i_21_n_0\
    );
\ip_hcs_calc_temp1[11]_i_22\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \bytes00_reg_n_0_[6]\,
      I1 => \identification_reg_n_0_[6]\,
      I2 => ip_total_length(6),
      O => \ip_hcs_calc_temp1[11]_i_22_n_0\
    );
\ip_hcs_calc_temp1[11]_i_23\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \bytes00_reg_n_0_[5]\,
      I1 => \identification_reg_n_0_[5]\,
      I2 => ip_total_length(5),
      O => \ip_hcs_calc_temp1[11]_i_23_n_0\
    );
\ip_hcs_calc_temp1[11]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \bytes00_reg_n_0_[4]\,
      I1 => \identification_reg_n_0_[4]\,
      I2 => ip_total_length(4),
      O => \ip_hcs_calc_temp1[11]_i_24_n_0\
    );
\ip_hcs_calc_temp1[11]_i_25\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \bytes00_reg_n_0_[3]\,
      I1 => \identification_reg_n_0_[3]\,
      I2 => ip_total_length(3),
      O => \ip_hcs_calc_temp1[11]_i_25_n_0\
    );
\ip_hcs_calc_temp1[11]_i_26\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \bytes00_reg_n_0_[7]\,
      I1 => \identification_reg_n_0_[7]\,
      I2 => ip_total_length(7),
      I3 => \ip_hcs_calc_temp1[11]_i_22_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_26_n_0\
    );
\ip_hcs_calc_temp1[11]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \bytes00_reg_n_0_[6]\,
      I1 => \identification_reg_n_0_[6]\,
      I2 => ip_total_length(6),
      I3 => \ip_hcs_calc_temp1[11]_i_23_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_27_n_0\
    );
\ip_hcs_calc_temp1[11]_i_28\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \bytes00_reg_n_0_[5]\,
      I1 => \identification_reg_n_0_[5]\,
      I2 => ip_total_length(5),
      I3 => \ip_hcs_calc_temp1[11]_i_24_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_28_n_0\
    );
\ip_hcs_calc_temp1[11]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \bytes00_reg_n_0_[4]\,
      I1 => \identification_reg_n_0_[4]\,
      I2 => ip_total_length(4),
      I3 => \ip_hcs_calc_temp1[11]_i_25_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_29_n_0\
    );
\ip_hcs_calc_temp1[11]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[15]_i_13_n_7\,
      I1 => \ip_hcs_calc_temp1_reg[15]_i_14_n_7\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_15_n_7\,
      I3 => \ip_hcs_calc_temp1_reg[15]_i_16_n_6\,
      I4 => \ip_hcs_calc_temp1[11]_i_11_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_3_n_0\
    );
\ip_hcs_calc_temp1[11]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(6),
      I1 => bytes08(6),
      I2 => bytes07(6),
      O => \ip_hcs_calc_temp1[11]_i_30_n_0\
    );
\ip_hcs_calc_temp1[11]_i_31\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(5),
      I1 => bytes08(5),
      I2 => bytes07(5),
      O => \ip_hcs_calc_temp1[11]_i_31_n_0\
    );
\ip_hcs_calc_temp1[11]_i_32\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(4),
      I1 => bytes08(4),
      I2 => bytes07(4),
      O => \ip_hcs_calc_temp1[11]_i_32_n_0\
    );
\ip_hcs_calc_temp1[11]_i_33\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(3),
      I1 => bytes08(3),
      I2 => bytes07(3),
      O => \ip_hcs_calc_temp1[11]_i_33_n_0\
    );
\ip_hcs_calc_temp1[11]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes06(7),
      I1 => bytes08(7),
      I2 => bytes07(7),
      I3 => \ip_hcs_calc_temp1[11]_i_30_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_34_n_0\
    );
\ip_hcs_calc_temp1[11]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes06(6),
      I1 => bytes08(6),
      I2 => bytes07(6),
      I3 => \ip_hcs_calc_temp1[11]_i_31_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_35_n_0\
    );
\ip_hcs_calc_temp1[11]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes06(5),
      I1 => bytes08(5),
      I2 => bytes07(5),
      I3 => \ip_hcs_calc_temp1[11]_i_32_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_36_n_0\
    );
\ip_hcs_calc_temp1[11]_i_37\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes06(4),
      I1 => bytes08(4),
      I2 => bytes07(4),
      I3 => \ip_hcs_calc_temp1[11]_i_33_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_37_n_0\
    );
\ip_hcs_calc_temp1[11]_i_38\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[6]\,
      I1 => ip_header_checksum(6),
      I2 => bytes04(6),
      O => \ip_hcs_calc_temp1[11]_i_38_n_0\
    );
\ip_hcs_calc_temp1[11]_i_39\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[5]\,
      I1 => ip_header_checksum(5),
      I2 => bytes04(5),
      O => \ip_hcs_calc_temp1[11]_i_39_n_0\
    );
\ip_hcs_calc_temp1[11]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[11]_i_12_n_4\,
      I1 => \ip_hcs_calc_temp1_reg[11]_i_13_n_4\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_14_n_4\,
      I3 => \ip_hcs_calc_temp1_reg[15]_i_16_n_7\,
      I4 => \ip_hcs_calc_temp1[11]_i_15_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_4_n_0\
    );
\ip_hcs_calc_temp1[11]_i_40\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[4]\,
      I1 => ip_header_checksum(4),
      I2 => bytes04(4),
      O => \ip_hcs_calc_temp1[11]_i_40_n_0\
    );
\ip_hcs_calc_temp1[11]_i_41\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[3]\,
      I1 => ip_header_checksum(3),
      I2 => bytes04(3),
      O => \ip_hcs_calc_temp1[11]_i_41_n_0\
    );
\ip_hcs_calc_temp1[11]_i_42\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[7]\,
      I1 => ip_header_checksum(7),
      I2 => bytes04(7),
      I3 => \ip_hcs_calc_temp1[11]_i_38_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_42_n_0\
    );
\ip_hcs_calc_temp1[11]_i_43\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[6]\,
      I1 => ip_header_checksum(6),
      I2 => bytes04(6),
      I3 => \ip_hcs_calc_temp1[11]_i_39_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_43_n_0\
    );
\ip_hcs_calc_temp1[11]_i_44\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[5]\,
      I1 => ip_header_checksum(5),
      I2 => bytes04(5),
      I3 => \ip_hcs_calc_temp1[11]_i_40_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_44_n_0\
    );
\ip_hcs_calc_temp1[11]_i_45\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[4]\,
      I1 => ip_header_checksum(4),
      I2 => bytes04(4),
      I3 => \ip_hcs_calc_temp1[11]_i_41_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_45_n_0\
    );
\ip_hcs_calc_temp1[11]_i_46\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(6),
      I1 => ip_hcs_calc_extra_reg(6),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[6]\,
      O => \ip_hcs_calc_temp1[11]_i_46_n_0\
    );
\ip_hcs_calc_temp1[11]_i_47\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(5),
      I1 => ip_hcs_calc_extra_reg(5),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[5]\,
      O => \ip_hcs_calc_temp1[11]_i_47_n_0\
    );
\ip_hcs_calc_temp1[11]_i_48\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(4),
      I1 => ip_hcs_calc_extra_reg(4),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[4]\,
      O => \ip_hcs_calc_temp1[11]_i_48_n_0\
    );
\ip_hcs_calc_temp1[11]_i_49\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(3),
      I1 => ip_hcs_calc_extra_reg(3),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[3]\,
      O => \ip_hcs_calc_temp1[11]_i_49_n_0\
    );
\ip_hcs_calc_temp1[11]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[11]_i_12_n_5\,
      I1 => \ip_hcs_calc_temp1_reg[11]_i_13_n_5\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_14_n_5\,
      I3 => \ip_hcs_calc_temp1_reg[11]_i_16_n_4\,
      I4 => \ip_hcs_calc_temp1[11]_i_17_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_5_n_0\
    );
\ip_hcs_calc_temp1[11]_i_50\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes09(7),
      I1 => ip_hcs_calc_extra_reg(7),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[7]\,
      I3 => \ip_hcs_calc_temp1[11]_i_46_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_50_n_0\
    );
\ip_hcs_calc_temp1[11]_i_51\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes09(6),
      I1 => ip_hcs_calc_extra_reg(6),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[6]\,
      I3 => \ip_hcs_calc_temp1[11]_i_47_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_51_n_0\
    );
\ip_hcs_calc_temp1[11]_i_52\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes09(5),
      I1 => ip_hcs_calc_extra_reg(5),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[5]\,
      I3 => \ip_hcs_calc_temp1[11]_i_48_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_52_n_0\
    );
\ip_hcs_calc_temp1[11]_i_53\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes09(4),
      I1 => ip_hcs_calc_extra_reg(4),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[4]\,
      I3 => \ip_hcs_calc_temp1[11]_i_49_n_0\,
      O => \ip_hcs_calc_temp1[11]_i_53_n_0\
    );
\ip_hcs_calc_temp1[11]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[11]_i_2_n_0\,
      I1 => \ip_hcs_calc_temp1[11]_i_18_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_15_n_4\,
      I3 => \ip_hcs_calc_temp1_reg[15]_i_14_n_4\,
      I4 => \ip_hcs_calc_temp1_reg[15]_i_13_n_4\,
      I5 => \ip_hcs_calc_temp1_reg[15]_i_16_n_4\,
      O => \ip_hcs_calc_temp1[11]_i_6_n_0\
    );
\ip_hcs_calc_temp1[11]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[11]_i_3_n_0\,
      I1 => \ip_hcs_calc_temp1[11]_i_19_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_15_n_5\,
      I3 => \ip_hcs_calc_temp1_reg[15]_i_14_n_5\,
      I4 => \ip_hcs_calc_temp1_reg[15]_i_13_n_5\,
      I5 => \ip_hcs_calc_temp1_reg[15]_i_16_n_5\,
      O => \ip_hcs_calc_temp1[11]_i_7_n_0\
    );
\ip_hcs_calc_temp1[11]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[11]_i_4_n_0\,
      I1 => \ip_hcs_calc_temp1[11]_i_20_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_15_n_6\,
      I3 => \ip_hcs_calc_temp1_reg[15]_i_14_n_6\,
      I4 => \ip_hcs_calc_temp1_reg[15]_i_13_n_6\,
      I5 => \ip_hcs_calc_temp1_reg[15]_i_16_n_6\,
      O => \ip_hcs_calc_temp1[11]_i_8_n_0\
    );
\ip_hcs_calc_temp1[11]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[11]_i_5_n_0\,
      I1 => \ip_hcs_calc_temp1[11]_i_21_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_15_n_7\,
      I3 => \ip_hcs_calc_temp1_reg[15]_i_14_n_7\,
      I4 => \ip_hcs_calc_temp1_reg[15]_i_13_n_7\,
      I5 => \ip_hcs_calc_temp1_reg[15]_i_16_n_7\,
      O => \ip_hcs_calc_temp1[11]_i_9_n_0\
    );
\ip_hcs_calc_temp1[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_16_n_5\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_15_n_5\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_14_n_5\,
      O => \ip_hcs_calc_temp1[15]_i_10_n_0\
    );
\ip_hcs_calc_temp1[15]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_16_n_6\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_15_n_6\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_14_n_6\,
      O => \ip_hcs_calc_temp1[15]_i_11_n_0\
    );
\ip_hcs_calc_temp1[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_16_n_7\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_15_n_7\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_14_n_7\,
      O => \ip_hcs_calc_temp1[15]_i_12_n_0\
    );
\ip_hcs_calc_temp1[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[15]_i_15_n_4\,
      I1 => \ip_hcs_calc_temp1_reg[15]_i_14_n_4\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_13_n_4\,
      O => \ip_hcs_calc_temp1[15]_i_17_n_0\
    );
\ip_hcs_calc_temp1[15]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_14_n_5\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_15_n_5\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_16_n_5\,
      O => \ip_hcs_calc_temp1[15]_i_18_n_0\
    );
\ip_hcs_calc_temp1[15]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_14_n_7\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_15_n_7\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_16_n_7\,
      O => \ip_hcs_calc_temp1[15]_i_19_n_0\
    );
\ip_hcs_calc_temp1[15]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEE8E888"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_18_n_5\,
      I1 => \ip_hcs_calc_temp1[15]_i_10_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_14_n_6\,
      I3 => \ip_hcs_calc_temp1_reg[19]_i_15_n_6\,
      I4 => \ip_hcs_calc_temp1_reg[19]_i_16_n_6\,
      O => \ip_hcs_calc_temp1[15]_i_2_n_0\
    );
\ip_hcs_calc_temp1[15]_i_20\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => data_counter_max2(2),
      I1 => \identification_reg_n_0_[10]\,
      I2 => ip_total_length(10),
      O => \ip_hcs_calc_temp1[15]_i_20_n_0\
    );
\ip_hcs_calc_temp1[15]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => data_counter_max2(1),
      I1 => \identification_reg_n_0_[9]\,
      I2 => ip_total_length(9),
      O => \ip_hcs_calc_temp1[15]_i_21_n_0\
    );
\ip_hcs_calc_temp1[15]_i_22\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => data_counter_max2(0),
      I1 => \identification_reg_n_0_[8]\,
      I2 => ip_total_length(8),
      O => \ip_hcs_calc_temp1[15]_i_22_n_0\
    );
\ip_hcs_calc_temp1[15]_i_23\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \bytes00_reg_n_0_[7]\,
      I1 => \identification_reg_n_0_[7]\,
      I2 => ip_total_length(7),
      O => \ip_hcs_calc_temp1[15]_i_23_n_0\
    );
\ip_hcs_calc_temp1[15]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => data_counter_max2(3),
      I1 => \identification_reg_n_0_[11]\,
      I2 => ip_total_length(11),
      I3 => \ip_hcs_calc_temp1[15]_i_20_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_24_n_0\
    );
\ip_hcs_calc_temp1[15]_i_25\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => data_counter_max2(2),
      I1 => \identification_reg_n_0_[10]\,
      I2 => ip_total_length(10),
      I3 => \ip_hcs_calc_temp1[15]_i_21_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_25_n_0\
    );
\ip_hcs_calc_temp1[15]_i_26\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => data_counter_max2(1),
      I1 => \identification_reg_n_0_[9]\,
      I2 => ip_total_length(9),
      I3 => \ip_hcs_calc_temp1[15]_i_22_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_26_n_0\
    );
\ip_hcs_calc_temp1[15]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => data_counter_max2(0),
      I1 => \identification_reg_n_0_[8]\,
      I2 => ip_total_length(8),
      I3 => \ip_hcs_calc_temp1[15]_i_23_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_27_n_0\
    );
\ip_hcs_calc_temp1[15]_i_28\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(10),
      I1 => bytes08(10),
      I2 => bytes07(10),
      O => \ip_hcs_calc_temp1[15]_i_28_n_0\
    );
\ip_hcs_calc_temp1[15]_i_29\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(9),
      I1 => bytes08(9),
      I2 => bytes07(9),
      O => \ip_hcs_calc_temp1[15]_i_29_n_0\
    );
\ip_hcs_calc_temp1[15]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_14_n_7\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_15_n_7\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_16_n_7\,
      I3 => \ip_hcs_calc_temp1_reg[19]_i_18_n_6\,
      I4 => \ip_hcs_calc_temp1[15]_i_11_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_3_n_0\
    );
\ip_hcs_calc_temp1[15]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(8),
      I1 => bytes08(8),
      I2 => bytes07(8),
      O => \ip_hcs_calc_temp1[15]_i_30_n_0\
    );
\ip_hcs_calc_temp1[15]_i_31\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(7),
      I1 => bytes08(7),
      I2 => bytes07(7),
      O => \ip_hcs_calc_temp1[15]_i_31_n_0\
    );
\ip_hcs_calc_temp1[15]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes06(11),
      I1 => bytes08(11),
      I2 => bytes07(11),
      I3 => \ip_hcs_calc_temp1[15]_i_28_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_32_n_0\
    );
\ip_hcs_calc_temp1[15]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes06(10),
      I1 => bytes08(10),
      I2 => bytes07(10),
      I3 => \ip_hcs_calc_temp1[15]_i_29_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_33_n_0\
    );
\ip_hcs_calc_temp1[15]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes06(9),
      I1 => bytes08(9),
      I2 => bytes07(9),
      I3 => \ip_hcs_calc_temp1[15]_i_30_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_34_n_0\
    );
\ip_hcs_calc_temp1[15]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes06(8),
      I1 => bytes08(8),
      I2 => bytes07(8),
      I3 => \ip_hcs_calc_temp1[15]_i_31_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_35_n_0\
    );
\ip_hcs_calc_temp1[15]_i_36\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[10]\,
      I1 => ip_header_checksum(10),
      I2 => bytes04(10),
      O => \ip_hcs_calc_temp1[15]_i_36_n_0\
    );
\ip_hcs_calc_temp1[15]_i_37\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[9]\,
      I1 => ip_header_checksum(9),
      I2 => bytes04(9),
      O => \ip_hcs_calc_temp1[15]_i_37_n_0\
    );
\ip_hcs_calc_temp1[15]_i_38\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[8]\,
      I1 => ip_header_checksum(8),
      I2 => bytes04(8),
      O => \ip_hcs_calc_temp1[15]_i_38_n_0\
    );
\ip_hcs_calc_temp1[15]_i_39\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[7]\,
      I1 => ip_header_checksum(7),
      I2 => bytes04(7),
      O => \ip_hcs_calc_temp1[15]_i_39_n_0\
    );
\ip_hcs_calc_temp1[15]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEE8E888"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_18_n_7\,
      I1 => \ip_hcs_calc_temp1[15]_i_12_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_13_n_4\,
      I3 => \ip_hcs_calc_temp1_reg[15]_i_14_n_4\,
      I4 => \ip_hcs_calc_temp1_reg[15]_i_15_n_4\,
      O => \ip_hcs_calc_temp1[15]_i_4_n_0\
    );
\ip_hcs_calc_temp1[15]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[11]\,
      I1 => ip_header_checksum(11),
      I2 => bytes04(11),
      I3 => \ip_hcs_calc_temp1[15]_i_36_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_40_n_0\
    );
\ip_hcs_calc_temp1[15]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[10]\,
      I1 => ip_header_checksum(10),
      I2 => bytes04(10),
      I3 => \ip_hcs_calc_temp1[15]_i_37_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_41_n_0\
    );
\ip_hcs_calc_temp1[15]_i_42\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[9]\,
      I1 => ip_header_checksum(9),
      I2 => bytes04(9),
      I3 => \ip_hcs_calc_temp1[15]_i_38_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_42_n_0\
    );
\ip_hcs_calc_temp1[15]_i_43\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[8]\,
      I1 => ip_header_checksum(8),
      I2 => bytes04(8),
      I3 => \ip_hcs_calc_temp1[15]_i_39_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_43_n_0\
    );
\ip_hcs_calc_temp1[15]_i_44\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(10),
      I1 => ip_hcs_calc_extra_reg(10),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[10]\,
      O => \ip_hcs_calc_temp1[15]_i_44_n_0\
    );
\ip_hcs_calc_temp1[15]_i_45\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(9),
      I1 => ip_hcs_calc_extra_reg(9),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[9]\,
      O => \ip_hcs_calc_temp1[15]_i_45_n_0\
    );
\ip_hcs_calc_temp1[15]_i_46\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(8),
      I1 => ip_hcs_calc_extra_reg(8),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[8]\,
      O => \ip_hcs_calc_temp1[15]_i_46_n_0\
    );
\ip_hcs_calc_temp1[15]_i_47\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(7),
      I1 => ip_hcs_calc_extra_reg(7),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[7]\,
      O => \ip_hcs_calc_temp1[15]_i_47_n_0\
    );
\ip_hcs_calc_temp1[15]_i_48\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes09(11),
      I1 => ip_hcs_calc_extra_reg(11),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[11]\,
      I3 => \ip_hcs_calc_temp1[15]_i_44_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_48_n_0\
    );
\ip_hcs_calc_temp1[15]_i_49\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes09(10),
      I1 => ip_hcs_calc_extra_reg(10),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[10]\,
      I3 => \ip_hcs_calc_temp1[15]_i_45_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_49_n_0\
    );
\ip_hcs_calc_temp1[15]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[15]_i_13_n_5\,
      I1 => \ip_hcs_calc_temp1_reg[15]_i_14_n_5\,
      I2 => \ip_hcs_calc_temp1_reg[15]_i_15_n_5\,
      I3 => \ip_hcs_calc_temp1_reg[15]_i_16_n_4\,
      I4 => \ip_hcs_calc_temp1[15]_i_17_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_5_n_0\
    );
\ip_hcs_calc_temp1[15]_i_50\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes09(9),
      I1 => ip_hcs_calc_extra_reg(9),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[9]\,
      I3 => \ip_hcs_calc_temp1[15]_i_46_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_50_n_0\
    );
\ip_hcs_calc_temp1[15]_i_51\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes09(8),
      I1 => ip_hcs_calc_extra_reg(8),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[8]\,
      I3 => \ip_hcs_calc_temp1[15]_i_47_n_0\,
      O => \ip_hcs_calc_temp1[15]_i_51_n_0\
    );
\ip_hcs_calc_temp1[15]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[15]_i_2_n_0\,
      I1 => \ip_hcs_calc_temp1[15]_i_18_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_16_n_4\,
      I3 => \ip_hcs_calc_temp1_reg[19]_i_15_n_4\,
      I4 => \ip_hcs_calc_temp1_reg[19]_i_14_n_4\,
      I5 => \ip_hcs_calc_temp1_reg[19]_i_18_n_4\,
      O => \ip_hcs_calc_temp1[15]_i_6_n_0\
    );
\ip_hcs_calc_temp1[15]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6969699669969696"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[15]_i_3_n_0\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_18_n_5\,
      I2 => \ip_hcs_calc_temp1[15]_i_10_n_0\,
      I3 => \ip_hcs_calc_temp1_reg[19]_i_14_n_6\,
      I4 => \ip_hcs_calc_temp1_reg[19]_i_15_n_6\,
      I5 => \ip_hcs_calc_temp1_reg[19]_i_16_n_6\,
      O => \ip_hcs_calc_temp1[15]_i_7_n_0\
    );
\ip_hcs_calc_temp1[15]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[15]_i_4_n_0\,
      I1 => \ip_hcs_calc_temp1[15]_i_19_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_16_n_6\,
      I3 => \ip_hcs_calc_temp1_reg[19]_i_15_n_6\,
      I4 => \ip_hcs_calc_temp1_reg[19]_i_14_n_6\,
      I5 => \ip_hcs_calc_temp1_reg[19]_i_18_n_6\,
      O => \ip_hcs_calc_temp1[15]_i_8_n_0\
    );
\ip_hcs_calc_temp1[15]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6969699669969696"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[15]_i_5_n_0\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_18_n_7\,
      I2 => \ip_hcs_calc_temp1[15]_i_12_n_0\,
      I3 => \ip_hcs_calc_temp1_reg[15]_i_13_n_4\,
      I4 => \ip_hcs_calc_temp1_reg[15]_i_14_n_4\,
      I5 => \ip_hcs_calc_temp1_reg[15]_i_15_n_4\,
      O => \ip_hcs_calc_temp1[15]_i_9_n_0\
    );
\ip_hcs_calc_temp1[19]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_10_n_2\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_11_n_2\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_12_n_2\,
      O => \ip_hcs_calc_temp1[19]_i_13_n_0\
    );
\ip_hcs_calc_temp1[19]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_10_n_7\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_11_n_7\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_12_n_7\,
      O => \ip_hcs_calc_temp1[19]_i_17_n_0\
    );
\ip_hcs_calc_temp1[19]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_16_n_4\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_15_n_4\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_14_n_4\,
      O => \ip_hcs_calc_temp1[19]_i_19_n_0\
    );
\ip_hcs_calc_temp1[19]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A880"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[23]_i_4_n_5\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_10_n_2\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_11_n_2\,
      I3 => \ip_hcs_calc_temp1_reg[19]_i_12_n_2\,
      O => \ip_hcs_calc_temp1[19]_i_2_n_0\
    );
\ip_hcs_calc_temp1[19]_i_20\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_12_n_7\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_11_n_7\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_10_n_7\,
      O => \ip_hcs_calc_temp1[19]_i_20_n_0\
    );
\ip_hcs_calc_temp1[19]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_14_n_4\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_15_n_4\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_16_n_4\,
      O => \ip_hcs_calc_temp1[19]_i_21_n_0\
    );
\ip_hcs_calc_temp1[19]_i_22\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[15]\,
      I1 => ip_header_checksum(15),
      I2 => bytes04(15),
      O => \ip_hcs_calc_temp1[19]_i_22_n_0\
    );
\ip_hcs_calc_temp1[19]_i_23\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(15),
      I1 => bytes08(15),
      I2 => bytes07(15),
      O => \ip_hcs_calc_temp1[19]_i_23_n_0\
    );
\ip_hcs_calc_temp1[19]_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \bytes00_reg_n_0_[15]\,
      I1 => \identification_reg_n_0_[15]\,
      I2 => ip_total_length(15),
      O => \ip_hcs_calc_temp1[19]_i_24_n_0\
    );
\ip_hcs_calc_temp1[19]_i_25\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \bytes00_reg_n_0_[14]\,
      I1 => \identification_reg_n_0_[14]\,
      I2 => ip_total_length(14),
      O => \ip_hcs_calc_temp1[19]_i_25_n_0\
    );
\ip_hcs_calc_temp1[19]_i_26\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \bytes00_reg_n_0_[13]\,
      I1 => \identification_reg_n_0_[13]\,
      I2 => ip_total_length(13),
      O => \ip_hcs_calc_temp1[19]_i_26_n_0\
    );
\ip_hcs_calc_temp1[19]_i_27\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \bytes00_reg_n_0_[12]\,
      I1 => \identification_reg_n_0_[12]\,
      I2 => ip_total_length(12),
      O => \ip_hcs_calc_temp1[19]_i_27_n_0\
    );
\ip_hcs_calc_temp1[19]_i_28\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => data_counter_max2(3),
      I1 => \identification_reg_n_0_[11]\,
      I2 => ip_total_length(11),
      O => \ip_hcs_calc_temp1[19]_i_28_n_0\
    );
\ip_hcs_calc_temp1[19]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[19]_i_25_n_0\,
      I1 => \bytes00_reg_n_0_[15]\,
      I2 => \identification_reg_n_0_[15]\,
      I3 => ip_total_length(15),
      O => \ip_hcs_calc_temp1[19]_i_29_n_0\
    );
\ip_hcs_calc_temp1[19]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_12_n_7\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_11_n_7\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_10_n_7\,
      I3 => \ip_hcs_calc_temp1_reg[23]_i_4_n_6\,
      I4 => \ip_hcs_calc_temp1[19]_i_13_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_3_n_0\
    );
\ip_hcs_calc_temp1[19]_i_30\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \bytes00_reg_n_0_[14]\,
      I1 => \identification_reg_n_0_[14]\,
      I2 => ip_total_length(14),
      I3 => \ip_hcs_calc_temp1[19]_i_26_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_30_n_0\
    );
\ip_hcs_calc_temp1[19]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \bytes00_reg_n_0_[13]\,
      I1 => \identification_reg_n_0_[13]\,
      I2 => ip_total_length(13),
      I3 => \ip_hcs_calc_temp1[19]_i_27_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_31_n_0\
    );
\ip_hcs_calc_temp1[19]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \bytes00_reg_n_0_[12]\,
      I1 => \identification_reg_n_0_[12]\,
      I2 => ip_total_length(12),
      I3 => \ip_hcs_calc_temp1[19]_i_28_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_32_n_0\
    );
\ip_hcs_calc_temp1[19]_i_33\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(14),
      I1 => bytes08(14),
      I2 => bytes07(14),
      O => \ip_hcs_calc_temp1[19]_i_33_n_0\
    );
\ip_hcs_calc_temp1[19]_i_34\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(13),
      I1 => bytes08(13),
      I2 => bytes07(13),
      O => \ip_hcs_calc_temp1[19]_i_34_n_0\
    );
\ip_hcs_calc_temp1[19]_i_35\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(12),
      I1 => bytes08(12),
      I2 => bytes07(12),
      O => \ip_hcs_calc_temp1[19]_i_35_n_0\
    );
\ip_hcs_calc_temp1[19]_i_36\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(11),
      I1 => bytes08(11),
      I2 => bytes07(11),
      O => \ip_hcs_calc_temp1[19]_i_36_n_0\
    );
\ip_hcs_calc_temp1[19]_i_37\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[19]_i_33_n_0\,
      I1 => bytes06(15),
      I2 => bytes08(15),
      I3 => bytes07(15),
      O => \ip_hcs_calc_temp1[19]_i_37_n_0\
    );
\ip_hcs_calc_temp1[19]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes06(14),
      I1 => bytes08(14),
      I2 => bytes07(14),
      I3 => \ip_hcs_calc_temp1[19]_i_34_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_38_n_0\
    );
\ip_hcs_calc_temp1[19]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes06(13),
      I1 => bytes08(13),
      I2 => bytes07(13),
      I3 => \ip_hcs_calc_temp1[19]_i_35_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_39_n_0\
    );
\ip_hcs_calc_temp1[19]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_14_n_4\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_15_n_4\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_16_n_4\,
      I3 => \ip_hcs_calc_temp1_reg[23]_i_4_n_7\,
      I4 => \ip_hcs_calc_temp1[19]_i_17_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_4_n_0\
    );
\ip_hcs_calc_temp1[19]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes06(12),
      I1 => bytes08(12),
      I2 => bytes07(12),
      I3 => \ip_hcs_calc_temp1[19]_i_36_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_40_n_0\
    );
\ip_hcs_calc_temp1[19]_i_41\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[14]\,
      I1 => ip_header_checksum(14),
      I2 => bytes04(14),
      O => \ip_hcs_calc_temp1[19]_i_41_n_0\
    );
\ip_hcs_calc_temp1[19]_i_42\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[13]\,
      I1 => ip_header_checksum(13),
      I2 => bytes04(13),
      O => \ip_hcs_calc_temp1[19]_i_42_n_0\
    );
\ip_hcs_calc_temp1[19]_i_43\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[12]\,
      I1 => ip_header_checksum(12),
      I2 => bytes04(12),
      O => \ip_hcs_calc_temp1[19]_i_43_n_0\
    );
\ip_hcs_calc_temp1[19]_i_44\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[11]\,
      I1 => ip_header_checksum(11),
      I2 => bytes04(11),
      O => \ip_hcs_calc_temp1[19]_i_44_n_0\
    );
\ip_hcs_calc_temp1[19]_i_45\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[19]_i_41_n_0\,
      I1 => \flags_offset_reg_n_0_[15]\,
      I2 => ip_header_checksum(15),
      I3 => bytes04(15),
      O => \ip_hcs_calc_temp1[19]_i_45_n_0\
    );
\ip_hcs_calc_temp1[19]_i_46\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[14]\,
      I1 => ip_header_checksum(14),
      I2 => bytes04(14),
      I3 => \ip_hcs_calc_temp1[19]_i_42_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_46_n_0\
    );
\ip_hcs_calc_temp1[19]_i_47\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[13]\,
      I1 => ip_header_checksum(13),
      I2 => bytes04(13),
      I3 => \ip_hcs_calc_temp1[19]_i_43_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_47_n_0\
    );
\ip_hcs_calc_temp1[19]_i_48\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[12]\,
      I1 => ip_header_checksum(12),
      I2 => bytes04(12),
      I3 => \ip_hcs_calc_temp1[19]_i_44_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_48_n_0\
    );
\ip_hcs_calc_temp1[19]_i_49\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(14),
      I1 => ip_hcs_calc_extra_reg(14),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[14]\,
      O => \ip_hcs_calc_temp1[19]_i_49_n_0\
    );
\ip_hcs_calc_temp1[19]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_14_n_5\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_15_n_5\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_16_n_5\,
      I3 => \ip_hcs_calc_temp1_reg[19]_i_18_n_4\,
      I4 => \ip_hcs_calc_temp1[19]_i_19_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_5_n_0\
    );
\ip_hcs_calc_temp1[19]_i_50\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(13),
      I1 => ip_hcs_calc_extra_reg(13),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[13]\,
      O => \ip_hcs_calc_temp1[19]_i_50_n_0\
    );
\ip_hcs_calc_temp1[19]_i_51\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(12),
      I1 => ip_hcs_calc_extra_reg(12),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[12]\,
      O => \ip_hcs_calc_temp1[19]_i_51_n_0\
    );
\ip_hcs_calc_temp1[19]_i_52\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(11),
      I1 => ip_hcs_calc_extra_reg(11),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[11]\,
      O => \ip_hcs_calc_temp1[19]_i_52_n_0\
    );
\ip_hcs_calc_temp1[19]_i_53\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[19]_i_49_n_0\,
      I1 => ip_hcs_calc_extra_reg(15),
      I2 => bytes09(15),
      I3 => \ip_hcs_calc_temp1_reg_n_0_[15]\,
      O => \ip_hcs_calc_temp1[19]_i_53_n_0\
    );
\ip_hcs_calc_temp1[19]_i_54\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes09(14),
      I1 => ip_hcs_calc_extra_reg(14),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[14]\,
      I3 => \ip_hcs_calc_temp1[19]_i_50_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_54_n_0\
    );
\ip_hcs_calc_temp1[19]_i_55\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes09(13),
      I1 => ip_hcs_calc_extra_reg(13),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[13]\,
      I3 => \ip_hcs_calc_temp1[19]_i_51_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_55_n_0\
    );
\ip_hcs_calc_temp1[19]_i_56\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes09(12),
      I1 => ip_hcs_calc_extra_reg(12),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[12]\,
      I3 => \ip_hcs_calc_temp1[19]_i_52_n_0\,
      O => \ip_hcs_calc_temp1[19]_i_56_n_0\
    );
\ip_hcs_calc_temp1[19]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17FFE800"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[19]_i_12_n_2\,
      I1 => \ip_hcs_calc_temp1_reg[19]_i_11_n_2\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_10_n_2\,
      I3 => \ip_hcs_calc_temp1_reg[23]_i_4_n_5\,
      I4 => \ip_hcs_calc_temp1_reg[23]_i_4_n_4\,
      O => \ip_hcs_calc_temp1[19]_i_6_n_0\
    );
\ip_hcs_calc_temp1[19]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B224244D4DDBDBB2"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[23]_i_4_n_6\,
      I1 => \ip_hcs_calc_temp1[19]_i_20_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_10_n_2\,
      I3 => \ip_hcs_calc_temp1_reg[19]_i_11_n_2\,
      I4 => \ip_hcs_calc_temp1_reg[19]_i_12_n_2\,
      I5 => \ip_hcs_calc_temp1_reg[23]_i_4_n_5\,
      O => \ip_hcs_calc_temp1[19]_i_7_n_0\
    );
\ip_hcs_calc_temp1[19]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[19]_i_4_n_0\,
      I1 => \ip_hcs_calc_temp1[19]_i_20_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_10_n_2\,
      I3 => \ip_hcs_calc_temp1_reg[19]_i_11_n_2\,
      I4 => \ip_hcs_calc_temp1_reg[19]_i_12_n_2\,
      I5 => \ip_hcs_calc_temp1_reg[23]_i_4_n_6\,
      O => \ip_hcs_calc_temp1[19]_i_8_n_0\
    );
\ip_hcs_calc_temp1[19]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[19]_i_5_n_0\,
      I1 => \ip_hcs_calc_temp1[19]_i_21_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[19]_i_10_n_7\,
      I3 => \ip_hcs_calc_temp1_reg[19]_i_11_n_7\,
      I4 => \ip_hcs_calc_temp1_reg[19]_i_12_n_7\,
      I5 => \ip_hcs_calc_temp1_reg[23]_i_4_n_7\,
      O => \ip_hcs_calc_temp1[19]_i_9_n_0\
    );
\ip_hcs_calc_temp1[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => edge_count_header,
      I1 => ip_hcs_done,
      O => \ip_hcs_calc_temp1[23]_i_1_n_0\
    );
\ip_hcs_calc_temp1[23]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[20]\,
      I1 => ip_hcs_calc_extra_reg(20),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[21]\,
      I3 => ip_hcs_calc_extra_reg(21),
      O => \ip_hcs_calc_temp1[23]_i_10_n_0\
    );
\ip_hcs_calc_temp1[23]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[19]\,
      I1 => ip_hcs_calc_extra_reg(19),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[20]\,
      I3 => ip_hcs_calc_extra_reg(20),
      O => \ip_hcs_calc_temp1[23]_i_11_n_0\
    );
\ip_hcs_calc_temp1[23]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_hcs_calc_extra_reg(18),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[18]\,
      O => \ip_hcs_calc_temp1[23]_i_12_n_0\
    );
\ip_hcs_calc_temp1[23]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_hcs_calc_extra_reg(17),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[17]\,
      O => \ip_hcs_calc_temp1[23]_i_13_n_0\
    );
\ip_hcs_calc_temp1[23]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_hcs_calc_extra_reg(16),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[16]\,
      O => \ip_hcs_calc_temp1[23]_i_14_n_0\
    );
\ip_hcs_calc_temp1[23]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(15),
      I1 => ip_hcs_calc_extra_reg(15),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[15]\,
      O => \ip_hcs_calc_temp1[23]_i_15_n_0\
    );
\ip_hcs_calc_temp1[23]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[18]\,
      I1 => ip_hcs_calc_extra_reg(18),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[19]\,
      I3 => ip_hcs_calc_extra_reg(19),
      O => \ip_hcs_calc_temp1[23]_i_16_n_0\
    );
\ip_hcs_calc_temp1[23]_i_17\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[17]\,
      I1 => ip_hcs_calc_extra_reg(17),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[18]\,
      I3 => ip_hcs_calc_extra_reg(18),
      O => \ip_hcs_calc_temp1[23]_i_17_n_0\
    );
\ip_hcs_calc_temp1[23]_i_18\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[16]\,
      I1 => ip_hcs_calc_extra_reg(16),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[17]\,
      I3 => ip_hcs_calc_extra_reg(17),
      O => \ip_hcs_calc_temp1[23]_i_18_n_0\
    );
\ip_hcs_calc_temp1[23]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E81717E8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[15]\,
      I1 => ip_hcs_calc_extra_reg(15),
      I2 => bytes09(15),
      I3 => \ip_hcs_calc_temp1_reg_n_0_[16]\,
      I4 => ip_hcs_calc_extra_reg(16),
      O => \ip_hcs_calc_temp1[23]_i_19_n_0\
    );
\ip_hcs_calc_temp1[23]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_hcs_calc_extra_reg(21),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[21]\,
      O => \ip_hcs_calc_temp1[23]_i_5_n_0\
    );
\ip_hcs_calc_temp1[23]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_hcs_calc_extra_reg(20),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[20]\,
      O => \ip_hcs_calc_temp1[23]_i_6_n_0\
    );
\ip_hcs_calc_temp1[23]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_hcs_calc_extra_reg(19),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[19]\,
      O => \ip_hcs_calc_temp1[23]_i_7_n_0\
    );
\ip_hcs_calc_temp1[23]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[22]\,
      I1 => ip_hcs_calc_extra_reg(22),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[23]\,
      I3 => ip_hcs_calc_extra_reg(23),
      O => \ip_hcs_calc_temp1[23]_i_8_n_0\
    );
\ip_hcs_calc_temp1[23]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[21]\,
      I1 => ip_hcs_calc_extra_reg(21),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[22]\,
      I3 => ip_hcs_calc_extra_reg(22),
      O => \ip_hcs_calc_temp1[23]_i_9_n_0\
    );
\ip_hcs_calc_temp1[3]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[7]_i_14_n_5\,
      I1 => \ip_hcs_calc_temp1_reg[7]_i_13_n_5\,
      I2 => \ip_hcs_calc_temp1_reg[7]_i_12_n_5\,
      O => \ip_hcs_calc_temp1[3]_i_10_n_0\
    );
\ip_hcs_calc_temp1[3]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(2),
      I1 => ip_hcs_calc_extra_reg(2),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[2]\,
      O => \ip_hcs_calc_temp1[3]_i_11_n_0\
    );
\ip_hcs_calc_temp1[3]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes09(1),
      I1 => ip_hcs_calc_extra_reg(1),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[1]\,
      O => \ip_hcs_calc_temp1[3]_i_12_n_0\
    );
\ip_hcs_calc_temp1[3]_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[0]\,
      I1 => ip_hcs_calc_extra_reg(0),
      I2 => bytes09(0),
      O => \ip_hcs_calc_temp1[3]_i_13_n_0\
    );
\ip_hcs_calc_temp1[3]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes09(3),
      I1 => ip_hcs_calc_extra_reg(3),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[3]\,
      I3 => \ip_hcs_calc_temp1[3]_i_11_n_0\,
      O => \ip_hcs_calc_temp1[3]_i_14_n_0\
    );
\ip_hcs_calc_temp1[3]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes09(2),
      I1 => ip_hcs_calc_extra_reg(2),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[2]\,
      I3 => \ip_hcs_calc_temp1[3]_i_12_n_0\,
      O => \ip_hcs_calc_temp1[3]_i_15_n_0\
    );
\ip_hcs_calc_temp1[3]_i_16\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes09(1),
      I1 => ip_hcs_calc_extra_reg(1),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[1]\,
      I3 => \ip_hcs_calc_temp1[3]_i_13_n_0\,
      O => \ip_hcs_calc_temp1[3]_i_16_n_0\
    );
\ip_hcs_calc_temp1[3]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[0]\,
      I1 => ip_hcs_calc_extra_reg(0),
      I2 => bytes09(0),
      O => \ip_hcs_calc_temp1[3]_i_17_n_0\
    );
\ip_hcs_calc_temp1[3]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[7]_i_12_n_5\,
      I1 => \ip_hcs_calc_temp1_reg[7]_i_13_n_5\,
      I2 => \ip_hcs_calc_temp1_reg[7]_i_14_n_5\,
      O => \ip_hcs_calc_temp1[3]_i_18_n_0\
    );
\ip_hcs_calc_temp1[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEE8E888"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[3]_i_5_n_5\,
      I1 => \ip_hcs_calc_temp1[3]_i_10_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[7]_i_12_n_6\,
      I3 => \ip_hcs_calc_temp1_reg[7]_i_13_n_6\,
      I4 => \ip_hcs_calc_temp1_reg[7]_i_14_n_6\,
      O => \ip_hcs_calc_temp1[3]_i_2_n_0\
    );
\ip_hcs_calc_temp1[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E81717E8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[7]_i_14_n_6\,
      I1 => \ip_hcs_calc_temp1_reg[7]_i_13_n_6\,
      I2 => \ip_hcs_calc_temp1_reg[7]_i_12_n_6\,
      I3 => \ip_hcs_calc_temp1[3]_i_10_n_0\,
      I4 => \ip_hcs_calc_temp1_reg[3]_i_5_n_5\,
      O => \ip_hcs_calc_temp1[3]_i_3_n_0\
    );
\ip_hcs_calc_temp1[3]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[7]_i_12_n_6\,
      I1 => \ip_hcs_calc_temp1_reg[7]_i_13_n_6\,
      I2 => \ip_hcs_calc_temp1_reg[7]_i_14_n_6\,
      I3 => \ip_hcs_calc_temp1_reg[3]_i_5_n_6\,
      O => \ip_hcs_calc_temp1[3]_i_4_n_0\
    );
\ip_hcs_calc_temp1[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[3]_i_2_n_0\,
      I1 => \ip_hcs_calc_temp1[3]_i_18_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[7]_i_14_n_4\,
      I3 => \ip_hcs_calc_temp1_reg[7]_i_13_n_4\,
      I4 => \ip_hcs_calc_temp1_reg[7]_i_12_n_4\,
      I5 => \ip_hcs_calc_temp1_reg[3]_i_5_n_4\,
      O => \ip_hcs_calc_temp1[3]_i_6_n_0\
    );
\ip_hcs_calc_temp1[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6999999699969666"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[3]_i_5_n_5\,
      I1 => \ip_hcs_calc_temp1[3]_i_10_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[7]_i_14_n_6\,
      I3 => \ip_hcs_calc_temp1_reg[7]_i_13_n_6\,
      I4 => \ip_hcs_calc_temp1_reg[7]_i_12_n_6\,
      I5 => \ip_hcs_calc_temp1_reg[3]_i_5_n_6\,
      O => \ip_hcs_calc_temp1[3]_i_7_n_0\
    );
\ip_hcs_calc_temp1[3]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"566A"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[3]_i_4_n_0\,
      I1 => \ip_hcs_calc_temp1_reg[7]_i_14_n_7\,
      I2 => \ip_hcs_calc_temp1_reg[7]_i_12_n_7\,
      I3 => \ip_hcs_calc_temp1_reg[7]_i_13_n_7\,
      O => \ip_hcs_calc_temp1[3]_i_8_n_0\
    );
\ip_hcs_calc_temp1[3]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[7]_i_12_n_7\,
      I1 => \ip_hcs_calc_temp1_reg[7]_i_14_n_7\,
      I2 => \ip_hcs_calc_temp1_reg[7]_i_13_n_7\,
      I3 => \ip_hcs_calc_temp1_reg[3]_i_5_n_7\,
      O => \ip_hcs_calc_temp1[3]_i_9_n_0\
    );
\ip_hcs_calc_temp1[7]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[11]_i_14_n_5\,
      I1 => \ip_hcs_calc_temp1_reg[11]_i_13_n_5\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_12_n_5\,
      O => \ip_hcs_calc_temp1[7]_i_10_n_0\
    );
\ip_hcs_calc_temp1[7]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[11]_i_14_n_6\,
      I1 => \ip_hcs_calc_temp1_reg[11]_i_13_n_6\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_12_n_6\,
      O => \ip_hcs_calc_temp1[7]_i_11_n_0\
    );
\ip_hcs_calc_temp1[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[11]_i_14_n_7\,
      I1 => \ip_hcs_calc_temp1_reg[11]_i_13_n_7\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_12_n_7\,
      O => \ip_hcs_calc_temp1[7]_i_15_n_0\
    );
\ip_hcs_calc_temp1[7]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[7]_i_14_n_4\,
      I1 => \ip_hcs_calc_temp1_reg[7]_i_13_n_4\,
      I2 => \ip_hcs_calc_temp1_reg[7]_i_12_n_4\,
      O => \ip_hcs_calc_temp1[7]_i_16_n_0\
    );
\ip_hcs_calc_temp1[7]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[11]_i_12_n_5\,
      I1 => \ip_hcs_calc_temp1_reg[11]_i_13_n_5\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_14_n_5\,
      O => \ip_hcs_calc_temp1[7]_i_17_n_0\
    );
\ip_hcs_calc_temp1[7]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[11]_i_12_n_6\,
      I1 => \ip_hcs_calc_temp1_reg[11]_i_13_n_6\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_14_n_6\,
      O => \ip_hcs_calc_temp1[7]_i_18_n_0\
    );
\ip_hcs_calc_temp1[7]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[11]_i_12_n_7\,
      I1 => \ip_hcs_calc_temp1_reg[11]_i_13_n_7\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_14_n_7\,
      O => \ip_hcs_calc_temp1[7]_i_19_n_0\
    );
\ip_hcs_calc_temp1[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[11]_i_12_n_6\,
      I1 => \ip_hcs_calc_temp1_reg[11]_i_13_n_6\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_14_n_6\,
      I3 => \ip_hcs_calc_temp1_reg[11]_i_16_n_5\,
      I4 => \ip_hcs_calc_temp1[7]_i_10_n_0\,
      O => \ip_hcs_calc_temp1[7]_i_2_n_0\
    );
\ip_hcs_calc_temp1[7]_i_20\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[7]_i_12_n_4\,
      I1 => \ip_hcs_calc_temp1_reg[7]_i_13_n_4\,
      I2 => \ip_hcs_calc_temp1_reg[7]_i_14_n_4\,
      O => \ip_hcs_calc_temp1[7]_i_20_n_0\
    );
\ip_hcs_calc_temp1[7]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \bytes00_reg_n_0_[2]\,
      I1 => \identification_reg_n_0_[2]\,
      I2 => ip_total_length(2),
      O => \ip_hcs_calc_temp1[7]_i_21_n_0\
    );
\ip_hcs_calc_temp1[7]_i_22\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \bytes00_reg_n_0_[1]\,
      I1 => \identification_reg_n_0_[1]\,
      I2 => \data_counter_max_reg_n_0_[1]\,
      O => \ip_hcs_calc_temp1[7]_i_22_n_0\
    );
\ip_hcs_calc_temp1[7]_i_23\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \identification_reg_n_0_[0]\,
      I1 => \data_counter_max_reg_n_0_[0]\,
      I2 => \bytes00_reg_n_0_[0]\,
      O => \ip_hcs_calc_temp1[7]_i_23_n_0\
    );
\ip_hcs_calc_temp1[7]_i_24\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \bytes00_reg_n_0_[3]\,
      I1 => \identification_reg_n_0_[3]\,
      I2 => ip_total_length(3),
      I3 => \ip_hcs_calc_temp1[7]_i_21_n_0\,
      O => \ip_hcs_calc_temp1[7]_i_24_n_0\
    );
\ip_hcs_calc_temp1[7]_i_25\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \bytes00_reg_n_0_[2]\,
      I1 => \identification_reg_n_0_[2]\,
      I2 => ip_total_length(2),
      I3 => \ip_hcs_calc_temp1[7]_i_22_n_0\,
      O => \ip_hcs_calc_temp1[7]_i_25_n_0\
    );
\ip_hcs_calc_temp1[7]_i_26\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \bytes00_reg_n_0_[1]\,
      I1 => \identification_reg_n_0_[1]\,
      I2 => \data_counter_max_reg_n_0_[1]\,
      I3 => \ip_hcs_calc_temp1[7]_i_23_n_0\,
      O => \ip_hcs_calc_temp1[7]_i_26_n_0\
    );
\ip_hcs_calc_temp1[7]_i_27\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \identification_reg_n_0_[0]\,
      I1 => \data_counter_max_reg_n_0_[0]\,
      I2 => \bytes00_reg_n_0_[0]\,
      O => \ip_hcs_calc_temp1[7]_i_27_n_0\
    );
\ip_hcs_calc_temp1[7]_i_28\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(2),
      I1 => bytes08(2),
      I2 => bytes07(2),
      O => \ip_hcs_calc_temp1[7]_i_28_n_0\
    );
\ip_hcs_calc_temp1[7]_i_29\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes06(1),
      I1 => bytes08(1),
      I2 => bytes07(1),
      O => \ip_hcs_calc_temp1[7]_i_29_n_0\
    );
\ip_hcs_calc_temp1[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[11]_i_12_n_7\,
      I1 => \ip_hcs_calc_temp1_reg[11]_i_13_n_7\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_14_n_7\,
      I3 => \ip_hcs_calc_temp1_reg[11]_i_16_n_6\,
      I4 => \ip_hcs_calc_temp1[7]_i_11_n_0\,
      O => \ip_hcs_calc_temp1[7]_i_3_n_0\
    );
\ip_hcs_calc_temp1[7]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes08(0),
      I1 => bytes06(0),
      I2 => bytes07(0),
      O => \ip_hcs_calc_temp1[7]_i_30_n_0\
    );
\ip_hcs_calc_temp1[7]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes06(3),
      I1 => bytes08(3),
      I2 => bytes07(3),
      I3 => \ip_hcs_calc_temp1[7]_i_28_n_0\,
      O => \ip_hcs_calc_temp1[7]_i_31_n_0\
    );
\ip_hcs_calc_temp1[7]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes06(2),
      I1 => bytes08(2),
      I2 => bytes07(2),
      I3 => \ip_hcs_calc_temp1[7]_i_29_n_0\,
      O => \ip_hcs_calc_temp1[7]_i_32_n_0\
    );
\ip_hcs_calc_temp1[7]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes06(1),
      I1 => bytes08(1),
      I2 => bytes07(1),
      I3 => \ip_hcs_calc_temp1[7]_i_30_n_0\,
      O => \ip_hcs_calc_temp1[7]_i_33_n_0\
    );
\ip_hcs_calc_temp1[7]_i_34\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => bytes08(0),
      I1 => bytes06(0),
      I2 => bytes07(0),
      O => \ip_hcs_calc_temp1[7]_i_34_n_0\
    );
\ip_hcs_calc_temp1[7]_i_35\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[2]\,
      I1 => ip_header_checksum(2),
      I2 => bytes04(2),
      O => \ip_hcs_calc_temp1[7]_i_35_n_0\
    );
\ip_hcs_calc_temp1[7]_i_36\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[1]\,
      I1 => ip_header_checksum(1),
      I2 => bytes04(1),
      O => \ip_hcs_calc_temp1[7]_i_36_n_0\
    );
\ip_hcs_calc_temp1[7]_i_37\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => ip_header_checksum(0),
      I1 => \flags_offset_reg_n_0_[0]\,
      I2 => bytes04(0),
      O => \ip_hcs_calc_temp1[7]_i_37_n_0\
    );
\ip_hcs_calc_temp1[7]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[3]\,
      I1 => ip_header_checksum(3),
      I2 => bytes04(3),
      I3 => \ip_hcs_calc_temp1[7]_i_35_n_0\,
      O => \ip_hcs_calc_temp1[7]_i_38_n_0\
    );
\ip_hcs_calc_temp1[7]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[2]\,
      I1 => ip_header_checksum(2),
      I2 => bytes04(2),
      I3 => \ip_hcs_calc_temp1[7]_i_36_n_0\,
      O => \ip_hcs_calc_temp1[7]_i_39_n_0\
    );
\ip_hcs_calc_temp1[7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[7]_i_12_n_4\,
      I1 => \ip_hcs_calc_temp1_reg[7]_i_13_n_4\,
      I2 => \ip_hcs_calc_temp1_reg[7]_i_14_n_4\,
      I3 => \ip_hcs_calc_temp1_reg[11]_i_16_n_7\,
      I4 => \ip_hcs_calc_temp1[7]_i_15_n_0\,
      O => \ip_hcs_calc_temp1[7]_i_4_n_0\
    );
\ip_hcs_calc_temp1[7]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \flags_offset_reg_n_0_[1]\,
      I1 => ip_header_checksum(1),
      I2 => bytes04(1),
      I3 => \ip_hcs_calc_temp1[7]_i_37_n_0\,
      O => \ip_hcs_calc_temp1[7]_i_40_n_0\
    );
\ip_hcs_calc_temp1[7]_i_41\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => ip_header_checksum(0),
      I1 => \flags_offset_reg_n_0_[0]\,
      I2 => bytes04(0),
      O => \ip_hcs_calc_temp1[7]_i_41_n_0\
    );
\ip_hcs_calc_temp1[7]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg[7]_i_12_n_5\,
      I1 => \ip_hcs_calc_temp1_reg[7]_i_13_n_5\,
      I2 => \ip_hcs_calc_temp1_reg[7]_i_14_n_5\,
      I3 => \ip_hcs_calc_temp1_reg[3]_i_5_n_4\,
      I4 => \ip_hcs_calc_temp1[7]_i_16_n_0\,
      O => \ip_hcs_calc_temp1[7]_i_5_n_0\
    );
\ip_hcs_calc_temp1[7]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[7]_i_2_n_0\,
      I1 => \ip_hcs_calc_temp1[7]_i_17_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_14_n_4\,
      I3 => \ip_hcs_calc_temp1_reg[11]_i_13_n_4\,
      I4 => \ip_hcs_calc_temp1_reg[11]_i_12_n_4\,
      I5 => \ip_hcs_calc_temp1_reg[11]_i_16_n_4\,
      O => \ip_hcs_calc_temp1[7]_i_6_n_0\
    );
\ip_hcs_calc_temp1[7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[7]_i_3_n_0\,
      I1 => \ip_hcs_calc_temp1[7]_i_18_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_14_n_5\,
      I3 => \ip_hcs_calc_temp1_reg[11]_i_13_n_5\,
      I4 => \ip_hcs_calc_temp1_reg[11]_i_12_n_5\,
      I5 => \ip_hcs_calc_temp1_reg[11]_i_16_n_5\,
      O => \ip_hcs_calc_temp1[7]_i_7_n_0\
    );
\ip_hcs_calc_temp1[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[7]_i_4_n_0\,
      I1 => \ip_hcs_calc_temp1[7]_i_19_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_14_n_6\,
      I3 => \ip_hcs_calc_temp1_reg[11]_i_13_n_6\,
      I4 => \ip_hcs_calc_temp1_reg[11]_i_12_n_6\,
      I5 => \ip_hcs_calc_temp1_reg[11]_i_16_n_6\,
      O => \ip_hcs_calc_temp1[7]_i_8_n_0\
    );
\ip_hcs_calc_temp1[7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \ip_hcs_calc_temp1[7]_i_5_n_0\,
      I1 => \ip_hcs_calc_temp1[7]_i_20_n_0\,
      I2 => \ip_hcs_calc_temp1_reg[11]_i_14_n_7\,
      I3 => \ip_hcs_calc_temp1_reg[11]_i_13_n_7\,
      I4 => \ip_hcs_calc_temp1_reg[11]_i_12_n_7\,
      I5 => \ip_hcs_calc_temp1_reg[11]_i_16_n_7\,
      O => \ip_hcs_calc_temp1[7]_i_9_n_0\
    );
\ip_hcs_calc_temp1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[3]_i_1_n_7\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[0]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[11]_i_1_n_5\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[10]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[11]_i_1_n_4\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[11]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[7]_i_1_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[11]_i_1_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[11]_i_1_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[11]_i_1_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[11]_i_2_n_0\,
      DI(2) => \ip_hcs_calc_temp1[11]_i_3_n_0\,
      DI(1) => \ip_hcs_calc_temp1[11]_i_4_n_0\,
      DI(0) => \ip_hcs_calc_temp1[11]_i_5_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[11]_i_1_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[11]_i_1_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[11]_i_1_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[11]_i_1_n_7\,
      S(3) => \ip_hcs_calc_temp1[11]_i_6_n_0\,
      S(2) => \ip_hcs_calc_temp1[11]_i_7_n_0\,
      S(1) => \ip_hcs_calc_temp1[11]_i_8_n_0\,
      S(0) => \ip_hcs_calc_temp1[11]_i_9_n_0\
    );
\ip_hcs_calc_temp1_reg[11]_i_12\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[7]_i_12_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[11]_i_12_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[11]_i_12_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[11]_i_12_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[11]_i_12_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[11]_i_22_n_0\,
      DI(2) => \ip_hcs_calc_temp1[11]_i_23_n_0\,
      DI(1) => \ip_hcs_calc_temp1[11]_i_24_n_0\,
      DI(0) => \ip_hcs_calc_temp1[11]_i_25_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[11]_i_12_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[11]_i_12_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[11]_i_12_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[11]_i_12_n_7\,
      S(3) => \ip_hcs_calc_temp1[11]_i_26_n_0\,
      S(2) => \ip_hcs_calc_temp1[11]_i_27_n_0\,
      S(1) => \ip_hcs_calc_temp1[11]_i_28_n_0\,
      S(0) => \ip_hcs_calc_temp1[11]_i_29_n_0\
    );
\ip_hcs_calc_temp1_reg[11]_i_13\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[7]_i_13_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[11]_i_13_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[11]_i_13_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[11]_i_13_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[11]_i_13_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[11]_i_30_n_0\,
      DI(2) => \ip_hcs_calc_temp1[11]_i_31_n_0\,
      DI(1) => \ip_hcs_calc_temp1[11]_i_32_n_0\,
      DI(0) => \ip_hcs_calc_temp1[11]_i_33_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[11]_i_13_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[11]_i_13_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[11]_i_13_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[11]_i_13_n_7\,
      S(3) => \ip_hcs_calc_temp1[11]_i_34_n_0\,
      S(2) => \ip_hcs_calc_temp1[11]_i_35_n_0\,
      S(1) => \ip_hcs_calc_temp1[11]_i_36_n_0\,
      S(0) => \ip_hcs_calc_temp1[11]_i_37_n_0\
    );
\ip_hcs_calc_temp1_reg[11]_i_14\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[7]_i_14_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[11]_i_14_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[11]_i_14_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[11]_i_14_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[11]_i_14_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[11]_i_38_n_0\,
      DI(2) => \ip_hcs_calc_temp1[11]_i_39_n_0\,
      DI(1) => \ip_hcs_calc_temp1[11]_i_40_n_0\,
      DI(0) => \ip_hcs_calc_temp1[11]_i_41_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[11]_i_14_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[11]_i_14_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[11]_i_14_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[11]_i_14_n_7\,
      S(3) => \ip_hcs_calc_temp1[11]_i_42_n_0\,
      S(2) => \ip_hcs_calc_temp1[11]_i_43_n_0\,
      S(1) => \ip_hcs_calc_temp1[11]_i_44_n_0\,
      S(0) => \ip_hcs_calc_temp1[11]_i_45_n_0\
    );
\ip_hcs_calc_temp1_reg[11]_i_16\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[3]_i_5_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[11]_i_16_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[11]_i_16_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[11]_i_16_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[11]_i_16_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[11]_i_46_n_0\,
      DI(2) => \ip_hcs_calc_temp1[11]_i_47_n_0\,
      DI(1) => \ip_hcs_calc_temp1[11]_i_48_n_0\,
      DI(0) => \ip_hcs_calc_temp1[11]_i_49_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[11]_i_16_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[11]_i_16_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[11]_i_16_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[11]_i_16_n_7\,
      S(3) => \ip_hcs_calc_temp1[11]_i_50_n_0\,
      S(2) => \ip_hcs_calc_temp1[11]_i_51_n_0\,
      S(1) => \ip_hcs_calc_temp1[11]_i_52_n_0\,
      S(0) => \ip_hcs_calc_temp1[11]_i_53_n_0\
    );
\ip_hcs_calc_temp1_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[15]_i_1_n_7\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[12]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[15]_i_1_n_6\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[13]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[15]_i_1_n_5\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[14]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[15]_i_1_n_4\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[15]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[15]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[11]_i_1_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[15]_i_1_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[15]_i_1_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[15]_i_1_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[15]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[15]_i_2_n_0\,
      DI(2) => \ip_hcs_calc_temp1[15]_i_3_n_0\,
      DI(1) => \ip_hcs_calc_temp1[15]_i_4_n_0\,
      DI(0) => \ip_hcs_calc_temp1[15]_i_5_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[15]_i_1_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[15]_i_1_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[15]_i_1_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[15]_i_1_n_7\,
      S(3) => \ip_hcs_calc_temp1[15]_i_6_n_0\,
      S(2) => \ip_hcs_calc_temp1[15]_i_7_n_0\,
      S(1) => \ip_hcs_calc_temp1[15]_i_8_n_0\,
      S(0) => \ip_hcs_calc_temp1[15]_i_9_n_0\
    );
\ip_hcs_calc_temp1_reg[15]_i_13\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[11]_i_12_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[15]_i_13_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[15]_i_13_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[15]_i_13_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[15]_i_13_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[15]_i_20_n_0\,
      DI(2) => \ip_hcs_calc_temp1[15]_i_21_n_0\,
      DI(1) => \ip_hcs_calc_temp1[15]_i_22_n_0\,
      DI(0) => \ip_hcs_calc_temp1[15]_i_23_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[15]_i_13_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[15]_i_13_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[15]_i_13_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[15]_i_13_n_7\,
      S(3) => \ip_hcs_calc_temp1[15]_i_24_n_0\,
      S(2) => \ip_hcs_calc_temp1[15]_i_25_n_0\,
      S(1) => \ip_hcs_calc_temp1[15]_i_26_n_0\,
      S(0) => \ip_hcs_calc_temp1[15]_i_27_n_0\
    );
\ip_hcs_calc_temp1_reg[15]_i_14\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[11]_i_13_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[15]_i_14_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[15]_i_14_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[15]_i_14_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[15]_i_14_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[15]_i_28_n_0\,
      DI(2) => \ip_hcs_calc_temp1[15]_i_29_n_0\,
      DI(1) => \ip_hcs_calc_temp1[15]_i_30_n_0\,
      DI(0) => \ip_hcs_calc_temp1[15]_i_31_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[15]_i_14_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[15]_i_14_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[15]_i_14_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[15]_i_14_n_7\,
      S(3) => \ip_hcs_calc_temp1[15]_i_32_n_0\,
      S(2) => \ip_hcs_calc_temp1[15]_i_33_n_0\,
      S(1) => \ip_hcs_calc_temp1[15]_i_34_n_0\,
      S(0) => \ip_hcs_calc_temp1[15]_i_35_n_0\
    );
\ip_hcs_calc_temp1_reg[15]_i_15\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[11]_i_14_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[15]_i_15_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[15]_i_15_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[15]_i_15_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[15]_i_15_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[15]_i_36_n_0\,
      DI(2) => \ip_hcs_calc_temp1[15]_i_37_n_0\,
      DI(1) => \ip_hcs_calc_temp1[15]_i_38_n_0\,
      DI(0) => \ip_hcs_calc_temp1[15]_i_39_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[15]_i_15_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[15]_i_15_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[15]_i_15_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[15]_i_15_n_7\,
      S(3) => \ip_hcs_calc_temp1[15]_i_40_n_0\,
      S(2) => \ip_hcs_calc_temp1[15]_i_41_n_0\,
      S(1) => \ip_hcs_calc_temp1[15]_i_42_n_0\,
      S(0) => \ip_hcs_calc_temp1[15]_i_43_n_0\
    );
\ip_hcs_calc_temp1_reg[15]_i_16\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[11]_i_16_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[15]_i_16_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[15]_i_16_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[15]_i_16_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[15]_i_16_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[15]_i_44_n_0\,
      DI(2) => \ip_hcs_calc_temp1[15]_i_45_n_0\,
      DI(1) => \ip_hcs_calc_temp1[15]_i_46_n_0\,
      DI(0) => \ip_hcs_calc_temp1[15]_i_47_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[15]_i_16_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[15]_i_16_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[15]_i_16_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[15]_i_16_n_7\,
      S(3) => \ip_hcs_calc_temp1[15]_i_48_n_0\,
      S(2) => \ip_hcs_calc_temp1[15]_i_49_n_0\,
      S(1) => \ip_hcs_calc_temp1[15]_i_50_n_0\,
      S(0) => \ip_hcs_calc_temp1[15]_i_51_n_0\
    );
\ip_hcs_calc_temp1_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[19]_i_1_n_7\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[16]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[19]_i_1_n_6\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[17]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[19]_i_1_n_5\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[18]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[19]_i_1_n_4\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[19]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[19]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[15]_i_1_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[19]_i_1_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[19]_i_1_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[19]_i_1_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[19]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[19]_i_2_n_0\,
      DI(2) => \ip_hcs_calc_temp1[19]_i_3_n_0\,
      DI(1) => \ip_hcs_calc_temp1[19]_i_4_n_0\,
      DI(0) => \ip_hcs_calc_temp1[19]_i_5_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[19]_i_1_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[19]_i_1_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[19]_i_1_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[19]_i_1_n_7\,
      S(3) => \ip_hcs_calc_temp1[19]_i_6_n_0\,
      S(2) => \ip_hcs_calc_temp1[19]_i_7_n_0\,
      S(1) => \ip_hcs_calc_temp1[19]_i_8_n_0\,
      S(0) => \ip_hcs_calc_temp1[19]_i_9_n_0\
    );
\ip_hcs_calc_temp1_reg[19]_i_10\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[19]_i_16_n_0\,
      CO(3 downto 2) => \NLW_ip_hcs_calc_temp1_reg[19]_i_10_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \ip_hcs_calc_temp1_reg[19]_i_10_n_2\,
      CO(0) => \NLW_ip_hcs_calc_temp1_reg[19]_i_10_CO_UNCONNECTED\(0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_ip_hcs_calc_temp1_reg[19]_i_10_O_UNCONNECTED\(3 downto 1),
      O(0) => \ip_hcs_calc_temp1_reg[19]_i_10_n_7\,
      S(3 downto 1) => B"001",
      S(0) => \ip_hcs_calc_temp1[19]_i_22_n_0\
    );
\ip_hcs_calc_temp1_reg[19]_i_11\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[19]_i_15_n_0\,
      CO(3 downto 2) => \NLW_ip_hcs_calc_temp1_reg[19]_i_11_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \ip_hcs_calc_temp1_reg[19]_i_11_n_2\,
      CO(0) => \NLW_ip_hcs_calc_temp1_reg[19]_i_11_CO_UNCONNECTED\(0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_ip_hcs_calc_temp1_reg[19]_i_11_O_UNCONNECTED\(3 downto 1),
      O(0) => \ip_hcs_calc_temp1_reg[19]_i_11_n_7\,
      S(3 downto 1) => B"001",
      S(0) => \ip_hcs_calc_temp1[19]_i_23_n_0\
    );
\ip_hcs_calc_temp1_reg[19]_i_12\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[19]_i_14_n_0\,
      CO(3 downto 2) => \NLW_ip_hcs_calc_temp1_reg[19]_i_12_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \ip_hcs_calc_temp1_reg[19]_i_12_n_2\,
      CO(0) => \NLW_ip_hcs_calc_temp1_reg[19]_i_12_CO_UNCONNECTED\(0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_ip_hcs_calc_temp1_reg[19]_i_12_O_UNCONNECTED\(3 downto 1),
      O(0) => \ip_hcs_calc_temp1_reg[19]_i_12_n_7\,
      S(3 downto 1) => B"001",
      S(0) => \ip_hcs_calc_temp1[19]_i_24_n_0\
    );
\ip_hcs_calc_temp1_reg[19]_i_14\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[15]_i_13_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[19]_i_14_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[19]_i_14_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[19]_i_14_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[19]_i_14_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[19]_i_25_n_0\,
      DI(2) => \ip_hcs_calc_temp1[19]_i_26_n_0\,
      DI(1) => \ip_hcs_calc_temp1[19]_i_27_n_0\,
      DI(0) => \ip_hcs_calc_temp1[19]_i_28_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[19]_i_14_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[19]_i_14_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[19]_i_14_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[19]_i_14_n_7\,
      S(3) => \ip_hcs_calc_temp1[19]_i_29_n_0\,
      S(2) => \ip_hcs_calc_temp1[19]_i_30_n_0\,
      S(1) => \ip_hcs_calc_temp1[19]_i_31_n_0\,
      S(0) => \ip_hcs_calc_temp1[19]_i_32_n_0\
    );
\ip_hcs_calc_temp1_reg[19]_i_15\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[15]_i_14_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[19]_i_15_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[19]_i_15_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[19]_i_15_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[19]_i_15_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[19]_i_33_n_0\,
      DI(2) => \ip_hcs_calc_temp1[19]_i_34_n_0\,
      DI(1) => \ip_hcs_calc_temp1[19]_i_35_n_0\,
      DI(0) => \ip_hcs_calc_temp1[19]_i_36_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[19]_i_15_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[19]_i_15_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[19]_i_15_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[19]_i_15_n_7\,
      S(3) => \ip_hcs_calc_temp1[19]_i_37_n_0\,
      S(2) => \ip_hcs_calc_temp1[19]_i_38_n_0\,
      S(1) => \ip_hcs_calc_temp1[19]_i_39_n_0\,
      S(0) => \ip_hcs_calc_temp1[19]_i_40_n_0\
    );
\ip_hcs_calc_temp1_reg[19]_i_16\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[15]_i_15_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[19]_i_16_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[19]_i_16_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[19]_i_16_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[19]_i_16_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[19]_i_41_n_0\,
      DI(2) => \ip_hcs_calc_temp1[19]_i_42_n_0\,
      DI(1) => \ip_hcs_calc_temp1[19]_i_43_n_0\,
      DI(0) => \ip_hcs_calc_temp1[19]_i_44_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[19]_i_16_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[19]_i_16_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[19]_i_16_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[19]_i_16_n_7\,
      S(3) => \ip_hcs_calc_temp1[19]_i_45_n_0\,
      S(2) => \ip_hcs_calc_temp1[19]_i_46_n_0\,
      S(1) => \ip_hcs_calc_temp1[19]_i_47_n_0\,
      S(0) => \ip_hcs_calc_temp1[19]_i_48_n_0\
    );
\ip_hcs_calc_temp1_reg[19]_i_18\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[15]_i_16_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[19]_i_18_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[19]_i_18_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[19]_i_18_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[19]_i_18_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[19]_i_49_n_0\,
      DI(2) => \ip_hcs_calc_temp1[19]_i_50_n_0\,
      DI(1) => \ip_hcs_calc_temp1[19]_i_51_n_0\,
      DI(0) => \ip_hcs_calc_temp1[19]_i_52_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[19]_i_18_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[19]_i_18_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[19]_i_18_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[19]_i_18_n_7\,
      S(3) => \ip_hcs_calc_temp1[19]_i_53_n_0\,
      S(2) => \ip_hcs_calc_temp1[19]_i_54_n_0\,
      S(1) => \ip_hcs_calc_temp1[19]_i_55_n_0\,
      S(0) => \ip_hcs_calc_temp1[19]_i_56_n_0\
    );
\ip_hcs_calc_temp1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[3]_i_1_n_6\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[1]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[23]_i_2_n_7\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[20]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[23]_i_2_n_6\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[21]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[23]_i_2_n_5\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[22]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[23]_i_2_n_4\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[23]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[23]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[19]_i_1_n_0\,
      CO(3) => \NLW_ip_hcs_calc_temp1_reg[23]_i_2_CO_UNCONNECTED\(3),
      CO(2) => \ip_hcs_calc_temp1_reg[23]_i_2_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[23]_i_2_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[23]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \ip_hcs_calc_temp1_reg[23]_i_2_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[23]_i_2_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[23]_i_2_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[23]_i_2_n_7\,
      S(3) => \ip_hcs_calc_temp1_reg[23]_i_3_n_4\,
      S(2) => \ip_hcs_calc_temp1_reg[23]_i_3_n_5\,
      S(1) => \ip_hcs_calc_temp1_reg[23]_i_3_n_6\,
      S(0) => \ip_hcs_calc_temp1_reg[23]_i_3_n_7\
    );
\ip_hcs_calc_temp1_reg[23]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[23]_i_4_n_0\,
      CO(3) => \NLW_ip_hcs_calc_temp1_reg[23]_i_3_CO_UNCONNECTED\(3),
      CO(2) => \ip_hcs_calc_temp1_reg[23]_i_3_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[23]_i_3_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[23]_i_3_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => \ip_hcs_calc_temp1[23]_i_5_n_0\,
      DI(1) => \ip_hcs_calc_temp1[23]_i_6_n_0\,
      DI(0) => \ip_hcs_calc_temp1[23]_i_7_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[23]_i_3_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[23]_i_3_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[23]_i_3_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[23]_i_3_n_7\,
      S(3) => \ip_hcs_calc_temp1[23]_i_8_n_0\,
      S(2) => \ip_hcs_calc_temp1[23]_i_9_n_0\,
      S(1) => \ip_hcs_calc_temp1[23]_i_10_n_0\,
      S(0) => \ip_hcs_calc_temp1[23]_i_11_n_0\
    );
\ip_hcs_calc_temp1_reg[23]_i_4\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[19]_i_18_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[23]_i_4_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[23]_i_4_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[23]_i_4_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[23]_i_4_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[23]_i_12_n_0\,
      DI(2) => \ip_hcs_calc_temp1[23]_i_13_n_0\,
      DI(1) => \ip_hcs_calc_temp1[23]_i_14_n_0\,
      DI(0) => \ip_hcs_calc_temp1[23]_i_15_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[23]_i_4_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[23]_i_4_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[23]_i_4_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[23]_i_4_n_7\,
      S(3) => \ip_hcs_calc_temp1[23]_i_16_n_0\,
      S(2) => \ip_hcs_calc_temp1[23]_i_17_n_0\,
      S(1) => \ip_hcs_calc_temp1[23]_i_18_n_0\,
      S(0) => \ip_hcs_calc_temp1[23]_i_19_n_0\
    );
\ip_hcs_calc_temp1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[3]_i_1_n_5\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[2]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[3]_i_1_n_4\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[3]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[3]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \ip_hcs_calc_temp1_reg[3]_i_1_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[3]_i_1_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[3]_i_1_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[3]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[3]_i_2_n_0\,
      DI(2) => \ip_hcs_calc_temp1[3]_i_3_n_0\,
      DI(1) => \ip_hcs_calc_temp1[3]_i_4_n_0\,
      DI(0) => \ip_hcs_calc_temp1_reg[3]_i_5_n_7\,
      O(3) => \ip_hcs_calc_temp1_reg[3]_i_1_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[3]_i_1_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[3]_i_1_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[3]_i_1_n_7\,
      S(3) => \ip_hcs_calc_temp1[3]_i_6_n_0\,
      S(2) => \ip_hcs_calc_temp1[3]_i_7_n_0\,
      S(1) => \ip_hcs_calc_temp1[3]_i_8_n_0\,
      S(0) => \ip_hcs_calc_temp1[3]_i_9_n_0\
    );
\ip_hcs_calc_temp1_reg[3]_i_5\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \ip_hcs_calc_temp1_reg[3]_i_5_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[3]_i_5_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[3]_i_5_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[3]_i_5_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[3]_i_11_n_0\,
      DI(2) => \ip_hcs_calc_temp1[3]_i_12_n_0\,
      DI(1) => \ip_hcs_calc_temp1[3]_i_13_n_0\,
      DI(0) => '0',
      O(3) => \ip_hcs_calc_temp1_reg[3]_i_5_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[3]_i_5_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[3]_i_5_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[3]_i_5_n_7\,
      S(3) => \ip_hcs_calc_temp1[3]_i_14_n_0\,
      S(2) => \ip_hcs_calc_temp1[3]_i_15_n_0\,
      S(1) => \ip_hcs_calc_temp1[3]_i_16_n_0\,
      S(0) => \ip_hcs_calc_temp1[3]_i_17_n_0\
    );
\ip_hcs_calc_temp1_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[7]_i_1_n_7\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[4]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[7]_i_1_n_6\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[5]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[7]_i_1_n_5\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[6]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[7]_i_1_n_4\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[7]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[7]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp1_reg[3]_i_1_n_0\,
      CO(3) => \ip_hcs_calc_temp1_reg[7]_i_1_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[7]_i_1_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[7]_i_1_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[7]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[7]_i_2_n_0\,
      DI(2) => \ip_hcs_calc_temp1[7]_i_3_n_0\,
      DI(1) => \ip_hcs_calc_temp1[7]_i_4_n_0\,
      DI(0) => \ip_hcs_calc_temp1[7]_i_5_n_0\,
      O(3) => \ip_hcs_calc_temp1_reg[7]_i_1_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[7]_i_1_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[7]_i_1_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[7]_i_1_n_7\,
      S(3) => \ip_hcs_calc_temp1[7]_i_6_n_0\,
      S(2) => \ip_hcs_calc_temp1[7]_i_7_n_0\,
      S(1) => \ip_hcs_calc_temp1[7]_i_8_n_0\,
      S(0) => \ip_hcs_calc_temp1[7]_i_9_n_0\
    );
\ip_hcs_calc_temp1_reg[7]_i_12\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \ip_hcs_calc_temp1_reg[7]_i_12_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[7]_i_12_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[7]_i_12_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[7]_i_12_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[7]_i_21_n_0\,
      DI(2) => \ip_hcs_calc_temp1[7]_i_22_n_0\,
      DI(1) => \ip_hcs_calc_temp1[7]_i_23_n_0\,
      DI(0) => '0',
      O(3) => \ip_hcs_calc_temp1_reg[7]_i_12_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[7]_i_12_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[7]_i_12_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[7]_i_12_n_7\,
      S(3) => \ip_hcs_calc_temp1[7]_i_24_n_0\,
      S(2) => \ip_hcs_calc_temp1[7]_i_25_n_0\,
      S(1) => \ip_hcs_calc_temp1[7]_i_26_n_0\,
      S(0) => \ip_hcs_calc_temp1[7]_i_27_n_0\
    );
\ip_hcs_calc_temp1_reg[7]_i_13\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \ip_hcs_calc_temp1_reg[7]_i_13_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[7]_i_13_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[7]_i_13_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[7]_i_13_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[7]_i_28_n_0\,
      DI(2) => \ip_hcs_calc_temp1[7]_i_29_n_0\,
      DI(1) => \ip_hcs_calc_temp1[7]_i_30_n_0\,
      DI(0) => '0',
      O(3) => \ip_hcs_calc_temp1_reg[7]_i_13_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[7]_i_13_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[7]_i_13_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[7]_i_13_n_7\,
      S(3) => \ip_hcs_calc_temp1[7]_i_31_n_0\,
      S(2) => \ip_hcs_calc_temp1[7]_i_32_n_0\,
      S(1) => \ip_hcs_calc_temp1[7]_i_33_n_0\,
      S(0) => \ip_hcs_calc_temp1[7]_i_34_n_0\
    );
\ip_hcs_calc_temp1_reg[7]_i_14\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \ip_hcs_calc_temp1_reg[7]_i_14_n_0\,
      CO(2) => \ip_hcs_calc_temp1_reg[7]_i_14_n_1\,
      CO(1) => \ip_hcs_calc_temp1_reg[7]_i_14_n_2\,
      CO(0) => \ip_hcs_calc_temp1_reg[7]_i_14_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp1[7]_i_35_n_0\,
      DI(2) => \ip_hcs_calc_temp1[7]_i_36_n_0\,
      DI(1) => \ip_hcs_calc_temp1[7]_i_37_n_0\,
      DI(0) => '0',
      O(3) => \ip_hcs_calc_temp1_reg[7]_i_14_n_4\,
      O(2) => \ip_hcs_calc_temp1_reg[7]_i_14_n_5\,
      O(1) => \ip_hcs_calc_temp1_reg[7]_i_14_n_6\,
      O(0) => \ip_hcs_calc_temp1_reg[7]_i_14_n_7\,
      S(3) => \ip_hcs_calc_temp1[7]_i_38_n_0\,
      S(2) => \ip_hcs_calc_temp1[7]_i_39_n_0\,
      S(1) => \ip_hcs_calc_temp1[7]_i_40_n_0\,
      S(0) => \ip_hcs_calc_temp1[7]_i_41_n_0\
    );
\ip_hcs_calc_temp1_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[11]_i_1_n_7\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[8]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp1_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp1[23]_i_1_n_0\,
      D => \ip_hcs_calc_temp1_reg[11]_i_1_n_6\,
      Q => \ip_hcs_calc_temp1_reg_n_0_[9]\,
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(0),
      O => \not\(0)
    );
\ip_hcs_calc_temp2[10]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(10),
      O => \not\(10)
    );
\ip_hcs_calc_temp2[11]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(11),
      O => \not\(11)
    );
\ip_hcs_calc_temp2[11]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E81717E8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[23]\,
      I1 => \ip_hcs_calc_temp2__0\(7),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[7]\,
      I3 => \ip_hcs_calc_temp2__0\(8),
      I4 => \ip_hcs_calc_temp1_reg_n_0_[8]\,
      O => \ip_hcs_calc_temp2[11]_i_10_n_0\
    );
\ip_hcs_calc_temp2[11]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[10]\,
      I1 => \ip_hcs_calc_temp2__0\(10),
      O => \ip_hcs_calc_temp2[11]_i_3_n_0\
    );
\ip_hcs_calc_temp2[11]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[9]\,
      I1 => \ip_hcs_calc_temp2__0\(9),
      O => \ip_hcs_calc_temp2[11]_i_4_n_0\
    );
\ip_hcs_calc_temp2[11]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[8]\,
      I1 => \ip_hcs_calc_temp2__0\(8),
      O => \ip_hcs_calc_temp2[11]_i_5_n_0\
    );
\ip_hcs_calc_temp2[11]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[7]\,
      I1 => \ip_hcs_calc_temp2__0\(7),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[23]\,
      O => \ip_hcs_calc_temp2[11]_i_6_n_0\
    );
\ip_hcs_calc_temp2[11]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ip_hcs_calc_temp2__0\(10),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[10]\,
      I2 => \ip_hcs_calc_temp2__0\(11),
      I3 => \ip_hcs_calc_temp1_reg_n_0_[11]\,
      O => \ip_hcs_calc_temp2[11]_i_7_n_0\
    );
\ip_hcs_calc_temp2[11]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ip_hcs_calc_temp2__0\(9),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[9]\,
      I2 => \ip_hcs_calc_temp2__0\(10),
      I3 => \ip_hcs_calc_temp1_reg_n_0_[10]\,
      O => \ip_hcs_calc_temp2[11]_i_8_n_0\
    );
\ip_hcs_calc_temp2[11]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ip_hcs_calc_temp2__0\(8),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[8]\,
      I2 => \ip_hcs_calc_temp2__0\(9),
      I3 => \ip_hcs_calc_temp1_reg_n_0_[9]\,
      O => \ip_hcs_calc_temp2[11]_i_9_n_0\
    );
\ip_hcs_calc_temp2[12]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(12),
      O => \not\(12)
    );
\ip_hcs_calc_temp2[13]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(13),
      O => \not\(13)
    );
\ip_hcs_calc_temp2[14]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(14),
      O => \not\(14)
    );
\ip_hcs_calc_temp2[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => ip_hcs_calc_temp2,
      I1 => ip_hcs_done,
      O => \ip_hcs_calc_temp2[15]_i_1_n_0\
    );
\ip_hcs_calc_temp2[15]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ip_hcs_calc_temp2__0\(11),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[11]\,
      I2 => \ip_hcs_calc_temp2__0\(12),
      I3 => \ip_hcs_calc_temp1_reg_n_0_[12]\,
      O => \ip_hcs_calc_temp2[15]_i_10_n_0\
    );
\ip_hcs_calc_temp2[15]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(15),
      O => \not\(15)
    );
\ip_hcs_calc_temp2[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[13]\,
      I1 => \ip_hcs_calc_temp2__0\(13),
      O => \ip_hcs_calc_temp2[15]_i_4_n_0\
    );
\ip_hcs_calc_temp2[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[12]\,
      I1 => \ip_hcs_calc_temp2__0\(12),
      O => \ip_hcs_calc_temp2[15]_i_5_n_0\
    );
\ip_hcs_calc_temp2[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[11]\,
      I1 => \ip_hcs_calc_temp2__0\(11),
      O => \ip_hcs_calc_temp2[15]_i_6_n_0\
    );
\ip_hcs_calc_temp2[15]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ip_hcs_calc_temp2__0\(14),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[14]\,
      I2 => \ip_hcs_calc_temp2__0\(15),
      I3 => \ip_hcs_calc_temp1_reg_n_0_[15]\,
      O => \ip_hcs_calc_temp2[15]_i_7_n_0\
    );
\ip_hcs_calc_temp2[15]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ip_hcs_calc_temp2__0\(13),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[13]\,
      I2 => \ip_hcs_calc_temp2__0\(14),
      I3 => \ip_hcs_calc_temp1_reg_n_0_[14]\,
      O => \ip_hcs_calc_temp2[15]_i_8_n_0\
    );
\ip_hcs_calc_temp2[15]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \ip_hcs_calc_temp2__0\(12),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[12]\,
      I2 => \ip_hcs_calc_temp2__0\(13),
      I3 => \ip_hcs_calc_temp1_reg_n_0_[13]\,
      O => \ip_hcs_calc_temp2[15]_i_9_n_0\
    );
\ip_hcs_calc_temp2[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(1),
      O => \not\(1)
    );
\ip_hcs_calc_temp2[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(2),
      O => \not\(2)
    );
\ip_hcs_calc_temp2[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(3),
      O => \not\(3)
    );
\ip_hcs_calc_temp2[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[2]\,
      I1 => \ip_hcs_calc_temp2__0\(2),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[18]\,
      O => \ip_hcs_calc_temp2[3]_i_3_n_0\
    );
\ip_hcs_calc_temp2[3]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[1]\,
      I1 => \ip_hcs_calc_temp2__0\(1),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[17]\,
      O => \ip_hcs_calc_temp2[3]_i_4_n_0\
    );
\ip_hcs_calc_temp2[3]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ip_hcs_calc_temp2__0\(0),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[0]\,
      I2 => \ip_hcs_calc_temp1_reg_n_0_[16]\,
      O => \ip_hcs_calc_temp2[3]_i_5_n_0\
    );
\ip_hcs_calc_temp2[3]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[3]\,
      I1 => \ip_hcs_calc_temp2__0\(3),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[19]\,
      I3 => \ip_hcs_calc_temp2[3]_i_3_n_0\,
      O => \ip_hcs_calc_temp2[3]_i_6_n_0\
    );
\ip_hcs_calc_temp2[3]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[2]\,
      I1 => \ip_hcs_calc_temp2__0\(2),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[18]\,
      I3 => \ip_hcs_calc_temp2[3]_i_4_n_0\,
      O => \ip_hcs_calc_temp2[3]_i_7_n_0\
    );
\ip_hcs_calc_temp2[3]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[1]\,
      I1 => \ip_hcs_calc_temp2__0\(1),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[17]\,
      I3 => \ip_hcs_calc_temp2[3]_i_5_n_0\,
      O => \ip_hcs_calc_temp2[3]_i_8_n_0\
    );
\ip_hcs_calc_temp2[3]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_hcs_calc_temp2__0\(0),
      I1 => \ip_hcs_calc_temp1_reg_n_0_[0]\,
      I2 => \ip_hcs_calc_temp1_reg_n_0_[16]\,
      O => \ip_hcs_calc_temp2[3]_i_9_n_0\
    );
\ip_hcs_calc_temp2[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(4),
      O => \not\(4)
    );
\ip_hcs_calc_temp2[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(5),
      O => \not\(5)
    );
\ip_hcs_calc_temp2[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(6),
      O => \not\(6)
    );
\ip_hcs_calc_temp2[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(7),
      O => \not\(7)
    );
\ip_hcs_calc_temp2[7]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[4]\,
      I1 => \ip_hcs_calc_temp2__0\(4),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[20]\,
      I3 => \ip_hcs_calc_temp2[7]_i_6_n_0\,
      O => \ip_hcs_calc_temp2[7]_i_10_n_0\
    );
\ip_hcs_calc_temp2[7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[6]\,
      I1 => \ip_hcs_calc_temp2__0\(6),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[22]\,
      O => \ip_hcs_calc_temp2[7]_i_3_n_0\
    );
\ip_hcs_calc_temp2[7]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[5]\,
      I1 => \ip_hcs_calc_temp2__0\(5),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[21]\,
      O => \ip_hcs_calc_temp2[7]_i_4_n_0\
    );
\ip_hcs_calc_temp2[7]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[4]\,
      I1 => \ip_hcs_calc_temp2__0\(4),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[20]\,
      O => \ip_hcs_calc_temp2[7]_i_5_n_0\
    );
\ip_hcs_calc_temp2[7]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[3]\,
      I1 => \ip_hcs_calc_temp2__0\(3),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[19]\,
      O => \ip_hcs_calc_temp2[7]_i_6_n_0\
    );
\ip_hcs_calc_temp2[7]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ip_hcs_calc_temp2[7]_i_3_n_0\,
      I1 => \ip_hcs_calc_temp1_reg_n_0_[7]\,
      I2 => \ip_hcs_calc_temp2__0\(7),
      I3 => \ip_hcs_calc_temp1_reg_n_0_[23]\,
      O => \ip_hcs_calc_temp2[7]_i_7_n_0\
    );
\ip_hcs_calc_temp2[7]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[6]\,
      I1 => \ip_hcs_calc_temp2__0\(6),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[22]\,
      I3 => \ip_hcs_calc_temp2[7]_i_4_n_0\,
      O => \ip_hcs_calc_temp2[7]_i_8_n_0\
    );
\ip_hcs_calc_temp2[7]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \ip_hcs_calc_temp1_reg_n_0_[5]\,
      I1 => \ip_hcs_calc_temp2__0\(5),
      I2 => \ip_hcs_calc_temp1_reg_n_0_[21]\,
      I3 => \ip_hcs_calc_temp2[7]_i_5_n_0\,
      O => \ip_hcs_calc_temp2[7]_i_9_n_0\
    );
\ip_hcs_calc_temp2[8]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(8),
      O => \not\(8)
    );
\ip_hcs_calc_temp2[9]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(9),
      O => \not\(9)
    );
\ip_hcs_calc_temp2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(0),
      Q => \ip_hcs_calc_temp2__0\(0),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(10),
      Q => \ip_hcs_calc_temp2__0\(10),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(11),
      Q => \ip_hcs_calc_temp2__0\(11),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[11]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp2_reg[7]_i_2_n_0\,
      CO(3) => \ip_hcs_calc_temp2_reg[11]_i_2_n_0\,
      CO(2) => \ip_hcs_calc_temp2_reg[11]_i_2_n_1\,
      CO(1) => \ip_hcs_calc_temp2_reg[11]_i_2_n_2\,
      CO(0) => \ip_hcs_calc_temp2_reg[11]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp2[11]_i_3_n_0\,
      DI(2) => \ip_hcs_calc_temp2[11]_i_4_n_0\,
      DI(1) => \ip_hcs_calc_temp2[11]_i_5_n_0\,
      DI(0) => \ip_hcs_calc_temp2[11]_i_6_n_0\,
      O(3 downto 0) => L(11 downto 8),
      S(3) => \ip_hcs_calc_temp2[11]_i_7_n_0\,
      S(2) => \ip_hcs_calc_temp2[11]_i_8_n_0\,
      S(1) => \ip_hcs_calc_temp2[11]_i_9_n_0\,
      S(0) => \ip_hcs_calc_temp2[11]_i_10_n_0\
    );
\ip_hcs_calc_temp2_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(12),
      Q => \ip_hcs_calc_temp2__0\(12),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(13),
      Q => \ip_hcs_calc_temp2__0\(13),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(14),
      Q => \ip_hcs_calc_temp2__0\(14),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(15),
      Q => \ip_hcs_calc_temp2__0\(15),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[15]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp2_reg[11]_i_2_n_0\,
      CO(3) => \NLW_ip_hcs_calc_temp2_reg[15]_i_3_CO_UNCONNECTED\(3),
      CO(2) => \ip_hcs_calc_temp2_reg[15]_i_3_n_1\,
      CO(1) => \ip_hcs_calc_temp2_reg[15]_i_3_n_2\,
      CO(0) => \ip_hcs_calc_temp2_reg[15]_i_3_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => \ip_hcs_calc_temp2[15]_i_4_n_0\,
      DI(1) => \ip_hcs_calc_temp2[15]_i_5_n_0\,
      DI(0) => \ip_hcs_calc_temp2[15]_i_6_n_0\,
      O(3 downto 0) => L(15 downto 12),
      S(3) => \ip_hcs_calc_temp2[15]_i_7_n_0\,
      S(2) => \ip_hcs_calc_temp2[15]_i_8_n_0\,
      S(1) => \ip_hcs_calc_temp2[15]_i_9_n_0\,
      S(0) => \ip_hcs_calc_temp2[15]_i_10_n_0\
    );
\ip_hcs_calc_temp2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(1),
      Q => \ip_hcs_calc_temp2__0\(1),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(2),
      Q => \ip_hcs_calc_temp2__0\(2),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(3),
      Q => \ip_hcs_calc_temp2__0\(3),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[3]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \ip_hcs_calc_temp2_reg[3]_i_2_n_0\,
      CO(2) => \ip_hcs_calc_temp2_reg[3]_i_2_n_1\,
      CO(1) => \ip_hcs_calc_temp2_reg[3]_i_2_n_2\,
      CO(0) => \ip_hcs_calc_temp2_reg[3]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp2[3]_i_3_n_0\,
      DI(2) => \ip_hcs_calc_temp2[3]_i_4_n_0\,
      DI(1) => \ip_hcs_calc_temp2[3]_i_5_n_0\,
      DI(0) => '0',
      O(3 downto 0) => L(3 downto 0),
      S(3) => \ip_hcs_calc_temp2[3]_i_6_n_0\,
      S(2) => \ip_hcs_calc_temp2[3]_i_7_n_0\,
      S(1) => \ip_hcs_calc_temp2[3]_i_8_n_0\,
      S(0) => \ip_hcs_calc_temp2[3]_i_9_n_0\
    );
\ip_hcs_calc_temp2_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(4),
      Q => \ip_hcs_calc_temp2__0\(4),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(5),
      Q => \ip_hcs_calc_temp2__0\(5),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(6),
      Q => \ip_hcs_calc_temp2__0\(6),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(7),
      Q => \ip_hcs_calc_temp2__0\(7),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[7]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_hcs_calc_temp2_reg[3]_i_2_n_0\,
      CO(3) => \ip_hcs_calc_temp2_reg[7]_i_2_n_0\,
      CO(2) => \ip_hcs_calc_temp2_reg[7]_i_2_n_1\,
      CO(1) => \ip_hcs_calc_temp2_reg[7]_i_2_n_2\,
      CO(0) => \ip_hcs_calc_temp2_reg[7]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => \ip_hcs_calc_temp2[7]_i_3_n_0\,
      DI(2) => \ip_hcs_calc_temp2[7]_i_4_n_0\,
      DI(1) => \ip_hcs_calc_temp2[7]_i_5_n_0\,
      DI(0) => \ip_hcs_calc_temp2[7]_i_6_n_0\,
      O(3 downto 0) => L(7 downto 4),
      S(3) => \ip_hcs_calc_temp2[7]_i_7_n_0\,
      S(2) => \ip_hcs_calc_temp2[7]_i_8_n_0\,
      S(1) => \ip_hcs_calc_temp2[7]_i_9_n_0\,
      S(0) => \ip_hcs_calc_temp2[7]_i_10_n_0\
    );
\ip_hcs_calc_temp2_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(8),
      Q => \ip_hcs_calc_temp2__0\(8),
      R => ip_hcs_calc_temp1
    );
\ip_hcs_calc_temp2_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \ip_hcs_calc_temp2[15]_i_1_n_0\,
      D => \not\(9),
      Q => \ip_hcs_calc_temp2__0\(9),
      R => ip_hcs_calc_temp1
    );
ip_hcs_done_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E00000"
    )
        port map (
      I0 => ip_hcs_calc,
      I1 => ip_hcs_done,
      I2 => \byte_read_done_reg_n_0_[9]\,
      I3 => arp_request_expected,
      I4 => eth_protocol_expected,
      O => ip_hcs_done_i_1_n_0
    );
ip_hcs_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => ip_hcs_done_i_1_n_0,
      Q => ip_hcs_done,
      R => '0'
    );
\ip_header_checksum[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \byte_read_done_reg_n_0_[5]\,
      I1 => arp_request_expected,
      I2 => eth_protocol_expected,
      O => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(0),
      Q => ip_header_checksum(0),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(10),
      Q => ip_header_checksum(10),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(11),
      Q => ip_header_checksum(11),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(12),
      Q => ip_header_checksum(12),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(13),
      Q => ip_header_checksum(13),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(14),
      Q => ip_header_checksum(14),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(15),
      Q => ip_header_checksum(15),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(1),
      Q => ip_header_checksum(1),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(2),
      Q => ip_header_checksum(2),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(3),
      Q => ip_header_checksum(3),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(4),
      Q => ip_header_checksum(4),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(5),
      Q => ip_header_checksum(5),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(6),
      Q => ip_header_checksum(6),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(7),
      Q => ip_header_checksum(7),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(8),
      Q => ip_header_checksum(8),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_checksum_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes05(9),
      Q => ip_header_checksum(9),
      R => \ip_header_checksum[15]_i_1_n_0\
    );
\ip_header_length[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \byte_read_done_reg_n_0_[0]\,
      I1 => arp_request_expected,
      I2 => eth_protocol_expected,
      O => RSTA
    );
\ip_header_length_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => data_counter_max2(0),
      Q => \ip_header_length_reg_n_0_[0]\,
      R => RSTA
    );
\ip_header_length_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => data_counter_max2(1),
      Q => \ip_header_length_reg_n_0_[1]\,
      R => RSTA
    );
\ip_header_length_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => data_counter_max2(2),
      Q => \ip_header_length_reg_n_0_[2]\,
      R => RSTA
    );
\ip_header_length_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => data_counter_max2(3),
      Q => \ip_header_length_reg_n_0_[3]\,
      R => RSTA
    );
\ip_header_options[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01FFFFFF01000000"
    )
        port map (
      I0 => \bit_count_reg[0]_rep_n_0\,
      I1 => \ip_header_options[7]_i_3_n_0\,
      I2 => \ip_header_options[6]_i_2_n_0\,
      I3 => \ip_header_options[5]_i_2_n_0\,
      I4 => \ip_header_options[3]_i_2_n_0\,
      I5 => \ip_header_options_reg_n_0_[0]\,
      O => \ip_header_options[0]_i_1_n_0\
    );
\ip_header_options[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01FFFFFF01000000"
    )
        port map (
      I0 => \bit_count_reg[0]_rep_n_0\,
      I1 => \ip_header_options[7]_i_3_n_0\,
      I2 => \ip_header_options[7]_i_2_n_0\,
      I3 => \ip_header_options[5]_i_2_n_0\,
      I4 => \ip_header_options[3]_i_2_n_0\,
      I5 => \ip_header_options_reg_n_0_[1]\,
      O => \ip_header_options[1]_i_1_n_0\
    );
\ip_header_options[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => \ip_header_options[6]_i_2_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => \ip_header_options[7]_i_3_n_0\,
      I3 => \ip_header_options[7]_i_5_n_0\,
      I4 => \ip_header_options[3]_i_2_n_0\,
      I5 => \ip_header_options_reg_n_0_[2]\,
      O => \ip_header_options[2]_i_1_n_0\
    );
\ip_header_options[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => \ip_header_options[7]_i_2_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => \ip_header_options[7]_i_3_n_0\,
      I3 => \ip_header_options[7]_i_5_n_0\,
      I4 => \ip_header_options[3]_i_2_n_0\,
      I5 => \ip_header_options_reg_n_0_[3]\,
      O => \ip_header_options[3]_i_1_n_0\
    );
\ip_header_options[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \byte_count_extra_reg_n_0_[0]\,
      I1 => \byte_count_extra_reg_n_0_[1]\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      O => \ip_header_options[3]_i_2_n_0\
    );
\ip_header_options[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01FFFFFF01000000"
    )
        port map (
      I0 => \bit_count_reg[0]_rep_n_0\,
      I1 => \ip_header_options[7]_i_3_n_0\,
      I2 => \ip_header_options[6]_i_2_n_0\,
      I3 => \ip_header_options[7]_i_4_n_0\,
      I4 => \ip_header_options[5]_i_2_n_0\,
      I5 => \ip_header_options_reg_n_0_[4]\,
      O => \ip_header_options[4]_i_1_n_0\
    );
\ip_header_options[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"01FFFFFF01000000"
    )
        port map (
      I0 => \bit_count_reg[0]_rep_n_0\,
      I1 => \ip_header_options[7]_i_3_n_0\,
      I2 => \ip_header_options[7]_i_2_n_0\,
      I3 => \ip_header_options[7]_i_4_n_0\,
      I4 => \ip_header_options[5]_i_2_n_0\,
      I5 => \ip_header_options_reg_n_0_[5]\,
      O => \ip_header_options[5]_i_1_n_0\
    );
\ip_header_options[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \state[2]_i_5__0_n_0\,
      I3 => \ip_header_options_reg[7]_i_6_n_3\,
      I4 => \ip_header_options[7]_i_8_n_0\,
      I5 => \bit_count_reg[0]_rep_n_0\,
      O => \ip_header_options[5]_i_2_n_0\
    );
\ip_header_options[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => \ip_header_options[6]_i_2_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => \ip_header_options[7]_i_3_n_0\,
      I3 => \ip_header_options[7]_i_4_n_0\,
      I4 => \ip_header_options[7]_i_5_n_0\,
      I5 => \ip_header_options_reg_n_0_[6]\,
      O => \ip_header_options[6]_i_1_n_0\
    );
\ip_header_options[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \ip_header_options_reg[7]_i_6_n_3\,
      O => \ip_header_options[6]_i_2_n_0\
    );
\ip_header_options[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"04FFFFFF04000000"
    )
        port map (
      I0 => \ip_header_options[7]_i_2_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => \ip_header_options[7]_i_3_n_0\,
      I3 => \ip_header_options[7]_i_4_n_0\,
      I4 => \ip_header_options[7]_i_5_n_0\,
      I5 => \ip_header_options_reg_n_0_[7]\,
      O => \ip_header_options[7]_i_1_n_0\
    );
\ip_header_options[7]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => ip_options_count_max(4),
      I1 => \byte_count_extra_reg_n_0_[4]\,
      O => \ip_header_options[7]_i_10_n_0\
    );
\ip_header_options[7]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => ip_options_count_max(3),
      I1 => \byte_count_extra_reg_n_0_[3]\,
      O => \ip_header_options[7]_i_11_n_0\
    );
\ip_header_options[7]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => ip_options_count_max(2),
      I1 => \byte_count_extra_reg_n_0_[2]\,
      O => \ip_header_options[7]_i_12_n_0\
    );
\ip_header_options[7]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => ip_header_options2(5),
      I1 => eth_rstn,
      O => \ip_header_options[7]_i_13_n_0\
    );
\ip_header_options[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \ip_header_options_reg[7]_i_6_n_3\,
      O => \ip_header_options[7]_i_2_n_0\
    );
\ip_header_options[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFEB"
    )
        port map (
      I0 => ip_header_options2(5),
      I1 => \byte_count_extra_reg_n_0_[2]\,
      I2 => ip_options_count_max(2),
      I3 => ip_header_options2(3),
      I4 => ip_header_options2(4),
      O => \ip_header_options[7]_i_3_n_0\
    );
\ip_header_options[7]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \byte_count_extra_reg_n_0_[0]\,
      I1 => \byte_count_extra_reg_n_0_[1]\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      O => \ip_header_options[7]_i_4_n_0\
    );
\ip_header_options[7]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \state_reg[1]_rep__0_n_0\,
      I2 => \state[2]_i_5__0_n_0\,
      I3 => \ip_header_options_reg[7]_i_6_n_3\,
      I4 => \bit_count_reg[0]_rep_n_0\,
      I5 => \ip_header_options[7]_i_8_n_0\,
      O => \ip_header_options[7]_i_5_n_0\
    );
\ip_header_options[7]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFF9FFFF"
    )
        port map (
      I0 => \byte_count_extra_reg_n_0_[2]\,
      I1 => ip_options_count_max(2),
      I2 => ip_header_options2(3),
      I3 => ip_header_options2(4),
      I4 => bit_count2,
      I5 => \ip_header_options[7]_i_13_n_0\,
      O => \ip_header_options[7]_i_8_n_0\
    );
\ip_header_options[7]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => ip_options_count_max(5),
      I1 => \byte_count_extra_reg_n_0_[5]\,
      O => \ip_header_options[7]_i_9_n_0\
    );
\ip_header_options_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \ip_header_options[0]_i_1_n_0\,
      Q => \ip_header_options_reg_n_0_[0]\,
      R => '0'
    );
\ip_header_options_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \ip_header_options[1]_i_1_n_0\,
      Q => \ip_header_options_reg_n_0_[1]\,
      R => '0'
    );
\ip_header_options_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \ip_header_options[2]_i_1_n_0\,
      Q => \ip_header_options_reg_n_0_[2]\,
      R => '0'
    );
\ip_header_options_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \ip_header_options[3]_i_1_n_0\,
      Q => \ip_header_options_reg_n_0_[3]\,
      R => '0'
    );
\ip_header_options_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \ip_header_options[4]_i_1_n_0\,
      Q => \ip_header_options_reg_n_0_[4]\,
      R => '0'
    );
\ip_header_options_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \ip_header_options[5]_i_1_n_0\,
      Q => \ip_header_options_reg_n_0_[5]\,
      R => '0'
    );
\ip_header_options_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \ip_header_options[6]_i_1_n_0\,
      Q => \ip_header_options_reg_n_0_[6]\,
      R => '0'
    );
\ip_header_options_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \ip_header_options[7]_i_1_n_0\,
      Q => \ip_header_options_reg_n_0_[7]\,
      R => '0'
    );
\ip_header_options_reg[7]_i_6\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_header_options_reg[7]_i_7_n_0\,
      CO(3 downto 1) => \NLW_ip_header_options_reg[7]_i_6_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \ip_header_options_reg[7]_i_6_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_ip_header_options_reg[7]_i_6_O_UNCONNECTED\(3 downto 0),
      S(3 downto 0) => B"0001"
    );
\ip_header_options_reg[7]_i_7\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \ip_header_options_reg[7]_i_7_n_0\,
      CO(2) => \ip_header_options_reg[7]_i_7_n_1\,
      CO(1) => \ip_header_options_reg[7]_i_7_n_2\,
      CO(0) => \ip_header_options_reg[7]_i_7_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => ip_options_count_max(5 downto 2),
      O(3 downto 1) => ip_header_options2(5 downto 3),
      O(0) => \NLW_ip_header_options_reg[7]_i_7_O_UNCONNECTED\(0),
      S(3) => \ip_header_options[7]_i_9_n_0\,
      S(2) => \ip_header_options[7]_i_10_n_0\,
      S(1) => \ip_header_options[7]_i_11_n_0\,
      S(0) => \ip_header_options[7]_i_12_n_0\
    );
\ip_options_count_max[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \ip_header_length_reg_n_0_[0]\,
      O => ip_options_count_max0(2)
    );
\ip_options_count_max[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \ip_header_length_reg_n_0_[1]\,
      I1 => \ip_header_length_reg_n_0_[0]\,
      O => \ip_options_count_max[3]_i_1_n_0\
    );
\ip_options_count_max[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"56"
    )
        port map (
      I0 => \ip_header_length_reg_n_0_[2]\,
      I1 => \ip_header_length_reg_n_0_[1]\,
      I2 => \ip_header_length_reg_n_0_[0]\,
      O => ip_options_count_max0(4)
    );
\ip_options_count_max[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFDFDFFFDFFFDFFF"
    )
        port map (
      I0 => \byte_read_done_reg_n_0_[0]\,
      I1 => arp_request_expected,
      I2 => eth_protocol_expected,
      I3 => \ip_header_length_reg_n_0_[3]\,
      I4 => \ip_header_length_reg_n_0_[2]\,
      I5 => \ip_header_length_reg_n_0_[1]\,
      O => RSTP
    );
\ip_options_count_max[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A955"
    )
        port map (
      I0 => \ip_header_length_reg_n_0_[3]\,
      I1 => \ip_header_length_reg_n_0_[1]\,
      I2 => \ip_header_length_reg_n_0_[0]\,
      I3 => \ip_header_length_reg_n_0_[2]\,
      O => \ip_options_count_max[5]_i_2_n_0\
    );
\ip_options_count_max_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => ip_options_count_max0(2),
      Q => ip_options_count_max(2),
      R => RSTP
    );
\ip_options_count_max_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \ip_options_count_max[3]_i_1_n_0\,
      Q => ip_options_count_max(3),
      R => RSTP
    );
\ip_options_count_max_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => ip_options_count_max0(4),
      Q => ip_options_count_max(4),
      R => RSTP
    );
\ip_options_count_max_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \ip_options_count_max[5]_i_2_n_0\,
      Q => ip_options_count_max(5),
      R => RSTP
    );
\ip_total_length_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(10),
      Q => ip_total_length(10),
      R => data_counter_max
    );
\ip_total_length_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(11),
      Q => ip_total_length(11),
      R => data_counter_max
    );
\ip_total_length_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(12),
      Q => ip_total_length(12),
      R => data_counter_max
    );
\ip_total_length_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(13),
      Q => ip_total_length(13),
      R => data_counter_max
    );
\ip_total_length_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(14),
      Q => ip_total_length(14),
      R => data_counter_max
    );
\ip_total_length_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(15),
      Q => ip_total_length(15),
      R => data_counter_max
    );
\ip_total_length_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(2),
      Q => ip_total_length(2),
      R => data_counter_max
    );
\ip_total_length_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(3),
      Q => ip_total_length(3),
      R => data_counter_max
    );
\ip_total_length_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(4),
      Q => ip_total_length(4),
      R => data_counter_max
    );
\ip_total_length_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(5),
      Q => ip_total_length(5),
      R => data_counter_max
    );
\ip_total_length_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(6),
      Q => ip_total_length(6),
      R => data_counter_max
    );
\ip_total_length_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(7),
      Q => ip_total_length(7),
      R => data_counter_max
    );
\ip_total_length_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(8),
      Q => ip_total_length(8),
      R => data_counter_max
    );
\ip_total_length_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes01(9),
      Q => ip_total_length(9),
      R => data_counter_max
    );
\pc_ip_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(0),
      Q => \^q\(0),
      R => '0'
    );
\pc_ip_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(10),
      Q => \^q\(10),
      R => '0'
    );
\pc_ip_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(11),
      Q => \^q\(11),
      R => '0'
    );
\pc_ip_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(12),
      Q => \^q\(12),
      R => '0'
    );
\pc_ip_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(13),
      Q => \^q\(13),
      R => '0'
    );
\pc_ip_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(14),
      Q => \^q\(14),
      R => '0'
    );
\pc_ip_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(15),
      Q => \^q\(15),
      R => '0'
    );
\pc_ip_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(16),
      Q => \^q\(16),
      R => '0'
    );
\pc_ip_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(17),
      Q => \^q\(17),
      R => '0'
    );
\pc_ip_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(18),
      Q => \^q\(18),
      R => '0'
    );
\pc_ip_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(19),
      Q => \^q\(19),
      R => '0'
    );
\pc_ip_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(1),
      Q => \^q\(1),
      R => '0'
    );
\pc_ip_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(20),
      Q => \^q\(20),
      R => '0'
    );
\pc_ip_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(21),
      Q => \^q\(21),
      R => '0'
    );
\pc_ip_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(22),
      Q => \^q\(22),
      R => '0'
    );
\pc_ip_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(23),
      Q => \^q\(23),
      R => '0'
    );
\pc_ip_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(24),
      Q => \^q\(24),
      R => '0'
    );
\pc_ip_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(25),
      Q => \^q\(25),
      R => '0'
    );
\pc_ip_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(26),
      Q => \^q\(26),
      R => '0'
    );
\pc_ip_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(27),
      Q => \^q\(27),
      R => '0'
    );
\pc_ip_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(28),
      Q => \^q\(28),
      R => '0'
    );
\pc_ip_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(29),
      Q => \^q\(29),
      R => '0'
    );
\pc_ip_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(2),
      Q => \^q\(2),
      R => '0'
    );
\pc_ip_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(30),
      Q => \^q\(30),
      R => '0'
    );
\pc_ip_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(31),
      Q => \^q\(31),
      R => '0'
    );
\pc_ip_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(3),
      Q => \^q\(3),
      R => '0'
    );
\pc_ip_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(4),
      Q => \^q\(4),
      R => '0'
    );
\pc_ip_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(5),
      Q => \^q\(5),
      R => '0'
    );
\pc_ip_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(6),
      Q => \^q\(6),
      R => '0'
    );
\pc_ip_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(7),
      Q => \^q\(7),
      R => '0'
    );
\pc_ip_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(8),
      Q => \^q\(8),
      R => '0'
    );
\pc_ip_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_ip(9),
      Q => \^q\(9),
      R => '0'
    );
\pc_mac_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(0),
      Q => \pc_mac_reg[47]_0\(0),
      R => '0'
    );
\pc_mac_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(10),
      Q => \pc_mac_reg[47]_0\(10),
      R => '0'
    );
\pc_mac_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(11),
      Q => \pc_mac_reg[47]_0\(11),
      R => '0'
    );
\pc_mac_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(12),
      Q => \pc_mac_reg[47]_0\(12),
      R => '0'
    );
\pc_mac_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(13),
      Q => \pc_mac_reg[47]_0\(13),
      R => '0'
    );
\pc_mac_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(14),
      Q => \pc_mac_reg[47]_0\(14),
      R => '0'
    );
\pc_mac_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(15),
      Q => \pc_mac_reg[47]_0\(15),
      R => '0'
    );
\pc_mac_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(16),
      Q => \pc_mac_reg[47]_0\(16),
      R => '0'
    );
\pc_mac_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(17),
      Q => \pc_mac_reg[47]_0\(17),
      R => '0'
    );
\pc_mac_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(18),
      Q => \pc_mac_reg[47]_0\(18),
      R => '0'
    );
\pc_mac_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(19),
      Q => \pc_mac_reg[47]_0\(19),
      R => '0'
    );
\pc_mac_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(1),
      Q => \pc_mac_reg[47]_0\(1),
      R => '0'
    );
\pc_mac_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(20),
      Q => \pc_mac_reg[47]_0\(20),
      R => '0'
    );
\pc_mac_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(21),
      Q => \pc_mac_reg[47]_0\(21),
      R => '0'
    );
\pc_mac_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(22),
      Q => \pc_mac_reg[47]_0\(22),
      R => '0'
    );
\pc_mac_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(23),
      Q => \pc_mac_reg[47]_0\(23),
      R => '0'
    );
\pc_mac_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(24),
      Q => \pc_mac_reg[47]_0\(24),
      R => '0'
    );
\pc_mac_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(25),
      Q => \pc_mac_reg[47]_0\(25),
      R => '0'
    );
\pc_mac_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(26),
      Q => \pc_mac_reg[47]_0\(26),
      R => '0'
    );
\pc_mac_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(27),
      Q => \pc_mac_reg[47]_0\(27),
      R => '0'
    );
\pc_mac_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(28),
      Q => \pc_mac_reg[47]_0\(28),
      R => '0'
    );
\pc_mac_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(29),
      Q => \pc_mac_reg[47]_0\(29),
      R => '0'
    );
\pc_mac_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(2),
      Q => \pc_mac_reg[47]_0\(2),
      R => '0'
    );
\pc_mac_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(30),
      Q => \pc_mac_reg[47]_0\(30),
      R => '0'
    );
\pc_mac_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(31),
      Q => \pc_mac_reg[47]_0\(31),
      R => '0'
    );
\pc_mac_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(32),
      Q => \pc_mac_reg[47]_0\(32),
      R => '0'
    );
\pc_mac_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(33),
      Q => \pc_mac_reg[47]_0\(33),
      R => '0'
    );
\pc_mac_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(34),
      Q => \pc_mac_reg[47]_0\(34),
      R => '0'
    );
\pc_mac_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(35),
      Q => \pc_mac_reg[47]_0\(35),
      R => '0'
    );
\pc_mac_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(36),
      Q => \pc_mac_reg[47]_0\(36),
      R => '0'
    );
\pc_mac_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(37),
      Q => \pc_mac_reg[47]_0\(37),
      R => '0'
    );
\pc_mac_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(38),
      Q => \pc_mac_reg[47]_0\(38),
      R => '0'
    );
\pc_mac_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(39),
      Q => \pc_mac_reg[47]_0\(39),
      R => '0'
    );
\pc_mac_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(3),
      Q => \pc_mac_reg[47]_0\(3),
      R => '0'
    );
\pc_mac_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(40),
      Q => \pc_mac_reg[47]_0\(40),
      R => '0'
    );
\pc_mac_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(41),
      Q => \pc_mac_reg[47]_0\(41),
      R => '0'
    );
\pc_mac_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(42),
      Q => \pc_mac_reg[47]_0\(42),
      R => '0'
    );
\pc_mac_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(43),
      Q => \pc_mac_reg[47]_0\(43),
      R => '0'
    );
\pc_mac_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(44),
      Q => \pc_mac_reg[47]_0\(44),
      R => '0'
    );
\pc_mac_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(45),
      Q => \pc_mac_reg[47]_0\(45),
      R => '0'
    );
\pc_mac_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(46),
      Q => \pc_mac_reg[47]_0\(46),
      R => '0'
    );
\pc_mac_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(47),
      Q => \pc_mac_reg[47]_0\(47),
      R => '0'
    );
\pc_mac_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(4),
      Q => \pc_mac_reg[47]_0\(4),
      R => '0'
    );
\pc_mac_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(5),
      Q => \pc_mac_reg[47]_0\(5),
      R => '0'
    );
\pc_mac_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(6),
      Q => \pc_mac_reg[47]_0\(6),
      R => '0'
    );
\pc_mac_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(7),
      Q => \pc_mac_reg[47]_0\(7),
      R => '0'
    );
\pc_mac_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(8),
      Q => \pc_mac_reg[47]_0\(8),
      R => '0'
    );
\pc_mac_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => crc_pass_reg_n_0,
      D => source_mac(9),
      Q => \pc_mac_reg[47]_0\(9),
      R => '0'
    );
\pc_port_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(0),
      Q => \pc_port_reg[15]_0\(0),
      R => '0'
    );
\pc_port_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(10),
      Q => \pc_port_reg[15]_0\(10),
      R => '0'
    );
\pc_port_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(11),
      Q => \pc_port_reg[15]_0\(11),
      R => '0'
    );
\pc_port_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(12),
      Q => \pc_port_reg[15]_0\(12),
      R => '0'
    );
\pc_port_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(13),
      Q => \pc_port_reg[15]_0\(13),
      R => '0'
    );
\pc_port_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(14),
      Q => \pc_port_reg[15]_0\(14),
      R => '0'
    );
\pc_port_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(15),
      Q => \pc_port_reg[15]_0\(15),
      R => '0'
    );
\pc_port_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(1),
      Q => \pc_port_reg[15]_0\(1),
      R => '0'
    );
\pc_port_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(2),
      Q => \pc_port_reg[15]_0\(2),
      R => '0'
    );
\pc_port_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(3),
      Q => \pc_port_reg[15]_0\(3),
      R => '0'
    );
\pc_port_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(4),
      Q => \pc_port_reg[15]_0\(4),
      R => '0'
    );
\pc_port_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(5),
      Q => \pc_port_reg[15]_0\(5),
      R => '0'
    );
\pc_port_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(6),
      Q => \pc_port_reg[15]_0\(6),
      R => '0'
    );
\pc_port_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(7),
      Q => \pc_port_reg[15]_0\(7),
      R => '0'
    );
\pc_port_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(8),
      Q => \pc_port_reg[15]_0\(8),
      R => '0'
    );
\pc_port_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => send_ethernet_protocol_i_1_n_0,
      D => source_port(9),
      Q => \pc_port_reg[15]_0\(9),
      R => '0'
    );
read_eth_header_done_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \state_reg[1]_rep__0_n_0\,
      I1 => read_eth_header_done_i_2_n_0,
      I2 => read_eth_header_done0,
      I3 => read_eth_header_done,
      O => read_eth_header_done_i_1_n_0
    );
read_eth_header_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFF7FFFFFFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_read_done[12]_i_5_n_0\,
      I3 => \byte_count_reg_n_0_[4]\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \byte_read_done[6]_i_2_n_0\,
      O => read_eth_header_done_i_2_n_0
    );
read_eth_header_done_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \eth_prot_type[7]_i_3_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \state_reg_n_0_[2]\,
      I3 => eth_rstn,
      O => read_eth_header_done0
    );
read_eth_header_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => read_eth_header_done_i_1_n_0,
      Q => read_eth_header_done,
      R => '0'
    );
read_frame_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBA3333888A0000"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => read_frame_done_i_2_n_0,
      I2 => valid_data_byte_read_i_4_n_0,
      I3 => read_frame_done_i_3_n_0,
      I4 => \state[3]_i_7_n_0\,
      I5 => read_frame_done_reg_n_0,
      O => read_frame_done_i_1_n_0
    );
read_frame_done_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => crc_pass_i_2_n_0,
      O => read_frame_done_i_2_n_0
    );
read_frame_done_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF7FFFFFFFFFFF"
    )
        port map (
      I0 => \state[2]_i_7_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \byte_count_reg_n_0_[2]\,
      I5 => \byte_count_reg_n_0_[1]\,
      O => read_frame_done_i_3_n_0
    );
read_frame_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => read_frame_done_i_1_n_0,
      Q => read_frame_done_reg_n_0,
      R => '0'
    );
rst_ram_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF4074"
    )
        port map (
      I0 => \byte_read_done[3]_i_3_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \state_reg_n_0_[0]\,
      I3 => start_crc_i_2_n_0,
      I4 => \state_reg_n_0_[2]\,
      I5 => \state_reg_n_0_[3]\,
      O => rst_ram_i_2_n_0
    );
rst_ram_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F00"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \state_reg[1]_rep_n_0\,
      I3 => eth_rstn,
      O => rst_ram_i_4_n_0
    );
rst_ram_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => crc_checker_n_1,
      Q => rst_ram_reg_n_0,
      R => '0'
    );
send_arp_reply_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => arp_request_expected,
      I1 => crc_pass_reg_n_0,
      O => send_arp_reply_i_1_n_0
    );
send_arp_reply_reg: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => send_arp_reply_i_1_n_0,
      Q => \^send_arp_reply\,
      R => '0'
    );
send_ethernet_protocol_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => crc_pass_reg_n_0,
      I1 => arp_request_expected,
      I2 => eth_protocol_expected,
      O => send_ethernet_protocol_i_1_n_0
    );
send_ethernet_protocol_reg: unisim.vcomponents.FDRE
     port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => send_ethernet_protocol_i_1_n_0,
      Q => udp_packet_recieved,
      R => '0'
    );
\sip[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => sip(1),
      I1 => sip(0),
      O => \sip[0]_i_1_n_0\
    );
\sip[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => sip(0),
      I1 => sip(1),
      O => \sip[1]_i_1_n_0\
    );
\sip_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_header1,
      D => \sip[0]_i_1_n_0\,
      Q => sip(0),
      R => ip_hcs_calc_temp1
    );
\sip_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_header1,
      D => \sip[1]_i_1_n_0\,
      Q => sip(1),
      R => ip_hcs_calc_temp1
    );
\source_ip[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(0),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(0),
      O => \source_ip[0]_i_1_n_0\
    );
\source_ip[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(10),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(10),
      O => \source_ip[10]_i_1_n_0\
    );
\source_ip[11]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(11),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(11),
      O => \source_ip[11]_i_1_n_0\
    );
\source_ip[12]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(12),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(12),
      O => \source_ip[12]_i_1_n_0\
    );
\source_ip[13]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(13),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(13),
      O => \source_ip[13]_i_1_n_0\
    );
\source_ip[14]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(14),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(14),
      O => \source_ip[14]_i_1_n_0\
    );
\source_ip[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(15),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(15),
      O => \source_ip[15]_i_1_n_0\
    );
\source_ip[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(0),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(0),
      O => \source_ip[16]_i_1_n_0\
    );
\source_ip[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(1),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(1),
      O => \source_ip[17]_i_1_n_0\
    );
\source_ip[18]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(2),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(2),
      O => \source_ip[18]_i_1_n_0\
    );
\source_ip[19]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(3),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(3),
      O => \source_ip[19]_i_1_n_0\
    );
\source_ip[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(1),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(1),
      O => \source_ip[1]_i_1_n_0\
    );
\source_ip[20]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(4),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(4),
      O => \source_ip[20]_i_1_n_0\
    );
\source_ip[21]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(5),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(5),
      O => \source_ip[21]_i_1_n_0\
    );
\source_ip[22]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(6),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(6),
      O => \source_ip[22]_i_1_n_0\
    );
\source_ip[23]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(7),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(7),
      O => \source_ip[23]_i_1_n_0\
    );
\source_ip[24]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(8),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(8),
      O => \source_ip[24]_i_1_n_0\
    );
\source_ip[25]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(9),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(9),
      O => \source_ip[25]_i_1_n_0\
    );
\source_ip[26]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(10),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(10),
      O => \source_ip[26]_i_1_n_0\
    );
\source_ip[27]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(11),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(11),
      O => \source_ip[27]_i_1_n_0\
    );
\source_ip[28]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(12),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(12),
      O => \source_ip[28]_i_1_n_0\
    );
\source_ip[29]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(13),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(13),
      O => \source_ip[29]_i_1_n_0\
    );
\source_ip[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(2),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(2),
      O => \source_ip[2]_i_1_n_0\
    );
\source_ip[30]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(14),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(14),
      O => \source_ip[30]_i_1_n_0\
    );
\source_ip[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F75FF7FF"
    )
        port map (
      I0 => p_171_in,
      I1 => \byte_read_done_reg_n_0_[6]\,
      I2 => arp_request_expected,
      I3 => eth_protocol_expected,
      I4 => \byte_read_done_reg_n_0_[8]\,
      O => \source_ip[31]_i_1_n_0\
    );
\source_ip[31]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes06(15),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes07(15),
      O => \source_ip[31]_i_2_n_0\
    );
\source_ip[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(3),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(3),
      O => \source_ip[3]_i_1_n_0\
    );
\source_ip[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(4),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(4),
      O => \source_ip[4]_i_1_n_0\
    );
\source_ip[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(5),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(5),
      O => \source_ip[5]_i_1_n_0\
    );
\source_ip[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(6),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(6),
      O => \source_ip[6]_i_1_n_0\
    );
\source_ip[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(7),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(7),
      O => \source_ip[7]_i_1_n_0\
    );
\source_ip[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(8),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(8),
      O => \source_ip[8]_i_1_n_0\
    );
\source_ip[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BA8A"
    )
        port map (
      I0 => bytes07(9),
      I1 => eth_protocol_expected,
      I2 => arp_request_expected,
      I3 => bytes08(9),
      O => \source_ip[9]_i_1_n_0\
    );
\source_ip_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[0]_i_1_n_0\,
      Q => source_ip(0),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[10]_i_1_n_0\,
      Q => source_ip(10),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[11]_i_1_n_0\,
      Q => source_ip(11),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[12]_i_1_n_0\,
      Q => source_ip(12),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[13]_i_1_n_0\,
      Q => source_ip(13),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[14]_i_1_n_0\,
      Q => source_ip(14),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[15]_i_1_n_0\,
      Q => source_ip(15),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[16]_i_1_n_0\,
      Q => source_ip(16),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[17]_i_1_n_0\,
      Q => source_ip(17),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[18]_i_1_n_0\,
      Q => source_ip(18),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[19]_i_1_n_0\,
      Q => source_ip(19),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[1]_i_1_n_0\,
      Q => source_ip(1),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[20]_i_1_n_0\,
      Q => source_ip(20),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[21]_i_1_n_0\,
      Q => source_ip(21),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[22]_i_1_n_0\,
      Q => source_ip(22),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[23]_i_1_n_0\,
      Q => source_ip(23),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[24]_i_1_n_0\,
      Q => source_ip(24),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[25]_i_1_n_0\,
      Q => source_ip(25),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[26]_i_1_n_0\,
      Q => source_ip(26),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[27]_i_1_n_0\,
      Q => source_ip(27),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[28]_i_1_n_0\,
      Q => source_ip(28),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[29]_i_1_n_0\,
      Q => source_ip(29),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[2]_i_1_n_0\,
      Q => source_ip(2),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[30]_i_1_n_0\,
      Q => source_ip(30),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[31]_i_2_n_0\,
      Q => source_ip(31),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[3]_i_1_n_0\,
      Q => source_ip(3),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[4]_i_1_n_0\,
      Q => source_ip(4),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[5]_i_1_n_0\,
      Q => source_ip(5),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[6]_i_1_n_0\,
      Q => source_ip(6),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[7]_i_1_n_0\,
      Q => source_ip(7),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[8]_i_1_n_0\,
      Q => source_ip(8),
      R => \source_ip[31]_i_1_n_0\
    );
\source_ip_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_ip[9]_i_1_n_0\,
      Q => source_ip(9),
      R => \source_ip[31]_i_1_n_0\
    );
\source_mac[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \source_mac[7]_i_2_n_0\,
      I1 => \source_mac[38]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \source_mac[33]_i_2_n_0\,
      I4 => \source_mac[1]_i_2_n_0\,
      I5 => source_mac(0),
      O => \source_mac[0]_i_1_n_0\
    );
\source_mac[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \source_mac[43]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[11]_i_2_n_0\,
      I5 => source_mac(10),
      O => \source_mac[10]_i_1_n_0\
    );
\source_mac[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \source_mac[43]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[11]_i_2_n_0\,
      I5 => source_mac(11),
      O => \source_mac[11]_i_1_n_0\
    );
\source_mac[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020002020202"
    )
        port map (
      I0 => \byte_count[10]_i_11_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \source_mac[43]_i_2_n_0\,
      I4 => \source_mac[15]_i_3_n_0\,
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \source_mac[11]_i_2_n_0\
    );
\source_mac[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \source_mac[45]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[13]_i_2_n_0\,
      I5 => source_mac(12),
      O => \source_mac[12]_i_1_n_0\
    );
\source_mac[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \source_mac[45]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[13]_i_2_n_0\,
      I5 => source_mac(13),
      O => \source_mac[13]_i_1_n_0\
    );
\source_mac[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020002020202"
    )
        port map (
      I0 => \byte_count[10]_i_11_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \source_mac[45]_i_2_n_0\,
      I4 => \source_mac[15]_i_3_n_0\,
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \source_mac[13]_i_2_n_0\
    );
\source_mac[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \source_mac[47]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[15]_i_2_n_0\,
      I5 => source_mac(14),
      O => \source_mac[14]_i_1_n_0\
    );
\source_mac[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \source_mac[47]_i_2_n_0\,
      I1 => eth_rxd(1),
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[15]_i_2_n_0\,
      I5 => source_mac(15),
      O => \source_mac[15]_i_1_n_0\
    );
\source_mac[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020002020202"
    )
        port map (
      I0 => \byte_count[10]_i_11_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \source_mac[47]_i_2_n_0\,
      I4 => \source_mac[15]_i_3_n_0\,
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \source_mac[15]_i_2_n_0\
    );
\source_mac[15]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFBF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => start_crc_i_2_n_0,
      I3 => \byte_read_done[12]_i_5_n_0\,
      I4 => \byte_count_reg_n_0_[4]\,
      O => \source_mac[15]_i_3_n_0\
    );
\source_mac[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => \source_mac[38]_i_2_n_0\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \source_mac[33]_i_2_n_0\,
      I3 => \source_mac[23]_i_2_n_0\,
      I4 => \source_mac[17]_i_2_n_0\,
      I5 => source_mac(16),
      O => \source_mac[16]_i_1_n_0\
    );
\source_mac[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => \source_mac[39]_i_2_n_0\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \source_mac[33]_i_2_n_0\,
      I3 => \source_mac[23]_i_2_n_0\,
      I4 => \source_mac[17]_i_2_n_0\,
      I5 => source_mac(17),
      O => \source_mac[17]_i_1_n_0\
    );
\source_mac[17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000800AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \source_mac[33]_i_2_n_0\,
      I2 => \source_mac[45]_i_4_n_0\,
      I3 => \byte_count_reg_n_0_[0]\,
      I4 => \source_mac[31]_i_5_n_0\,
      I5 => \state_reg_n_0_[1]\,
      O => \source_mac[17]_i_2_n_0\
    );
\source_mac[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => \source_mac[38]_i_2_n_0\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \source_mac[35]_i_2_n_0\,
      I3 => \source_mac[23]_i_2_n_0\,
      I4 => \source_mac[19]_i_2_n_0\,
      I5 => source_mac(18),
      O => \source_mac[18]_i_1_n_0\
    );
\source_mac[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => \source_mac[39]_i_2_n_0\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \source_mac[35]_i_2_n_0\,
      I3 => \source_mac[23]_i_2_n_0\,
      I4 => \source_mac[19]_i_2_n_0\,
      I5 => source_mac(19),
      O => \source_mac[19]_i_1_n_0\
    );
\source_mac[19]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000800AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \source_mac[35]_i_2_n_0\,
      I2 => \source_mac[45]_i_4_n_0\,
      I3 => \byte_count_reg_n_0_[0]\,
      I4 => \source_mac[31]_i_5_n_0\,
      I5 => \state_reg_n_0_[1]\,
      O => \source_mac[19]_i_2_n_0\
    );
\source_mac[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \source_mac[7]_i_2_n_0\,
      I1 => \source_mac[39]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \source_mac[33]_i_2_n_0\,
      I4 => \source_mac[1]_i_2_n_0\,
      I5 => source_mac(1),
      O => \source_mac[1]_i_1_n_0\
    );
\source_mac[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00002000AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \source_mac[45]_i_4_n_0\,
      I2 => \source_mac[33]_i_2_n_0\,
      I3 => \state[3]_i_6_n_0\,
      I4 => \source_mac[15]_i_3_n_0\,
      I5 => \state_reg_n_0_[1]\,
      O => \source_mac[1]_i_2_n_0\
    );
\source_mac[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => \source_mac[38]_i_2_n_0\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \source_mac[37]_i_2_n_0\,
      I3 => \source_mac[23]_i_2_n_0\,
      I4 => \source_mac[21]_i_2_n_0\,
      I5 => source_mac(20),
      O => \source_mac[20]_i_1_n_0\
    );
\source_mac[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => \source_mac[39]_i_2_n_0\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \source_mac[37]_i_2_n_0\,
      I3 => \source_mac[23]_i_2_n_0\,
      I4 => \source_mac[21]_i_2_n_0\,
      I5 => source_mac(21),
      O => \source_mac[21]_i_1_n_0\
    );
\source_mac[21]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000800AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \source_mac[37]_i_2_n_0\,
      I2 => \source_mac[45]_i_4_n_0\,
      I3 => \byte_count_reg_n_0_[0]\,
      I4 => \source_mac[31]_i_5_n_0\,
      I5 => \state_reg_n_0_[1]\,
      O => \source_mac[21]_i_2_n_0\
    );
\source_mac[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => \source_mac[38]_i_2_n_0\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \byte_read_done[6]_i_2_n_0\,
      I3 => \source_mac[23]_i_2_n_0\,
      I4 => \source_mac[23]_i_3_n_0\,
      I5 => source_mac(22),
      O => \source_mac[22]_i_1_n_0\
    );
\source_mac[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008FFFF00080000"
    )
        port map (
      I0 => \byte_count_reg_n_0_[0]\,
      I1 => \byte_read_done[6]_i_2_n_0\,
      I2 => \source_mac[39]_i_2_n_0\,
      I3 => \source_mac[23]_i_2_n_0\,
      I4 => \source_mac[23]_i_3_n_0\,
      I5 => source_mac(23),
      O => \source_mac[23]_i_1_n_0\
    );
\source_mac[23]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[1]\,
      O => \source_mac[23]_i_2_n_0\
    );
\source_mac[23]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000800AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \byte_read_done[6]_i_2_n_0\,
      I2 => \source_mac[45]_i_4_n_0\,
      I3 => \byte_count_reg_n_0_[0]\,
      I4 => \source_mac[31]_i_5_n_0\,
      I5 => \state_reg_n_0_[1]\,
      O => \source_mac[23]_i_3_n_0\
    );
\source_mac[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F737300404040"
    )
        port map (
      I0 => \source_mac[30]_i_2_n_0\,
      I1 => \source_mac[31]_i_3_n_0\,
      I2 => \source_mac[25]_i_2_n_0\,
      I3 => \source_mac[31]_i_5_n_0\,
      I4 => \state_reg_n_0_[1]\,
      I5 => source_mac(24),
      O => \source_mac[24]_i_1_n_0\
    );
\source_mac[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F737300404040"
    )
        port map (
      I0 => \source_mac[31]_i_2_n_0\,
      I1 => \source_mac[31]_i_3_n_0\,
      I2 => \source_mac[25]_i_2_n_0\,
      I3 => \source_mac[31]_i_5_n_0\,
      I4 => \state_reg_n_0_[1]\,
      I5 => source_mac(25),
      O => \source_mac[25]_i_1_n_0\
    );
\source_mac[25]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400040000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \source_mac[33]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_read_done[12]_i_5_n_0\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => \byte_count_reg_n_0_[2]\,
      O => \source_mac[25]_i_2_n_0\
    );
\source_mac[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F737300404040"
    )
        port map (
      I0 => \source_mac[30]_i_2_n_0\,
      I1 => \source_mac[31]_i_3_n_0\,
      I2 => \source_mac[27]_i_2_n_0\,
      I3 => \source_mac[31]_i_5_n_0\,
      I4 => \state_reg_n_0_[1]\,
      I5 => source_mac(26),
      O => \source_mac[26]_i_1_n_0\
    );
\source_mac[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F737300404040"
    )
        port map (
      I0 => \source_mac[31]_i_2_n_0\,
      I1 => \source_mac[31]_i_3_n_0\,
      I2 => \source_mac[27]_i_2_n_0\,
      I3 => \source_mac[31]_i_5_n_0\,
      I4 => \state_reg_n_0_[1]\,
      I5 => source_mac(27),
      O => \source_mac[27]_i_1_n_0\
    );
\source_mac[27]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400040000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \source_mac[35]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_read_done[12]_i_5_n_0\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => \byte_count_reg_n_0_[2]\,
      O => \source_mac[27]_i_2_n_0\
    );
\source_mac[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F737300404040"
    )
        port map (
      I0 => \source_mac[30]_i_2_n_0\,
      I1 => \source_mac[31]_i_3_n_0\,
      I2 => \source_mac[29]_i_2_n_0\,
      I3 => \source_mac[31]_i_5_n_0\,
      I4 => \state_reg_n_0_[1]\,
      I5 => source_mac(28),
      O => \source_mac[28]_i_1_n_0\
    );
\source_mac[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F737300404040"
    )
        port map (
      I0 => \source_mac[31]_i_2_n_0\,
      I1 => \source_mac[31]_i_3_n_0\,
      I2 => \source_mac[29]_i_2_n_0\,
      I3 => \source_mac[31]_i_5_n_0\,
      I4 => \state_reg_n_0_[1]\,
      I5 => source_mac(29),
      O => \source_mac[29]_i_1_n_0\
    );
\source_mac[29]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400040000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \source_mac[37]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_read_done[12]_i_5_n_0\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => \byte_count_reg_n_0_[2]\,
      O => \source_mac[29]_i_2_n_0\
    );
\source_mac[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \source_mac[7]_i_2_n_0\,
      I1 => \source_mac[38]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \source_mac[35]_i_2_n_0\,
      I4 => \source_mac[3]_i_2_n_0\,
      I5 => source_mac(2),
      O => \source_mac[2]_i_1_n_0\
    );
\source_mac[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F737300404040"
    )
        port map (
      I0 => \source_mac[30]_i_2_n_0\,
      I1 => \source_mac[31]_i_3_n_0\,
      I2 => \source_mac[31]_i_4_n_0\,
      I3 => \source_mac[31]_i_5_n_0\,
      I4 => \state_reg_n_0_[1]\,
      I5 => source_mac(30),
      O => \source_mac[30]_i_1_n_0\
    );
\source_mac[30]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \source_mac[23]_i_2_n_0\,
      O => \source_mac[30]_i_2_n_0\
    );
\source_mac[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF7F737300404040"
    )
        port map (
      I0 => \source_mac[31]_i_2_n_0\,
      I1 => \source_mac[31]_i_3_n_0\,
      I2 => \source_mac[31]_i_4_n_0\,
      I3 => \source_mac[31]_i_5_n_0\,
      I4 => \state_reg_n_0_[1]\,
      I5 => source_mac(31),
      O => \source_mac[31]_i_1_n_0\
    );
\source_mac[31]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \source_mac[23]_i_2_n_0\,
      O => \source_mac[31]_i_2_n_0\
    );
\source_mac[31]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \byte_count[10]_i_11_n_0\,
      O => \source_mac[31]_i_3_n_0\
    );
\source_mac[31]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000400040000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_read_done[6]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_read_done[12]_i_5_n_0\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => \byte_count_reg_n_0_[2]\,
      O => \source_mac[31]_i_4_n_0\
    );
\source_mac[31]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[4]\,
      I1 => \byte_read_done[12]_i_5_n_0\,
      I2 => start_crc_i_2_n_0,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[2]\,
      I5 => \byte_count_reg_n_0_[1]\,
      O => \source_mac[31]_i_5_n_0\
    );
\source_mac[32]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \source_mac[39]_i_3_n_0\,
      I1 => \source_mac[38]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \source_mac[33]_i_2_n_0\,
      I4 => \source_mac[33]_i_3_n_0\,
      I5 => source_mac(32),
      O => \source_mac[32]_i_1_n_0\
    );
\source_mac[33]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \source_mac[39]_i_3_n_0\,
      I1 => \source_mac[39]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \source_mac[33]_i_2_n_0\,
      I4 => \source_mac[33]_i_3_n_0\,
      I5 => source_mac(33),
      O => \source_mac[33]_i_1_n_0\
    );
\source_mac[33]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \bit_count_reg[1]_rep_n_0\,
      I1 => ip_header_options1(1),
      O => \source_mac[33]_i_2_n_0\
    );
\source_mac[33]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08000000AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \source_mac[47]_i_5_n_0\,
      I2 => \source_mac[45]_i_4_n_0\,
      I3 => \source_mac[33]_i_2_n_0\,
      I4 => \state[3]_i_6_n_0\,
      I5 => \state_reg_n_0_[1]\,
      O => \source_mac[33]_i_3_n_0\
    );
\source_mac[34]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \source_mac[39]_i_3_n_0\,
      I1 => \source_mac[38]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \source_mac[35]_i_2_n_0\,
      I4 => \source_mac[35]_i_3_n_0\,
      I5 => source_mac(34),
      O => \source_mac[34]_i_1_n_0\
    );
\source_mac[35]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \source_mac[39]_i_3_n_0\,
      I1 => \source_mac[39]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \source_mac[35]_i_2_n_0\,
      I4 => \source_mac[35]_i_3_n_0\,
      I5 => source_mac(35),
      O => \source_mac[35]_i_1_n_0\
    );
\source_mac[35]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      O => \source_mac[35]_i_2_n_0\
    );
\source_mac[35]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08000000AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \source_mac[47]_i_5_n_0\,
      I2 => \source_mac[45]_i_4_n_0\,
      I3 => \source_mac[35]_i_2_n_0\,
      I4 => \state[3]_i_6_n_0\,
      I5 => \state_reg_n_0_[1]\,
      O => \source_mac[35]_i_3_n_0\
    );
\source_mac[36]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \source_mac[39]_i_3_n_0\,
      I1 => \source_mac[38]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \source_mac[37]_i_2_n_0\,
      I4 => \source_mac[37]_i_3_n_0\,
      I5 => source_mac(36),
      O => \source_mac[36]_i_1_n_0\
    );
\source_mac[37]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \source_mac[39]_i_3_n_0\,
      I1 => \source_mac[39]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \source_mac[37]_i_2_n_0\,
      I4 => \source_mac[37]_i_3_n_0\,
      I5 => source_mac(37),
      O => \source_mac[37]_i_1_n_0\
    );
\source_mac[37]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \bit_count_reg[1]_rep_n_0\,
      I1 => ip_header_options1(1),
      O => \source_mac[37]_i_2_n_0\
    );
\source_mac[37]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08000000AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \source_mac[47]_i_5_n_0\,
      I2 => \source_mac[45]_i_4_n_0\,
      I3 => \source_mac[37]_i_2_n_0\,
      I4 => \state[3]_i_6_n_0\,
      I5 => \state_reg_n_0_[1]\,
      O => \source_mac[37]_i_3_n_0\
    );
\source_mac[38]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \source_mac[39]_i_3_n_0\,
      I1 => \source_mac[38]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \byte_read_done[6]_i_2_n_0\,
      I4 => \source_mac[39]_i_4_n_0\,
      I5 => source_mac(38),
      O => \source_mac[38]_i_1_n_0\
    );
\source_mac[38]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \source_mac[45]_i_4_n_0\,
      O => \source_mac[38]_i_2_n_0\
    );
\source_mac[39]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_read_done[6]_i_2_n_0\,
      I2 => \source_mac[39]_i_2_n_0\,
      I3 => \source_mac[39]_i_3_n_0\,
      I4 => \source_mac[39]_i_4_n_0\,
      I5 => source_mac(39),
      O => \source_mac[39]_i_1_n_0\
    );
\source_mac[39]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \source_mac[45]_i_4_n_0\,
      O => \source_mac[39]_i_2_n_0\
    );
\source_mac[39]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \state_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[1]\,
      O => \source_mac[39]_i_3_n_0\
    );
\source_mac[39]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08000000AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \source_mac[47]_i_5_n_0\,
      I2 => \source_mac[45]_i_4_n_0\,
      I3 => \byte_read_done[6]_i_2_n_0\,
      I4 => \state[3]_i_6_n_0\,
      I5 => \state_reg_n_0_[1]\,
      O => \source_mac[39]_i_4_n_0\
    );
\source_mac[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \source_mac[7]_i_2_n_0\,
      I1 => \source_mac[39]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \source_mac[35]_i_2_n_0\,
      I4 => \source_mac[3]_i_2_n_0\,
      I5 => source_mac(3),
      O => \source_mac[3]_i_1_n_0\
    );
\source_mac[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00002000AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \source_mac[45]_i_4_n_0\,
      I2 => \source_mac[35]_i_2_n_0\,
      I3 => \state[3]_i_6_n_0\,
      I4 => \source_mac[15]_i_3_n_0\,
      I5 => \state_reg_n_0_[1]\,
      O => \source_mac[3]_i_2_n_0\
    );
\source_mac[40]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \source_mac[41]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[41]_i_3_n_0\,
      I5 => source_mac(40),
      O => \source_mac[40]_i_1_n_0\
    );
\source_mac[41]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \source_mac[41]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[41]_i_3_n_0\,
      I5 => source_mac(41),
      O => \source_mac[41]_i_1_n_0\
    );
\source_mac[41]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00010000"
    )
        port map (
      I0 => \source_mac[45]_i_4_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      I4 => \byte_count_reg_n_0_[1]\,
      O => \source_mac[41]_i_2_n_0\
    );
\source_mac[41]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000002020202"
    )
        port map (
      I0 => \byte_count[10]_i_11_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \source_mac[47]_i_5_n_0\,
      I4 => \source_mac[41]_i_2_n_0\,
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \source_mac[41]_i_3_n_0\
    );
\source_mac[42]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \source_mac[43]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[43]_i_3_n_0\,
      I5 => source_mac(42),
      O => \source_mac[42]_i_1_n_0\
    );
\source_mac[43]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \source_mac[43]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[43]_i_3_n_0\,
      I5 => source_mac(43),
      O => \source_mac[43]_i_1_n_0\
    );
\source_mac[43]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00100000"
    )
        port map (
      I0 => \source_mac[45]_i_4_n_0\,
      I1 => ip_header_options1(2),
      I2 => \bit_count_reg[0]_rep_n_0\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      I4 => \byte_count_reg_n_0_[1]\,
      O => \source_mac[43]_i_2_n_0\
    );
\source_mac[43]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000002020202"
    )
        port map (
      I0 => \byte_count[10]_i_11_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \source_mac[47]_i_5_n_0\,
      I4 => \source_mac[43]_i_2_n_0\,
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \source_mac[43]_i_3_n_0\
    );
\source_mac[44]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \source_mac[45]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[45]_i_3_n_0\,
      I5 => source_mac(44),
      O => \source_mac[44]_i_1_n_0\
    );
\source_mac[45]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \source_mac[45]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[45]_i_3_n_0\,
      I5 => source_mac(45),
      O => \source_mac[45]_i_1_n_0\
    );
\source_mac[45]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00100000"
    )
        port map (
      I0 => \source_mac[45]_i_4_n_0\,
      I1 => \bit_count_reg[0]_rep_n_0\,
      I2 => ip_header_options1(2),
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      I4 => \byte_count_reg_n_0_[1]\,
      O => \source_mac[45]_i_2_n_0\
    );
\source_mac[45]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000002020202"
    )
        port map (
      I0 => \byte_count[10]_i_11_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \source_mac[47]_i_5_n_0\,
      I4 => \source_mac[45]_i_2_n_0\,
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \source_mac[45]_i_3_n_0\
    );
\source_mac[45]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEEF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[4]\,
      I1 => \byte_read_done[12]_i_5_n_0\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      O => \source_mac[45]_i_4_n_0\
    );
\source_mac[46]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \source_mac[47]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[47]_i_3_n_0\,
      I5 => source_mac(46),
      O => \source_mac[46]_i_1_n_0\
    );
\source_mac[47]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000FFFF80000000"
    )
        port map (
      I0 => \source_mac[47]_i_2_n_0\,
      I1 => eth_rxd(1),
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[47]_i_3_n_0\,
      I5 => source_mac(47),
      O => \source_mac[47]_i_1_n_0\
    );
\source_mac[47]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000060000000000"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \source_mac[47]_i_4_n_0\,
      I3 => \byte_read_done[6]_i_2_n_0\,
      I4 => \byte_count_reg[0]_rep__1_n_0\,
      I5 => \byte_count_reg_n_0_[1]\,
      O => \source_mac[47]_i_2_n_0\
    );
\source_mac[47]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200000002020202"
    )
        port map (
      I0 => \byte_count[10]_i_11_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \source_mac[47]_i_2_n_0\,
      I4 => \source_mac[47]_i_5_n_0\,
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \source_mac[47]_i_3_n_0\
    );
\source_mac[47]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \byte_count_reg_n_0_[4]\,
      I1 => \byte_read_done[12]_i_5_n_0\,
      O => \source_mac[47]_i_4_n_0\
    );
\source_mac[47]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000800"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => start_crc_i_2_n_0,
      I4 => \byte_read_done[12]_i_5_n_0\,
      I5 => \byte_count_reg_n_0_[4]\,
      O => \source_mac[47]_i_5_n_0\
    );
\source_mac[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \source_mac[7]_i_2_n_0\,
      I1 => \source_mac[38]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \source_mac[37]_i_2_n_0\,
      I4 => \source_mac[5]_i_2_n_0\,
      I5 => source_mac(4),
      O => \source_mac[4]_i_1_n_0\
    );
\source_mac[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \source_mac[7]_i_2_n_0\,
      I1 => \source_mac[39]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \source_mac[37]_i_2_n_0\,
      I4 => \source_mac[5]_i_2_n_0\,
      I5 => source_mac(5),
      O => \source_mac[5]_i_1_n_0\
    );
\source_mac[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00002000AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \source_mac[45]_i_4_n_0\,
      I2 => \source_mac[37]_i_2_n_0\,
      I3 => \state[3]_i_6_n_0\,
      I4 => \source_mac[15]_i_3_n_0\,
      I5 => \state_reg_n_0_[1]\,
      O => \source_mac[5]_i_2_n_0\
    );
\source_mac[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2000FFFF20000000"
    )
        port map (
      I0 => \source_mac[7]_i_2_n_0\,
      I1 => \source_mac[38]_i_2_n_0\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \byte_read_done[6]_i_2_n_0\,
      I4 => \source_mac[7]_i_3_n_0\,
      I5 => source_mac(6),
      O => \source_mac[6]_i_1_n_0\
    );
\source_mac[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080FFFF00800000"
    )
        port map (
      I0 => \source_mac[7]_i_2_n_0\,
      I1 => \byte_count_reg[0]_rep__1_n_0\,
      I2 => \byte_read_done[6]_i_2_n_0\,
      I3 => \source_mac[39]_i_2_n_0\,
      I4 => \source_mac[7]_i_3_n_0\,
      I5 => source_mac(7),
      O => \source_mac[7]_i_1_n_0\
    );
\source_mac[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \state_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[1]\,
      O => \source_mac[7]_i_2_n_0\
    );
\source_mac[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00002000AAAAAAAA"
    )
        port map (
      I0 => \source_mac[31]_i_3_n_0\,
      I1 => \source_mac[45]_i_4_n_0\,
      I2 => \byte_read_done[6]_i_2_n_0\,
      I3 => \state[3]_i_6_n_0\,
      I4 => \source_mac[15]_i_3_n_0\,
      I5 => \state_reg_n_0_[1]\,
      O => \source_mac[7]_i_3_n_0\
    );
\source_mac[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \source_mac[41]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[9]_i_2_n_0\,
      I5 => source_mac(8),
      O => \source_mac[8]_i_1_n_0\
    );
\source_mac[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800FFFF08000000"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => \source_mac[41]_i_2_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg[1]_rep__0_n_0\,
      I4 => \source_mac[9]_i_2_n_0\,
      I5 => source_mac(9),
      O => \source_mac[9]_i_1_n_0\
    );
\source_mac[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020002020202"
    )
        port map (
      I0 => \byte_count[10]_i_11_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \source_mac[41]_i_2_n_0\,
      I4 => \source_mac[15]_i_3_n_0\,
      I5 => \state_reg[1]_rep__0_n_0\,
      O => \source_mac[9]_i_2_n_0\
    );
\source_mac_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[0]_i_1_n_0\,
      Q => source_mac(0),
      R => '0'
    );
\source_mac_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[10]_i_1_n_0\,
      Q => source_mac(10),
      R => '0'
    );
\source_mac_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[11]_i_1_n_0\,
      Q => source_mac(11),
      R => '0'
    );
\source_mac_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[12]_i_1_n_0\,
      Q => source_mac(12),
      R => '0'
    );
\source_mac_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[13]_i_1_n_0\,
      Q => source_mac(13),
      R => '0'
    );
\source_mac_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[14]_i_1_n_0\,
      Q => source_mac(14),
      R => '0'
    );
\source_mac_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[15]_i_1_n_0\,
      Q => source_mac(15),
      R => '0'
    );
\source_mac_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[16]_i_1_n_0\,
      Q => source_mac(16),
      R => '0'
    );
\source_mac_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[17]_i_1_n_0\,
      Q => source_mac(17),
      R => '0'
    );
\source_mac_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[18]_i_1_n_0\,
      Q => source_mac(18),
      R => '0'
    );
\source_mac_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[19]_i_1_n_0\,
      Q => source_mac(19),
      R => '0'
    );
\source_mac_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[1]_i_1_n_0\,
      Q => source_mac(1),
      R => '0'
    );
\source_mac_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[20]_i_1_n_0\,
      Q => source_mac(20),
      R => '0'
    );
\source_mac_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[21]_i_1_n_0\,
      Q => source_mac(21),
      R => '0'
    );
\source_mac_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[22]_i_1_n_0\,
      Q => source_mac(22),
      R => '0'
    );
\source_mac_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[23]_i_1_n_0\,
      Q => source_mac(23),
      R => '0'
    );
\source_mac_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[24]_i_1_n_0\,
      Q => source_mac(24),
      R => '0'
    );
\source_mac_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[25]_i_1_n_0\,
      Q => source_mac(25),
      R => '0'
    );
\source_mac_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[26]_i_1_n_0\,
      Q => source_mac(26),
      R => '0'
    );
\source_mac_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[27]_i_1_n_0\,
      Q => source_mac(27),
      R => '0'
    );
\source_mac_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[28]_i_1_n_0\,
      Q => source_mac(28),
      R => '0'
    );
\source_mac_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[29]_i_1_n_0\,
      Q => source_mac(29),
      R => '0'
    );
\source_mac_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[2]_i_1_n_0\,
      Q => source_mac(2),
      R => '0'
    );
\source_mac_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[30]_i_1_n_0\,
      Q => source_mac(30),
      R => '0'
    );
\source_mac_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[31]_i_1_n_0\,
      Q => source_mac(31),
      R => '0'
    );
\source_mac_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[32]_i_1_n_0\,
      Q => source_mac(32),
      R => '0'
    );
\source_mac_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[33]_i_1_n_0\,
      Q => source_mac(33),
      R => '0'
    );
\source_mac_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[34]_i_1_n_0\,
      Q => source_mac(34),
      R => '0'
    );
\source_mac_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[35]_i_1_n_0\,
      Q => source_mac(35),
      R => '0'
    );
\source_mac_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[36]_i_1_n_0\,
      Q => source_mac(36),
      R => '0'
    );
\source_mac_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[37]_i_1_n_0\,
      Q => source_mac(37),
      R => '0'
    );
\source_mac_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[38]_i_1_n_0\,
      Q => source_mac(38),
      R => '0'
    );
\source_mac_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[39]_i_1_n_0\,
      Q => source_mac(39),
      R => '0'
    );
\source_mac_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[3]_i_1_n_0\,
      Q => source_mac(3),
      R => '0'
    );
\source_mac_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[40]_i_1_n_0\,
      Q => source_mac(40),
      R => '0'
    );
\source_mac_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[41]_i_1_n_0\,
      Q => source_mac(41),
      R => '0'
    );
\source_mac_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[42]_i_1_n_0\,
      Q => source_mac(42),
      R => '0'
    );
\source_mac_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[43]_i_1_n_0\,
      Q => source_mac(43),
      R => '0'
    );
\source_mac_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[44]_i_1_n_0\,
      Q => source_mac(44),
      R => '0'
    );
\source_mac_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[45]_i_1_n_0\,
      Q => source_mac(45),
      R => '0'
    );
\source_mac_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[46]_i_1_n_0\,
      Q => source_mac(46),
      R => '0'
    );
\source_mac_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[47]_i_1_n_0\,
      Q => source_mac(47),
      R => '0'
    );
\source_mac_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[4]_i_1_n_0\,
      Q => source_mac(4),
      R => '0'
    );
\source_mac_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[5]_i_1_n_0\,
      Q => source_mac(5),
      R => '0'
    );
\source_mac_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[6]_i_1_n_0\,
      Q => source_mac(6),
      R => '0'
    );
\source_mac_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[7]_i_1_n_0\,
      Q => source_mac(7),
      R => '0'
    );
\source_mac_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[8]_i_1_n_0\,
      Q => source_mac(8),
      R => '0'
    );
\source_mac_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \source_mac[9]_i_1_n_0\,
      Q => source_mac(9),
      R => '0'
    );
\source_port[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \byte_read_done_reg_n_0_[10]\,
      I1 => arp_request_expected,
      I2 => eth_protocol_expected,
      O => \source_port[15]_i_1_n_0\
    );
\source_port_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(0),
      Q => source_port(0),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(10),
      Q => source_port(10),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(11),
      Q => source_port(11),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(12),
      Q => source_port(12),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(13),
      Q => source_port(13),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(14),
      Q => source_port(14),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(15),
      Q => source_port(15),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(1),
      Q => source_port(1),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(2),
      Q => source_port(2),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(3),
      Q => source_port(3),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(4),
      Q => source_port(4),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(5),
      Q => source_port(5),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(6),
      Q => source_port(6),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(7),
      Q => source_port(7),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(8),
      Q => source_port(8),
      R => \source_port[15]_i_1_n_0\
    );
\source_port_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes10(9),
      Q => source_port(9),
      R => \source_port[15]_i_1_n_0\
    );
start_crc_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0400FFFF04000000"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \state_reg_n_0_[2]\,
      I3 => start_crc_i_2_n_0,
      I4 => start_crc0,
      I5 => start_crc_reg_n_0,
      O => start_crc_i_1_n_0
    );
start_crc_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_crsdv,
      I1 => eth_rxerr,
      O => start_crc_i_2_n_0
    );
start_crc_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00002A0000AA2AAA"
    )
        port map (
      I0 => \byte_count[10]_i_11_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \state_reg_n_0_[2]\,
      I4 => start_crc_i_4_n_0,
      I5 => start_crc_i_5_n_0,
      O => start_crc0
    );
start_crc_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF0000"
    )
        port map (
      I0 => start_crc2,
      I1 => \byte_read_done[6]_i_2_n_0\,
      I2 => start_crc024_in,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => start_crc_i_6_n_0,
      O => start_crc_i_4_n_0
    );
start_crc_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55400440"
    )
        port map (
      I0 => stop_crc_i_4_n_0,
      I1 => start_crc_i_2_n_0,
      I2 => \state_reg_n_0_[0]\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      O => start_crc_i_5_n_0
    );
start_crc_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800000000000000"
    )
        port map (
      I0 => \state[0]_i_9_n_0\,
      I1 => start_crc1,
      I2 => \state_reg[1]_rep_n_0\,
      I3 => \state_reg_n_0_[0]\,
      I4 => start_crc277_in,
      I5 => \byte_read_done[6]_i_2_n_0\,
      O => start_crc_i_6_n_0
    );
start_crc_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => start_crc_i_1_n_0,
      Q => start_crc_reg_n_0,
      R => '0'
    );
\state[0]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2AAAAAAA"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \byte_count_reg[0]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => ip_header_options1(1),
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => \byte_read_done[3]_i_4_n_0\,
      O => \state[0]_i_10_n_0\
    );
\state[0]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000008000"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[4]\,
      I5 => \byte_read_done[12]_i_5_n_0\,
      O => \state[0]_i_11_n_0\
    );
\state[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4040454055555555"
    )
        port map (
      I0 => \state_reg_n_0_[3]\,
      I1 => \state_reg[0]_i_2_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \state[0]_i_3_n_0\,
      I4 => \state[0]_i_4__0_n_0\,
      I5 => \state[0]_i_5_n_0\,
      O => \state[0]_i_1__1_n_0\
    );
\state[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => \state_reg[1]_rep_n_0\,
      O => \state[0]_i_3_n_0\
    );
\state[0]_i_4__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => start_crc_i_2_n_0,
      O => \state[0]_i_4__0_n_0\
    );
\state[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDFDDDFDFDFDDDF"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state[0]_i_8_n_0\,
      I3 => \state[1]_i_9_n_0\,
      I4 => \state[1]_i_10_n_0\,
      I5 => \state[2]_i_6_n_0\,
      O => \state[0]_i_5_n_0\
    );
\state[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFFFEFAAAAAAAA"
    )
        port map (
      I0 => \state[1]_i_7_n_0\,
      I1 => \state[0]_i_9_n_0\,
      I2 => start_crc1,
      I3 => start_crc277_in,
      I4 => \byte_read_done[6]_i_2_n_0\,
      I5 => valid_data_byte_read_i_3_n_0,
      O => \state[0]_i_6_n_0\
    );
\state[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAABAAABAAA"
    )
        port map (
      I0 => \state[0]_i_10_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \byte_read_done[3]_i_3_n_0\,
      I3 => start_crc024_in,
      I4 => \byte_read_done[6]_i_2_n_0\,
      I5 => start_crc2,
      O => \state[0]_i_7_n_0\
    );
\state[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000400000000000"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg[0]_rep__0_n_0\,
      I2 => \state[0]_i_11_n_0\,
      I3 => \dest_mac[39]_i_4_n_0\,
      I4 => \state_reg_n_0_[0]\,
      I5 => \eth_prot_type[15]_i_4_n_0\,
      O => \state[0]_i_8_n_0\
    );
\state[0]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[3]\,
      I1 => \zero_counter_reg_n_0_[1]\,
      I2 => \zero_counter_reg_n_0_[0]\,
      I3 => \zero_counter_reg_n_0_[2]\,
      I4 => \zero_counter_reg_n_0_[4]\,
      O => \state[0]_i_9_n_0\
    );
\state[1]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[4]\,
      I1 => \data_counter_max_reg_n_0_[1]\,
      I2 => \data_counter_max_reg_n_0_[2]\,
      I3 => \data_counter_max_reg_n_0_[3]\,
      I4 => \data_counter_max_reg_n_0_[0]\,
      I5 => \zero_counter[4]_i_5_n_0\,
      O => \state[1]_i_10_n_0\
    );
\state[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0005890089000089"
    )
        port map (
      I0 => \byte_count_reg_n_0_[10]\,
      I1 => \data_counter_max_reg_n_0_[10]\,
      I2 => \state[1]_i_10_n_0\,
      I3 => \data_counter_max_reg_n_0_[9]\,
      I4 => valid_data_byte_read_i_18_n_0,
      I5 => \byte_count_reg_n_0_[9]\,
      O => \state[1]_i_11_n_0\
    );
\state[1]_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D22D0000"
    )
        port map (
      I0 => valid_data_byte_read_i_19_n_0,
      I1 => \data_counter_max_reg_n_0_[7]\,
      I2 => \data_counter_max_reg_n_0_[8]\,
      I3 => \byte_count_reg_n_0_[8]\,
      I4 => \state[1]_i_15_n_0\,
      O => \state[1]_i_12_n_0\
    );
\state[1]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888222222228"
    )
        port map (
      I0 => \state[1]_i_16_n_0\,
      I1 => \data_counter_max_reg_n_0_[3]\,
      I2 => \data_counter_max_reg_n_0_[2]\,
      I3 => \data_counter_max_reg_n_0_[0]\,
      I4 => \data_counter_max_reg_n_0_[1]\,
      I5 => \byte_count_reg_n_0_[3]\,
      O => \state[1]_i_13_n_0\
    );
\state[1]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0900009000600900"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg[0]_rep__1_n_0\,
      I3 => \data_counter_max_reg_n_0_[0]\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \data_counter_max_reg_n_0_[1]\,
      O => \state[1]_i_14_n_0\
    );
\state[1]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9090069009099009"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[7]\,
      I1 => \byte_count_reg_n_0_[7]\,
      I2 => \data_counter_max_reg_n_0_[6]\,
      I3 => valid_data_byte_read_i_20_n_0,
      I4 => \data_counter_max_reg_n_0_[5]\,
      I5 => \byte_count_reg_n_0_[6]\,
      O => \state[1]_i_15_n_0\
    );
\state[1]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"09609009"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[5]\,
      I1 => \byte_count_reg_n_0_[5]\,
      I2 => valid_data_byte_read_i_21_n_0,
      I3 => \data_counter_max_reg_n_0_[4]\,
      I4 => \byte_count_reg_n_0_[4]\,
      O => \state[1]_i_16_n_0\
    );
\state[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555445455555555"
    )
        port map (
      I0 => \state_reg_n_0_[3]\,
      I1 => \state[2]_i_3_n_0\,
      I2 => \state[1]_i_2_n_0\,
      I3 => \state[1]_i_3_n_0\,
      I4 => \state[1]_i_4_n_0\,
      I5 => \state[1]_i_5_n_0\,
      O => \state[1]_i_1__1_n_0\
    );
\state[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \state_reg_n_0_[2]\,
      I3 => start_crc_i_2_n_0,
      O => \state[1]_i_2_n_0\
    );
\state[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => eth_rxd(1),
      O => \state[1]_i_3_n_0\
    );
\state[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8A888A888888888"
    )
        port map (
      I0 => \state[1]_i_6_n_0\,
      I1 => \state[1]_i_7_n_0\,
      I2 => start_crc1,
      I3 => start_crc277_in,
      I4 => \byte_read_done[6]_i_2_n_0\,
      I5 => valid_data_byte_read_i_3_n_0,
      O => \state[1]_i_4_n_0\
    );
\state[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBFBBBFAAAABBBF"
    )
        port map (
      I0 => \byte_read_done[11]_i_3_n_0\,
      I1 => \state[1]_i_9_n_0\,
      I2 => \state[2]_i_6_n_0\,
      I3 => \state[1]_i_10_n_0\,
      I4 => start_crc_i_2_n_0,
      I5 => \state_reg_n_0_[0]\,
      O => \state[1]_i_5_n_0\
    );
\state[1]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \state_reg[1]_rep_n_0\,
      O => \state[1]_i_6_n_0\
    );
\state[1]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0202000200020002"
    )
        port map (
      I0 => \byte_read_done[3]_i_3_n_0\,
      I1 => \byte_count_extra_reg[5]_i_4_n_0\,
      I2 => \state_reg_n_0_[0]\,
      I3 => bit_count2,
      I4 => ip_header_options1(1),
      I5 => \bit_count_reg[1]_rep_n_0\,
      O => \state[1]_i_7_n_0\
    );
\state[1]_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80888888"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \byte_read_done[3]_i_3_n_0\,
      I2 => \dest_mac[12]_i_4_n_0\,
      I3 => ip_extra_options,
      I4 => \bytes04[15]_i_4_n_0\,
      O => \state[1]_i_9_n_0\
    );
\state[1]_rep_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555445455555555"
    )
        port map (
      I0 => \state_reg_n_0_[3]\,
      I1 => \state[2]_i_3_n_0\,
      I2 => \state[1]_i_2_n_0\,
      I3 => \state[1]_i_3_n_0\,
      I4 => \state[1]_i_4_n_0\,
      I5 => \state[1]_i_5_n_0\,
      O => \state[1]_rep_i_1_n_0\
    );
\state[1]_rep_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555445455555555"
    )
        port map (
      I0 => \state_reg_n_0_[3]\,
      I1 => \state[2]_i_3_n_0\,
      I2 => \state[1]_i_2_n_0\,
      I3 => \state[1]_i_3_n_0\,
      I4 => \state[1]_i_4_n_0\,
      I5 => \state[1]_i_5_n_0\,
      O => \state[1]_rep_i_1__0_n_0\
    );
\state[1]_rep_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555445455555555"
    )
        port map (
      I0 => \state_reg_n_0_[3]\,
      I1 => \state[2]_i_3_n_0\,
      I2 => \state[1]_i_2_n_0\,
      I3 => \state[1]_i_3_n_0\,
      I4 => \state[1]_i_4_n_0\,
      I5 => \state[1]_i_5_n_0\,
      O => \state[1]_rep_i_1__1_n_0\
    );
\state[2]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"030306000800040C"
    )
        port map (
      I0 => \byte_read_done[6]_i_2_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_read_done[12]_i_5_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg_n_0_[2]\,
      I5 => \byte_count_reg_n_0_[3]\,
      O => \state[2]_i_10_n_0\
    );
\state[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5454545455545454"
    )
        port map (
      I0 => \state_reg_n_0_[3]\,
      I1 => \state[2]_i_2_n_0\,
      I2 => \state[2]_i_3_n_0\,
      I3 => \state[2]_i_4_n_0\,
      I4 => \state[2]_i_5__0_n_0\,
      I5 => \state_reg[1]_rep_n_0\,
      O => \state[2]_i_1__0_n_0\
    );
\state[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0101010103000000"
    )
        port map (
      I0 => \state[2]_i_6_n_0\,
      I1 => \state[2]_i_7_n_0\,
      I2 => \state[2]_i_8_n_0\,
      I3 => \byte_read_done[6]_i_2_n_0\,
      I4 => ip_extra_options,
      I5 => \state[2]_i_9__0_n_0\,
      O => \state[2]_i_2_n_0\
    );
\state[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0888888800808080"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \state[3]_i_6_n_0\,
      I4 => \state[3]_i_7_n_0\,
      I5 => \byte_read_done[3]_i_3_n_0\,
      O => \state[2]_i_3_n_0\
    );
\state[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFF70"
    )
        port map (
      I0 => \bit_count_reg[1]_rep_n_0\,
      I1 => ip_header_options1(1),
      I2 => bit_count2,
      I3 => \state_reg_n_0_[0]\,
      I4 => \byte_count_extra_reg[5]_i_4_n_0\,
      O => \state[2]_i_4_n_0\
    );
\state[2]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => unknown_request1_reg_n_0,
      I1 => unknown_request4_reg_n_0,
      I2 => unknown_request3_reg_n_0,
      I3 => unknown_request2,
      I4 => start_crc_i_2_n_0,
      I5 => \state_reg_n_0_[2]\,
      O => \state[2]_i_5__0_n_0\
    );
\state[2]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \state[2]_i_10_n_0\,
      I1 => \byte_count[1]_i_7_n_0\,
      I2 => \byte_count_reg[0]_rep__0_n_0\,
      O => \state[2]_i_6_n_0\
    );
\state[2]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \byte_read_done[12]_i_5_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[3]\,
      O => \state[2]_i_7_n_0\
    );
\state[2]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \byte_read_done[3]_i_3_n_0\,
      O => \state[2]_i_8_n_0\
    );
\state[2]_i_9__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFD"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_read_done[12]_i_5_n_0\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[1]\,
      O => \state[2]_i_9__0_n_0\
    );
\state[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFCFDFDFCFFFDFD"
    )
        port map (
      I0 => \state[3]_i_3_n_0\,
      I1 => \state_reg_n_0_[3]\,
      I2 => \state[3]_i_4_n_0\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \state_reg_n_0_[2]\,
      I5 => \state[3]_i_5_n_0\,
      O => state
    );
\state[3]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FA80"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \byte_count[10]_i_17_n_0\,
      I2 => start_crc_i_2_n_0,
      I3 => \state_reg_n_0_[0]\,
      O => \state[3]_i_10_n_0\
    );
\state[3]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FF7FFFFFFFFF"
    )
        port map (
      I0 => \state[3]_i_27_n_0\,
      I1 => \state[3]_i_28_n_0\,
      I2 => \byte_count_extra[4]_i_2_n_0\,
      I3 => \state[3]_i_29_n_0\,
      I4 => \byte_count_extra_reg[5]_i_4_n_0\,
      I5 => bit_count2,
      O => \state[3]_i_13_n_0\
    );
\state[3]_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_read_done[12]_i_5_n_0\,
      I3 => \byte_count_reg_n_0_[2]\,
      O => \state[3]_i_14_n_0\
    );
\state[3]_i_15\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"337F"
    )
        port map (
      I0 => \byte_read_done[6]_i_2_n_0\,
      I1 => \byte_read_done[3]_i_3_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_read_done[3]_i_4_n_0\,
      O => \state[3]_i_15_n_0\
    );
\state[3]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_read_done[12]_i_5_n_0\,
      O => \state[3]_i_16_n_0\
    );
\state[3]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => \state[0]_i_9_n_0\,
      I1 => \byte_count_reg_n_0_[9]\,
      I2 => \byte_count_reg_n_0_[8]\,
      O => \state[3]_i_18_n_0\
    );
\state[3]_i_19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555554"
    )
        port map (
      I0 => \byte_count_reg_n_0_[10]\,
      I1 => \zero_counter_reg_n_0_[4]\,
      I2 => \zero_counter_reg_n_0_[2]\,
      I3 => \zero_counter_reg_n_0_[0]\,
      I4 => \zero_counter_reg_n_0_[1]\,
      I5 => \zero_counter_reg_n_0_[3]\,
      O => \state[3]_i_19_n_0\
    );
\state[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000080000000"
    )
        port map (
      I0 => \state[3]_i_6_n_0\,
      I1 => \state[3]_i_7_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \state_reg_n_0_[0]\,
      I4 => \state_reg[1]_rep_n_0\,
      I5 => \state_reg_n_0_[3]\,
      O => \state[3]_i_2_n_0\
    );
\state[3]_i_20\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"81"
    )
        port map (
      I0 => \state[0]_i_9_n_0\,
      I1 => \byte_count_reg_n_0_[8]\,
      I2 => \byte_count_reg_n_0_[9]\,
      O => \state[3]_i_20_n_0\
    );
\state[3]_i_21\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4147"
    )
        port map (
      I0 => \byte_count_extra_reg_n_0_[3]\,
      I1 => ip_options_count_max(3),
      I2 => ip_options_count_max(2),
      I3 => \byte_count_extra_reg_n_0_[2]\,
      O => \state[3]_i_21_n_0\
    );
\state[3]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \byte_count_extra_reg_n_0_[0]\,
      I1 => \byte_count_extra_reg_n_0_[1]\,
      O => \state[3]_i_22_n_0\
    );
\state[3]_i_23\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => ip_options_count_max(5),
      I1 => ip_options_count_max(4),
      I2 => ip_options_count_max(3),
      I3 => ip_options_count_max(2),
      O => \state[3]_i_23_n_0\
    );
\state[3]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9090900609090990"
    )
        port map (
      I0 => ip_options_count_max(5),
      I1 => \byte_count_extra_reg_n_0_[5]\,
      I2 => ip_options_count_max(4),
      I3 => ip_options_count_max(3),
      I4 => ip_options_count_max(2),
      I5 => \byte_count_extra_reg_n_0_[4]\,
      O => \state[3]_i_24_n_0\
    );
\state[3]_i_25\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0690"
    )
        port map (
      I0 => ip_options_count_max(3),
      I1 => \byte_count_extra_reg_n_0_[3]\,
      I2 => ip_options_count_max(2),
      I3 => \byte_count_extra_reg_n_0_[2]\,
      O => \state[3]_i_25_n_0\
    );
\state[3]_i_26\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \byte_count_extra_reg_n_0_[1]\,
      I1 => \byte_count_extra_reg_n_0_[0]\,
      O => \state[3]_i_26_n_0\
    );
\state[3]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9090900609090990"
    )
        port map (
      I0 => ip_options_count_max(5),
      I1 => \byte_count_extra_reg_n_0_[5]\,
      I2 => ip_options_count_max(4),
      I3 => ip_options_count_max(3),
      I4 => ip_options_count_max(2),
      I5 => \byte_count_extra_reg_n_0_[4]\,
      O => \state[3]_i_27_n_0\
    );
\state[3]_i_28\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0690"
    )
        port map (
      I0 => ip_options_count_max(3),
      I1 => \byte_count_extra_reg_n_0_[3]\,
      I2 => ip_options_count_max(2),
      I3 => \byte_count_extra_reg_n_0_[2]\,
      O => \state[3]_i_28_n_0\
    );
\state[3]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => ip_options_count_max(2),
      I1 => ip_options_count_max(3),
      I2 => ip_options_count_max(4),
      I3 => ip_options_count_max(5),
      O => \state[3]_i_29_n_0\
    );
\state[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000077F70000"
    )
        port map (
      I0 => \state_reg[1]_rep_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \state[3]_i_8_n_0\,
      I3 => \state[3]_i_9_n_0\,
      I4 => \state[3]_i_10_n_0\,
      I5 => \state[0]_i_3_n_0\,
      O => \state[3]_i_3_n_0\
    );
\state[3]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => \state[0]_i_9_n_0\,
      I1 => \byte_count_reg_n_0_[7]\,
      I2 => \byte_count_reg_n_0_[6]\,
      O => \state[3]_i_30_n_0\
    );
\state[3]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1F01"
    )
        port map (
      I0 => \byte_count_reg_n_0_[4]\,
      I1 => \state[3]_i_38_n_0\,
      I2 => \byte_count_reg_n_0_[5]\,
      I3 => \state[0]_i_9_n_0\,
      O => \state[3]_i_31_n_0\
    );
\state[3]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55540001FD555403"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \zero_counter_reg_n_0_[1]\,
      I2 => \zero_counter_reg_n_0_[0]\,
      I3 => \zero_counter_reg_n_0_[2]\,
      I4 => \zero_counter_reg_n_0_[3]\,
      I5 => \byte_count_reg_n_0_[2]\,
      O => \state[3]_i_32_n_0\
    );
\state[3]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0D13"
    )
        port map (
      I0 => \byte_count_reg[0]_rep_n_0\,
      I1 => \zero_counter_reg_n_0_[0]\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \zero_counter_reg_n_0_[1]\,
      O => \state[3]_i_33_n_0\
    );
\state[3]_i_34\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"81"
    )
        port map (
      I0 => \state[0]_i_9_n_0\,
      I1 => \byte_count_reg_n_0_[7]\,
      I2 => \byte_count_reg_n_0_[6]\,
      O => \state[3]_i_34_n_0\
    );
\state[3]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0990"
    )
        port map (
      I0 => \state[0]_i_9_n_0\,
      I1 => \byte_count_reg_n_0_[5]\,
      I2 => \state[3]_i_38_n_0\,
      I3 => \byte_count_reg_n_0_[4]\,
      O => \state[3]_i_35_n_0\
    );
\state[3]_i_36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9090900609090990"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[3]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \zero_counter_reg_n_0_[2]\,
      I3 => \zero_counter_reg_n_0_[1]\,
      I4 => \zero_counter_reg_n_0_[0]\,
      I5 => \byte_count_reg_n_0_[2]\,
      O => \state[3]_i_36_n_0\
    );
\state[3]_i_37\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0690"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \zero_counter_reg_n_0_[0]\,
      I3 => \byte_count_reg[0]_rep_n_0\,
      O => \state[3]_i_37_n_0\
    );
\state[3]_i_38\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0001FFFE"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[2]\,
      I1 => \zero_counter_reg_n_0_[0]\,
      I2 => \zero_counter_reg_n_0_[1]\,
      I3 => \zero_counter_reg_n_0_[3]\,
      I4 => \zero_counter_reg_n_0_[4]\,
      O => \state[3]_i_38_n_0\
    );
\state[3]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40404040C000C0C0"
    )
        port map (
      I0 => \byte_read_done[3]_i_4_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => start_crc2,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => \state_reg_n_0_[0]\,
      O => \state[3]_i_4_n_0\
    );
\state[3]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4C404C4C40404040"
    )
        port map (
      I0 => start_crc277_in,
      I1 => \byte_read_done[3]_i_3_n_0\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \byte_read_done[6]_i_2_n_0\,
      I4 => bit_count2,
      I5 => \state[3]_i_13_n_0\,
      O => \state[3]_i_5_n_0\
    );
\state[3]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \byte_count_reg[0]_rep__1_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      O => \state[3]_i_6_n_0\
    );
\state[3]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => \bit_count_reg[1]_rep_n_0\,
      I2 => \byte_read_done[3]_i_4_n_0\,
      O => \state[3]_i_7_n_0\
    );
\state[3]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EBABEBBB"
    )
        port map (
      I0 => \byte_read_done[12]_i_5_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[1]\,
      O => \state[3]_i_8_n_0\
    );
\state[3]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFFFEFEFEFFFF"
    )
        port map (
      I0 => \byte_read_done[1]_i_4_n_0\,
      I1 => \state[3]_i_14_n_0\,
      I2 => \state[3]_i_15_n_0\,
      I3 => \state[3]_i_16_n_0\,
      I4 => \state[2]_i_9__0_n_0\,
      I5 => \byte_read_done[6]_i_2_n_0\,
      O => \state[3]_i_9_n_0\
    );
\state_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => state,
      CLR => \state_reg[3]_0\,
      D => \state[0]_i_1__1_n_0\,
      Q => \state_reg_n_0_[0]\
    );
\state_reg[0]_i_2\: unisim.vcomponents.MUXF7
     port map (
      I0 => \state[0]_i_6_n_0\,
      I1 => \state[0]_i_7_n_0\,
      O => \state_reg[0]_i_2_n_0\,
      S => \state_reg[1]_rep_n_0\
    );
\state_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => state,
      CLR => \state_reg[3]_0\,
      D => \state[1]_i_1__1_n_0\,
      Q => \state_reg_n_0_[1]\
    );
\state_reg[1]_i_8\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => start_crc1,
      CO(2) => \state_reg[1]_i_8_n_1\,
      CO(1) => \state_reg[1]_i_8_n_2\,
      CO(0) => \state_reg[1]_i_8_n_3\,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_state_reg[1]_i_8_O_UNCONNECTED\(3 downto 0),
      S(3) => \state[1]_i_11_n_0\,
      S(2) => \state[1]_i_12_n_0\,
      S(1) => \state[1]_i_13_n_0\,
      S(0) => \state[1]_i_14_n_0\
    );
\state_reg[1]_rep\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => state,
      CLR => \state_reg[3]_0\,
      D => \state[1]_rep_i_1_n_0\,
      Q => \state_reg[1]_rep_n_0\
    );
\state_reg[1]_rep__0\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => state,
      CLR => \state_reg[3]_0\,
      D => \state[1]_rep_i_1__0_n_0\,
      Q => \state_reg[1]_rep__0_n_0\
    );
\state_reg[1]_rep__1\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => state,
      CLR => \state_reg[3]_0\,
      D => \state[1]_rep_i_1__1_n_0\,
      Q => \state_reg[1]_rep__1_n_0\
    );
\state_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => state,
      CLR => \state_reg[3]_0\,
      D => \state[2]_i_1__0_n_0\,
      Q => \state_reg_n_0_[2]\
    );
\state_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => state,
      CLR => \state_reg[3]_0\,
      D => \state[3]_i_2_n_0\,
      Q => \state_reg_n_0_[3]\
    );
\state_reg[3]_i_11\: unisim.vcomponents.CARRY4
     port map (
      CI => \state_reg[3]_i_17_n_0\,
      CO(3 downto 2) => \NLW_state_reg[3]_i_11_CO_UNCONNECTED\(3 downto 2),
      CO(1) => start_crc2,
      CO(0) => \state_reg[3]_i_11_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \state[3]_i_18_n_0\,
      O(3 downto 0) => \NLW_state_reg[3]_i_11_O_UNCONNECTED\(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => \state[3]_i_19_n_0\,
      S(0) => \state[3]_i_20_n_0\
    );
\state_reg[3]_i_12\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => bit_count2,
      CO(2) => \state_reg[3]_i_12_n_1\,
      CO(1) => \state_reg[3]_i_12_n_2\,
      CO(0) => \state_reg[3]_i_12_n_3\,
      CYINIT => '1',
      DI(3) => '0',
      DI(2) => \byte_count_extra[5]_i_9_n_0\,
      DI(1) => \state[3]_i_21_n_0\,
      DI(0) => \state[3]_i_22_n_0\,
      O(3 downto 0) => \NLW_state_reg[3]_i_12_O_UNCONNECTED\(3 downto 0),
      S(3) => \state[3]_i_23_n_0\,
      S(2) => \state[3]_i_24_n_0\,
      S(1) => \state[3]_i_25_n_0\,
      S(0) => \state[3]_i_26_n_0\
    );
\state_reg[3]_i_17\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \state_reg[3]_i_17_n_0\,
      CO(2) => \state_reg[3]_i_17_n_1\,
      CO(1) => \state_reg[3]_i_17_n_2\,
      CO(0) => \state_reg[3]_i_17_n_3\,
      CYINIT => '1',
      DI(3) => \state[3]_i_30_n_0\,
      DI(2) => \state[3]_i_31_n_0\,
      DI(1) => \state[3]_i_32_n_0\,
      DI(0) => \state[3]_i_33_n_0\,
      O(3 downto 0) => \NLW_state_reg[3]_i_17_O_UNCONNECTED\(3 downto 0),
      S(3) => \state[3]_i_34_n_0\,
      S(2) => \state[3]_i_35_n_0\,
      S(1) => \state[3]_i_36_n_0\,
      S(0) => \state[3]_i_37_n_0\
    );
stop_crc_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BF80"
    )
        port map (
      I0 => stop_crc_i_2_n_0,
      I1 => stop_crc_i_3_n_0,
      I2 => \byte_count[10]_i_11_n_0\,
      I3 => udp_datasum_done14_out,
      O => stop_crc_i_1_n_0
    );
stop_crc_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"54475777"
    )
        port map (
      I0 => \byte_read_done[3]_i_3_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => start_crc_i_2_n_0,
      O => stop_crc_i_2_n_0
    );
stop_crc_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000FFFAABFFBBF"
    )
        port map (
      I0 => stop_crc_i_4_n_0,
      I1 => start_crc_i_2_n_0,
      I2 => \state_reg_n_0_[0]\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => \state_reg_n_0_[2]\,
      O => stop_crc_i_3_n_0
    );
stop_crc_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state[0]_i_3_n_0\,
      I1 => eth_rxd(1),
      O => stop_crc_i_4_n_0
    );
stop_crc_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => stop_crc_i_1_n_0,
      Q => udp_datasum_done14_out,
      R => '0'
    );
\temp_data[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \temp_data[1]_i_2_n_0\,
      I2 => \temp_data[4]_i_2_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => temp_data(0),
      O => \temp_data[0]_i_1_n_0\
    );
\temp_data[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \temp_data[1]_i_2_n_0\,
      I2 => \temp_data[5]_i_3_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => temp_data(1),
      O => \temp_data[1]_i_1_n_0\
    );
\temp_data[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAA2AAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => start_crc277_in,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \temp_data[5]_i_4_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => ip_header_options1(1),
      O => \temp_data[1]_i_2_n_0\
    );
\temp_data[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \temp_data[3]_i_2_n_0\,
      I2 => \temp_data[6]_i_2_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => temp_data(2),
      O => \temp_data[2]_i_1_n_0\
    );
\temp_data[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DDDDFDDD00002000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \temp_data[3]_i_2_n_0\,
      I2 => \temp_data[7]_i_3_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \bit_count_reg[1]_rep_n_0\,
      I5 => temp_data(3),
      O => \temp_data[3]_i_1_n_0\
    );
\temp_data[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \source_mac[35]_i_2_n_0\,
      I4 => start_crc277_in,
      I5 => valid_data_byte_read_i_3_n_0,
      O => \temp_data[3]_i_2_n_0\
    );
\temp_data[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDDDDDDD20000000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \temp_data[5]_i_2_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \temp_data[4]_i_2_n_0\,
      I5 => temp_data(4),
      O => \temp_data[4]_i_1_n_0\
    );
\temp_data[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rxd(0),
      I1 => ip_header_options1(1),
      O => \temp_data[4]_i_2_n_0\
    );
\temp_data[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDDDDDDD20000000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \temp_data[5]_i_2_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \temp_data[5]_i_3_n_0\,
      I5 => temp_data(5),
      O => \temp_data[5]_i_1_n_0\
    );
\temp_data[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA2AAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => start_crc277_in,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \temp_data[5]_i_4_n_0\,
      I4 => \byte_read_done[3]_i_3_n_0\,
      I5 => ip_header_options1(1),
      O => \temp_data[5]_i_2_n_0\
    );
\temp_data[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rxd(1),
      I1 => ip_header_options1(1),
      O => \temp_data[5]_i_3_n_0\
    );
\temp_data[5]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \state_reg[1]_rep_n_0\,
      I2 => \state_reg_n_0_[0]\,
      O => \temp_data[5]_i_4_n_0\
    );
\temp_data[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDDDDDDD20000000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \temp_data[7]_i_2_n_0\,
      I2 => \bit_count_reg[1]_rep_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \temp_data[6]_i_2_n_0\,
      I5 => temp_data(6),
      O => \temp_data[6]_i_1_n_0\
    );
\temp_data[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => eth_rxd(0),
      O => \temp_data[6]_i_2_n_0\
    );
\temp_data[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDDDDDDD20000000"
    )
        port map (
      I0 => eth_rstn,
      I1 => \temp_data[7]_i_2_n_0\,
      I2 => \temp_data[7]_i_3_n_0\,
      I3 => \bit_count_reg[1]_rep_n_0\,
      I4 => \state_reg_n_0_[2]\,
      I5 => temp_data(7),
      O => \temp_data[7]_i_1_n_0\
    );
\temp_data[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA8AAAAAAAAAAAAA"
    )
        port map (
      I0 => \bytes00[15]_i_4_n_0\,
      I1 => \byte_count[10]_i_18_n_0\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => \state_reg_n_0_[2]\,
      I5 => \byte_read_done[3]_i_3_n_0\,
      O => \temp_data[7]_i_2_n_0\
    );
\temp_data[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip_header_options1(1),
      I1 => eth_rxd(1),
      O => \temp_data[7]_i_3_n_0\
    );
\temp_data_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \temp_data[0]_i_1_n_0\,
      Q => temp_data(0),
      R => '0'
    );
\temp_data_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \temp_data[1]_i_1_n_0\,
      Q => temp_data(1),
      R => '0'
    );
\temp_data_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \temp_data[2]_i_1_n_0\,
      Q => temp_data(2),
      R => '0'
    );
\temp_data_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \temp_data[3]_i_1_n_0\,
      Q => temp_data(3),
      R => '0'
    );
\temp_data_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \temp_data[4]_i_1_n_0\,
      Q => temp_data(4),
      R => '0'
    );
\temp_data_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \temp_data[5]_i_1_n_0\,
      Q => temp_data(5),
      R => '0'
    );
\temp_data_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \temp_data[6]_i_1_n_0\,
      Q => temp_data(6),
      R => '0'
    );
\temp_data_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \temp_data[7]_i_1_n_0\,
      Q => temp_data(7),
      R => '0'
    );
\udp_data_sum[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => valid_data_byte_read_reg_n_0,
      I1 => start_crc_reg_n_0,
      O => edge_count_data0
    );
\udp_data_sum[0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => temp_data(3),
      I1 => \edge_count_data__0\,
      I2 => udp_data_sum_reg(3),
      O => \udp_data_sum[0]_i_3_n_0\
    );
\udp_data_sum[0]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => temp_data(2),
      I1 => \edge_count_data__0\,
      I2 => udp_data_sum_reg(2),
      O => \udp_data_sum[0]_i_4_n_0\
    );
\udp_data_sum[0]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => temp_data(1),
      I1 => \edge_count_data__0\,
      I2 => udp_data_sum_reg(1),
      O => \udp_data_sum[0]_i_5_n_0\
    );
\udp_data_sum[0]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \edge_count_data__0\,
      I1 => temp_data(0),
      I2 => udp_data_sum_reg(0),
      O => \udp_data_sum[0]_i_6_n_0\
    );
\udp_data_sum[12]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \edge_count_data__0\,
      I1 => temp_data(7),
      I2 => udp_data_sum_reg(15),
      O => \udp_data_sum[12]_i_2_n_0\
    );
\udp_data_sum[12]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \edge_count_data__0\,
      I1 => temp_data(6),
      I2 => udp_data_sum_reg(14),
      O => \udp_data_sum[12]_i_3_n_0\
    );
\udp_data_sum[12]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \edge_count_data__0\,
      I1 => temp_data(5),
      I2 => udp_data_sum_reg(13),
      O => \udp_data_sum[12]_i_4_n_0\
    );
\udp_data_sum[12]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \edge_count_data__0\,
      I1 => temp_data(4),
      I2 => udp_data_sum_reg(12),
      O => \udp_data_sum[12]_i_5_n_0\
    );
\udp_data_sum[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => temp_data(7),
      I1 => \edge_count_data__0\,
      I2 => udp_data_sum_reg(7),
      O => \udp_data_sum[4]_i_2_n_0\
    );
\udp_data_sum[4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => temp_data(6),
      I1 => \edge_count_data__0\,
      I2 => udp_data_sum_reg(6),
      O => \udp_data_sum[4]_i_3_n_0\
    );
\udp_data_sum[4]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => temp_data(5),
      I1 => \edge_count_data__0\,
      I2 => udp_data_sum_reg(5),
      O => \udp_data_sum[4]_i_4_n_0\
    );
\udp_data_sum[4]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => temp_data(4),
      I1 => \edge_count_data__0\,
      I2 => udp_data_sum_reg(4),
      O => \udp_data_sum[4]_i_5_n_0\
    );
\udp_data_sum[8]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \edge_count_data__0\,
      I1 => temp_data(3),
      I2 => udp_data_sum_reg(11),
      O => \udp_data_sum[8]_i_2_n_0\
    );
\udp_data_sum[8]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \edge_count_data__0\,
      I1 => temp_data(2),
      I2 => udp_data_sum_reg(10),
      O => \udp_data_sum[8]_i_3_n_0\
    );
\udp_data_sum[8]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \edge_count_data__0\,
      I1 => temp_data(1),
      I2 => udp_data_sum_reg(9),
      O => \udp_data_sum[8]_i_4_n_0\
    );
\udp_data_sum[8]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \edge_count_data__0\,
      I1 => temp_data(0),
      I2 => udp_data_sum_reg(8),
      O => \udp_data_sum[8]_i_5_n_0\
    );
\udp_data_sum_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[0]_i_2_n_7\,
      Q => udp_data_sum_reg(0),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \udp_data_sum_reg[0]_i_2_n_0\,
      CO(2) => \udp_data_sum_reg[0]_i_2_n_1\,
      CO(1) => \udp_data_sum_reg[0]_i_2_n_2\,
      CO(0) => \udp_data_sum_reg[0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => udp_data_sum_reg(3 downto 0),
      O(3) => \udp_data_sum_reg[0]_i_2_n_4\,
      O(2) => \udp_data_sum_reg[0]_i_2_n_5\,
      O(1) => \udp_data_sum_reg[0]_i_2_n_6\,
      O(0) => \udp_data_sum_reg[0]_i_2_n_7\,
      S(3) => \udp_data_sum[0]_i_3_n_0\,
      S(2) => \udp_data_sum[0]_i_4_n_0\,
      S(1) => \udp_data_sum[0]_i_5_n_0\,
      S(0) => \udp_data_sum[0]_i_6_n_0\
    );
\udp_data_sum_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[8]_i_1_n_5\,
      Q => udp_data_sum_reg(10),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[8]_i_1_n_4\,
      Q => udp_data_sum_reg(11),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[12]_i_1_n_7\,
      Q => udp_data_sum_reg(12),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_data_sum_reg[8]_i_1_n_0\,
      CO(3) => \udp_data_sum_reg[12]_i_1_n_0\,
      CO(2) => \udp_data_sum_reg[12]_i_1_n_1\,
      CO(1) => \udp_data_sum_reg[12]_i_1_n_2\,
      CO(0) => \udp_data_sum_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => udp_data_sum_reg(15 downto 12),
      O(3) => \udp_data_sum_reg[12]_i_1_n_4\,
      O(2) => \udp_data_sum_reg[12]_i_1_n_5\,
      O(1) => \udp_data_sum_reg[12]_i_1_n_6\,
      O(0) => \udp_data_sum_reg[12]_i_1_n_7\,
      S(3) => \udp_data_sum[12]_i_2_n_0\,
      S(2) => \udp_data_sum[12]_i_3_n_0\,
      S(1) => \udp_data_sum[12]_i_4_n_0\,
      S(0) => \udp_data_sum[12]_i_5_n_0\
    );
\udp_data_sum_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[12]_i_1_n_6\,
      Q => udp_data_sum_reg(13),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[12]_i_1_n_5\,
      Q => udp_data_sum_reg(14),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[12]_i_1_n_4\,
      Q => udp_data_sum_reg(15),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[16]_i_1_n_7\,
      Q => udp_data_sum_reg(16),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_data_sum_reg[12]_i_1_n_0\,
      CO(3) => \udp_data_sum_reg[16]_i_1_n_0\,
      CO(2) => \udp_data_sum_reg[16]_i_1_n_1\,
      CO(1) => \udp_data_sum_reg[16]_i_1_n_2\,
      CO(0) => \udp_data_sum_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \udp_data_sum_reg[16]_i_1_n_4\,
      O(2) => \udp_data_sum_reg[16]_i_1_n_5\,
      O(1) => \udp_data_sum_reg[16]_i_1_n_6\,
      O(0) => \udp_data_sum_reg[16]_i_1_n_7\,
      S(3 downto 0) => udp_data_sum_reg(19 downto 16)
    );
\udp_data_sum_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[16]_i_1_n_6\,
      Q => udp_data_sum_reg(17),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[16]_i_1_n_5\,
      Q => udp_data_sum_reg(18),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[16]_i_1_n_4\,
      Q => udp_data_sum_reg(19),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[0]_i_2_n_6\,
      Q => udp_data_sum_reg(1),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[20]_i_1_n_7\,
      Q => udp_data_sum_reg(20),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[20]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_data_sum_reg[16]_i_1_n_0\,
      CO(3) => \NLW_udp_data_sum_reg[20]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \udp_data_sum_reg[20]_i_1_n_1\,
      CO(1) => \udp_data_sum_reg[20]_i_1_n_2\,
      CO(0) => \udp_data_sum_reg[20]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \udp_data_sum_reg[20]_i_1_n_4\,
      O(2) => \udp_data_sum_reg[20]_i_1_n_5\,
      O(1) => \udp_data_sum_reg[20]_i_1_n_6\,
      O(0) => \udp_data_sum_reg[20]_i_1_n_7\,
      S(3 downto 0) => udp_data_sum_reg(23 downto 20)
    );
\udp_data_sum_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[20]_i_1_n_6\,
      Q => udp_data_sum_reg(21),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[20]_i_1_n_5\,
      Q => udp_data_sum_reg(22),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[20]_i_1_n_4\,
      Q => udp_data_sum_reg(23),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[0]_i_2_n_5\,
      Q => udp_data_sum_reg(2),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[0]_i_2_n_4\,
      Q => udp_data_sum_reg(3),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[4]_i_1_n_7\,
      Q => udp_data_sum_reg(4),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_data_sum_reg[0]_i_2_n_0\,
      CO(3) => \udp_data_sum_reg[4]_i_1_n_0\,
      CO(2) => \udp_data_sum_reg[4]_i_1_n_1\,
      CO(1) => \udp_data_sum_reg[4]_i_1_n_2\,
      CO(0) => \udp_data_sum_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => udp_data_sum_reg(7 downto 4),
      O(3) => \udp_data_sum_reg[4]_i_1_n_4\,
      O(2) => \udp_data_sum_reg[4]_i_1_n_5\,
      O(1) => \udp_data_sum_reg[4]_i_1_n_6\,
      O(0) => \udp_data_sum_reg[4]_i_1_n_7\,
      S(3) => \udp_data_sum[4]_i_2_n_0\,
      S(2) => \udp_data_sum[4]_i_3_n_0\,
      S(1) => \udp_data_sum[4]_i_4_n_0\,
      S(0) => \udp_data_sum[4]_i_5_n_0\
    );
\udp_data_sum_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[4]_i_1_n_6\,
      Q => udp_data_sum_reg(5),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[4]_i_1_n_5\,
      Q => udp_data_sum_reg(6),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[4]_i_1_n_4\,
      Q => udp_data_sum_reg(7),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[8]_i_1_n_7\,
      Q => udp_data_sum_reg(8),
      R => udp_datasum_done14_out
    );
\udp_data_sum_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_data_sum_reg[4]_i_1_n_0\,
      CO(3) => \udp_data_sum_reg[8]_i_1_n_0\,
      CO(2) => \udp_data_sum_reg[8]_i_1_n_1\,
      CO(1) => \udp_data_sum_reg[8]_i_1_n_2\,
      CO(0) => \udp_data_sum_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => udp_data_sum_reg(11 downto 8),
      O(3) => \udp_data_sum_reg[8]_i_1_n_4\,
      O(2) => \udp_data_sum_reg[8]_i_1_n_5\,
      O(1) => \udp_data_sum_reg[8]_i_1_n_6\,
      O(0) => \udp_data_sum_reg[8]_i_1_n_7\,
      S(3) => \udp_data_sum[8]_i_2_n_0\,
      S(2) => \udp_data_sum[8]_i_3_n_0\,
      S(1) => \udp_data_sum[8]_i_4_n_0\,
      S(0) => \udp_data_sum[8]_i_5_n_0\
    );
\udp_data_sum_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => edge_count_data0,
      D => \udp_data_sum_reg[8]_i_1_n_6\,
      Q => udp_data_sum_reg(9),
      R => udp_datasum_done14_out
    );
udp_datasum_done_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"23"
    )
        port map (
      I0 => udp_datasum_done_reg_n_0,
      I1 => udp_datasum_done14_out,
      I2 => start_crc_reg_n_0,
      O => udp_datasum_done_i_1_n_0
    );
udp_datasum_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => udp_datasum_done_i_1_n_0,
      Q => udp_datasum_done_reg_n_0,
      R => '0'
    );
\udp_hcs_calc[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => udp_hcs_calc,
      I1 => udp_hcs_done,
      O => \udp_hcs_calc[15]_i_1_n_0\
    );
\udp_hcs_calc_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(0),
      Q => \udp_hcs_calc__0\(0),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[10]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(10),
      Q => \udp_hcs_calc__0\(10),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[11]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(11),
      Q => \udp_hcs_calc__0\(11),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[12]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(12),
      Q => \udp_hcs_calc__0\(12),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[13]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(13),
      Q => \udp_hcs_calc__0\(13),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[14]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(14),
      Q => \udp_hcs_calc__0\(14),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[15]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(15),
      Q => \udp_hcs_calc__0\(15),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(1),
      Q => \udp_hcs_calc__0\(1),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(2),
      Q => \udp_hcs_calc__0\(2),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(3),
      Q => \udp_hcs_calc__0\(3),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[4]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(4),
      Q => \udp_hcs_calc__0\(4),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[5]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(5),
      Q => \udp_hcs_calc__0\(5),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[6]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(6),
      Q => \udp_hcs_calc__0\(6),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(7),
      Q => \udp_hcs_calc__0\(7),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[8]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(8),
      Q => \udp_hcs_calc__0\(8),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_reg[9]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2__0\(9),
      Q => \udp_hcs_calc__0\(9),
      S => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1[11]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[11]\,
      I1 => udp_data_sum_reg(11),
      O => \udp_hcs_calc_temp1[11]_i_2_n_0\
    );
\udp_hcs_calc_temp1[11]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[10]\,
      I1 => udp_data_sum_reg(10),
      O => \udp_hcs_calc_temp1[11]_i_3_n_0\
    );
\udp_hcs_calc_temp1[11]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[9]\,
      I1 => udp_data_sum_reg(9),
      O => \udp_hcs_calc_temp1[11]_i_4_n_0\
    );
\udp_hcs_calc_temp1[11]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[8]\,
      I1 => udp_data_sum_reg(8),
      O => \udp_hcs_calc_temp1[11]_i_5_n_0\
    );
\udp_hcs_calc_temp1[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[15]\,
      I1 => udp_data_sum_reg(15),
      O => \udp_hcs_calc_temp1[15]_i_2_n_0\
    );
\udp_hcs_calc_temp1[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[14]\,
      I1 => udp_data_sum_reg(14),
      O => \udp_hcs_calc_temp1[15]_i_3_n_0\
    );
\udp_hcs_calc_temp1[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[13]\,
      I1 => udp_data_sum_reg(13),
      O => \udp_hcs_calc_temp1[15]_i_4_n_0\
    );
\udp_hcs_calc_temp1[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[12]\,
      I1 => udp_data_sum_reg(12),
      O => \udp_hcs_calc_temp1[15]_i_5_n_0\
    );
\udp_hcs_calc_temp1[19]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[19]\,
      I1 => udp_data_sum_reg(19),
      O => \udp_hcs_calc_temp1[19]_i_2_n_0\
    );
\udp_hcs_calc_temp1[19]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[18]\,
      I1 => udp_data_sum_reg(18),
      O => \udp_hcs_calc_temp1[19]_i_3_n_0\
    );
\udp_hcs_calc_temp1[19]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[17]\,
      I1 => udp_data_sum_reg(17),
      O => \udp_hcs_calc_temp1[19]_i_4_n_0\
    );
\udp_hcs_calc_temp1[19]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[16]\,
      I1 => udp_data_sum_reg(16),
      O => \udp_hcs_calc_temp1[19]_i_5_n_0\
    );
\udp_hcs_calc_temp1[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => udp_datasum_done_reg_n_0,
      I1 => udp_presum_done,
      O => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1[23]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => udp_hcs_calc_temp1,
      I1 => udp_hcs_done,
      O => \udp_hcs_calc_temp1[23]_i_2_n_0\
    );
\udp_hcs_calc_temp1[23]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => udp_data_sum_reg(23),
      I1 => \udp_presum_reg_n_0_[23]\,
      O => \udp_hcs_calc_temp1[23]_i_4_n_0\
    );
\udp_hcs_calc_temp1[23]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[22]\,
      I1 => udp_data_sum_reg(22),
      O => \udp_hcs_calc_temp1[23]_i_5_n_0\
    );
\udp_hcs_calc_temp1[23]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[21]\,
      I1 => udp_data_sum_reg(21),
      O => \udp_hcs_calc_temp1[23]_i_6_n_0\
    );
\udp_hcs_calc_temp1[23]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[20]\,
      I1 => udp_data_sum_reg(20),
      O => \udp_hcs_calc_temp1[23]_i_7_n_0\
    );
\udp_hcs_calc_temp1[3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[3]\,
      I1 => udp_data_sum_reg(3),
      O => \udp_hcs_calc_temp1[3]_i_2_n_0\
    );
\udp_hcs_calc_temp1[3]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[2]\,
      I1 => udp_data_sum_reg(2),
      O => \udp_hcs_calc_temp1[3]_i_3_n_0\
    );
\udp_hcs_calc_temp1[3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[1]\,
      I1 => udp_data_sum_reg(1),
      O => \udp_hcs_calc_temp1[3]_i_4_n_0\
    );
\udp_hcs_calc_temp1[3]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[0]\,
      I1 => udp_data_sum_reg(0),
      O => \udp_hcs_calc_temp1[3]_i_5_n_0\
    );
\udp_hcs_calc_temp1[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[7]\,
      I1 => udp_data_sum_reg(7),
      O => \udp_hcs_calc_temp1[7]_i_2_n_0\
    );
\udp_hcs_calc_temp1[7]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[6]\,
      I1 => udp_data_sum_reg(6),
      O => \udp_hcs_calc_temp1[7]_i_3_n_0\
    );
\udp_hcs_calc_temp1[7]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[5]\,
      I1 => udp_data_sum_reg(5),
      O => \udp_hcs_calc_temp1[7]_i_4_n_0\
    );
\udp_hcs_calc_temp1[7]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[4]\,
      I1 => udp_data_sum_reg(4),
      O => \udp_hcs_calc_temp1[7]_i_5_n_0\
    );
\udp_hcs_calc_temp1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[3]_i_1_n_7\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[0]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[11]_i_1_n_5\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[10]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[11]_i_1_n_4\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[11]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_hcs_calc_temp1_reg[7]_i_1_n_0\,
      CO(3) => \udp_hcs_calc_temp1_reg[11]_i_1_n_0\,
      CO(2) => \udp_hcs_calc_temp1_reg[11]_i_1_n_1\,
      CO(1) => \udp_hcs_calc_temp1_reg[11]_i_1_n_2\,
      CO(0) => \udp_hcs_calc_temp1_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum_reg_n_0_[11]\,
      DI(2) => \udp_presum_reg_n_0_[10]\,
      DI(1) => \udp_presum_reg_n_0_[9]\,
      DI(0) => \udp_presum_reg_n_0_[8]\,
      O(3) => \udp_hcs_calc_temp1_reg[11]_i_1_n_4\,
      O(2) => \udp_hcs_calc_temp1_reg[11]_i_1_n_5\,
      O(1) => \udp_hcs_calc_temp1_reg[11]_i_1_n_6\,
      O(0) => \udp_hcs_calc_temp1_reg[11]_i_1_n_7\,
      S(3) => \udp_hcs_calc_temp1[11]_i_2_n_0\,
      S(2) => \udp_hcs_calc_temp1[11]_i_3_n_0\,
      S(1) => \udp_hcs_calc_temp1[11]_i_4_n_0\,
      S(0) => \udp_hcs_calc_temp1[11]_i_5_n_0\
    );
\udp_hcs_calc_temp1_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[15]_i_1_n_7\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[12]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[15]_i_1_n_6\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[13]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[15]_i_1_n_5\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[14]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[15]_i_1_n_4\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[15]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[15]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_hcs_calc_temp1_reg[11]_i_1_n_0\,
      CO(3) => \udp_hcs_calc_temp1_reg[15]_i_1_n_0\,
      CO(2) => \udp_hcs_calc_temp1_reg[15]_i_1_n_1\,
      CO(1) => \udp_hcs_calc_temp1_reg[15]_i_1_n_2\,
      CO(0) => \udp_hcs_calc_temp1_reg[15]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum_reg_n_0_[15]\,
      DI(2) => \udp_presum_reg_n_0_[14]\,
      DI(1) => \udp_presum_reg_n_0_[13]\,
      DI(0) => \udp_presum_reg_n_0_[12]\,
      O(3) => \udp_hcs_calc_temp1_reg[15]_i_1_n_4\,
      O(2) => \udp_hcs_calc_temp1_reg[15]_i_1_n_5\,
      O(1) => \udp_hcs_calc_temp1_reg[15]_i_1_n_6\,
      O(0) => \udp_hcs_calc_temp1_reg[15]_i_1_n_7\,
      S(3) => \udp_hcs_calc_temp1[15]_i_2_n_0\,
      S(2) => \udp_hcs_calc_temp1[15]_i_3_n_0\,
      S(1) => \udp_hcs_calc_temp1[15]_i_4_n_0\,
      S(0) => \udp_hcs_calc_temp1[15]_i_5_n_0\
    );
\udp_hcs_calc_temp1_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[19]_i_1_n_7\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[16]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[19]_i_1_n_6\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[17]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[19]_i_1_n_5\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[18]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[19]_i_1_n_4\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[19]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[19]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_hcs_calc_temp1_reg[15]_i_1_n_0\,
      CO(3) => \udp_hcs_calc_temp1_reg[19]_i_1_n_0\,
      CO(2) => \udp_hcs_calc_temp1_reg[19]_i_1_n_1\,
      CO(1) => \udp_hcs_calc_temp1_reg[19]_i_1_n_2\,
      CO(0) => \udp_hcs_calc_temp1_reg[19]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum_reg_n_0_[19]\,
      DI(2) => \udp_presum_reg_n_0_[18]\,
      DI(1) => \udp_presum_reg_n_0_[17]\,
      DI(0) => \udp_presum_reg_n_0_[16]\,
      O(3) => \udp_hcs_calc_temp1_reg[19]_i_1_n_4\,
      O(2) => \udp_hcs_calc_temp1_reg[19]_i_1_n_5\,
      O(1) => \udp_hcs_calc_temp1_reg[19]_i_1_n_6\,
      O(0) => \udp_hcs_calc_temp1_reg[19]_i_1_n_7\,
      S(3) => \udp_hcs_calc_temp1[19]_i_2_n_0\,
      S(2) => \udp_hcs_calc_temp1[19]_i_3_n_0\,
      S(1) => \udp_hcs_calc_temp1[19]_i_4_n_0\,
      S(0) => \udp_hcs_calc_temp1[19]_i_5_n_0\
    );
\udp_hcs_calc_temp1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[3]_i_1_n_6\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[1]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[23]_i_3_n_7\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[20]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[23]_i_3_n_6\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[21]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[23]_i_3_n_5\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[22]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[23]_i_3_n_4\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[23]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[23]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_hcs_calc_temp1_reg[19]_i_1_n_0\,
      CO(3) => \NLW_udp_hcs_calc_temp1_reg[23]_i_3_CO_UNCONNECTED\(3),
      CO(2) => \udp_hcs_calc_temp1_reg[23]_i_3_n_1\,
      CO(1) => \udp_hcs_calc_temp1_reg[23]_i_3_n_2\,
      CO(0) => \udp_hcs_calc_temp1_reg[23]_i_3_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => \udp_presum_reg_n_0_[22]\,
      DI(1) => \udp_presum_reg_n_0_[21]\,
      DI(0) => \udp_presum_reg_n_0_[20]\,
      O(3) => \udp_hcs_calc_temp1_reg[23]_i_3_n_4\,
      O(2) => \udp_hcs_calc_temp1_reg[23]_i_3_n_5\,
      O(1) => \udp_hcs_calc_temp1_reg[23]_i_3_n_6\,
      O(0) => \udp_hcs_calc_temp1_reg[23]_i_3_n_7\,
      S(3) => \udp_hcs_calc_temp1[23]_i_4_n_0\,
      S(2) => \udp_hcs_calc_temp1[23]_i_5_n_0\,
      S(1) => \udp_hcs_calc_temp1[23]_i_6_n_0\,
      S(0) => \udp_hcs_calc_temp1[23]_i_7_n_0\
    );
\udp_hcs_calc_temp1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[3]_i_1_n_5\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[2]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[3]_i_1_n_4\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[3]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[3]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \udp_hcs_calc_temp1_reg[3]_i_1_n_0\,
      CO(2) => \udp_hcs_calc_temp1_reg[3]_i_1_n_1\,
      CO(1) => \udp_hcs_calc_temp1_reg[3]_i_1_n_2\,
      CO(0) => \udp_hcs_calc_temp1_reg[3]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum_reg_n_0_[3]\,
      DI(2) => \udp_presum_reg_n_0_[2]\,
      DI(1) => \udp_presum_reg_n_0_[1]\,
      DI(0) => \udp_presum_reg_n_0_[0]\,
      O(3) => \udp_hcs_calc_temp1_reg[3]_i_1_n_4\,
      O(2) => \udp_hcs_calc_temp1_reg[3]_i_1_n_5\,
      O(1) => \udp_hcs_calc_temp1_reg[3]_i_1_n_6\,
      O(0) => \udp_hcs_calc_temp1_reg[3]_i_1_n_7\,
      S(3) => \udp_hcs_calc_temp1[3]_i_2_n_0\,
      S(2) => \udp_hcs_calc_temp1[3]_i_3_n_0\,
      S(1) => \udp_hcs_calc_temp1[3]_i_4_n_0\,
      S(0) => \udp_hcs_calc_temp1[3]_i_5_n_0\
    );
\udp_hcs_calc_temp1_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[7]_i_1_n_7\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[4]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[7]_i_1_n_6\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[5]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[7]_i_1_n_5\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[6]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[7]_i_1_n_4\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[7]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[7]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_hcs_calc_temp1_reg[3]_i_1_n_0\,
      CO(3) => \udp_hcs_calc_temp1_reg[7]_i_1_n_0\,
      CO(2) => \udp_hcs_calc_temp1_reg[7]_i_1_n_1\,
      CO(1) => \udp_hcs_calc_temp1_reg[7]_i_1_n_2\,
      CO(0) => \udp_hcs_calc_temp1_reg[7]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum_reg_n_0_[7]\,
      DI(2) => \udp_presum_reg_n_0_[6]\,
      DI(1) => \udp_presum_reg_n_0_[5]\,
      DI(0) => \udp_presum_reg_n_0_[4]\,
      O(3) => \udp_hcs_calc_temp1_reg[7]_i_1_n_4\,
      O(2) => \udp_hcs_calc_temp1_reg[7]_i_1_n_5\,
      O(1) => \udp_hcs_calc_temp1_reg[7]_i_1_n_6\,
      O(0) => \udp_hcs_calc_temp1_reg[7]_i_1_n_7\,
      S(3) => \udp_hcs_calc_temp1[7]_i_2_n_0\,
      S(2) => \udp_hcs_calc_temp1[7]_i_3_n_0\,
      S(1) => \udp_hcs_calc_temp1[7]_i_4_n_0\,
      S(0) => \udp_hcs_calc_temp1[7]_i_5_n_0\
    );
\udp_hcs_calc_temp1_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[11]_i_1_n_7\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[8]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp1_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp1[23]_i_2_n_0\,
      D => \udp_hcs_calc_temp1_reg[11]_i_1_n_6\,
      Q => \udp_hcs_calc_temp1_reg_n_0_[9]\,
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[3]_i_2_n_7\,
      O => \udp_hcs_calc_temp2[0]_i_1_n_0\
    );
\udp_hcs_calc_temp2[10]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[11]_i_2_n_5\,
      O => \udp_hcs_calc_temp2[10]_i_1_n_0\
    );
\udp_hcs_calc_temp2[11]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[11]_i_2_n_4\,
      O => \udp_hcs_calc_temp2[11]_i_1_n_0\
    );
\udp_hcs_calc_temp2[11]_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E81717E8"
    )
        port map (
      I0 => \udp_hcs_calc_temp2__0\(7),
      I1 => \udp_hcs_calc_temp1_reg_n_0_[23]\,
      I2 => \udp_hcs_calc_temp1_reg_n_0_[7]\,
      I3 => \udp_hcs_calc_temp1_reg_n_0_[8]\,
      I4 => \udp_hcs_calc_temp2__0\(8),
      O => \udp_hcs_calc_temp2[11]_i_10_n_0\
    );
\udp_hcs_calc_temp2[11]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[10]\,
      I1 => \udp_hcs_calc_temp2__0\(10),
      O => \udp_hcs_calc_temp2[11]_i_3_n_0\
    );
\udp_hcs_calc_temp2[11]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[9]\,
      I1 => \udp_hcs_calc_temp2__0\(9),
      O => \udp_hcs_calc_temp2[11]_i_4_n_0\
    );
\udp_hcs_calc_temp2[11]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[8]\,
      I1 => \udp_hcs_calc_temp2__0\(8),
      O => \udp_hcs_calc_temp2[11]_i_5_n_0\
    );
\udp_hcs_calc_temp2[11]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[7]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[23]\,
      I2 => \udp_hcs_calc_temp2__0\(7),
      O => \udp_hcs_calc_temp2[11]_i_6_n_0\
    );
\udp_hcs_calc_temp2[11]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \udp_hcs_calc_temp2__0\(10),
      I1 => \udp_hcs_calc_temp1_reg_n_0_[10]\,
      I2 => \udp_hcs_calc_temp1_reg_n_0_[11]\,
      I3 => \udp_hcs_calc_temp2__0\(11),
      O => \udp_hcs_calc_temp2[11]_i_7_n_0\
    );
\udp_hcs_calc_temp2[11]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \udp_hcs_calc_temp2__0\(9),
      I1 => \udp_hcs_calc_temp1_reg_n_0_[9]\,
      I2 => \udp_hcs_calc_temp1_reg_n_0_[10]\,
      I3 => \udp_hcs_calc_temp2__0\(10),
      O => \udp_hcs_calc_temp2[11]_i_8_n_0\
    );
\udp_hcs_calc_temp2[11]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \udp_hcs_calc_temp2__0\(8),
      I1 => \udp_hcs_calc_temp1_reg_n_0_[8]\,
      I2 => \udp_hcs_calc_temp1_reg_n_0_[9]\,
      I3 => \udp_hcs_calc_temp2__0\(9),
      O => \udp_hcs_calc_temp2[11]_i_9_n_0\
    );
\udp_hcs_calc_temp2[12]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[15]_i_3_n_7\,
      O => \udp_hcs_calc_temp2[12]_i_1_n_0\
    );
\udp_hcs_calc_temp2[13]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[15]_i_3_n_6\,
      O => \udp_hcs_calc_temp2[13]_i_1_n_0\
    );
\udp_hcs_calc_temp2[14]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[15]_i_3_n_5\,
      O => \udp_hcs_calc_temp2[14]_i_1_n_0\
    );
\udp_hcs_calc_temp2[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => udp_hcs_calc_temp2,
      I1 => udp_hcs_done,
      O => \udp_hcs_calc_temp2[15]_i_1_n_0\
    );
\udp_hcs_calc_temp2[15]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \udp_hcs_calc_temp2__0\(11),
      I1 => \udp_hcs_calc_temp1_reg_n_0_[11]\,
      I2 => \udp_hcs_calc_temp1_reg_n_0_[12]\,
      I3 => \udp_hcs_calc_temp2__0\(12),
      O => \udp_hcs_calc_temp2[15]_i_10_n_0\
    );
\udp_hcs_calc_temp2[15]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[15]_i_3_n_4\,
      O => \udp_hcs_calc_temp2[15]_i_2_n_0\
    );
\udp_hcs_calc_temp2[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[13]\,
      I1 => \udp_hcs_calc_temp2__0\(13),
      O => \udp_hcs_calc_temp2[15]_i_4_n_0\
    );
\udp_hcs_calc_temp2[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[12]\,
      I1 => \udp_hcs_calc_temp2__0\(12),
      O => \udp_hcs_calc_temp2[15]_i_5_n_0\
    );
\udp_hcs_calc_temp2[15]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[11]\,
      I1 => \udp_hcs_calc_temp2__0\(11),
      O => \udp_hcs_calc_temp2[15]_i_6_n_0\
    );
\udp_hcs_calc_temp2[15]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \udp_hcs_calc_temp2__0\(14),
      I1 => \udp_hcs_calc_temp1_reg_n_0_[14]\,
      I2 => \udp_hcs_calc_temp1_reg_n_0_[15]\,
      I3 => \udp_hcs_calc_temp2__0\(15),
      O => \udp_hcs_calc_temp2[15]_i_7_n_0\
    );
\udp_hcs_calc_temp2[15]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \udp_hcs_calc_temp2__0\(13),
      I1 => \udp_hcs_calc_temp1_reg_n_0_[13]\,
      I2 => \udp_hcs_calc_temp1_reg_n_0_[14]\,
      I3 => \udp_hcs_calc_temp2__0\(14),
      O => \udp_hcs_calc_temp2[15]_i_8_n_0\
    );
\udp_hcs_calc_temp2[15]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \udp_hcs_calc_temp2__0\(12),
      I1 => \udp_hcs_calc_temp1_reg_n_0_[12]\,
      I2 => \udp_hcs_calc_temp1_reg_n_0_[13]\,
      I3 => \udp_hcs_calc_temp2__0\(13),
      O => \udp_hcs_calc_temp2[15]_i_9_n_0\
    );
\udp_hcs_calc_temp2[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[3]_i_2_n_6\,
      O => \udp_hcs_calc_temp2[1]_i_1_n_0\
    );
\udp_hcs_calc_temp2[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[3]_i_2_n_5\,
      O => \udp_hcs_calc_temp2[2]_i_1_n_0\
    );
\udp_hcs_calc_temp2[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[3]_i_2_n_4\,
      O => \udp_hcs_calc_temp2[3]_i_1_n_0\
    );
\udp_hcs_calc_temp2[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[2]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[18]\,
      I2 => \udp_hcs_calc_temp2__0\(2),
      O => \udp_hcs_calc_temp2[3]_i_3_n_0\
    );
\udp_hcs_calc_temp2[3]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[1]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[17]\,
      I2 => \udp_hcs_calc_temp2__0\(1),
      O => \udp_hcs_calc_temp2[3]_i_4_n_0\
    );
\udp_hcs_calc_temp2[3]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[0]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[16]\,
      I2 => \udp_hcs_calc_temp2__0\(0),
      O => \udp_hcs_calc_temp2[3]_i_5_n_0\
    );
\udp_hcs_calc_temp2[3]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[3]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[19]\,
      I2 => \udp_hcs_calc_temp2__0\(3),
      I3 => \udp_hcs_calc_temp2[3]_i_3_n_0\,
      O => \udp_hcs_calc_temp2[3]_i_6_n_0\
    );
\udp_hcs_calc_temp2[3]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[2]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[18]\,
      I2 => \udp_hcs_calc_temp2__0\(2),
      I3 => \udp_hcs_calc_temp2[3]_i_4_n_0\,
      O => \udp_hcs_calc_temp2[3]_i_7_n_0\
    );
\udp_hcs_calc_temp2[3]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[1]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[17]\,
      I2 => \udp_hcs_calc_temp2__0\(1),
      I3 => \udp_hcs_calc_temp2[3]_i_5_n_0\,
      O => \udp_hcs_calc_temp2[3]_i_8_n_0\
    );
\udp_hcs_calc_temp2[3]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[0]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[16]\,
      I2 => \udp_hcs_calc_temp2__0\(0),
      O => \udp_hcs_calc_temp2[3]_i_9_n_0\
    );
\udp_hcs_calc_temp2[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[7]_i_2_n_7\,
      O => \udp_hcs_calc_temp2[4]_i_1_n_0\
    );
\udp_hcs_calc_temp2[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[7]_i_2_n_6\,
      O => \udp_hcs_calc_temp2[5]_i_1_n_0\
    );
\udp_hcs_calc_temp2[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[7]_i_2_n_5\,
      O => \udp_hcs_calc_temp2[6]_i_1_n_0\
    );
\udp_hcs_calc_temp2[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[7]_i_2_n_4\,
      O => \udp_hcs_calc_temp2[7]_i_1_n_0\
    );
\udp_hcs_calc_temp2[7]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[4]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[20]\,
      I2 => \udp_hcs_calc_temp2__0\(4),
      I3 => \udp_hcs_calc_temp2[7]_i_6_n_0\,
      O => \udp_hcs_calc_temp2[7]_i_10_n_0\
    );
\udp_hcs_calc_temp2[7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[6]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[22]\,
      I2 => \udp_hcs_calc_temp2__0\(6),
      O => \udp_hcs_calc_temp2[7]_i_3_n_0\
    );
\udp_hcs_calc_temp2[7]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[5]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[21]\,
      I2 => \udp_hcs_calc_temp2__0\(5),
      O => \udp_hcs_calc_temp2[7]_i_4_n_0\
    );
\udp_hcs_calc_temp2[7]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[4]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[20]\,
      I2 => \udp_hcs_calc_temp2__0\(4),
      O => \udp_hcs_calc_temp2[7]_i_5_n_0\
    );
\udp_hcs_calc_temp2[7]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[3]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[19]\,
      I2 => \udp_hcs_calc_temp2__0\(3),
      O => \udp_hcs_calc_temp2[7]_i_6_n_0\
    );
\udp_hcs_calc_temp2[7]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \udp_hcs_calc_temp2[7]_i_3_n_0\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[23]\,
      I2 => \udp_hcs_calc_temp1_reg_n_0_[7]\,
      I3 => \udp_hcs_calc_temp2__0\(7),
      O => \udp_hcs_calc_temp2[7]_i_7_n_0\
    );
\udp_hcs_calc_temp2[7]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[6]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[22]\,
      I2 => \udp_hcs_calc_temp2__0\(6),
      I3 => \udp_hcs_calc_temp2[7]_i_4_n_0\,
      O => \udp_hcs_calc_temp2[7]_i_8_n_0\
    );
\udp_hcs_calc_temp2[7]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \udp_hcs_calc_temp1_reg_n_0_[5]\,
      I1 => \udp_hcs_calc_temp1_reg_n_0_[21]\,
      I2 => \udp_hcs_calc_temp2__0\(5),
      I3 => \udp_hcs_calc_temp2[7]_i_5_n_0\,
      O => \udp_hcs_calc_temp2[7]_i_9_n_0\
    );
\udp_hcs_calc_temp2[8]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[11]_i_2_n_7\,
      O => \udp_hcs_calc_temp2[8]_i_1_n_0\
    );
\udp_hcs_calc_temp2[9]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \udp_hcs_calc_temp2_reg[11]_i_2_n_6\,
      O => \udp_hcs_calc_temp2[9]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[0]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(0),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[10]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(10),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[11]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(11),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[11]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_hcs_calc_temp2_reg[7]_i_2_n_0\,
      CO(3) => \udp_hcs_calc_temp2_reg[11]_i_2_n_0\,
      CO(2) => \udp_hcs_calc_temp2_reg[11]_i_2_n_1\,
      CO(1) => \udp_hcs_calc_temp2_reg[11]_i_2_n_2\,
      CO(0) => \udp_hcs_calc_temp2_reg[11]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => \udp_hcs_calc_temp2[11]_i_3_n_0\,
      DI(2) => \udp_hcs_calc_temp2[11]_i_4_n_0\,
      DI(1) => \udp_hcs_calc_temp2[11]_i_5_n_0\,
      DI(0) => \udp_hcs_calc_temp2[11]_i_6_n_0\,
      O(3) => \udp_hcs_calc_temp2_reg[11]_i_2_n_4\,
      O(2) => \udp_hcs_calc_temp2_reg[11]_i_2_n_5\,
      O(1) => \udp_hcs_calc_temp2_reg[11]_i_2_n_6\,
      O(0) => \udp_hcs_calc_temp2_reg[11]_i_2_n_7\,
      S(3) => \udp_hcs_calc_temp2[11]_i_7_n_0\,
      S(2) => \udp_hcs_calc_temp2[11]_i_8_n_0\,
      S(1) => \udp_hcs_calc_temp2[11]_i_9_n_0\,
      S(0) => \udp_hcs_calc_temp2[11]_i_10_n_0\
    );
\udp_hcs_calc_temp2_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[12]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(12),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[13]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(13),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[14]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(14),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[15]_i_2_n_0\,
      Q => \udp_hcs_calc_temp2__0\(15),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[15]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_hcs_calc_temp2_reg[11]_i_2_n_0\,
      CO(3) => \NLW_udp_hcs_calc_temp2_reg[15]_i_3_CO_UNCONNECTED\(3),
      CO(2) => \udp_hcs_calc_temp2_reg[15]_i_3_n_1\,
      CO(1) => \udp_hcs_calc_temp2_reg[15]_i_3_n_2\,
      CO(0) => \udp_hcs_calc_temp2_reg[15]_i_3_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => \udp_hcs_calc_temp2[15]_i_4_n_0\,
      DI(1) => \udp_hcs_calc_temp2[15]_i_5_n_0\,
      DI(0) => \udp_hcs_calc_temp2[15]_i_6_n_0\,
      O(3) => \udp_hcs_calc_temp2_reg[15]_i_3_n_4\,
      O(2) => \udp_hcs_calc_temp2_reg[15]_i_3_n_5\,
      O(1) => \udp_hcs_calc_temp2_reg[15]_i_3_n_6\,
      O(0) => \udp_hcs_calc_temp2_reg[15]_i_3_n_7\,
      S(3) => \udp_hcs_calc_temp2[15]_i_7_n_0\,
      S(2) => \udp_hcs_calc_temp2[15]_i_8_n_0\,
      S(1) => \udp_hcs_calc_temp2[15]_i_9_n_0\,
      S(0) => \udp_hcs_calc_temp2[15]_i_10_n_0\
    );
\udp_hcs_calc_temp2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[1]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(1),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[2]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(2),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[3]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(3),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[3]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \udp_hcs_calc_temp2_reg[3]_i_2_n_0\,
      CO(2) => \udp_hcs_calc_temp2_reg[3]_i_2_n_1\,
      CO(1) => \udp_hcs_calc_temp2_reg[3]_i_2_n_2\,
      CO(0) => \udp_hcs_calc_temp2_reg[3]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => \udp_hcs_calc_temp2[3]_i_3_n_0\,
      DI(2) => \udp_hcs_calc_temp2[3]_i_4_n_0\,
      DI(1) => \udp_hcs_calc_temp2[3]_i_5_n_0\,
      DI(0) => '0',
      O(3) => \udp_hcs_calc_temp2_reg[3]_i_2_n_4\,
      O(2) => \udp_hcs_calc_temp2_reg[3]_i_2_n_5\,
      O(1) => \udp_hcs_calc_temp2_reg[3]_i_2_n_6\,
      O(0) => \udp_hcs_calc_temp2_reg[3]_i_2_n_7\,
      S(3) => \udp_hcs_calc_temp2[3]_i_6_n_0\,
      S(2) => \udp_hcs_calc_temp2[3]_i_7_n_0\,
      S(1) => \udp_hcs_calc_temp2[3]_i_8_n_0\,
      S(0) => \udp_hcs_calc_temp2[3]_i_9_n_0\
    );
\udp_hcs_calc_temp2_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[4]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(4),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[5]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(5),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[6]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(6),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[7]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(7),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[7]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_hcs_calc_temp2_reg[3]_i_2_n_0\,
      CO(3) => \udp_hcs_calc_temp2_reg[7]_i_2_n_0\,
      CO(2) => \udp_hcs_calc_temp2_reg[7]_i_2_n_1\,
      CO(1) => \udp_hcs_calc_temp2_reg[7]_i_2_n_2\,
      CO(0) => \udp_hcs_calc_temp2_reg[7]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => \udp_hcs_calc_temp2[7]_i_3_n_0\,
      DI(2) => \udp_hcs_calc_temp2[7]_i_4_n_0\,
      DI(1) => \udp_hcs_calc_temp2[7]_i_5_n_0\,
      DI(0) => \udp_hcs_calc_temp2[7]_i_6_n_0\,
      O(3) => \udp_hcs_calc_temp2_reg[7]_i_2_n_4\,
      O(2) => \udp_hcs_calc_temp2_reg[7]_i_2_n_5\,
      O(1) => \udp_hcs_calc_temp2_reg[7]_i_2_n_6\,
      O(0) => \udp_hcs_calc_temp2_reg[7]_i_2_n_7\,
      S(3) => \udp_hcs_calc_temp2[7]_i_7_n_0\,
      S(2) => \udp_hcs_calc_temp2[7]_i_8_n_0\,
      S(1) => \udp_hcs_calc_temp2[7]_i_9_n_0\,
      S(0) => \udp_hcs_calc_temp2[7]_i_10_n_0\
    );
\udp_hcs_calc_temp2_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[8]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(8),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
\udp_hcs_calc_temp2_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => \udp_hcs_calc_temp2[15]_i_1_n_0\,
      D => \udp_hcs_calc_temp2[9]_i_1_n_0\,
      Q => \udp_hcs_calc_temp2__0\(9),
      R => \udp_hcs_calc_temp1[23]_i_1_n_0\
    );
udp_hcs_done_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E000"
    )
        port map (
      I0 => udp_hcs_calc,
      I1 => udp_hcs_done,
      I2 => udp_presum_done,
      I3 => udp_datasum_done_reg_n_0,
      O => udp_hcs_done_i_1_n_0
    );
udp_hcs_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => udp_hcs_done_i_1_n_0,
      Q => udp_hcs_done,
      R => '0'
    );
\udp_length[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => p_1_in65_in,
      I1 => arp_request_expected,
      I2 => eth_protocol_expected,
      O => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(0),
      Q => udp_length(0),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(10),
      Q => udp_length(10),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(11),
      Q => udp_length(11),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(12),
      Q => udp_length(12),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(13),
      Q => udp_length(13),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(14),
      Q => udp_length(14),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(15),
      Q => udp_length(15),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(1),
      Q => udp_length(1),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(2),
      Q => udp_length(2),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(3),
      Q => udp_length(3),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(4),
      Q => udp_length(4),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(5),
      Q => udp_length(5),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(6),
      Q => udp_length(6),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(7),
      Q => udp_length(7),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(8),
      Q => udp_length(8),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_length_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => bytes12(9),
      Q => udp_length(9),
      R => \udp_length[15]_i_1_n_0\
    );
\udp_presum[11]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg[15]_i_13_n_6\,
      I1 => \udp_presum_reg[15]_i_14_n_6\,
      I2 => \udp_presum_reg[15]_i_15_n_6\,
      O => \udp_presum[11]_i_10_n_0\
    );
\udp_presum[11]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17E8E817"
    )
        port map (
      I0 => \udp_presum_reg[15]_i_13_n_6\,
      I1 => \udp_presum_reg[15]_i_14_n_6\,
      I2 => \udp_presum_reg[15]_i_15_n_6\,
      I3 => \udp_presum[15]_i_19_n_0\,
      I4 => source_ip(26),
      O => \udp_presum[11]_i_11_n_0\
    );
\udp_presum[11]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg[15]_i_13_n_7\,
      I1 => \udp_presum_reg[15]_i_14_n_7\,
      I2 => \udp_presum_reg[15]_i_15_n_7\,
      O => \udp_presum[11]_i_12_n_0\
    );
\udp_presum[11]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17E8E817"
    )
        port map (
      I0 => \udp_presum_reg[15]_i_13_n_7\,
      I1 => \udp_presum_reg[15]_i_14_n_7\,
      I2 => \udp_presum_reg[15]_i_15_n_7\,
      I3 => \udp_presum[11]_i_10_n_0\,
      I4 => source_ip(25),
      O => \udp_presum[11]_i_16_n_0\
    );
\udp_presum[11]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg[11]_i_13_n_4\,
      I1 => \udp_presum_reg[11]_i_14_n_4\,
      I2 => \udp_presum_reg[11]_i_15_n_4\,
      O => \udp_presum[11]_i_17_n_0\
    );
\udp_presum[11]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17E8E817"
    )
        port map (
      I0 => \udp_presum_reg[11]_i_13_n_4\,
      I1 => \udp_presum_reg[11]_i_14_n_4\,
      I2 => \udp_presum_reg[11]_i_15_n_4\,
      I3 => \udp_presum[11]_i_12_n_0\,
      I4 => source_ip(24),
      O => \udp_presum[11]_i_18_n_0\
    );
\udp_presum[11]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg[11]_i_13_n_5\,
      I1 => \udp_presum_reg[11]_i_14_n_5\,
      I2 => \udp_presum_reg[11]_i_15_n_5\,
      O => \udp_presum[11]_i_19_n_0\
    );
\udp_presum[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE8E888"
    )
        port map (
      I0 => \udp_presum[11]_i_10_n_0\,
      I1 => source_ip(25),
      I2 => \udp_presum_reg[15]_i_13_n_7\,
      I3 => \udp_presum_reg[15]_i_14_n_7\,
      I4 => \udp_presum_reg[15]_i_15_n_7\,
      I5 => \udp_presum[11]_i_11_n_0\,
      O => \udp_presum[11]_i_2_n_0\
    );
\udp_presum[11]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17E8E817"
    )
        port map (
      I0 => \udp_presum_reg[11]_i_13_n_5\,
      I1 => \udp_presum_reg[11]_i_14_n_5\,
      I2 => \udp_presum_reg[11]_i_15_n_5\,
      I3 => \udp_presum[11]_i_17_n_0\,
      I4 => source_ip(23),
      O => \udp_presum[11]_i_20_n_0\
    );
\udp_presum[11]_i_21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"001717FF"
    )
        port map (
      I0 => \udp_presum_reg[15]_i_15_n_6\,
      I1 => \udp_presum_reg[15]_i_14_n_6\,
      I2 => \udp_presum_reg[15]_i_13_n_6\,
      I3 => source_ip(26),
      I4 => \udp_presum[15]_i_19_n_0\,
      O => \udp_presum[11]_i_21_n_0\
    );
\udp_presum[11]_i_22\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"001717FF"
    )
        port map (
      I0 => \udp_presum_reg[15]_i_15_n_7\,
      I1 => \udp_presum_reg[15]_i_14_n_7\,
      I2 => \udp_presum_reg[15]_i_13_n_7\,
      I3 => source_ip(25),
      I4 => \udp_presum[11]_i_10_n_0\,
      O => \udp_presum[11]_i_22_n_0\
    );
\udp_presum[11]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"001717FF"
    )
        port map (
      I0 => \udp_presum_reg[11]_i_15_n_4\,
      I1 => \udp_presum_reg[11]_i_14_n_4\,
      I2 => \udp_presum_reg[11]_i_13_n_4\,
      I3 => source_ip(24),
      I4 => \udp_presum[11]_i_12_n_0\,
      O => \udp_presum[11]_i_23_n_0\
    );
\udp_presum[11]_i_24\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"001717FF"
    )
        port map (
      I0 => \udp_presum_reg[11]_i_15_n_5\,
      I1 => \udp_presum_reg[11]_i_14_n_5\,
      I2 => \udp_presum_reg[11]_i_13_n_5\,
      I3 => source_ip(23),
      I4 => \udp_presum[11]_i_17_n_0\,
      O => \udp_presum[11]_i_24_n_0\
    );
\udp_presum[11]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => udp_length(6),
      I1 => source_port(6),
      O => \udp_presum[11]_i_25_n_0\
    );
\udp_presum[11]_i_26\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => udp_length(5),
      I1 => source_port(5),
      O => \udp_presum[11]_i_26_n_0\
    );
\udp_presum[11]_i_27\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => udp_length(4),
      I1 => source_port(4),
      O => \udp_presum[11]_i_27_n_0\
    );
\udp_presum[11]_i_28\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => udp_length(3),
      I1 => source_port(3),
      O => \udp_presum[11]_i_28_n_0\
    );
\udp_presum[11]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1EE1"
    )
        port map (
      I0 => source_port(6),
      I1 => udp_length(6),
      I2 => source_port(7),
      I3 => udp_length(7),
      O => \udp_presum[11]_i_29_n_0\
    );
\udp_presum[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE8E888"
    )
        port map (
      I0 => \udp_presum[11]_i_12_n_0\,
      I1 => source_ip(24),
      I2 => \udp_presum_reg[11]_i_13_n_4\,
      I3 => \udp_presum_reg[11]_i_14_n_4\,
      I4 => \udp_presum_reg[11]_i_15_n_4\,
      I5 => \udp_presum[11]_i_16_n_0\,
      O => \udp_presum[11]_i_3_n_0\
    );
\udp_presum[11]_i_30\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7887"
    )
        port map (
      I0 => source_port(5),
      I1 => udp_length(5),
      I2 => source_port(6),
      I3 => udp_length(6),
      O => \udp_presum[11]_i_30_n_0\
    );
\udp_presum[11]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E11E"
    )
        port map (
      I0 => source_port(4),
      I1 => udp_length(4),
      I2 => source_port(5),
      I3 => udp_length(5),
      O => \udp_presum[11]_i_31_n_0\
    );
\udp_presum[11]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7887"
    )
        port map (
      I0 => source_port(3),
      I1 => udp_length(3),
      I2 => source_port(4),
      I3 => udp_length(4),
      O => \udp_presum[11]_i_32_n_0\
    );
\udp_presum[11]_i_33\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes13(6),
      I1 => \udp_presum_reg_n_0_[6]\,
      I2 => udp_length(6),
      O => \udp_presum[11]_i_33_n_0\
    );
\udp_presum[11]_i_34\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => udp_length(5),
      I1 => bytes13(5),
      I2 => \udp_presum_reg_n_0_[5]\,
      O => \udp_presum[11]_i_34_n_0\
    );
\udp_presum[11]_i_35\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes13(4),
      I1 => \udp_presum_reg_n_0_[4]\,
      I2 => udp_length(4),
      O => \udp_presum[11]_i_35_n_0\
    );
\udp_presum[11]_i_36\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => udp_length(3),
      I1 => bytes13(3),
      I2 => \udp_presum_reg_n_0_[3]\,
      O => \udp_presum[11]_i_36_n_0\
    );
\udp_presum[11]_i_37\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes13(7),
      I1 => \udp_presum_reg_n_0_[7]\,
      I2 => udp_length(7),
      I3 => \udp_presum[11]_i_33_n_0\,
      O => \udp_presum[11]_i_37_n_0\
    );
\udp_presum[11]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes13(6),
      I1 => \udp_presum_reg_n_0_[6]\,
      I2 => udp_length(6),
      I3 => \udp_presum[11]_i_34_n_0\,
      O => \udp_presum[11]_i_38_n_0\
    );
\udp_presum[11]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => udp_length(5),
      I1 => bytes13(5),
      I2 => \udp_presum_reg_n_0_[5]\,
      I3 => \udp_presum[11]_i_35_n_0\,
      O => \udp_presum[11]_i_39_n_0\
    );
\udp_presum[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE8E888"
    )
        port map (
      I0 => \udp_presum[11]_i_17_n_0\,
      I1 => source_ip(23),
      I2 => \udp_presum_reg[11]_i_13_n_5\,
      I3 => \udp_presum_reg[11]_i_14_n_5\,
      I4 => \udp_presum_reg[11]_i_15_n_5\,
      I5 => \udp_presum[11]_i_18_n_0\,
      O => \udp_presum[11]_i_4_n_0\
    );
\udp_presum[11]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes13(4),
      I1 => \udp_presum_reg_n_0_[4]\,
      I2 => udp_length(4),
      I3 => \udp_presum[11]_i_36_n_0\,
      O => \udp_presum[11]_i_40_n_0\
    );
\udp_presum[11]_i_41\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => ip(3),
      I1 => source_ip(3),
      O => \udp_presum[11]_i_41_n_0\
    );
\udp_presum[11]_i_42\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => source_ip(7),
      O => \udp_presum[11]_i_42_n_0\
    );
\udp_presum[11]_i_43\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => source_ip(6),
      O => \udp_presum[11]_i_43_n_0\
    );
\udp_presum[11]_i_44\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => source_ip(4),
      I1 => ip(4),
      I2 => source_ip(5),
      O => \udp_presum[11]_i_44_n_0\
    );
\udp_presum[11]_i_45\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E11E"
    )
        port map (
      I0 => source_ip(3),
      I1 => ip(3),
      I2 => source_ip(4),
      I3 => ip(4),
      O => \udp_presum[11]_i_45_n_0\
    );
\udp_presum[11]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE8E888"
    )
        port map (
      I0 => \udp_presum[11]_i_19_n_0\,
      I1 => source_ip(22),
      I2 => \udp_presum_reg[11]_i_13_n_6\,
      I3 => \udp_presum_reg[11]_i_14_n_6\,
      I4 => \udp_presum_reg[11]_i_15_n_6\,
      I5 => \udp_presum[11]_i_20_n_0\,
      O => \udp_presum[11]_i_5_n_0\
    );
\udp_presum[11]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum[11]_i_2_n_0\,
      I1 => \udp_presum[15]_i_20_n_0\,
      I2 => \udp_presum[11]_i_21_n_0\,
      O => \udp_presum[11]_i_6_n_0\
    );
\udp_presum[11]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum[11]_i_3_n_0\,
      I1 => \udp_presum[11]_i_11_n_0\,
      I2 => \udp_presum[11]_i_22_n_0\,
      O => \udp_presum[11]_i_7_n_0\
    );
\udp_presum[11]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum[11]_i_4_n_0\,
      I1 => \udp_presum[11]_i_16_n_0\,
      I2 => \udp_presum[11]_i_23_n_0\,
      O => \udp_presum[11]_i_8_n_0\
    );
\udp_presum[11]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum[11]_i_5_n_0\,
      I1 => \udp_presum[11]_i_18_n_0\,
      I2 => \udp_presum[11]_i_24_n_0\,
      O => \udp_presum[11]_i_9_n_0\
    );
\udp_presum[15]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_12_n_6\,
      I1 => \udp_presum_reg[19]_i_13_n_6\,
      I2 => \udp_presum_reg[19]_i_14_n_6\,
      O => \udp_presum[15]_i_10_n_0\
    );
\udp_presum[15]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17E8E817"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_12_n_6\,
      I1 => \udp_presum_reg[19]_i_13_n_6\,
      I2 => \udp_presum_reg[19]_i_14_n_6\,
      I3 => \udp_presum[19]_i_17_n_0\,
      I4 => source_ip(30),
      O => \udp_presum[15]_i_11_n_0\
    );
\udp_presum[15]_i_12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_12_n_7\,
      I1 => \udp_presum_reg[19]_i_13_n_7\,
      I2 => \udp_presum_reg[19]_i_14_n_7\,
      O => \udp_presum[15]_i_12_n_0\
    );
\udp_presum[15]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17E8E817"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_12_n_7\,
      I1 => \udp_presum_reg[19]_i_13_n_7\,
      I2 => \udp_presum_reg[19]_i_14_n_7\,
      I3 => \udp_presum[15]_i_10_n_0\,
      I4 => source_ip(29),
      O => \udp_presum[15]_i_16_n_0\
    );
\udp_presum[15]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg[15]_i_13_n_4\,
      I1 => \udp_presum_reg[15]_i_14_n_4\,
      I2 => \udp_presum_reg[15]_i_15_n_4\,
      O => \udp_presum[15]_i_17_n_0\
    );
\udp_presum[15]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17E8E817"
    )
        port map (
      I0 => \udp_presum_reg[15]_i_13_n_4\,
      I1 => \udp_presum_reg[15]_i_14_n_4\,
      I2 => \udp_presum_reg[15]_i_15_n_4\,
      I3 => \udp_presum[15]_i_12_n_0\,
      I4 => source_ip(28),
      O => \udp_presum[15]_i_18_n_0\
    );
\udp_presum[15]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg[15]_i_13_n_5\,
      I1 => \udp_presum_reg[15]_i_14_n_5\,
      I2 => \udp_presum_reg[15]_i_15_n_5\,
      O => \udp_presum[15]_i_19_n_0\
    );
\udp_presum[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE8E888"
    )
        port map (
      I0 => \udp_presum[15]_i_10_n_0\,
      I1 => source_ip(29),
      I2 => \udp_presum_reg[19]_i_12_n_7\,
      I3 => \udp_presum_reg[19]_i_13_n_7\,
      I4 => \udp_presum_reg[19]_i_14_n_7\,
      I5 => \udp_presum[15]_i_11_n_0\,
      O => \udp_presum[15]_i_2_n_0\
    );
\udp_presum[15]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17E8E817"
    )
        port map (
      I0 => \udp_presum_reg[15]_i_13_n_5\,
      I1 => \udp_presum_reg[15]_i_14_n_5\,
      I2 => \udp_presum_reg[15]_i_15_n_5\,
      I3 => \udp_presum[15]_i_17_n_0\,
      I4 => source_ip(27),
      O => \udp_presum[15]_i_20_n_0\
    );
\udp_presum[15]_i_21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"001717FF"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_14_n_6\,
      I1 => \udp_presum_reg[19]_i_13_n_6\,
      I2 => \udp_presum_reg[19]_i_12_n_6\,
      I3 => source_ip(30),
      I4 => \udp_presum[19]_i_17_n_0\,
      O => \udp_presum[15]_i_21_n_0\
    );
\udp_presum[15]_i_22\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"001717FF"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_14_n_7\,
      I1 => \udp_presum_reg[19]_i_13_n_7\,
      I2 => \udp_presum_reg[19]_i_12_n_7\,
      I3 => source_ip(29),
      I4 => \udp_presum[15]_i_10_n_0\,
      O => \udp_presum[15]_i_22_n_0\
    );
\udp_presum[15]_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"001717FF"
    )
        port map (
      I0 => \udp_presum_reg[15]_i_15_n_4\,
      I1 => \udp_presum_reg[15]_i_14_n_4\,
      I2 => \udp_presum_reg[15]_i_13_n_4\,
      I3 => source_ip(28),
      I4 => \udp_presum[15]_i_12_n_0\,
      O => \udp_presum[15]_i_23_n_0\
    );
\udp_presum[15]_i_24\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"001717FF"
    )
        port map (
      I0 => \udp_presum_reg[15]_i_15_n_5\,
      I1 => \udp_presum_reg[15]_i_14_n_5\,
      I2 => \udp_presum_reg[15]_i_13_n_5\,
      I3 => source_ip(27),
      I4 => \udp_presum[15]_i_17_n_0\,
      O => \udp_presum[15]_i_24_n_0\
    );
\udp_presum[15]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => udp_length(10),
      I1 => source_port(10),
      O => \udp_presum[15]_i_25_n_0\
    );
\udp_presum[15]_i_26\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => udp_length(9),
      I1 => source_port(9),
      O => \udp_presum[15]_i_26_n_0\
    );
\udp_presum[15]_i_27\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => udp_length(8),
      I1 => source_port(8),
      O => \udp_presum[15]_i_27_n_0\
    );
\udp_presum[15]_i_28\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => udp_length(7),
      I1 => source_port(7),
      O => \udp_presum[15]_i_28_n_0\
    );
\udp_presum[15]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E11E"
    )
        port map (
      I0 => source_port(10),
      I1 => udp_length(10),
      I2 => source_port(11),
      I3 => udp_length(11),
      O => \udp_presum[15]_i_29_n_0\
    );
\udp_presum[15]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE8E888"
    )
        port map (
      I0 => \udp_presum[15]_i_12_n_0\,
      I1 => source_ip(28),
      I2 => \udp_presum_reg[15]_i_13_n_4\,
      I3 => \udp_presum_reg[15]_i_14_n_4\,
      I4 => \udp_presum_reg[15]_i_15_n_4\,
      I5 => \udp_presum[15]_i_16_n_0\,
      O => \udp_presum[15]_i_3_n_0\
    );
\udp_presum[15]_i_30\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7887"
    )
        port map (
      I0 => source_port(9),
      I1 => udp_length(9),
      I2 => source_port(10),
      I3 => udp_length(10),
      O => \udp_presum[15]_i_30_n_0\
    );
\udp_presum[15]_i_31\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => source_port(8),
      I1 => udp_length(8),
      I2 => source_port(9),
      I3 => udp_length(9),
      O => \udp_presum[15]_i_31_n_0\
    );
\udp_presum[15]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E11E"
    )
        port map (
      I0 => source_port(7),
      I1 => udp_length(7),
      I2 => source_port(8),
      I3 => udp_length(8),
      O => \udp_presum[15]_i_32_n_0\
    );
\udp_presum[15]_i_33\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes13(10),
      I1 => \udp_presum_reg_n_0_[10]\,
      I2 => udp_length(10),
      O => \udp_presum[15]_i_33_n_0\
    );
\udp_presum[15]_i_34\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => udp_length(9),
      I1 => bytes13(9),
      I2 => \udp_presum_reg_n_0_[9]\,
      O => \udp_presum[15]_i_34_n_0\
    );
\udp_presum[15]_i_35\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => udp_length(8),
      I1 => bytes13(8),
      I2 => \udp_presum_reg_n_0_[8]\,
      O => \udp_presum[15]_i_35_n_0\
    );
\udp_presum[15]_i_36\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes13(7),
      I1 => \udp_presum_reg_n_0_[7]\,
      I2 => udp_length(7),
      O => \udp_presum[15]_i_36_n_0\
    );
\udp_presum[15]_i_37\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => udp_length(11),
      I1 => bytes13(11),
      I2 => \udp_presum_reg_n_0_[11]\,
      I3 => \udp_presum[15]_i_33_n_0\,
      O => \udp_presum[15]_i_37_n_0\
    );
\udp_presum[15]_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes13(10),
      I1 => \udp_presum_reg_n_0_[10]\,
      I2 => udp_length(10),
      I3 => \udp_presum[15]_i_34_n_0\,
      O => \udp_presum[15]_i_38_n_0\
    );
\udp_presum[15]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => udp_length(9),
      I1 => bytes13(9),
      I2 => \udp_presum_reg_n_0_[9]\,
      I3 => \udp_presum[15]_i_35_n_0\,
      O => \udp_presum[15]_i_39_n_0\
    );
\udp_presum[15]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE8E888"
    )
        port map (
      I0 => \udp_presum[15]_i_17_n_0\,
      I1 => source_ip(27),
      I2 => \udp_presum_reg[15]_i_13_n_5\,
      I3 => \udp_presum_reg[15]_i_14_n_5\,
      I4 => \udp_presum_reg[15]_i_15_n_5\,
      I5 => \udp_presum[15]_i_18_n_0\,
      O => \udp_presum[15]_i_4_n_0\
    );
\udp_presum[15]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => udp_length(8),
      I1 => bytes13(8),
      I2 => \udp_presum_reg_n_0_[8]\,
      I3 => \udp_presum[15]_i_36_n_0\,
      O => \udp_presum[15]_i_40_n_0\
    );
\udp_presum[15]_i_41\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => source_ip(8),
      I1 => source_ip(9),
      O => \udp_presum[15]_i_41_n_0\
    );
\udp_presum[15]_i_42\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => source_ip(7),
      I1 => source_ip(8),
      O => \udp_presum[15]_i_42_n_0\
    );
\udp_presum[15]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE8E888"
    )
        port map (
      I0 => \udp_presum[15]_i_19_n_0\,
      I1 => source_ip(26),
      I2 => \udp_presum_reg[15]_i_13_n_6\,
      I3 => \udp_presum_reg[15]_i_14_n_6\,
      I4 => \udp_presum_reg[15]_i_15_n_6\,
      I5 => \udp_presum[15]_i_20_n_0\,
      O => \udp_presum[15]_i_5_n_0\
    );
\udp_presum[15]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum[15]_i_2_n_0\,
      I1 => \udp_presum[19]_i_18_n_0\,
      I2 => \udp_presum[15]_i_21_n_0\,
      O => \udp_presum[15]_i_6_n_0\
    );
\udp_presum[15]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum[15]_i_3_n_0\,
      I1 => \udp_presum[15]_i_11_n_0\,
      I2 => \udp_presum[15]_i_22_n_0\,
      O => \udp_presum[15]_i_7_n_0\
    );
\udp_presum[15]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum[15]_i_4_n_0\,
      I1 => \udp_presum[15]_i_16_n_0\,
      I2 => \udp_presum[15]_i_23_n_0\,
      O => \udp_presum[15]_i_8_n_0\
    );
\udp_presum[15]_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum[15]_i_5_n_0\,
      I1 => \udp_presum[15]_i_18_n_0\,
      I2 => \udp_presum[15]_i_24_n_0\,
      O => \udp_presum[15]_i_9_n_0\
    );
\udp_presum[19]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_10_n_7\,
      I1 => \udp_presum_reg[23]_i_5_n_7\,
      I2 => \udp_presum_reg[19]_i_11_n_7\,
      O => \udp_presum[19]_i_15_n_0\
    );
\udp_presum[19]_i_16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_14_n_5\,
      I1 => \udp_presum_reg[19]_i_13_n_5\,
      I2 => \udp_presum_reg[19]_i_12_n_5\,
      O => \udp_presum[19]_i_16_n_0\
    );
\udp_presum[19]_i_17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_12_n_5\,
      I1 => \udp_presum_reg[19]_i_13_n_5\,
      I2 => \udp_presum_reg[19]_i_14_n_5\,
      O => \udp_presum[19]_i_17_n_0\
    );
\udp_presum[19]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17E8E817"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_12_n_5\,
      I1 => \udp_presum_reg[19]_i_13_n_5\,
      I2 => \udp_presum_reg[19]_i_14_n_5\,
      I3 => \udp_presum[19]_i_40_n_0\,
      I4 => source_ip(31),
      O => \udp_presum[19]_i_18_n_0\
    );
\udp_presum[19]_i_19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_10_n_2\,
      I1 => \udp_presum_reg[19]_i_11_n_2\,
      I2 => \udp_presum_reg[23]_i_5_n_6\,
      O => \udp_presum[19]_i_19_n_0\
    );
\udp_presum[19]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A880"
    )
        port map (
      I0 => \udp_presum_reg[23]_i_5_n_5\,
      I1 => \udp_presum_reg[19]_i_10_n_2\,
      I2 => \udp_presum_reg[23]_i_5_n_6\,
      I3 => \udp_presum_reg[19]_i_11_n_2\,
      O => \udp_presum[19]_i_2_n_0\
    );
\udp_presum[19]_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_14_n_5\,
      I1 => \udp_presum_reg[19]_i_13_n_5\,
      I2 => \udp_presum_reg[19]_i_12_n_5\,
      I3 => \udp_presum[19]_i_40_n_0\,
      I4 => source_ip(31),
      O => \udp_presum[19]_i_20_n_0\
    );
\udp_presum[19]_i_21\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => udp_length(15),
      I1 => source_port(15),
      O => \udp_presum[19]_i_21_n_0\
    );
\udp_presum[19]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => udp_length(14),
      I1 => source_port(14),
      O => \udp_presum[19]_i_22_n_0\
    );
\udp_presum[19]_i_23\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => udp_length(13),
      I1 => source_port(13),
      O => \udp_presum[19]_i_23_n_0\
    );
\udp_presum[19]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => udp_length(12),
      I1 => source_port(12),
      O => \udp_presum[19]_i_24_n_0\
    );
\udp_presum[19]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => udp_length(11),
      I1 => source_port(11),
      O => \udp_presum[19]_i_25_n_0\
    );
\udp_presum[19]_i_26\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => source_port(14),
      I1 => udp_length(14),
      I2 => source_port(15),
      I3 => udp_length(15),
      O => \udp_presum[19]_i_26_n_0\
    );
\udp_presum[19]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => source_port(13),
      I1 => udp_length(13),
      I2 => source_port(14),
      I3 => udp_length(14),
      O => \udp_presum[19]_i_27_n_0\
    );
\udp_presum[19]_i_28\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => source_port(12),
      I1 => udp_length(12),
      I2 => source_port(13),
      I3 => udp_length(13),
      O => \udp_presum[19]_i_28_n_0\
    );
\udp_presum[19]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => source_port(11),
      I1 => udp_length(11),
      I2 => source_port(12),
      I3 => udp_length(12),
      O => \udp_presum[19]_i_29_n_0\
    );
\udp_presum[19]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_10_n_7\,
      I1 => \udp_presum_reg[23]_i_5_n_7\,
      I2 => \udp_presum_reg[19]_i_11_n_7\,
      I3 => \udp_presum_reg[23]_i_5_n_6\,
      I4 => \udp_presum_reg[19]_i_11_n_2\,
      I5 => \udp_presum_reg[19]_i_10_n_2\,
      O => \udp_presum[19]_i_3_n_0\
    );
\udp_presum[19]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => udp_length(14),
      I1 => bytes13(14),
      I2 => \udp_presum_reg_n_0_[14]\,
      O => \udp_presum[19]_i_30_n_0\
    );
\udp_presum[19]_i_31\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => udp_length(13),
      I1 => bytes13(13),
      I2 => \udp_presum_reg_n_0_[13]\,
      O => \udp_presum[19]_i_31_n_0\
    );
\udp_presum[19]_i_32\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => udp_length(12),
      I1 => bytes13(12),
      I2 => \udp_presum_reg_n_0_[12]\,
      O => \udp_presum[19]_i_32_n_0\
    );
\udp_presum[19]_i_33\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => udp_length(11),
      I1 => bytes13(11),
      I2 => \udp_presum_reg_n_0_[11]\,
      O => \udp_presum[19]_i_33_n_0\
    );
\udp_presum[19]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \udp_presum[19]_i_30_n_0\,
      I1 => bytes13(15),
      I2 => udp_length(15),
      I3 => \udp_presum_reg_n_0_[15]\,
      O => \udp_presum[19]_i_34_n_0\
    );
\udp_presum[19]_i_35\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => udp_length(14),
      I1 => bytes13(14),
      I2 => \udp_presum_reg_n_0_[14]\,
      I3 => \udp_presum[19]_i_31_n_0\,
      O => \udp_presum[19]_i_35_n_0\
    );
\udp_presum[19]_i_36\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => udp_length(13),
      I1 => bytes13(13),
      I2 => \udp_presum_reg_n_0_[13]\,
      I3 => \udp_presum[19]_i_32_n_0\,
      O => \udp_presum[19]_i_36_n_0\
    );
\udp_presum[19]_i_37\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => udp_length(12),
      I1 => bytes13(12),
      I2 => \udp_presum_reg_n_0_[12]\,
      I3 => \udp_presum[19]_i_33_n_0\,
      O => \udp_presum[19]_i_37_n_0\
    );
\udp_presum[19]_i_38\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => source_ip(14),
      I1 => source_ip(15),
      O => \udp_presum[19]_i_38_n_0\
    );
\udp_presum[19]_i_39\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => source_ip(14),
      O => \udp_presum[19]_i_39_n_0\
    );
\udp_presum[19]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FE80FFE8E800FE80"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_12_n_4\,
      I1 => \udp_presum_reg[19]_i_13_n_4\,
      I2 => \udp_presum_reg[19]_i_14_n_4\,
      I3 => \udp_presum[19]_i_15_n_0\,
      I4 => \udp_presum[19]_i_16_n_0\,
      I5 => source_ip(31),
      O => \udp_presum[19]_i_4_n_0\
    );
\udp_presum[19]_i_40\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_12_n_4\,
      I1 => \udp_presum_reg[19]_i_13_n_4\,
      I2 => \udp_presum_reg[19]_i_14_n_4\,
      O => \udp_presum[19]_i_40_n_0\
    );
\udp_presum[19]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEE8E888"
    )
        port map (
      I0 => \udp_presum[19]_i_17_n_0\,
      I1 => source_ip(30),
      I2 => \udp_presum_reg[19]_i_12_n_6\,
      I3 => \udp_presum_reg[19]_i_13_n_6\,
      I4 => \udp_presum_reg[19]_i_14_n_6\,
      I5 => \udp_presum[19]_i_18_n_0\,
      O => \udp_presum[19]_i_5_n_0\
    );
\udp_presum[19]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17FFE800"
    )
        port map (
      I0 => \udp_presum_reg[19]_i_11_n_2\,
      I1 => \udp_presum_reg[23]_i_5_n_6\,
      I2 => \udp_presum_reg[19]_i_10_n_2\,
      I3 => \udp_presum_reg[23]_i_5_n_5\,
      I4 => \udp_presum_reg[23]_i_5_n_4\,
      O => \udp_presum[19]_i_6_n_0\
    );
\udp_presum[19]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A995566A"
    )
        port map (
      I0 => \udp_presum[19]_i_3_n_0\,
      I1 => \udp_presum_reg[19]_i_10_n_2\,
      I2 => \udp_presum_reg[23]_i_5_n_6\,
      I3 => \udp_presum_reg[19]_i_11_n_2\,
      I4 => \udp_presum_reg[23]_i_5_n_5\,
      O => \udp_presum[19]_i_7_n_0\
    );
\udp_presum[19]_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66696999"
    )
        port map (
      I0 => \udp_presum[19]_i_4_n_0\,
      I1 => \udp_presum[19]_i_19_n_0\,
      I2 => \udp_presum_reg[19]_i_11_n_7\,
      I3 => \udp_presum_reg[23]_i_5_n_7\,
      I4 => \udp_presum_reg[19]_i_10_n_7\,
      O => \udp_presum[19]_i_8_n_0\
    );
\udp_presum[19]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6669699999969666"
    )
        port map (
      I0 => \udp_presum[19]_i_5_n_0\,
      I1 => \udp_presum[19]_i_15_n_0\,
      I2 => \udp_presum_reg[19]_i_14_n_4\,
      I3 => \udp_presum_reg[19]_i_13_n_4\,
      I4 => \udp_presum_reg[19]_i_12_n_4\,
      I5 => \udp_presum[19]_i_20_n_0\,
      O => \udp_presum[19]_i_9_n_0\
    );
\udp_presum[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DF"
    )
        port map (
      I0 => p_0_in57_in,
      I1 => arp_request_expected,
      I2 => eth_protocol_expected,
      O => udp_presum
    );
\udp_presum[23]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => udp_presum_done,
      O => udp_presum0
    );
\udp_presum[23]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"17E8"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[15]\,
      I1 => bytes13(15),
      I2 => udp_length(15),
      I3 => \udp_presum_reg_n_0_[16]\,
      O => \udp_presum[23]_i_6_n_0\
    );
\udp_presum[3]_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg[7]_i_13_n_5\,
      I1 => \udp_presum_reg[7]_i_12_n_5\,
      I2 => \udp_presum_reg[7]_i_11_n_5\,
      O => \udp_presum[3]_i_10_n_0\
    );
\udp_presum[3]_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \udp_presum_reg[7]_i_11_n_5\,
      I1 => \udp_presum_reg[7]_i_12_n_5\,
      I2 => \udp_presum_reg[7]_i_13_n_5\,
      O => \udp_presum[3]_i_11_n_0\
    );
\udp_presum[3]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \udp_presum_reg[7]_i_12_n_7\,
      I1 => source_ip(16),
      O => \udp_presum[3]_i_12_n_0\
    );
\udp_presum[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \udp_presum_reg[7]_i_11_n_6\,
      I1 => \udp_presum_reg[7]_i_12_n_6\,
      I2 => \udp_presum_reg[7]_i_13_n_6\,
      I3 => \udp_presum[3]_i_10_n_0\,
      I4 => source_ip(18),
      O => \udp_presum[3]_i_2_n_0\
    );
\udp_presum[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EA8080EA80EAEA80"
    )
        port map (
      I0 => source_ip(17),
      I1 => source_ip(16),
      I2 => \udp_presum_reg[7]_i_12_n_7\,
      I3 => \udp_presum_reg[7]_i_13_n_6\,
      I4 => \udp_presum_reg[7]_i_12_n_6\,
      I5 => \udp_presum_reg[7]_i_11_n_6\,
      O => \udp_presum[3]_i_3_n_0\
    );
\udp_presum[3]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \udp_presum_reg[7]_i_11_n_7\,
      I1 => \udp_presum_reg[7]_i_13_n_7\,
      O => \udp_presum[3]_i_4_n_0\
    );
\udp_presum[3]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \udp_presum_reg[7]_i_13_n_7\,
      I1 => \udp_presum_reg[7]_i_11_n_7\,
      O => \udp_presum[3]_i_5_n_0\
    );
\udp_presum[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \udp_presum[3]_i_2_n_0\,
      I1 => \udp_presum[3]_i_11_n_0\,
      I2 => \udp_presum_reg[7]_i_13_n_4\,
      I3 => \udp_presum_reg[7]_i_12_n_4\,
      I4 => \udp_presum_reg[7]_i_11_n_4\,
      I5 => source_ip(19),
      O => \udp_presum[3]_i_6_n_0\
    );
\udp_presum[3]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6969699669969696"
    )
        port map (
      I0 => \udp_presum[3]_i_3_n_0\,
      I1 => source_ip(18),
      I2 => \udp_presum[3]_i_10_n_0\,
      I3 => \udp_presum_reg[7]_i_11_n_6\,
      I4 => \udp_presum_reg[7]_i_12_n_6\,
      I5 => \udp_presum_reg[7]_i_13_n_6\,
      O => \udp_presum[3]_i_7_n_0\
    );
\udp_presum[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => source_ip(17),
      I1 => \udp_presum[3]_i_12_n_0\,
      I2 => \udp_presum_reg[7]_i_13_n_6\,
      I3 => \udp_presum_reg[7]_i_12_n_6\,
      I4 => \udp_presum_reg[7]_i_11_n_6\,
      I5 => \udp_presum[3]_i_4_n_0\,
      O => \udp_presum[3]_i_8_n_0\
    );
\udp_presum[3]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9669"
    )
        port map (
      I0 => \udp_presum_reg[7]_i_11_n_7\,
      I1 => \udp_presum_reg[7]_i_13_n_7\,
      I2 => source_ip(16),
      I3 => \udp_presum_reg[7]_i_12_n_7\,
      O => \udp_presum[3]_i_9_n_0\
    );
\udp_presum[7]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E00E0E0E0EE0E0E0"
    )
        port map (
      I0 => \udp_presum_reg[11]_i_13_n_7\,
      I1 => \udp_presum_reg[11]_i_15_n_7\,
      I2 => source_ip(21),
      I3 => source_ip(20),
      I4 => \udp_presum_reg[11]_i_14_n_7\,
      I5 => \udp_presum[7]_i_18_n_0\,
      O => \udp_presum[7]_i_10_n_0\
    );
\udp_presum[7]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \udp_presum_reg[11]_i_15_n_7\,
      I1 => \udp_presum_reg[11]_i_13_n_7\,
      O => \udp_presum[7]_i_14_n_0\
    );
\udp_presum[7]_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg[7]_i_13_n_4\,
      I1 => \udp_presum_reg[7]_i_12_n_4\,
      I2 => \udp_presum_reg[7]_i_11_n_4\,
      O => \udp_presum[7]_i_15_n_0\
    );
\udp_presum[7]_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"001717FF"
    )
        port map (
      I0 => \udp_presum_reg[11]_i_15_n_6\,
      I1 => \udp_presum_reg[11]_i_14_n_6\,
      I2 => \udp_presum_reg[11]_i_13_n_6\,
      I3 => source_ip(22),
      I4 => \udp_presum[11]_i_19_n_0\,
      O => \udp_presum[7]_i_16_n_0\
    );
\udp_presum[7]_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"17E8E817"
    )
        port map (
      I0 => \udp_presum_reg[11]_i_13_n_6\,
      I1 => \udp_presum_reg[11]_i_14_n_6\,
      I2 => \udp_presum_reg[11]_i_15_n_6\,
      I3 => \udp_presum[11]_i_19_n_0\,
      I4 => source_ip(22),
      O => \udp_presum[7]_i_17_n_0\
    );
\udp_presum[7]_i_18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg[11]_i_13_n_6\,
      I1 => \udp_presum_reg[11]_i_14_n_6\,
      I2 => \udp_presum_reg[11]_i_15_n_6\,
      O => \udp_presum[7]_i_18_n_0\
    );
\udp_presum[7]_i_19\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \udp_presum_reg[11]_i_14_n_7\,
      I1 => source_ip(20),
      O => \udp_presum[7]_i_19_n_0\
    );
\udp_presum[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8282822882282828"
    )
        port map (
      I0 => \udp_presum[7]_i_10_n_0\,
      I1 => source_ip(22),
      I2 => \udp_presum[11]_i_19_n_0\,
      I3 => \udp_presum_reg[11]_i_15_n_6\,
      I4 => \udp_presum_reg[11]_i_14_n_6\,
      I5 => \udp_presum_reg[11]_i_13_n_6\,
      O => \udp_presum[7]_i_2_n_0\
    );
\udp_presum[7]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996969696696969"
    )
        port map (
      I0 => \udp_presum_reg[11]_i_15_n_6\,
      I1 => \udp_presum_reg[11]_i_14_n_6\,
      I2 => \udp_presum_reg[11]_i_13_n_6\,
      I3 => \udp_presum_reg[11]_i_14_n_7\,
      I4 => source_ip(20),
      I5 => source_ip(21),
      O => \udp_presum[7]_i_20_n_0\
    );
\udp_presum[7]_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \udp_presum_reg[7]_i_11_n_4\,
      I1 => \udp_presum_reg[7]_i_12_n_4\,
      I2 => \udp_presum_reg[7]_i_13_n_4\,
      O => \udp_presum[7]_i_21_n_0\
    );
\udp_presum[7]_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip(2),
      I1 => source_ip(2),
      O => \udp_presum[7]_i_22_n_0\
    );
\udp_presum[7]_i_23\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip(1),
      I1 => source_ip(1),
      O => \udp_presum[7]_i_23_n_0\
    );
\udp_presum[7]_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip(0),
      I1 => source_ip(0),
      O => \udp_presum[7]_i_24_n_0\
    );
\udp_presum[7]_i_25\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7887"
    )
        port map (
      I0 => source_ip(2),
      I1 => ip(2),
      I2 => source_ip(3),
      I3 => ip(3),
      O => \udp_presum[7]_i_25_n_0\
    );
\udp_presum[7]_i_26\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => source_ip(1),
      I1 => ip(1),
      I2 => source_ip(2),
      I3 => ip(2),
      O => \udp_presum[7]_i_26_n_0\
    );
\udp_presum[7]_i_27\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => source_ip(0),
      I1 => ip(0),
      I2 => source_ip(1),
      I3 => ip(1),
      O => \udp_presum[7]_i_27_n_0\
    );
\udp_presum[7]_i_28\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ip(0),
      I1 => source_ip(0),
      O => \udp_presum[7]_i_28_n_0\
    );
\udp_presum[7]_i_29\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => udp_length(2),
      I1 => bytes13(2),
      I2 => \udp_presum_reg_n_0_[2]\,
      O => \udp_presum[7]_i_29_n_0\
    );
\udp_presum[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6969699669969696"
    )
        port map (
      I0 => \udp_presum[7]_i_10_n_0\,
      I1 => source_ip(22),
      I2 => \udp_presum[11]_i_19_n_0\,
      I3 => \udp_presum_reg[11]_i_15_n_6\,
      I4 => \udp_presum_reg[11]_i_14_n_6\,
      I5 => \udp_presum_reg[11]_i_13_n_6\,
      O => \udp_presum[7]_i_3_n_0\
    );
\udp_presum[7]_i_30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => bytes13(1),
      I1 => \udp_presum_reg_n_0_[1]\,
      I2 => udp_length(1),
      O => \udp_presum[7]_i_30_n_0\
    );
\udp_presum[7]_i_31\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[0]\,
      I1 => bytes13(0),
      I2 => udp_length(0),
      O => \udp_presum[7]_i_31_n_0\
    );
\udp_presum[7]_i_32\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => udp_length(3),
      I1 => bytes13(3),
      I2 => \udp_presum_reg_n_0_[3]\,
      I3 => \udp_presum[7]_i_29_n_0\,
      O => \udp_presum[7]_i_32_n_0\
    );
\udp_presum[7]_i_33\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => udp_length(2),
      I1 => bytes13(2),
      I2 => \udp_presum_reg_n_0_[2]\,
      I3 => \udp_presum[7]_i_30_n_0\,
      O => \udp_presum[7]_i_33_n_0\
    );
\udp_presum[7]_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => bytes13(1),
      I1 => \udp_presum_reg_n_0_[1]\,
      I2 => udp_length(1),
      I3 => \udp_presum[7]_i_31_n_0\,
      O => \udp_presum[7]_i_34_n_0\
    );
\udp_presum[7]_i_35\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum_reg_n_0_[0]\,
      I1 => bytes13(0),
      I2 => udp_length(0),
      O => \udp_presum[7]_i_35_n_0\
    );
\udp_presum[7]_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => udp_length(2),
      I1 => source_port(2),
      O => \udp_presum[7]_i_36_n_0\
    );
\udp_presum[7]_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => udp_length(1),
      I1 => source_port(1),
      O => \udp_presum[7]_i_37_n_0\
    );
\udp_presum[7]_i_38\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => udp_length(0),
      I1 => source_port(0),
      O => \udp_presum[7]_i_38_n_0\
    );
\udp_presum[7]_i_39\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => source_port(2),
      I1 => udp_length(2),
      I2 => source_port(3),
      I3 => udp_length(3),
      O => \udp_presum[7]_i_39_n_0\
    );
\udp_presum[7]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00E8E800E8FFFFE8"
    )
        port map (
      I0 => \udp_presum_reg[7]_i_11_n_4\,
      I1 => \udp_presum_reg[7]_i_12_n_4\,
      I2 => \udp_presum_reg[7]_i_13_n_4\,
      I3 => source_ip(20),
      I4 => \udp_presum_reg[11]_i_14_n_7\,
      I5 => \udp_presum[7]_i_14_n_0\,
      O => \udp_presum[7]_i_4_n_0\
    );
\udp_presum[7]_i_40\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E11E"
    )
        port map (
      I0 => source_port(1),
      I1 => udp_length(1),
      I2 => source_port(2),
      I3 => udp_length(2),
      O => \udp_presum[7]_i_40_n_0\
    );
\udp_presum[7]_i_41\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7887"
    )
        port map (
      I0 => source_port(0),
      I1 => udp_length(0),
      I2 => source_port(1),
      I3 => udp_length(1),
      O => \udp_presum[7]_i_41_n_0\
    );
\udp_presum[7]_i_42\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => source_port(0),
      I1 => udp_length(0),
      O => \udp_presum[7]_i_42_n_0\
    );
\udp_presum[7]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFE8E800"
    )
        port map (
      I0 => \udp_presum_reg[7]_i_11_n_5\,
      I1 => \udp_presum_reg[7]_i_12_n_5\,
      I2 => \udp_presum_reg[7]_i_13_n_5\,
      I3 => source_ip(19),
      I4 => \udp_presum[7]_i_15_n_0\,
      O => \udp_presum[7]_i_5_n_0\
    );
\udp_presum[7]_i_6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \udp_presum[7]_i_2_n_0\,
      I1 => \udp_presum[11]_i_20_n_0\,
      I2 => \udp_presum[7]_i_16_n_0\,
      O => \udp_presum[7]_i_6_n_0\
    );
\udp_presum[7]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"56AAAAA9AAA9A955"
    )
        port map (
      I0 => \udp_presum[7]_i_17_n_0\,
      I1 => \udp_presum_reg[11]_i_13_n_7\,
      I2 => \udp_presum_reg[11]_i_15_n_7\,
      I3 => source_ip(21),
      I4 => \udp_presum[7]_i_18_n_0\,
      I5 => \udp_presum[7]_i_19_n_0\,
      O => \udp_presum[7]_i_7_n_0\
    );
\udp_presum[7]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6669"
    )
        port map (
      I0 => \udp_presum[7]_i_4_n_0\,
      I1 => \udp_presum[7]_i_20_n_0\,
      I2 => \udp_presum_reg[11]_i_15_n_7\,
      I3 => \udp_presum_reg[11]_i_13_n_7\,
      O => \udp_presum[7]_i_8_n_0\
    );
\udp_presum[7]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \udp_presum[7]_i_5_n_0\,
      I1 => \udp_presum[7]_i_21_n_0\,
      I2 => source_ip(20),
      I3 => \udp_presum_reg[11]_i_14_n_7\,
      I4 => \udp_presum_reg[11]_i_13_n_7\,
      I5 => \udp_presum_reg[11]_i_15_n_7\,
      O => \udp_presum[7]_i_9_n_0\
    );
udp_presum_done_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => p_0_in57_in,
      I1 => arp_request_expected,
      I2 => eth_protocol_expected,
      O => udp_presum_done_i_1_n_0
    );
udp_presum_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => udp_presum_done_i_1_n_0,
      Q => udp_presum_done,
      R => '0'
    );
\udp_presum_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[3]_i_1_n_7\,
      Q => \udp_presum_reg_n_0_[0]\,
      R => udp_presum
    );
\udp_presum_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[11]_i_1_n_5\,
      Q => \udp_presum_reg_n_0_[10]\,
      R => udp_presum
    );
\udp_presum_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[11]_i_1_n_4\,
      Q => \udp_presum_reg_n_0_[11]\,
      R => udp_presum
    );
\udp_presum_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[7]_i_1_n_0\,
      CO(3) => \udp_presum_reg[11]_i_1_n_0\,
      CO(2) => \udp_presum_reg[11]_i_1_n_1\,
      CO(1) => \udp_presum_reg[11]_i_1_n_2\,
      CO(0) => \udp_presum_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum[11]_i_2_n_0\,
      DI(2) => \udp_presum[11]_i_3_n_0\,
      DI(1) => \udp_presum[11]_i_4_n_0\,
      DI(0) => \udp_presum[11]_i_5_n_0\,
      O(3) => \udp_presum_reg[11]_i_1_n_4\,
      O(2) => \udp_presum_reg[11]_i_1_n_5\,
      O(1) => \udp_presum_reg[11]_i_1_n_6\,
      O(0) => \udp_presum_reg[11]_i_1_n_7\,
      S(3) => \udp_presum[11]_i_6_n_0\,
      S(2) => \udp_presum[11]_i_7_n_0\,
      S(1) => \udp_presum[11]_i_8_n_0\,
      S(0) => \udp_presum[11]_i_9_n_0\
    );
\udp_presum_reg[11]_i_13\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[7]_i_13_n_0\,
      CO(3) => \udp_presum_reg[11]_i_13_n_0\,
      CO(2) => \udp_presum_reg[11]_i_13_n_1\,
      CO(1) => \udp_presum_reg[11]_i_13_n_2\,
      CO(0) => \udp_presum_reg[11]_i_13_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum[11]_i_25_n_0\,
      DI(2) => \udp_presum[11]_i_26_n_0\,
      DI(1) => \udp_presum[11]_i_27_n_0\,
      DI(0) => \udp_presum[11]_i_28_n_0\,
      O(3) => \udp_presum_reg[11]_i_13_n_4\,
      O(2) => \udp_presum_reg[11]_i_13_n_5\,
      O(1) => \udp_presum_reg[11]_i_13_n_6\,
      O(0) => \udp_presum_reg[11]_i_13_n_7\,
      S(3) => \udp_presum[11]_i_29_n_0\,
      S(2) => \udp_presum[11]_i_30_n_0\,
      S(1) => \udp_presum[11]_i_31_n_0\,
      S(0) => \udp_presum[11]_i_32_n_0\
    );
\udp_presum_reg[11]_i_14\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[7]_i_12_n_0\,
      CO(3) => \udp_presum_reg[11]_i_14_n_0\,
      CO(2) => \udp_presum_reg[11]_i_14_n_1\,
      CO(1) => \udp_presum_reg[11]_i_14_n_2\,
      CO(0) => \udp_presum_reg[11]_i_14_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum[11]_i_33_n_0\,
      DI(2) => \udp_presum[11]_i_34_n_0\,
      DI(1) => \udp_presum[11]_i_35_n_0\,
      DI(0) => \udp_presum[11]_i_36_n_0\,
      O(3) => \udp_presum_reg[11]_i_14_n_4\,
      O(2) => \udp_presum_reg[11]_i_14_n_5\,
      O(1) => \udp_presum_reg[11]_i_14_n_6\,
      O(0) => \udp_presum_reg[11]_i_14_n_7\,
      S(3) => \udp_presum[11]_i_37_n_0\,
      S(2) => \udp_presum[11]_i_38_n_0\,
      S(1) => \udp_presum[11]_i_39_n_0\,
      S(0) => \udp_presum[11]_i_40_n_0\
    );
\udp_presum_reg[11]_i_15\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[7]_i_11_n_0\,
      CO(3) => \udp_presum_reg[11]_i_15_n_0\,
      CO(2) => \udp_presum_reg[11]_i_15_n_1\,
      CO(1) => \udp_presum_reg[11]_i_15_n_2\,
      CO(0) => \udp_presum_reg[11]_i_15_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"01",
      DI(1) => source_ip(5),
      DI(0) => \udp_presum[11]_i_41_n_0\,
      O(3) => \udp_presum_reg[11]_i_15_n_4\,
      O(2) => \udp_presum_reg[11]_i_15_n_5\,
      O(1) => \udp_presum_reg[11]_i_15_n_6\,
      O(0) => \udp_presum_reg[11]_i_15_n_7\,
      S(3) => \udp_presum[11]_i_42_n_0\,
      S(2) => \udp_presum[11]_i_43_n_0\,
      S(1) => \udp_presum[11]_i_44_n_0\,
      S(0) => \udp_presum[11]_i_45_n_0\
    );
\udp_presum_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[15]_i_1_n_7\,
      Q => \udp_presum_reg_n_0_[12]\,
      R => udp_presum
    );
\udp_presum_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[15]_i_1_n_6\,
      Q => \udp_presum_reg_n_0_[13]\,
      R => udp_presum
    );
\udp_presum_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[15]_i_1_n_5\,
      Q => \udp_presum_reg_n_0_[14]\,
      R => udp_presum
    );
\udp_presum_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[15]_i_1_n_4\,
      Q => \udp_presum_reg_n_0_[15]\,
      R => udp_presum
    );
\udp_presum_reg[15]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[11]_i_1_n_0\,
      CO(3) => \udp_presum_reg[15]_i_1_n_0\,
      CO(2) => \udp_presum_reg[15]_i_1_n_1\,
      CO(1) => \udp_presum_reg[15]_i_1_n_2\,
      CO(0) => \udp_presum_reg[15]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum[15]_i_2_n_0\,
      DI(2) => \udp_presum[15]_i_3_n_0\,
      DI(1) => \udp_presum[15]_i_4_n_0\,
      DI(0) => \udp_presum[15]_i_5_n_0\,
      O(3) => \udp_presum_reg[15]_i_1_n_4\,
      O(2) => \udp_presum_reg[15]_i_1_n_5\,
      O(1) => \udp_presum_reg[15]_i_1_n_6\,
      O(0) => \udp_presum_reg[15]_i_1_n_7\,
      S(3) => \udp_presum[15]_i_6_n_0\,
      S(2) => \udp_presum[15]_i_7_n_0\,
      S(1) => \udp_presum[15]_i_8_n_0\,
      S(0) => \udp_presum[15]_i_9_n_0\
    );
\udp_presum_reg[15]_i_13\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[11]_i_13_n_0\,
      CO(3) => \udp_presum_reg[15]_i_13_n_0\,
      CO(2) => \udp_presum_reg[15]_i_13_n_1\,
      CO(1) => \udp_presum_reg[15]_i_13_n_2\,
      CO(0) => \udp_presum_reg[15]_i_13_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum[15]_i_25_n_0\,
      DI(2) => \udp_presum[15]_i_26_n_0\,
      DI(1) => \udp_presum[15]_i_27_n_0\,
      DI(0) => \udp_presum[15]_i_28_n_0\,
      O(3) => \udp_presum_reg[15]_i_13_n_4\,
      O(2) => \udp_presum_reg[15]_i_13_n_5\,
      O(1) => \udp_presum_reg[15]_i_13_n_6\,
      O(0) => \udp_presum_reg[15]_i_13_n_7\,
      S(3) => \udp_presum[15]_i_29_n_0\,
      S(2) => \udp_presum[15]_i_30_n_0\,
      S(1) => \udp_presum[15]_i_31_n_0\,
      S(0) => \udp_presum[15]_i_32_n_0\
    );
\udp_presum_reg[15]_i_14\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[11]_i_14_n_0\,
      CO(3) => \udp_presum_reg[15]_i_14_n_0\,
      CO(2) => \udp_presum_reg[15]_i_14_n_1\,
      CO(1) => \udp_presum_reg[15]_i_14_n_2\,
      CO(0) => \udp_presum_reg[15]_i_14_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum[15]_i_33_n_0\,
      DI(2) => \udp_presum[15]_i_34_n_0\,
      DI(1) => \udp_presum[15]_i_35_n_0\,
      DI(0) => \udp_presum[15]_i_36_n_0\,
      O(3) => \udp_presum_reg[15]_i_14_n_4\,
      O(2) => \udp_presum_reg[15]_i_14_n_5\,
      O(1) => \udp_presum_reg[15]_i_14_n_6\,
      O(0) => \udp_presum_reg[15]_i_14_n_7\,
      S(3) => \udp_presum[15]_i_37_n_0\,
      S(2) => \udp_presum[15]_i_38_n_0\,
      S(1) => \udp_presum[15]_i_39_n_0\,
      S(0) => \udp_presum[15]_i_40_n_0\
    );
\udp_presum_reg[15]_i_15\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[11]_i_15_n_0\,
      CO(3) => \udp_presum_reg[15]_i_15_n_0\,
      CO(2) => \udp_presum_reg[15]_i_15_n_1\,
      CO(1) => \udp_presum_reg[15]_i_15_n_2\,
      CO(0) => \udp_presum_reg[15]_i_15_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => source_ip(8 downto 7),
      O(3) => \udp_presum_reg[15]_i_15_n_4\,
      O(2) => \udp_presum_reg[15]_i_15_n_5\,
      O(1) => \udp_presum_reg[15]_i_15_n_6\,
      O(0) => \udp_presum_reg[15]_i_15_n_7\,
      S(3 downto 2) => source_ip(11 downto 10),
      S(1) => \udp_presum[15]_i_41_n_0\,
      S(0) => \udp_presum[15]_i_42_n_0\
    );
\udp_presum_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[19]_i_1_n_7\,
      Q => \udp_presum_reg_n_0_[16]\,
      R => udp_presum
    );
\udp_presum_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[19]_i_1_n_6\,
      Q => \udp_presum_reg_n_0_[17]\,
      R => udp_presum
    );
\udp_presum_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[19]_i_1_n_5\,
      Q => \udp_presum_reg_n_0_[18]\,
      R => udp_presum
    );
\udp_presum_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[19]_i_1_n_4\,
      Q => \udp_presum_reg_n_0_[19]\,
      R => udp_presum
    );
\udp_presum_reg[19]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[15]_i_1_n_0\,
      CO(3) => \udp_presum_reg[19]_i_1_n_0\,
      CO(2) => \udp_presum_reg[19]_i_1_n_1\,
      CO(1) => \udp_presum_reg[19]_i_1_n_2\,
      CO(0) => \udp_presum_reg[19]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum[19]_i_2_n_0\,
      DI(2) => \udp_presum[19]_i_3_n_0\,
      DI(1) => \udp_presum[19]_i_4_n_0\,
      DI(0) => \udp_presum[19]_i_5_n_0\,
      O(3) => \udp_presum_reg[19]_i_1_n_4\,
      O(2) => \udp_presum_reg[19]_i_1_n_5\,
      O(1) => \udp_presum_reg[19]_i_1_n_6\,
      O(0) => \udp_presum_reg[19]_i_1_n_7\,
      S(3) => \udp_presum[19]_i_6_n_0\,
      S(2) => \udp_presum[19]_i_7_n_0\,
      S(1) => \udp_presum[19]_i_8_n_0\,
      S(0) => \udp_presum[19]_i_9_n_0\
    );
\udp_presum_reg[19]_i_10\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[19]_i_12_n_0\,
      CO(3 downto 2) => \NLW_udp_presum_reg[19]_i_10_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \udp_presum_reg[19]_i_10_n_2\,
      CO(0) => \NLW_udp_presum_reg[19]_i_10_CO_UNCONNECTED\(0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_udp_presum_reg[19]_i_10_O_UNCONNECTED\(3 downto 1),
      O(0) => \udp_presum_reg[19]_i_10_n_7\,
      S(3 downto 1) => B"001",
      S(0) => \udp_presum[19]_i_21_n_0\
    );
\udp_presum_reg[19]_i_11\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[19]_i_14_n_0\,
      CO(3 downto 2) => \NLW_udp_presum_reg[19]_i_11_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \udp_presum_reg[19]_i_11_n_2\,
      CO(0) => \NLW_udp_presum_reg[19]_i_11_CO_UNCONNECTED\(0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_udp_presum_reg[19]_i_11_O_UNCONNECTED\(3 downto 1),
      O(0) => \udp_presum_reg[19]_i_11_n_7\,
      S(3 downto 1) => B"001",
      S(0) => source_ip(15)
    );
\udp_presum_reg[19]_i_12\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[15]_i_13_n_0\,
      CO(3) => \udp_presum_reg[19]_i_12_n_0\,
      CO(2) => \udp_presum_reg[19]_i_12_n_1\,
      CO(1) => \udp_presum_reg[19]_i_12_n_2\,
      CO(0) => \udp_presum_reg[19]_i_12_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum[19]_i_22_n_0\,
      DI(2) => \udp_presum[19]_i_23_n_0\,
      DI(1) => \udp_presum[19]_i_24_n_0\,
      DI(0) => \udp_presum[19]_i_25_n_0\,
      O(3) => \udp_presum_reg[19]_i_12_n_4\,
      O(2) => \udp_presum_reg[19]_i_12_n_5\,
      O(1) => \udp_presum_reg[19]_i_12_n_6\,
      O(0) => \udp_presum_reg[19]_i_12_n_7\,
      S(3) => \udp_presum[19]_i_26_n_0\,
      S(2) => \udp_presum[19]_i_27_n_0\,
      S(1) => \udp_presum[19]_i_28_n_0\,
      S(0) => \udp_presum[19]_i_29_n_0\
    );
\udp_presum_reg[19]_i_13\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[15]_i_14_n_0\,
      CO(3) => \udp_presum_reg[19]_i_13_n_0\,
      CO(2) => \udp_presum_reg[19]_i_13_n_1\,
      CO(1) => \udp_presum_reg[19]_i_13_n_2\,
      CO(0) => \udp_presum_reg[19]_i_13_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum[19]_i_30_n_0\,
      DI(2) => \udp_presum[19]_i_31_n_0\,
      DI(1) => \udp_presum[19]_i_32_n_0\,
      DI(0) => \udp_presum[19]_i_33_n_0\,
      O(3) => \udp_presum_reg[19]_i_13_n_4\,
      O(2) => \udp_presum_reg[19]_i_13_n_5\,
      O(1) => \udp_presum_reg[19]_i_13_n_6\,
      O(0) => \udp_presum_reg[19]_i_13_n_7\,
      S(3) => \udp_presum[19]_i_34_n_0\,
      S(2) => \udp_presum[19]_i_35_n_0\,
      S(1) => \udp_presum[19]_i_36_n_0\,
      S(0) => \udp_presum[19]_i_37_n_0\
    );
\udp_presum_reg[19]_i_14\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[15]_i_15_n_0\,
      CO(3) => \udp_presum_reg[19]_i_14_n_0\,
      CO(2) => \udp_presum_reg[19]_i_14_n_1\,
      CO(1) => \udp_presum_reg[19]_i_14_n_2\,
      CO(0) => \udp_presum_reg[19]_i_14_n_3\,
      CYINIT => '0',
      DI(3) => source_ip(14),
      DI(2 downto 0) => B"000",
      O(3) => \udp_presum_reg[19]_i_14_n_4\,
      O(2) => \udp_presum_reg[19]_i_14_n_5\,
      O(1) => \udp_presum_reg[19]_i_14_n_6\,
      O(0) => \udp_presum_reg[19]_i_14_n_7\,
      S(3) => \udp_presum[19]_i_38_n_0\,
      S(2) => \udp_presum[19]_i_39_n_0\,
      S(1 downto 0) => source_ip(13 downto 12)
    );
\udp_presum_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[3]_i_1_n_6\,
      Q => \udp_presum_reg_n_0_[1]\,
      R => udp_presum
    );
\udp_presum_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[23]_i_3_n_7\,
      Q => \udp_presum_reg_n_0_[20]\,
      R => udp_presum
    );
\udp_presum_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[23]_i_3_n_6\,
      Q => \udp_presum_reg_n_0_[21]\,
      R => udp_presum
    );
\udp_presum_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[23]_i_3_n_5\,
      Q => \udp_presum_reg_n_0_[22]\,
      R => udp_presum
    );
\udp_presum_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[23]_i_3_n_4\,
      Q => \udp_presum_reg_n_0_[23]\,
      R => udp_presum
    );
\udp_presum_reg[23]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[19]_i_1_n_0\,
      CO(3) => \NLW_udp_presum_reg[23]_i_3_CO_UNCONNECTED\(3),
      CO(2) => \udp_presum_reg[23]_i_3_n_1\,
      CO(1) => \udp_presum_reg[23]_i_3_n_2\,
      CO(0) => \udp_presum_reg[23]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \udp_presum_reg[23]_i_3_n_4\,
      O(2) => \udp_presum_reg[23]_i_3_n_5\,
      O(1) => \udp_presum_reg[23]_i_3_n_6\,
      O(0) => \udp_presum_reg[23]_i_3_n_7\,
      S(3) => \udp_presum_reg[23]_i_4_n_4\,
      S(2) => \udp_presum_reg[23]_i_4_n_5\,
      S(1) => \udp_presum_reg[23]_i_4_n_6\,
      S(0) => \udp_presum_reg[23]_i_4_n_7\
    );
\udp_presum_reg[23]_i_4\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[23]_i_5_n_0\,
      CO(3) => \NLW_udp_presum_reg[23]_i_4_CO_UNCONNECTED\(3),
      CO(2) => \udp_presum_reg[23]_i_4_n_1\,
      CO(1) => \udp_presum_reg[23]_i_4_n_2\,
      CO(0) => \udp_presum_reg[23]_i_4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \udp_presum_reg[23]_i_4_n_4\,
      O(2) => \udp_presum_reg[23]_i_4_n_5\,
      O(1) => \udp_presum_reg[23]_i_4_n_6\,
      O(0) => \udp_presum_reg[23]_i_4_n_7\,
      S(3) => \udp_presum_reg_n_0_[23]\,
      S(2) => \udp_presum_reg_n_0_[22]\,
      S(1) => \udp_presum_reg_n_0_[21]\,
      S(0) => \udp_presum_reg_n_0_[20]\
    );
\udp_presum_reg[23]_i_5\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[19]_i_13_n_0\,
      CO(3) => \udp_presum_reg[23]_i_5_n_0\,
      CO(2) => \udp_presum_reg[23]_i_5_n_1\,
      CO(1) => \udp_presum_reg[23]_i_5_n_2\,
      CO(0) => \udp_presum_reg[23]_i_5_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \udp_presum_reg_n_0_[16]\,
      O(3) => \udp_presum_reg[23]_i_5_n_4\,
      O(2) => \udp_presum_reg[23]_i_5_n_5\,
      O(1) => \udp_presum_reg[23]_i_5_n_6\,
      O(0) => \udp_presum_reg[23]_i_5_n_7\,
      S(3) => \udp_presum_reg_n_0_[19]\,
      S(2) => \udp_presum_reg_n_0_[18]\,
      S(1) => \udp_presum_reg_n_0_[17]\,
      S(0) => \udp_presum[23]_i_6_n_0\
    );
\udp_presum_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[3]_i_1_n_5\,
      Q => \udp_presum_reg_n_0_[2]\,
      R => udp_presum
    );
\udp_presum_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[3]_i_1_n_4\,
      Q => \udp_presum_reg_n_0_[3]\,
      R => udp_presum
    );
\udp_presum_reg[3]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \udp_presum_reg[3]_i_1_n_0\,
      CO(2) => \udp_presum_reg[3]_i_1_n_1\,
      CO(1) => \udp_presum_reg[3]_i_1_n_2\,
      CO(0) => \udp_presum_reg[3]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum[3]_i_2_n_0\,
      DI(2) => \udp_presum[3]_i_3_n_0\,
      DI(1) => \udp_presum[3]_i_4_n_0\,
      DI(0) => \udp_presum[3]_i_5_n_0\,
      O(3) => \udp_presum_reg[3]_i_1_n_4\,
      O(2) => \udp_presum_reg[3]_i_1_n_5\,
      O(1) => \udp_presum_reg[3]_i_1_n_6\,
      O(0) => \udp_presum_reg[3]_i_1_n_7\,
      S(3) => \udp_presum[3]_i_6_n_0\,
      S(2) => \udp_presum[3]_i_7_n_0\,
      S(1) => \udp_presum[3]_i_8_n_0\,
      S(0) => \udp_presum[3]_i_9_n_0\
    );
\udp_presum_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[7]_i_1_n_7\,
      Q => \udp_presum_reg_n_0_[4]\,
      R => udp_presum
    );
\udp_presum_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[7]_i_1_n_6\,
      Q => \udp_presum_reg_n_0_[5]\,
      R => udp_presum
    );
\udp_presum_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[7]_i_1_n_5\,
      Q => \udp_presum_reg_n_0_[6]\,
      R => udp_presum
    );
\udp_presum_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[7]_i_1_n_4\,
      Q => \udp_presum_reg_n_0_[7]\,
      R => udp_presum
    );
\udp_presum_reg[7]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_presum_reg[3]_i_1_n_0\,
      CO(3) => \udp_presum_reg[7]_i_1_n_0\,
      CO(2) => \udp_presum_reg[7]_i_1_n_1\,
      CO(1) => \udp_presum_reg[7]_i_1_n_2\,
      CO(0) => \udp_presum_reg[7]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum[7]_i_2_n_0\,
      DI(2) => \udp_presum[7]_i_3_n_0\,
      DI(1) => \udp_presum[7]_i_4_n_0\,
      DI(0) => \udp_presum[7]_i_5_n_0\,
      O(3) => \udp_presum_reg[7]_i_1_n_4\,
      O(2) => \udp_presum_reg[7]_i_1_n_5\,
      O(1) => \udp_presum_reg[7]_i_1_n_6\,
      O(0) => \udp_presum_reg[7]_i_1_n_7\,
      S(3) => \udp_presum[7]_i_6_n_0\,
      S(2) => \udp_presum[7]_i_7_n_0\,
      S(1) => \udp_presum[7]_i_8_n_0\,
      S(0) => \udp_presum[7]_i_9_n_0\
    );
\udp_presum_reg[7]_i_11\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \udp_presum_reg[7]_i_11_n_0\,
      CO(2) => \udp_presum_reg[7]_i_11_n_1\,
      CO(1) => \udp_presum_reg[7]_i_11_n_2\,
      CO(0) => \udp_presum_reg[7]_i_11_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum[7]_i_22_n_0\,
      DI(2) => \udp_presum[7]_i_23_n_0\,
      DI(1) => \udp_presum[7]_i_24_n_0\,
      DI(0) => '0',
      O(3) => \udp_presum_reg[7]_i_11_n_4\,
      O(2) => \udp_presum_reg[7]_i_11_n_5\,
      O(1) => \udp_presum_reg[7]_i_11_n_6\,
      O(0) => \udp_presum_reg[7]_i_11_n_7\,
      S(3) => \udp_presum[7]_i_25_n_0\,
      S(2) => \udp_presum[7]_i_26_n_0\,
      S(1) => \udp_presum[7]_i_27_n_0\,
      S(0) => \udp_presum[7]_i_28_n_0\
    );
\udp_presum_reg[7]_i_12\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \udp_presum_reg[7]_i_12_n_0\,
      CO(2) => \udp_presum_reg[7]_i_12_n_1\,
      CO(1) => \udp_presum_reg[7]_i_12_n_2\,
      CO(0) => \udp_presum_reg[7]_i_12_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum[7]_i_29_n_0\,
      DI(2) => \udp_presum[7]_i_30_n_0\,
      DI(1) => \udp_presum[7]_i_31_n_0\,
      DI(0) => '0',
      O(3) => \udp_presum_reg[7]_i_12_n_4\,
      O(2) => \udp_presum_reg[7]_i_12_n_5\,
      O(1) => \udp_presum_reg[7]_i_12_n_6\,
      O(0) => \udp_presum_reg[7]_i_12_n_7\,
      S(3) => \udp_presum[7]_i_32_n_0\,
      S(2) => \udp_presum[7]_i_33_n_0\,
      S(1) => \udp_presum[7]_i_34_n_0\,
      S(0) => \udp_presum[7]_i_35_n_0\
    );
\udp_presum_reg[7]_i_13\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \udp_presum_reg[7]_i_13_n_0\,
      CO(2) => \udp_presum_reg[7]_i_13_n_1\,
      CO(1) => \udp_presum_reg[7]_i_13_n_2\,
      CO(0) => \udp_presum_reg[7]_i_13_n_3\,
      CYINIT => '0',
      DI(3) => \udp_presum[7]_i_36_n_0\,
      DI(2) => \udp_presum[7]_i_37_n_0\,
      DI(1) => \udp_presum[7]_i_38_n_0\,
      DI(0) => '0',
      O(3) => \udp_presum_reg[7]_i_13_n_4\,
      O(2) => \udp_presum_reg[7]_i_13_n_5\,
      O(1) => \udp_presum_reg[7]_i_13_n_6\,
      O(0) => \udp_presum_reg[7]_i_13_n_7\,
      S(3) => \udp_presum[7]_i_39_n_0\,
      S(2) => \udp_presum[7]_i_40_n_0\,
      S(1) => \udp_presum[7]_i_41_n_0\,
      S(0) => \udp_presum[7]_i_42_n_0\
    );
\udp_presum_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[11]_i_1_n_7\,
      Q => \udp_presum_reg_n_0_[8]\,
      R => udp_presum
    );
\udp_presum_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => udp_presum0,
      D => \udp_presum_reg[11]_i_1_n_6\,
      Q => \udp_presum_reg_n_0_[9]\,
      R => udp_presum
    );
udp_send_data_valid_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E000"
    )
        port map (
      I0 => udp_send_data_valid_i_2_n_0,
      I1 => udp_send_data_valid_i_3_n_0,
      I2 => udp_send_data_valid17_out,
      I3 => CO(0),
      O => udp_send_data_valid
    );
udp_send_data_valid_i_19: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^q\(21),
      I1 => \^q\(20),
      I2 => \^q\(23),
      I3 => \^q\(22),
      O => udp_send_data_valid_i_19_n_0
    );
udp_send_data_valid_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => udp_send_data_valid_i_6_n_0,
      I1 => \^q\(26),
      I2 => \^q\(25),
      I3 => \^q\(27),
      I4 => \^q\(24),
      I5 => udp_send_data_valid_i_7_n_0,
      O => udp_send_data_valid_i_2_n_0
    );
udp_send_data_valid_i_20: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^q\(5),
      I1 => \^q\(4),
      I2 => \^q\(7),
      I3 => \^q\(6),
      O => udp_send_data_valid_i_20_n_0
    );
udp_send_data_valid_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => udp_send_data_valid_i_8_n_0,
      I1 => \^q\(11),
      I2 => \^q\(10),
      I3 => \^q\(9),
      I4 => \^q\(8),
      I5 => udp_send_data_valid_i_9_n_0,
      O => udp_send_data_valid_i_3_n_0
    );
udp_send_data_valid_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^q\(30),
      I1 => \^q\(29),
      I2 => \^q\(31),
      I3 => \^q\(28),
      O => udp_send_data_valid_i_6_n_0
    );
udp_send_data_valid_i_7: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^q\(16),
      I1 => \^q\(19),
      I2 => \^q\(17),
      I3 => \^q\(18),
      I4 => udp_send_data_valid_i_19_n_0,
      O => udp_send_data_valid_i_7_n_0
    );
udp_send_data_valid_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^q\(13),
      I1 => \^q\(12),
      I2 => \^q\(15),
      I3 => \^q\(14),
      O => udp_send_data_valid_i_8_n_0
    );
udp_send_data_valid_i_9: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(3),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => udp_send_data_valid_i_20_n_0,
      O => udp_send_data_valid_i_9_n_0
    );
unknown_request1_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAA8AA8"
    )
        port map (
      I0 => read_eth_header_done,
      I1 => eth_protocol_expected_i_2_n_0,
      I2 => eth_prot_type(2),
      I3 => eth_prot_type(1),
      I4 => eth_protocol_expected_i_3_n_0,
      I5 => eth_protocol_expected_i_4_n_0,
      O => unknown_request1_i_1_n_0
    );
unknown_request1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => unknown_request1_i_1_n_0,
      Q => unknown_request1_reg_n_0,
      R => '0'
    );
unknown_request2_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400040"
    )
        port map (
      I0 => unknown_request2_reg_i_2_n_2,
      I1 => \byte_read_done_reg_n_0_[11]\,
      I2 => eth_protocol_expected,
      I3 => arp_request_expected,
      I4 => unknown_request20,
      I5 => unknown_request2_i_4_n_0,
      O => unknown_request2_i_1_n_0
    );
unknown_request2_i_10: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => bytes12(12),
      I1 => bytes12(11),
      I2 => bytes12(13),
      O => unknown_request2_i_10_n_0
    );
unknown_request2_i_11: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => bytes12(9),
      I1 => bytes12(8),
      I2 => bytes12(10),
      O => unknown_request2_i_11_n_0
    );
unknown_request2_i_12: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => bytes11(11),
      I1 => bytes11(10),
      I2 => bytes11(9),
      O => unknown_request2_i_12_n_0
    );
unknown_request2_i_13: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => bytes11(6),
      I1 => bytes11(7),
      I2 => bytes11(8),
      O => unknown_request2_i_13_n_0
    );
unknown_request2_i_14: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => bytes11(5),
      I1 => bytes11(4),
      I2 => bytes11(3),
      O => unknown_request2_i_14_n_0
    );
unknown_request2_i_15: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => bytes11(2),
      I1 => bytes11(1),
      I2 => bytes11(0),
      O => unknown_request2_i_15_n_0
    );
unknown_request2_i_17: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => bytes12(5),
      I1 => bytes12(7),
      I2 => bytes12(6),
      O => unknown_request2_i_17_n_0
    );
unknown_request2_i_18: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => bytes12(4),
      I1 => bytes12(3),
      I2 => bytes12(2),
      O => unknown_request2_i_18_n_0
    );
unknown_request2_i_19: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => bytes12(0),
      I1 => bytes13(15),
      I2 => bytes12(1),
      O => unknown_request2_i_19_n_0
    );
unknown_request2_i_20: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => bytes13(13),
      I1 => bytes13(12),
      I2 => bytes13(14),
      O => unknown_request2_i_20_n_0
    );
unknown_request2_i_21: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => bytes13(10),
      I1 => bytes13(9),
      I2 => bytes13(11),
      O => unknown_request2_i_21_n_0
    );
unknown_request2_i_22: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => bytes13(7),
      I1 => bytes13(8),
      I2 => bytes13(6),
      O => unknown_request2_i_22_n_0
    );
unknown_request2_i_23: unisim.vcomponents.LUT5
    generic map(
      INIT => X"90000090"
    )
        port map (
      I0 => bytes13(3),
      I1 => ip(3),
      I2 => bytes13(5),
      I3 => ip(4),
      I4 => bytes13(4),
      O => unknown_request2_i_23_n_0
    );
unknown_request2_i_24: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => bytes13(2),
      I1 => ip(2),
      I2 => ip(0),
      I3 => bytes13(0),
      I4 => ip(1),
      I5 => bytes13(1),
      O => unknown_request2_i_24_n_0
    );
unknown_request2_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2000"
    )
        port map (
      I0 => arp_request_expected,
      I1 => eth_protocol_expected,
      I2 => p_0_in57_in,
      I3 => p_1_in65_in,
      O => unknown_request2_i_4_n_0
    );
unknown_request2_i_6: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => bytes11(15),
      O => unknown_request2_i_6_n_0
    );
unknown_request2_i_7: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => bytes11(13),
      I1 => bytes11(12),
      I2 => bytes11(14),
      O => unknown_request2_i_7_n_0
    );
unknown_request2_i_9: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => bytes12(15),
      I1 => bytes12(14),
      O => unknown_request2_i_9_n_0
    );
unknown_request2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => unknown_request2_i_1_n_0,
      Q => unknown_request2,
      R => '0'
    );
unknown_request2_reg_i_16: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => unknown_request2_reg_i_16_n_0,
      CO(2) => unknown_request2_reg_i_16_n_1,
      CO(1) => unknown_request2_reg_i_16_n_2,
      CO(0) => unknown_request2_reg_i_16_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_unknown_request2_reg_i_16_O_UNCONNECTED(3 downto 0),
      S(3) => unknown_request2_i_21_n_0,
      S(2) => unknown_request2_i_22_n_0,
      S(1) => unknown_request2_i_23_n_0,
      S(0) => unknown_request2_i_24_n_0
    );
unknown_request2_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => unknown_request2_reg_i_5_n_0,
      CO(3 downto 2) => NLW_unknown_request2_reg_i_2_CO_UNCONNECTED(3 downto 2),
      CO(1) => unknown_request2_reg_i_2_n_2,
      CO(0) => unknown_request2_reg_i_2_n_3,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_unknown_request2_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => unknown_request2_i_6_n_0,
      S(0) => unknown_request2_i_7_n_0
    );
unknown_request2_reg_i_3: unisim.vcomponents.CARRY4
     port map (
      CI => unknown_request2_reg_i_8_n_0,
      CO(3) => NLW_unknown_request2_reg_i_3_CO_UNCONNECTED(3),
      CO(2) => unknown_request20,
      CO(1) => unknown_request2_reg_i_3_n_2,
      CO(0) => unknown_request2_reg_i_3_n_3,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_unknown_request2_reg_i_3_O_UNCONNECTED(3 downto 0),
      S(3) => '0',
      S(2) => unknown_request2_i_9_n_0,
      S(1) => unknown_request2_i_10_n_0,
      S(0) => unknown_request2_i_11_n_0
    );
unknown_request2_reg_i_5: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => unknown_request2_reg_i_5_n_0,
      CO(2) => unknown_request2_reg_i_5_n_1,
      CO(1) => unknown_request2_reg_i_5_n_2,
      CO(0) => unknown_request2_reg_i_5_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_unknown_request2_reg_i_5_O_UNCONNECTED(3 downto 0),
      S(3) => unknown_request2_i_12_n_0,
      S(2) => unknown_request2_i_13_n_0,
      S(1) => unknown_request2_i_14_n_0,
      S(0) => unknown_request2_i_15_n_0
    );
unknown_request2_reg_i_8: unisim.vcomponents.CARRY4
     port map (
      CI => unknown_request2_reg_i_16_n_0,
      CO(3) => unknown_request2_reg_i_8_n_0,
      CO(2) => unknown_request2_reg_i_8_n_1,
      CO(1) => unknown_request2_reg_i_8_n_2,
      CO(0) => unknown_request2_reg_i_8_n_3,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_unknown_request2_reg_i_8_O_UNCONNECTED(3 downto 0),
      S(3) => unknown_request2_i_17_n_0,
      S(2) => unknown_request2_i_18_n_0,
      S(1) => unknown_request2_i_19_n_0,
      S(0) => unknown_request2_i_20_n_0
    );
unknown_request3_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAA8AA"
    )
        port map (
      I0 => ip_hcs_done,
      I1 => unknown_request3_i_2_n_0,
      I2 => unknown_request3_i_3_n_0,
      I3 => unknown_request3_i_4_n_0,
      I4 => unknown_request3_i_5_n_0,
      O => unknown_request3_i_1_n_0
    );
unknown_request3_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \ip_hcs_calc__0\(11),
      I1 => \ip_hcs_calc__0\(2),
      I2 => \ip_hcs_calc__0\(15),
      I3 => \ip_hcs_calc__0\(4),
      O => unknown_request3_i_2_n_0
    );
unknown_request3_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \ip_hcs_calc__0\(14),
      I1 => \ip_hcs_calc__0\(0),
      I2 => \ip_hcs_calc__0\(12),
      I3 => \ip_hcs_calc__0\(3),
      O => unknown_request3_i_3_n_0
    );
unknown_request3_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \ip_hcs_calc__0\(6),
      I1 => \ip_hcs_calc__0\(5),
      I2 => \ip_hcs_calc__0\(9),
      I3 => \ip_hcs_calc__0\(8),
      O => unknown_request3_i_4_n_0
    );
unknown_request3_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \ip_hcs_calc__0\(13),
      I1 => \ip_hcs_calc__0\(10),
      I2 => \ip_hcs_calc__0\(7),
      I3 => \ip_hcs_calc__0\(1),
      O => unknown_request3_i_5_n_0
    );
unknown_request3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => unknown_request3_i_1_n_0,
      Q => unknown_request3_reg_n_0,
      R => '0'
    );
unknown_request4_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAA8AA"
    )
        port map (
      I0 => udp_hcs_done,
      I1 => unknown_request4_i_2_n_0,
      I2 => unknown_request4_i_3_n_0,
      I3 => unknown_request4_i_4_n_0,
      I4 => unknown_request4_i_5_n_0,
      O => unknown_request4_i_1_n_0
    );
unknown_request4_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \udp_hcs_calc__0\(11),
      I1 => \udp_hcs_calc__0\(2),
      I2 => \udp_hcs_calc__0\(15),
      I3 => \udp_hcs_calc__0\(4),
      O => unknown_request4_i_2_n_0
    );
unknown_request4_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \udp_hcs_calc__0\(14),
      I1 => \udp_hcs_calc__0\(0),
      I2 => \udp_hcs_calc__0\(12),
      I3 => \udp_hcs_calc__0\(3),
      O => unknown_request4_i_3_n_0
    );
unknown_request4_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \udp_hcs_calc__0\(6),
      I1 => \udp_hcs_calc__0\(5),
      I2 => \udp_hcs_calc__0\(9),
      I3 => \udp_hcs_calc__0\(8),
      O => unknown_request4_i_4_n_0
    );
unknown_request4_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \udp_hcs_calc__0\(13),
      I1 => \udp_hcs_calc__0\(10),
      I2 => \udp_hcs_calc__0\(7),
      I3 => \udp_hcs_calc__0\(1),
      O => unknown_request4_i_5_n_0
    );
unknown_request4_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => unknown_request4_i_1_n_0,
      Q => unknown_request4_reg_n_0,
      R => '0'
    );
valid_data_byte_read_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF00BF00000080"
    )
        port map (
      I0 => \byte_read_done[6]_i_2_n_0\,
      I1 => start_crc277_in,
      I2 => valid_data_byte_read_i_3_n_0,
      I3 => \state_reg[1]_rep_n_0\,
      I4 => valid_data_byte_read_i_4_n_0,
      I5 => valid_data_byte_read_reg_n_0,
      O => valid_data_byte_read_i_1_n_0
    );
valid_data_byte_read_i_10: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55510004F575501C"
    )
        port map (
      I0 => \byte_count_reg_n_0_[7]\,
      I1 => valid_data_byte_read_i_20_n_0,
      I2 => \data_counter_max_reg_n_0_[6]\,
      I3 => \data_counter_max_reg_n_0_[5]\,
      I4 => \data_counter_max_reg_n_0_[7]\,
      I5 => \byte_count_reg_n_0_[6]\,
      O => valid_data_byte_read_i_10_n_0
    );
valid_data_byte_read_i_11: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5104751C"
    )
        port map (
      I0 => \byte_count_reg_n_0_[5]\,
      I1 => valid_data_byte_read_i_21_n_0,
      I2 => \data_counter_max_reg_n_0_[4]\,
      I3 => \data_counter_max_reg_n_0_[5]\,
      I4 => \byte_count_reg_n_0_[4]\,
      O => valid_data_byte_read_i_11_n_0
    );
valid_data_byte_read_i_12: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55540001FD555403"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \data_counter_max_reg_n_0_[1]\,
      I2 => \data_counter_max_reg_n_0_[0]\,
      I3 => \data_counter_max_reg_n_0_[2]\,
      I4 => \data_counter_max_reg_n_0_[3]\,
      I5 => \byte_count_reg_n_0_[2]\,
      O => valid_data_byte_read_i_12_n_0
    );
valid_data_byte_read_i_13: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4147"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \data_counter_max_reg_n_0_[1]\,
      I2 => \data_counter_max_reg_n_0_[0]\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      O => valid_data_byte_read_i_13_n_0
    );
valid_data_byte_read_i_14: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9090069009099009"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[7]\,
      I1 => \byte_count_reg_n_0_[7]\,
      I2 => \data_counter_max_reg_n_0_[6]\,
      I3 => valid_data_byte_read_i_20_n_0,
      I4 => \data_counter_max_reg_n_0_[5]\,
      I5 => \byte_count_reg_n_0_[6]\,
      O => valid_data_byte_read_i_14_n_0
    );
valid_data_byte_read_i_15: unisim.vcomponents.LUT5
    generic map(
      INIT => X"09609009"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[5]\,
      I1 => \byte_count_reg_n_0_[5]\,
      I2 => valid_data_byte_read_i_21_n_0,
      I3 => \data_counter_max_reg_n_0_[4]\,
      I4 => \byte_count_reg_n_0_[4]\,
      O => valid_data_byte_read_i_15_n_0
    );
valid_data_byte_read_i_16: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8484844221212118"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \data_counter_max_reg_n_0_[3]\,
      I2 => \data_counter_max_reg_n_0_[2]\,
      I3 => \data_counter_max_reg_n_0_[0]\,
      I4 => \data_counter_max_reg_n_0_[1]\,
      I5 => \byte_count_reg_n_0_[3]\,
      O => valid_data_byte_read_i_16_n_0
    );
valid_data_byte_read_i_17: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0690"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \data_counter_max_reg_n_0_[0]\,
      I3 => \byte_count_reg[0]_rep__1_n_0\,
      O => valid_data_byte_read_i_17_n_0
    );
valid_data_byte_read_i_18: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[5]\,
      I1 => \data_counter_max_reg_n_0_[6]\,
      I2 => valid_data_byte_read_i_20_n_0,
      I3 => \data_counter_max_reg_n_0_[8]\,
      I4 => \data_counter_max_reg_n_0_[7]\,
      O => valid_data_byte_read_i_18_n_0
    );
valid_data_byte_read_i_19: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => valid_data_byte_read_i_20_n_0,
      I1 => \data_counter_max_reg_n_0_[6]\,
      I2 => \data_counter_max_reg_n_0_[5]\,
      O => valid_data_byte_read_i_19_n_0
    );
valid_data_byte_read_i_20: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[0]\,
      I1 => \data_counter_max_reg_n_0_[3]\,
      I2 => \data_counter_max_reg_n_0_[2]\,
      I3 => \data_counter_max_reg_n_0_[1]\,
      I4 => \data_counter_max_reg_n_0_[4]\,
      O => valid_data_byte_read_i_20_n_0
    );
valid_data_byte_read_i_21: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[1]\,
      I1 => \data_counter_max_reg_n_0_[2]\,
      I2 => \data_counter_max_reg_n_0_[3]\,
      I3 => \data_counter_max_reg_n_0_[0]\,
      O => valid_data_byte_read_i_21_n_0
    );
valid_data_byte_read_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => unknown_request1_reg_n_0,
      I1 => unknown_request4_reg_n_0,
      I2 => unknown_request3_reg_n_0,
      I3 => unknown_request2,
      I4 => start_crc_i_2_n_0,
      I5 => \state_reg_n_0_[0]\,
      O => valid_data_byte_read_i_3_n_0
    );
valid_data_byte_read_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => eth_rstn,
      O => valid_data_byte_read_i_4_n_0
    );
valid_data_byte_read_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4500"
    )
        port map (
      I0 => \byte_count_reg_n_0_[10]\,
      I1 => \data_counter_max_reg_n_0_[9]\,
      I2 => valid_data_byte_read_i_18_n_0,
      I3 => \data_counter_max_reg_n_0_[10]\,
      O => valid_data_byte_read_i_6_n_0
    );
valid_data_byte_read_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55510004F575501C"
    )
        port map (
      I0 => \byte_count_reg_n_0_[9]\,
      I1 => valid_data_byte_read_i_19_n_0,
      I2 => \data_counter_max_reg_n_0_[8]\,
      I3 => \data_counter_max_reg_n_0_[7]\,
      I4 => \data_counter_max_reg_n_0_[9]\,
      I5 => \byte_count_reg_n_0_[8]\,
      O => valid_data_byte_read_i_7_n_0
    );
valid_data_byte_read_i_8: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CC0C1151"
    )
        port map (
      I0 => \state[1]_i_10_n_0\,
      I1 => \data_counter_max_reg_n_0_[10]\,
      I2 => valid_data_byte_read_i_18_n_0,
      I3 => \data_counter_max_reg_n_0_[9]\,
      I4 => \byte_count_reg_n_0_[10]\,
      O => valid_data_byte_read_i_8_n_0
    );
valid_data_byte_read_i_9: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8442884421182211"
    )
        port map (
      I0 => \byte_count_reg_n_0_[8]\,
      I1 => \data_counter_max_reg_n_0_[9]\,
      I2 => \data_counter_max_reg_n_0_[7]\,
      I3 => \data_counter_max_reg_n_0_[8]\,
      I4 => valid_data_byte_read_i_19_n_0,
      I5 => \byte_count_reg_n_0_[9]\,
      O => valid_data_byte_read_i_9_n_0
    );
valid_data_byte_read_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => valid_data_byte_read_i_1_n_0,
      Q => valid_data_byte_read_reg_n_0,
      R => '0'
    );
valid_data_byte_read_reg_i_2: unisim.vcomponents.CARRY4
     port map (
      CI => valid_data_byte_read_reg_i_5_n_0,
      CO(3 downto 2) => NLW_valid_data_byte_read_reg_i_2_CO_UNCONNECTED(3 downto 2),
      CO(1) => start_crc277_in,
      CO(0) => valid_data_byte_read_reg_i_2_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => valid_data_byte_read_i_6_n_0,
      DI(0) => valid_data_byte_read_i_7_n_0,
      O(3 downto 0) => NLW_valid_data_byte_read_reg_i_2_O_UNCONNECTED(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => valid_data_byte_read_i_8_n_0,
      S(0) => valid_data_byte_read_i_9_n_0
    );
valid_data_byte_read_reg_i_5: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => valid_data_byte_read_reg_i_5_n_0,
      CO(2) => valid_data_byte_read_reg_i_5_n_1,
      CO(1) => valid_data_byte_read_reg_i_5_n_2,
      CO(0) => valid_data_byte_read_reg_i_5_n_3,
      CYINIT => '1',
      DI(3) => valid_data_byte_read_i_10_n_0,
      DI(2) => valid_data_byte_read_i_11_n_0,
      DI(1) => valid_data_byte_read_i_12_n_0,
      DI(0) => valid_data_byte_read_i_13_n_0,
      O(3 downto 0) => NLW_valid_data_byte_read_reg_i_5_O_UNCONNECTED(3 downto 0),
      S(3) => valid_data_byte_read_i_14_n_0,
      S(2) => valid_data_byte_read_i_15_n_0,
      S(1) => valid_data_byte_read_i_16_n_0,
      S(0) => valid_data_byte_read_i_17_n_0
    );
we_ram_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => s_ram(1),
      I1 => wrt_enable_ram,
      I2 => valid_data_byte_read_reg_n_0,
      O => we_ram_i_1_n_0
    );
we_ram_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => we_ram_i_1_n_0,
      Q => wrt_enable_ram,
      R => '0'
    );
\zero_counter[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[0]\,
      I1 => zero_counter(4),
      O => \zero_counter[0]_i_1_n_0\
    );
\zero_counter[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF41"
    )
        port map (
      I0 => zero_counter(4),
      I1 => \data_counter_max_reg_n_0_[0]\,
      I2 => \data_counter_max_reg_n_0_[1]\,
      I3 => \zero_counter[4]_i_4_n_0\,
      O => \zero_counter[1]_i_1_n_0\
    );
\zero_counter[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[0]\,
      I1 => \data_counter_max_reg_n_0_[1]\,
      I2 => \data_counter_max_reg_n_0_[2]\,
      I3 => zero_counter(4),
      O => \zero_counter[2]_i_1_n_0\
    );
\zero_counter[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000015EA"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[2]\,
      I1 => \data_counter_max_reg_n_0_[1]\,
      I2 => \data_counter_max_reg_n_0_[0]\,
      I3 => \data_counter_max_reg_n_0_[3]\,
      I4 => zero_counter(4),
      O => \zero_counter[3]_i_1_n_0\
    );
\zero_counter[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4144"
    )
        port map (
      I0 => zero_counter(4),
      I1 => \data_counter_max_reg_n_0_[4]\,
      I2 => \data_counter_max_reg_n_0_[3]\,
      I3 => \zero_counter[4]_i_3__0_n_0\,
      I4 => \zero_counter[4]_i_4_n_0\,
      O => \zero_counter[4]_i_1_n_0\
    );
\zero_counter[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEEEEEEEA"
    )
        port map (
      I0 => \zero_counter[4]_i_5_n_0\,
      I1 => \data_counter_max_reg_n_0_[4]\,
      I2 => \data_counter_max_reg_n_0_[1]\,
      I3 => \data_counter_max_reg_n_0_[2]\,
      I4 => \data_counter_max_reg_n_0_[3]\,
      I5 => data_counter_max,
      O => zero_counter(4)
    );
\zero_counter[4]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"15"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[2]\,
      I1 => \data_counter_max_reg_n_0_[1]\,
      I2 => \data_counter_max_reg_n_0_[0]\,
      O => \zero_counter[4]_i_3__0_n_0\
    );
\zero_counter[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \zero_counter[4]_i_6_n_0\,
      I1 => \zero_counter[4]_i_7_n_0\,
      I2 => bytes03(9),
      I3 => bytes03(5),
      I4 => bytes03(2),
      O => \zero_counter[4]_i_4_n_0\
    );
\zero_counter[4]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[6]\,
      I1 => \data_counter_max_reg_n_0_[5]\,
      I2 => \data_counter_max_reg_n_0_[9]\,
      I3 => \data_counter_max_reg_n_0_[10]\,
      I4 => \data_counter_max_reg_n_0_[7]\,
      I5 => \data_counter_max_reg_n_0_[8]\,
      O => \zero_counter[4]_i_5_n_0\
    );
\zero_counter[4]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => bytes03(6),
      I1 => bytes03(15),
      I2 => bytes03(13),
      I3 => bytes03(14),
      I4 => \zero_counter[4]_i_8_n_0\,
      O => \zero_counter[4]_i_6_n_0\
    );
\zero_counter[4]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => bytes03(3),
      I1 => bytes03(4),
      I2 => bytes03(8),
      I3 => bytes03(11),
      I4 => \zero_counter[4]_i_9_n_0\,
      O => \zero_counter[4]_i_7_n_0\
    );
\zero_counter[4]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => arp_request_expected,
      I1 => eth_protocol_expected,
      I2 => p_0_in,
      I3 => bytes03(1),
      O => \zero_counter[4]_i_8_n_0\
    );
\zero_counter[4]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => bytes03(0),
      I1 => bytes03(7),
      I2 => bytes03(12),
      I3 => bytes03(10),
      O => \zero_counter[4]_i_9_n_0\
    );
\zero_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \zero_counter[0]_i_1_n_0\,
      Q => \zero_counter_reg_n_0_[0]\,
      R => '0'
    );
\zero_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \zero_counter[1]_i_1_n_0\,
      Q => \zero_counter_reg_n_0_[1]\,
      R => '0'
    );
\zero_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \zero_counter[2]_i_1_n_0\,
      Q => \zero_counter_reg_n_0_[2]\,
      R => '0'
    );
\zero_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \zero_counter[3]_i_1_n_0\,
      Q => \zero_counter_reg_n_0_[3]\,
      R => '0'
    );
\zero_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \addr_count_reg[1]_0\,
      CE => '1',
      D => \zero_counter[4]_i_1_n_0\,
      Q => \zero_counter_reg_n_0_[4]\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_ethernet_transceiver2_0_0_eth_transmitter is
  port (
    eth_txen : out STD_LOGIC;
    fifo_read_enable : out STD_LOGIC;
    sent_arp_response : out STD_LOGIC;
    udp_send_data_valid17_out : out STD_LOGIC;
    db_sw_reg : out STD_LOGIC;
    arp_response_pending_reg : out STD_LOGIC;
    db_sw_reg_0 : out STD_LOGIC;
    eth_txd : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    b_clk50mhz_shift : in STD_LOGIC;
    eth_rstn : in STD_LOGIC;
    eth_protocol_reg_0 : in STD_LOGIC;
    eth_protocol_reg_1 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    ip : in STD_LOGIC_VECTOR ( 4 downto 0 );
    tx_data_valid_reg : in STD_LOGIC;
    state : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 13 downto 0 );
    fifo_read_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
    db_sw : in STD_LOGIC;
    arp_response_pending : in STD_LOGIC;
    \state_reg[0]_0\ : in STD_LOGIC;
    \data_counter_max_reg[10]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
    \dest_mac_reg[47]_0\ : in STD_LOGIC_VECTOR ( 47 downto 0 );
    \dest_ip_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \dest_port_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    udp_packet_checksum : in STD_LOGIC_VECTOR ( 15 downto 0 );
    b_clk100mhz : in STD_LOGIC
  );
end design_1_ethernet_transceiver2_0_0_eth_transmitter;

architecture STRUCTURE of design_1_ethernet_transceiver2_0_0_eth_transmitter is
  signal \FSM_onehot_s[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_s[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_s[2]_i_1_n_0\ : STD_LOGIC;
  signal L : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \L__0_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \L__0_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \L__0_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \L__0_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \L__0_carry__0_i_5_n_0\ : STD_LOGIC;
  signal \L__0_carry__0_i_6_n_0\ : STD_LOGIC;
  signal \L__0_carry__0_i_7_n_0\ : STD_LOGIC;
  signal \L__0_carry__0_i_8_n_0\ : STD_LOGIC;
  signal \L__0_carry__0_n_0\ : STD_LOGIC;
  signal \L__0_carry__0_n_1\ : STD_LOGIC;
  signal \L__0_carry__0_n_2\ : STD_LOGIC;
  signal \L__0_carry__0_n_3\ : STD_LOGIC;
  signal \L__0_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \L__0_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \L__0_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \L__0_carry__1_i_4_n_0\ : STD_LOGIC;
  signal \L__0_carry__1_i_5_n_0\ : STD_LOGIC;
  signal \L__0_carry__1_i_6_n_0\ : STD_LOGIC;
  signal \L__0_carry__1_i_7_n_0\ : STD_LOGIC;
  signal \L__0_carry__1_i_8_n_0\ : STD_LOGIC;
  signal \L__0_carry__1_n_0\ : STD_LOGIC;
  signal \L__0_carry__1_n_1\ : STD_LOGIC;
  signal \L__0_carry__1_n_2\ : STD_LOGIC;
  signal \L__0_carry__1_n_3\ : STD_LOGIC;
  signal \L__0_carry__2_i_1_n_0\ : STD_LOGIC;
  signal \L__0_carry__2_i_2_n_0\ : STD_LOGIC;
  signal \L__0_carry__2_i_3_n_0\ : STD_LOGIC;
  signal \L__0_carry__2_i_4_n_0\ : STD_LOGIC;
  signal \L__0_carry__2_i_5_n_0\ : STD_LOGIC;
  signal \L__0_carry__2_i_6_n_0\ : STD_LOGIC;
  signal \L__0_carry__2_i_7_n_0\ : STD_LOGIC;
  signal \L__0_carry__2_n_1\ : STD_LOGIC;
  signal \L__0_carry__2_n_2\ : STD_LOGIC;
  signal \L__0_carry__2_n_3\ : STD_LOGIC;
  signal \L__0_carry_i_1_n_0\ : STD_LOGIC;
  signal \L__0_carry_i_2_n_0\ : STD_LOGIC;
  signal \L__0_carry_i_3_n_0\ : STD_LOGIC;
  signal \L__0_carry_i_4_n_0\ : STD_LOGIC;
  signal \L__0_carry_i_5_n_0\ : STD_LOGIC;
  signal \L__0_carry_i_6_n_0\ : STD_LOGIC;
  signal \L__0_carry_i_7_n_0\ : STD_LOGIC;
  signal \L__0_carry_n_0\ : STD_LOGIC;
  signal \L__0_carry_n_1\ : STD_LOGIC;
  signal \L__0_carry_n_2\ : STD_LOGIC;
  signal \L__0_carry_n_3\ : STD_LOGIC;
  signal arp_reply_i_1_n_0 : STD_LOGIC;
  signal arp_reply_reg_n_0 : STD_LOGIC;
  signal bit_count0 : STD_LOGIC;
  signal \bit_count0_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
  signal \bit_count0_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
  signal \bit_count0_inferred__0/i__carry_n_0\ : STD_LOGIC;
  signal \bit_count0_inferred__0/i__carry_n_1\ : STD_LOGIC;
  signal \bit_count0_inferred__0/i__carry_n_2\ : STD_LOGIC;
  signal \bit_count0_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal bit_count223_in : STD_LOGIC;
  signal bit_count233_in : STD_LOGIC;
  signal \bit_count2_inferred__4/i__carry_n_0\ : STD_LOGIC;
  signal \bit_count2_inferred__4/i__carry_n_1\ : STD_LOGIC;
  signal \bit_count2_inferred__4/i__carry_n_2\ : STD_LOGIC;
  signal \bit_count2_inferred__4/i__carry_n_3\ : STD_LOGIC;
  signal \bit_count2_inferred__5/i__carry__0_n_3\ : STD_LOGIC;
  signal \bit_count2_inferred__5/i__carry_n_0\ : STD_LOGIC;
  signal \bit_count2_inferred__5/i__carry_n_1\ : STD_LOGIC;
  signal \bit_count2_inferred__5/i__carry_n_2\ : STD_LOGIC;
  signal \bit_count2_inferred__5/i__carry_n_3\ : STD_LOGIC;
  signal \bit_count[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \bit_count[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \bit_count[2]_i_1_n_0\ : STD_LOGIC;
  signal \bit_count[2]_i_2_n_0\ : STD_LOGIC;
  signal \bit_count[2]_i_3_n_0\ : STD_LOGIC;
  signal \bit_count[2]_i_4_n_0\ : STD_LOGIC;
  signal \bit_count[2]_i_5_n_0\ : STD_LOGIC;
  signal \bit_count[3]_i_2_n_0\ : STD_LOGIC;
  signal \bit_count[3]_i_3_n_0\ : STD_LOGIC;
  signal \bit_count[3]_i_5_n_0\ : STD_LOGIC;
  signal \bit_count[3]_i_6_n_0\ : STD_LOGIC;
  signal \bit_count[3]_i_7_n_0\ : STD_LOGIC;
  signal \bit_count[3]_i_8_n_0\ : STD_LOGIC;
  signal \bit_count[3]_i_9_n_0\ : STD_LOGIC;
  signal \bit_count_reg[3]_i_4_n_0\ : STD_LOGIC;
  signal \bit_count_reg_n_0_[0]\ : STD_LOGIC;
  signal \bit_count_reg_n_0_[1]\ : STD_LOGIC;
  signal \bit_count_reg_n_0_[2]\ : STD_LOGIC;
  signal \bit_count_reg_n_0_[3]\ : STD_LOGIC;
  signal byte0 : STD_LOGIC_VECTOR ( 2 to 2 );
  signal byte10 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \byte10[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte10[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte10[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte10[4]_i_1_n_0\ : STD_LOGIC;
  signal \byte10[5]_i_1_n_0\ : STD_LOGIC;
  signal byte11 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \byte11[0]_i_1_n_0\ : STD_LOGIC;
  signal byte12 : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \byte12[7]_i_1_n_0\ : STD_LOGIC;
  signal byte13 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \byte13[0]_i_1_n_0\ : STD_LOGIC;
  signal \byte13[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte13[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte13[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte13[4]_i_1_n_0\ : STD_LOGIC;
  signal byte15 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \byte15[3]_i_1_n_0\ : STD_LOGIC;
  signal byte16 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \byte16[0]_i_1_n_0\ : STD_LOGIC;
  signal byte17 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \byte17[0]_i_1_n_0\ : STD_LOGIC;
  signal \byte17[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte17[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte17[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte17[4]_i_1_n_0\ : STD_LOGIC;
  signal \byte17[5]_i_1_n_0\ : STD_LOGIC;
  signal byte18 : STD_LOGIC;
  signal \byte18[0]_i_1_n_0\ : STD_LOGIC;
  signal \byte18[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte18[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte18[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte18[4]_i_1_n_0\ : STD_LOGIC;
  signal \byte18[5]_i_1_n_0\ : STD_LOGIC;
  signal \byte18[6]_i_1_n_0\ : STD_LOGIC;
  signal \byte18[7]_i_2_n_0\ : STD_LOGIC;
  signal \byte18_reg_n_0_[0]\ : STD_LOGIC;
  signal \byte18_reg_n_0_[1]\ : STD_LOGIC;
  signal \byte18_reg_n_0_[2]\ : STD_LOGIC;
  signal \byte18_reg_n_0_[3]\ : STD_LOGIC;
  signal \byte18_reg_n_0_[4]\ : STD_LOGIC;
  signal \byte18_reg_n_0_[5]\ : STD_LOGIC;
  signal \byte18_reg_n_0_[6]\ : STD_LOGIC;
  signal \byte18_reg_n_0_[7]\ : STD_LOGIC;
  signal byte19 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \byte19[0]_i_1_n_0\ : STD_LOGIC;
  signal \byte19[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte19[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte19[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte19[4]_i_1_n_0\ : STD_LOGIC;
  signal \byte19[5]_i_1_n_0\ : STD_LOGIC;
  signal \byte19[6]_i_1_n_0\ : STD_LOGIC;
  signal \byte19[7]_i_1_n_0\ : STD_LOGIC;
  signal byte2 : STD_LOGIC_VECTOR ( 1 to 1 );
  signal byte20 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \byte20[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte20[7]_i_1_n_0\ : STD_LOGIC;
  signal byte21 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \byte21[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte21[4]_i_1_n_0\ : STD_LOGIC;
  signal \byte21[6]_i_1_n_0\ : STD_LOGIC;
  signal \byte21[7]_i_1_n_0\ : STD_LOGIC;
  signal byte22 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \byte22[0]_i_1_n_0\ : STD_LOGIC;
  signal \byte22[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte22[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte22[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte22[4]_i_1_n_0\ : STD_LOGIC;
  signal \byte22[5]_i_1_n_0\ : STD_LOGIC;
  signal \byte22[6]_i_1_n_0\ : STD_LOGIC;
  signal \byte22[7]_i_1_n_0\ : STD_LOGIC;
  signal byte23 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \byte23[0]_i_1_n_0\ : STD_LOGIC;
  signal \byte23[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte23[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte23[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte23[4]_i_1_n_0\ : STD_LOGIC;
  signal \byte23[5]_i_1_n_0\ : STD_LOGIC;
  signal \byte23[6]_i_1_n_0\ : STD_LOGIC;
  signal \byte23[7]_i_1_n_0\ : STD_LOGIC;
  signal byte24 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \byte24[0]_i_1_n_0\ : STD_LOGIC;
  signal \byte24[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte24[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte24[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte24[4]_i_1_n_0\ : STD_LOGIC;
  signal \byte24[5]_i_1_n_0\ : STD_LOGIC;
  signal \byte24[6]_i_1_n_0\ : STD_LOGIC;
  signal \byte24[7]_i_1_n_0\ : STD_LOGIC;
  signal byte25 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \byte25[0]_i_1_n_0\ : STD_LOGIC;
  signal \byte25[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte25[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte25[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte25[4]_i_1_n_0\ : STD_LOGIC;
  signal \byte25[5]_i_1_n_0\ : STD_LOGIC;
  signal \byte25[6]_i_1_n_0\ : STD_LOGIC;
  signal \byte25[7]_i_1_n_0\ : STD_LOGIC;
  signal byte26 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \byte26[0]_i_1_n_0\ : STD_LOGIC;
  signal \byte26[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte26[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte26[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte26[4]_i_1_n_0\ : STD_LOGIC;
  signal \byte26[5]_i_1_n_0\ : STD_LOGIC;
  signal \byte26[6]_i_1_n_0\ : STD_LOGIC;
  signal \byte26[7]_i_1_n_0\ : STD_LOGIC;
  signal byte27 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \byte27[0]_i_1_n_0\ : STD_LOGIC;
  signal \byte27[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte27[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte27[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte27[4]_i_1_n_0\ : STD_LOGIC;
  signal \byte27[5]_i_1_n_0\ : STD_LOGIC;
  signal \byte27[6]_i_1_n_0\ : STD_LOGIC;
  signal \byte27[7]_i_1_n_0\ : STD_LOGIC;
  signal \byte2[3]_i_1_n_0\ : STD_LOGIC;
  signal \byte2_reg_n_0_[0]\ : STD_LOGIC;
  signal \byte2_reg_n_0_[1]\ : STD_LOGIC;
  signal \byte2_reg_n_0_[2]\ : STD_LOGIC;
  signal \byte2_reg_n_0_[3]\ : STD_LOGIC;
  signal \byte2_reg_n_0_[4]\ : STD_LOGIC;
  signal \byte2_reg_n_0_[5]\ : STD_LOGIC;
  signal \byte2_reg_n_0_[6]\ : STD_LOGIC;
  signal \byte2_reg_n_0_[7]\ : STD_LOGIC;
  signal byte3 : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal byte4 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \byte4[1]_i_1_n_0\ : STD_LOGIC;
  signal \byte4[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte5[2]_i_1_n_0\ : STD_LOGIC;
  signal \byte5_reg_n_0_[0]\ : STD_LOGIC;
  signal \byte5_reg_n_0_[1]\ : STD_LOGIC;
  signal \byte5_reg_n_0_[2]\ : STD_LOGIC;
  signal \byte5_reg_n_0_[3]\ : STD_LOGIC;
  signal \byte5_reg_n_0_[4]\ : STD_LOGIC;
  signal \byte5_reg_n_0_[5]\ : STD_LOGIC;
  signal \byte5_reg_n_0_[6]\ : STD_LOGIC;
  signal \byte5_reg_n_0_[7]\ : STD_LOGIC;
  signal byte7 : STD_LOGIC_VECTOR ( 1 to 1 );
  signal byte8 : STD_LOGIC_VECTOR ( 7 to 7 );
  signal \byte8_reg_n_0_[7]\ : STD_LOGIC;
  signal byte9 : STD_LOGIC_VECTOR ( 3 to 3 );
  signal byte_count : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal byte_count0 : STD_LOGIC;
  signal \byte_count[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \byte_count[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \byte_count[0]_i_4_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_10__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_11__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_12_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_13__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_14__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_15__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_16__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_17__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_18__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_19__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_20__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_21__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_22_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_23_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_24_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_25_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_26_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_27_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_28_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_29_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_3__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_4__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_5__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_6__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_7__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_8__0_n_0\ : STD_LOGIC;
  signal \byte_count[10]_i_9__0_n_0\ : STD_LOGIC;
  signal \byte_count[2]_i_2_n_0\ : STD_LOGIC;
  signal \byte_count[3]_i_2_n_0\ : STD_LOGIC;
  signal \byte_count[3]_i_3_n_0\ : STD_LOGIC;
  signal \byte_count[4]_i_2_n_0\ : STD_LOGIC;
  signal \byte_count[4]_i_3_n_0\ : STD_LOGIC;
  signal \byte_count[4]_i_4_n_0\ : STD_LOGIC;
  signal \byte_count[4]_i_5_n_0\ : STD_LOGIC;
  signal \byte_count[5]_i_2_n_0\ : STD_LOGIC;
  signal \byte_count[5]_i_3_n_0\ : STD_LOGIC;
  signal \byte_count[6]_i_2_n_0\ : STD_LOGIC;
  signal \byte_count[6]_i_3_n_0\ : STD_LOGIC;
  signal \byte_count[7]_i_2_n_0\ : STD_LOGIC;
  signal \byte_count[7]_i_3_n_0\ : STD_LOGIC;
  signal \byte_count[8]_i_2_n_0\ : STD_LOGIC;
  signal \byte_count[8]_i_3_n_0\ : STD_LOGIC;
  signal \byte_count[9]_i_2_n_0\ : STD_LOGIC;
  signal \byte_count[9]_i_3_n_0\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[0]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[10]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[1]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[2]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[3]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[4]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[5]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[6]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[7]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[8]\ : STD_LOGIC;
  signal \byte_count_reg_n_0_[9]\ : STD_LOGIC;
  signal crc_calculator_n_0 : STD_LOGIC;
  signal crc_calculator_n_1 : STD_LOGIC;
  signal crc_calculator_n_2 : STD_LOGIC;
  signal crc_calculator_n_3 : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[10]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[2]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[3]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[4]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[5]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[6]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[7]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[8]\ : STD_LOGIC;
  signal \data_counter_max_reg_n_0_[9]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[0]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[10]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[11]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[12]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[13]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[14]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[15]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[1]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[2]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[3]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[4]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[5]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[6]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[7]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[8]\ : STD_LOGIC;
  signal \dest_ip_reg_n_0_[9]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[0]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[10]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[11]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[12]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[13]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[14]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[15]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[16]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[17]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[18]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[19]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[1]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[20]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[21]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[22]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[23]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[24]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[25]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[26]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[27]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[28]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[29]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[2]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[30]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[31]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[32]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[33]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[34]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[35]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[36]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[37]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[38]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[39]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[3]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[40]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[41]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[42]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[43]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[44]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[45]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[46]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[47]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[4]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[5]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[6]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[7]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[8]\ : STD_LOGIC;
  signal \dest_mac_reg_n_0_[9]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[0]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[10]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[11]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[12]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[13]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[14]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[15]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[1]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[2]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[3]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[4]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[5]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[6]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[7]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[8]\ : STD_LOGIC;
  signal \dest_port_reg_n_0_[9]\ : STD_LOGIC;
  signal eth_protocol_i_1_n_0 : STD_LOGIC;
  signal eth_type : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal eth_type1 : STD_LOGIC;
  signal eth_type118_out : STD_LOGIC;
  signal \^fifo_read_enable\ : STD_LOGIC;
  signal \i__carry__0_i_1__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_1__1_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_2__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_2__1_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_3__0_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_3__1_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_5_n_0\ : STD_LOGIC;
  signal \i__carry_i_10__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_10_n_0\ : STD_LOGIC;
  signal \i__carry_i_11__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_11_n_0\ : STD_LOGIC;
  signal \i__carry_i_12_n_0\ : STD_LOGIC;
  signal \i__carry_i_1__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_1__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_1__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_1_n_0\ : STD_LOGIC;
  signal \i__carry_i_2__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_2__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_2__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_2_n_0\ : STD_LOGIC;
  signal \i__carry_i_3__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_3__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_3__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_3_n_0\ : STD_LOGIC;
  signal \i__carry_i_4__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_4__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_4__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_4_n_0\ : STD_LOGIC;
  signal \i__carry_i_5__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_5__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_5__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_5_n_0\ : STD_LOGIC;
  signal \i__carry_i_6__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_6__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_6__2_n_0\ : STD_LOGIC;
  signal \i__carry_i_6_n_0\ : STD_LOGIC;
  signal \i__carry_i_7__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_7__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_7_n_0\ : STD_LOGIC;
  signal \i__carry_i_8__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_8__1_n_0\ : STD_LOGIC;
  signal \i__carry_i_8_n_0\ : STD_LOGIC;
  signal \i__carry_i_9__0_n_0\ : STD_LOGIC;
  signal \i__carry_i_9_n_0\ : STD_LOGIC;
  signal id_counter121_out : STD_LOGIC;
  signal \id_counter[0]_i_1_n_0\ : STD_LOGIC;
  signal \id_counter[15]_i_1_n_0\ : STD_LOGIC;
  signal \id_counter__0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \id_counter_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \id_counter_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \id_counter_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \id_counter_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \id_counter_reg[15]_i_2_n_2\ : STD_LOGIC;
  signal \id_counter_reg[15]_i_2_n_3\ : STD_LOGIC;
  signal \id_counter_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \id_counter_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \id_counter_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \id_counter_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \id_counter_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \id_counter_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \id_counter_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \id_counter_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal ip_header_calc_done : STD_LOGIC;
  signal ip_header_calc_done_i_1_n_0 : STD_LOGIC;
  signal ip_header_checksum : STD_LOGIC;
  signal \ip_header_checksum[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[0]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[10]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[11]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[12]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[13]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[14]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[15]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[1]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[2]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[3]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[4]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[5]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[6]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[7]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[8]\ : STD_LOGIC;
  signal \ip_header_checksum_reg_n_0_[9]\ : STD_LOGIC;
  signal \ip_total_length[4]_i_2_n_0\ : STD_LOGIC;
  signal \ip_total_length[4]_i_3_n_0\ : STD_LOGIC;
  signal \ip_total_length_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \ip_total_length_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \ip_total_length_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \ip_total_length_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \ip_total_length_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \ip_total_length_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \ip_total_length_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \ip_total_length_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \ip_total_length_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \ip_total_length_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \ip_total_length_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \ip_total_length_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \ip_total_length_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \ip_total_length_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \ip_total_length_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \ip_total_length_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \ip_total_length_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \ip_total_length_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \ip_total_length_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \ip_total_length_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \ip_total_length_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \ip_total_length_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \ip_total_length_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \ip_total_length_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \ip_total_length_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \ip_total_length_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \ip_total_length_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \ip_total_length_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \ip_total_length_reg_n_0_[2]\ : STD_LOGIC;
  signal \ip_total_length_reg_n_0_[3]\ : STD_LOGIC;
  signal \ip_total_length_reg_n_0_[4]\ : STD_LOGIC;
  signal \ip_total_length_reg_n_0_[5]\ : STD_LOGIC;
  signal \ip_total_length_reg_n_0_[6]\ : STD_LOGIC;
  signal \ip_total_length_reg_n_0_[7]\ : STD_LOGIC;
  signal is_idle : STD_LOGIC;
  signal is_idle_i_1_n_0 : STD_LOGIC;
  signal \not\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal p_0_in0_in : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal plusOp : STD_LOGIC_VECTOR ( 15 downto 1 );
  signal rd_enable_fifo0 : STD_LOGIC;
  signal rd_enable_fifo04_out : STD_LOGIC;
  signal \rd_enable_fifo0_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \rd_enable_fifo0_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \rd_enable_fifo0_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \rd_enable_fifo0_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \rd_enable_fifo0_carry__0_i_5_n_0\ : STD_LOGIC;
  signal \rd_enable_fifo0_carry__0_n_3\ : STD_LOGIC;
  signal rd_enable_fifo0_carry_i_10_n_0 : STD_LOGIC;
  signal rd_enable_fifo0_carry_i_11_n_0 : STD_LOGIC;
  signal rd_enable_fifo0_carry_i_12_n_0 : STD_LOGIC;
  signal rd_enable_fifo0_carry_i_13_n_0 : STD_LOGIC;
  signal rd_enable_fifo0_carry_i_1_n_0 : STD_LOGIC;
  signal rd_enable_fifo0_carry_i_2_n_0 : STD_LOGIC;
  signal rd_enable_fifo0_carry_i_3_n_0 : STD_LOGIC;
  signal rd_enable_fifo0_carry_i_4_n_0 : STD_LOGIC;
  signal rd_enable_fifo0_carry_i_5_n_0 : STD_LOGIC;
  signal rd_enable_fifo0_carry_i_6_n_0 : STD_LOGIC;
  signal rd_enable_fifo0_carry_i_7_n_0 : STD_LOGIC;
  signal rd_enable_fifo0_carry_i_8_n_0 : STD_LOGIC;
  signal rd_enable_fifo0_carry_i_9_n_0 : STD_LOGIC;
  signal rd_enable_fifo0_carry_n_0 : STD_LOGIC;
  signal rd_enable_fifo0_carry_n_1 : STD_LOGIC;
  signal rd_enable_fifo0_carry_n_2 : STD_LOGIC;
  signal rd_enable_fifo0_carry_n_3 : STD_LOGIC;
  signal rd_enable_fifo_i_1_n_0 : STD_LOGIC;
  signal rd_enable_fifo_i_2_n_0 : STD_LOGIC;
  signal rd_enable_fifo_i_4_n_0 : STD_LOGIC;
  signal rd_enable_fifo_i_5_n_0 : STD_LOGIC;
  signal sent_arp_response_i_1_n_0 : STD_LOGIC;
  signal start_crc : STD_LOGIC;
  signal \start_crc_i_1__0_n_0\ : STD_LOGIC;
  signal \start_crc_i_2__0_n_0\ : STD_LOGIC;
  signal \start_crc_i_3__0_n_0\ : STD_LOGIC;
  signal \start_crc_i_4__0_n_0\ : STD_LOGIC;
  signal \start_crc_i_5__0_n_0\ : STD_LOGIC;
  signal \start_crc_i_6__0_n_0\ : STD_LOGIC;
  signal start_crc_i_7_n_0 : STD_LOGIC;
  signal \state[0]_i_1_n_0\ : STD_LOGIC;
  signal \state[0]_i_2_n_0\ : STD_LOGIC;
  signal \state[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \state[0]_i_4_n_0\ : STD_LOGIC;
  signal \state[0]_i_5__0_n_0\ : STD_LOGIC;
  signal \state[0]_i_6__0_n_0\ : STD_LOGIC;
  signal \state[0]_i_7__0_n_0\ : STD_LOGIC;
  signal \state[0]_i_8__0_n_0\ : STD_LOGIC;
  signal \state[0]_i_9__0_n_0\ : STD_LOGIC;
  signal \state[1]_i_1_n_0\ : STD_LOGIC;
  signal \state[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \state[1]_i_3__1_n_0\ : STD_LOGIC;
  signal \state[1]_i_4__0_n_0\ : STD_LOGIC;
  signal \state[1]_i_5__1_n_0\ : STD_LOGIC;
  signal \state[2]_i_10__0_n_0\ : STD_LOGIC;
  signal \state[2]_i_11_n_0\ : STD_LOGIC;
  signal \state[2]_i_1_n_0\ : STD_LOGIC;
  signal \state[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \state[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \state[2]_i_5_n_0\ : STD_LOGIC;
  signal \state[2]_i_6__0_n_0\ : STD_LOGIC;
  signal \state[2]_i_7__0_n_0\ : STD_LOGIC;
  signal \state[2]_i_8__0_n_0\ : STD_LOGIC;
  signal \state[2]_i_9_n_0\ : STD_LOGIC;
  signal state_0 : STD_LOGIC;
  signal \state_reg_n_0_[0]\ : STD_LOGIC;
  signal \state_reg_n_0_[1]\ : STD_LOGIC;
  signal \state_reg_n_0_[2]\ : STD_LOGIC;
  signal stop_crc : STD_LOGIC;
  signal \stop_crc_i_1__0_n_0\ : STD_LOGIC;
  signal temp_iphc1 : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_i_5_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_i_6_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_i_7_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_i_8_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_n_1\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_n_2\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_n_3\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_n_4\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_n_5\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_n_6\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__0_n_7\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_i_4_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_i_5_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_i_6_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_i_7_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_i_8_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_n_1\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_n_2\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_n_3\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_n_4\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_n_5\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_n_6\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__1_n_7\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_i_2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_i_3_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_i_4_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_i_5_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_i_6_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_i_7_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_i_8_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_n_1\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_n_2\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_n_3\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_n_4\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_n_5\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_n_6\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__2_n_7\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__3_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__3_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__3_n_1\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__3_n_2\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__3_n_3\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__3_n_4\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__3_n_5\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__3_n_6\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__3_n_7\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__4_n_1\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__4_n_2\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__4_n_3\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__4_n_4\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__4_n_5\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__4_n_6\ : STD_LOGIC;
  signal \temp_iphc10__0_carry__4_n_7\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_i_2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_i_3_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_i_4_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_i_5_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_i_6_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_i_7_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_n_0\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_n_1\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_n_2\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_n_3\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_n_4\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_n_5\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_n_6\ : STD_LOGIC;
  signal \temp_iphc10__0_carry_n_7\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_i_10_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_i_11_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_i_5_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_i_6_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_i_7_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_i_8_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_i_9_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_n_1\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_n_2\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_n_3\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_n_4\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_n_5\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_n_6\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__0_n_7\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_i_4_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_i_5_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_i_6_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_i_7_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_i_8_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_i_9_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_n_1\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_n_2\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_n_3\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_n_4\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_n_5\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_n_6\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__1_n_7\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_i_10_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_i_2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_i_3_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_i_4_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_i_5_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_i_6_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_i_7_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_i_8_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_i_9_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_n_1\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_n_2\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_n_3\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_n_4\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_n_5\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_n_6\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__2_n_7\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__3_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__3_i_2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__3_i_3_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__3_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__3_n_1\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__3_n_2\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__3_n_3\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__3_n_4\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__3_n_5\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__3_n_6\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__3_n_7\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__4_n_2\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__4_n_3\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__4_n_5\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__4_n_6\ : STD_LOGIC;
  signal \temp_iphc10__110_carry__4_n_7\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_i_2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_i_3_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_i_4_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_i_5_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_i_6_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_i_7_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_i_8_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_n_0\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_n_1\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_n_2\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_n_3\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_n_4\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_n_5\ : STD_LOGIC;
  signal \temp_iphc10__110_carry_n_6\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__0_i_5_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__0_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__0_n_1\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__0_n_2\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__0_n_3\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__0_n_4\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__0_n_5\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__0_n_6\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__0_n_7\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__1_n_1\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__1_n_2\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__1_n_3\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__1_n_4\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__1_n_5\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__1_n_6\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__1_n_7\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__2_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__2_i_2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__2_n_1\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__2_n_2\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__2_n_3\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__2_n_4\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__2_n_5\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__2_n_6\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__2_n_7\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__3_n_2\ : STD_LOGIC;
  signal \temp_iphc10__64_carry__3_n_7\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_i_2_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_i_3_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_i_4_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_i_5_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_i_6_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_i_7_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_n_0\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_n_1\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_n_2\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_n_3\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_n_4\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_n_5\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_n_6\ : STD_LOGIC;
  signal \temp_iphc10__64_carry_n_7\ : STD_LOGIC;
  signal \temp_iphc1[0]_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc1[1]_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc1[23]_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc1[23]_i_2_n_0\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[0]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[10]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[11]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[12]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[13]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[14]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[15]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[16]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[17]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[18]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[19]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[1]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[20]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[21]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[22]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[23]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[2]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[3]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[4]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[5]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[6]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[7]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[8]\ : STD_LOGIC;
  signal \temp_iphc1_reg_n_0_[9]\ : STD_LOGIC;
  signal temp_iphc2 : STD_LOGIC;
  signal \temp_iphc2[15]_i_1_n_0\ : STD_LOGIC;
  signal \temp_iphc2__0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal tx_done : STD_LOGIC;
  signal tx_done_i_1_n_0 : STD_LOGIC;
  signal tx_ready : STD_LOGIC;
  signal txd0 : STD_LOGIC;
  signal txd1 : STD_LOGIC_VECTOR ( 5 downto 2 );
  signal \txd1_inferred__4/i__carry_n_1\ : STD_LOGIC;
  signal \txd1_inferred__4/i__carry_n_2\ : STD_LOGIC;
  signal \txd1_inferred__4/i__carry_n_3\ : STD_LOGIC;
  signal \txd[0]_i_11_n_0\ : STD_LOGIC;
  signal \txd[0]_i_12_n_0\ : STD_LOGIC;
  signal \txd[0]_i_13_n_0\ : STD_LOGIC;
  signal \txd[0]_i_14_n_0\ : STD_LOGIC;
  signal \txd[0]_i_15_n_0\ : STD_LOGIC;
  signal \txd[0]_i_16_n_0\ : STD_LOGIC;
  signal \txd[0]_i_17_n_0\ : STD_LOGIC;
  signal \txd[0]_i_20_n_0\ : STD_LOGIC;
  signal \txd[0]_i_21_n_0\ : STD_LOGIC;
  signal \txd[0]_i_22_n_0\ : STD_LOGIC;
  signal \txd[0]_i_23_n_0\ : STD_LOGIC;
  signal \txd[0]_i_24_n_0\ : STD_LOGIC;
  signal \txd[0]_i_25_n_0\ : STD_LOGIC;
  signal \txd[0]_i_26_n_0\ : STD_LOGIC;
  signal \txd[0]_i_27_n_0\ : STD_LOGIC;
  signal \txd[0]_i_28_n_0\ : STD_LOGIC;
  signal \txd[0]_i_29_n_0\ : STD_LOGIC;
  signal \txd[0]_i_30_n_0\ : STD_LOGIC;
  signal \txd[0]_i_31_n_0\ : STD_LOGIC;
  signal \txd[0]_i_32_n_0\ : STD_LOGIC;
  signal \txd[0]_i_33_n_0\ : STD_LOGIC;
  signal \txd[0]_i_34_n_0\ : STD_LOGIC;
  signal \txd[0]_i_35_n_0\ : STD_LOGIC;
  signal \txd[0]_i_38_n_0\ : STD_LOGIC;
  signal \txd[0]_i_39_n_0\ : STD_LOGIC;
  signal \txd[0]_i_3_n_0\ : STD_LOGIC;
  signal \txd[0]_i_40_n_0\ : STD_LOGIC;
  signal \txd[0]_i_41_n_0\ : STD_LOGIC;
  signal \txd[0]_i_42_n_0\ : STD_LOGIC;
  signal \txd[0]_i_43_n_0\ : STD_LOGIC;
  signal \txd[0]_i_44_n_0\ : STD_LOGIC;
  signal \txd[0]_i_45_n_0\ : STD_LOGIC;
  signal \txd[0]_i_49_n_0\ : STD_LOGIC;
  signal \txd[0]_i_4_n_0\ : STD_LOGIC;
  signal \txd[0]_i_50_n_0\ : STD_LOGIC;
  signal \txd[0]_i_51_n_0\ : STD_LOGIC;
  signal \txd[0]_i_52_n_0\ : STD_LOGIC;
  signal \txd[0]_i_53_n_0\ : STD_LOGIC;
  signal \txd[0]_i_56_n_0\ : STD_LOGIC;
  signal \txd[0]_i_57_n_0\ : STD_LOGIC;
  signal \txd[0]_i_58_n_0\ : STD_LOGIC;
  signal \txd[0]_i_59_n_0\ : STD_LOGIC;
  signal \txd[0]_i_5_n_0\ : STD_LOGIC;
  signal \txd[0]_i_60_n_0\ : STD_LOGIC;
  signal \txd[0]_i_61_n_0\ : STD_LOGIC;
  signal \txd[0]_i_62_n_0\ : STD_LOGIC;
  signal \txd[0]_i_63_n_0\ : STD_LOGIC;
  signal \txd[0]_i_64_n_0\ : STD_LOGIC;
  signal \txd[0]_i_65_n_0\ : STD_LOGIC;
  signal \txd[0]_i_66_n_0\ : STD_LOGIC;
  signal \txd[0]_i_67_n_0\ : STD_LOGIC;
  signal \txd[0]_i_68_n_0\ : STD_LOGIC;
  signal \txd[0]_i_69_n_0\ : STD_LOGIC;
  signal \txd[0]_i_6_n_0\ : STD_LOGIC;
  signal \txd[0]_i_70_n_0\ : STD_LOGIC;
  signal \txd[0]_i_71_n_0\ : STD_LOGIC;
  signal \txd[0]_i_80_n_0\ : STD_LOGIC;
  signal \txd[0]_i_81_n_0\ : STD_LOGIC;
  signal \txd[0]_i_82_n_0\ : STD_LOGIC;
  signal \txd[0]_i_83_n_0\ : STD_LOGIC;
  signal \txd[0]_i_84_n_0\ : STD_LOGIC;
  signal \txd[0]_i_85_n_0\ : STD_LOGIC;
  signal \txd[0]_i_86_n_0\ : STD_LOGIC;
  signal \txd[0]_i_87_n_0\ : STD_LOGIC;
  signal \txd[0]_i_88_n_0\ : STD_LOGIC;
  signal \txd[0]_i_89_n_0\ : STD_LOGIC;
  signal \txd[0]_i_8_n_0\ : STD_LOGIC;
  signal \txd[0]_i_90_n_0\ : STD_LOGIC;
  signal \txd[0]_i_91_n_0\ : STD_LOGIC;
  signal \txd[1]_i_100_n_0\ : STD_LOGIC;
  signal \txd[1]_i_10_n_0\ : STD_LOGIC;
  signal \txd[1]_i_11_n_0\ : STD_LOGIC;
  signal \txd[1]_i_12_n_0\ : STD_LOGIC;
  signal \txd[1]_i_13_n_0\ : STD_LOGIC;
  signal \txd[1]_i_15_n_0\ : STD_LOGIC;
  signal \txd[1]_i_18_n_0\ : STD_LOGIC;
  signal \txd[1]_i_19_n_0\ : STD_LOGIC;
  signal \txd[1]_i_1_n_0\ : STD_LOGIC;
  signal \txd[1]_i_20_n_0\ : STD_LOGIC;
  signal \txd[1]_i_21_n_0\ : STD_LOGIC;
  signal \txd[1]_i_24_n_0\ : STD_LOGIC;
  signal \txd[1]_i_25_n_0\ : STD_LOGIC;
  signal \txd[1]_i_27_n_0\ : STD_LOGIC;
  signal \txd[1]_i_28_n_0\ : STD_LOGIC;
  signal \txd[1]_i_29_n_0\ : STD_LOGIC;
  signal \txd[1]_i_30_n_0\ : STD_LOGIC;
  signal \txd[1]_i_31_n_0\ : STD_LOGIC;
  signal \txd[1]_i_32_n_0\ : STD_LOGIC;
  signal \txd[1]_i_39_n_0\ : STD_LOGIC;
  signal \txd[1]_i_3_n_0\ : STD_LOGIC;
  signal \txd[1]_i_44_n_0\ : STD_LOGIC;
  signal \txd[1]_i_45_n_0\ : STD_LOGIC;
  signal \txd[1]_i_46_n_0\ : STD_LOGIC;
  signal \txd[1]_i_47_n_0\ : STD_LOGIC;
  signal \txd[1]_i_48_n_0\ : STD_LOGIC;
  signal \txd[1]_i_49_n_0\ : STD_LOGIC;
  signal \txd[1]_i_4_n_0\ : STD_LOGIC;
  signal \txd[1]_i_50_n_0\ : STD_LOGIC;
  signal \txd[1]_i_51_n_0\ : STD_LOGIC;
  signal \txd[1]_i_52_n_0\ : STD_LOGIC;
  signal \txd[1]_i_53_n_0\ : STD_LOGIC;
  signal \txd[1]_i_54_n_0\ : STD_LOGIC;
  signal \txd[1]_i_55_n_0\ : STD_LOGIC;
  signal \txd[1]_i_56_n_0\ : STD_LOGIC;
  signal \txd[1]_i_57_n_0\ : STD_LOGIC;
  signal \txd[1]_i_58_n_0\ : STD_LOGIC;
  signal \txd[1]_i_59_n_0\ : STD_LOGIC;
  signal \txd[1]_i_5_n_0\ : STD_LOGIC;
  signal \txd[1]_i_60_n_0\ : STD_LOGIC;
  signal \txd[1]_i_61_n_0\ : STD_LOGIC;
  signal \txd[1]_i_62_n_0\ : STD_LOGIC;
  signal \txd[1]_i_63_n_0\ : STD_LOGIC;
  signal \txd[1]_i_64_n_0\ : STD_LOGIC;
  signal \txd[1]_i_65_n_0\ : STD_LOGIC;
  signal \txd[1]_i_68_n_0\ : STD_LOGIC;
  signal \txd[1]_i_69_n_0\ : STD_LOGIC;
  signal \txd[1]_i_70_n_0\ : STD_LOGIC;
  signal \txd[1]_i_71_n_0\ : STD_LOGIC;
  signal \txd[1]_i_73_n_0\ : STD_LOGIC;
  signal \txd[1]_i_74_n_0\ : STD_LOGIC;
  signal \txd[1]_i_75_n_0\ : STD_LOGIC;
  signal \txd[1]_i_76_n_0\ : STD_LOGIC;
  signal \txd[1]_i_77_n_0\ : STD_LOGIC;
  signal \txd[1]_i_78_n_0\ : STD_LOGIC;
  signal \txd[1]_i_79_n_0\ : STD_LOGIC;
  signal \txd[1]_i_7_n_0\ : STD_LOGIC;
  signal \txd[1]_i_80_n_0\ : STD_LOGIC;
  signal \txd[1]_i_81_n_0\ : STD_LOGIC;
  signal \txd[1]_i_82_n_0\ : STD_LOGIC;
  signal \txd[1]_i_83_n_0\ : STD_LOGIC;
  signal \txd[1]_i_84_n_0\ : STD_LOGIC;
  signal \txd[1]_i_85_n_0\ : STD_LOGIC;
  signal \txd[1]_i_86_n_0\ : STD_LOGIC;
  signal \txd[1]_i_87_n_0\ : STD_LOGIC;
  signal \txd[1]_i_88_n_0\ : STD_LOGIC;
  signal \txd[1]_i_89_n_0\ : STD_LOGIC;
  signal \txd[1]_i_8_n_0\ : STD_LOGIC;
  signal \txd[1]_i_90_n_0\ : STD_LOGIC;
  signal \txd[1]_i_91_n_0\ : STD_LOGIC;
  signal \txd[1]_i_92_n_0\ : STD_LOGIC;
  signal \txd[1]_i_93_n_0\ : STD_LOGIC;
  signal \txd[1]_i_98_n_0\ : STD_LOGIC;
  signal \txd[1]_i_99_n_0\ : STD_LOGIC;
  signal \txd[1]_i_9_n_0\ : STD_LOGIC;
  signal \txd_reg[0]_i_10_n_0\ : STD_LOGIC;
  signal \txd_reg[0]_i_37_n_0\ : STD_LOGIC;
  signal \txd_reg[0]_i_9_n_1\ : STD_LOGIC;
  signal \txd_reg[0]_i_9_n_2\ : STD_LOGIC;
  signal \txd_reg[0]_i_9_n_3\ : STD_LOGIC;
  signal \txd_reg[0]_i_9_n_4\ : STD_LOGIC;
  signal \txd_reg[0]_i_9_n_5\ : STD_LOGIC;
  signal \txd_reg[0]_i_9_n_6\ : STD_LOGIC;
  signal \txd_reg[0]_i_9_n_7\ : STD_LOGIC;
  signal \txd_reg[1]_i_22_n_0\ : STD_LOGIC;
  signal \txd_reg[1]_i_23_n_0\ : STD_LOGIC;
  signal \txd_reg[1]_i_26_n_0\ : STD_LOGIC;
  signal \txd_reg[1]_i_38_n_1\ : STD_LOGIC;
  signal \txd_reg[1]_i_38_n_2\ : STD_LOGIC;
  signal \txd_reg[1]_i_38_n_3\ : STD_LOGIC;
  signal \txd_reg[1]_i_38_n_4\ : STD_LOGIC;
  signal \txd_reg[1]_i_38_n_5\ : STD_LOGIC;
  signal \txd_reg[1]_i_38_n_6\ : STD_LOGIC;
  signal \txd_reg[1]_i_40_n_0\ : STD_LOGIC;
  signal \txd_reg[1]_i_41_n_0\ : STD_LOGIC;
  signal \txd_reg[1]_i_42_n_0\ : STD_LOGIC;
  signal \txd_reg[1]_i_43_n_0\ : STD_LOGIC;
  signal \txd_reg[1]_i_72_n_2\ : STD_LOGIC;
  signal \txd_reg[1]_i_72_n_3\ : STD_LOGIC;
  signal \txd_reg[1]_i_72_n_5\ : STD_LOGIC;
  signal \txd_reg[1]_i_72_n_6\ : STD_LOGIC;
  signal txen_i_1_n_0 : STD_LOGIC;
  signal txen_i_2_n_0 : STD_LOGIC;
  signal txen_i_3_n_0 : STD_LOGIC;
  signal txen_i_4_n_0 : STD_LOGIC;
  signal udp_checksum : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[0]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[10]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[11]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[12]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[13]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[14]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[15]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[1]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[2]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[3]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[4]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[5]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[6]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[7]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[8]\ : STD_LOGIC;
  signal \udp_checksum_reg_n_0_[9]\ : STD_LOGIC;
  signal \udp_length_reg_n_0_[10]\ : STD_LOGIC;
  signal \udp_length_reg_n_0_[11]\ : STD_LOGIC;
  signal \udp_length_reg_n_0_[12]\ : STD_LOGIC;
  signal \udp_length_reg_n_0_[13]\ : STD_LOGIC;
  signal \udp_length_reg_n_0_[14]\ : STD_LOGIC;
  signal \udp_length_reg_n_0_[15]\ : STD_LOGIC;
  signal \udp_length_reg_n_0_[2]\ : STD_LOGIC;
  signal \udp_length_reg_n_0_[3]\ : STD_LOGIC;
  signal \udp_length_reg_n_0_[4]\ : STD_LOGIC;
  signal \udp_length_reg_n_0_[5]\ : STD_LOGIC;
  signal \udp_length_reg_n_0_[6]\ : STD_LOGIC;
  signal \udp_length_reg_n_0_[7]\ : STD_LOGIC;
  signal \udp_length_reg_n_0_[8]\ : STD_LOGIC;
  signal \udp_length_reg_n_0_[9]\ : STD_LOGIC;
  signal \^udp_send_data_valid17_out\ : STD_LOGIC;
  signal zero_counter : STD_LOGIC_VECTOR ( 4 to 4 );
  signal \zero_counter[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \zero_counter[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \zero_counter[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \zero_counter[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \zero_counter[4]_i_3_n_0\ : STD_LOGIC;
  signal \zero_counter[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \zero_counter_reg_n_0_[1]\ : STD_LOGIC;
  signal \zero_counter_reg_n_0_[2]\ : STD_LOGIC;
  signal \zero_counter_reg_n_0_[3]\ : STD_LOGIC;
  signal \zero_counter_reg_n_0_[4]\ : STD_LOGIC;
  signal \NLW_L__0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_bit_count0_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_bit_count0_inferred__0/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_bit_count0_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_bit_count2_inferred__4/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_bit_count2_inferred__4/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_bit_count2_inferred__4/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_bit_count2_inferred__5/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_bit_count2_inferred__5/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_bit_count2_inferred__5/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_id_counter_reg[15]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_id_counter_reg[15]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_ip_total_length_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ip_total_length_reg[15]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_ip_total_length_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_rd_enable_fifo0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_rd_enable_fifo0_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_rd_enable_fifo0_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_temp_iphc10__0_carry__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_temp_iphc10__110_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_temp_iphc10__110_carry__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_temp_iphc10__110_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_temp_iphc10__64_carry__3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_temp_iphc10__64_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_txd1_inferred__4/i__carry_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_txd_reg[0]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_txd_reg[1]_i_38_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_txd_reg[1]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_txd_reg[1]_i_72_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_txd_reg[1]_i_72_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_s[0]_i_1\ : label is "soft_lutpair238";
  attribute SOFT_HLUTNM of \FSM_onehot_s[1]_i_1\ : label is "soft_lutpair238";
  attribute SOFT_HLUTNM of \FSM_onehot_s[2]_i_1\ : label is "soft_lutpair235";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_s_reg[0]\ : label is "s1:001,s2:010,s3:100,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_s_reg[1]\ : label is "s1:001,s2:010,s3:100,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_s_reg[2]\ : label is "s1:001,s2:010,s3:100,";
  attribute HLUTNM : string;
  attribute HLUTNM of \L__0_carry__0_i_1\ : label is "lutpair87";
  attribute HLUTNM of \L__0_carry__0_i_2\ : label is "lutpair86";
  attribute HLUTNM of \L__0_carry__0_i_3\ : label is "lutpair85";
  attribute HLUTNM of \L__0_carry__0_i_4\ : label is "lutpair84";
  attribute HLUTNM of \L__0_carry__0_i_6\ : label is "lutpair87";
  attribute HLUTNM of \L__0_carry__0_i_7\ : label is "lutpair86";
  attribute HLUTNM of \L__0_carry__0_i_8\ : label is "lutpair85";
  attribute HLUTNM of \L__0_carry_i_1\ : label is "lutpair83";
  attribute HLUTNM of \L__0_carry_i_2\ : label is "lutpair82";
  attribute HLUTNM of \L__0_carry_i_3\ : label is "lutpair81";
  attribute HLUTNM of \L__0_carry_i_4\ : label is "lutpair84";
  attribute HLUTNM of \L__0_carry_i_5\ : label is "lutpair83";
  attribute HLUTNM of \L__0_carry_i_6\ : label is "lutpair82";
  attribute HLUTNM of \L__0_carry_i_7\ : label is "lutpair81";
  attribute SOFT_HLUTNM of arp_reply_i_1 : label is "soft_lutpair267";
  attribute SOFT_HLUTNM of \bit_count[1]_i_1__0\ : label is "soft_lutpair261";
  attribute SOFT_HLUTNM of \bit_count[2]_i_4\ : label is "soft_lutpair271";
  attribute SOFT_HLUTNM of \bit_count[3]_i_5\ : label is "soft_lutpair265";
  attribute SOFT_HLUTNM of \bit_count[3]_i_7\ : label is "soft_lutpair230";
  attribute SOFT_HLUTNM of \byte10[1]_i_1\ : label is "soft_lutpair272";
  attribute SOFT_HLUTNM of \byte10[2]_i_1\ : label is "soft_lutpair273";
  attribute SOFT_HLUTNM of \byte10[3]_i_1\ : label is "soft_lutpair274";
  attribute SOFT_HLUTNM of \byte10[4]_i_1\ : label is "soft_lutpair273";
  attribute SOFT_HLUTNM of \byte10[5]_i_1\ : label is "soft_lutpair272";
  attribute SOFT_HLUTNM of \byte11[0]_i_1\ : label is "soft_lutpair274";
  attribute SOFT_HLUTNM of \byte12[7]_i_1\ : label is "soft_lutpair229";
  attribute SOFT_HLUTNM of \byte13[0]_i_1\ : label is "soft_lutpair247";
  attribute SOFT_HLUTNM of \byte13[1]_i_1\ : label is "soft_lutpair249";
  attribute SOFT_HLUTNM of \byte13[3]_i_1\ : label is "soft_lutpair253";
  attribute SOFT_HLUTNM of \byte13[4]_i_1\ : label is "soft_lutpair267";
  attribute SOFT_HLUTNM of \byte15[3]_i_1\ : label is "soft_lutpair275";
  attribute SOFT_HLUTNM of \byte16[0]_i_1\ : label is "soft_lutpair275";
  attribute SOFT_HLUTNM of \byte17[0]_i_1\ : label is "soft_lutpair247";
  attribute SOFT_HLUTNM of \byte17[1]_i_1\ : label is "soft_lutpair249";
  attribute SOFT_HLUTNM of \byte17[2]_i_1\ : label is "soft_lutpair229";
  attribute SOFT_HLUTNM of \byte17[3]_i_1\ : label is "soft_lutpair253";
  attribute SOFT_HLUTNM of \byte17[4]_i_1\ : label is "soft_lutpair228";
  attribute SOFT_HLUTNM of \byte17[5]_i_1\ : label is "soft_lutpair276";
  attribute SOFT_HLUTNM of \byte18[0]_i_1\ : label is "soft_lutpair287";
  attribute SOFT_HLUTNM of \byte18[1]_i_1\ : label is "soft_lutpair286";
  attribute SOFT_HLUTNM of \byte18[2]_i_1\ : label is "soft_lutpair285";
  attribute SOFT_HLUTNM of \byte18[3]_i_1\ : label is "soft_lutpair282";
  attribute SOFT_HLUTNM of \byte18[4]_i_1\ : label is "soft_lutpair281";
  attribute SOFT_HLUTNM of \byte18[5]_i_1\ : label is "soft_lutpair278";
  attribute SOFT_HLUTNM of \byte18[6]_i_1\ : label is "soft_lutpair279";
  attribute SOFT_HLUTNM of \byte18[7]_i_2\ : label is "soft_lutpair277";
  attribute SOFT_HLUTNM of \byte19[0]_i_1\ : label is "soft_lutpair295";
  attribute SOFT_HLUTNM of \byte19[1]_i_1\ : label is "soft_lutpair294";
  attribute SOFT_HLUTNM of \byte19[2]_i_1\ : label is "soft_lutpair293";
  attribute SOFT_HLUTNM of \byte19[3]_i_1\ : label is "soft_lutpair292";
  attribute SOFT_HLUTNM of \byte19[4]_i_1\ : label is "soft_lutpair291";
  attribute SOFT_HLUTNM of \byte19[5]_i_1\ : label is "soft_lutpair290";
  attribute SOFT_HLUTNM of \byte19[6]_i_1\ : label is "soft_lutpair289";
  attribute SOFT_HLUTNM of \byte19[7]_i_1\ : label is "soft_lutpair288";
  attribute SOFT_HLUTNM of \byte20[2]_i_1\ : label is "soft_lutpair255";
  attribute SOFT_HLUTNM of \byte21[1]_i_1\ : label is "soft_lutpair257";
  attribute SOFT_HLUTNM of \byte21[4]_i_1\ : label is "soft_lutpair256";
  attribute SOFT_HLUTNM of \byte21[6]_i_1\ : label is "soft_lutpair255";
  attribute SOFT_HLUTNM of \byte21[7]_i_1\ : label is "soft_lutpair256";
  attribute SOFT_HLUTNM of \byte22[0]_i_1\ : label is "soft_lutpair299";
  attribute SOFT_HLUTNM of \byte22[1]_i_1\ : label is "soft_lutpair299";
  attribute SOFT_HLUTNM of \byte22[2]_i_1\ : label is "soft_lutpair298";
  attribute SOFT_HLUTNM of \byte22[3]_i_1\ : label is "soft_lutpair298";
  attribute SOFT_HLUTNM of \byte22[4]_i_1\ : label is "soft_lutpair297";
  attribute SOFT_HLUTNM of \byte22[5]_i_1\ : label is "soft_lutpair297";
  attribute SOFT_HLUTNM of \byte22[6]_i_1\ : label is "soft_lutpair296";
  attribute SOFT_HLUTNM of \byte22[7]_i_1\ : label is "soft_lutpair296";
  attribute SOFT_HLUTNM of \byte23[0]_i_1\ : label is "soft_lutpair303";
  attribute SOFT_HLUTNM of \byte23[1]_i_1\ : label is "soft_lutpair303";
  attribute SOFT_HLUTNM of \byte23[2]_i_1\ : label is "soft_lutpair302";
  attribute SOFT_HLUTNM of \byte23[3]_i_1\ : label is "soft_lutpair302";
  attribute SOFT_HLUTNM of \byte23[4]_i_1\ : label is "soft_lutpair301";
  attribute SOFT_HLUTNM of \byte23[5]_i_1\ : label is "soft_lutpair301";
  attribute SOFT_HLUTNM of \byte23[6]_i_1\ : label is "soft_lutpair300";
  attribute SOFT_HLUTNM of \byte23[7]_i_1\ : label is "soft_lutpair300";
  attribute SOFT_HLUTNM of \byte24[0]_i_1\ : label is "soft_lutpair277";
  attribute SOFT_HLUTNM of \byte24[1]_i_1\ : label is "soft_lutpair307";
  attribute SOFT_HLUTNM of \byte24[2]_i_1\ : label is "soft_lutpair306";
  attribute SOFT_HLUTNM of \byte24[3]_i_1\ : label is "soft_lutpair306";
  attribute SOFT_HLUTNM of \byte24[4]_i_1\ : label is "soft_lutpair305";
  attribute SOFT_HLUTNM of \byte24[5]_i_1\ : label is "soft_lutpair305";
  attribute SOFT_HLUTNM of \byte24[6]_i_1\ : label is "soft_lutpair304";
  attribute SOFT_HLUTNM of \byte24[7]_i_1\ : label is "soft_lutpair304";
  attribute SOFT_HLUTNM of \byte25[0]_i_1\ : label is "soft_lutpair312";
  attribute SOFT_HLUTNM of \byte25[1]_i_1\ : label is "soft_lutpair311";
  attribute SOFT_HLUTNM of \byte25[2]_i_1\ : label is "soft_lutpair308";
  attribute SOFT_HLUTNM of \byte25[3]_i_1\ : label is "soft_lutpair308";
  attribute SOFT_HLUTNM of \byte25[4]_i_1\ : label is "soft_lutpair285";
  attribute SOFT_HLUTNM of \byte25[5]_i_1\ : label is "soft_lutpair282";
  attribute SOFT_HLUTNM of \byte25[6]_i_1\ : label is "soft_lutpair281";
  attribute SOFT_HLUTNM of \byte25[7]_i_1\ : label is "soft_lutpair307";
  attribute SOFT_HLUTNM of \byte26[0]_i_1\ : label is "soft_lutpair287";
  attribute SOFT_HLUTNM of \byte26[1]_i_1\ : label is "soft_lutpair286";
  attribute SOFT_HLUTNM of \byte26[2]_i_1\ : label is "soft_lutpair313";
  attribute SOFT_HLUTNM of \byte26[3]_i_1\ : label is "soft_lutpair313";
  attribute SOFT_HLUTNM of \byte26[4]_i_1\ : label is "soft_lutpair312";
  attribute SOFT_HLUTNM of \byte26[5]_i_1\ : label is "soft_lutpair278";
  attribute SOFT_HLUTNM of \byte26[6]_i_1\ : label is "soft_lutpair279";
  attribute SOFT_HLUTNM of \byte26[7]_i_1\ : label is "soft_lutpair311";
  attribute SOFT_HLUTNM of \byte27[0]_i_1\ : label is "soft_lutpair295";
  attribute SOFT_HLUTNM of \byte27[1]_i_1\ : label is "soft_lutpair294";
  attribute SOFT_HLUTNM of \byte27[2]_i_1\ : label is "soft_lutpair293";
  attribute SOFT_HLUTNM of \byte27[3]_i_1\ : label is "soft_lutpair292";
  attribute SOFT_HLUTNM of \byte27[4]_i_1\ : label is "soft_lutpair291";
  attribute SOFT_HLUTNM of \byte27[5]_i_1\ : label is "soft_lutpair290";
  attribute SOFT_HLUTNM of \byte27[6]_i_1\ : label is "soft_lutpair289";
  attribute SOFT_HLUTNM of \byte27[7]_i_1\ : label is "soft_lutpair288";
  attribute SOFT_HLUTNM of \byte4[1]_i_1\ : label is "soft_lutpair309";
  attribute SOFT_HLUTNM of \byte4[2]_i_1\ : label is "soft_lutpair309";
  attribute SOFT_HLUTNM of \byte5[2]_i_1\ : label is "soft_lutpair276";
  attribute SOFT_HLUTNM of \byte8[7]_i_1\ : label is "soft_lutpair228";
  attribute SOFT_HLUTNM of \byte_count[0]_i_3__0\ : label is "soft_lutpair232";
  attribute SOFT_HLUTNM of \byte_count[10]_i_11__0\ : label is "soft_lutpair265";
  attribute SOFT_HLUTNM of \byte_count[10]_i_12\ : label is "soft_lutpair258";
  attribute SOFT_HLUTNM of \byte_count[10]_i_13__0\ : label is "soft_lutpair266";
  attribute SOFT_HLUTNM of \byte_count[10]_i_14__0\ : label is "soft_lutpair254";
  attribute SOFT_HLUTNM of \byte_count[10]_i_16__0\ : label is "soft_lutpair246";
  attribute SOFT_HLUTNM of \byte_count[10]_i_17__0\ : label is "soft_lutpair242";
  attribute SOFT_HLUTNM of \byte_count[10]_i_18__0\ : label is "soft_lutpair233";
  attribute SOFT_HLUTNM of \byte_count[10]_i_19__0\ : label is "soft_lutpair317";
  attribute SOFT_HLUTNM of \byte_count[10]_i_29\ : label is "soft_lutpair264";
  attribute SOFT_HLUTNM of \byte_count[10]_i_6__0\ : label is "soft_lutpair316";
  attribute SOFT_HLUTNM of \byte_count[10]_i_9__0\ : label is "soft_lutpair234";
  attribute SOFT_HLUTNM of \byte_count[3]_i_3\ : label is "soft_lutpair245";
  attribute SOFT_HLUTNM of \byte_count[4]_i_2\ : label is "soft_lutpair263";
  attribute SOFT_HLUTNM of \byte_count[4]_i_4\ : label is "soft_lutpair239";
  attribute SOFT_HLUTNM of \byte_count[4]_i_5\ : label is "soft_lutpair263";
  attribute SOFT_HLUTNM of \byte_count[5]_i_2\ : label is "soft_lutpair270";
  attribute SOFT_HLUTNM of \byte_count[6]_i_2\ : label is "soft_lutpair250";
  attribute SOFT_HLUTNM of eth_protocol_i_1 : label is "soft_lutpair248";
  attribute SOFT_HLUTNM of \i__carry__0_i_3\ : label is "soft_lutpair237";
  attribute SOFT_HLUTNM of \i__carry_i_10\ : label is "soft_lutpair237";
  attribute SOFT_HLUTNM of \i__carry_i_10__0\ : label is "soft_lutpair250";
  attribute SOFT_HLUTNM of \i__carry_i_11\ : label is "soft_lutpair280";
  attribute SOFT_HLUTNM of \i__carry_i_11__0\ : label is "soft_lutpair236";
  attribute SOFT_HLUTNM of \i__carry_i_12\ : label is "soft_lutpair310";
  attribute SOFT_HLUTNM of ip_header_calc_done_i_1 : label is "soft_lutpair235";
  attribute SOFT_HLUTNM of is_idle_i_1 : label is "soft_lutpair260";
  attribute SOFT_HLUTNM of rd_enable_fifo0_carry_i_10 : label is "soft_lutpair239";
  attribute SOFT_HLUTNM of rd_enable_fifo0_carry_i_11 : label is "soft_lutpair251";
  attribute SOFT_HLUTNM of rd_enable_fifo0_carry_i_12 : label is "soft_lutpair251";
  attribute SOFT_HLUTNM of rd_enable_fifo0_carry_i_13 : label is "soft_lutpair269";
  attribute SOFT_HLUTNM of rd_enable_fifo_i_3 : label is "soft_lutpair316";
  attribute SOFT_HLUTNM of rd_enable_fifo_i_4 : label is "soft_lutpair264";
  attribute SOFT_HLUTNM of rd_enable_fifo_i_5 : label is "soft_lutpair232";
  attribute SOFT_HLUTNM of \send_countdown[0]_i_1\ : label is "soft_lutpair315";
  attribute SOFT_HLUTNM of sent_arp_response_i_1 : label is "soft_lutpair257";
  attribute SOFT_HLUTNM of \start_crc_i_3__0\ : label is "soft_lutpair236";
  attribute SOFT_HLUTNM of \start_crc_i_5__0\ : label is "soft_lutpair231";
  attribute SOFT_HLUTNM of \start_crc_i_6__0\ : label is "soft_lutpair262";
  attribute SOFT_HLUTNM of start_crc_i_7 : label is "soft_lutpair244";
  attribute SOFT_HLUTNM of \state[0]_i_2\ : label is "soft_lutpair314";
  attribute SOFT_HLUTNM of \state[0]_i_3__0\ : label is "soft_lutpair240";
  attribute SOFT_HLUTNM of \state[0]_i_5__0\ : label is "soft_lutpair260";
  attribute SOFT_HLUTNM of \state[0]_i_7__0\ : label is "soft_lutpair317";
  attribute SOFT_HLUTNM of \state[0]_i_9__0\ : label is "soft_lutpair258";
  attribute SOFT_HLUTNM of \state[2]_i_1\ : label is "soft_lutpair240";
  attribute SOFT_HLUTNM of \state[2]_i_11\ : label is "soft_lutpair242";
  attribute SOFT_HLUTNM of \state[2]_i_6__0\ : label is "soft_lutpair231";
  attribute SOFT_HLUTNM of \state[2]_i_7__0\ : label is "soft_lutpair271";
  attribute SOFT_HLUTNM of \stop_crc_i_1__0\ : label is "soft_lutpair234";
  attribute HLUTNM of \temp_iphc10__0_carry__0_i_1\ : label is "lutpair70";
  attribute HLUTNM of \temp_iphc10__0_carry__0_i_2\ : label is "lutpair69";
  attribute HLUTNM of \temp_iphc10__0_carry__0_i_3\ : label is "lutpair68";
  attribute HLUTNM of \temp_iphc10__0_carry__0_i_4\ : label is "lutpair67";
  attribute HLUTNM of \temp_iphc10__0_carry__0_i_5\ : label is "lutpair71";
  attribute HLUTNM of \temp_iphc10__0_carry__0_i_6\ : label is "lutpair70";
  attribute HLUTNM of \temp_iphc10__0_carry__0_i_7\ : label is "lutpair69";
  attribute HLUTNM of \temp_iphc10__0_carry__0_i_8\ : label is "lutpair68";
  attribute HLUTNM of \temp_iphc10__0_carry__1_i_1\ : label is "lutpair74";
  attribute HLUTNM of \temp_iphc10__0_carry__1_i_2\ : label is "lutpair73";
  attribute HLUTNM of \temp_iphc10__0_carry__1_i_3\ : label is "lutpair72";
  attribute HLUTNM of \temp_iphc10__0_carry__1_i_4\ : label is "lutpair71";
  attribute HLUTNM of \temp_iphc10__0_carry__1_i_5\ : label is "lutpair75";
  attribute HLUTNM of \temp_iphc10__0_carry__1_i_6\ : label is "lutpair74";
  attribute HLUTNM of \temp_iphc10__0_carry__1_i_7\ : label is "lutpair73";
  attribute HLUTNM of \temp_iphc10__0_carry__1_i_8\ : label is "lutpair72";
  attribute HLUTNM of \temp_iphc10__0_carry__2_i_1\ : label is "lutpair78";
  attribute HLUTNM of \temp_iphc10__0_carry__2_i_2\ : label is "lutpair77";
  attribute HLUTNM of \temp_iphc10__0_carry__2_i_3\ : label is "lutpair76";
  attribute HLUTNM of \temp_iphc10__0_carry__2_i_4\ : label is "lutpair75";
  attribute HLUTNM of \temp_iphc10__0_carry__2_i_6\ : label is "lutpair78";
  attribute HLUTNM of \temp_iphc10__0_carry__2_i_7\ : label is "lutpair77";
  attribute HLUTNM of \temp_iphc10__0_carry__2_i_8\ : label is "lutpair76";
  attribute HLUTNM of \temp_iphc10__0_carry_i_1\ : label is "lutpair66";
  attribute HLUTNM of \temp_iphc10__0_carry_i_2\ : label is "lutpair65";
  attribute HLUTNM of \temp_iphc10__0_carry_i_3\ : label is "lutpair64";
  attribute HLUTNM of \temp_iphc10__0_carry_i_4\ : label is "lutpair67";
  attribute HLUTNM of \temp_iphc10__0_carry_i_5\ : label is "lutpair66";
  attribute HLUTNM of \temp_iphc10__0_carry_i_6\ : label is "lutpair65";
  attribute HLUTNM of \temp_iphc10__0_carry_i_7\ : label is "lutpair64";
  attribute SOFT_HLUTNM of \temp_iphc10__110_carry__0_i_10\ : label is "soft_lutpair284";
  attribute SOFT_HLUTNM of \temp_iphc10__110_carry__0_i_9\ : label is "soft_lutpair284";
  attribute SOFT_HLUTNM of \temp_iphc10__110_carry__2_i_10\ : label is "soft_lutpair283";
  attribute SOFT_HLUTNM of \temp_iphc10__110_carry__2_i_9\ : label is "soft_lutpair283";
  attribute HLUTNM of \temp_iphc10__110_carry_i_2\ : label is "lutpair80";
  attribute HLUTNM of \temp_iphc10__110_carry_i_3\ : label is "lutpair79";
  attribute HLUTNM of \temp_iphc10__110_carry_i_7\ : label is "lutpair80";
  attribute HLUTNM of \temp_iphc10__110_carry_i_8\ : label is "lutpair79";
  attribute SOFT_HLUTNM of \temp_iphc1[0]_i_1\ : label is "soft_lutpair268";
  attribute SOFT_HLUTNM of \temp_iphc1[1]_i_1\ : label is "soft_lutpair268";
  attribute SOFT_HLUTNM of tx_data_valid_i_1 : label is "soft_lutpair315";
  attribute SOFT_HLUTNM of tx_done_i_1 : label is "soft_lutpair241";
  attribute SOFT_HLUTNM of tx_ready_i_2 : label is "soft_lutpair248";
  attribute SOFT_HLUTNM of \txd[0]_i_11\ : label is "soft_lutpair262";
  attribute SOFT_HLUTNM of \txd[0]_i_41\ : label is "soft_lutpair233";
  attribute SOFT_HLUTNM of \txd[0]_i_43\ : label is "soft_lutpair314";
  attribute SOFT_HLUTNM of \txd[0]_i_45\ : label is "soft_lutpair259";
  attribute SOFT_HLUTNM of \txd[0]_i_58\ : label is "soft_lutpair261";
  attribute SOFT_HLUTNM of \txd[0]_i_6\ : label is "soft_lutpair266";
  attribute SOFT_HLUTNM of \txd[0]_i_62\ : label is "soft_lutpair243";
  attribute SOFT_HLUTNM of \txd[0]_i_64\ : label is "soft_lutpair244";
  attribute SOFT_HLUTNM of \txd[0]_i_67\ : label is "soft_lutpair230";
  attribute SOFT_HLUTNM of \txd[1]_i_12\ : label is "soft_lutpair259";
  attribute SOFT_HLUTNM of \txd[1]_i_29\ : label is "soft_lutpair246";
  attribute SOFT_HLUTNM of \txd[1]_i_44\ : label is "soft_lutpair310";
  attribute SOFT_HLUTNM of \txd[1]_i_51\ : label is "soft_lutpair243";
  attribute SOFT_HLUTNM of \txd[1]_i_55\ : label is "soft_lutpair245";
  attribute SOFT_HLUTNM of \txd[1]_i_87\ : label is "soft_lutpair254";
  attribute SOFT_HLUTNM of txen_i_1 : label is "soft_lutpair241";
  attribute SOFT_HLUTNM of txen_i_2 : label is "soft_lutpair270";
  attribute SOFT_HLUTNM of \zero_counter[2]_i_1__0\ : label is "soft_lutpair252";
  attribute SOFT_HLUTNM of \zero_counter[3]_i_1__0\ : label is "soft_lutpair252";
  attribute SOFT_HLUTNM of \zero_counter[4]_i_1__0\ : label is "soft_lutpair269";
  attribute SOFT_HLUTNM of \zero_counter[4]_i_3\ : label is "soft_lutpair280";
begin
  fifo_read_enable <= \^fifo_read_enable\;
  udp_send_data_valid17_out <= \^udp_send_data_valid17_out\;
\FSM_onehot_s[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8FFF"
    )
        port map (
      I0 => temp_iphc1,
      I1 => ip_header_calc_done,
      I2 => id_counter121_out,
      I3 => tx_ready,
      O => \FSM_onehot_s[0]_i_1_n_0\
    );
\FSM_onehot_s[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8000000"
    )
        port map (
      I0 => temp_iphc2,
      I1 => ip_header_calc_done,
      I2 => temp_iphc1,
      I3 => id_counter121_out,
      I4 => tx_ready,
      O => \FSM_onehot_s[1]_i_1_n_0\
    );
\FSM_onehot_s[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BA000000"
    )
        port map (
      I0 => ip_header_checksum,
      I1 => ip_header_calc_done,
      I2 => temp_iphc2,
      I3 => id_counter121_out,
      I4 => tx_ready,
      O => \FSM_onehot_s[2]_i_1_n_0\
    );
\FSM_onehot_s_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \FSM_onehot_s[0]_i_1_n_0\,
      Q => temp_iphc1,
      R => '0'
    );
\FSM_onehot_s_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \FSM_onehot_s[1]_i_1_n_0\,
      Q => temp_iphc2,
      R => '0'
    );
\FSM_onehot_s_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \FSM_onehot_s[2]_i_1_n_0\,
      Q => ip_header_checksum,
      R => '0'
    );
\L__0_carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \L__0_carry_n_0\,
      CO(2) => \L__0_carry_n_1\,
      CO(1) => \L__0_carry_n_2\,
      CO(0) => \L__0_carry_n_3\,
      CYINIT => '0',
      DI(3) => \L__0_carry_i_1_n_0\,
      DI(2) => \L__0_carry_i_2_n_0\,
      DI(1) => \L__0_carry_i_3_n_0\,
      DI(0) => '0',
      O(3 downto 0) => L(3 downto 0),
      S(3) => \L__0_carry_i_4_n_0\,
      S(2) => \L__0_carry_i_5_n_0\,
      S(1) => \L__0_carry_i_6_n_0\,
      S(0) => \L__0_carry_i_7_n_0\
    );
\L__0_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \L__0_carry_n_0\,
      CO(3) => \L__0_carry__0_n_0\,
      CO(2) => \L__0_carry__0_n_1\,
      CO(1) => \L__0_carry__0_n_2\,
      CO(0) => \L__0_carry__0_n_3\,
      CYINIT => '0',
      DI(3) => \L__0_carry__0_i_1_n_0\,
      DI(2) => \L__0_carry__0_i_2_n_0\,
      DI(1) => \L__0_carry__0_i_3_n_0\,
      DI(0) => \L__0_carry__0_i_4_n_0\,
      O(3 downto 0) => L(7 downto 4),
      S(3) => \L__0_carry__0_i_5_n_0\,
      S(2) => \L__0_carry__0_i_6_n_0\,
      S(1) => \L__0_carry__0_i_7_n_0\,
      S(0) => \L__0_carry__0_i_8_n_0\
    );
\L__0_carry__0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[6]\,
      I1 => \temp_iphc2__0\(6),
      I2 => \temp_iphc1_reg_n_0_[22]\,
      O => \L__0_carry__0_i_1_n_0\
    );
\L__0_carry__0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[5]\,
      I1 => \temp_iphc2__0\(5),
      I2 => \temp_iphc1_reg_n_0_[21]\,
      O => \L__0_carry__0_i_2_n_0\
    );
\L__0_carry__0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[4]\,
      I1 => \temp_iphc2__0\(4),
      I2 => \temp_iphc1_reg_n_0_[20]\,
      O => \L__0_carry__0_i_3_n_0\
    );
\L__0_carry__0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[3]\,
      I1 => \temp_iphc2__0\(3),
      I2 => \temp_iphc1_reg_n_0_[19]\,
      O => \L__0_carry__0_i_4_n_0\
    );
\L__0_carry__0_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \L__0_carry__0_i_1_n_0\,
      I1 => \temp_iphc1_reg_n_0_[7]\,
      I2 => \temp_iphc2__0\(7),
      I3 => \temp_iphc1_reg_n_0_[23]\,
      O => \L__0_carry__0_i_5_n_0\
    );
\L__0_carry__0_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[6]\,
      I1 => \temp_iphc2__0\(6),
      I2 => \temp_iphc1_reg_n_0_[22]\,
      I3 => \L__0_carry__0_i_2_n_0\,
      O => \L__0_carry__0_i_6_n_0\
    );
\L__0_carry__0_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[5]\,
      I1 => \temp_iphc2__0\(5),
      I2 => \temp_iphc1_reg_n_0_[21]\,
      I3 => \L__0_carry__0_i_3_n_0\,
      O => \L__0_carry__0_i_7_n_0\
    );
\L__0_carry__0_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[4]\,
      I1 => \temp_iphc2__0\(4),
      I2 => \temp_iphc1_reg_n_0_[20]\,
      I3 => \L__0_carry__0_i_4_n_0\,
      O => \L__0_carry__0_i_8_n_0\
    );
\L__0_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \L__0_carry__0_n_0\,
      CO(3) => \L__0_carry__1_n_0\,
      CO(2) => \L__0_carry__1_n_1\,
      CO(1) => \L__0_carry__1_n_2\,
      CO(0) => \L__0_carry__1_n_3\,
      CYINIT => '0',
      DI(3) => \L__0_carry__1_i_1_n_0\,
      DI(2) => \L__0_carry__1_i_2_n_0\,
      DI(1) => \L__0_carry__1_i_3_n_0\,
      DI(0) => \L__0_carry__1_i_4_n_0\,
      O(3 downto 0) => L(11 downto 8),
      S(3) => \L__0_carry__1_i_5_n_0\,
      S(2) => \L__0_carry__1_i_6_n_0\,
      S(1) => \L__0_carry__1_i_7_n_0\,
      S(0) => \L__0_carry__1_i_8_n_0\
    );
\L__0_carry__1_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[10]\,
      I1 => \temp_iphc2__0\(10),
      O => \L__0_carry__1_i_1_n_0\
    );
\L__0_carry__1_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[9]\,
      I1 => \temp_iphc2__0\(9),
      O => \L__0_carry__1_i_2_n_0\
    );
\L__0_carry__1_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[8]\,
      I1 => \temp_iphc2__0\(8),
      O => \L__0_carry__1_i_3_n_0\
    );
\L__0_carry__1_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[7]\,
      I1 => \temp_iphc2__0\(7),
      I2 => \temp_iphc1_reg_n_0_[23]\,
      O => \L__0_carry__1_i_4_n_0\
    );
\L__0_carry__1_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \temp_iphc2__0\(10),
      I1 => \temp_iphc1_reg_n_0_[10]\,
      I2 => \temp_iphc2__0\(11),
      I3 => \temp_iphc1_reg_n_0_[11]\,
      O => \L__0_carry__1_i_5_n_0\
    );
\L__0_carry__1_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \temp_iphc2__0\(9),
      I1 => \temp_iphc1_reg_n_0_[9]\,
      I2 => \temp_iphc2__0\(10),
      I3 => \temp_iphc1_reg_n_0_[10]\,
      O => \L__0_carry__1_i_6_n_0\
    );
\L__0_carry__1_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \temp_iphc2__0\(8),
      I1 => \temp_iphc1_reg_n_0_[8]\,
      I2 => \temp_iphc2__0\(9),
      I3 => \temp_iphc1_reg_n_0_[9]\,
      O => \L__0_carry__1_i_7_n_0\
    );
\L__0_carry__1_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E81717E8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[23]\,
      I1 => \temp_iphc2__0\(7),
      I2 => \temp_iphc1_reg_n_0_[7]\,
      I3 => \temp_iphc2__0\(8),
      I4 => \temp_iphc1_reg_n_0_[8]\,
      O => \L__0_carry__1_i_8_n_0\
    );
\L__0_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \L__0_carry__1_n_0\,
      CO(3) => \NLW_L__0_carry__2_CO_UNCONNECTED\(3),
      CO(2) => \L__0_carry__2_n_1\,
      CO(1) => \L__0_carry__2_n_2\,
      CO(0) => \L__0_carry__2_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => \L__0_carry__2_i_1_n_0\,
      DI(1) => \L__0_carry__2_i_2_n_0\,
      DI(0) => \L__0_carry__2_i_3_n_0\,
      O(3 downto 0) => L(15 downto 12),
      S(3) => \L__0_carry__2_i_4_n_0\,
      S(2) => \L__0_carry__2_i_5_n_0\,
      S(1) => \L__0_carry__2_i_6_n_0\,
      S(0) => \L__0_carry__2_i_7_n_0\
    );
\L__0_carry__2_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[13]\,
      I1 => \temp_iphc2__0\(13),
      O => \L__0_carry__2_i_1_n_0\
    );
\L__0_carry__2_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[12]\,
      I1 => \temp_iphc2__0\(12),
      O => \L__0_carry__2_i_2_n_0\
    );
\L__0_carry__2_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[11]\,
      I1 => \temp_iphc2__0\(11),
      O => \L__0_carry__2_i_3_n_0\
    );
\L__0_carry__2_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \temp_iphc2__0\(14),
      I1 => \temp_iphc1_reg_n_0_[14]\,
      I2 => \temp_iphc2__0\(15),
      I3 => \temp_iphc1_reg_n_0_[15]\,
      O => \L__0_carry__2_i_4_n_0\
    );
\L__0_carry__2_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \temp_iphc2__0\(13),
      I1 => \temp_iphc1_reg_n_0_[13]\,
      I2 => \temp_iphc2__0\(14),
      I3 => \temp_iphc1_reg_n_0_[14]\,
      O => \L__0_carry__2_i_5_n_0\
    );
\L__0_carry__2_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \temp_iphc2__0\(12),
      I1 => \temp_iphc1_reg_n_0_[12]\,
      I2 => \temp_iphc2__0\(13),
      I3 => \temp_iphc1_reg_n_0_[13]\,
      O => \L__0_carry__2_i_6_n_0\
    );
\L__0_carry__2_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \temp_iphc2__0\(11),
      I1 => \temp_iphc1_reg_n_0_[11]\,
      I2 => \temp_iphc2__0\(12),
      I3 => \temp_iphc1_reg_n_0_[12]\,
      O => \L__0_carry__2_i_7_n_0\
    );
\L__0_carry_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[2]\,
      I1 => \temp_iphc2__0\(2),
      I2 => \temp_iphc1_reg_n_0_[18]\,
      O => \L__0_carry_i_1_n_0\
    );
\L__0_carry_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[1]\,
      I1 => \temp_iphc2__0\(1),
      I2 => \temp_iphc1_reg_n_0_[17]\,
      O => \L__0_carry_i_2_n_0\
    );
\L__0_carry_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \temp_iphc2__0\(0),
      I1 => \temp_iphc1_reg_n_0_[0]\,
      I2 => \temp_iphc1_reg_n_0_[16]\,
      O => \L__0_carry_i_3_n_0\
    );
\L__0_carry_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[3]\,
      I1 => \temp_iphc2__0\(3),
      I2 => \temp_iphc1_reg_n_0_[19]\,
      I3 => \L__0_carry_i_1_n_0\,
      O => \L__0_carry_i_4_n_0\
    );
\L__0_carry_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[2]\,
      I1 => \temp_iphc2__0\(2),
      I2 => \temp_iphc1_reg_n_0_[18]\,
      I3 => \L__0_carry_i_2_n_0\,
      O => \L__0_carry_i_5_n_0\
    );
\L__0_carry_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[1]\,
      I1 => \temp_iphc2__0\(1),
      I2 => \temp_iphc1_reg_n_0_[17]\,
      I3 => \L__0_carry_i_3_n_0\,
      O => \L__0_carry_i_6_n_0\
    );
\L__0_carry_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \temp_iphc2__0\(0),
      I1 => \temp_iphc1_reg_n_0_[0]\,
      I2 => \temp_iphc1_reg_n_0_[16]\,
      O => \L__0_carry_i_7_n_0\
    );
arp_reply_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0E0A"
    )
        port map (
      I0 => arp_reply_reg_n_0,
      I1 => E(0),
      I2 => tx_done,
      I3 => eth_protocol_reg_0,
      O => arp_reply_i_1_n_0
    );
arp_reply_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => arp_reply_i_1_n_0,
      Q => arp_reply_reg_n_0,
      R => '0'
    );
arp_send_valid_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^udp_send_data_valid17_out\,
      I1 => arp_response_pending,
      O => arp_response_pending_reg
    );
\bit_count0_inferred__0/i__carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \bit_count0_inferred__0/i__carry_n_0\,
      CO(2) => \bit_count0_inferred__0/i__carry_n_1\,
      CO(1) => \bit_count0_inferred__0/i__carry_n_2\,
      CO(0) => \bit_count0_inferred__0/i__carry_n_3\,
      CYINIT => '0',
      DI(3) => \i__carry_i_1__2_n_0\,
      DI(2) => \i__carry_i_2__0_n_0\,
      DI(1) => \i__carry_i_3__0_n_0\,
      DI(0) => \i__carry_i_4__1_n_0\,
      O(3 downto 0) => \NLW_bit_count0_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry_i_5__0_n_0\,
      S(2) => \i__carry_i_6__0_n_0\,
      S(1) => \i__carry_i_7__0_n_0\,
      S(0) => \i__carry_i_8__0_n_0\
    );
\bit_count0_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \bit_count0_inferred__0/i__carry_n_0\,
      CO(3 downto 2) => \NLW_bit_count0_inferred__0/i__carry__0_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \bit_count0_inferred__0/i__carry__0_n_2\,
      CO(0) => \bit_count0_inferred__0/i__carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \i__carry__0_i_1__0_n_0\,
      DI(0) => \i__carry__0_i_2__0_n_0\,
      O(3 downto 0) => \NLW_bit_count0_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => \i__carry__0_i_3__1_n_0\,
      S(0) => \i__carry__0_i_4_n_0\
    );
\bit_count2_inferred__4/i__carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \bit_count2_inferred__4/i__carry_n_0\,
      CO(2) => \bit_count2_inferred__4/i__carry_n_1\,
      CO(1) => \bit_count2_inferred__4/i__carry_n_2\,
      CO(0) => \bit_count2_inferred__4/i__carry_n_3\,
      CYINIT => '0',
      DI(3) => \i__carry_i_1_n_0\,
      DI(2) => \i__carry_i_2_n_0\,
      DI(1) => \i__carry_i_3_n_0\,
      DI(0) => \i__carry_i_4_n_0\,
      O(3 downto 0) => \NLW_bit_count2_inferred__4/i__carry_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry_i_5_n_0\,
      S(2) => \i__carry_i_6_n_0\,
      S(1) => \i__carry_i_7_n_0\,
      S(0) => \i__carry_i_8_n_0\
    );
\bit_count2_inferred__4/i__carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \bit_count2_inferred__4/i__carry_n_0\,
      CO(3 downto 1) => \NLW_bit_count2_inferred__4/i__carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => bit_count223_in,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \i__carry__0_i_1_n_0\,
      O(3 downto 0) => \NLW_bit_count2_inferred__4/i__carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => \i__carry__0_i_2_n_0\
    );
\bit_count2_inferred__5/i__carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \bit_count2_inferred__5/i__carry_n_0\,
      CO(2) => \bit_count2_inferred__5/i__carry_n_1\,
      CO(1) => \bit_count2_inferred__5/i__carry_n_2\,
      CO(0) => \bit_count2_inferred__5/i__carry_n_3\,
      CYINIT => '1',
      DI(3) => \i__carry_i_1__1_n_0\,
      DI(2) => \i__carry_i_2__2_n_0\,
      DI(1) => \i__carry_i_3__1_n_0\,
      DI(0) => \i__carry_i_4__0_n_0\,
      O(3 downto 0) => \NLW_bit_count2_inferred__5/i__carry_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry_i_5__1_n_0\,
      S(2) => \i__carry_i_6__1_n_0\,
      S(1) => \i__carry_i_7__1_n_0\,
      S(0) => \i__carry_i_8__1_n_0\
    );
\bit_count2_inferred__5/i__carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \bit_count2_inferred__5/i__carry_n_0\,
      CO(3 downto 2) => \NLW_bit_count2_inferred__5/i__carry__0_CO_UNCONNECTED\(3 downto 2),
      CO(1) => bit_count233_in,
      CO(0) => \bit_count2_inferred__5/i__carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \i__carry__0_i_1__1_n_0\,
      O(3 downto 0) => \NLW_bit_count2_inferred__5/i__carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => \i__carry__0_i_2__1_n_0\,
      S(0) => \i__carry__0_i_3__0_n_0\
    );
\bit_count[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \bit_count_reg_n_0_[0]\,
      I1 => \bit_count[1]_i_2__0_n_0\,
      O => \bit_count[0]_i_1__0_n_0\
    );
\bit_count[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \bit_count_reg_n_0_[0]\,
      I1 => \bit_count_reg_n_0_[1]\,
      I2 => \bit_count[1]_i_2__0_n_0\,
      O => \bit_count[1]_i_1__0_n_0\
    );
\bit_count[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAAAAAEAAAEAAA"
    )
        port map (
      I0 => \bit_count[3]_i_6_n_0\,
      I1 => \state_reg_n_0_[1]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \state_reg_n_0_[2]\,
      I4 => txen_i_2_n_0,
      I5 => \byte_count[10]_i_17__0_n_0\,
      O => \bit_count[1]_i_2__0_n_0\
    );
\bit_count[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3322332233220322"
    )
        port map (
      I0 => \bit_count[2]_i_2_n_0\,
      I1 => \bit_count[2]_i_3_n_0\,
      I2 => \bit_count[2]_i_4_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \state_reg_n_0_[1]\,
      I5 => \bit_count[2]_i_5_n_0\,
      O => \bit_count[2]_i_1_n_0\
    );
\bit_count[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5F0C5FFC500C50FC"
    )
        port map (
      I0 => \byte_count[10]_i_15__0_n_0\,
      I1 => tx_ready,
      I2 => \state_reg_n_0_[0]\,
      I3 => \state_reg_n_0_[1]\,
      I4 => \byte_count[0]_i_4_n_0\,
      I5 => \state[0]_i_2_n_0\,
      O => \bit_count[2]_i_2_n_0\
    );
\bit_count[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EDEFEDEDA5A5A5A5"
    )
        port map (
      I0 => \byte_count[10]_i_14__0_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => \bit_count_reg_n_0_[3]\,
      I4 => bit_count233_in,
      I5 => rd_enable_fifo_i_5_n_0,
      O => \bit_count[2]_i_3_n_0\
    );
\bit_count[2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAAB"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \byte_count[4]_i_5_n_0\,
      I2 => \bit_count_reg_n_0_[3]\,
      I3 => \bit_count_reg_n_0_[2]\,
      O => \bit_count[2]_i_4_n_0\
    );
\bit_count[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => bit_count223_in,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \bit_count_reg_n_0_[1]\,
      I4 => \bit_count_reg_n_0_[3]\,
      I5 => \bit_count_reg_n_0_[2]\,
      O => \bit_count[2]_i_5_n_0\
    );
\bit_count[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2A2A2FF00000000"
    )
        port map (
      I0 => \state[2]_i_2__0_n_0\,
      I1 => \bit_count[3]_i_3_n_0\,
      I2 => \state_reg_n_0_[1]\,
      I3 => \bit_count_reg[3]_i_4_n_0\,
      I4 => \state_reg_n_0_[2]\,
      I5 => eth_rstn,
      O => bit_count0
    );
\bit_count[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000006CCC"
    )
        port map (
      I0 => \bit_count_reg_n_0_[2]\,
      I1 => \bit_count_reg_n_0_[3]\,
      I2 => \bit_count_reg_n_0_[1]\,
      I3 => \bit_count_reg_n_0_[0]\,
      I4 => \bit_count[3]_i_5_n_0\,
      I5 => \bit_count[3]_i_6_n_0\,
      O => \bit_count[3]_i_2_n_0\
    );
\bit_count[3]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FF3A"
    )
        port map (
      I0 => \bit_count[3]_i_7_n_0\,
      I1 => \state[2]_i_7__0_n_0\,
      I2 => rd_enable_fifo0_carry_i_10_n_0,
      I3 => \bit_count[3]_i_8_n_0\,
      I4 => \state_reg_n_0_[0]\,
      O => \bit_count[3]_i_3_n_0\
    );
\bit_count[3]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \state_reg_n_0_[1]\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \state_reg_n_0_[2]\,
      O => \bit_count[3]_i_5_n_0\
    );
\bit_count[3]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001440100010001"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \state_reg_n_0_[0]\,
      I2 => tx_ready,
      I3 => \state_reg_n_0_[1]\,
      I4 => \bit_count[3]_i_9_n_0\,
      I5 => \byte_count[10]_i_14__0_n_0\,
      O => \bit_count[3]_i_6_n_0\
    );
\bit_count[3]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[0]\,
      O => \bit_count[3]_i_7_n_0\
    );
\bit_count[3]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \byte_count_reg_n_0_[10]\,
      I1 => \byte_count_reg_n_0_[9]\,
      I2 => \byte_count_reg_n_0_[5]\,
      I3 => \byte_count_reg_n_0_[6]\,
      I4 => \byte_count_reg_n_0_[7]\,
      I5 => \byte_count_reg_n_0_[8]\,
      O => \bit_count[3]_i_8_n_0\
    );
\bit_count[3]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEEEEFFF"
    )
        port map (
      I0 => \bit_count_reg_n_0_[2]\,
      I1 => \bit_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => txen_i_3_n_0,
      O => \bit_count[3]_i_9_n_0\
    );
\bit_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => bit_count0,
      D => \bit_count[0]_i_1__0_n_0\,
      Q => \bit_count_reg_n_0_[0]\,
      R => '0'
    );
\bit_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => bit_count0,
      D => \bit_count[1]_i_1__0_n_0\,
      Q => \bit_count_reg_n_0_[1]\,
      R => '0'
    );
\bit_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => bit_count0,
      D => \bit_count[2]_i_1_n_0\,
      Q => \bit_count_reg_n_0_[2]\,
      R => '0'
    );
\bit_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => bit_count0,
      D => \bit_count[3]_i_2_n_0\,
      Q => \bit_count_reg_n_0_[3]\,
      R => '0'
    );
\bit_count_reg[3]_i_4\: unisim.vcomponents.MUXF7
     port map (
      I0 => \state[2]_i_9_n_0\,
      I1 => \state[2]_i_8__0_n_0\,
      O => \bit_count_reg[3]_i_4_n_0\,
      S => \state_reg_n_0_[1]\
    );
\byte0_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => eth_type1,
      Q => byte0(2),
      R => eth_type118_out
    );
\byte10[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \ip_header_checksum_reg_n_0_[9]\,
      I1 => tx_done,
      I2 => id_counter121_out,
      O => \byte10[1]_i_1_n_0\
    );
\byte10[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \ip_header_checksum_reg_n_0_[10]\,
      I1 => tx_done,
      I2 => id_counter121_out,
      O => \byte10[2]_i_1_n_0\
    );
\byte10[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \ip_header_checksum_reg_n_0_[11]\,
      I1 => tx_done,
      I2 => id_counter121_out,
      O => \byte10[3]_i_1_n_0\
    );
\byte10[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \ip_header_checksum_reg_n_0_[12]\,
      I1 => tx_done,
      I2 => id_counter121_out,
      O => \byte10[4]_i_1_n_0\
    );
\byte10[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \ip_header_checksum_reg_n_0_[13]\,
      I1 => tx_done,
      I2 => id_counter121_out,
      O => \byte10[5]_i_1_n_0\
    );
\byte10_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_header_checksum_reg_n_0_[8]\,
      Q => byte10(0),
      R => byte2(1)
    );
\byte10_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte10[1]_i_1_n_0\,
      Q => byte10(1),
      S => eth_type118_out
    );
\byte10_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte10[2]_i_1_n_0\,
      Q => byte10(2),
      S => eth_type118_out
    );
\byte10_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte10[3]_i_1_n_0\,
      Q => byte10(3),
      S => eth_type118_out
    );
\byte10_reg[4]\: unisim.vcomponents.FDSE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte10[4]_i_1_n_0\,
      Q => byte10(4),
      S => eth_type118_out
    );
\byte10_reg[5]\: unisim.vcomponents.FDSE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte10[5]_i_1_n_0\,
      Q => byte10(5),
      S => eth_type118_out
    );
\byte10_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_header_checksum_reg_n_0_[14]\,
      Q => byte10(6),
      R => byte2(1)
    );
\byte10_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_header_checksum_reg_n_0_[15]\,
      Q => byte10(7),
      R => byte2(1)
    );
\byte11[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \ip_header_checksum_reg_n_0_[0]\,
      I1 => tx_done,
      I2 => id_counter121_out,
      O => \byte11[0]_i_1_n_0\
    );
\byte11_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte11[0]_i_1_n_0\,
      Q => byte11(0),
      S => eth_type118_out
    );
\byte11_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_header_checksum_reg_n_0_[1]\,
      Q => byte11(1),
      R => byte2(1)
    );
\byte11_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_header_checksum_reg_n_0_[2]\,
      Q => byte11(2),
      R => byte2(1)
    );
\byte11_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_header_checksum_reg_n_0_[3]\,
      Q => byte11(3),
      R => byte2(1)
    );
\byte11_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_header_checksum_reg_n_0_[4]\,
      Q => byte11(4),
      R => byte2(1)
    );
\byte11_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_header_checksum_reg_n_0_[5]\,
      Q => byte11(5),
      R => byte2(1)
    );
\byte11_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_header_checksum_reg_n_0_[6]\,
      Q => byte11(6),
      R => byte2(1)
    );
\byte11_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_header_checksum_reg_n_0_[7]\,
      Q => byte11(7),
      R => byte2(1)
    );
\byte12[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"32"
    )
        port map (
      I0 => arp_reply_reg_n_0,
      I1 => tx_done,
      I2 => id_counter121_out,
      O => \byte12[7]_i_1_n_0\
    );
\byte12_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte12[7]_i_1_n_0\,
      Q => byte12(7),
      R => '0'
    );
\byte13[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => ip(0),
      I1 => tx_done,
      I2 => arp_reply_reg_n_0,
      O => \byte13[0]_i_1_n_0\
    );
\byte13[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => ip(1),
      I1 => tx_done,
      I2 => arp_reply_reg_n_0,
      O => \byte13[1]_i_1_n_0\
    );
\byte13[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => ip(2),
      I1 => tx_done,
      I2 => arp_reply_reg_n_0,
      O => \byte13[2]_i_1_n_0\
    );
\byte13[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0B08"
    )
        port map (
      I0 => ip(3),
      I1 => arp_reply_reg_n_0,
      I2 => tx_done,
      I3 => id_counter121_out,
      O => \byte13[3]_i_1_n_0\
    );
\byte13[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => ip(4),
      I1 => tx_done,
      I2 => arp_reply_reg_n_0,
      O => \byte13[4]_i_1_n_0\
    );
\byte13_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte13[0]_i_1_n_0\,
      Q => byte13(0),
      R => '0'
    );
\byte13_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte13[1]_i_1_n_0\,
      Q => byte13(1),
      R => '0'
    );
\byte13_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte13[2]_i_1_n_0\,
      Q => byte13(2),
      R => '0'
    );
\byte13_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte13[3]_i_1_n_0\,
      Q => byte13(3),
      R => '0'
    );
\byte13_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte13[4]_i_1_n_0\,
      Q => byte13(4),
      R => '0'
    );
\byte15[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => ip(3),
      I1 => tx_done,
      I2 => id_counter121_out,
      O => \byte15[3]_i_1_n_0\
    );
\byte15_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => ip(0),
      Q => byte15(0),
      R => byte2(1)
    );
\byte15_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => ip(1),
      Q => byte15(1),
      R => byte2(1)
    );
\byte15_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => ip(2),
      Q => byte15(2),
      R => byte2(1)
    );
\byte15_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte15[3]_i_1_n_0\,
      Q => byte15(3),
      S => eth_type118_out
    );
\byte15_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => ip(4),
      Q => byte15(4),
      R => byte2(1)
    );
\byte16[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => p_0_in0_in(8),
      I1 => tx_done,
      I2 => id_counter121_out,
      O => \byte16[0]_i_1_n_0\
    );
\byte16_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte16[0]_i_1_n_0\,
      Q => byte16(0),
      S => eth_type118_out
    );
\byte16_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_0_in0_in(9),
      Q => byte16(1),
      R => byte2(1)
    );
\byte16_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_0_in0_in(10),
      Q => byte16(2),
      R => byte2(1)
    );
\byte16_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_0_in0_in(11),
      Q => byte16(3),
      R => byte2(1)
    );
\byte16_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_0_in0_in(12),
      Q => byte16(4),
      R => byte2(1)
    );
\byte16_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_0_in0_in(13),
      Q => byte16(5),
      R => byte2(1)
    );
\byte16_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_0_in0_in(14),
      Q => byte16(6),
      R => byte2(1)
    );
\byte16_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_0_in0_in(15),
      Q => byte16(7),
      R => byte2(1)
    );
\byte17[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22302200"
    )
        port map (
      I0 => ip(0),
      I1 => tx_done,
      I2 => id_counter121_out,
      I3 => arp_reply_reg_n_0,
      I4 => p_0_in0_in(0),
      O => \byte17[0]_i_1_n_0\
    );
\byte17[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22302200"
    )
        port map (
      I0 => ip(1),
      I1 => tx_done,
      I2 => id_counter121_out,
      I3 => arp_reply_reg_n_0,
      I4 => p_0_in0_in(1),
      O => \byte17[1]_i_1_n_0\
    );
\byte17[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22302200"
    )
        port map (
      I0 => ip(2),
      I1 => tx_done,
      I2 => id_counter121_out,
      I3 => arp_reply_reg_n_0,
      I4 => p_0_in0_in(2),
      O => \byte17[2]_i_1_n_0\
    );
\byte17[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0B080808"
    )
        port map (
      I0 => ip(3),
      I1 => arp_reply_reg_n_0,
      I2 => tx_done,
      I3 => p_0_in0_in(3),
      I4 => id_counter121_out,
      O => \byte17[3]_i_1_n_0\
    );
\byte17[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22302200"
    )
        port map (
      I0 => ip(4),
      I1 => tx_done,
      I2 => id_counter121_out,
      I3 => arp_reply_reg_n_0,
      I4 => p_0_in0_in(4),
      O => \byte17[4]_i_1_n_0\
    );
\byte17[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => p_0_in0_in(5),
      I1 => tx_done,
      I2 => id_counter121_out,
      O => \byte17[5]_i_1_n_0\
    );
\byte17_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte17[0]_i_1_n_0\,
      Q => byte17(0),
      R => '0'
    );
\byte17_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte17[1]_i_1_n_0\,
      Q => byte17(1),
      R => '0'
    );
\byte17_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte17[2]_i_1_n_0\,
      Q => byte17(2),
      R => '0'
    );
\byte17_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte17[3]_i_1_n_0\,
      Q => byte17(3),
      R => '0'
    );
\byte17_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte17[4]_i_1_n_0\,
      Q => byte17(4),
      R => '0'
    );
\byte17_reg[5]\: unisim.vcomponents.FDSE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte17[5]_i_1_n_0\,
      Q => byte17(5),
      S => eth_type118_out
    );
\byte17_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_0_in0_in(6),
      Q => byte17(6),
      R => byte2(1)
    );
\byte17_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_0_in0_in(7),
      Q => byte17(7),
      R => byte2(1)
    );
\byte18[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[40]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[8]\,
      O => \byte18[0]_i_1_n_0\
    );
\byte18[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[41]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[9]\,
      O => \byte18[1]_i_1_n_0\
    );
\byte18[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[42]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[10]\,
      O => \byte18[2]_i_1_n_0\
    );
\byte18[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[43]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[11]\,
      O => \byte18[3]_i_1_n_0\
    );
\byte18[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[44]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[12]\,
      O => \byte18[4]_i_1_n_0\
    );
\byte18[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[45]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[13]\,
      O => \byte18[5]_i_1_n_0\
    );
\byte18[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[46]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[14]\,
      O => \byte18[6]_i_1_n_0\
    );
\byte18[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"CD"
    )
        port map (
      I0 => id_counter121_out,
      I1 => tx_done,
      I2 => arp_reply_reg_n_0,
      O => byte18
    );
\byte18[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[47]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[15]\,
      O => \byte18[7]_i_2_n_0\
    );
\byte18_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte18[0]_i_1_n_0\,
      Q => \byte18_reg_n_0_[0]\,
      R => byte18
    );
\byte18_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte18[1]_i_1_n_0\,
      Q => \byte18_reg_n_0_[1]\,
      R => byte18
    );
\byte18_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte18[2]_i_1_n_0\,
      Q => \byte18_reg_n_0_[2]\,
      R => byte18
    );
\byte18_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte18[3]_i_1_n_0\,
      Q => \byte18_reg_n_0_[3]\,
      R => byte18
    );
\byte18_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte18[4]_i_1_n_0\,
      Q => \byte18_reg_n_0_[4]\,
      R => byte18
    );
\byte18_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte18[5]_i_1_n_0\,
      Q => \byte18_reg_n_0_[5]\,
      R => byte18
    );
\byte18_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte18[6]_i_1_n_0\,
      Q => \byte18_reg_n_0_[6]\,
      R => byte18
    );
\byte18_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte18[7]_i_2_n_0\,
      Q => \byte18_reg_n_0_[7]\,
      R => byte18
    );
\byte19[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[32]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[0]\,
      O => \byte19[0]_i_1_n_0\
    );
\byte19[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[33]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[1]\,
      O => \byte19[1]_i_1_n_0\
    );
\byte19[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[34]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[2]\,
      O => \byte19[2]_i_1_n_0\
    );
\byte19[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[35]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[3]\,
      O => \byte19[3]_i_1_n_0\
    );
\byte19[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[36]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[4]\,
      O => \byte19[4]_i_1_n_0\
    );
\byte19[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[37]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[5]\,
      O => \byte19[5]_i_1_n_0\
    );
\byte19[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[38]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[6]\,
      O => \byte19[6]_i_1_n_0\
    );
\byte19[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[39]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_ip_reg_n_0_[7]\,
      O => \byte19[7]_i_1_n_0\
    );
\byte19_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte19[0]_i_1_n_0\,
      Q => byte19(0),
      R => byte18
    );
\byte19_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte19[1]_i_1_n_0\,
      Q => byte19(1),
      R => byte18
    );
\byte19_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte19[2]_i_1_n_0\,
      Q => byte19(2),
      R => byte18
    );
\byte19_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte19[3]_i_1_n_0\,
      Q => byte19(3),
      R => byte18
    );
\byte19_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte19[4]_i_1_n_0\,
      Q => byte19(4),
      R => byte18
    );
\byte19_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte19[5]_i_1_n_0\,
      Q => byte19(5),
      R => byte18
    );
\byte19_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte19[6]_i_1_n_0\,
      Q => byte19(6),
      R => byte18
    );
\byte19_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte19[7]_i_1_n_0\,
      Q => byte19(7),
      R => byte18
    );
\byte20[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0B08"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[26]\,
      I1 => arp_reply_reg_n_0,
      I2 => tx_done,
      I3 => id_counter121_out,
      O => \byte20[2]_i_1_n_0\
    );
\byte20[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => tx_done,
      I1 => arp_reply_reg_n_0,
      O => \byte20[7]_i_1_n_0\
    );
\byte20_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \dest_mac_reg_n_0_[24]\,
      Q => byte20(0),
      R => \byte20[7]_i_1_n_0\
    );
\byte20_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \dest_mac_reg_n_0_[25]\,
      Q => byte20(1),
      R => \byte20[7]_i_1_n_0\
    );
\byte20_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte20[2]_i_1_n_0\,
      Q => byte20(2),
      R => '0'
    );
\byte20_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \dest_mac_reg_n_0_[27]\,
      Q => byte20(3),
      R => \byte20[7]_i_1_n_0\
    );
\byte20_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \dest_mac_reg_n_0_[28]\,
      Q => byte20(4),
      R => \byte20[7]_i_1_n_0\
    );
\byte20_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \dest_mac_reg_n_0_[29]\,
      Q => byte20(5),
      R => \byte20[7]_i_1_n_0\
    );
\byte20_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \dest_mac_reg_n_0_[30]\,
      Q => byte20(6),
      R => \byte20[7]_i_1_n_0\
    );
\byte20_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \dest_mac_reg_n_0_[31]\,
      Q => byte20(7),
      R => \byte20[7]_i_1_n_0\
    );
\byte21[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0B08"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[17]\,
      I1 => arp_reply_reg_n_0,
      I2 => tx_done,
      I3 => id_counter121_out,
      O => \byte21[1]_i_1_n_0\
    );
\byte21[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0B08"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[20]\,
      I1 => arp_reply_reg_n_0,
      I2 => tx_done,
      I3 => id_counter121_out,
      O => \byte21[4]_i_1_n_0\
    );
\byte21[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0B08"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[22]\,
      I1 => arp_reply_reg_n_0,
      I2 => tx_done,
      I3 => id_counter121_out,
      O => \byte21[6]_i_1_n_0\
    );
\byte21[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0B08"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[23]\,
      I1 => arp_reply_reg_n_0,
      I2 => tx_done,
      I3 => id_counter121_out,
      O => \byte21[7]_i_1_n_0\
    );
\byte21_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \dest_mac_reg_n_0_[16]\,
      Q => byte21(0),
      R => \byte20[7]_i_1_n_0\
    );
\byte21_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte21[1]_i_1_n_0\,
      Q => byte21(1),
      R => '0'
    );
\byte21_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \dest_mac_reg_n_0_[18]\,
      Q => byte21(2),
      R => \byte20[7]_i_1_n_0\
    );
\byte21_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \dest_mac_reg_n_0_[19]\,
      Q => byte21(3),
      R => \byte20[7]_i_1_n_0\
    );
\byte21_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte21[4]_i_1_n_0\,
      Q => byte21(4),
      R => '0'
    );
\byte21_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \dest_mac_reg_n_0_[21]\,
      Q => byte21(5),
      R => \byte20[7]_i_1_n_0\
    );
\byte21_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte21[6]_i_1_n_0\,
      Q => byte21(6),
      R => '0'
    );
\byte21_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte21[7]_i_1_n_0\,
      Q => byte21(7),
      R => '0'
    );
\byte22[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[8]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[8]\,
      O => \byte22[0]_i_1_n_0\
    );
\byte22[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[9]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[9]\,
      O => \byte22[1]_i_1_n_0\
    );
\byte22[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[10]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[10]\,
      O => \byte22[2]_i_1_n_0\
    );
\byte22[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[11]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[11]\,
      O => \byte22[3]_i_1_n_0\
    );
\byte22[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[12]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[12]\,
      O => \byte22[4]_i_1_n_0\
    );
\byte22[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[13]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[13]\,
      O => \byte22[5]_i_1_n_0\
    );
\byte22[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[14]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[14]\,
      O => \byte22[6]_i_1_n_0\
    );
\byte22[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[15]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[15]\,
      O => \byte22[7]_i_1_n_0\
    );
\byte22_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte22[0]_i_1_n_0\,
      Q => byte22(0),
      R => byte18
    );
\byte22_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte22[1]_i_1_n_0\,
      Q => byte22(1),
      R => byte18
    );
\byte22_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte22[2]_i_1_n_0\,
      Q => byte22(2),
      R => byte18
    );
\byte22_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte22[3]_i_1_n_0\,
      Q => byte22(3),
      R => byte18
    );
\byte22_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte22[4]_i_1_n_0\,
      Q => byte22(4),
      R => byte18
    );
\byte22_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte22[5]_i_1_n_0\,
      Q => byte22(5),
      R => byte18
    );
\byte22_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte22[6]_i_1_n_0\,
      Q => byte22(6),
      R => byte18
    );
\byte22_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte22[7]_i_1_n_0\,
      Q => byte22(7),
      R => byte18
    );
\byte23[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[0]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[0]\,
      O => \byte23[0]_i_1_n_0\
    );
\byte23[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[1]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[1]\,
      O => \byte23[1]_i_1_n_0\
    );
\byte23[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[2]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[2]\,
      O => \byte23[2]_i_1_n_0\
    );
\byte23[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[3]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[3]\,
      O => \byte23[3]_i_1_n_0\
    );
\byte23[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[4]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[4]\,
      O => \byte23[4]_i_1_n_0\
    );
\byte23[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[5]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[5]\,
      O => \byte23[5]_i_1_n_0\
    );
\byte23[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[6]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[6]\,
      O => \byte23[6]_i_1_n_0\
    );
\byte23[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[7]\,
      I1 => arp_reply_reg_n_0,
      I2 => \dest_port_reg_n_0_[7]\,
      O => \byte23[7]_i_1_n_0\
    );
\byte23_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte23[0]_i_1_n_0\,
      Q => byte23(0),
      R => byte18
    );
\byte23_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte23[1]_i_1_n_0\,
      Q => byte23(1),
      R => byte18
    );
\byte23_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte23[2]_i_1_n_0\,
      Q => byte23(2),
      R => byte18
    );
\byte23_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte23[3]_i_1_n_0\,
      Q => byte23(3),
      R => byte18
    );
\byte23_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte23[4]_i_1_n_0\,
      Q => byte23(4),
      R => byte18
    );
\byte23_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte23[5]_i_1_n_0\,
      Q => byte23(5),
      R => byte18
    );
\byte23_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte23[6]_i_1_n_0\,
      Q => byte23(6),
      R => byte18
    );
\byte23_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte23[7]_i_1_n_0\,
      Q => byte23(7),
      R => byte18
    );
\byte24[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in0_in(8),
      I1 => arp_reply_reg_n_0,
      I2 => \udp_length_reg_n_0_[8]\,
      O => \byte24[0]_i_1_n_0\
    );
\byte24[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in0_in(9),
      I1 => arp_reply_reg_n_0,
      I2 => \udp_length_reg_n_0_[9]\,
      O => \byte24[1]_i_1_n_0\
    );
\byte24[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in0_in(10),
      I1 => arp_reply_reg_n_0,
      I2 => \udp_length_reg_n_0_[10]\,
      O => \byte24[2]_i_1_n_0\
    );
\byte24[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in0_in(11),
      I1 => arp_reply_reg_n_0,
      I2 => \udp_length_reg_n_0_[11]\,
      O => \byte24[3]_i_1_n_0\
    );
\byte24[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in0_in(12),
      I1 => arp_reply_reg_n_0,
      I2 => \udp_length_reg_n_0_[12]\,
      O => \byte24[4]_i_1_n_0\
    );
\byte24[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in0_in(13),
      I1 => arp_reply_reg_n_0,
      I2 => \udp_length_reg_n_0_[13]\,
      O => \byte24[5]_i_1_n_0\
    );
\byte24[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in0_in(14),
      I1 => arp_reply_reg_n_0,
      I2 => \udp_length_reg_n_0_[14]\,
      O => \byte24[6]_i_1_n_0\
    );
\byte24[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in0_in(15),
      I1 => arp_reply_reg_n_0,
      I2 => \udp_length_reg_n_0_[15]\,
      O => \byte24[7]_i_1_n_0\
    );
\byte24_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte24[0]_i_1_n_0\,
      Q => byte24(0),
      R => byte18
    );
\byte24_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte24[1]_i_1_n_0\,
      Q => byte24(1),
      R => byte18
    );
\byte24_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte24[2]_i_1_n_0\,
      Q => byte24(2),
      R => byte18
    );
\byte24_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte24[3]_i_1_n_0\,
      Q => byte24(3),
      R => byte18
    );
\byte24_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte24[4]_i_1_n_0\,
      Q => byte24(4),
      R => byte18
    );
\byte24_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte24[5]_i_1_n_0\,
      Q => byte24(5),
      R => byte18
    );
\byte24_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte24[6]_i_1_n_0\,
      Q => byte24(6),
      R => byte18
    );
\byte24_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte24[7]_i_1_n_0\,
      Q => byte24(7),
      R => byte18
    );
\byte25[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in0_in(0),
      I1 => arp_reply_reg_n_0,
      O => \byte25[0]_i_1_n_0\
    );
\byte25[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in0_in(1),
      I1 => arp_reply_reg_n_0,
      O => \byte25[1]_i_1_n_0\
    );
\byte25[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in0_in(2),
      I1 => arp_reply_reg_n_0,
      I2 => \udp_length_reg_n_0_[2]\,
      O => \byte25[2]_i_1_n_0\
    );
\byte25[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in0_in(3),
      I1 => arp_reply_reg_n_0,
      I2 => \udp_length_reg_n_0_[3]\,
      O => \byte25[3]_i_1_n_0\
    );
\byte25[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in0_in(4),
      I1 => arp_reply_reg_n_0,
      I2 => \udp_length_reg_n_0_[4]\,
      O => \byte25[4]_i_1_n_0\
    );
\byte25[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in0_in(5),
      I1 => arp_reply_reg_n_0,
      I2 => \udp_length_reg_n_0_[5]\,
      O => \byte25[5]_i_1_n_0\
    );
\byte25[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in0_in(6),
      I1 => arp_reply_reg_n_0,
      I2 => \udp_length_reg_n_0_[6]\,
      O => \byte25[6]_i_1_n_0\
    );
\byte25[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => p_0_in0_in(7),
      I1 => arp_reply_reg_n_0,
      I2 => \udp_length_reg_n_0_[7]\,
      O => \byte25[7]_i_1_n_0\
    );
\byte25_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte25[0]_i_1_n_0\,
      Q => byte25(0),
      R => byte18
    );
\byte25_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte25[1]_i_1_n_0\,
      Q => byte25(1),
      R => byte18
    );
\byte25_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte25[2]_i_1_n_0\,
      Q => byte25(2),
      R => byte18
    );
\byte25_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte25[3]_i_1_n_0\,
      Q => byte25(3),
      R => byte18
    );
\byte25_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte25[4]_i_1_n_0\,
      Q => byte25(4),
      R => byte18
    );
\byte25_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte25[5]_i_1_n_0\,
      Q => byte25(5),
      R => byte18
    );
\byte25_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte25[6]_i_1_n_0\,
      Q => byte25(6),
      R => byte18
    );
\byte25_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte25[7]_i_1_n_0\,
      Q => byte25(7),
      R => byte18
    );
\byte26[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[8]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[8]\,
      O => \byte26[0]_i_1_n_0\
    );
\byte26[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[9]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[9]\,
      O => \byte26[1]_i_1_n_0\
    );
\byte26[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[10]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[10]\,
      O => \byte26[2]_i_1_n_0\
    );
\byte26[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[11]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[11]\,
      O => \byte26[3]_i_1_n_0\
    );
\byte26[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[12]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[12]\,
      O => \byte26[4]_i_1_n_0\
    );
\byte26[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[13]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[13]\,
      O => \byte26[5]_i_1_n_0\
    );
\byte26[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[14]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[14]\,
      O => \byte26[6]_i_1_n_0\
    );
\byte26[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[15]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[15]\,
      O => \byte26[7]_i_1_n_0\
    );
\byte26_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte26[0]_i_1_n_0\,
      Q => byte26(0),
      R => byte18
    );
\byte26_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte26[1]_i_1_n_0\,
      Q => byte26(1),
      R => byte18
    );
\byte26_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte26[2]_i_1_n_0\,
      Q => byte26(2),
      R => byte18
    );
\byte26_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte26[3]_i_1_n_0\,
      Q => byte26(3),
      R => byte18
    );
\byte26_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte26[4]_i_1_n_0\,
      Q => byte26(4),
      R => byte18
    );
\byte26_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte26[5]_i_1_n_0\,
      Q => byte26(5),
      R => byte18
    );
\byte26_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte26[6]_i_1_n_0\,
      Q => byte26(6),
      R => byte18
    );
\byte26_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte26[7]_i_1_n_0\,
      Q => byte26(7),
      R => byte18
    );
\byte27[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[0]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[0]\,
      O => \byte27[0]_i_1_n_0\
    );
\byte27[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[1]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[1]\,
      O => \byte27[1]_i_1_n_0\
    );
\byte27[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[2]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[2]\,
      O => \byte27[2]_i_1_n_0\
    );
\byte27[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[3]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[3]\,
      O => \byte27[3]_i_1_n_0\
    );
\byte27[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[4]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[4]\,
      O => \byte27[4]_i_1_n_0\
    );
\byte27[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[5]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[5]\,
      O => \byte27[5]_i_1_n_0\
    );
\byte27[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[6]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[6]\,
      O => \byte27[6]_i_1_n_0\
    );
\byte27[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[7]\,
      I1 => arp_reply_reg_n_0,
      I2 => \udp_checksum_reg_n_0_[7]\,
      O => \byte27[7]_i_1_n_0\
    );
\byte27_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte27[0]_i_1_n_0\,
      Q => byte27(0),
      R => byte18
    );
\byte27_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte27[1]_i_1_n_0\,
      Q => byte27(1),
      R => byte18
    );
\byte27_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte27[2]_i_1_n_0\,
      Q => byte27(2),
      R => byte18
    );
\byte27_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte27[3]_i_1_n_0\,
      Q => byte27(3),
      R => byte18
    );
\byte27_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte27[4]_i_1_n_0\,
      Q => byte27(4),
      R => byte18
    );
\byte27_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte27[5]_i_1_n_0\,
      Q => byte27(5),
      R => byte18
    );
\byte27_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte27[6]_i_1_n_0\,
      Q => byte27(6),
      R => byte18
    );
\byte27_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte27[7]_i_1_n_0\,
      Q => byte27(7),
      R => byte18
    );
\byte2[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => p_1_in(3),
      I1 => tx_done,
      I2 => id_counter121_out,
      O => \byte2[3]_i_1_n_0\
    );
\byte2[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FB"
    )
        port map (
      I0 => arp_reply_reg_n_0,
      I1 => id_counter121_out,
      I2 => tx_done,
      O => byte2(1)
    );
\byte2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_1_in(0),
      Q => \byte2_reg_n_0_[0]\,
      R => byte2(1)
    );
\byte2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_1_in(1),
      Q => \byte2_reg_n_0_[1]\,
      R => byte2(1)
    );
\byte2_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_1_in(2),
      Q => \byte2_reg_n_0_[2]\,
      R => byte2(1)
    );
\byte2_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte2[3]_i_1_n_0\,
      Q => \byte2_reg_n_0_[3]\,
      S => eth_type118_out
    );
\byte2_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_1_in(4),
      Q => \byte2_reg_n_0_[4]\,
      R => byte2(1)
    );
\byte2_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_1_in(5),
      Q => \byte2_reg_n_0_[5]\,
      R => byte2(1)
    );
\byte2_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_1_in(6),
      Q => \byte2_reg_n_0_[6]\,
      R => byte2(1)
    );
\byte2_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => p_1_in(7),
      Q => \byte2_reg_n_0_[7]\,
      R => byte2(1)
    );
\byte3_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_total_length_reg_n_0_[2]\,
      Q => byte3(2),
      R => byte2(1)
    );
\byte3_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_total_length_reg_n_0_[3]\,
      Q => byte3(3),
      R => byte2(1)
    );
\byte3_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_total_length_reg_n_0_[4]\,
      Q => byte3(4),
      R => byte2(1)
    );
\byte3_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_total_length_reg_n_0_[5]\,
      Q => byte3(5),
      R => byte2(1)
    );
\byte3_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_total_length_reg_n_0_[6]\,
      Q => byte3(6),
      R => byte2(1)
    );
\byte3_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \ip_total_length_reg_n_0_[7]\,
      Q => byte3(7),
      R => byte2(1)
    );
\byte4[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \id_counter__0\(9),
      I1 => tx_done,
      I2 => id_counter121_out,
      O => \byte4[1]_i_1_n_0\
    );
\byte4[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \id_counter__0\(10),
      I1 => tx_done,
      I2 => id_counter121_out,
      O => \byte4[2]_i_1_n_0\
    );
\byte4_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \id_counter__0\(8),
      Q => byte4(0),
      R => byte2(1)
    );
\byte4_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte4[1]_i_1_n_0\,
      Q => byte4(1),
      S => eth_type118_out
    );
\byte4_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte4[2]_i_1_n_0\,
      Q => byte4(2),
      S => eth_type118_out
    );
\byte4_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \id_counter__0\(11),
      Q => byte4(3),
      R => byte2(1)
    );
\byte4_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \id_counter__0\(12),
      Q => byte4(4),
      R => byte2(1)
    );
\byte4_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \id_counter__0\(13),
      Q => byte4(5),
      R => byte2(1)
    );
\byte4_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \id_counter__0\(14),
      Q => byte4(6),
      R => byte2(1)
    );
\byte4_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \id_counter__0\(15),
      Q => byte4(7),
      R => byte2(1)
    );
\byte5[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \id_counter__0\(2),
      I1 => tx_done,
      I2 => id_counter121_out,
      O => \byte5[2]_i_1_n_0\
    );
\byte5_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \id_counter__0\(0),
      Q => \byte5_reg_n_0_[0]\,
      R => byte2(1)
    );
\byte5_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \id_counter__0\(1),
      Q => \byte5_reg_n_0_[1]\,
      R => byte2(1)
    );
\byte5_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte5[2]_i_1_n_0\,
      Q => \byte5_reg_n_0_[2]\,
      S => eth_type118_out
    );
\byte5_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \id_counter__0\(3),
      Q => \byte5_reg_n_0_[3]\,
      R => byte2(1)
    );
\byte5_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \id_counter__0\(4),
      Q => \byte5_reg_n_0_[4]\,
      R => byte2(1)
    );
\byte5_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \id_counter__0\(5),
      Q => \byte5_reg_n_0_[5]\,
      R => byte2(1)
    );
\byte5_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \id_counter__0\(6),
      Q => \byte5_reg_n_0_[6]\,
      R => byte2(1)
    );
\byte5_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \id_counter__0\(7),
      Q => \byte5_reg_n_0_[7]\,
      R => byte2(1)
    );
\byte7_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => '0',
      Q => byte7(1),
      S => eth_type118_out
    );
\byte8[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => tx_done,
      I1 => id_counter121_out,
      I2 => arp_reply_reg_n_0,
      O => byte8(7)
    );
\byte8_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => byte8(7),
      Q => \byte8_reg_n_0_[7]\,
      R => '0'
    );
\byte9_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => eth_type118_out,
      Q => byte9(3),
      R => '0'
    );
\byte_count[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000F0FEFEFEFE"
    )
        port map (
      I0 => \byte_count[10]_i_11__0_n_0\,
      I1 => \byte_count[0]_i_2__0_n_0\,
      I2 => \byte_count[0]_i_3__0_n_0\,
      I3 => \byte_count[10]_i_8__0_n_0\,
      I4 => \state_reg_n_0_[1]\,
      I5 => \byte_count_reg_n_0_[0]\,
      O => byte_count(0)
    );
\byte_count[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"080A080008000800"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \byte_count[10]_i_15__0_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \state_reg_n_0_[1]\,
      I4 => \byte_count[0]_i_4_n_0\,
      I5 => \byte_count[10]_i_14__0_n_0\,
      O => \byte_count[0]_i_2__0_n_0\
    );
\byte_count[0]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAFEAA"
    )
        port map (
      I0 => \byte_count[10]_i_21__0_n_0\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \byte_count[4]_i_3_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \state_reg_n_0_[1]\,
      O => \byte_count[0]_i_3__0_n_0\
    );
\byte_count[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000001010001"
    )
        port map (
      I0 => \bit_count_reg_n_0_[2]\,
      I1 => \bit_count_reg_n_0_[3]\,
      I2 => txen_i_3_n_0,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count[3]_i_3_n_0\,
      I5 => \byte_count_reg_n_0_[3]\,
      O => \byte_count[0]_i_4_n_0\
    );
\byte_count[10]_i_10__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \byte_count[10]_i_21__0_n_0\,
      I1 => \byte_count[0]_i_2__0_n_0\,
      O => \byte_count[10]_i_10__0_n_0\
    );
\byte_count[10]_i_11__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \byte_count[10]_i_22_n_0\,
      I1 => \state_reg_n_0_[1]\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \state_reg_n_0_[0]\,
      O => \byte_count[10]_i_11__0_n_0\
    );
\byte_count[10]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[10]\,
      I1 => \i__carry__0_i_5_n_0\,
      I2 => \byte_count_reg_n_0_[8]\,
      I3 => \byte_count_reg_n_0_[9]\,
      O => \byte_count[10]_i_12_n_0\
    );
\byte_count[10]_i_13__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \state_reg_n_0_[1]\,
      I2 => \state[2]_i_11_n_0\,
      O => \byte_count[10]_i_13__0_n_0\
    );
\byte_count[10]_i_14__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \bit_count_reg_n_0_[1]\,
      I1 => \bit_count_reg_n_0_[0]\,
      O => \byte_count[10]_i_14__0_n_0\
    );
\byte_count[10]_i_15__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00002AAA00000000"
    )
        port map (
      I0 => \state[2]_i_7__0_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => txen_i_3_n_0,
      I5 => \byte_count[10]_i_14__0_n_0\,
      O => \byte_count[10]_i_15__0_n_0\
    );
\byte_count[10]_i_16__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \byte_count_reg_n_0_[0]\,
      I1 => \byte_count_reg_n_0_[1]\,
      O => \byte_count[10]_i_16__0_n_0\
    );
\byte_count[10]_i_17__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0111"
    )
        port map (
      I0 => \bit_count_reg_n_0_[3]\,
      I1 => \bit_count_reg_n_0_[2]\,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \bit_count_reg_n_0_[1]\,
      O => \byte_count[10]_i_17__0_n_0\
    );
\byte_count[10]_i_18__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \byte_count_reg_n_0_[1]\,
      O => \byte_count[10]_i_18__0_n_0\
    );
\byte_count[10]_i_19__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \state_reg_n_0_[1]\,
      O => \byte_count[10]_i_19__0_n_0\
    );
\byte_count[10]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000EEEEFFEF"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \byte_count[10]_i_3__0_n_0\,
      I2 => \state_reg_n_0_[1]\,
      I3 => \byte_count[10]_i_4__0_n_0\,
      I4 => \byte_count[10]_i_5__0_n_0\,
      I5 => \byte_count[10]_i_6__0_n_0\,
      O => byte_count0
    );
\byte_count[10]_i_20__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000000000FE"
    )
        port map (
      I0 => \state_reg_n_0_[1]\,
      I1 => \byte_count[10]_i_23_n_0\,
      I2 => \byte_count[10]_i_24_n_0\,
      I3 => \byte_count[10]_i_25_n_0\,
      I4 => \byte_count[10]_i_26_n_0\,
      I5 => \byte_count[10]_i_27_n_0\,
      O => \byte_count[10]_i_20__0_n_0\
    );
\byte_count[10]_i_21__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A00800080008000"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \byte_count[10]_i_28_n_0\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \state_reg_n_0_[1]\,
      I4 => \byte_count[10]_i_14__0_n_0\,
      I5 => \state[2]_i_6__0_n_0\,
      O => \byte_count[10]_i_21__0_n_0\
    );
\byte_count[10]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => txen_i_3_n_0,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count[10]_i_29_n_0\,
      I4 => \byte_count_reg_n_0_[0]\,
      I5 => \byte_count_reg_n_0_[1]\,
      O => \byte_count[10]_i_22_n_0\
    );
\byte_count[10]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAABAAAB"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \byte_count[4]_i_5_n_0\,
      I2 => \bit_count_reg_n_0_[3]\,
      I3 => \bit_count_reg_n_0_[2]\,
      I4 => \bit_count_reg_n_0_[0]\,
      I5 => \bit_count_reg_n_0_[1]\,
      O => \byte_count[10]_i_23_n_0\
    );
\byte_count[10]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFCAAAAAAA"
    )
        port map (
      I0 => \byte_count[10]_i_29_n_0\,
      I1 => \bit_count[3]_i_7_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[4]\,
      I5 => \bit_count[3]_i_8_n_0\,
      O => \byte_count[10]_i_24_n_0\
    );
\byte_count[10]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FF8000000000"
    )
        port map (
      I0 => \byte_count[10]_i_14__0_n_0\,
      I1 => \bit_count_reg_n_0_[3]\,
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => bit_count223_in,
      I4 => \state_reg_n_0_[1]\,
      I5 => \state_reg_n_0_[0]\,
      O => \byte_count[10]_i_25_n_0\
    );
\byte_count[10]_i_26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"33F3333333B333B3"
    )
        port map (
      I0 => \bit_count0_inferred__0/i__carry__0_n_2\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[1]\,
      I3 => \state_reg_n_0_[0]\,
      I4 => \byte_count[10]_i_14__0_n_0\,
      I5 => \state[2]_i_6__0_n_0\,
      O => \byte_count[10]_i_26_n_0\
    );
\byte_count[10]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF02000000000000"
    )
        port map (
      I0 => \byte_count[10]_i_14__0_n_0\,
      I1 => \bit_count_reg_n_0_[3]\,
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => txen_i_2_n_0,
      I4 => \state_reg_n_0_[0]\,
      I5 => \state_reg_n_0_[1]\,
      O => \byte_count[10]_i_27_n_0\
    );
\byte_count[10]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \bit_count_reg_n_0_[2]\,
      I1 => \bit_count_reg_n_0_[3]\,
      I2 => \byte_count[10]_i_14__0_n_0\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => txen_i_3_n_0,
      O => \byte_count[10]_i_28_n_0\
    );
\byte_count[10]_i_29\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => \bit_count_reg_n_0_[0]\,
      I1 => \bit_count_reg_n_0_[1]\,
      I2 => \bit_count_reg_n_0_[3]\,
      I3 => \bit_count_reg_n_0_[2]\,
      O => \byte_count[10]_i_29_n_0\
    );
\byte_count[10]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF10FF10101010"
    )
        port map (
      I0 => \byte_count[10]_i_7__0_n_0\,
      I1 => \byte_count[10]_i_8__0_n_0\,
      I2 => \byte_count[10]_i_9__0_n_0\,
      I3 => \byte_count[10]_i_10__0_n_0\,
      I4 => \byte_count[10]_i_11__0_n_0\,
      I5 => \byte_count[10]_i_12_n_0\,
      O => byte_count(10)
    );
\byte_count[10]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000022222000"
    )
        port map (
      I0 => \byte_count[10]_i_13__0_n_0\,
      I1 => txen_i_2_n_0,
      I2 => \byte_count[10]_i_14__0_n_0\,
      I3 => \state[2]_i_7__0_n_0\,
      I4 => \byte_count_reg_n_0_[0]\,
      I5 => \byte_count_reg_n_0_[1]\,
      O => \byte_count[10]_i_3__0_n_0\
    );
\byte_count[10]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0A0A0A0B0B000A0"
    )
        port map (
      I0 => \byte_count[10]_i_15__0_n_0\,
      I1 => \byte_count[10]_i_16__0_n_0\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \byte_count[10]_i_17__0_n_0\,
      I4 => \i__carry_i_12_n_0\,
      I5 => txen_i_3_n_0,
      O => \byte_count[10]_i_4__0_n_0\
    );
\byte_count[10]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF0FFF700000000"
    )
        port map (
      I0 => \state[2]_i_7__0_n_0\,
      I1 => \byte_count[10]_i_14__0_n_0\,
      I2 => txen_i_3_n_0,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count[10]_i_18__0_n_0\,
      I5 => \byte_count[10]_i_19__0_n_0\,
      O => \byte_count[10]_i_5__0_n_0\
    );
\byte_count[10]_i_6__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"D"
    )
        port map (
      I0 => eth_rstn,
      I1 => \byte_count[10]_i_20__0_n_0\,
      O => \byte_count[10]_i_6__0_n_0\
    );
\byte_count[10]_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5595555555555555"
    )
        port map (
      I0 => \byte_count_reg_n_0_[10]\,
      I1 => \byte_count_reg_n_0_[7]\,
      I2 => \byte_count_reg_n_0_[6]\,
      I3 => \i__carry_i_10__0_n_0\,
      I4 => \byte_count_reg_n_0_[8]\,
      I5 => \byte_count_reg_n_0_[9]\,
      O => \byte_count[10]_i_7__0_n_0\
    );
\byte_count[10]_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => bit_count223_in,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \bit_count_reg_n_0_[1]\,
      I4 => \bit_count_reg_n_0_[3]\,
      I5 => \bit_count_reg_n_0_[2]\,
      O => \byte_count[10]_i_8__0_n_0\
    );
\byte_count[10]_i_9__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \state_reg_n_0_[1]\,
      O => \byte_count[10]_i_9__0_n_0\
    );
\byte_count[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2222A0FFA2FF0000"
    )
        port map (
      I0 => \byte_count[10]_i_9__0_n_0\,
      I1 => \byte_count[10]_i_8__0_n_0\,
      I2 => \byte_count[4]_i_3_n_0\,
      I3 => \byte_count[10]_i_10__0_n_0\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \byte_count_reg_n_0_[0]\,
      O => byte_count(1)
    );
\byte_count[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAFBFBAAFBAAFBAA"
    )
        port map (
      I0 => \byte_count[2]_i_2_n_0\,
      I1 => \byte_count[10]_i_10__0_n_0\,
      I2 => \byte_count[10]_i_11__0_n_0\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[0]\,
      I5 => \byte_count_reg_n_0_[1]\,
      O => byte_count(2)
    );
\byte_count[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2A8000002AAA00AA"
    )
        port map (
      I0 => \byte_count[10]_i_9__0_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[0]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count[4]_i_3_n_0\,
      I5 => \byte_count[10]_i_8__0_n_0\,
      O => \byte_count[2]_i_2_n_0\
    );
\byte_count[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBAAAAFBFBAAFBAA"
    )
        port map (
      I0 => \byte_count[3]_i_2_n_0\,
      I1 => \byte_count[10]_i_10__0_n_0\,
      I2 => \byte_count[10]_i_11__0_n_0\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count[3]_i_3_n_0\,
      I5 => \byte_count_reg_n_0_[2]\,
      O => byte_count(3)
    );
\byte_count[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A2080000A2882288"
    )
        port map (
      I0 => \byte_count[10]_i_9__0_n_0\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count[3]_i_3_n_0\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count[4]_i_3_n_0\,
      I5 => \byte_count[10]_i_8__0_n_0\,
      O => \byte_count[3]_i_2_n_0\
    );
\byte_count[3]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[0]\,
      O => \byte_count[3]_i_3_n_0\
    );
\byte_count[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFD0FF50505050"
    )
        port map (
      I0 => \byte_count[4]_i_2_n_0\,
      I1 => \byte_count[4]_i_3_n_0\,
      I2 => \byte_count[10]_i_9__0_n_0\,
      I3 => \byte_count[10]_i_10__0_n_0\,
      I4 => \byte_count[10]_i_11__0_n_0\,
      I5 => \byte_count[4]_i_4_n_0\,
      O => byte_count(4)
    );
\byte_count[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EABF"
    )
        port map (
      I0 => \byte_count[10]_i_8__0_n_0\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[4]\,
      O => \byte_count[4]_i_2_n_0\
    );
\byte_count[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \byte_count[4]_i_5_n_0\,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \bit_count_reg_n_0_[1]\,
      I4 => \bit_count_reg_n_0_[3]\,
      I5 => \bit_count_reg_n_0_[2]\,
      O => \byte_count[4]_i_3_n_0\
    );
\byte_count[4]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[4]\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[0]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[3]\,
      O => \byte_count[4]_i_4_n_0\
    );
\byte_count[4]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EAAA"
    )
        port map (
      I0 => \bit_count[3]_i_8_n_0\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[4]\,
      O => \byte_count[4]_i_5_n_0\
    );
\byte_count[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF40FF40404040"
    )
        port map (
      I0 => \byte_count[10]_i_8__0_n_0\,
      I1 => \byte_count[5]_i_2_n_0\,
      I2 => \byte_count[10]_i_9__0_n_0\,
      I3 => \byte_count[10]_i_10__0_n_0\,
      I4 => \byte_count[10]_i_11__0_n_0\,
      I5 => \byte_count[5]_i_3_n_0\,
      O => byte_count(5)
    );
\byte_count[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[5]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[4]\,
      O => \byte_count[5]_i_2_n_0\
    );
\byte_count[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[5]\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \byte_count_reg_n_0_[0]\,
      O => \byte_count[5]_i_3_n_0\
    );
\byte_count[6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF40FF40404040"
    )
        port map (
      I0 => \byte_count[10]_i_8__0_n_0\,
      I1 => \byte_count[6]_i_2_n_0\,
      I2 => \byte_count[10]_i_9__0_n_0\,
      I3 => \byte_count[10]_i_10__0_n_0\,
      I4 => \byte_count[10]_i_11__0_n_0\,
      I5 => \byte_count[6]_i_3_n_0\,
      O => byte_count(6)
    );
\byte_count[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[6]\,
      I1 => \byte_count_reg_n_0_[5]\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[2]\,
      O => \byte_count[6]_i_2_n_0\
    );
\byte_count[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA6AAAAAAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[6]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[4]\,
      I4 => \byte_count_reg_n_0_[5]\,
      I5 => \byte_count[3]_i_3_n_0\,
      O => \byte_count[6]_i_3_n_0\
    );
\byte_count[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF40FF40404040"
    )
        port map (
      I0 => \byte_count[10]_i_8__0_n_0\,
      I1 => \byte_count[7]_i_2_n_0\,
      I2 => \byte_count[10]_i_9__0_n_0\,
      I3 => \byte_count[10]_i_10__0_n_0\,
      I4 => \byte_count[10]_i_11__0_n_0\,
      I5 => \byte_count[7]_i_3_n_0\,
      O => byte_count(7)
    );
\byte_count[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[7]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[4]\,
      I4 => \byte_count_reg_n_0_[5]\,
      I5 => \byte_count_reg_n_0_[6]\,
      O => \byte_count[7]_i_2_n_0\
    );
\byte_count[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA6AAAAAAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[7]\,
      I1 => \byte_count_reg_n_0_[6]\,
      I2 => \byte_count_reg_n_0_[0]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg_n_0_[5]\,
      I5 => rd_enable_fifo0_carry_i_10_n_0,
      O => \byte_count[7]_i_3_n_0\
    );
\byte_count[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF40FF40404040"
    )
        port map (
      I0 => \byte_count[10]_i_8__0_n_0\,
      I1 => \byte_count[8]_i_2_n_0\,
      I2 => \byte_count[10]_i_9__0_n_0\,
      I3 => \byte_count[10]_i_10__0_n_0\,
      I4 => \byte_count[10]_i_11__0_n_0\,
      I5 => \byte_count[8]_i_3_n_0\,
      O => byte_count(8)
    );
\byte_count[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[8]\,
      I1 => \i__carry_i_12_n_0\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_count_reg_n_0_[5]\,
      I4 => \byte_count_reg_n_0_[6]\,
      I5 => \byte_count_reg_n_0_[7]\,
      O => \byte_count[8]_i_2_n_0\
    );
\byte_count[8]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A6AAAAAAAAAAAAAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[8]\,
      I1 => \byte_count_reg_n_0_[7]\,
      I2 => \i__carry_i_10__0_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg_n_0_[0]\,
      I5 => \byte_count_reg_n_0_[6]\,
      O => \byte_count[8]_i_3_n_0\
    );
\byte_count[9]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF40FF40404040"
    )
        port map (
      I0 => \byte_count[10]_i_8__0_n_0\,
      I1 => \byte_count[9]_i_2_n_0\,
      I2 => \byte_count[10]_i_9__0_n_0\,
      I3 => \byte_count[10]_i_10__0_n_0\,
      I4 => \byte_count[10]_i_11__0_n_0\,
      I5 => \byte_count[9]_i_3_n_0\,
      O => byte_count(9)
    );
\byte_count[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA6AAAAAAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[9]\,
      I1 => \byte_count_reg_n_0_[8]\,
      I2 => \byte_count_reg_n_0_[7]\,
      I3 => \byte_count_reg_n_0_[6]\,
      I4 => \byte_count_reg_n_0_[5]\,
      I5 => rd_enable_fifo0_carry_i_10_n_0,
      O => \byte_count[9]_i_2_n_0\
    );
\byte_count[9]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAA6AAAAAAAAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[9]\,
      I1 => \byte_count_reg_n_0_[8]\,
      I2 => \byte_count_reg_n_0_[6]\,
      I3 => \byte_count[3]_i_3_n_0\,
      I4 => \i__carry_i_10__0_n_0\,
      I5 => \byte_count_reg_n_0_[7]\,
      O => \byte_count[9]_i_3_n_0\
    );
\byte_count_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => byte_count0,
      D => byte_count(0),
      Q => \byte_count_reg_n_0_[0]\,
      R => '0'
    );
\byte_count_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => byte_count0,
      D => byte_count(10),
      Q => \byte_count_reg_n_0_[10]\,
      R => '0'
    );
\byte_count_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => byte_count0,
      D => byte_count(1),
      Q => \byte_count_reg_n_0_[1]\,
      R => '0'
    );
\byte_count_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => byte_count0,
      D => byte_count(2),
      Q => \byte_count_reg_n_0_[2]\,
      R => '0'
    );
\byte_count_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => byte_count0,
      D => byte_count(3),
      Q => \byte_count_reg_n_0_[3]\,
      R => '0'
    );
\byte_count_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => byte_count0,
      D => byte_count(4),
      Q => \byte_count_reg_n_0_[4]\,
      R => '0'
    );
\byte_count_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => byte_count0,
      D => byte_count(5),
      Q => \byte_count_reg_n_0_[5]\,
      R => '0'
    );
\byte_count_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => byte_count0,
      D => byte_count(6),
      Q => \byte_count_reg_n_0_[6]\,
      R => '0'
    );
\byte_count_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => byte_count0,
      D => byte_count(7),
      Q => \byte_count_reg_n_0_[7]\,
      R => '0'
    );
\byte_count_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => byte_count0,
      D => byte_count(8),
      Q => \byte_count_reg_n_0_[8]\,
      R => '0'
    );
\byte_count_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => byte_count0,
      D => byte_count(9),
      Q => \byte_count_reg_n_0_[9]\,
      R => '0'
    );
crc_calculator: entity work.design_1_ethernet_transceiver2_0_0_crc32_parallel
     port map (
      AS(0) => stop_crc,
      CO(0) => bit_count233_in,
      O(2 downto 0) => txd1(4 downto 2),
      Q(3) => \bit_count_reg_n_0_[3]\,
      Q(2) => \bit_count_reg_n_0_[2]\,
      Q(1) => \bit_count_reg_n_0_[1]\,
      Q(0) => \bit_count_reg_n_0_[0]\,
      b_clk100mhz => b_clk100mhz,
      \bit_count_reg[3]\ => crc_calculator_n_1,
      \bit_count_reg[3]_0\ => crc_calculator_n_2,
      eth_txd(1 downto 0) => eth_txd(1 downto 0),
      start_crc => start_crc,
      \state_reg[1]\ => crc_calculator_n_3,
      \state_reg[2]\ => crc_calculator_n_0,
      txd0 => txd0,
      \txd[0]_i_2_0\ => \txd[0]_i_15_n_0\,
      \txd[0]_i_2_1\ => \txd[0]_i_16_n_0\,
      \txd[0]_i_2_2\ => \txd[0]_i_17_n_0\,
      \txd[0]_i_7_0\ => \state_reg_n_0_[0]\,
      \txd[1]_i_3\ => rd_enable_fifo_i_5_n_0,
      \txd[1]_i_3_0\ => \txd[1]_i_15_n_0\,
      \txd_reg[0]\ => \txd[0]_i_3_n_0\,
      \txd_reg[0]_0\ => \txd[0]_i_4_n_0\,
      \txd_reg[0]_1\ => \txd[0]_i_5_n_0\,
      \txd_reg[0]_2\ => \txd[0]_i_6_n_0\,
      \txd_reg[0]_3\ => \state_reg_n_0_[2]\
    );
\data_counter_max[10]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => E(0),
      I1 => tx_done,
      O => udp_checksum
    );
\data_counter_max_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \data_counter_max_reg[10]_0\(8),
      Q => \data_counter_max_reg_n_0_[10]\,
      R => tx_done
    );
\data_counter_max_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \data_counter_max_reg[10]_0\(0),
      Q => \data_counter_max_reg_n_0_[2]\,
      R => tx_done
    );
\data_counter_max_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \data_counter_max_reg[10]_0\(1),
      Q => \data_counter_max_reg_n_0_[3]\,
      R => tx_done
    );
\data_counter_max_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \data_counter_max_reg[10]_0\(2),
      Q => \data_counter_max_reg_n_0_[4]\,
      R => tx_done
    );
\data_counter_max_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \data_counter_max_reg[10]_0\(3),
      Q => \data_counter_max_reg_n_0_[5]\,
      R => tx_done
    );
\data_counter_max_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \data_counter_max_reg[10]_0\(4),
      Q => \data_counter_max_reg_n_0_[6]\,
      R => tx_done
    );
\data_counter_max_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \data_counter_max_reg[10]_0\(5),
      Q => \data_counter_max_reg_n_0_[7]\,
      R => tx_done
    );
\data_counter_max_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \data_counter_max_reg[10]_0\(6),
      Q => \data_counter_max_reg_n_0_[8]\,
      R => tx_done
    );
\data_counter_max_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \data_counter_max_reg[10]_0\(7),
      Q => \data_counter_max_reg_n_0_[9]\,
      R => tx_done
    );
\dest_ip_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(0),
      Q => \dest_ip_reg_n_0_[0]\,
      R => tx_done
    );
\dest_ip_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(10),
      Q => \dest_ip_reg_n_0_[10]\,
      R => tx_done
    );
\dest_ip_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(11),
      Q => \dest_ip_reg_n_0_[11]\,
      R => tx_done
    );
\dest_ip_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(12),
      Q => \dest_ip_reg_n_0_[12]\,
      R => tx_done
    );
\dest_ip_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(13),
      Q => \dest_ip_reg_n_0_[13]\,
      R => tx_done
    );
\dest_ip_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(14),
      Q => \dest_ip_reg_n_0_[14]\,
      R => tx_done
    );
\dest_ip_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(15),
      Q => \dest_ip_reg_n_0_[15]\,
      R => tx_done
    );
\dest_ip_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(16),
      Q => p_0_in0_in(0),
      R => tx_done
    );
\dest_ip_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(17),
      Q => p_0_in0_in(1),
      R => tx_done
    );
\dest_ip_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(18),
      Q => p_0_in0_in(2),
      R => tx_done
    );
\dest_ip_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(19),
      Q => p_0_in0_in(3),
      R => tx_done
    );
\dest_ip_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(1),
      Q => \dest_ip_reg_n_0_[1]\,
      R => tx_done
    );
\dest_ip_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(20),
      Q => p_0_in0_in(4),
      R => tx_done
    );
\dest_ip_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(21),
      Q => p_0_in0_in(5),
      R => tx_done
    );
\dest_ip_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(22),
      Q => p_0_in0_in(6),
      R => tx_done
    );
\dest_ip_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(23),
      Q => p_0_in0_in(7),
      R => tx_done
    );
\dest_ip_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(24),
      Q => p_0_in0_in(8),
      R => tx_done
    );
\dest_ip_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(25),
      Q => p_0_in0_in(9),
      R => tx_done
    );
\dest_ip_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(26),
      Q => p_0_in0_in(10),
      R => tx_done
    );
\dest_ip_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(27),
      Q => p_0_in0_in(11),
      R => tx_done
    );
\dest_ip_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(28),
      Q => p_0_in0_in(12),
      R => tx_done
    );
\dest_ip_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(29),
      Q => p_0_in0_in(13),
      R => tx_done
    );
\dest_ip_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(2),
      Q => \dest_ip_reg_n_0_[2]\,
      R => tx_done
    );
\dest_ip_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(30),
      Q => p_0_in0_in(14),
      R => tx_done
    );
\dest_ip_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(31),
      Q => p_0_in0_in(15),
      R => tx_done
    );
\dest_ip_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(3),
      Q => \dest_ip_reg_n_0_[3]\,
      R => tx_done
    );
\dest_ip_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(4),
      Q => \dest_ip_reg_n_0_[4]\,
      R => tx_done
    );
\dest_ip_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(5),
      Q => \dest_ip_reg_n_0_[5]\,
      R => tx_done
    );
\dest_ip_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(6),
      Q => \dest_ip_reg_n_0_[6]\,
      R => tx_done
    );
\dest_ip_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(7),
      Q => \dest_ip_reg_n_0_[7]\,
      R => tx_done
    );
\dest_ip_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(8),
      Q => \dest_ip_reg_n_0_[8]\,
      R => tx_done
    );
\dest_ip_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_ip_reg[31]_0\(9),
      Q => \dest_ip_reg_n_0_[9]\,
      R => tx_done
    );
\dest_mac_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(0),
      Q => \dest_mac_reg_n_0_[0]\,
      R => tx_done
    );
\dest_mac_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(10),
      Q => \dest_mac_reg_n_0_[10]\,
      R => tx_done
    );
\dest_mac_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(11),
      Q => \dest_mac_reg_n_0_[11]\,
      R => tx_done
    );
\dest_mac_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(12),
      Q => \dest_mac_reg_n_0_[12]\,
      R => tx_done
    );
\dest_mac_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(13),
      Q => \dest_mac_reg_n_0_[13]\,
      R => tx_done
    );
\dest_mac_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(14),
      Q => \dest_mac_reg_n_0_[14]\,
      R => tx_done
    );
\dest_mac_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(15),
      Q => \dest_mac_reg_n_0_[15]\,
      R => tx_done
    );
\dest_mac_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(16),
      Q => \dest_mac_reg_n_0_[16]\,
      R => tx_done
    );
\dest_mac_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(17),
      Q => \dest_mac_reg_n_0_[17]\,
      R => tx_done
    );
\dest_mac_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(18),
      Q => \dest_mac_reg_n_0_[18]\,
      R => tx_done
    );
\dest_mac_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(19),
      Q => \dest_mac_reg_n_0_[19]\,
      R => tx_done
    );
\dest_mac_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(1),
      Q => \dest_mac_reg_n_0_[1]\,
      R => tx_done
    );
\dest_mac_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(20),
      Q => \dest_mac_reg_n_0_[20]\,
      R => tx_done
    );
\dest_mac_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(21),
      Q => \dest_mac_reg_n_0_[21]\,
      R => tx_done
    );
\dest_mac_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(22),
      Q => \dest_mac_reg_n_0_[22]\,
      R => tx_done
    );
\dest_mac_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(23),
      Q => \dest_mac_reg_n_0_[23]\,
      R => tx_done
    );
\dest_mac_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(24),
      Q => \dest_mac_reg_n_0_[24]\,
      R => tx_done
    );
\dest_mac_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(25),
      Q => \dest_mac_reg_n_0_[25]\,
      R => tx_done
    );
\dest_mac_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(26),
      Q => \dest_mac_reg_n_0_[26]\,
      R => tx_done
    );
\dest_mac_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(27),
      Q => \dest_mac_reg_n_0_[27]\,
      R => tx_done
    );
\dest_mac_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(28),
      Q => \dest_mac_reg_n_0_[28]\,
      R => tx_done
    );
\dest_mac_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(29),
      Q => \dest_mac_reg_n_0_[29]\,
      R => tx_done
    );
\dest_mac_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(2),
      Q => \dest_mac_reg_n_0_[2]\,
      R => tx_done
    );
\dest_mac_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(30),
      Q => \dest_mac_reg_n_0_[30]\,
      R => tx_done
    );
\dest_mac_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(31),
      Q => \dest_mac_reg_n_0_[31]\,
      R => tx_done
    );
\dest_mac_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(32),
      Q => \dest_mac_reg_n_0_[32]\,
      R => tx_done
    );
\dest_mac_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(33),
      Q => \dest_mac_reg_n_0_[33]\,
      R => tx_done
    );
\dest_mac_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(34),
      Q => \dest_mac_reg_n_0_[34]\,
      R => tx_done
    );
\dest_mac_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(35),
      Q => \dest_mac_reg_n_0_[35]\,
      R => tx_done
    );
\dest_mac_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(36),
      Q => \dest_mac_reg_n_0_[36]\,
      R => tx_done
    );
\dest_mac_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(37),
      Q => \dest_mac_reg_n_0_[37]\,
      R => tx_done
    );
\dest_mac_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(38),
      Q => \dest_mac_reg_n_0_[38]\,
      R => tx_done
    );
\dest_mac_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(39),
      Q => \dest_mac_reg_n_0_[39]\,
      R => tx_done
    );
\dest_mac_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(3),
      Q => \dest_mac_reg_n_0_[3]\,
      R => tx_done
    );
\dest_mac_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(40),
      Q => \dest_mac_reg_n_0_[40]\,
      R => tx_done
    );
\dest_mac_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(41),
      Q => \dest_mac_reg_n_0_[41]\,
      R => tx_done
    );
\dest_mac_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(42),
      Q => \dest_mac_reg_n_0_[42]\,
      R => tx_done
    );
\dest_mac_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(43),
      Q => \dest_mac_reg_n_0_[43]\,
      R => tx_done
    );
\dest_mac_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(44),
      Q => \dest_mac_reg_n_0_[44]\,
      R => tx_done
    );
\dest_mac_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(45),
      Q => \dest_mac_reg_n_0_[45]\,
      R => tx_done
    );
\dest_mac_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(46),
      Q => \dest_mac_reg_n_0_[46]\,
      R => tx_done
    );
\dest_mac_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(47),
      Q => \dest_mac_reg_n_0_[47]\,
      R => tx_done
    );
\dest_mac_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(4),
      Q => \dest_mac_reg_n_0_[4]\,
      R => tx_done
    );
\dest_mac_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(5),
      Q => \dest_mac_reg_n_0_[5]\,
      R => tx_done
    );
\dest_mac_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(6),
      Q => \dest_mac_reg_n_0_[6]\,
      R => tx_done
    );
\dest_mac_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(7),
      Q => \dest_mac_reg_n_0_[7]\,
      R => tx_done
    );
\dest_mac_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(8),
      Q => \dest_mac_reg_n_0_[8]\,
      R => tx_done
    );
\dest_mac_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_mac_reg[47]_0\(9),
      Q => \dest_mac_reg_n_0_[9]\,
      R => tx_done
    );
\dest_port_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(0),
      Q => \dest_port_reg_n_0_[0]\,
      R => tx_done
    );
\dest_port_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(10),
      Q => \dest_port_reg_n_0_[10]\,
      R => tx_done
    );
\dest_port_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(11),
      Q => \dest_port_reg_n_0_[11]\,
      R => tx_done
    );
\dest_port_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(12),
      Q => \dest_port_reg_n_0_[12]\,
      R => tx_done
    );
\dest_port_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(13),
      Q => \dest_port_reg_n_0_[13]\,
      R => tx_done
    );
\dest_port_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(14),
      Q => \dest_port_reg_n_0_[14]\,
      R => tx_done
    );
\dest_port_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(15),
      Q => \dest_port_reg_n_0_[15]\,
      R => tx_done
    );
\dest_port_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(1),
      Q => \dest_port_reg_n_0_[1]\,
      R => tx_done
    );
\dest_port_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(2),
      Q => \dest_port_reg_n_0_[2]\,
      R => tx_done
    );
\dest_port_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(3),
      Q => \dest_port_reg_n_0_[3]\,
      R => tx_done
    );
\dest_port_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(4),
      Q => \dest_port_reg_n_0_[4]\,
      R => tx_done
    );
\dest_port_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(5),
      Q => \dest_port_reg_n_0_[5]\,
      R => tx_done
    );
\dest_port_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(6),
      Q => \dest_port_reg_n_0_[6]\,
      R => tx_done
    );
\dest_port_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(7),
      Q => \dest_port_reg_n_0_[7]\,
      R => tx_done
    );
\dest_port_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(8),
      Q => \dest_port_reg_n_0_[8]\,
      R => tx_done
    );
\dest_port_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => \dest_port_reg[15]_0\(9),
      Q => \dest_port_reg_n_0_[9]\,
      R => tx_done
    );
eth_protocol_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000BAAA"
    )
        port map (
      I0 => id_counter121_out,
      I1 => eth_protocol_reg_0,
      I2 => eth_protocol_reg_1,
      I3 => E(0),
      I4 => tx_done,
      O => eth_protocol_i_1_n_0
    );
eth_protocol_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => eth_protocol_i_1_n_0,
      Q => id_counter121_out,
      R => '0'
    );
\eth_type_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \byte12[7]_i_1_n_0\,
      Q => eth_type(11),
      R => '0'
    );
\eth_type_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => '0',
      Q => eth_type(1),
      S => eth_type118_out
    );
\i__carry__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"222B"
    )
        port map (
      I0 => \byte_count_reg_n_0_[10]\,
      I1 => \data_counter_max_reg_n_0_[10]\,
      I2 => \i__carry__0_i_3_n_0\,
      I3 => \data_counter_max_reg_n_0_[9]\,
      O => \i__carry__0_i_1_n_0\
    );
\i__carry__0_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF6AAA"
    )
        port map (
      I0 => \byte_count_reg_n_0_[10]\,
      I1 => \i__carry__0_i_5_n_0\,
      I2 => \byte_count_reg_n_0_[8]\,
      I3 => \byte_count_reg_n_0_[9]\,
      I4 => \i__carry_i_9__0_n_0\,
      O => \i__carry__0_i_1__0_n_0\
    );
\i__carry__0_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010001"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[4]\,
      I1 => \zero_counter_reg_n_0_[2]\,
      I2 => \zero_counter_reg_n_0_[1]\,
      I3 => \zero_counter_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[9]\,
      I5 => \byte_count_reg_n_0_[8]\,
      O => \i__carry__0_i_1__1_n_0\
    );
\i__carry__0_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A856"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[10]\,
      I1 => \i__carry__0_i_3_n_0\,
      I2 => \data_counter_max_reg_n_0_[9]\,
      I3 => \byte_count_reg_n_0_[10]\,
      O => \i__carry__0_i_2_n_0\
    );
\i__carry__0_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1554"
    )
        port map (
      I0 => \i__carry_i_9__0_n_0\,
      I1 => \byte_count_reg_n_0_[8]\,
      I2 => \i__carry__0_i_5_n_0\,
      I3 => \byte_count_reg_n_0_[9]\,
      O => \i__carry__0_i_2__0_n_0\
    );
\i__carry__0_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55555554"
    )
        port map (
      I0 => \byte_count_reg_n_0_[10]\,
      I1 => \zero_counter_reg_n_0_[4]\,
      I2 => \zero_counter_reg_n_0_[2]\,
      I3 => \zero_counter_reg_n_0_[1]\,
      I4 => \zero_counter_reg_n_0_[3]\,
      O => \i__carry__0_i_2__1_n_0\
    );
\i__carry__0_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[5]\,
      I1 => \data_counter_max_reg_n_0_[8]\,
      I2 => \data_counter_max_reg_n_0_[6]\,
      I3 => \data_counter_max_reg_n_0_[7]\,
      I4 => \i__carry_i_11_n_0\,
      O => \i__carry__0_i_3_n_0\
    );
\i__carry__0_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000100000000FFFE"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[3]\,
      I1 => \zero_counter_reg_n_0_[1]\,
      I2 => \zero_counter_reg_n_0_[2]\,
      I3 => \zero_counter_reg_n_0_[4]\,
      I4 => \byte_count_reg_n_0_[8]\,
      I5 => \byte_count_reg_n_0_[9]\,
      O => \i__carry__0_i_3__0_n_0\
    );
\i__carry__0_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40001555"
    )
        port map (
      I0 => \i__carry_i_9__0_n_0\,
      I1 => \byte_count_reg_n_0_[9]\,
      I2 => \byte_count_reg_n_0_[8]\,
      I3 => \i__carry__0_i_5_n_0\,
      I4 => \byte_count_reg_n_0_[10]\,
      O => \i__carry__0_i_3__1_n_0\
    );
\i__carry__0_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2881"
    )
        port map (
      I0 => \byte_count_reg_n_0_[9]\,
      I1 => \byte_count_reg_n_0_[8]\,
      I2 => \i__carry__0_i_5_n_0\,
      I3 => \i__carry_i_9__0_n_0\,
      O => \i__carry__0_i_4_n_0\
    );
\i__carry__0_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000800000000000"
    )
        port map (
      I0 => \byte_count_reg_n_0_[6]\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[5]\,
      I4 => rd_enable_fifo0_carry_i_10_n_0,
      I5 => \byte_count_reg_n_0_[7]\,
      O => \i__carry__0_i_5_n_0\
    );
\i__carry_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88E8"
    )
        port map (
      I0 => \byte_count_reg_n_0_[9]\,
      I1 => \i__carry_i_9_n_0\,
      I2 => \byte_count_reg_n_0_[8]\,
      I3 => \i__carry_i_10_n_0\,
      O => \i__carry_i_1_n_0\
    );
\i__carry_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAA9"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[8]\,
      I1 => \data_counter_max_reg_n_0_[7]\,
      I2 => \data_counter_max_reg_n_0_[6]\,
      I3 => \i__carry_i_11_n_0\,
      I4 => \data_counter_max_reg_n_0_[5]\,
      O => \i__carry_i_10_n_0\
    );
\i__carry_i_10__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_count_reg_n_0_[5]\,
      O => \i__carry_i_10__0_n_0\
    );
\i__carry_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[4]\,
      I1 => \data_counter_max_reg_n_0_[3]\,
      I2 => \data_counter_max_reg_n_0_[2]\,
      O => \i__carry_i_11_n_0\
    );
\i__carry_i_11__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA9"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[4]\,
      I1 => \zero_counter_reg_n_0_[3]\,
      I2 => \zero_counter_reg_n_0_[1]\,
      I3 => \zero_counter_reg_n_0_[2]\,
      O => \i__carry_i_11__0_n_0\
    );
\i__carry_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[3]\,
      O => \i__carry_i_12_n_0\
    );
\i__carry_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      O => \i__carry_i_1__0_n_0\
    );
\i__carry_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100010001"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[4]\,
      I1 => \zero_counter_reg_n_0_[2]\,
      I2 => \zero_counter_reg_n_0_[1]\,
      I3 => \zero_counter_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[7]\,
      I5 => \byte_count_reg_n_0_[6]\,
      O => \i__carry_i_1__1_n_0\
    );
\i__carry_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5155555545444444"
    )
        port map (
      I0 => \i__carry_i_9__0_n_0\,
      I1 => \byte_count_reg_n_0_[6]\,
      I2 => \i__carry_i_10__0_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg_n_0_[0]\,
      I5 => \byte_count_reg_n_0_[7]\,
      O => \i__carry_i_1__2_n_0\
    );
\i__carry_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"222ABBBC0002AAA8"
    )
        port map (
      I0 => \byte_count_reg_n_0_[7]\,
      I1 => \data_counter_max_reg_n_0_[6]\,
      I2 => \i__carry_i_11_n_0\,
      I3 => \data_counter_max_reg_n_0_[5]\,
      I4 => \data_counter_max_reg_n_0_[7]\,
      I5 => \byte_count_reg_n_0_[6]\,
      O => \i__carry_i_2_n_0\
    );
\i__carry_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F44114F4F444F44"
    )
        port map (
      I0 => \i__carry_i_9__0_n_0\,
      I1 => \byte_count_reg_n_0_[5]\,
      I2 => \i__carry_i_11__0_n_0\,
      I3 => \byte_count_reg_n_0_[4]\,
      I4 => \byte_count[3]_i_3_n_0\,
      I5 => \i__carry_i_12_n_0\,
      O => \i__carry_i_2__0_n_0\
    );
\i__carry_i_2__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \byte_count_reg_n_0_[0]\,
      O => \i__carry_i_2__1_n_0\
    );
\i__carry_i_2__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000144444443"
    )
        port map (
      I0 => \byte_count_reg_n_0_[5]\,
      I1 => \zero_counter_reg_n_0_[4]\,
      I2 => \zero_counter_reg_n_0_[2]\,
      I3 => \zero_counter_reg_n_0_[1]\,
      I4 => \zero_counter_reg_n_0_[3]\,
      I5 => \byte_count_reg_n_0_[4]\,
      O => \i__carry_i_2__2_n_0\
    );
\i__carry_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"222ABBBC0002AAA8"
    )
        port map (
      I0 => \byte_count_reg_n_0_[5]\,
      I1 => \data_counter_max_reg_n_0_[4]\,
      I2 => \data_counter_max_reg_n_0_[3]\,
      I3 => \data_counter_max_reg_n_0_[2]\,
      I4 => \data_counter_max_reg_n_0_[5]\,
      I5 => \byte_count_reg_n_0_[4]\,
      O => \i__carry_i_3_n_0\
    );
\i__carry_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7E1E007E06001E06"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[1]\,
      I1 => \zero_counter_reg_n_0_[2]\,
      I2 => \zero_counter_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count[3]_i_3_n_0\,
      I5 => \byte_count_reg_n_0_[3]\,
      O => \i__carry_i_3__0_n_0\
    );
\i__carry_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"5401D543"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \zero_counter_reg_n_0_[1]\,
      I2 => \zero_counter_reg_n_0_[2]\,
      I3 => \zero_counter_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[2]\,
      O => \i__carry_i_3__1_n_0\
    );
\i__carry_i_3__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"56"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \bit_count_reg_n_0_[3]\,
      I2 => \bit_count_reg_n_0_[2]\,
      O => \i__carry_i_3__2_n_0\
    );
\i__carry_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B828"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \data_counter_max_reg_n_0_[3]\,
      I2 => \data_counter_max_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[2]\,
      O => \i__carry_i_4_n_0\
    );
\i__carry_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \byte_count_reg_n_0_[0]\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \zero_counter_reg_n_0_[1]\,
      O => \i__carry_i_4__0_n_0\
    );
\i__carry_i_4__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \byte_count_reg_n_0_[1]\,
      O => \i__carry_i_4__1_n_0\
    );
\i__carry_i_4__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \bit_count_reg_n_0_[3]\,
      I2 => \bit_count_reg_n_0_[2]\,
      O => \i__carry_i_4__2_n_0\
    );
\i__carry_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6006"
    )
        port map (
      I0 => \i__carry_i_9_n_0\,
      I1 => \byte_count_reg_n_0_[9]\,
      I2 => \i__carry_i_10_n_0\,
      I3 => \byte_count_reg_n_0_[8]\,
      O => \i__carry_i_5_n_0\
    );
\i__carry_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8288888818111111"
    )
        port map (
      I0 => \byte_count_reg_n_0_[7]\,
      I1 => \byte_count_reg_n_0_[6]\,
      I2 => \i__carry_i_10__0_n_0\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg_n_0_[0]\,
      I5 => \i__carry_i_9__0_n_0\,
      O => \i__carry_i_5__0_n_0\
    );
\i__carry_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000100000000FFFE"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[3]\,
      I1 => \zero_counter_reg_n_0_[1]\,
      I2 => \zero_counter_reg_n_0_[2]\,
      I3 => \zero_counter_reg_n_0_[4]\,
      I4 => \byte_count_reg_n_0_[6]\,
      I5 => \byte_count_reg_n_0_[7]\,
      O => \i__carry_i_5__1_n_0\
    );
\i__carry_i_5__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \byte_count_reg_n_0_[0]\,
      I1 => \bit_count_reg_n_0_[2]\,
      O => \i__carry_i_5__2_n_0\
    );
\i__carry_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9090900609090990"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[7]\,
      I1 => \byte_count_reg_n_0_[7]\,
      I2 => \data_counter_max_reg_n_0_[6]\,
      I3 => \i__carry_i_11_n_0\,
      I4 => \data_counter_max_reg_n_0_[5]\,
      I5 => \byte_count_reg_n_0_[6]\,
      O => \i__carry_i_6_n_0\
    );
\i__carry_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009909009600909"
    )
        port map (
      I0 => \byte_count_reg_n_0_[5]\,
      I1 => \i__carry_i_9__0_n_0\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_count[3]_i_3_n_0\,
      I4 => \i__carry_i_12_n_0\,
      I5 => \i__carry_i_11__0_n_0\,
      O => \i__carry_i_6__0_n_0\
    );
\i__carry_i_6__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4444444211111114"
    )
        port map (
      I0 => \byte_count_reg_n_0_[5]\,
      I1 => \zero_counter_reg_n_0_[4]\,
      I2 => \zero_counter_reg_n_0_[3]\,
      I3 => \zero_counter_reg_n_0_[1]\,
      I4 => \zero_counter_reg_n_0_[2]\,
      I5 => \byte_count_reg_n_0_[4]\,
      O => \i__carry_i_6__1_n_0\
    );
\i__carry_i_6__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \bit_count_reg_n_0_[1]\,
      O => \i__carry_i_6__2_n_0\
    );
\i__carry_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9090900609090990"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[5]\,
      I1 => \byte_count_reg_n_0_[5]\,
      I2 => \data_counter_max_reg_n_0_[4]\,
      I3 => \data_counter_max_reg_n_0_[3]\,
      I4 => \data_counter_max_reg_n_0_[2]\,
      I5 => \byte_count_reg_n_0_[4]\,
      O => \i__carry_i_7_n_0\
    );
\i__carry_i_7__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009096009606006"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \zero_counter_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count[3]_i_3_n_0\,
      I4 => \zero_counter_reg_n_0_[1]\,
      I5 => \zero_counter_reg_n_0_[2]\,
      O => \i__carry_i_7__0_n_0\
    );
\i__carry_i_7__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"90060990"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[3]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \zero_counter_reg_n_0_[1]\,
      I3 => \zero_counter_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[2]\,
      O => \i__carry_i_7__1_n_0\
    );
\i__carry_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0690"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[3]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \data_counter_max_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[2]\,
      O => \i__carry_i_8_n_0\
    );
\i__carry_i_8__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[0]\,
      O => \i__carry_i_8__0_n_0\
    );
\i__carry_i_8__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[0]\,
      O => \i__carry_i_8__1_n_0\
    );
\i__carry_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555555555556"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[9]\,
      I1 => \i__carry_i_11_n_0\,
      I2 => \data_counter_max_reg_n_0_[7]\,
      I3 => \data_counter_max_reg_n_0_[6]\,
      I4 => \data_counter_max_reg_n_0_[8]\,
      I5 => \data_counter_max_reg_n_0_[5]\,
      O => \i__carry_i_9_n_0\
    );
\i__carry_i_9__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \zero_counter_reg_n_0_[3]\,
      I1 => \zero_counter_reg_n_0_[1]\,
      I2 => \zero_counter_reg_n_0_[2]\,
      I3 => \zero_counter_reg_n_0_[4]\,
      O => \i__carry_i_9__0_n_0\
    );
\id_counter[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \id_counter__0\(0),
      O => \id_counter[0]_i_1_n_0\
    );
\id_counter[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => id_counter121_out,
      I1 => \state_reg_n_0_[1]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \state_reg_n_0_[2]\,
      I4 => txen_i_2_n_0,
      O => \id_counter[15]_i_1_n_0\
    );
\id_counter_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => \id_counter[0]_i_1_n_0\,
      Q => \id_counter__0\(0)
    );
\id_counter_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(10),
      Q => \id_counter__0\(10)
    );
\id_counter_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(11),
      Q => \id_counter__0\(11)
    );
\id_counter_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(12),
      Q => \id_counter__0\(12)
    );
\id_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \id_counter_reg[8]_i_1_n_0\,
      CO(3) => \id_counter_reg[12]_i_1_n_0\,
      CO(2) => \id_counter_reg[12]_i_1_n_1\,
      CO(1) => \id_counter_reg[12]_i_1_n_2\,
      CO(0) => \id_counter_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => plusOp(12 downto 9),
      S(3 downto 0) => \id_counter__0\(12 downto 9)
    );
\id_counter_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(13),
      Q => \id_counter__0\(13)
    );
\id_counter_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(14),
      Q => \id_counter__0\(14)
    );
\id_counter_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(15),
      Q => \id_counter__0\(15)
    );
\id_counter_reg[15]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \id_counter_reg[12]_i_1_n_0\,
      CO(3 downto 2) => \NLW_id_counter_reg[15]_i_2_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \id_counter_reg[15]_i_2_n_2\,
      CO(0) => \id_counter_reg[15]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_id_counter_reg[15]_i_2_O_UNCONNECTED\(3),
      O(2 downto 0) => plusOp(15 downto 13),
      S(3) => '0',
      S(2 downto 0) => \id_counter__0\(15 downto 13)
    );
\id_counter_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(1),
      Q => \id_counter__0\(1)
    );
\id_counter_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(2),
      Q => \id_counter__0\(2)
    );
\id_counter_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(3),
      Q => \id_counter__0\(3)
    );
\id_counter_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(4),
      Q => \id_counter__0\(4)
    );
\id_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \id_counter_reg[4]_i_1_n_0\,
      CO(2) => \id_counter_reg[4]_i_1_n_1\,
      CO(1) => \id_counter_reg[4]_i_1_n_2\,
      CO(0) => \id_counter_reg[4]_i_1_n_3\,
      CYINIT => \id_counter__0\(0),
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => plusOp(4 downto 1),
      S(3 downto 0) => \id_counter__0\(4 downto 1)
    );
\id_counter_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(5),
      Q => \id_counter__0\(5)
    );
\id_counter_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(6),
      Q => \id_counter__0\(6)
    );
\id_counter_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(7),
      Q => \id_counter__0\(7)
    );
\id_counter_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(8),
      Q => \id_counter__0\(8)
    );
\id_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \id_counter_reg[4]_i_1_n_0\,
      CO(3) => \id_counter_reg[8]_i_1_n_0\,
      CO(2) => \id_counter_reg[8]_i_1_n_1\,
      CO(1) => \id_counter_reg[8]_i_1_n_2\,
      CO(0) => \id_counter_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => plusOp(8 downto 5),
      S(3 downto 0) => \id_counter__0\(8 downto 5)
    );
\id_counter_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \id_counter[15]_i_1_n_0\,
      CLR => \state_reg[0]_0\,
      D => plusOp(9),
      Q => \id_counter__0\(9)
    );
ip_header_calc_done_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E000"
    )
        port map (
      I0 => ip_header_checksum,
      I1 => ip_header_calc_done,
      I2 => id_counter121_out,
      I3 => tx_ready,
      O => ip_header_calc_done_i_1_n_0
    );
ip_header_calc_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => ip_header_calc_done_i_1_n_0,
      Q => ip_header_calc_done,
      R => '0'
    );
\ip_header_checksum[15]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => ip_header_checksum,
      I1 => ip_header_calc_done,
      O => \ip_header_checksum[15]_i_1__0_n_0\
    );
\ip_header_checksum_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(0),
      Q => \ip_header_checksum_reg_n_0_[0]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(10),
      Q => \ip_header_checksum_reg_n_0_[10]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(11),
      Q => \ip_header_checksum_reg_n_0_[11]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(12),
      Q => \ip_header_checksum_reg_n_0_[12]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(13),
      Q => \ip_header_checksum_reg_n_0_[13]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(14),
      Q => \ip_header_checksum_reg_n_0_[14]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(15),
      Q => \ip_header_checksum_reg_n_0_[15]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(1),
      Q => \ip_header_checksum_reg_n_0_[1]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(2),
      Q => \ip_header_checksum_reg_n_0_[2]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(3),
      Q => \ip_header_checksum_reg_n_0_[3]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(4),
      Q => \ip_header_checksum_reg_n_0_[4]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(5),
      Q => \ip_header_checksum_reg_n_0_[5]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(6),
      Q => \ip_header_checksum_reg_n_0_[6]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(7),
      Q => \ip_header_checksum_reg_n_0_[7]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(8),
      Q => \ip_header_checksum_reg_n_0_[8]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_header_checksum_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \ip_header_checksum[15]_i_1__0_n_0\,
      D => \temp_iphc2__0\(9),
      Q => \ip_header_checksum_reg_n_0_[9]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\ip_total_length[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => Q(2),
      O => \ip_total_length[4]_i_2_n_0\
    );
\ip_total_length[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => Q(0),
      O => \ip_total_length[4]_i_3_n_0\
    );
\ip_total_length_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => E(0),
      D => \ip_total_length_reg[12]_i_1_n_6\,
      Q => p_1_in(2),
      R => tx_done
    );
\ip_total_length_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => E(0),
      D => \ip_total_length_reg[12]_i_1_n_5\,
      Q => p_1_in(3),
      R => tx_done
    );
\ip_total_length_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => E(0),
      D => \ip_total_length_reg[12]_i_1_n_4\,
      Q => p_1_in(4),
      R => tx_done
    );
\ip_total_length_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_total_length_reg[8]_i_1_n_0\,
      CO(3) => \ip_total_length_reg[12]_i_1_n_0\,
      CO(2) => \ip_total_length_reg[12]_i_1_n_1\,
      CO(1) => \ip_total_length_reg[12]_i_1_n_2\,
      CO(0) => \ip_total_length_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \ip_total_length_reg[12]_i_1_n_4\,
      O(2) => \ip_total_length_reg[12]_i_1_n_5\,
      O(1) => \ip_total_length_reg[12]_i_1_n_6\,
      O(0) => \ip_total_length_reg[12]_i_1_n_7\,
      S(3 downto 0) => Q(10 downto 7)
    );
\ip_total_length_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => E(0),
      D => \ip_total_length_reg[15]_i_1_n_7\,
      Q => p_1_in(5),
      R => tx_done
    );
\ip_total_length_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => E(0),
      D => \ip_total_length_reg[15]_i_1_n_6\,
      Q => p_1_in(6),
      R => tx_done
    );
\ip_total_length_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => E(0),
      D => \ip_total_length_reg[15]_i_1_n_5\,
      Q => p_1_in(7),
      R => tx_done
    );
\ip_total_length_reg[15]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_total_length_reg[12]_i_1_n_0\,
      CO(3 downto 2) => \NLW_ip_total_length_reg[15]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \ip_total_length_reg[15]_i_1_n_2\,
      CO(0) => \ip_total_length_reg[15]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_ip_total_length_reg[15]_i_1_O_UNCONNECTED\(3),
      O(2) => \ip_total_length_reg[15]_i_1_n_5\,
      O(1) => \ip_total_length_reg[15]_i_1_n_6\,
      O(0) => \ip_total_length_reg[15]_i_1_n_7\,
      S(3) => '0',
      S(2 downto 0) => Q(13 downto 11)
    );
\ip_total_length_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => E(0),
      D => \ip_total_length_reg[4]_i_1_n_6\,
      Q => \ip_total_length_reg_n_0_[2]\,
      R => tx_done
    );
\ip_total_length_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => E(0),
      D => \ip_total_length_reg[4]_i_1_n_5\,
      Q => \ip_total_length_reg_n_0_[3]\,
      R => tx_done
    );
\ip_total_length_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => E(0),
      D => \ip_total_length_reg[4]_i_1_n_4\,
      Q => \ip_total_length_reg_n_0_[4]\,
      R => tx_done
    );
\ip_total_length_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \ip_total_length_reg[4]_i_1_n_0\,
      CO(2) => \ip_total_length_reg[4]_i_1_n_1\,
      CO(1) => \ip_total_length_reg[4]_i_1_n_2\,
      CO(0) => \ip_total_length_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => Q(2),
      DI(2) => '0',
      DI(1) => Q(0),
      DI(0) => '0',
      O(3) => \ip_total_length_reg[4]_i_1_n_4\,
      O(2) => \ip_total_length_reg[4]_i_1_n_5\,
      O(1) => \ip_total_length_reg[4]_i_1_n_6\,
      O(0) => \NLW_ip_total_length_reg[4]_i_1_O_UNCONNECTED\(0),
      S(3) => \ip_total_length[4]_i_2_n_0\,
      S(2) => Q(1),
      S(1) => \ip_total_length[4]_i_3_n_0\,
      S(0) => '0'
    );
\ip_total_length_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => E(0),
      D => \ip_total_length_reg[8]_i_1_n_7\,
      Q => \ip_total_length_reg_n_0_[5]\,
      R => tx_done
    );
\ip_total_length_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => E(0),
      D => \ip_total_length_reg[8]_i_1_n_6\,
      Q => \ip_total_length_reg_n_0_[6]\,
      R => tx_done
    );
\ip_total_length_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => E(0),
      D => \ip_total_length_reg[8]_i_1_n_5\,
      Q => \ip_total_length_reg_n_0_[7]\,
      R => tx_done
    );
\ip_total_length_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => E(0),
      D => \ip_total_length_reg[8]_i_1_n_4\,
      Q => p_1_in(0),
      R => tx_done
    );
\ip_total_length_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \ip_total_length_reg[4]_i_1_n_0\,
      CO(3) => \ip_total_length_reg[8]_i_1_n_0\,
      CO(2) => \ip_total_length_reg[8]_i_1_n_1\,
      CO(1) => \ip_total_length_reg[8]_i_1_n_2\,
      CO(0) => \ip_total_length_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \ip_total_length_reg[8]_i_1_n_4\,
      O(2) => \ip_total_length_reg[8]_i_1_n_5\,
      O(1) => \ip_total_length_reg[8]_i_1_n_6\,
      O(0) => \ip_total_length_reg[8]_i_1_n_7\,
      S(3 downto 0) => Q(6 downto 3)
    );
\ip_total_length_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => E(0),
      D => \ip_total_length_reg[12]_i_1_n_7\,
      Q => p_1_in(1),
      R => tx_done
    );
is_idle_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \state_reg_n_0_[1]\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      O => is_idle_i_1_n_0
    );
is_idle_reg: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => is_idle_i_1_n_0,
      Q => is_idle,
      R => '0'
    );
rd_enable_fifo0_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => rd_enable_fifo0_carry_n_0,
      CO(2) => rd_enable_fifo0_carry_n_1,
      CO(1) => rd_enable_fifo0_carry_n_2,
      CO(0) => rd_enable_fifo0_carry_n_3,
      CYINIT => '1',
      DI(3) => rd_enable_fifo0_carry_i_1_n_0,
      DI(2) => rd_enable_fifo0_carry_i_2_n_0,
      DI(1) => rd_enable_fifo0_carry_i_3_n_0,
      DI(0) => rd_enable_fifo0_carry_i_4_n_0,
      O(3 downto 0) => NLW_rd_enable_fifo0_carry_O_UNCONNECTED(3 downto 0),
      S(3) => rd_enable_fifo0_carry_i_5_n_0,
      S(2) => rd_enable_fifo0_carry_i_6_n_0,
      S(1) => rd_enable_fifo0_carry_i_7_n_0,
      S(0) => rd_enable_fifo0_carry_i_8_n_0
    );
\rd_enable_fifo0_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => rd_enable_fifo0_carry_n_0,
      CO(3 downto 2) => \NLW_rd_enable_fifo0_carry__0_CO_UNCONNECTED\(3 downto 2),
      CO(1) => rd_enable_fifo0,
      CO(0) => \rd_enable_fifo0_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \rd_enable_fifo0_carry__0_i_1_n_0\,
      DI(0) => \rd_enable_fifo0_carry__0_i_2_n_0\,
      O(3 downto 0) => \NLW_rd_enable_fifo0_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 2) => B"00",
      S(1) => \rd_enable_fifo0_carry__0_i_3_n_0\,
      S(0) => \rd_enable_fifo0_carry__0_i_4_n_0\
    );
\rd_enable_fifo0_carry__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E000"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[9]\,
      I1 => \i__carry__0_i_3_n_0\,
      I2 => \data_counter_max_reg_n_0_[10]\,
      I3 => \byte_count[10]_i_7__0_n_0\,
      O => \rd_enable_fifo0_carry__0_i_1_n_0\
    );
\rd_enable_fifo0_carry__0_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"C1574015"
    )
        port map (
      I0 => \i__carry_i_9_n_0\,
      I1 => \rd_enable_fifo0_carry__0_i_5_n_0\,
      I2 => \byte_count_reg_n_0_[8]\,
      I3 => \byte_count_reg_n_0_[9]\,
      I4 => \i__carry_i_10_n_0\,
      O => \rd_enable_fifo0_carry__0_i_2_n_0\
    );
\rd_enable_fifo0_carry__0_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6668"
    )
        port map (
      I0 => \byte_count[10]_i_7__0_n_0\,
      I1 => \data_counter_max_reg_n_0_[10]\,
      I2 => \i__carry__0_i_3_n_0\,
      I3 => \data_counter_max_reg_n_0_[9]\,
      O => \rd_enable_fifo0_carry__0_i_3_n_0\
    );
\rd_enable_fifo0_carry__0_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"06609006"
    )
        port map (
      I0 => \byte_count_reg_n_0_[9]\,
      I1 => \i__carry_i_9_n_0\,
      I2 => \byte_count_reg_n_0_[8]\,
      I3 => \rd_enable_fifo0_carry__0_i_5_n_0\,
      I4 => \i__carry_i_10_n_0\,
      O => \rd_enable_fifo0_carry__0_i_4_n_0\
    );
\rd_enable_fifo0_carry__0_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \byte_count_reg_n_0_[7]\,
      I1 => \byte_count_reg_n_0_[6]\,
      I2 => \byte_count_reg_n_0_[5]\,
      I3 => \byte_count_reg_n_0_[4]\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => \byte_count_reg_n_0_[2]\,
      O => \rd_enable_fifo0_carry__0_i_5_n_0\
    );
rd_enable_fifo0_carry_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0080AA2A22C2BBAB"
    )
        port map (
      I0 => rd_enable_fifo0_carry_i_9_n_0,
      I1 => \byte_count_reg_n_0_[6]\,
      I2 => \byte_count_reg_n_0_[5]\,
      I3 => rd_enable_fifo0_carry_i_10_n_0,
      I4 => \byte_count_reg_n_0_[7]\,
      I5 => rd_enable_fifo0_carry_i_11_n_0,
      O => rd_enable_fifo0_carry_i_1_n_0
    );
rd_enable_fifo0_carry_i_10: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \byte_count_reg_n_0_[4]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[2]\,
      O => rd_enable_fifo0_carry_i_10_n_0
    );
rd_enable_fifo0_carry_i_11: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55555556"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[6]\,
      I1 => \data_counter_max_reg_n_0_[4]\,
      I2 => \data_counter_max_reg_n_0_[3]\,
      I3 => \data_counter_max_reg_n_0_[2]\,
      I4 => \data_counter_max_reg_n_0_[5]\,
      O => rd_enable_fifo0_carry_i_11_n_0
    );
rd_enable_fifo0_carry_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"5556"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[5]\,
      I1 => \data_counter_max_reg_n_0_[2]\,
      I2 => \data_counter_max_reg_n_0_[3]\,
      I3 => \data_counter_max_reg_n_0_[4]\,
      O => rd_enable_fifo0_carry_i_12_n_0
    );
rd_enable_fifo0_carry_i_13: unisim.vcomponents.LUT3
    generic map(
      INIT => X"56"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[4]\,
      I1 => \data_counter_max_reg_n_0_[3]\,
      I2 => \data_counter_max_reg_n_0_[2]\,
      O => rd_enable_fifo0_carry_i_13_n_0
    );
rd_enable_fifo0_carry_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"40001555C1115777"
    )
        port map (
      I0 => rd_enable_fifo0_carry_i_12_n_0,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[5]\,
      I5 => rd_enable_fifo0_carry_i_13_n_0,
      O => rd_enable_fifo0_carry_i_2_n_0
    );
rd_enable_fifo0_carry_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B109"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[3]\,
      I1 => \data_counter_max_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      O => rd_enable_fifo0_carry_i_3_n_0
    );
rd_enable_fifo0_carry_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[0]\,
      O => rd_enable_fifo0_carry_i_4_n_0
    );
rd_enable_fifo0_carry_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0909600990900990"
    )
        port map (
      I0 => \byte_count_reg_n_0_[7]\,
      I1 => rd_enable_fifo0_carry_i_9_n_0,
      I2 => \byte_count_reg_n_0_[6]\,
      I3 => \byte_count_reg_n_0_[5]\,
      I4 => rd_enable_fifo0_carry_i_10_n_0,
      I5 => rd_enable_fifo0_carry_i_11_n_0,
      O => rd_enable_fifo0_carry_i_5_n_0
    );
rd_enable_fifo0_carry_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9006060606606060"
    )
        port map (
      I0 => \byte_count_reg_n_0_[5]\,
      I1 => rd_enable_fifo0_carry_i_12_n_0,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[2]\,
      I5 => rd_enable_fifo0_carry_i_13_n_0,
      O => rd_enable_fifo0_carry_i_6_n_0
    );
rd_enable_fifo0_carry_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6006"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \data_counter_max_reg_n_0_[3]\,
      I2 => \data_counter_max_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[2]\,
      O => rd_enable_fifo0_carry_i_7_n_0
    );
rd_enable_fifo0_carry_i_8: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \byte_count_reg_n_0_[0]\,
      I1 => \byte_count_reg_n_0_[1]\,
      O => rd_enable_fifo0_carry_i_8_n_0
    );
rd_enable_fifo0_carry_i_9: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAA9"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[7]\,
      I1 => \data_counter_max_reg_n_0_[5]\,
      I2 => \data_counter_max_reg_n_0_[2]\,
      I3 => \data_counter_max_reg_n_0_[3]\,
      I4 => \data_counter_max_reg_n_0_[4]\,
      I5 => \data_counter_max_reg_n_0_[6]\,
      O => rd_enable_fifo0_carry_i_9_n_0
    );
rd_enable_fifo_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF80FFFFFF800000"
    )
        port map (
      I0 => id_counter121_out,
      I1 => tx_ready,
      I2 => is_idle_i_1_n_0,
      I3 => rd_enable_fifo_i_2_n_0,
      I4 => rd_enable_fifo04_out,
      I5 => \^fifo_read_enable\,
      O => rd_enable_fifo_i_1_n_0
    );
rd_enable_fifo_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => bit_count223_in,
      I1 => rd_enable_fifo_i_4_n_0,
      I2 => rd_enable_fifo0,
      I3 => \state_reg_n_0_[2]\,
      I4 => \state_reg_n_0_[0]\,
      O => rd_enable_fifo_i_2_n_0
    );
rd_enable_fifo_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => eth_rstn,
      I1 => rd_enable_fifo_i_5_n_0,
      O => rd_enable_fifo04_out
    );
rd_enable_fifo_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \bit_count_reg_n_0_[0]\,
      I1 => \bit_count_reg_n_0_[1]\,
      I2 => \bit_count_reg_n_0_[3]\,
      I3 => \bit_count_reg_n_0_[2]\,
      O => rd_enable_fifo_i_4_n_0
    );
rd_enable_fifo_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \state_reg_n_0_[1]\,
      O => rd_enable_fifo_i_5_n_0
    );
rd_enable_fifo_reg: unisim.vcomponents.FDRE
     port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => rd_enable_fifo_i_1_n_0,
      Q => \^fifo_read_enable\,
      R => '0'
    );
\send_countdown[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^udp_send_data_valid17_out\,
      I1 => db_sw,
      O => db_sw_reg_0
    );
sent_arp_response_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => arp_reply_reg_n_0,
      I1 => tx_done,
      O => sent_arp_response_i_1_n_0
    );
sent_arp_response_reg: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => sent_arp_response_i_1_n_0,
      Q => sent_arp_response,
      R => '0'
    );
\start_crc_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDFD0020"
    )
        port map (
      I0 => eth_rstn,
      I1 => \start_crc_i_2__0_n_0\,
      I2 => \state_reg_n_0_[1]\,
      I3 => \state_reg_n_0_[2]\,
      I4 => start_crc,
      O => \start_crc_i_1__0_n_0\
    );
\start_crc_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFCCCFCBBCC88CC"
    )
        port map (
      I0 => \start_crc_i_3__0_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \start_crc_i_4__0_n_0\,
      I3 => \state_reg_n_0_[2]\,
      I4 => \start_crc_i_5__0_n_0\,
      I5 => \state_reg_n_0_[1]\,
      O => \start_crc_i_2__0_n_0\
    );
\start_crc_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFD"
    )
        port map (
      I0 => bit_count223_in,
      I1 => \zero_counter_reg_n_0_[4]\,
      I2 => \zero_counter_reg_n_0_[2]\,
      I3 => \zero_counter_reg_n_0_[1]\,
      I4 => \zero_counter_reg_n_0_[3]\,
      O => \start_crc_i_3__0_n_0\
    );
\start_crc_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \start_crc_i_6__0_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => start_crc_i_7_n_0,
      I5 => txen_i_4_n_0,
      O => \start_crc_i_4__0_n_0\
    );
\start_crc_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10FFFFFF"
    )
        port map (
      I0 => \bit_count_reg_n_0_[2]\,
      I1 => \bit_count_reg_n_0_[3]\,
      I2 => bit_count233_in,
      I3 => \state_reg_n_0_[1]\,
      I4 => \bit_count0_inferred__0/i__carry__0_n_2\,
      O => \start_crc_i_5__0_n_0\
    );
\start_crc_i_6__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \byte_count_reg_n_0_[8]\,
      I1 => \byte_count_reg_n_0_[7]\,
      I2 => \byte_count_reg_n_0_[6]\,
      I3 => \byte_count_reg_n_0_[5]\,
      O => \start_crc_i_6__0_n_0\
    );
start_crc_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[0]\,
      O => start_crc_i_7_n_0
    );
start_crc_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \start_crc_i_1__0_n_0\,
      Q => start_crc,
      R => '0'
    );
\state[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFCFFFFFFF80000"
    )
        port map (
      I0 => \state[0]_i_2_n_0\,
      I1 => \state[0]_i_3__0_n_0\,
      I2 => \state[0]_i_4_n_0\,
      I3 => \state[0]_i_5__0_n_0\,
      I4 => state_0,
      I5 => \state_reg_n_0_[0]\,
      O => \state[0]_i_1_n_0\
    );
\state[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \state[0]_i_6__0_n_0\,
      I1 => \bit_count_reg_n_0_[3]\,
      I2 => \bit_count_reg_n_0_[2]\,
      O => \state[0]_i_2_n_0\
    );
\state[0]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \state_reg_n_0_[1]\,
      I2 => \state[2]_i_3__0_n_0\,
      O => \state[0]_i_3__0_n_0\
    );
\state[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F000F004F404F4"
    )
        port map (
      I0 => \state[0]_i_7__0_n_0\,
      I1 => \state[1]_i_3__1_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \state[0]_i_8__0_n_0\,
      I4 => \state[2]_i_5_n_0\,
      I5 => \state_reg_n_0_[1]\,
      O => \state[0]_i_4_n_0\
    );
\state[0]_i_5__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \state[1]_i_4__0_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[1]\,
      I3 => \bit_count[2]_i_4_n_0\,
      O => \state[0]_i_5__0_n_0\
    );
\state[0]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \txd[0]_i_11_n_0\,
      I4 => \bit_count[3]_i_7_n_0\,
      I5 => \state[0]_i_9__0_n_0\,
      O => \state[0]_i_6__0_n_0\
    );
\state[0]_i_7__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => tx_ready,
      I1 => \state_reg_n_0_[0]\,
      O => \state[0]_i_7__0_n_0\
    );
\state[0]_i_8__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFBBBB00F0FFFF"
    )
        port map (
      I0 => \state[2]_i_6__0_n_0\,
      I1 => \bit_count0_inferred__0/i__carry__0_n_2\,
      I2 => bit_count223_in,
      I3 => \i__carry_i_9__0_n_0\,
      I4 => \state_reg_n_0_[0]\,
      I5 => \state_reg_n_0_[1]\,
      O => \state[0]_i_8__0_n_0\
    );
\state[0]_i_9__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \byte_count_reg_n_0_[10]\,
      I1 => \byte_count_reg_n_0_[9]\,
      I2 => \byte_count_reg_n_0_[8]\,
      I3 => \byte_count_reg_n_0_[7]\,
      O => \state[0]_i_9__0_n_0\
    );
\state[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABABFFFFAABB0000"
    )
        port map (
      I0 => \state[1]_i_2__0_n_0\,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state[2]_i_3__0_n_0\,
      I3 => \state[1]_i_3__1_n_0\,
      I4 => state_0,
      I5 => \state_reg_n_0_[1]\,
      O => \state[1]_i_1_n_0\
    );
\state[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A888A888A888AAAA"
    )
        port map (
      I0 => \state[2]_i_2__0_n_0\,
      I1 => \state_reg_n_0_[1]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => bit_count223_in,
      I4 => \bit_count[2]_i_4_n_0\,
      I5 => \state[1]_i_4__0_n_0\,
      O => \state[1]_i_2__0_n_0\
    );
\state[1]_i_3__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00450000FFFFFFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \byte_count[3]_i_3_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => txen_i_3_n_0,
      I4 => \state[2]_i_7__0_n_0\,
      I5 => \state_reg_n_0_[0]\,
      O => \state[1]_i_3__1_n_0\
    );
\state[1]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFEFFFFFFF"
    )
        port map (
      I0 => \state[1]_i_5__1_n_0\,
      I1 => \bit_count[3]_i_7_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[3]\,
      I4 => \byte_count_reg_n_0_[4]\,
      I5 => \bit_count[3]_i_8_n_0\,
      O => \state[1]_i_4__0_n_0\
    );
\state[1]_i_5__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[4]\,
      I1 => \data_counter_max_reg_n_0_[3]\,
      I2 => \data_counter_max_reg_n_0_[2]\,
      I3 => \zero_counter[4]_i_4__0_n_0\,
      I4 => \data_counter_max_reg_n_0_[9]\,
      I5 => \data_counter_max_reg_n_0_[10]\,
      O => \state[1]_i_5__1_n_0\
    );
\state[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAFFEA00"
    )
        port map (
      I0 => \state[2]_i_2__0_n_0\,
      I1 => \state_reg_n_0_[1]\,
      I2 => \state[2]_i_3__0_n_0\,
      I3 => state_0,
      I4 => \state_reg_n_0_[2]\,
      O => \state[2]_i_1_n_0\
    );
\state[2]_i_10__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDDDDDDDCDDDDDDD"
    )
        port map (
      I0 => \state[2]_i_7__0_n_0\,
      I1 => txen_i_3_n_0,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => \byte_count_reg_n_0_[0]\,
      O => \state[2]_i_10__0_n_0\
    );
\state[2]_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFEA"
    )
        port map (
      I0 => \state[0]_i_6__0_n_0\,
      I1 => \bit_count_reg_n_0_[1]\,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \bit_count_reg_n_0_[2]\,
      I4 => \bit_count_reg_n_0_[3]\,
      O => \state[2]_i_11_n_0\
    );
\state[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888AAA8AAAAAAAA"
    )
        port map (
      I0 => \state_reg_n_0_[2]\,
      I1 => \state[2]_i_5_n_0\,
      I2 => \bit_count0_inferred__0/i__carry__0_n_2\,
      I3 => \state[2]_i_6__0_n_0\,
      I4 => \state_reg_n_0_[0]\,
      I5 => \state_reg_n_0_[1]\,
      O => \state[2]_i_2__0_n_0\
    );
\state[2]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDDDDDDD00000000"
    )
        port map (
      I0 => \state[2]_i_7__0_n_0\,
      I1 => txen_i_3_n_0,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => \state_reg_n_0_[0]\,
      O => \state[2]_i_3__0_n_0\
    );
\state[2]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF000F55335533"
    )
        port map (
      I0 => \state[2]_i_8__0_n_0\,
      I1 => \state[2]_i_9_n_0\,
      I2 => \bit_count[3]_i_3_n_0\,
      I3 => \state_reg_n_0_[1]\,
      I4 => \txd[1]_i_4_n_0\,
      I5 => \state_reg_n_0_[2]\,
      O => state_0
    );
\state[2]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => txen_i_3_n_0,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \bit_count_reg_n_0_[3]\,
      I5 => \bit_count_reg_n_0_[2]\,
      O => \state[2]_i_5_n_0\
    );
\state[2]_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => bit_count233_in,
      I1 => \bit_count_reg_n_0_[3]\,
      I2 => \bit_count_reg_n_0_[2]\,
      O => \state[2]_i_6__0_n_0\
    );
\state[2]_i_7__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \bit_count_reg_n_0_[2]\,
      I1 => \bit_count_reg_n_0_[3]\,
      O => \state[2]_i_7__0_n_0\
    );
\state[2]_i_8__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888B888"
    )
        port map (
      I0 => \state[2]_i_10__0_n_0\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \state[2]_i_11_n_0\,
      I3 => \start_crc_i_4__0_n_0\,
      I4 => \byte_count[10]_i_22_n_0\,
      O => \state[2]_i_8__0_n_0\
    );
\state[2]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAA2A2A0A2"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \state[2]_i_7__0_n_0\,
      I2 => txen_i_3_n_0,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \byte_count[3]_i_3_n_0\,
      I5 => \byte_count_reg_n_0_[3]\,
      O => \state[2]_i_9_n_0\
    );
\state_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      CLR => \state_reg[0]_0\,
      D => \state[0]_i_1_n_0\,
      Q => \state_reg_n_0_[0]\
    );
\state_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      CLR => \state_reg[0]_0\,
      D => \state[1]_i_1_n_0\,
      Q => \state_reg_n_0_[1]\
    );
\state_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      CLR => \state_reg[0]_0\,
      D => \state[2]_i_1_n_0\,
      Q => \state_reg_n_0_[2]\
    );
\stop_crc_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DDDF0002"
    )
        port map (
      I0 => eth_rstn,
      I1 => \start_crc_i_2__0_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \state_reg_n_0_[1]\,
      I4 => stop_crc,
      O => \stop_crc_i_1__0_n_0\
    );
stop_crc_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \stop_crc_i_1__0_n_0\,
      Q => stop_crc,
      R => '0'
    );
\temp_iphc10__0_carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \temp_iphc10__0_carry_n_0\,
      CO(2) => \temp_iphc10__0_carry_n_1\,
      CO(1) => \temp_iphc10__0_carry_n_2\,
      CO(0) => \temp_iphc10__0_carry_n_3\,
      CYINIT => '0',
      DI(3) => \temp_iphc10__0_carry_i_1_n_0\,
      DI(2) => \temp_iphc10__0_carry_i_2_n_0\,
      DI(1) => \temp_iphc10__0_carry_i_3_n_0\,
      DI(0) => '0',
      O(3) => \temp_iphc10__0_carry_n_4\,
      O(2) => \temp_iphc10__0_carry_n_5\,
      O(1) => \temp_iphc10__0_carry_n_6\,
      O(0) => \temp_iphc10__0_carry_n_7\,
      S(3) => \temp_iphc10__0_carry_i_4_n_0\,
      S(2) => \temp_iphc10__0_carry_i_5_n_0\,
      S(1) => \temp_iphc10__0_carry_i_6_n_0\,
      S(0) => \temp_iphc10__0_carry_i_7_n_0\
    );
\temp_iphc10__0_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \temp_iphc10__0_carry_n_0\,
      CO(3) => \temp_iphc10__0_carry__0_n_0\,
      CO(2) => \temp_iphc10__0_carry__0_n_1\,
      CO(1) => \temp_iphc10__0_carry__0_n_2\,
      CO(0) => \temp_iphc10__0_carry__0_n_3\,
      CYINIT => '0',
      DI(3) => \temp_iphc10__0_carry__0_i_1_n_0\,
      DI(2) => \temp_iphc10__0_carry__0_i_2_n_0\,
      DI(1) => \temp_iphc10__0_carry__0_i_3_n_0\,
      DI(0) => \temp_iphc10__0_carry__0_i_4_n_0\,
      O(3) => \temp_iphc10__0_carry__0_n_4\,
      O(2) => \temp_iphc10__0_carry__0_n_5\,
      O(1) => \temp_iphc10__0_carry__0_n_6\,
      O(0) => \temp_iphc10__0_carry__0_n_7\,
      S(3) => \temp_iphc10__0_carry__0_i_5_n_0\,
      S(2) => \temp_iphc10__0_carry__0_i_6_n_0\,
      S(1) => \temp_iphc10__0_carry__0_i_7_n_0\,
      S(0) => \temp_iphc10__0_carry__0_i_8_n_0\
    );
\temp_iphc10__0_carry__0_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => p_0_in0_in(6),
      I1 => \temp_iphc1_reg_n_0_[6]\,
      I2 => \dest_ip_reg_n_0_[6]\,
      O => \temp_iphc10__0_carry__0_i_1_n_0\
    );
\temp_iphc10__0_carry__0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => p_0_in0_in(5),
      I1 => \temp_iphc1_reg_n_0_[5]\,
      I2 => \dest_ip_reg_n_0_[5]\,
      O => \temp_iphc10__0_carry__0_i_2_n_0\
    );
\temp_iphc10__0_carry__0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => p_0_in0_in(4),
      I1 => \temp_iphc1_reg_n_0_[4]\,
      I2 => \dest_ip_reg_n_0_[4]\,
      O => \temp_iphc10__0_carry__0_i_3_n_0\
    );
\temp_iphc10__0_carry__0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => p_0_in0_in(3),
      I1 => \temp_iphc1_reg_n_0_[3]\,
      I2 => \dest_ip_reg_n_0_[3]\,
      O => \temp_iphc10__0_carry__0_i_4_n_0\
    );
\temp_iphc10__0_carry__0_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_0_in0_in(7),
      I1 => \temp_iphc1_reg_n_0_[7]\,
      I2 => \dest_ip_reg_n_0_[7]\,
      I3 => \temp_iphc10__0_carry__0_i_1_n_0\,
      O => \temp_iphc10__0_carry__0_i_5_n_0\
    );
\temp_iphc10__0_carry__0_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_0_in0_in(6),
      I1 => \temp_iphc1_reg_n_0_[6]\,
      I2 => \dest_ip_reg_n_0_[6]\,
      I3 => \temp_iphc10__0_carry__0_i_2_n_0\,
      O => \temp_iphc10__0_carry__0_i_6_n_0\
    );
\temp_iphc10__0_carry__0_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_0_in0_in(5),
      I1 => \temp_iphc1_reg_n_0_[5]\,
      I2 => \dest_ip_reg_n_0_[5]\,
      I3 => \temp_iphc10__0_carry__0_i_3_n_0\,
      O => \temp_iphc10__0_carry__0_i_7_n_0\
    );
\temp_iphc10__0_carry__0_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_0_in0_in(4),
      I1 => \temp_iphc1_reg_n_0_[4]\,
      I2 => \dest_ip_reg_n_0_[4]\,
      I3 => \temp_iphc10__0_carry__0_i_4_n_0\,
      O => \temp_iphc10__0_carry__0_i_8_n_0\
    );
\temp_iphc10__0_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \temp_iphc10__0_carry__0_n_0\,
      CO(3) => \temp_iphc10__0_carry__1_n_0\,
      CO(2) => \temp_iphc10__0_carry__1_n_1\,
      CO(1) => \temp_iphc10__0_carry__1_n_2\,
      CO(0) => \temp_iphc10__0_carry__1_n_3\,
      CYINIT => '0',
      DI(3) => \temp_iphc10__0_carry__1_i_1_n_0\,
      DI(2) => \temp_iphc10__0_carry__1_i_2_n_0\,
      DI(1) => \temp_iphc10__0_carry__1_i_3_n_0\,
      DI(0) => \temp_iphc10__0_carry__1_i_4_n_0\,
      O(3) => \temp_iphc10__0_carry__1_n_4\,
      O(2) => \temp_iphc10__0_carry__1_n_5\,
      O(1) => \temp_iphc10__0_carry__1_n_6\,
      O(0) => \temp_iphc10__0_carry__1_n_7\,
      S(3) => \temp_iphc10__0_carry__1_i_5_n_0\,
      S(2) => \temp_iphc10__0_carry__1_i_6_n_0\,
      S(1) => \temp_iphc10__0_carry__1_i_7_n_0\,
      S(0) => \temp_iphc10__0_carry__1_i_8_n_0\
    );
\temp_iphc10__0_carry__1_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => p_0_in0_in(10),
      I1 => \temp_iphc1_reg_n_0_[10]\,
      I2 => \dest_ip_reg_n_0_[10]\,
      O => \temp_iphc10__0_carry__1_i_1_n_0\
    );
\temp_iphc10__0_carry__1_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => p_0_in0_in(9),
      I1 => \temp_iphc1_reg_n_0_[9]\,
      I2 => \dest_ip_reg_n_0_[9]\,
      O => \temp_iphc10__0_carry__1_i_2_n_0\
    );
\temp_iphc10__0_carry__1_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => p_0_in0_in(8),
      I1 => \temp_iphc1_reg_n_0_[8]\,
      I2 => \dest_ip_reg_n_0_[8]\,
      O => \temp_iphc10__0_carry__1_i_3_n_0\
    );
\temp_iphc10__0_carry__1_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => p_0_in0_in(7),
      I1 => \temp_iphc1_reg_n_0_[7]\,
      I2 => \dest_ip_reg_n_0_[7]\,
      O => \temp_iphc10__0_carry__1_i_4_n_0\
    );
\temp_iphc10__0_carry__1_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_0_in0_in(11),
      I1 => \temp_iphc1_reg_n_0_[11]\,
      I2 => \dest_ip_reg_n_0_[11]\,
      I3 => \temp_iphc10__0_carry__1_i_1_n_0\,
      O => \temp_iphc10__0_carry__1_i_5_n_0\
    );
\temp_iphc10__0_carry__1_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_0_in0_in(10),
      I1 => \temp_iphc1_reg_n_0_[10]\,
      I2 => \dest_ip_reg_n_0_[10]\,
      I3 => \temp_iphc10__0_carry__1_i_2_n_0\,
      O => \temp_iphc10__0_carry__1_i_6_n_0\
    );
\temp_iphc10__0_carry__1_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_0_in0_in(9),
      I1 => \temp_iphc1_reg_n_0_[9]\,
      I2 => \dest_ip_reg_n_0_[9]\,
      I3 => \temp_iphc10__0_carry__1_i_3_n_0\,
      O => \temp_iphc10__0_carry__1_i_7_n_0\
    );
\temp_iphc10__0_carry__1_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_0_in0_in(8),
      I1 => \temp_iphc1_reg_n_0_[8]\,
      I2 => \dest_ip_reg_n_0_[8]\,
      I3 => \temp_iphc10__0_carry__1_i_4_n_0\,
      O => \temp_iphc10__0_carry__1_i_8_n_0\
    );
\temp_iphc10__0_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \temp_iphc10__0_carry__1_n_0\,
      CO(3) => \temp_iphc10__0_carry__2_n_0\,
      CO(2) => \temp_iphc10__0_carry__2_n_1\,
      CO(1) => \temp_iphc10__0_carry__2_n_2\,
      CO(0) => \temp_iphc10__0_carry__2_n_3\,
      CYINIT => '0',
      DI(3) => \temp_iphc10__0_carry__2_i_1_n_0\,
      DI(2) => \temp_iphc10__0_carry__2_i_2_n_0\,
      DI(1) => \temp_iphc10__0_carry__2_i_3_n_0\,
      DI(0) => \temp_iphc10__0_carry__2_i_4_n_0\,
      O(3) => \temp_iphc10__0_carry__2_n_4\,
      O(2) => \temp_iphc10__0_carry__2_n_5\,
      O(1) => \temp_iphc10__0_carry__2_n_6\,
      O(0) => \temp_iphc10__0_carry__2_n_7\,
      S(3) => \temp_iphc10__0_carry__2_i_5_n_0\,
      S(2) => \temp_iphc10__0_carry__2_i_6_n_0\,
      S(1) => \temp_iphc10__0_carry__2_i_7_n_0\,
      S(0) => \temp_iphc10__0_carry__2_i_8_n_0\
    );
\temp_iphc10__0_carry__2_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => p_0_in0_in(14),
      I1 => \temp_iphc1_reg_n_0_[14]\,
      I2 => \dest_ip_reg_n_0_[14]\,
      O => \temp_iphc10__0_carry__2_i_1_n_0\
    );
\temp_iphc10__0_carry__2_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => p_0_in0_in(13),
      I1 => \temp_iphc1_reg_n_0_[13]\,
      I2 => \dest_ip_reg_n_0_[13]\,
      O => \temp_iphc10__0_carry__2_i_2_n_0\
    );
\temp_iphc10__0_carry__2_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => p_0_in0_in(12),
      I1 => \temp_iphc1_reg_n_0_[12]\,
      I2 => \dest_ip_reg_n_0_[12]\,
      O => \temp_iphc10__0_carry__2_i_3_n_0\
    );
\temp_iphc10__0_carry__2_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => p_0_in0_in(11),
      I1 => \temp_iphc1_reg_n_0_[11]\,
      I2 => \dest_ip_reg_n_0_[11]\,
      O => \temp_iphc10__0_carry__2_i_4_n_0\
    );
\temp_iphc10__0_carry__2_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \temp_iphc10__0_carry__2_i_1_n_0\,
      I1 => p_0_in0_in(15),
      I2 => \temp_iphc1_reg_n_0_[15]\,
      I3 => \dest_ip_reg_n_0_[15]\,
      O => \temp_iphc10__0_carry__2_i_5_n_0\
    );
\temp_iphc10__0_carry__2_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_0_in0_in(14),
      I1 => \temp_iphc1_reg_n_0_[14]\,
      I2 => \dest_ip_reg_n_0_[14]\,
      I3 => \temp_iphc10__0_carry__2_i_2_n_0\,
      O => \temp_iphc10__0_carry__2_i_6_n_0\
    );
\temp_iphc10__0_carry__2_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_0_in0_in(13),
      I1 => \temp_iphc1_reg_n_0_[13]\,
      I2 => \dest_ip_reg_n_0_[13]\,
      I3 => \temp_iphc10__0_carry__2_i_3_n_0\,
      O => \temp_iphc10__0_carry__2_i_7_n_0\
    );
\temp_iphc10__0_carry__2_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_0_in0_in(12),
      I1 => \temp_iphc1_reg_n_0_[12]\,
      I2 => \dest_ip_reg_n_0_[12]\,
      I3 => \temp_iphc10__0_carry__2_i_4_n_0\,
      O => \temp_iphc10__0_carry__2_i_8_n_0\
    );
\temp_iphc10__0_carry__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \temp_iphc10__0_carry__2_n_0\,
      CO(3) => \temp_iphc10__0_carry__3_n_0\,
      CO(2) => \temp_iphc10__0_carry__3_n_1\,
      CO(1) => \temp_iphc10__0_carry__3_n_2\,
      CO(0) => \temp_iphc10__0_carry__3_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \temp_iphc1_reg_n_0_[16]\,
      O(3) => \temp_iphc10__0_carry__3_n_4\,
      O(2) => \temp_iphc10__0_carry__3_n_5\,
      O(1) => \temp_iphc10__0_carry__3_n_6\,
      O(0) => \temp_iphc10__0_carry__3_n_7\,
      S(3) => \temp_iphc1_reg_n_0_[19]\,
      S(2) => \temp_iphc1_reg_n_0_[18]\,
      S(1) => \temp_iphc1_reg_n_0_[17]\,
      S(0) => \temp_iphc10__0_carry__3_i_1_n_0\
    );
\temp_iphc10__0_carry__3_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"17E8"
    )
        port map (
      I0 => \dest_ip_reg_n_0_[15]\,
      I1 => \temp_iphc1_reg_n_0_[15]\,
      I2 => p_0_in0_in(15),
      I3 => \temp_iphc1_reg_n_0_[16]\,
      O => \temp_iphc10__0_carry__3_i_1_n_0\
    );
\temp_iphc10__0_carry__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \temp_iphc10__0_carry__3_n_0\,
      CO(3) => \NLW_temp_iphc10__0_carry__4_CO_UNCONNECTED\(3),
      CO(2) => \temp_iphc10__0_carry__4_n_1\,
      CO(1) => \temp_iphc10__0_carry__4_n_2\,
      CO(0) => \temp_iphc10__0_carry__4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \temp_iphc10__0_carry__4_n_4\,
      O(2) => \temp_iphc10__0_carry__4_n_5\,
      O(1) => \temp_iphc10__0_carry__4_n_6\,
      O(0) => \temp_iphc10__0_carry__4_n_7\,
      S(3) => \temp_iphc1_reg_n_0_[23]\,
      S(2) => \temp_iphc1_reg_n_0_[22]\,
      S(1) => \temp_iphc1_reg_n_0_[21]\,
      S(0) => \temp_iphc1_reg_n_0_[20]\
    );
\temp_iphc10__0_carry_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => p_0_in0_in(2),
      I1 => \temp_iphc1_reg_n_0_[2]\,
      I2 => \dest_ip_reg_n_0_[2]\,
      O => \temp_iphc10__0_carry_i_1_n_0\
    );
\temp_iphc10__0_carry_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => p_0_in0_in(1),
      I1 => \temp_iphc1_reg_n_0_[1]\,
      I2 => \dest_ip_reg_n_0_[1]\,
      O => \temp_iphc10__0_carry_i_2_n_0\
    );
\temp_iphc10__0_carry_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[0]\,
      I1 => p_0_in0_in(0),
      I2 => \dest_ip_reg_n_0_[0]\,
      O => \temp_iphc10__0_carry_i_3_n_0\
    );
\temp_iphc10__0_carry_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_0_in0_in(3),
      I1 => \temp_iphc1_reg_n_0_[3]\,
      I2 => \dest_ip_reg_n_0_[3]\,
      I3 => \temp_iphc10__0_carry_i_1_n_0\,
      O => \temp_iphc10__0_carry_i_4_n_0\
    );
\temp_iphc10__0_carry_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_0_in0_in(2),
      I1 => \temp_iphc1_reg_n_0_[2]\,
      I2 => \dest_ip_reg_n_0_[2]\,
      I3 => \temp_iphc10__0_carry_i_2_n_0\,
      O => \temp_iphc10__0_carry_i_5_n_0\
    );
\temp_iphc10__0_carry_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => p_0_in0_in(1),
      I1 => \temp_iphc1_reg_n_0_[1]\,
      I2 => \dest_ip_reg_n_0_[1]\,
      I3 => \temp_iphc10__0_carry_i_3_n_0\,
      O => \temp_iphc10__0_carry_i_6_n_0\
    );
\temp_iphc10__0_carry_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \temp_iphc1_reg_n_0_[0]\,
      I1 => p_0_in0_in(0),
      I2 => \dest_ip_reg_n_0_[0]\,
      O => \temp_iphc10__0_carry_i_7_n_0\
    );
\temp_iphc10__110_carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \temp_iphc10__110_carry_n_0\,
      CO(2) => \temp_iphc10__110_carry_n_1\,
      CO(1) => \temp_iphc10__110_carry_n_2\,
      CO(0) => \temp_iphc10__110_carry_n_3\,
      CYINIT => '0',
      DI(3) => \temp_iphc10__110_carry_i_1_n_0\,
      DI(2) => \temp_iphc10__110_carry_i_2_n_0\,
      DI(1) => \temp_iphc10__110_carry_i_3_n_0\,
      DI(0) => \temp_iphc10__110_carry_i_4_n_0\,
      O(3) => \temp_iphc10__110_carry_n_4\,
      O(2) => \temp_iphc10__110_carry_n_5\,
      O(1) => \temp_iphc10__110_carry_n_6\,
      O(0) => \NLW_temp_iphc10__110_carry_O_UNCONNECTED\(0),
      S(3) => \temp_iphc10__110_carry_i_5_n_0\,
      S(2) => \temp_iphc10__110_carry_i_6_n_0\,
      S(1) => \temp_iphc10__110_carry_i_7_n_0\,
      S(0) => \temp_iphc10__110_carry_i_8_n_0\
    );
\temp_iphc10__110_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \temp_iphc10__110_carry_n_0\,
      CO(3) => \temp_iphc10__110_carry__0_n_0\,
      CO(2) => \temp_iphc10__110_carry__0_n_1\,
      CO(1) => \temp_iphc10__110_carry__0_n_2\,
      CO(0) => \temp_iphc10__110_carry__0_n_3\,
      CYINIT => '0',
      DI(3) => \temp_iphc10__110_carry__0_i_1_n_0\,
      DI(2) => \temp_iphc10__110_carry__0_i_2_n_0\,
      DI(1) => \temp_iphc10__110_carry__0_i_3_n_0\,
      DI(0) => \temp_iphc10__110_carry__0_i_4_n_0\,
      O(3) => \temp_iphc10__110_carry__0_n_4\,
      O(2) => \temp_iphc10__110_carry__0_n_5\,
      O(1) => \temp_iphc10__110_carry__0_n_6\,
      O(0) => \temp_iphc10__110_carry__0_n_7\,
      S(3) => \temp_iphc10__110_carry__0_i_5_n_0\,
      S(2) => \temp_iphc10__110_carry__0_i_6_n_0\,
      S(1) => \temp_iphc10__110_carry__0_i_7_n_0\,
      S(0) => \temp_iphc10__110_carry__0_i_8_n_0\
    );
\temp_iphc10__110_carry__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696960096000000"
    )
        port map (
      I0 => \temp_iphc10__64_carry__0_n_4\,
      I1 => \temp_iphc10__0_carry__0_n_4\,
      I2 => \ip_total_length_reg_n_0_[7]\,
      I3 => \temp_iphc10__0_carry__0_n_5\,
      I4 => \ip_total_length_reg_n_0_[6]\,
      I5 => \temp_iphc10__64_carry__0_n_5\,
      O => \temp_iphc10__110_carry__0_i_1_n_0\
    );
\temp_iphc10__110_carry__0_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \ip_total_length_reg_n_0_[7]\,
      I1 => \temp_iphc10__0_carry__0_n_4\,
      I2 => \temp_iphc10__64_carry__0_n_4\,
      O => \temp_iphc10__110_carry__0_i_10_n_0\
    );
\temp_iphc10__110_carry__0_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \temp_iphc10__0_carry__0_n_5\,
      I1 => \temp_iphc10__64_carry__0_n_5\,
      I2 => \ip_total_length_reg_n_0_[6]\,
      O => \temp_iphc10__110_carry__0_i_11_n_0\
    );
\temp_iphc10__110_carry__0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \temp_iphc10__0_carry__0_n_6\,
      I1 => \ip_total_length_reg_n_0_[5]\,
      I2 => \temp_iphc10__64_carry__0_n_6\,
      I3 => \ip_total_length_reg_n_0_[6]\,
      I4 => \temp_iphc10__64_carry__0_n_5\,
      I5 => \temp_iphc10__0_carry__0_n_5\,
      O => \temp_iphc10__110_carry__0_i_2_n_0\
    );
\temp_iphc10__110_carry__0_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \temp_iphc10__0_carry__0_n_7\,
      I1 => \temp_iphc10__64_carry__0_n_7\,
      I2 => \ip_total_length_reg_n_0_[5]\,
      I3 => \temp_iphc10__64_carry__0_n_6\,
      I4 => \temp_iphc10__0_carry__0_n_6\,
      O => \temp_iphc10__110_carry__0_i_3_n_0\
    );
\temp_iphc10__110_carry__0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"82"
    )
        port map (
      I0 => \ip_total_length_reg_n_0_[4]\,
      I1 => \temp_iphc10__0_carry__0_n_7\,
      I2 => \temp_iphc10__64_carry__0_n_7\,
      O => \temp_iphc10__110_carry__0_i_4_n_0\
    );
\temp_iphc10__110_carry__0_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969669"
    )
        port map (
      I0 => p_1_in(0),
      I1 => \temp_iphc10__64_carry__1_n_7\,
      I2 => \temp_iphc10__0_carry__1_n_7\,
      I3 => \temp_iphc10__110_carry__0_i_9_n_0\,
      I4 => \temp_iphc10__110_carry__0_i_1_n_0\,
      O => \temp_iphc10__110_carry__0_i_5_n_0\
    );
\temp_iphc10__110_carry__0_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A995566A"
    )
        port map (
      I0 => \temp_iphc10__110_carry__0_i_2_n_0\,
      I1 => \temp_iphc10__0_carry__0_n_5\,
      I2 => \ip_total_length_reg_n_0_[6]\,
      I3 => \temp_iphc10__64_carry__0_n_5\,
      I4 => \temp_iphc10__110_carry__0_i_10_n_0\,
      O => \temp_iphc10__110_carry__0_i_6_n_0\
    );
\temp_iphc10__110_carry__0_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66696999"
    )
        port map (
      I0 => \temp_iphc10__110_carry__0_i_3_n_0\,
      I1 => \temp_iphc10__110_carry__0_i_11_n_0\,
      I2 => \temp_iphc10__64_carry__0_n_6\,
      I3 => \ip_total_length_reg_n_0_[5]\,
      I4 => \temp_iphc10__0_carry__0_n_6\,
      O => \temp_iphc10__110_carry__0_i_7_n_0\
    );
\temp_iphc10__110_carry__0_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669966996696996"
    )
        port map (
      I0 => \temp_iphc10__110_carry__0_i_4_n_0\,
      I1 => \temp_iphc10__0_carry__0_n_6\,
      I2 => \temp_iphc10__64_carry__0_n_6\,
      I3 => \ip_total_length_reg_n_0_[5]\,
      I4 => \temp_iphc10__64_carry__0_n_7\,
      I5 => \temp_iphc10__0_carry__0_n_7\,
      O => \temp_iphc10__110_carry__0_i_8_n_0\
    );
\temp_iphc10__110_carry__0_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \temp_iphc10__64_carry__0_n_4\,
      I1 => \temp_iphc10__0_carry__0_n_4\,
      I2 => \ip_total_length_reg_n_0_[7]\,
      O => \temp_iphc10__110_carry__0_i_9_n_0\
    );
\temp_iphc10__110_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \temp_iphc10__110_carry__0_n_0\,
      CO(3) => \temp_iphc10__110_carry__1_n_0\,
      CO(2) => \temp_iphc10__110_carry__1_n_1\,
      CO(1) => \temp_iphc10__110_carry__1_n_2\,
      CO(0) => \temp_iphc10__110_carry__1_n_3\,
      CYINIT => '0',
      DI(3) => \temp_iphc10__110_carry__1_i_1_n_0\,
      DI(2) => \temp_iphc10__110_carry__1_i_2_n_0\,
      DI(1) => \temp_iphc10__110_carry__1_i_3_n_0\,
      DI(0) => \temp_iphc10__110_carry__1_i_4_n_0\,
      O(3) => \temp_iphc10__110_carry__1_n_4\,
      O(2) => \temp_iphc10__110_carry__1_n_5\,
      O(1) => \temp_iphc10__110_carry__1_n_6\,
      O(0) => \temp_iphc10__110_carry__1_n_7\,
      S(3) => \temp_iphc10__110_carry__1_i_5_n_0\,
      S(2) => \temp_iphc10__110_carry__1_i_6_n_0\,
      S(1) => \temp_iphc10__110_carry__1_i_7_n_0\,
      S(0) => \temp_iphc10__110_carry__1_i_8_n_0\
    );
\temp_iphc10__110_carry__1_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E00E0EE0"
    )
        port map (
      I0 => \temp_iphc10__0_carry__1_n_5\,
      I1 => \temp_iphc10__64_carry__1_n_5\,
      I2 => p_1_in(3),
      I3 => \temp_iphc10__64_carry__1_n_4\,
      I4 => \temp_iphc10__0_carry__1_n_4\,
      O => \temp_iphc10__110_carry__1_i_1_n_0\
    );
\temp_iphc10__110_carry__1_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F9F9F990F9909090"
    )
        port map (
      I0 => \temp_iphc10__0_carry__1_n_5\,
      I1 => \temp_iphc10__64_carry__1_n_5\,
      I2 => p_1_in(2),
      I3 => \temp_iphc10__64_carry__1_n_6\,
      I4 => \temp_iphc10__0_carry__1_n_6\,
      I5 => p_1_in(1),
      O => \temp_iphc10__110_carry__1_i_2_n_0\
    );
\temp_iphc10__110_carry__1_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E81717E817E8E817"
    )
        port map (
      I0 => p_1_in(1),
      I1 => \temp_iphc10__0_carry__1_n_6\,
      I2 => \temp_iphc10__64_carry__1_n_6\,
      I3 => \temp_iphc10__0_carry__1_n_5\,
      I4 => \temp_iphc10__64_carry__1_n_5\,
      I5 => p_1_in(2),
      O => \temp_iphc10__110_carry__1_i_3_n_0\
    );
\temp_iphc10__110_carry__1_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F9F9F990F9909090"
    )
        port map (
      I0 => \temp_iphc10__0_carry__1_n_7\,
      I1 => \temp_iphc10__64_carry__1_n_7\,
      I2 => p_1_in(0),
      I3 => \temp_iphc10__64_carry__0_n_4\,
      I4 => \temp_iphc10__0_carry__0_n_4\,
      I5 => \ip_total_length_reg_n_0_[7]\,
      O => \temp_iphc10__110_carry__1_i_4_n_0\
    );
\temp_iphc10__110_carry__1_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66696999"
    )
        port map (
      I0 => \temp_iphc10__110_carry__1_i_1_n_0\,
      I1 => \temp_iphc10__110_carry__1_i_9_n_0\,
      I2 => \temp_iphc10__64_carry__1_n_4\,
      I3 => p_1_in(3),
      I4 => \temp_iphc10__0_carry__1_n_4\,
      O => \temp_iphc10__110_carry__1_i_5_n_0\
    );
\temp_iphc10__110_carry__1_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669966996696996"
    )
        port map (
      I0 => \temp_iphc10__110_carry__1_i_2_n_0\,
      I1 => \temp_iphc10__0_carry__1_n_4\,
      I2 => \temp_iphc10__64_carry__1_n_4\,
      I3 => p_1_in(3),
      I4 => \temp_iphc10__64_carry__1_n_5\,
      I5 => \temp_iphc10__0_carry__1_n_5\,
      O => \temp_iphc10__110_carry__1_i_6_n_0\
    );
\temp_iphc10__110_carry__1_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"699669966996AAAA"
    )
        port map (
      I0 => \temp_iphc10__110_carry__1_i_3_n_0\,
      I1 => p_1_in(1),
      I2 => \temp_iphc10__0_carry__1_n_6\,
      I3 => \temp_iphc10__64_carry__1_n_6\,
      I4 => \temp_iphc10__64_carry__1_n_7\,
      I5 => \temp_iphc10__0_carry__1_n_7\,
      O => \temp_iphc10__110_carry__1_i_7_n_0\
    );
\temp_iphc10__110_carry__1_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669966996696996"
    )
        port map (
      I0 => \temp_iphc10__110_carry__1_i_4_n_0\,
      I1 => p_1_in(1),
      I2 => \temp_iphc10__0_carry__1_n_6\,
      I3 => \temp_iphc10__64_carry__1_n_6\,
      I4 => \temp_iphc10__64_carry__1_n_7\,
      I5 => \temp_iphc10__0_carry__1_n_7\,
      O => \temp_iphc10__110_carry__1_i_8_n_0\
    );
\temp_iphc10__110_carry__1_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \temp_iphc10__0_carry__2_n_7\,
      I1 => \temp_iphc10__64_carry__2_n_7\,
      I2 => p_1_in(4),
      O => \temp_iphc10__110_carry__1_i_9_n_0\
    );
\temp_iphc10__110_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \temp_iphc10__110_carry__1_n_0\,
      CO(3) => \temp_iphc10__110_carry__2_n_0\,
      CO(2) => \temp_iphc10__110_carry__2_n_1\,
      CO(1) => \temp_iphc10__110_carry__2_n_2\,
      CO(0) => \temp_iphc10__110_carry__2_n_3\,
      CYINIT => '0',
      DI(3) => \temp_iphc10__110_carry__2_i_1_n_0\,
      DI(2) => \temp_iphc10__110_carry__2_i_2_n_0\,
      DI(1) => \temp_iphc10__110_carry__2_i_3_n_0\,
      DI(0) => \temp_iphc10__110_carry__2_i_4_n_0\,
      O(3) => \temp_iphc10__110_carry__2_n_4\,
      O(2) => \temp_iphc10__110_carry__2_n_5\,
      O(1) => \temp_iphc10__110_carry__2_n_6\,
      O(0) => \temp_iphc10__110_carry__2_n_7\,
      S(3) => \temp_iphc10__110_carry__2_i_5_n_0\,
      S(2) => \temp_iphc10__110_carry__2_i_6_n_0\,
      S(1) => \temp_iphc10__110_carry__2_i_7_n_0\,
      S(0) => \temp_iphc10__110_carry__2_i_8_n_0\
    );
\temp_iphc10__110_carry__2_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEE0E0FE"
    )
        port map (
      I0 => \temp_iphc10__0_carry__2_n_5\,
      I1 => \temp_iphc10__64_carry__2_n_5\,
      I2 => p_1_in(7),
      I3 => \temp_iphc10__0_carry__2_n_4\,
      I4 => \temp_iphc10__64_carry__2_n_4\,
      O => \temp_iphc10__110_carry__2_i_1_n_0\
    );
\temp_iphc10__110_carry__2_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => p_1_in(5),
      I1 => \temp_iphc10__0_carry__2_n_6\,
      I2 => \temp_iphc10__64_carry__2_n_6\,
      O => \temp_iphc10__110_carry__2_i_10_n_0\
    );
\temp_iphc10__110_carry__2_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F9F9F990F9909090"
    )
        port map (
      I0 => \temp_iphc10__0_carry__2_n_5\,
      I1 => \temp_iphc10__64_carry__2_n_5\,
      I2 => p_1_in(6),
      I3 => \temp_iphc10__64_carry__2_n_6\,
      I4 => \temp_iphc10__0_carry__2_n_6\,
      I5 => p_1_in(5),
      O => \temp_iphc10__110_carry__2_i_2_n_0\
    );
\temp_iphc10__110_carry__2_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696960096000000"
    )
        port map (
      I0 => \temp_iphc10__64_carry__2_n_6\,
      I1 => \temp_iphc10__0_carry__2_n_6\,
      I2 => p_1_in(5),
      I3 => \temp_iphc10__0_carry__2_n_7\,
      I4 => p_1_in(4),
      I5 => \temp_iphc10__64_carry__2_n_7\,
      O => \temp_iphc10__110_carry__2_i_3_n_0\
    );
\temp_iphc10__110_carry__2_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E80000E800E8E800"
    )
        port map (
      I0 => \temp_iphc10__0_carry__1_n_4\,
      I1 => p_1_in(3),
      I2 => \temp_iphc10__64_carry__1_n_4\,
      I3 => p_1_in(4),
      I4 => \temp_iphc10__64_carry__2_n_7\,
      I5 => \temp_iphc10__0_carry__2_n_7\,
      O => \temp_iphc10__110_carry__2_i_4_n_0\
    );
\temp_iphc10__110_carry__2_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69696996"
    )
        port map (
      I0 => \temp_iphc10__110_carry__2_i_1_n_0\,
      I1 => \temp_iphc10__0_carry__3_n_7\,
      I2 => \temp_iphc10__64_carry__3_n_7\,
      I3 => \temp_iphc10__64_carry__2_n_4\,
      I4 => \temp_iphc10__0_carry__2_n_4\,
      O => \temp_iphc10__110_carry__2_i_5_n_0\
    );
\temp_iphc10__110_carry__2_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6669999699966669"
    )
        port map (
      I0 => \temp_iphc10__110_carry__2_i_2_n_0\,
      I1 => p_1_in(7),
      I2 => \temp_iphc10__64_carry__2_n_5\,
      I3 => \temp_iphc10__0_carry__2_n_5\,
      I4 => \temp_iphc10__0_carry__2_n_4\,
      I5 => \temp_iphc10__64_carry__2_n_4\,
      O => \temp_iphc10__110_carry__2_i_6_n_0\
    );
\temp_iphc10__110_carry__2_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969669"
    )
        port map (
      I0 => p_1_in(6),
      I1 => \temp_iphc10__64_carry__2_n_5\,
      I2 => \temp_iphc10__0_carry__2_n_5\,
      I3 => \temp_iphc10__110_carry__2_i_9_n_0\,
      I4 => \temp_iphc10__110_carry__2_i_3_n_0\,
      O => \temp_iphc10__110_carry__2_i_7_n_0\
    );
\temp_iphc10__110_carry__2_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A995566A"
    )
        port map (
      I0 => \temp_iphc10__110_carry__2_i_4_n_0\,
      I1 => \temp_iphc10__0_carry__2_n_7\,
      I2 => p_1_in(4),
      I3 => \temp_iphc10__64_carry__2_n_7\,
      I4 => \temp_iphc10__110_carry__2_i_10_n_0\,
      O => \temp_iphc10__110_carry__2_i_8_n_0\
    );
\temp_iphc10__110_carry__2_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \temp_iphc10__64_carry__2_n_6\,
      I1 => \temp_iphc10__0_carry__2_n_6\,
      I2 => p_1_in(5),
      O => \temp_iphc10__110_carry__2_i_9_n_0\
    );
\temp_iphc10__110_carry__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \temp_iphc10__110_carry__2_n_0\,
      CO(3) => \temp_iphc10__110_carry__3_n_0\,
      CO(2) => \temp_iphc10__110_carry__3_n_1\,
      CO(1) => \temp_iphc10__110_carry__3_n_2\,
      CO(0) => \temp_iphc10__110_carry__3_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \temp_iphc10__0_carry__3_n_5\,
      DI(0) => \temp_iphc10__110_carry__3_i_1_n_0\,
      O(3) => \temp_iphc10__110_carry__3_n_4\,
      O(2) => \temp_iphc10__110_carry__3_n_5\,
      O(1) => \temp_iphc10__110_carry__3_n_6\,
      O(0) => \temp_iphc10__110_carry__3_n_7\,
      S(3) => \temp_iphc10__0_carry__4_n_7\,
      S(2) => \temp_iphc10__0_carry__3_n_4\,
      S(1) => \temp_iphc10__110_carry__3_i_2_n_0\,
      S(0) => \temp_iphc10__110_carry__3_i_3_n_0\
    );
\temp_iphc10__110_carry__3_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EEE8"
    )
        port map (
      I0 => \temp_iphc10__64_carry__3_n_7\,
      I1 => \temp_iphc10__0_carry__3_n_7\,
      I2 => \temp_iphc10__64_carry__2_n_4\,
      I3 => \temp_iphc10__0_carry__2_n_4\,
      O => \temp_iphc10__110_carry__3_i_1_n_0\
    );
\temp_iphc10__110_carry__3_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => \temp_iphc10__0_carry__3_n_6\,
      I1 => \temp_iphc10__64_carry__3_n_2\,
      I2 => \temp_iphc10__0_carry__3_n_5\,
      O => \temp_iphc10__110_carry__3_i_2_n_0\
    );
\temp_iphc10__110_carry__3_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEE0011F011FFEE0"
    )
        port map (
      I0 => \temp_iphc10__0_carry__2_n_4\,
      I1 => \temp_iphc10__64_carry__2_n_4\,
      I2 => \temp_iphc10__0_carry__3_n_7\,
      I3 => \temp_iphc10__64_carry__3_n_7\,
      I4 => \temp_iphc10__0_carry__3_n_6\,
      I5 => \temp_iphc10__64_carry__3_n_2\,
      O => \temp_iphc10__110_carry__3_i_3_n_0\
    );
\temp_iphc10__110_carry__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \temp_iphc10__110_carry__3_n_0\,
      CO(3 downto 2) => \NLW_temp_iphc10__110_carry__4_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \temp_iphc10__110_carry__4_n_2\,
      CO(0) => \temp_iphc10__110_carry__4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_temp_iphc10__110_carry__4_O_UNCONNECTED\(3),
      O(2) => \temp_iphc10__110_carry__4_n_5\,
      O(1) => \temp_iphc10__110_carry__4_n_6\,
      O(0) => \temp_iphc10__110_carry__4_n_7\,
      S(3) => '0',
      S(2) => \temp_iphc10__0_carry__4_n_4\,
      S(1) => \temp_iphc10__0_carry__4_n_5\,
      S(0) => \temp_iphc10__0_carry__4_n_6\
    );
\temp_iphc10__110_carry_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => \temp_iphc10__0_carry__0_n_7\,
      I1 => \temp_iphc10__64_carry__0_n_7\,
      I2 => \ip_total_length_reg_n_0_[4]\,
      O => \temp_iphc10__110_carry_i_1_n_0\
    );
\temp_iphc10__110_carry_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \temp_iphc10__64_carry_n_5\,
      I1 => \ip_total_length_reg_n_0_[2]\,
      I2 => \temp_iphc10__0_carry_n_5\,
      O => \temp_iphc10__110_carry_i_2_n_0\
    );
\temp_iphc10__110_carry_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \temp_iphc10__64_carry_n_6\,
      I1 => \temp_iphc10__0_carry_n_6\,
      O => \temp_iphc10__110_carry_i_3_n_0\
    );
\temp_iphc10__110_carry_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \temp_iphc10__64_carry_n_7\,
      I1 => \temp_iphc10__0_carry_n_7\,
      O => \temp_iphc10__110_carry_i_4_n_0\
    );
\temp_iphc10__110_carry_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9696966996696969"
    )
        port map (
      I0 => \ip_total_length_reg_n_0_[4]\,
      I1 => \temp_iphc10__64_carry__0_n_7\,
      I2 => \temp_iphc10__0_carry__0_n_7\,
      I3 => \temp_iphc10__0_carry_n_4\,
      I4 => \ip_total_length_reg_n_0_[3]\,
      I5 => \temp_iphc10__64_carry_n_4\,
      O => \temp_iphc10__110_carry_i_5_n_0\
    );
\temp_iphc10__110_carry_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \temp_iphc10__110_carry_i_2_n_0\,
      I1 => \temp_iphc10__64_carry_n_4\,
      I2 => \ip_total_length_reg_n_0_[3]\,
      I3 => \temp_iphc10__0_carry_n_4\,
      O => \temp_iphc10__110_carry_i_6_n_0\
    );
\temp_iphc10__110_carry_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => \temp_iphc10__64_carry_n_5\,
      I1 => \ip_total_length_reg_n_0_[2]\,
      I2 => \temp_iphc10__0_carry_n_5\,
      I3 => \temp_iphc10__110_carry_i_3_n_0\,
      O => \temp_iphc10__110_carry_i_7_n_0\
    );
\temp_iphc10__110_carry_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9996"
    )
        port map (
      I0 => \temp_iphc10__64_carry_n_6\,
      I1 => \temp_iphc10__0_carry_n_6\,
      I2 => \temp_iphc10__0_carry_n_7\,
      I3 => \temp_iphc10__64_carry_n_7\,
      O => \temp_iphc10__110_carry_i_8_n_0\
    );
\temp_iphc10__64_carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \temp_iphc10__64_carry_n_0\,
      CO(2) => \temp_iphc10__64_carry_n_1\,
      CO(1) => \temp_iphc10__64_carry_n_2\,
      CO(0) => \temp_iphc10__64_carry_n_3\,
      CYINIT => '0',
      DI(3) => \temp_iphc10__64_carry_i_1_n_0\,
      DI(2) => \temp_iphc10__64_carry_i_2_n_0\,
      DI(1) => \temp_iphc10__64_carry_i_3_n_0\,
      DI(0) => '0',
      O(3) => \temp_iphc10__64_carry_n_4\,
      O(2) => \temp_iphc10__64_carry_n_5\,
      O(1) => \temp_iphc10__64_carry_n_6\,
      O(0) => \temp_iphc10__64_carry_n_7\,
      S(3) => \temp_iphc10__64_carry_i_4_n_0\,
      S(2) => \temp_iphc10__64_carry_i_5_n_0\,
      S(1) => \temp_iphc10__64_carry_i_6_n_0\,
      S(0) => \temp_iphc10__64_carry_i_7_n_0\
    );
\temp_iphc10__64_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \temp_iphc10__64_carry_n_0\,
      CO(3) => \temp_iphc10__64_carry__0_n_0\,
      CO(2) => \temp_iphc10__64_carry__0_n_1\,
      CO(1) => \temp_iphc10__64_carry__0_n_2\,
      CO(0) => \temp_iphc10__64_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"01",
      DI(1) => \id_counter__0\(5),
      DI(0) => \temp_iphc10__64_carry__0_i_1_n_0\,
      O(3) => \temp_iphc10__64_carry__0_n_4\,
      O(2) => \temp_iphc10__64_carry__0_n_5\,
      O(1) => \temp_iphc10__64_carry__0_n_6\,
      O(0) => \temp_iphc10__64_carry__0_n_7\,
      S(3) => \temp_iphc10__64_carry__0_i_2_n_0\,
      S(2) => \temp_iphc10__64_carry__0_i_3_n_0\,
      S(1) => \temp_iphc10__64_carry__0_i_4_n_0\,
      S(0) => \temp_iphc10__64_carry__0_i_5_n_0\
    );
\temp_iphc10__64_carry__0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => ip(3),
      I1 => \id_counter__0\(3),
      O => \temp_iphc10__64_carry__0_i_1_n_0\
    );
\temp_iphc10__64_carry__0_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \id_counter__0\(7),
      O => \temp_iphc10__64_carry__0_i_2_n_0\
    );
\temp_iphc10__64_carry__0_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \id_counter__0\(6),
      O => \temp_iphc10__64_carry__0_i_3_n_0\
    );
\temp_iphc10__64_carry__0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => ip(4),
      I1 => \id_counter__0\(4),
      I2 => \id_counter__0\(5),
      O => \temp_iphc10__64_carry__0_i_4_n_0\
    );
\temp_iphc10__64_carry__0_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E11E"
    )
        port map (
      I0 => \id_counter__0\(3),
      I1 => ip(3),
      I2 => ip(4),
      I3 => \id_counter__0\(4),
      O => \temp_iphc10__64_carry__0_i_5_n_0\
    );
\temp_iphc10__64_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \temp_iphc10__64_carry__0_n_0\,
      CO(3) => \temp_iphc10__64_carry__1_n_0\,
      CO(2) => \temp_iphc10__64_carry__1_n_1\,
      CO(1) => \temp_iphc10__64_carry__1_n_2\,
      CO(0) => \temp_iphc10__64_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => \id_counter__0\(8 downto 7),
      O(3) => \temp_iphc10__64_carry__1_n_4\,
      O(2) => \temp_iphc10__64_carry__1_n_5\,
      O(1) => \temp_iphc10__64_carry__1_n_6\,
      O(0) => \temp_iphc10__64_carry__1_n_7\,
      S(3 downto 2) => \id_counter__0\(11 downto 10),
      S(1) => \temp_iphc10__64_carry__1_i_1_n_0\,
      S(0) => \temp_iphc10__64_carry__1_i_2_n_0\
    );
\temp_iphc10__64_carry__1_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \id_counter__0\(8),
      I1 => \id_counter__0\(9),
      O => \temp_iphc10__64_carry__1_i_1_n_0\
    );
\temp_iphc10__64_carry__1_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \id_counter__0\(7),
      I1 => \id_counter__0\(8),
      O => \temp_iphc10__64_carry__1_i_2_n_0\
    );
\temp_iphc10__64_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \temp_iphc10__64_carry__1_n_0\,
      CO(3) => \temp_iphc10__64_carry__2_n_0\,
      CO(2) => \temp_iphc10__64_carry__2_n_1\,
      CO(1) => \temp_iphc10__64_carry__2_n_2\,
      CO(0) => \temp_iphc10__64_carry__2_n_3\,
      CYINIT => '0',
      DI(3) => \id_counter__0\(14),
      DI(2 downto 0) => B"000",
      O(3) => \temp_iphc10__64_carry__2_n_4\,
      O(2) => \temp_iphc10__64_carry__2_n_5\,
      O(1) => \temp_iphc10__64_carry__2_n_6\,
      O(0) => \temp_iphc10__64_carry__2_n_7\,
      S(3) => \temp_iphc10__64_carry__2_i_1_n_0\,
      S(2) => \temp_iphc10__64_carry__2_i_2_n_0\,
      S(1 downto 0) => \id_counter__0\(13 downto 12)
    );
\temp_iphc10__64_carry__2_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \id_counter__0\(14),
      I1 => \id_counter__0\(15),
      O => \temp_iphc10__64_carry__2_i_1_n_0\
    );
\temp_iphc10__64_carry__2_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \id_counter__0\(14),
      O => \temp_iphc10__64_carry__2_i_2_n_0\
    );
\temp_iphc10__64_carry__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \temp_iphc10__64_carry__2_n_0\,
      CO(3 downto 2) => \NLW_temp_iphc10__64_carry__3_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \temp_iphc10__64_carry__3_n_2\,
      CO(0) => \NLW_temp_iphc10__64_carry__3_CO_UNCONNECTED\(0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_temp_iphc10__64_carry__3_O_UNCONNECTED\(3 downto 1),
      O(0) => \temp_iphc10__64_carry__3_n_7\,
      S(3 downto 1) => B"001",
      S(0) => \id_counter__0\(15)
    );
\temp_iphc10__64_carry_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \id_counter__0\(2),
      I1 => ip(2),
      O => \temp_iphc10__64_carry_i_1_n_0\
    );
\temp_iphc10__64_carry_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \id_counter__0\(1),
      I1 => ip(1),
      O => \temp_iphc10__64_carry_i_2_n_0\
    );
\temp_iphc10__64_carry_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ip(0),
      I1 => \id_counter__0\(0),
      O => \temp_iphc10__64_carry_i_3_n_0\
    );
\temp_iphc10__64_carry_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7887"
    )
        port map (
      I0 => ip(2),
      I1 => \id_counter__0\(2),
      I2 => ip(3),
      I3 => \id_counter__0\(3),
      O => \temp_iphc10__64_carry_i_4_n_0\
    );
\temp_iphc10__64_carry_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => ip(1),
      I1 => \id_counter__0\(1),
      I2 => ip(2),
      I3 => \id_counter__0\(2),
      O => \temp_iphc10__64_carry_i_5_n_0\
    );
\temp_iphc10__64_carry_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8778"
    )
        port map (
      I0 => \id_counter__0\(0),
      I1 => ip(0),
      I2 => ip(1),
      I3 => \id_counter__0\(1),
      O => \temp_iphc10__64_carry_i_6_n_0\
    );
\temp_iphc10__64_carry_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => ip(0),
      I1 => \id_counter__0\(0),
      O => \temp_iphc10__64_carry_i_7_n_0\
    );
\temp_iphc1[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \temp_iphc10__0_carry_n_7\,
      I1 => \temp_iphc10__64_carry_n_7\,
      O => \temp_iphc1[0]_i_1_n_0\
    );
\temp_iphc1[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"E11E"
    )
        port map (
      I0 => \temp_iphc10__0_carry_n_7\,
      I1 => \temp_iphc10__64_carry_n_7\,
      I2 => \temp_iphc10__0_carry_n_6\,
      I3 => \temp_iphc10__64_carry_n_6\,
      O => \temp_iphc1[1]_i_1_n_0\
    );
\temp_iphc1[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => tx_ready,
      I1 => id_counter121_out,
      O => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1[23]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => temp_iphc1,
      I1 => ip_header_calc_done,
      O => \temp_iphc1[23]_i_2_n_0\
    );
\temp_iphc1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc1[0]_i_1_n_0\,
      Q => \temp_iphc1_reg_n_0_[0]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__1_n_6\,
      Q => \temp_iphc1_reg_n_0_[10]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__1_n_5\,
      Q => \temp_iphc1_reg_n_0_[11]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__1_n_4\,
      Q => \temp_iphc1_reg_n_0_[12]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__2_n_7\,
      Q => \temp_iphc1_reg_n_0_[13]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__2_n_6\,
      Q => \temp_iphc1_reg_n_0_[14]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__2_n_5\,
      Q => \temp_iphc1_reg_n_0_[15]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__2_n_4\,
      Q => \temp_iphc1_reg_n_0_[16]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__3_n_7\,
      Q => \temp_iphc1_reg_n_0_[17]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__3_n_6\,
      Q => \temp_iphc1_reg_n_0_[18]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__3_n_5\,
      Q => \temp_iphc1_reg_n_0_[19]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc1[1]_i_1_n_0\,
      Q => \temp_iphc1_reg_n_0_[1]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__3_n_4\,
      Q => \temp_iphc1_reg_n_0_[20]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__4_n_7\,
      Q => \temp_iphc1_reg_n_0_[21]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__4_n_6\,
      Q => \temp_iphc1_reg_n_0_[22]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__4_n_5\,
      Q => \temp_iphc1_reg_n_0_[23]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry_n_6\,
      Q => \temp_iphc1_reg_n_0_[2]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry_n_5\,
      Q => \temp_iphc1_reg_n_0_[3]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry_n_4\,
      Q => \temp_iphc1_reg_n_0_[4]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__0_n_7\,
      Q => \temp_iphc1_reg_n_0_[5]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__0_n_6\,
      Q => \temp_iphc1_reg_n_0_[6]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__0_n_5\,
      Q => \temp_iphc1_reg_n_0_[7]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__0_n_4\,
      Q => \temp_iphc1_reg_n_0_[8]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc1_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc1[23]_i_2_n_0\,
      D => \temp_iphc10__110_carry__1_n_7\,
      Q => \temp_iphc1_reg_n_0_[9]\,
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(0),
      O => \not\(0)
    );
\temp_iphc2[10]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(10),
      O => \not\(10)
    );
\temp_iphc2[11]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(11),
      O => \not\(11)
    );
\temp_iphc2[12]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(12),
      O => \not\(12)
    );
\temp_iphc2[13]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(13),
      O => \not\(13)
    );
\temp_iphc2[14]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(14),
      O => \not\(14)
    );
\temp_iphc2[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => temp_iphc2,
      I1 => ip_header_calc_done,
      O => \temp_iphc2[15]_i_1_n_0\
    );
\temp_iphc2[15]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(15),
      O => \not\(15)
    );
\temp_iphc2[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(1),
      O => \not\(1)
    );
\temp_iphc2[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(2),
      O => \not\(2)
    );
\temp_iphc2[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(3),
      O => \not\(3)
    );
\temp_iphc2[4]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(4),
      O => \not\(4)
    );
\temp_iphc2[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(5),
      O => \not\(5)
    );
\temp_iphc2[6]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(6),
      O => \not\(6)
    );
\temp_iphc2[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(7),
      O => \not\(7)
    );
\temp_iphc2[8]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(8),
      O => \not\(8)
    );
\temp_iphc2[9]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => L(9),
      O => \not\(9)
    );
\temp_iphc2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(0),
      Q => \temp_iphc2__0\(0),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(10),
      Q => \temp_iphc2__0\(10),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(11),
      Q => \temp_iphc2__0\(11),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(12),
      Q => \temp_iphc2__0\(12),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(13),
      Q => \temp_iphc2__0\(13),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(14),
      Q => \temp_iphc2__0\(14),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(15),
      Q => \temp_iphc2__0\(15),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(1),
      Q => \temp_iphc2__0\(1),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(2),
      Q => \temp_iphc2__0\(2),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(3),
      Q => \temp_iphc2__0\(3),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(4),
      Q => \temp_iphc2__0\(4),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(5),
      Q => \temp_iphc2__0\(5),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(6),
      Q => \temp_iphc2__0\(6),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(7),
      Q => \temp_iphc2__0\(7),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(8),
      Q => \temp_iphc2__0\(8),
      R => \temp_iphc1[23]_i_1_n_0\
    );
\temp_iphc2_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => \temp_iphc2[15]_i_1_n_0\,
      D => \not\(9),
      Q => \temp_iphc2__0\(9),
      R => \temp_iphc1[23]_i_1_n_0\
    );
tx_data_valid_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^udp_send_data_valid17_out\,
      I1 => db_sw,
      I2 => E(0),
      O => db_sw_reg
    );
tx_done_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => txen_i_2_n_0,
      I1 => \state_reg_n_0_[2]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \state_reg_n_0_[1]\,
      O => tx_done_i_1_n_0
    );
tx_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => eth_rstn,
      D => tx_done_i_1_n_0,
      Q => tx_done,
      R => '0'
    );
tx_ready_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => arp_reply_reg_n_0,
      I1 => tx_done,
      O => eth_type118_out
    );
tx_ready_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => id_counter121_out,
      I1 => tx_done,
      O => eth_type1
    );
tx_ready_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => eth_type1,
      Q => tx_ready,
      S => eth_type118_out
    );
\txd1_inferred__4/i__carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \NLW_txd1_inferred__4/i__carry_CO_UNCONNECTED\(3),
      CO(2) => \txd1_inferred__4/i__carry_n_1\,
      CO(1) => \txd1_inferred__4/i__carry_n_2\,
      CO(0) => \txd1_inferred__4/i__carry_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => \i__carry_i_1__0_n_0\,
      DI(1) => \i__carry_i_2__1_n_0\,
      DI(0) => '0',
      O(3 downto 0) => txd1(5 downto 2),
      S(3) => \i__carry_i_3__2_n_0\,
      S(2) => \i__carry_i_4__2_n_0\,
      S(1) => \i__carry_i_5__2_n_0\,
      S(0) => \i__carry_i_6__2_n_0\
    );
\txd[0]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \byte_count_reg_n_0_[5]\,
      I1 => \byte_count_reg_n_0_[6]\,
      O => \txd[0]_i_11_n_0\
    );
\txd[0]_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFF8"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[8]\,
      I4 => \byte_count_reg_n_0_[9]\,
      I5 => \byte_count_reg_n_0_[10]\,
      O => \txd[0]_i_12_n_0\
    );
\txd[0]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF000FEEEEEEEE"
    )
        port map (
      I0 => \txd[0]_i_30_n_0\,
      I1 => \txd[0]_i_31_n_0\,
      I2 => \txd[0]_i_32_n_0\,
      I3 => \bit_count_reg_n_0_[0]\,
      I4 => \txd[0]_i_33_n_0\,
      I5 => \txd[1]_i_20_n_0\,
      O => \txd[0]_i_13_n_0\
    );
\txd[0]_i_14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000F0F03000A0A"
    )
        port map (
      I0 => tx_ready,
      I1 => \bit_count_reg_n_0_[3]\,
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => \txd[0]_i_34_n_0\,
      I4 => \state_reg_n_0_[1]\,
      I5 => \state_reg_n_0_[0]\,
      O => \txd[0]_i_14_n_0\
    );
\txd[0]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2EEE0000FFFFFFFF"
    )
        port map (
      I0 => \txd[0]_i_35_n_0\,
      I1 => bit_count223_in,
      I2 => \i__carry_i_9__0_n_0\,
      I3 => crc_calculator_n_2,
      I4 => \state_reg_n_0_[0]\,
      I5 => \byte_count[10]_i_9__0_n_0\,
      O => \txd[0]_i_15_n_0\
    );
\txd[0]_i_16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0101015151515151"
    )
        port map (
      I0 => txen_i_3_n_0,
      I1 => \txd_reg[0]_i_37_n_0\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \txd[0]_i_38_n_0\,
      I5 => \txd[0]_i_39_n_0\,
      O => \txd[0]_i_16_n_0\
    );
\txd[0]_i_17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF1F110000"
    )
        port map (
      I0 => \txd[0]_i_40_n_0\,
      I1 => \txd[0]_i_41_n_0\,
      I2 => \txd[0]_i_42_n_0\,
      I3 => \txd[0]_i_43_n_0\,
      I4 => \txd[0]_i_44_n_0\,
      I5 => \txd[0]_i_45_n_0\,
      O => \txd[0]_i_17_n_0\
    );
\txd[0]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[26]\,
      I1 => \dest_mac_reg_n_0_[10]\,
      I2 => \txd_reg[0]_i_9_n_6\,
      I3 => \dest_mac_reg_n_0_[18]\,
      I4 => \txd_reg[0]_i_9_n_5\,
      I5 => \dest_mac_reg_n_0_[2]\,
      O => \txd[0]_i_20_n_0\
    );
\txd[0]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[30]\,
      I1 => \dest_mac_reg_n_0_[14]\,
      I2 => \txd_reg[0]_i_9_n_6\,
      I3 => \dest_mac_reg_n_0_[22]\,
      I4 => \txd_reg[0]_i_9_n_5\,
      I5 => \dest_mac_reg_n_0_[6]\,
      O => \txd[0]_i_21_n_0\
    );
\txd[0]_i_22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[28]\,
      I1 => \dest_mac_reg_n_0_[12]\,
      I2 => \txd_reg[0]_i_9_n_6\,
      I3 => \dest_mac_reg_n_0_[20]\,
      I4 => \txd_reg[0]_i_9_n_5\,
      I5 => \dest_mac_reg_n_0_[4]\,
      O => \txd[0]_i_22_n_0\
    );
\txd[0]_i_23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[24]\,
      I1 => \dest_mac_reg_n_0_[8]\,
      I2 => \txd_reg[0]_i_9_n_6\,
      I3 => \dest_mac_reg_n_0_[16]\,
      I4 => \txd_reg[0]_i_9_n_5\,
      I5 => \dest_mac_reg_n_0_[0]\,
      O => \txd[0]_i_23_n_0\
    );
\txd[0]_i_24\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \byte_count_reg_n_0_[0]\,
      O => \txd[0]_i_24_n_0\
    );
\txd[0]_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \byte_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[1]\,
      O => \txd[0]_i_25_n_0\
    );
\txd[0]_i_26\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \bit_count_reg_n_0_[3]\,
      O => \txd[0]_i_26_n_0\
    );
\txd[0]_i_27\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \byte_count_reg_n_0_[0]\,
      I1 => \bit_count_reg_n_0_[2]\,
      O => \txd[0]_i_27_n_0\
    );
\txd[0]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000F5353F0FF5353"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[40]\,
      I1 => \dest_mac_reg_n_0_[32]\,
      I2 => \txd_reg[0]_i_9_n_6\,
      I3 => \dest_mac_reg_n_0_[36]\,
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => \dest_mac_reg_n_0_[44]\,
      O => \txd[0]_i_28_n_0\
    );
\txd[0]_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000F5353F0FF5353"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[42]\,
      I1 => \dest_mac_reg_n_0_[34]\,
      I2 => \txd_reg[0]_i_9_n_6\,
      I3 => \dest_mac_reg_n_0_[38]\,
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => \dest_mac_reg_n_0_[46]\,
      O => \txd[0]_i_29_n_0\
    );
\txd[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \state_reg_n_0_[1]\,
      I1 => \state_reg_n_0_[0]\,
      O => \txd[0]_i_3_n_0\
    );
\txd[0]_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7333733353007333"
    )
        port map (
      I0 => \txd[1]_i_24_n_0\,
      I1 => \txd[0]_i_49_n_0\,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \bit_count_reg_n_0_[1]\,
      I4 => byte0(2),
      I5 => \bit_count_reg_n_0_[2]\,
      O => \txd[0]_i_30_n_0\
    );
\txd[0]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAA8AAAAA"
    )
        port map (
      I0 => \txd[0]_i_49_n_0\,
      I1 => \txd_reg[1]_i_72_n_5\,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \txd_reg[0]_i_9_n_7\,
      I4 => eth_type(1),
      I5 => \txd_reg[1]_i_72_n_6\,
      O => \txd[0]_i_31_n_0\
    );
\txd[0]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00CC003300FFCCB8"
    )
        port map (
      I0 => ip(4),
      I1 => \bit_count_reg_n_0_[1]\,
      I2 => ip(0),
      I3 => \txd_reg[1]_i_38_n_4\,
      I4 => \txd_reg[1]_i_38_n_6\,
      I5 => \txd_reg[1]_i_38_n_5\,
      O => \txd[0]_i_32_n_0\
    );
\txd[0]_i_33\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAA8800AAAAAA02"
    )
        port map (
      I0 => \bit_count_reg_n_0_[0]\,
      I1 => \bit_count_reg_n_0_[1]\,
      I2 => ip(2),
      I3 => \txd_reg[1]_i_38_n_5\,
      I4 => \txd_reg[1]_i_38_n_4\,
      I5 => \txd_reg[1]_i_38_n_6\,
      O => \txd[0]_i_33_n_0\
    );
\txd[0]_i_34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[46]\,
      I1 => \dest_mac_reg_n_0_[44]\,
      I2 => \bit_count_reg_n_0_[1]\,
      I3 => \dest_mac_reg_n_0_[42]\,
      I4 => \bit_count_reg_n_0_[0]\,
      I5 => \dest_mac_reg_n_0_[40]\,
      O => \txd[0]_i_34_n_0\
    );
\txd[0]_i_35\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F3300550F33FF55"
    )
        port map (
      I0 => \txd[0]_i_50_n_0\,
      I1 => \txd[0]_i_51_n_0\,
      I2 => \txd[0]_i_52_n_0\,
      I3 => \bit_count_reg_n_0_[0]\,
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => \txd[0]_i_53_n_0\,
      O => \txd[0]_i_35_n_0\
    );
\txd[0]_i_38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F2FEF3F3F2FEFFFF"
    )
        port map (
      I0 => \txd[0]_i_58_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => \txd[0]_i_59_n_0\,
      I4 => \byte_count_reg_n_0_[0]\,
      I5 => \txd[0]_i_60_n_0\,
      O => \txd[0]_i_38_n_0\
    );
\txd[0]_i_39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF77F377FF77FF77"
    )
        port map (
      I0 => \txd[0]_i_61_n_0\,
      I1 => \byte_count_reg_n_0_[2]\,
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \txd[0]_i_62_n_0\,
      I5 => \txd[0]_i_63_n_0\,
      O => \txd[0]_i_39_n_0\
    );
\txd[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBFBFBAB"
    )
        port map (
      I0 => \txd[1]_i_24_n_0\,
      I1 => \txd[0]_i_8_n_0\,
      I2 => \txd_reg[0]_i_9_n_4\,
      I3 => \txd_reg[0]_i_10_n_0\,
      I4 => \txd_reg[0]_i_9_n_5\,
      O => \txd[0]_i_4_n_0\
    );
\txd[0]_i_40\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEEEEEFEEEFEE"
    )
        port map (
      I0 => \bit_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \txd[0]_i_64_n_0\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \bit_count[3]_i_7_n_0\,
      I5 => \txd[0]_i_65_n_0\,
      O => \txd[0]_i_40_n_0\
    );
\txd[0]_i_41\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000FD"
    )
        port map (
      I0 => \txd[0]_i_66_n_0\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \txd[0]_i_67_n_0\,
      O => \txd[0]_i_41_n_0\
    );
\txd[0]_i_42\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0033550FFF33550F"
    )
        port map (
      I0 => \txd[0]_i_68_n_0\,
      I1 => \txd[0]_i_69_n_0\,
      I2 => \txd[0]_i_70_n_0\,
      I3 => \byte_count_reg_n_0_[0]\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \txd[0]_i_71_n_0\,
      O => \txd[0]_i_42_n_0\
    );
\txd[0]_i_43\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \bit_count_reg_n_0_[2]\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[2]\,
      O => \txd[0]_i_43_n_0\
    );
\txd[0]_i_44\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \byte_count_reg_n_0_[4]\,
      I1 => \byte_count_reg_n_0_[8]\,
      I2 => \byte_count_reg_n_0_[7]\,
      I3 => \byte_count_reg_n_0_[6]\,
      I4 => \byte_count_reg_n_0_[5]\,
      I5 => txen_i_4_n_0,
      O => \txd[0]_i_44_n_0\
    );
\txd[0]_i_45\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BAAA"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \txd[0]_i_35_n_0\,
      I2 => \byte_count[4]_i_5_n_0\,
      I3 => \state[1]_i_5__1_n_0\,
      O => \txd[0]_i_45_n_0\
    );
\txd[0]_i_49\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000020000"
    )
        port map (
      I0 => \state[2]_i_7__0_n_0\,
      I1 => \state[0]_i_9__0_n_0\,
      I2 => \txd[0]_i_11_n_0\,
      I3 => \byte_count_reg_n_0_[4]\,
      I4 => \i__carry_i_12_n_0\,
      I5 => \byte_count_reg_n_0_[1]\,
      O => \txd[0]_i_49_n_0\
    );
\txd[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFFFD"
    )
        port map (
      I0 => \byte_count[10]_i_17__0_n_0\,
      I1 => \byte_count_reg_n_0_[4]\,
      I2 => \txd[0]_i_11_n_0\,
      I3 => \byte_count_reg_n_0_[7]\,
      I4 => \txd[0]_i_12_n_0\,
      I5 => \txd[0]_i_13_n_0\,
      O => \txd[0]_i_5_n_0\
    );
\txd[0]_i_50\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => fifo_read_data(0),
      I1 => fifo_read_data(16),
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => fifo_read_data(8),
      I4 => \bit_count_reg_n_0_[3]\,
      I5 => fifo_read_data(24),
      O => \txd[0]_i_50_n_0\
    );
\txd[0]_i_51\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => fifo_read_data(4),
      I1 => fifo_read_data(20),
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => fifo_read_data(12),
      I4 => \bit_count_reg_n_0_[3]\,
      I5 => fifo_read_data(28),
      O => \txd[0]_i_51_n_0\
    );
\txd[0]_i_52\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => fifo_read_data(6),
      I1 => fifo_read_data(22),
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => fifo_read_data(14),
      I4 => \bit_count_reg_n_0_[3]\,
      I5 => fifo_read_data(30),
      O => \txd[0]_i_52_n_0\
    );
\txd[0]_i_53\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => fifo_read_data(2),
      I1 => fifo_read_data(18),
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => fifo_read_data(10),
      I4 => \bit_count_reg_n_0_[3]\,
      I5 => fifo_read_data(26),
      O => \txd[0]_i_53_n_0\
    );
\txd[0]_i_56\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8BBFFFFB8BB0000"
    )
        port map (
      I0 => \txd[0]_i_80_n_0\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => \txd[0]_i_81_n_0\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \txd[0]_i_82_n_0\,
      O => \txd[0]_i_56_n_0\
    );
\txd[0]_i_57\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FAFBFFFB"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \txd[0]_i_83_n_0\,
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[0]\,
      I4 => \txd[0]_i_84_n_0\,
      O => \txd[0]_i_57_n_0\
    );
\txd[0]_i_58\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F4F7"
    )
        port map (
      I0 => byte12(7),
      I1 => \bit_count_reg_n_0_[1]\,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \byte8_reg_n_0_[7]\,
      O => \txd[0]_i_58_n_0\
    );
\txd[0]_i_59\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte11(6),
      I1 => byte11(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte11(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte11(0),
      O => \txd[0]_i_59_n_0\
    );
\txd[0]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF04"
    )
        port map (
      I0 => \state[0]_i_2_n_0\,
      I1 => \state_reg_n_0_[1]\,
      I2 => \state_reg_n_0_[0]\,
      I3 => \txd[0]_i_14_n_0\,
      O => \txd[0]_i_6_n_0\
    );
\txd[0]_i_60\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte10(6),
      I1 => byte10(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte10(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte10(0),
      O => \txd[0]_i_60_n_0\
    );
\txd[0]_i_61\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2323232020232020"
    )
        port map (
      I0 => \txd[0]_i_85_n_0\,
      I1 => \bit_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[0]\,
      I3 => \byte_count[10]_i_14__0_n_0\,
      I4 => byte9(3),
      I5 => byte12(7),
      O => \txd[0]_i_61_n_0\
    );
\txd[0]_i_62\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00003DFD"
    )
        port map (
      I0 => \byte8_reg_n_0_[7]\,
      I1 => \bit_count_reg_n_0_[0]\,
      I2 => \bit_count_reg_n_0_[1]\,
      I3 => byte9(3),
      I4 => \byte_count_reg_n_0_[0]\,
      O => \txd[0]_i_62_n_0\
    );
\txd[0]_i_63\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0FAFAFFF0FCFCF"
    )
        port map (
      I0 => byte15(4),
      I1 => byte15(0),
      I2 => \byte_count_reg_n_0_[0]\,
      I3 => byte15(2),
      I4 => \bit_count_reg_n_0_[0]\,
      I5 => \bit_count_reg_n_0_[1]\,
      O => \txd[0]_i_63_n_0\
    );
\txd[0]_i_64\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FAC00AC0"
    )
        port map (
      I0 => \txd[0]_i_86_n_0\,
      I1 => \txd[0]_i_87_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[0]\,
      I4 => \txd[0]_i_88_n_0\,
      O => \txd[0]_i_64_n_0\
    );
\txd[0]_i_65\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte20(6),
      I1 => byte20(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte20(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte20(0),
      O => \txd[0]_i_65_n_0\
    );
\txd[0]_i_66\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte16(6),
      I1 => byte16(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte16(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte16(0),
      O => \txd[0]_i_66_n_0\
    );
\txd[0]_i_67\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FAC00AC0"
    )
        port map (
      I0 => \txd[0]_i_89_n_0\,
      I1 => \txd[0]_i_90_n_0\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[0]\,
      I4 => \txd[0]_i_91_n_0\,
      O => \txd[0]_i_67_n_0\
    );
\txd[0]_i_68\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte25(6),
      I1 => byte25(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte25(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte25(0),
      O => \txd[0]_i_68_n_0\
    );
\txd[0]_i_69\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte26(6),
      I1 => byte26(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte26(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte26(0),
      O => \txd[0]_i_69_n_0\
    );
\txd[0]_i_70\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte24(6),
      I1 => byte24(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte24(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte24(0),
      O => \txd[0]_i_70_n_0\
    );
\txd[0]_i_71\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte27(6),
      I1 => byte27(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte27(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte27(0),
      O => \txd[0]_i_71_n_0\
    );
\txd[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCAACCAAF0FFF000"
    )
        port map (
      I0 => \txd[0]_i_20_n_0\,
      I1 => \txd[0]_i_21_n_0\,
      I2 => \txd[0]_i_22_n_0\,
      I3 => \bit_count_reg_n_0_[1]\,
      I4 => \txd[0]_i_23_n_0\,
      I5 => \bit_count_reg_n_0_[0]\,
      O => \txd[0]_i_8_n_0\
    );
\txd[0]_i_80\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABFAFBFFABFFFBF"
    )
        port map (
      I0 => \bit_count_reg_n_0_[2]\,
      I1 => byte3(4),
      I2 => \bit_count_reg_n_0_[1]\,
      I3 => \bit_count_reg_n_0_[0]\,
      I4 => byte3(2),
      I5 => byte3(6),
      O => \txd[0]_i_80_n_0\
    );
\txd[0]_i_81\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \byte2_reg_n_0_[6]\,
      I1 => \byte2_reg_n_0_[2]\,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \byte2_reg_n_0_[4]\,
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => \byte2_reg_n_0_[0]\,
      O => \txd[0]_i_81_n_0\
    );
\txd[0]_i_82\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFCFC4FFF7"
    )
        port map (
      I0 => byte9(3),
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \bit_count_reg_n_0_[1]\,
      I4 => byte0(2),
      I5 => \bit_count_reg_n_0_[2]\,
      O => \txd[0]_i_82_n_0\
    );
\txd[0]_i_83\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte4(6),
      I1 => byte4(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte4(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte4(0),
      O => \txd[0]_i_83_n_0\
    );
\txd[0]_i_84\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \byte5_reg_n_0_[6]\,
      I1 => \byte5_reg_n_0_[2]\,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \byte5_reg_n_0_[4]\,
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => \byte5_reg_n_0_[0]\,
      O => \txd[0]_i_84_n_0\
    );
\txd[0]_i_85\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte9(3),
      I1 => byte13(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte13(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte13(0),
      O => \txd[0]_i_85_n_0\
    );
\txd[0]_i_86\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte21(6),
      I1 => byte21(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte21(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte21(0),
      O => \txd[0]_i_86_n_0\
    );
\txd[0]_i_87\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte22(6),
      I1 => byte22(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte22(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte22(0),
      O => \txd[0]_i_87_n_0\
    );
\txd[0]_i_88\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte23(6),
      I1 => byte23(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte23(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte23(0),
      O => \txd[0]_i_88_n_0\
    );
\txd[0]_i_89\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte17(6),
      I1 => byte17(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte17(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte17(0),
      O => \txd[0]_i_89_n_0\
    );
\txd[0]_i_90\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \byte18_reg_n_0_[6]\,
      I1 => \byte18_reg_n_0_[2]\,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \byte18_reg_n_0_[4]\,
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => \byte18_reg_n_0_[0]\,
      O => \txd[0]_i_90_n_0\
    );
\txd[0]_i_91\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte19(6),
      I1 => byte19(2),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte19(4),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte19(0),
      O => \txd[0]_i_91_n_0\
    );
\txd[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => txd0,
      I1 => eth_txd(1),
      I2 => \txd[1]_i_3_n_0\,
      O => \txd[1]_i_1_n_0\
    );
\txd[1]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEAEAEAEAEAE"
    )
        port map (
      I0 => txen_i_3_n_0,
      I1 => \txd_reg[1]_i_26_n_0\,
      I2 => \byte_count_reg_n_0_[3]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \txd[1]_i_27_n_0\,
      I5 => \txd[1]_i_28_n_0\,
      O => \txd[1]_i_10_n_0\
    );
\txd[1]_i_100\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \byte_count_reg_n_0_[0]\,
      I1 => \bit_count_reg_n_0_[2]\,
      O => \txd[1]_i_100_n_0\
    );
\txd[1]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEEFFF0FFEE"
    )
        port map (
      I0 => \txd[1]_i_29_n_0\,
      I1 => \txd[1]_i_30_n_0\,
      I2 => \txd[1]_i_31_n_0\,
      I3 => \bit_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => \byte_count_reg_n_0_[2]\,
      O => \txd[1]_i_11_n_0\
    );
\txd[1]_i_12\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"BAAA"
    )
        port map (
      I0 => \state_reg_n_0_[0]\,
      I1 => \txd[1]_i_32_n_0\,
      I2 => \byte_count[4]_i_5_n_0\,
      I3 => \state[1]_i_5__1_n_0\,
      O => \txd[1]_i_12_n_0\
    );
\txd[1]_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2EEE0000FFFFFFFF"
    )
        port map (
      I0 => \txd[1]_i_32_n_0\,
      I1 => bit_count223_in,
      I2 => \i__carry_i_9__0_n_0\,
      I3 => crc_calculator_n_1,
      I4 => \state_reg_n_0_[0]\,
      I5 => \byte_count[10]_i_9__0_n_0\,
      O => \txd[1]_i_13_n_0\
    );
\txd[1]_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFBFF"
    )
        port map (
      I0 => txd1(5),
      I1 => \state[2]_i_7__0_n_0\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \state_reg_n_0_[0]\,
      I4 => \byte_count_reg_n_0_[3]\,
      I5 => txen_i_3_n_0,
      O => \txd[1]_i_15_n_0\
    );
\txd[1]_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFE8E8F"
    )
        port map (
      I0 => \bit_count_reg_n_0_[1]\,
      I1 => \txd_reg[1]_i_38_n_5\,
      I2 => \txd_reg[1]_i_38_n_6\,
      I3 => ip(3),
      I4 => \txd_reg[1]_i_38_n_4\,
      O => \txd[1]_i_18_n_0\
    );
\txd[1]_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF55FF45"
    )
        port map (
      I0 => \txd_reg[1]_i_38_n_6\,
      I1 => \bit_count_reg_n_0_[1]\,
      I2 => ip(1),
      I3 => \txd_reg[1]_i_38_n_4\,
      I4 => \txd_reg[1]_i_38_n_5\,
      O => \txd[1]_i_19_n_0\
    );
\txd[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D0DF0000"
    )
        port map (
      I0 => \state_reg_n_0_[1]\,
      I1 => \txd[1]_i_4_n_0\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \bit_count_reg[3]_i_4_n_0\,
      I4 => eth_rstn,
      O => txd0
    );
\txd[1]_i_20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001404"
    )
        port map (
      I0 => txen_i_3_n_0,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \bit_count_reg_n_0_[3]\,
      I5 => \bit_count_reg_n_0_[2]\,
      O => \txd[1]_i_20_n_0\
    );
\txd[1]_i_21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000073300000000"
    )
        port map (
      I0 => \txd[1]_i_39_n_0\,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => txen_i_3_n_0,
      I5 => \state[2]_i_7__0_n_0\,
      O => \txd[1]_i_21_n_0\
    );
\txd[1]_i_24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFDFFFFFFFF"
    )
        port map (
      I0 => \state[2]_i_7__0_n_0\,
      I1 => \state[0]_i_9__0_n_0\,
      I2 => \byte_count_reg_n_0_[5]\,
      I3 => \byte_count_reg_n_0_[6]\,
      I4 => \byte_count_reg_n_0_[4]\,
      I5 => \txd[1]_i_44_n_0\,
      O => \txd[1]_i_24_n_0\
    );
\txd[1]_i_25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2020200000002000"
    )
        port map (
      I0 => \state_reg_n_0_[1]\,
      I1 => \state_reg_n_0_[0]\,
      I2 => \state[2]_i_7__0_n_0\,
      I3 => \byte_count[10]_i_14__0_n_0\,
      I4 => \state[0]_i_6__0_n_0\,
      I5 => \txd[1]_i_45_n_0\,
      O => \txd[1]_i_25_n_0\
    );
\txd[1]_i_27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DFDDDFFF"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \bit_count_reg_n_0_[2]\,
      I2 => \txd[1]_i_48_n_0\,
      I3 => \byte_count_reg_n_0_[0]\,
      I4 => \txd[1]_i_49_n_0\,
      I5 => \txd[1]_i_50_n_0\,
      O => \txd[1]_i_27_n_0\
    );
\txd[1]_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F2F2FFFFFF00FFFF"
    )
        port map (
      I0 => \txd[1]_i_51_n_0\,
      I1 => \txd[1]_i_52_n_0\,
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => \txd[1]_i_53_n_0\,
      I4 => \byte_count_reg_n_0_[2]\,
      I5 => \byte_count_reg_n_0_[1]\,
      O => \txd[1]_i_28_n_0\
    );
\txd[1]_i_29\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000F700"
    )
        port map (
      I0 => \txd[1]_i_54_n_0\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \byte_count_reg_n_0_[1]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \txd[1]_i_55_n_0\,
      O => \txd[1]_i_29_n_0\
    );
\txd[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EEEEEFEEEFEFEFEF"
    )
        port map (
      I0 => \txd[1]_i_5_n_0\,
      I1 => crc_calculator_n_0,
      I2 => \state_reg_n_0_[2]\,
      I3 => \txd[1]_i_7_n_0\,
      I4 => \txd[1]_i_8_n_0\,
      I5 => \txd[1]_i_9_n_0\,
      O => \txd[1]_i_3_n_0\
    );
\txd[1]_i_30\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000F7"
    )
        port map (
      I0 => \txd[1]_i_56_n_0\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[0]\,
      I3 => \byte_count_reg_n_0_[2]\,
      I4 => \txd[1]_i_57_n_0\,
      O => \txd[1]_i_30_n_0\
    );
\txd[1]_i_31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0055330FFF55330F"
    )
        port map (
      I0 => \txd[1]_i_58_n_0\,
      I1 => \txd[1]_i_59_n_0\,
      I2 => \txd[1]_i_60_n_0\,
      I3 => \byte_count_reg_n_0_[0]\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \txd[1]_i_61_n_0\,
      O => \txd[1]_i_31_n_0\
    );
\txd[1]_i_32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F3300550F33FF55"
    )
        port map (
      I0 => \txd[1]_i_62_n_0\,
      I1 => \txd[1]_i_63_n_0\,
      I2 => \txd[1]_i_64_n_0\,
      I3 => \bit_count_reg_n_0_[0]\,
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => \txd[1]_i_65_n_0\,
      O => \txd[1]_i_32_n_0\
    );
\txd[1]_i_39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBBFFEFFFFFFFEF"
    )
        port map (
      I0 => \txd_reg[1]_i_72_n_5\,
      I1 => \txd_reg[1]_i_72_n_6\,
      I2 => eth_type(1),
      I3 => \txd_reg[0]_i_9_n_7\,
      I4 => \bit_count_reg_n_0_[0]\,
      I5 => eth_type(11),
      O => \txd[1]_i_39_n_0\
    );
\txd[1]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBBFC8800000000"
    )
        port map (
      I0 => txen_i_2_n_0,
      I1 => \state_reg_n_0_[0]\,
      I2 => bit_count233_in,
      I3 => \state[2]_i_7__0_n_0\,
      I4 => \bit_count0_inferred__0/i__carry__0_n_2\,
      I5 => \state_reg_n_0_[1]\,
      O => \txd[1]_i_4_n_0\
    );
\txd[1]_i_44\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"15"
    )
        port map (
      I0 => \byte_count_reg_n_0_[3]\,
      I1 => \byte_count_reg_n_0_[1]\,
      I2 => \byte_count_reg_n_0_[2]\,
      O => \txd[1]_i_44_n_0\
    );
\txd[1]_i_45\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[47]\,
      I1 => \dest_mac_reg_n_0_[45]\,
      I2 => \bit_count_reg_n_0_[1]\,
      I3 => \dest_mac_reg_n_0_[43]\,
      I4 => \bit_count_reg_n_0_[0]\,
      I5 => \dest_mac_reg_n_0_[41]\,
      O => \txd[1]_i_45_n_0\
    );
\txd[1]_i_46\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FD0DFFFF"
    )
        port map (
      I0 => \txd[1]_i_81_n_0\,
      I1 => \bit_count_reg_n_0_[2]\,
      I2 => \byte_count_reg_n_0_[0]\,
      I3 => \txd[1]_i_82_n_0\,
      I4 => \byte_count_reg_n_0_[1]\,
      O => \txd[1]_i_46_n_0\
    );
\txd[1]_i_47\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFF1FFFD"
    )
        port map (
      I0 => \txd[1]_i_83_n_0\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \txd[1]_i_84_n_0\,
      I5 => \txd[1]_i_85_n_0\,
      O => \txd[1]_i_47_n_0\
    );
\txd[1]_i_48\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte11(7),
      I1 => byte11(3),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte11(5),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte11(1),
      O => \txd[1]_i_48_n_0\
    );
\txd[1]_i_49\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte10(7),
      I1 => byte10(3),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte10(5),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte10(1),
      O => \txd[1]_i_49_n_0\
    );
\txd[1]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFF5575"
    )
        port map (
      I0 => \txd[1]_i_10_n_0\,
      I1 => \txd[1]_i_11_n_0\,
      I2 => \byte_count_reg_n_0_[4]\,
      I3 => \bit_count[3]_i_8_n_0\,
      I4 => \txd[1]_i_12_n_0\,
      I5 => \txd[1]_i_13_n_0\,
      O => \txd[1]_i_5_n_0\
    );
\txd[1]_i_50\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00000040"
    )
        port map (
      I0 => \bit_count_reg_n_0_[2]\,
      I1 => \byte_count[10]_i_14__0_n_0\,
      I2 => \byte8_reg_n_0_[7]\,
      I3 => \byte_count_reg_n_0_[0]\,
      I4 => \byte_count_reg_n_0_[1]\,
      I5 => \txd[1]_i_86_n_0\,
      O => \txd[1]_i_50_n_0\
    );
\txd[1]_i_51\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => byte9(3),
      I1 => \bit_count_reg_n_0_[0]\,
      I2 => \bit_count_reg_n_0_[1]\,
      O => \txd[1]_i_51_n_0\
    );
\txd[1]_i_52\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08AA08A0080A0800"
    )
        port map (
      I0 => \byte_count_reg_n_0_[0]\,
      I1 => byte15(3),
      I2 => \bit_count_reg_n_0_[1]\,
      I3 => \bit_count_reg_n_0_[0]\,
      I4 => byte15(1),
      I5 => byte12(7),
      O => \txd[1]_i_52_n_0\
    );
\txd[1]_i_53\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FF1BFFFFFF1B"
    )
        port map (
      I0 => \byte_count[10]_i_14__0_n_0\,
      I1 => byte9(3),
      I2 => byte12(7),
      I3 => \bit_count_reg_n_0_[2]\,
      I4 => \byte_count_reg_n_0_[0]\,
      I5 => \txd[1]_i_87_n_0\,
      O => \txd[1]_i_53_n_0\
    );
\txd[1]_i_54\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte21(7),
      I1 => byte21(3),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte21(5),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte21(1),
      O => \txd[1]_i_54_n_0\
    );
\txd[1]_i_55\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FA0C0A0C"
    )
        port map (
      I0 => \txd[1]_i_88_n_0\,
      I1 => \txd[1]_i_89_n_0\,
      I2 => \byte_count_reg_n_0_[0]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \txd[1]_i_90_n_0\,
      O => \txd[1]_i_55_n_0\
    );
\txd[1]_i_56\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \byte18_reg_n_0_[7]\,
      I1 => \byte18_reg_n_0_[3]\,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \byte18_reg_n_0_[5]\,
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => \byte18_reg_n_0_[1]\,
      O => \txd[1]_i_56_n_0\
    );
\txd[1]_i_57\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F0AC00AC"
    )
        port map (
      I0 => \txd[1]_i_91_n_0\,
      I1 => \txd[1]_i_92_n_0\,
      I2 => \byte_count_reg_n_0_[0]\,
      I3 => \byte_count_reg_n_0_[1]\,
      I4 => \txd[1]_i_93_n_0\,
      O => \txd[1]_i_57_n_0\
    );
\txd[1]_i_58\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte26(7),
      I1 => byte26(3),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte26(5),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte26(1),
      O => \txd[1]_i_58_n_0\
    );
\txd[1]_i_59\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte25(7),
      I1 => byte25(3),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte25(5),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte25(1),
      O => \txd[1]_i_59_n_0\
    );
\txd[1]_i_60\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte24(7),
      I1 => byte24(3),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte24(5),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte24(1),
      O => \txd[1]_i_60_n_0\
    );
\txd[1]_i_61\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte27(7),
      I1 => byte27(3),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte27(5),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte27(1),
      O => \txd[1]_i_61_n_0\
    );
\txd[1]_i_62\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => fifo_read_data(1),
      I1 => fifo_read_data(17),
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => fifo_read_data(9),
      I4 => \bit_count_reg_n_0_[3]\,
      I5 => fifo_read_data(25),
      O => \txd[1]_i_62_n_0\
    );
\txd[1]_i_63\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => fifo_read_data(5),
      I1 => fifo_read_data(21),
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => fifo_read_data(13),
      I4 => \bit_count_reg_n_0_[3]\,
      I5 => fifo_read_data(29),
      O => \txd[1]_i_63_n_0\
    );
\txd[1]_i_64\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => fifo_read_data(7),
      I1 => fifo_read_data(23),
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => fifo_read_data(15),
      I4 => \bit_count_reg_n_0_[3]\,
      I5 => fifo_read_data(31),
      O => \txd[1]_i_64_n_0\
    );
\txd[1]_i_65\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => fifo_read_data(3),
      I1 => fifo_read_data(19),
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => fifo_read_data(11),
      I4 => \bit_count_reg_n_0_[3]\,
      I5 => fifo_read_data(27),
      O => \txd[1]_i_65_n_0\
    );
\txd[1]_i_68\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      O => \txd[1]_i_68_n_0\
    );
\txd[1]_i_69\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \byte_count_reg_n_0_[0]\,
      O => \txd[1]_i_69_n_0\
    );
\txd[1]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF4700"
    )
        port map (
      I0 => \txd[1]_i_18_n_0\,
      I1 => \bit_count_reg_n_0_[0]\,
      I2 => \txd[1]_i_19_n_0\,
      I3 => \txd[1]_i_20_n_0\,
      I4 => \txd[1]_i_21_n_0\,
      O => \txd[1]_i_7_n_0\
    );
\txd[1]_i_70\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \bit_count_reg_n_0_[3]\,
      I1 => \byte_count_reg_n_0_[1]\,
      O => \txd[1]_i_70_n_0\
    );
\txd[1]_i_71\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \byte_count_reg_n_0_[0]\,
      I1 => \bit_count_reg_n_0_[2]\,
      O => \txd[1]_i_71_n_0\
    );
\txd[1]_i_73\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[19]\,
      I1 => \txd_reg[0]_i_9_n_5\,
      I2 => \dest_mac_reg_n_0_[35]\,
      I3 => \txd_reg[0]_i_9_n_4\,
      I4 => \dest_mac_reg_n_0_[3]\,
      O => \txd[1]_i_73_n_0\
    );
\txd[1]_i_74\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[27]\,
      I1 => \txd_reg[0]_i_9_n_5\,
      I2 => \dest_mac_reg_n_0_[43]\,
      I3 => \txd_reg[0]_i_9_n_4\,
      I4 => \dest_mac_reg_n_0_[11]\,
      O => \txd[1]_i_74_n_0\
    );
\txd[1]_i_75\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[23]\,
      I1 => \txd_reg[0]_i_9_n_5\,
      I2 => \dest_mac_reg_n_0_[39]\,
      I3 => \txd_reg[0]_i_9_n_4\,
      I4 => \dest_mac_reg_n_0_[7]\,
      O => \txd[1]_i_75_n_0\
    );
\txd[1]_i_76\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[31]\,
      I1 => \txd_reg[0]_i_9_n_5\,
      I2 => \dest_mac_reg_n_0_[47]\,
      I3 => \txd_reg[0]_i_9_n_4\,
      I4 => \dest_mac_reg_n_0_[15]\,
      O => \txd[1]_i_76_n_0\
    );
\txd[1]_i_77\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[17]\,
      I1 => \txd_reg[0]_i_9_n_5\,
      I2 => \dest_mac_reg_n_0_[33]\,
      I3 => \txd_reg[0]_i_9_n_4\,
      I4 => \dest_mac_reg_n_0_[1]\,
      O => \txd[1]_i_77_n_0\
    );
\txd[1]_i_78\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[25]\,
      I1 => \txd_reg[0]_i_9_n_5\,
      I2 => \dest_mac_reg_n_0_[41]\,
      I3 => \txd_reg[0]_i_9_n_4\,
      I4 => \dest_mac_reg_n_0_[9]\,
      O => \txd[1]_i_78_n_0\
    );
\txd[1]_i_79\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[21]\,
      I1 => \txd_reg[0]_i_9_n_5\,
      I2 => \dest_mac_reg_n_0_[37]\,
      I3 => \txd_reg[0]_i_9_n_4\,
      I4 => \dest_mac_reg_n_0_[5]\,
      O => \txd[1]_i_79_n_0\
    );
\txd[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0047FFFFFFFFFFFF"
    )
        port map (
      I0 => \txd_reg[1]_i_22_n_0\,
      I1 => \bit_count_reg_n_0_[0]\,
      I2 => \txd_reg[1]_i_23_n_0\,
      I3 => \txd[1]_i_24_n_0\,
      I4 => \state_reg_n_0_[0]\,
      I5 => \state_reg_n_0_[1]\,
      O => \txd[1]_i_8_n_0\
    );
\txd[1]_i_80\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \dest_mac_reg_n_0_[29]\,
      I1 => \txd_reg[0]_i_9_n_5\,
      I2 => \dest_mac_reg_n_0_[45]\,
      I3 => \txd_reg[0]_i_9_n_4\,
      I4 => \dest_mac_reg_n_0_[13]\,
      O => \txd[1]_i_80_n_0\
    );
\txd[1]_i_81\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \byte2_reg_n_0_[7]\,
      I1 => \byte2_reg_n_0_[3]\,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \byte2_reg_n_0_[5]\,
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => \byte2_reg_n_0_[1]\,
      O => \txd[1]_i_81_n_0\
    );
\txd[1]_i_82\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABFAFBFFABFFFBF"
    )
        port map (
      I0 => \bit_count_reg_n_0_[2]\,
      I1 => byte3(5),
      I2 => \bit_count_reg_n_0_[1]\,
      I3 => \bit_count_reg_n_0_[0]\,
      I4 => byte3(3),
      I5 => byte3(7),
      O => \txd[1]_i_82_n_0\
    );
\txd[1]_i_83\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte4(7),
      I1 => byte4(3),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte4(5),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte4(1),
      O => \txd[1]_i_83_n_0\
    );
\txd[1]_i_84\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \byte5_reg_n_0_[7]\,
      I1 => \byte5_reg_n_0_[3]\,
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \byte5_reg_n_0_[5]\,
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => \byte5_reg_n_0_[1]\,
      O => \txd[1]_i_84_n_0\
    );
\txd[1]_i_85\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000080"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => byte7(1),
      I3 => \bit_count_reg_n_0_[1]\,
      I4 => \bit_count_reg_n_0_[0]\,
      I5 => \bit_count_reg_n_0_[2]\,
      O => \txd[1]_i_85_n_0\
    );
\txd[1]_i_86\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \byte_count_reg_n_0_[0]\,
      I2 => byte9(3),
      I3 => \bit_count_reg_n_0_[1]\,
      I4 => \bit_count_reg_n_0_[0]\,
      I5 => \bit_count_reg_n_0_[2]\,
      O => \txd[1]_i_86_n_0\
    );
\txd[1]_i_87\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFAC00AC"
    )
        port map (
      I0 => byte13(3),
      I1 => byte13(1),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => \bit_count_reg_n_0_[1]\,
      I4 => \byte8_reg_n_0_[7]\,
      O => \txd[1]_i_87_n_0\
    );
\txd[1]_i_88\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte22(7),
      I1 => byte22(3),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte22(5),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte22(1),
      O => \txd[1]_i_88_n_0\
    );
\txd[1]_i_89\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte20(7),
      I1 => byte20(3),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte20(5),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte20(1),
      O => \txd[1]_i_89_n_0\
    );
\txd[1]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FEFFFFFF"
    )
        port map (
      I0 => \state_reg_n_0_[1]\,
      I1 => \state[1]_i_3__1_n_0\,
      I2 => \bit_count_reg_n_0_[2]\,
      I3 => \bit_count_reg_n_0_[0]\,
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => \txd[1]_i_25_n_0\,
      O => \txd[1]_i_9_n_0\
    );
\txd[1]_i_90\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte23(7),
      I1 => byte23(3),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte23(5),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte23(1),
      O => \txd[1]_i_90_n_0\
    );
\txd[1]_i_91\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte17(7),
      I1 => byte17(3),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte17(5),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte17(1),
      O => \txd[1]_i_91_n_0\
    );
\txd[1]_i_92\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte16(7),
      I1 => byte16(3),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte16(5),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte16(1),
      O => \txd[1]_i_92_n_0\
    );
\txd[1]_i_93\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => byte19(7),
      I1 => byte19(3),
      I2 => \bit_count_reg_n_0_[0]\,
      I3 => byte19(5),
      I4 => \bit_count_reg_n_0_[1]\,
      I5 => byte19(1),
      O => \txd[1]_i_93_n_0\
    );
\txd[1]_i_98\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \byte_count_reg_n_0_[0]\,
      O => \txd[1]_i_98_n_0\
    );
\txd[1]_i_99\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \byte_count_reg_n_0_[1]\,
      I1 => \bit_count_reg_n_0_[3]\,
      O => \txd[1]_i_99_n_0\
    );
\txd_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => crc_calculator_n_3,
      Q => eth_txd(0),
      R => '0'
    );
\txd_reg[0]_i_10\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txd[0]_i_28_n_0\,
      I1 => \txd[0]_i_29_n_0\,
      O => \txd_reg[0]_i_10_n_0\,
      S => \bit_count_reg_n_0_[0]\
    );
\txd_reg[0]_i_37\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txd[0]_i_56_n_0\,
      I1 => \txd[0]_i_57_n_0\,
      O => \txd_reg[0]_i_37_n_0\,
      S => \byte_count_reg_n_0_[2]\
    );
\txd_reg[0]_i_9\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \NLW_txd_reg[0]_i_9_CO_UNCONNECTED\(3),
      CO(2) => \txd_reg[0]_i_9_n_1\,
      CO(1) => \txd_reg[0]_i_9_n_2\,
      CO(0) => \txd_reg[0]_i_9_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => \byte_count_reg_n_0_[1]\,
      DI(1) => \txd[0]_i_24_n_0\,
      DI(0) => '0',
      O(3) => \txd_reg[0]_i_9_n_4\,
      O(2) => \txd_reg[0]_i_9_n_5\,
      O(1) => \txd_reg[0]_i_9_n_6\,
      O(0) => \txd_reg[0]_i_9_n_7\,
      S(3) => \txd[0]_i_25_n_0\,
      S(2) => \txd[0]_i_26_n_0\,
      S(1) => \txd[0]_i_27_n_0\,
      S(0) => \bit_count_reg_n_0_[1]\
    );
\txd_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \txd[1]_i_1_n_0\,
      Q => eth_txd(1),
      R => '0'
    );
\txd_reg[1]_i_22\: unisim.vcomponents.MUXF8
     port map (
      I0 => \txd_reg[1]_i_40_n_0\,
      I1 => \txd_reg[1]_i_41_n_0\,
      O => \txd_reg[1]_i_22_n_0\,
      S => \bit_count_reg_n_0_[1]\
    );
\txd_reg[1]_i_23\: unisim.vcomponents.MUXF8
     port map (
      I0 => \txd_reg[1]_i_42_n_0\,
      I1 => \txd_reg[1]_i_43_n_0\,
      O => \txd_reg[1]_i_23_n_0\,
      S => \bit_count_reg_n_0_[1]\
    );
\txd_reg[1]_i_26\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txd[1]_i_46_n_0\,
      I1 => \txd[1]_i_47_n_0\,
      O => \txd_reg[1]_i_26_n_0\,
      S => \byte_count_reg_n_0_[2]\
    );
\txd_reg[1]_i_38\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \NLW_txd_reg[1]_i_38_CO_UNCONNECTED\(3),
      CO(2) => \txd_reg[1]_i_38_n_1\,
      CO(1) => \txd_reg[1]_i_38_n_2\,
      CO(0) => \txd_reg[1]_i_38_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => \txd[1]_i_68_n_0\,
      DI(1) => \txd[1]_i_69_n_0\,
      DI(0) => '0',
      O(3) => \txd_reg[1]_i_38_n_4\,
      O(2) => \txd_reg[1]_i_38_n_5\,
      O(1) => \txd_reg[1]_i_38_n_6\,
      O(0) => \NLW_txd_reg[1]_i_38_O_UNCONNECTED\(0),
      S(3) => \byte_count_reg_n_0_[2]\,
      S(2) => \txd[1]_i_70_n_0\,
      S(1) => \txd[1]_i_71_n_0\,
      S(0) => \bit_count_reg_n_0_[1]\
    );
\txd_reg[1]_i_40\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txd[1]_i_73_n_0\,
      I1 => \txd[1]_i_74_n_0\,
      O => \txd_reg[1]_i_40_n_0\,
      S => \txd_reg[0]_i_9_n_6\
    );
\txd_reg[1]_i_41\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txd[1]_i_75_n_0\,
      I1 => \txd[1]_i_76_n_0\,
      O => \txd_reg[1]_i_41_n_0\,
      S => \txd_reg[0]_i_9_n_6\
    );
\txd_reg[1]_i_42\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txd[1]_i_77_n_0\,
      I1 => \txd[1]_i_78_n_0\,
      O => \txd_reg[1]_i_42_n_0\,
      S => \txd_reg[0]_i_9_n_6\
    );
\txd_reg[1]_i_43\: unisim.vcomponents.MUXF7
     port map (
      I0 => \txd[1]_i_79_n_0\,
      I1 => \txd[1]_i_80_n_0\,
      O => \txd_reg[1]_i_43_n_0\,
      S => \txd_reg[0]_i_9_n_6\
    );
\txd_reg[1]_i_72\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3 downto 2) => \NLW_txd_reg[1]_i_72_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \txd_reg[1]_i_72_n_2\,
      CO(0) => \txd_reg[1]_i_72_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => \txd[1]_i_98_n_0\,
      DI(0) => '0',
      O(3) => \NLW_txd_reg[1]_i_72_O_UNCONNECTED\(3),
      O(2) => \txd_reg[1]_i_72_n_5\,
      O(1) => \txd_reg[1]_i_72_n_6\,
      O(0) => \NLW_txd_reg[1]_i_72_O_UNCONNECTED\(0),
      S(3) => '0',
      S(2) => \txd[1]_i_99_n_0\,
      S(1) => \txd[1]_i_100_n_0\,
      S(0) => \bit_count_reg_n_0_[1]\
    );
txen_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF7FFC"
    )
        port map (
      I0 => txen_i_2_n_0,
      I1 => \state_reg_n_0_[0]\,
      I2 => \state_reg_n_0_[2]\,
      I3 => \state_reg_n_0_[1]\,
      I4 => tx_ready,
      O => txen_i_1_n_0
    );
txen_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => txen_i_3_n_0,
      I1 => \byte_count_reg_n_0_[3]\,
      I2 => \byte_count_reg_n_0_[2]\,
      O => txen_i_2_n_0
    );
txen_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \byte_count_reg_n_0_[7]\,
      I1 => \byte_count_reg_n_0_[8]\,
      I2 => txen_i_4_n_0,
      I3 => \byte_count_reg_n_0_[5]\,
      I4 => \byte_count_reg_n_0_[6]\,
      I5 => \byte_count_reg_n_0_[4]\,
      O => txen_i_3_n_0
    );
txen_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \byte_count_reg_n_0_[9]\,
      I1 => \byte_count_reg_n_0_[10]\,
      O => txen_i_4_n_0
    );
txen_reg: unisim.vcomponents.FDRE
     port map (
      C => b_clk50mhz_shift,
      CE => eth_rstn,
      D => txen_i_1_n_0,
      Q => eth_txen,
      R => '0'
    );
\udp_checksum_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(0),
      Q => \udp_checksum_reg_n_0_[0]\,
      R => tx_done
    );
\udp_checksum_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(10),
      Q => \udp_checksum_reg_n_0_[10]\,
      R => tx_done
    );
\udp_checksum_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(11),
      Q => \udp_checksum_reg_n_0_[11]\,
      R => tx_done
    );
\udp_checksum_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(12),
      Q => \udp_checksum_reg_n_0_[12]\,
      R => tx_done
    );
\udp_checksum_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(13),
      Q => \udp_checksum_reg_n_0_[13]\,
      R => tx_done
    );
\udp_checksum_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(14),
      Q => \udp_checksum_reg_n_0_[14]\,
      R => tx_done
    );
\udp_checksum_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(15),
      Q => \udp_checksum_reg_n_0_[15]\,
      R => tx_done
    );
\udp_checksum_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(1),
      Q => \udp_checksum_reg_n_0_[1]\,
      R => tx_done
    );
\udp_checksum_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(2),
      Q => \udp_checksum_reg_n_0_[2]\,
      R => tx_done
    );
\udp_checksum_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(3),
      Q => \udp_checksum_reg_n_0_[3]\,
      R => tx_done
    );
\udp_checksum_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(4),
      Q => \udp_checksum_reg_n_0_[4]\,
      R => tx_done
    );
\udp_checksum_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(5),
      Q => \udp_checksum_reg_n_0_[5]\,
      R => tx_done
    );
\udp_checksum_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(6),
      Q => \udp_checksum_reg_n_0_[6]\,
      R => tx_done
    );
\udp_checksum_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(7),
      Q => \udp_checksum_reg_n_0_[7]\,
      R => tx_done
    );
\udp_checksum_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(8),
      Q => \udp_checksum_reg_n_0_[8]\,
      R => tx_done
    );
\udp_checksum_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => udp_packet_checksum(9),
      Q => \udp_checksum_reg_n_0_[9]\,
      R => tx_done
    );
\udp_length_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => Q(8),
      Q => \udp_length_reg_n_0_[10]\,
      R => tx_done
    );
\udp_length_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => Q(9),
      Q => \udp_length_reg_n_0_[11]\,
      R => tx_done
    );
\udp_length_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => Q(10),
      Q => \udp_length_reg_n_0_[12]\,
      R => tx_done
    );
\udp_length_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => Q(11),
      Q => \udp_length_reg_n_0_[13]\,
      R => tx_done
    );
\udp_length_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => Q(12),
      Q => \udp_length_reg_n_0_[14]\,
      R => tx_done
    );
\udp_length_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => Q(13),
      Q => \udp_length_reg_n_0_[15]\,
      R => tx_done
    );
\udp_length_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => Q(0),
      Q => \udp_length_reg_n_0_[2]\,
      R => tx_done
    );
\udp_length_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => Q(1),
      Q => \udp_length_reg_n_0_[3]\,
      R => tx_done
    );
\udp_length_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => Q(2),
      Q => \udp_length_reg_n_0_[4]\,
      R => tx_done
    );
\udp_length_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => Q(3),
      Q => \udp_length_reg_n_0_[5]\,
      R => tx_done
    );
\udp_length_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => Q(4),
      Q => \udp_length_reg_n_0_[6]\,
      R => tx_done
    );
\udp_length_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => Q(5),
      Q => \udp_length_reg_n_0_[7]\,
      R => tx_done
    );
\udp_length_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => Q(6),
      Q => \udp_length_reg_n_0_[8]\,
      R => tx_done
    );
\udp_length_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => udp_checksum,
      D => Q(7),
      Q => \udp_length_reg_n_0_[9]\,
      R => tx_done
    );
udp_send_data_valid_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => tx_data_valid_reg,
      I1 => state(0),
      I2 => state(1),
      I3 => is_idle,
      O => \^udp_send_data_valid17_out\
    );
\zero_counter[1]_i_1__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => zero_counter(4),
      O => \zero_counter[1]_i_1__0_n_0\
    );
\zero_counter[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00A2"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[2]\,
      I1 => arp_reply_reg_n_0,
      I2 => tx_done,
      I3 => zero_counter(4),
      O => \zero_counter[2]_i_1__0_n_0\
    );
\zero_counter[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006606"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[3]\,
      I1 => \data_counter_max_reg_n_0_[2]\,
      I2 => arp_reply_reg_n_0,
      I3 => tx_done,
      I4 => zero_counter(4),
      O => \zero_counter[3]_i_1__0_n_0\
    );
\zero_counter[4]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E1"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[2]\,
      I1 => \data_counter_max_reg_n_0_[3]\,
      I2 => \data_counter_max_reg_n_0_[4]\,
      I3 => zero_counter(4),
      O => \zero_counter[4]_i_1__0_n_0\
    );
\zero_counter[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFF8F"
    )
        port map (
      I0 => \zero_counter[4]_i_3_n_0\,
      I1 => \data_counter_max_reg_n_0_[4]\,
      I2 => eth_type1,
      I3 => \zero_counter[4]_i_4__0_n_0\,
      I4 => \data_counter_max_reg_n_0_[9]\,
      I5 => \data_counter_max_reg_n_0_[10]\,
      O => zero_counter(4)
    );
\zero_counter[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[2]\,
      I1 => \data_counter_max_reg_n_0_[3]\,
      O => \zero_counter[4]_i_3_n_0\
    );
\zero_counter[4]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \data_counter_max_reg_n_0_[7]\,
      I1 => \data_counter_max_reg_n_0_[6]\,
      I2 => \data_counter_max_reg_n_0_[8]\,
      I3 => \data_counter_max_reg_n_0_[5]\,
      O => \zero_counter[4]_i_4__0_n_0\
    );
\zero_counter_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \zero_counter[1]_i_1__0_n_0\,
      Q => \zero_counter_reg_n_0_[1]\,
      S => eth_type118_out
    );
\zero_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \zero_counter[2]_i_1__0_n_0\,
      Q => \zero_counter_reg_n_0_[2]\,
      R => '0'
    );
\zero_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \zero_counter[3]_i_1__0_n_0\,
      Q => \zero_counter_reg_n_0_[3]\,
      R => '0'
    );
\zero_counter_reg[4]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '1'
    )
        port map (
      C => b_clk50mhz_shift,
      CE => '1',
      D => \zero_counter[4]_i_1__0_n_0\,
      Q => \zero_counter_reg_n_0_[4]\,
      S => eth_type118_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_ethernet_transceiver2_0_0_ethernet_transceiver2 is
  port (
    clk100mhz : in STD_LOGIC;
    eth_rxd : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    eth_txd : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    eth_crsdv : inout STD_LOGIC;
    eth_txen : inout STD_LOGIC;
    eth_rxerr : inout STD_LOGIC;
    eth_mdc : out STD_LOGIC;
    eth_mdio : inout STD_LOGIC;
    eth_refclk : out STD_LOGIC;
    eth_rstn : inout STD_LOGIC;
    led16_b : out STD_LOGIC;
    led16_g : out STD_LOGIC;
    led16_r : out STD_LOGIC;
    led17_b : out STD_LOGIC;
    led17_g : out STD_LOGIC;
    led17_r : out STD_LOGIC;
    btn_reset : in STD_LOGIC;
    led : out STD_LOGIC_VECTOR ( 15 downto 0 );
    udp_packet_checksum : in STD_LOGIC_VECTOR ( 15 downto 0 );
    udp_packet_recieved : out STD_LOGIC;
    udp_packet_sending : out STD_LOGIC;
    fifo_write_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
    fifo_write_enable : out STD_LOGIC;
    fifo_write_full : in STD_LOGIC;
    fifo_read_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
    fifo_read_enable : out STD_LOGIC;
    fifo_read_length : in STD_LOGIC_VECTOR ( 15 downto 0 );
    fifo_read_empty : in STD_LOGIC;
    ip : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ADDR_WIDTH : integer;
  attribute ADDR_WIDTH of design_1_ethernet_transceiver2_0_0_ethernet_transceiver2 : entity is 10;
  attribute DATA_WIDTH : integer;
  attribute DATA_WIDTH of design_1_ethernet_transceiver2_0_0_ethernet_transceiver2 : entity is 8;
  attribute FIFO_WIDTH : integer;
  attribute FIFO_WIDTH of design_1_ethernet_transceiver2_0_0_ethernet_transceiver2 : entity is 32;
  attribute M_clk2_5mhz1 : integer;
  attribute M_clk2_5mhz1 of design_1_ethernet_transceiver2_0_0_ethernet_transceiver2 : entity is 20;
  attribute M_clk2_5mhz2 : integer;
  attribute M_clk2_5mhz2 of design_1_ethernet_transceiver2_0_0_ethernet_transceiver2 : entity is 10;
  attribute N : integer;
  attribute N of design_1_ethernet_transceiver2_0_0_ethernet_transceiver2 : entity is 22;
end design_1_ethernet_transceiver2_0_0_ethernet_transceiver2;

architecture STRUCTURE of design_1_ethernet_transceiver2_0_0_ethernet_transceiver2 is
  signal Ethernet_receiver_n_35 : STD_LOGIC;
  signal Ethernet_receiver_n_36 : STD_LOGIC;
  signal Ethernet_receiver_n_39 : STD_LOGIC;
  signal Ethernet_receiver_n_40 : STD_LOGIC;
  signal Ethernet_transmitter_n_4 : STD_LOGIC;
  signal Ethernet_transmitter_n_5 : STD_LOGIC;
  signal Ethernet_transmitter_n_6 : STD_LOGIC;
  signal I : STD_LOGIC;
  signal Switch_n_5 : STD_LOGIC;
  signal arp_response_pending : STD_LOGIC;
  signal arp_send_valid_reg_n_0 : STD_LOGIC;
  signal b_clk100mhz : STD_LOGIC;
  signal b_clk2_5mhz_shift : STD_LOGIC;
  signal b_clk50mhz_shift : STD_LOGIC;
  signal clear : STD_LOGIC;
  signal clk2_5mhz_shift : STD_LOGIC;
  signal clk50mhz : STD_LOGIC;
  signal clk_out_shift : STD_LOGIC;
  signal \crc_rx_reg[30]_i_2_n_0\ : STD_LOGIC;
  signal \crc_rx_reg[30]_i_4_n_0\ : STD_LOGIC;
  signal datacm : STD_LOGIC_VECTOR ( 10 downto 2 );
  signal \datacm_send[10]_i_10_n_0\ : STD_LOGIC;
  signal \datacm_send[10]_i_11_n_0\ : STD_LOGIC;
  signal \datacm_send[10]_i_12_n_0\ : STD_LOGIC;
  signal \datacm_send[10]_i_13_n_0\ : STD_LOGIC;
  signal \datacm_send[10]_i_14_n_0\ : STD_LOGIC;
  signal \datacm_send[10]_i_15_n_0\ : STD_LOGIC;
  signal \datacm_send[10]_i_16_n_0\ : STD_LOGIC;
  signal \datacm_send[10]_i_4_n_0\ : STD_LOGIC;
  signal \datacm_send[10]_i_5_n_0\ : STD_LOGIC;
  signal \datacm_send[10]_i_6_n_0\ : STD_LOGIC;
  signal \datacm_send[10]_i_7_n_0\ : STD_LOGIC;
  signal \datacm_send[10]_i_8_n_0\ : STD_LOGIC;
  signal \datacm_send[10]_i_9_n_0\ : STD_LOGIC;
  signal \datacm_send_reg[10]_i_2_n_0\ : STD_LOGIC;
  signal \datacm_send_reg[10]_i_2_n_1\ : STD_LOGIC;
  signal \datacm_send_reg[10]_i_2_n_2\ : STD_LOGIC;
  signal \datacm_send_reg[10]_i_2_n_3\ : STD_LOGIC;
  signal \datacm_send_reg[10]_i_3_n_0\ : STD_LOGIC;
  signal \datacm_send_reg[10]_i_3_n_1\ : STD_LOGIC;
  signal \datacm_send_reg[10]_i_3_n_2\ : STD_LOGIC;
  signal \datacm_send_reg[10]_i_3_n_3\ : STD_LOGIC;
  signal db_sw : STD_LOGIC;
  signal \^eth_refclk\ : STD_LOGIC;
  signal eth_rstn_i_10_n_0 : STD_LOGIC;
  signal eth_rstn_i_1_n_0 : STD_LOGIC;
  signal eth_rstn_i_3_n_0 : STD_LOGIC;
  signal eth_rstn_i_4_n_0 : STD_LOGIC;
  signal eth_rstn_i_5_n_0 : STD_LOGIC;
  signal eth_rstn_i_6_n_0 : STD_LOGIC;
  signal eth_rstn_i_7_n_0 : STD_LOGIC;
  signal eth_rstn_i_8_n_0 : STD_LOGIC;
  signal eth_rstn_i_9_n_0 : STD_LOGIC;
  signal \^fifo_write_enable\ : STD_LOGIC;
  signal \init_proc__0\ : STD_LOGIC;
  signal led16_b_reg_i_2_n_0 : STD_LOGIC;
  signal p_2_out : STD_LOGIC_VECTOR ( 31 downto 23 );
  signal pc_ip : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal pc_mac : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal pc_port : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal po_counter0 : STD_LOGIC;
  signal \po_counter[0]_i_3_n_0\ : STD_LOGIC;
  signal \po_counter[0]_i_4_n_0\ : STD_LOGIC;
  signal \po_counter[0]_i_5_n_0\ : STD_LOGIC;
  signal \po_counter[0]_i_6_n_0\ : STD_LOGIC;
  signal \po_counter[0]_i_7_n_0\ : STD_LOGIC;
  signal \po_counter[12]_i_2_n_0\ : STD_LOGIC;
  signal \po_counter[12]_i_3_n_0\ : STD_LOGIC;
  signal \po_counter[12]_i_4_n_0\ : STD_LOGIC;
  signal \po_counter[12]_i_5_n_0\ : STD_LOGIC;
  signal \po_counter[16]_i_2_n_0\ : STD_LOGIC;
  signal \po_counter[16]_i_3_n_0\ : STD_LOGIC;
  signal \po_counter[16]_i_4_n_0\ : STD_LOGIC;
  signal \po_counter[16]_i_5_n_0\ : STD_LOGIC;
  signal \po_counter[20]_i_2_n_0\ : STD_LOGIC;
  signal \po_counter[20]_i_3_n_0\ : STD_LOGIC;
  signal \po_counter[4]_i_2_n_0\ : STD_LOGIC;
  signal \po_counter[4]_i_3_n_0\ : STD_LOGIC;
  signal \po_counter[4]_i_4_n_0\ : STD_LOGIC;
  signal \po_counter[4]_i_5_n_0\ : STD_LOGIC;
  signal \po_counter[8]_i_2_n_0\ : STD_LOGIC;
  signal \po_counter[8]_i_3_n_0\ : STD_LOGIC;
  signal \po_counter[8]_i_4_n_0\ : STD_LOGIC;
  signal \po_counter[8]_i_5_n_0\ : STD_LOGIC;
  signal po_counter_reg : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \po_counter_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \po_counter_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \po_counter_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \po_counter_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \po_counter_reg[0]_i_2_n_4\ : STD_LOGIC;
  signal \po_counter_reg[0]_i_2_n_5\ : STD_LOGIC;
  signal \po_counter_reg[0]_i_2_n_6\ : STD_LOGIC;
  signal \po_counter_reg[0]_i_2_n_7\ : STD_LOGIC;
  signal \po_counter_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \po_counter_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \po_counter_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \po_counter_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \po_counter_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \po_counter_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \po_counter_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \po_counter_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \po_counter_reg[16]_i_1_n_0\ : STD_LOGIC;
  signal \po_counter_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \po_counter_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \po_counter_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \po_counter_reg[16]_i_1_n_4\ : STD_LOGIC;
  signal \po_counter_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \po_counter_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \po_counter_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \po_counter_reg[20]_i_1_n_3\ : STD_LOGIC;
  signal \po_counter_reg[20]_i_1_n_6\ : STD_LOGIC;
  signal \po_counter_reg[20]_i_1_n_7\ : STD_LOGIC;
  signal \po_counter_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \po_counter_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \po_counter_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \po_counter_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \po_counter_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \po_counter_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \po_counter_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \po_counter_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \po_counter_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \po_counter_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \po_counter_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \po_counter_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \po_counter_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \po_counter_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \po_counter_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \po_counter_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal rstn_counter0 : STD_LOGIC_VECTOR ( 12 downto 1 );
  signal \rstn_counter[0]_i_1_n_0\ : STD_LOGIC;
  signal \rstn_counter[0]_i_3_n_0\ : STD_LOGIC;
  signal \rstn_counter[0]_i_4_n_0\ : STD_LOGIC;
  signal \rstn_counter[0]_i_5_n_0\ : STD_LOGIC;
  signal \rstn_counter[0]_i_6_n_0\ : STD_LOGIC;
  signal \rstn_counter[0]_i_7_n_0\ : STD_LOGIC;
  signal \rstn_counter[12]_i_2_n_0\ : STD_LOGIC;
  signal \rstn_counter[4]_i_2_n_0\ : STD_LOGIC;
  signal \rstn_counter[4]_i_3_n_0\ : STD_LOGIC;
  signal \rstn_counter[4]_i_4_n_0\ : STD_LOGIC;
  signal \rstn_counter[4]_i_5_n_0\ : STD_LOGIC;
  signal \rstn_counter[8]_i_2_n_0\ : STD_LOGIC;
  signal \rstn_counter[8]_i_3_n_0\ : STD_LOGIC;
  signal \rstn_counter[8]_i_4_n_0\ : STD_LOGIC;
  signal \rstn_counter[8]_i_5_n_0\ : STD_LOGIC;
  signal rstn_counter_reg : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \rstn_counter_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \rstn_counter_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \rstn_counter_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \rstn_counter_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \rstn_counter_reg[0]_i_2_n_4\ : STD_LOGIC;
  signal \rstn_counter_reg[0]_i_2_n_5\ : STD_LOGIC;
  signal \rstn_counter_reg[0]_i_2_n_6\ : STD_LOGIC;
  signal \rstn_counter_reg[0]_i_2_n_7\ : STD_LOGIC;
  signal \rstn_counter_reg[0]_i_8_n_0\ : STD_LOGIC;
  signal \rstn_counter_reg[0]_i_8_n_1\ : STD_LOGIC;
  signal \rstn_counter_reg[0]_i_8_n_2\ : STD_LOGIC;
  signal \rstn_counter_reg[0]_i_8_n_3\ : STD_LOGIC;
  signal \rstn_counter_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \rstn_counter_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \rstn_counter_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \rstn_counter_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \rstn_counter_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \rstn_counter_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \rstn_counter_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \rstn_counter_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \rstn_counter_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \rstn_counter_reg[4]_i_6_n_0\ : STD_LOGIC;
  signal \rstn_counter_reg[4]_i_6_n_1\ : STD_LOGIC;
  signal \rstn_counter_reg[4]_i_6_n_2\ : STD_LOGIC;
  signal \rstn_counter_reg[4]_i_6_n_3\ : STD_LOGIC;
  signal \rstn_counter_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \rstn_counter_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \rstn_counter_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \rstn_counter_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \rstn_counter_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \rstn_counter_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \rstn_counter_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \rstn_counter_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \rstn_counter_reg[8]_i_6_n_1\ : STD_LOGIC;
  signal \rstn_counter_reg[8]_i_6_n_2\ : STD_LOGIC;
  signal \rstn_counter_reg[8]_i_6_n_3\ : STD_LOGIC;
  signal rx_data : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal send_arp_reply : STD_LOGIC;
  signal send_countdown0 : STD_LOGIC;
  signal \send_countdown[0]_i_10_n_0\ : STD_LOGIC;
  signal \send_countdown[0]_i_4_n_0\ : STD_LOGIC;
  signal \send_countdown[0]_i_5_n_0\ : STD_LOGIC;
  signal \send_countdown[0]_i_6_n_0\ : STD_LOGIC;
  signal \send_countdown[0]_i_7_n_0\ : STD_LOGIC;
  signal \send_countdown[0]_i_8_n_0\ : STD_LOGIC;
  signal \send_countdown[0]_i_9_n_0\ : STD_LOGIC;
  signal \send_countdown[12]_i_2_n_0\ : STD_LOGIC;
  signal \send_countdown[4]_i_2_n_0\ : STD_LOGIC;
  signal \send_countdown[4]_i_3_n_0\ : STD_LOGIC;
  signal \send_countdown[4]_i_4_n_0\ : STD_LOGIC;
  signal \send_countdown[4]_i_5_n_0\ : STD_LOGIC;
  signal \send_countdown[8]_i_2_n_0\ : STD_LOGIC;
  signal \send_countdown[8]_i_3_n_0\ : STD_LOGIC;
  signal \send_countdown[8]_i_4_n_0\ : STD_LOGIC;
  signal \send_countdown[8]_i_5_n_0\ : STD_LOGIC;
  signal send_countdown_reg : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal \send_countdown_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \send_countdown_reg[0]_i_3_n_1\ : STD_LOGIC;
  signal \send_countdown_reg[0]_i_3_n_2\ : STD_LOGIC;
  signal \send_countdown_reg[0]_i_3_n_3\ : STD_LOGIC;
  signal \send_countdown_reg[0]_i_3_n_4\ : STD_LOGIC;
  signal \send_countdown_reg[0]_i_3_n_5\ : STD_LOGIC;
  signal \send_countdown_reg[0]_i_3_n_6\ : STD_LOGIC;
  signal \send_countdown_reg[0]_i_3_n_7\ : STD_LOGIC;
  signal \send_countdown_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \send_countdown_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \send_countdown_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \send_countdown_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \send_countdown_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \send_countdown_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \send_countdown_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \send_countdown_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \send_countdown_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \send_countdown_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \send_countdown_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \send_countdown_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \send_countdown_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \send_countdown_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \send_countdown_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \send_countdown_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \send_countdown_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal sent_arp_response : STD_LOGIC;
  signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \state[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \state[1]_i_10__0_n_0\ : STD_LOGIC;
  signal \state[1]_i_11__0_n_0\ : STD_LOGIC;
  signal \state[1]_i_12__0_n_0\ : STD_LOGIC;
  signal \state[1]_i_13__0_n_0\ : STD_LOGIC;
  signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \state[1]_i_2__1_n_0\ : STD_LOGIC;
  signal \state[1]_i_3__0_n_0\ : STD_LOGIC;
  signal \state[1]_i_4__1_n_0\ : STD_LOGIC;
  signal \state[1]_i_5__0_n_0\ : STD_LOGIC;
  signal \state[1]_i_6__0_n_0\ : STD_LOGIC;
  signal \state[1]_i_7__0_n_0\ : STD_LOGIC;
  signal \state[1]_i_8_n_0\ : STD_LOGIC;
  signal \state[1]_i_9__0_n_0\ : STD_LOGIC;
  signal tx_data_valid : STD_LOGIC;
  signal udp_packet_length : STD_LOGIC_VECTOR ( 15 downto 2 );
  signal udp_packet_length0 : STD_LOGIC_VECTOR ( 15 downto 2 );
  signal \udp_packet_length0__0\ : STD_LOGIC;
  signal \udp_packet_length[5]_i_2_n_0\ : STD_LOGIC;
  signal \udp_packet_length_reg[13]_i_1_n_0\ : STD_LOGIC;
  signal \udp_packet_length_reg[13]_i_1_n_1\ : STD_LOGIC;
  signal \udp_packet_length_reg[13]_i_1_n_2\ : STD_LOGIC;
  signal \udp_packet_length_reg[13]_i_1_n_3\ : STD_LOGIC;
  signal \udp_packet_length_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \udp_packet_length_reg[5]_i_1_n_0\ : STD_LOGIC;
  signal \udp_packet_length_reg[5]_i_1_n_1\ : STD_LOGIC;
  signal \udp_packet_length_reg[5]_i_1_n_2\ : STD_LOGIC;
  signal \udp_packet_length_reg[5]_i_1_n_3\ : STD_LOGIC;
  signal \udp_packet_length_reg[9]_i_1_n_0\ : STD_LOGIC;
  signal \udp_packet_length_reg[9]_i_1_n_1\ : STD_LOGIC;
  signal \udp_packet_length_reg[9]_i_1_n_2\ : STD_LOGIC;
  signal \udp_packet_length_reg[9]_i_1_n_3\ : STD_LOGIC;
  signal \^udp_packet_recieved\ : STD_LOGIC;
  signal udp_send_data_valid : STD_LOGIC;
  signal udp_send_data_valid11_in : STD_LOGIC;
  signal udp_send_data_valid17_out : STD_LOGIC;
  signal udp_send_data_valid_i_11_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_12_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_13_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_14_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_15_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_16_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_17_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_18_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_21_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_22_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_23_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_24_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_25_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_26_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_27_n_0 : STD_LOGIC;
  signal udp_send_data_valid_i_28_n_0 : STD_LOGIC;
  signal udp_send_data_valid_reg_i_10_n_0 : STD_LOGIC;
  signal udp_send_data_valid_reg_i_10_n_1 : STD_LOGIC;
  signal udp_send_data_valid_reg_i_10_n_2 : STD_LOGIC;
  signal udp_send_data_valid_reg_i_10_n_3 : STD_LOGIC;
  signal udp_send_data_valid_reg_i_5_n_1 : STD_LOGIC;
  signal udp_send_data_valid_reg_i_5_n_2 : STD_LOGIC;
  signal udp_send_data_valid_reg_i_5_n_3 : STD_LOGIC;
  signal udp_send_data_valid_reg_n_0 : STD_LOGIC;
  signal \NLW_datacm_send_reg[10]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_datacm_send_reg[10]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_po_counter_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_po_counter_reg[20]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_rstn_counter_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_rstn_counter_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_rstn_counter_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_send_countdown_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_send_countdown_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_udp_packet_length_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_udp_packet_length_reg[15]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal NLW_udp_send_data_valid_reg_i_10_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_udp_send_data_valid_reg_i_5_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute box_type : string;
  attribute box_type of PULLUP_MODE0 : label is "PRIMITIVE";
  attribute box_type of PULLUP_MODE1 : label is "PRIMITIVE";
  attribute box_type of PULLUP_MODE2 : label is "PRIMITIVE";
  attribute box_type of PULLUP_PHYAD0 : label is "PRIMITIVE";
  attribute box_type of U1 : label is "PRIMITIVE";
  attribute box_type of U2 : label is "PRIMITIVE";
  attribute box_type of U3 : label is "PRIMITIVE";
  attribute box_type of U4 : label is "PRIMITIVE";
  attribute box_type of U5 : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of eth_rstn_i_3 : label is "soft_lutpair344";
  attribute SOFT_HLUTNM of \state[1]_i_2__1\ : label is "soft_lutpair344";
begin
  eth_refclk <= \^eth_refclk\;
  fifo_write_enable <= \^fifo_write_enable\;
  udp_packet_recieved <= \^udp_packet_recieved\;
CLOCK_2_5MHz: entity work.design_1_ethernet_transceiver2_0_0_clock_mod2
     port map (
      I => I,
      b_clk100mhz => b_clk100mhz,
      clk2_5mhz_shift => clk2_5mhz_shift
    );
CLOCK_50MHz: entity work.design_1_ethernet_transceiver2_0_0_clock_mod
     port map (
      b_clk100mhz => b_clk100mhz,
      clk50mhz => clk50mhz,
      clk_out_shift => clk_out_shift
    );
Ethernet_receiver: entity work.design_1_ethernet_transceiver2_0_0_eth_receiver
     port map (
      CO(0) => udp_send_data_valid11_in,
      E(3) => p_2_out(31),
      E(2) => p_2_out(23),
      E(1) => Ethernet_receiver_n_39,
      E(0) => Ethernet_receiver_n_40,
      Q(31 downto 0) => pc_ip(31 downto 0),
      \addr_count_reg[1]_0\ => \^eth_refclk\,
      arp_response_pending => arp_response_pending,
      b_clk100mhz => b_clk100mhz,
      \crc_rx_reg[30]_0\ => \crc_rx_reg[30]_i_2_n_0\,
      \crc_rx_reg[30]_1\ => \crc_rx_reg[30]_i_4_n_0\,
      \data_to_ram_reg[7]_0\(7 downto 0) => rx_data(7 downto 0),
      eth_crsdv => eth_crsdv,
      eth_rstn => eth_rstn,
      eth_rxd(1 downto 0) => eth_rxd(1 downto 0),
      eth_rxerr => eth_rxerr,
      fifo_write_enable => \^fifo_write_enable\,
      ip(4 downto 0) => ip(4 downto 0),
      \pc_mac_reg[47]_0\(47 downto 0) => pc_mac(47 downto 0),
      \pc_port_reg[15]_0\(15 downto 0) => pc_port(15 downto 0),
      send_arp_reply => send_arp_reply,
      send_arp_reply_reg_0 => Ethernet_receiver_n_35,
      sent_arp_response => sent_arp_response,
      \state_reg[3]_0\ => led16_b_reg_i_2_n_0,
      udp_packet_recieved => \^udp_packet_recieved\,
      udp_send_data_valid => udp_send_data_valid,
      udp_send_data_valid17_out => udp_send_data_valid17_out,
      we_ram_reg_0 => Ethernet_receiver_n_36
    );
Ethernet_transmitter: entity work.design_1_ethernet_transceiver2_0_0_eth_transmitter
     port map (
      E(0) => tx_data_valid,
      Q(13 downto 0) => udp_packet_length(15 downto 2),
      arp_response_pending => arp_response_pending,
      arp_response_pending_reg => Ethernet_transmitter_n_5,
      b_clk100mhz => b_clk100mhz,
      b_clk50mhz_shift => b_clk50mhz_shift,
      \data_counter_max_reg[10]_0\(8 downto 0) => datacm(10 downto 2),
      db_sw => db_sw,
      db_sw_reg => Ethernet_transmitter_n_4,
      db_sw_reg_0 => Ethernet_transmitter_n_6,
      \dest_ip_reg[31]_0\(31 downto 0) => pc_ip(31 downto 0),
      \dest_mac_reg[47]_0\(47 downto 0) => pc_mac(47 downto 0),
      \dest_port_reg[15]_0\(15 downto 0) => pc_port(15 downto 0),
      eth_protocol_reg_0 => arp_send_valid_reg_n_0,
      eth_protocol_reg_1 => udp_send_data_valid_reg_n_0,
      eth_rstn => eth_rstn,
      eth_txd(1 downto 0) => eth_txd(1 downto 0),
      eth_txen => eth_txen,
      fifo_read_data(31 downto 0) => fifo_read_data(31 downto 0),
      fifo_read_enable => fifo_read_enable,
      ip(4 downto 0) => ip(4 downto 0),
      sent_arp_response => sent_arp_response,
      state(1 downto 0) => state(1 downto 0),
      \state_reg[0]_0\ => led16_b_reg_i_2_n_0,
      tx_data_valid_reg => \send_countdown[0]_i_4_n_0\,
      udp_packet_checksum(15 downto 0) => udp_packet_checksum(15 downto 0),
      udp_send_data_valid17_out => udp_send_data_valid17_out
    );
LED_count: entity work.design_1_ethernet_transceiver2_0_0_led1
     port map (
      CLK => \^eth_refclk\,
      led16_b => led16_b,
      led16_g => led16_g,
      led16_r => led16_r,
      led17_b => led17_b,
      led17_g => led17_g,
      led17_g_reg_0 => led16_b_reg_i_2_n_0,
      led17_r => led17_r,
      send_arp_reply => send_arp_reply,
      udp_packet_recieved => \^udp_packet_recieved\
    );
MDIO_Interface: entity work.design_1_ethernet_transceiver2_0_0_md_interface
     port map (
      b_clk2_5mhz_shift => b_clk2_5mhz_shift,
      eth_mdio => eth_mdio,
      eth_rstn => eth_rstn,
      led(15 downto 0) => led(15 downto 0),
      state_reg_0 => led16_b_reg_i_2_n_0
    );
PULLUP_MODE0: unisim.vcomponents.PULLUP
     port map (
      O => eth_rxd(0)
    );
PULLUP_MODE1: unisim.vcomponents.PULLUP
     port map (
      O => eth_rxd(1)
    );
PULLUP_MODE2: unisim.vcomponents.PULLUP
     port map (
      O => eth_crsdv
    );
PULLUP_PHYAD0: unisim.vcomponents.PULLUP
     port map (
      O => eth_rxerr
    );
Switch: entity work.design_1_ethernet_transceiver2_0_0_debounce_switch
     port map (
      CO(0) => \datacm_send_reg[10]_i_2_n_0\,
      SR(0) => \udp_packet_length0__0\,
      b_clk100mhz => b_clk100mhz,
      btn_reset => btn_reset,
      clear => clear,
      db_sw => db_sw,
      db_sw_reg_0 => Switch_n_5,
      \init_proc__0\ => \init_proc__0\,
      po_counter0 => po_counter0,
      \po_counter_reg[0]\ => \state[1]_i_4__1_n_0\,
      \po_counter_reg[0]_0\ => eth_rstn_i_4_n_0,
      send_countdown0 => send_countdown0,
      \send_countdown_reg[0]\ => \send_countdown[0]_i_4_n_0\,
      state(0) => state(0)
    );
U1: unisim.vcomponents.BUFG
     port map (
      I => clk100mhz,
      O => b_clk100mhz
    );
U2: unisim.vcomponents.BUFG
     port map (
      I => I,
      O => eth_mdc
    );
U3: unisim.vcomponents.BUFG
     port map (
      I => clk2_5mhz_shift,
      O => b_clk2_5mhz_shift
    );
U4: unisim.vcomponents.BUFG
     port map (
      I => clk50mhz,
      O => \^eth_refclk\
    );
U5: unisim.vcomponents.BUFG
     port map (
      I => clk_out_shift,
      O => b_clk50mhz_shift
    );
arp_response_pending_reg: unisim.vcomponents.FDCE
     port map (
      C => \^eth_refclk\,
      CE => '1',
      CLR => clear,
      D => Ethernet_receiver_n_35,
      Q => arp_response_pending
    );
arp_send_valid_reg: unisim.vcomponents.FDCE
     port map (
      C => \^eth_refclk\,
      CE => '1',
      CLR => clear,
      D => Ethernet_transmitter_n_5,
      Q => arp_send_valid_reg_n_0
    );
\crc_rx_reg[30]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => eth_rxd(0),
      O => \crc_rx_reg[30]_i_2_n_0\
    );
\crc_rx_reg[30]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => eth_rxd(1),
      O => \crc_rx_reg[30]_i_4_n_0\
    );
\datacm_send[10]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => fifo_read_length(8),
      I1 => fifo_read_length(9),
      O => \datacm_send[10]_i_10_n_0\
    );
\datacm_send[10]_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fifo_read_length(2),
      I1 => fifo_read_length(3),
      O => \datacm_send[10]_i_11_n_0\
    );
\datacm_send[10]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fifo_read_length(0),
      I1 => fifo_read_length(1),
      O => \datacm_send[10]_i_12_n_0\
    );
\datacm_send[10]_i_13\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => fifo_read_length(6),
      I1 => fifo_read_length(7),
      O => \datacm_send[10]_i_13_n_0\
    );
\datacm_send[10]_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => fifo_read_length(4),
      I1 => fifo_read_length(5),
      O => \datacm_send[10]_i_14_n_0\
    );
\datacm_send[10]_i_15\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fifo_read_length(3),
      I1 => fifo_read_length(2),
      O => \datacm_send[10]_i_15_n_0\
    );
\datacm_send[10]_i_16\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fifo_read_length(1),
      I1 => fifo_read_length(0),
      O => \datacm_send[10]_i_16_n_0\
    );
\datacm_send[10]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fifo_read_length(14),
      I1 => fifo_read_length(15),
      O => \datacm_send[10]_i_4_n_0\
    );
\datacm_send[10]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fifo_read_length(12),
      I1 => fifo_read_length(13),
      O => \datacm_send[10]_i_5_n_0\
    );
\datacm_send[10]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fifo_read_length(10),
      I1 => fifo_read_length(11),
      O => \datacm_send[10]_i_6_n_0\
    );
\datacm_send[10]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fifo_read_length(15),
      I1 => fifo_read_length(14),
      O => \datacm_send[10]_i_7_n_0\
    );
\datacm_send[10]_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fifo_read_length(13),
      I1 => fifo_read_length(12),
      O => \datacm_send[10]_i_8_n_0\
    );
\datacm_send[10]_i_9\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fifo_read_length(11),
      I1 => fifo_read_length(10),
      O => \datacm_send[10]_i_9_n_0\
    );
\datacm_send_reg[10]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => fifo_read_length(8),
      Q => datacm(10),
      S => \udp_packet_length0__0\
    );
\datacm_send_reg[10]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \datacm_send_reg[10]_i_3_n_0\,
      CO(3) => \datacm_send_reg[10]_i_2_n_0\,
      CO(2) => \datacm_send_reg[10]_i_2_n_1\,
      CO(1) => \datacm_send_reg[10]_i_2_n_2\,
      CO(0) => \datacm_send_reg[10]_i_2_n_3\,
      CYINIT => '0',
      DI(3) => \datacm_send[10]_i_4_n_0\,
      DI(2) => \datacm_send[10]_i_5_n_0\,
      DI(1) => \datacm_send[10]_i_6_n_0\,
      DI(0) => fifo_read_length(9),
      O(3 downto 0) => \NLW_datacm_send_reg[10]_i_2_O_UNCONNECTED\(3 downto 0),
      S(3) => \datacm_send[10]_i_7_n_0\,
      S(2) => \datacm_send[10]_i_8_n_0\,
      S(1) => \datacm_send[10]_i_9_n_0\,
      S(0) => \datacm_send[10]_i_10_n_0\
    );
\datacm_send_reg[10]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \datacm_send_reg[10]_i_3_n_0\,
      CO(2) => \datacm_send_reg[10]_i_3_n_1\,
      CO(1) => \datacm_send_reg[10]_i_3_n_2\,
      CO(0) => \datacm_send_reg[10]_i_3_n_3\,
      CYINIT => '0',
      DI(3) => fifo_read_length(7),
      DI(2) => '0',
      DI(1) => \datacm_send[10]_i_11_n_0\,
      DI(0) => \datacm_send[10]_i_12_n_0\,
      O(3 downto 0) => \NLW_datacm_send_reg[10]_i_3_O_UNCONNECTED\(3 downto 0),
      S(3) => \datacm_send[10]_i_13_n_0\,
      S(2) => \datacm_send[10]_i_14_n_0\,
      S(1) => \datacm_send[10]_i_15_n_0\,
      S(0) => \datacm_send[10]_i_16_n_0\
    );
\datacm_send_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => fifo_read_length(0),
      Q => datacm(2),
      R => \udp_packet_length0__0\
    );
\datacm_send_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => fifo_read_length(1),
      Q => datacm(3),
      R => \udp_packet_length0__0\
    );
\datacm_send_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => fifo_read_length(2),
      Q => datacm(4),
      R => \udp_packet_length0__0\
    );
\datacm_send_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => fifo_read_length(3),
      Q => datacm(5),
      R => \udp_packet_length0__0\
    );
\datacm_send_reg[6]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => fifo_read_length(4),
      Q => datacm(6),
      S => \udp_packet_length0__0\
    );
\datacm_send_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => fifo_read_length(5),
      Q => datacm(7),
      S => \udp_packet_length0__0\
    );
\datacm_send_reg[8]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => fifo_read_length(6),
      Q => datacm(8),
      S => \udp_packet_length0__0\
    );
\datacm_send_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => fifo_read_length(7),
      Q => datacm(9),
      R => \udp_packet_length0__0\
    );
eth_rstn_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0DDDFFFF0DDD0000"
    )
        port map (
      I0 => state(1),
      I1 => eth_rstn_i_3_n_0,
      I2 => eth_rstn_i_4_n_0,
      I3 => state(0),
      I4 => eth_rstn_i_5_n_0,
      I5 => eth_rstn,
      O => eth_rstn_i_1_n_0
    );
eth_rstn_i_10: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => po_counter_reg(16),
      I1 => po_counter_reg(14),
      I2 => po_counter_reg(15),
      O => eth_rstn_i_10_n_0
    );
eth_rstn_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rstn_counter_reg(12),
      I1 => eth_rstn_i_6_n_0,
      O => eth_rstn_i_3_n_0
    );
eth_rstn_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEEEE00000000"
    )
        port map (
      I0 => po_counter_reg(19),
      I1 => po_counter_reg(20),
      I2 => eth_rstn_i_7_n_0,
      I3 => po_counter_reg(18),
      I4 => po_counter_reg(17),
      I5 => po_counter_reg(21),
      O => eth_rstn_i_4_n_0
    );
eth_rstn_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"07777777"
    )
        port map (
      I0 => \state[1]_i_3__0_n_0\,
      I1 => state(1),
      I2 => eth_rstn_i_4_n_0,
      I3 => \state[1]_i_4__1_n_0\,
      I4 => state(0),
      O => eth_rstn_i_5_n_0
    );
eth_rstn_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000AAAAAAAB"
    )
        port map (
      I0 => \state[1]_i_6__0_n_0\,
      I1 => rstn_counter_reg(6),
      I2 => rstn_counter_reg(5),
      I3 => rstn_counter_reg(4),
      I4 => rstn_counter_reg(3),
      I5 => eth_rstn_i_8_n_0,
      O => eth_rstn_i_6_n_0
    );
eth_rstn_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000001101FFFF"
    )
        port map (
      I0 => po_counter_reg(11),
      I1 => po_counter_reg(12),
      I2 => po_counter_reg(10),
      I3 => eth_rstn_i_9_n_0,
      I4 => po_counter_reg(13),
      I5 => eth_rstn_i_10_n_0,
      O => eth_rstn_i_7_n_0
    );
eth_rstn_i_8: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rstn_counter_reg(10),
      I1 => rstn_counter_reg(11),
      O => eth_rstn_i_8_n_0
    );
eth_rstn_i_9: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000001FFFFFF"
    )
        port map (
      I0 => \state[1]_i_11__0_n_0\,
      I1 => po_counter_reg(5),
      I2 => po_counter_reg(6),
      I3 => po_counter_reg(8),
      I4 => po_counter_reg(7),
      I5 => po_counter_reg(9),
      O => eth_rstn_i_9_n_0
    );
eth_rstn_reg: unisim.vcomponents.FDCE
     port map (
      C => \^eth_refclk\,
      CE => '1',
      CLR => clear,
      D => eth_rstn_i_1_n_0,
      Q => eth_rstn
    );
fifo_we_reg: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => '1',
      D => Ethernet_receiver_n_36,
      Q => \^fifo_write_enable\,
      R => '0'
    );
\fifo_write_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_40,
      D => rx_data(0),
      Q => fifo_write_data(0),
      R => '0'
    );
\fifo_write_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_39,
      D => rx_data(2),
      Q => fifo_write_data(10),
      R => '0'
    );
\fifo_write_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_39,
      D => rx_data(3),
      Q => fifo_write_data(11),
      R => '0'
    );
\fifo_write_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_39,
      D => rx_data(4),
      Q => fifo_write_data(12),
      R => '0'
    );
\fifo_write_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_39,
      D => rx_data(5),
      Q => fifo_write_data(13),
      R => '0'
    );
\fifo_write_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_39,
      D => rx_data(6),
      Q => fifo_write_data(14),
      R => '0'
    );
\fifo_write_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_39,
      D => rx_data(7),
      Q => fifo_write_data(15),
      R => '0'
    );
\fifo_write_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(23),
      D => rx_data(0),
      Q => fifo_write_data(16),
      R => '0'
    );
\fifo_write_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(23),
      D => rx_data(1),
      Q => fifo_write_data(17),
      R => '0'
    );
\fifo_write_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(23),
      D => rx_data(2),
      Q => fifo_write_data(18),
      R => '0'
    );
\fifo_write_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(23),
      D => rx_data(3),
      Q => fifo_write_data(19),
      R => '0'
    );
\fifo_write_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_40,
      D => rx_data(1),
      Q => fifo_write_data(1),
      R => '0'
    );
\fifo_write_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(23),
      D => rx_data(4),
      Q => fifo_write_data(20),
      R => '0'
    );
\fifo_write_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(23),
      D => rx_data(5),
      Q => fifo_write_data(21),
      R => '0'
    );
\fifo_write_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(23),
      D => rx_data(6),
      Q => fifo_write_data(22),
      R => '0'
    );
\fifo_write_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(23),
      D => rx_data(7),
      Q => fifo_write_data(23),
      R => '0'
    );
\fifo_write_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(31),
      D => rx_data(0),
      Q => fifo_write_data(24),
      R => '0'
    );
\fifo_write_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(31),
      D => rx_data(1),
      Q => fifo_write_data(25),
      R => '0'
    );
\fifo_write_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(31),
      D => rx_data(2),
      Q => fifo_write_data(26),
      R => '0'
    );
\fifo_write_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(31),
      D => rx_data(3),
      Q => fifo_write_data(27),
      R => '0'
    );
\fifo_write_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(31),
      D => rx_data(4),
      Q => fifo_write_data(28),
      R => '0'
    );
\fifo_write_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(31),
      D => rx_data(5),
      Q => fifo_write_data(29),
      R => '0'
    );
\fifo_write_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_40,
      D => rx_data(2),
      Q => fifo_write_data(2),
      R => '0'
    );
\fifo_write_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(31),
      D => rx_data(6),
      Q => fifo_write_data(30),
      R => '0'
    );
\fifo_write_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => p_2_out(31),
      D => rx_data(7),
      Q => fifo_write_data(31),
      R => '0'
    );
\fifo_write_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_40,
      D => rx_data(3),
      Q => fifo_write_data(3),
      R => '0'
    );
\fifo_write_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_40,
      D => rx_data(4),
      Q => fifo_write_data(4),
      R => '0'
    );
\fifo_write_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_40,
      D => rx_data(5),
      Q => fifo_write_data(5),
      R => '0'
    );
\fifo_write_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_40,
      D => rx_data(6),
      Q => fifo_write_data(6),
      R => '0'
    );
\fifo_write_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_40,
      D => rx_data(7),
      Q => fifo_write_data(7),
      R => '0'
    );
\fifo_write_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_39,
      D => rx_data(0),
      Q => fifo_write_data(8),
      R => '0'
    );
\fifo_write_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      IS_C_INVERTED => '1'
    )
        port map (
      C => clk100mhz,
      CE => Ethernet_receiver_n_39,
      D => rx_data(1),
      Q => fifo_write_data(9),
      R => '0'
    );
init_proc_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => '1',
      D => Switch_n_5,
      Q => \init_proc__0\,
      R => '0'
    );
led16_b_reg_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => eth_rstn,
      O => led16_b_reg_i_2_n_0
    );
\po_counter[0]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => eth_rstn_i_4_n_0,
      O => \po_counter[0]_i_3_n_0\
    );
\po_counter[0]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(3),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[0]_i_4_n_0\
    );
\po_counter[0]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(2),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[0]_i_5_n_0\
    );
\po_counter[0]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(1),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[0]_i_6_n_0\
    );
\po_counter[0]_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => po_counter_reg(0),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[0]_i_7_n_0\
    );
\po_counter[12]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(15),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[12]_i_2_n_0\
    );
\po_counter[12]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(14),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[12]_i_3_n_0\
    );
\po_counter[12]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(13),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[12]_i_4_n_0\
    );
\po_counter[12]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(12),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[12]_i_5_n_0\
    );
\po_counter[16]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(19),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[16]_i_2_n_0\
    );
\po_counter[16]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(18),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[16]_i_3_n_0\
    );
\po_counter[16]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(17),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[16]_i_4_n_0\
    );
\po_counter[16]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(16),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[16]_i_5_n_0\
    );
\po_counter[20]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1011111100000000"
    )
        port map (
      I0 => po_counter_reg(19),
      I1 => po_counter_reg(20),
      I2 => eth_rstn_i_7_n_0,
      I3 => po_counter_reg(18),
      I4 => po_counter_reg(17),
      I5 => po_counter_reg(21),
      O => \po_counter[20]_i_2_n_0\
    );
\po_counter[20]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(20),
      I1 => po_counter_reg(21),
      O => \po_counter[20]_i_3_n_0\
    );
\po_counter[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(7),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[4]_i_2_n_0\
    );
\po_counter[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(6),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[4]_i_3_n_0\
    );
\po_counter[4]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(5),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[4]_i_4_n_0\
    );
\po_counter[4]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(4),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[4]_i_5_n_0\
    );
\po_counter[8]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(11),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[8]_i_2_n_0\
    );
\po_counter[8]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(10),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[8]_i_3_n_0\
    );
\po_counter[8]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(9),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[8]_i_4_n_0\
    );
\po_counter[8]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => po_counter_reg(8),
      I1 => eth_rstn_i_4_n_0,
      O => \po_counter[8]_i_5_n_0\
    );
\po_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[0]_i_2_n_7\,
      Q => po_counter_reg(0),
      R => '0'
    );
\po_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \po_counter_reg[0]_i_2_n_0\,
      CO(2) => \po_counter_reg[0]_i_2_n_1\,
      CO(1) => \po_counter_reg[0]_i_2_n_2\,
      CO(0) => \po_counter_reg[0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \po_counter[0]_i_3_n_0\,
      O(3) => \po_counter_reg[0]_i_2_n_4\,
      O(2) => \po_counter_reg[0]_i_2_n_5\,
      O(1) => \po_counter_reg[0]_i_2_n_6\,
      O(0) => \po_counter_reg[0]_i_2_n_7\,
      S(3) => \po_counter[0]_i_4_n_0\,
      S(2) => \po_counter[0]_i_5_n_0\,
      S(1) => \po_counter[0]_i_6_n_0\,
      S(0) => \po_counter[0]_i_7_n_0\
    );
\po_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[8]_i_1_n_5\,
      Q => po_counter_reg(10),
      R => '0'
    );
\po_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[8]_i_1_n_4\,
      Q => po_counter_reg(11),
      R => '0'
    );
\po_counter_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[12]_i_1_n_7\,
      Q => po_counter_reg(12),
      R => '0'
    );
\po_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \po_counter_reg[8]_i_1_n_0\,
      CO(3) => \po_counter_reg[12]_i_1_n_0\,
      CO(2) => \po_counter_reg[12]_i_1_n_1\,
      CO(1) => \po_counter_reg[12]_i_1_n_2\,
      CO(0) => \po_counter_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \po_counter_reg[12]_i_1_n_4\,
      O(2) => \po_counter_reg[12]_i_1_n_5\,
      O(1) => \po_counter_reg[12]_i_1_n_6\,
      O(0) => \po_counter_reg[12]_i_1_n_7\,
      S(3) => \po_counter[12]_i_2_n_0\,
      S(2) => \po_counter[12]_i_3_n_0\,
      S(1) => \po_counter[12]_i_4_n_0\,
      S(0) => \po_counter[12]_i_5_n_0\
    );
\po_counter_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[12]_i_1_n_6\,
      Q => po_counter_reg(13),
      R => '0'
    );
\po_counter_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[12]_i_1_n_5\,
      Q => po_counter_reg(14),
      R => '0'
    );
\po_counter_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[12]_i_1_n_4\,
      Q => po_counter_reg(15),
      R => '0'
    );
\po_counter_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[16]_i_1_n_7\,
      Q => po_counter_reg(16),
      R => '0'
    );
\po_counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \po_counter_reg[12]_i_1_n_0\,
      CO(3) => \po_counter_reg[16]_i_1_n_0\,
      CO(2) => \po_counter_reg[16]_i_1_n_1\,
      CO(1) => \po_counter_reg[16]_i_1_n_2\,
      CO(0) => \po_counter_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \po_counter_reg[16]_i_1_n_4\,
      O(2) => \po_counter_reg[16]_i_1_n_5\,
      O(1) => \po_counter_reg[16]_i_1_n_6\,
      O(0) => \po_counter_reg[16]_i_1_n_7\,
      S(3) => \po_counter[16]_i_2_n_0\,
      S(2) => \po_counter[16]_i_3_n_0\,
      S(1) => \po_counter[16]_i_4_n_0\,
      S(0) => \po_counter[16]_i_5_n_0\
    );
\po_counter_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[16]_i_1_n_6\,
      Q => po_counter_reg(17),
      R => '0'
    );
\po_counter_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[16]_i_1_n_5\,
      Q => po_counter_reg(18),
      R => '0'
    );
\po_counter_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[16]_i_1_n_4\,
      Q => po_counter_reg(19),
      R => '0'
    );
\po_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[0]_i_2_n_6\,
      Q => po_counter_reg(1),
      R => '0'
    );
\po_counter_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[20]_i_1_n_7\,
      Q => po_counter_reg(20),
      R => '0'
    );
\po_counter_reg[20]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \po_counter_reg[16]_i_1_n_0\,
      CO(3 downto 1) => \NLW_po_counter_reg[20]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \po_counter_reg[20]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 2) => \NLW_po_counter_reg[20]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1) => \po_counter_reg[20]_i_1_n_6\,
      O(0) => \po_counter_reg[20]_i_1_n_7\,
      S(3 downto 2) => B"00",
      S(1) => \po_counter[20]_i_2_n_0\,
      S(0) => \po_counter[20]_i_3_n_0\
    );
\po_counter_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[20]_i_1_n_6\,
      Q => po_counter_reg(21),
      R => '0'
    );
\po_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[0]_i_2_n_5\,
      Q => po_counter_reg(2),
      R => '0'
    );
\po_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[0]_i_2_n_4\,
      Q => po_counter_reg(3),
      R => '0'
    );
\po_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[4]_i_1_n_7\,
      Q => po_counter_reg(4),
      R => '0'
    );
\po_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \po_counter_reg[0]_i_2_n_0\,
      CO(3) => \po_counter_reg[4]_i_1_n_0\,
      CO(2) => \po_counter_reg[4]_i_1_n_1\,
      CO(1) => \po_counter_reg[4]_i_1_n_2\,
      CO(0) => \po_counter_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \po_counter_reg[4]_i_1_n_4\,
      O(2) => \po_counter_reg[4]_i_1_n_5\,
      O(1) => \po_counter_reg[4]_i_1_n_6\,
      O(0) => \po_counter_reg[4]_i_1_n_7\,
      S(3) => \po_counter[4]_i_2_n_0\,
      S(2) => \po_counter[4]_i_3_n_0\,
      S(1) => \po_counter[4]_i_4_n_0\,
      S(0) => \po_counter[4]_i_5_n_0\
    );
\po_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[4]_i_1_n_6\,
      Q => po_counter_reg(5),
      R => '0'
    );
\po_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[4]_i_1_n_5\,
      Q => po_counter_reg(6),
      R => '0'
    );
\po_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[4]_i_1_n_4\,
      Q => po_counter_reg(7),
      R => '0'
    );
\po_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[8]_i_1_n_7\,
      Q => po_counter_reg(8),
      R => '0'
    );
\po_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \po_counter_reg[4]_i_1_n_0\,
      CO(3) => \po_counter_reg[8]_i_1_n_0\,
      CO(2) => \po_counter_reg[8]_i_1_n_1\,
      CO(1) => \po_counter_reg[8]_i_1_n_2\,
      CO(0) => \po_counter_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \po_counter_reg[8]_i_1_n_4\,
      O(2) => \po_counter_reg[8]_i_1_n_5\,
      O(1) => \po_counter_reg[8]_i_1_n_6\,
      O(0) => \po_counter_reg[8]_i_1_n_7\,
      S(3) => \po_counter[8]_i_2_n_0\,
      S(2) => \po_counter[8]_i_3_n_0\,
      S(1) => \po_counter[8]_i_4_n_0\,
      S(0) => \po_counter[8]_i_5_n_0\
    );
\po_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => po_counter0,
      D => \po_counter_reg[8]_i_1_n_6\,
      Q => po_counter_reg(9),
      R => '0'
    );
\rstn_counter[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => state(1),
      I1 => \state[1]_i_3__0_n_0\,
      O => \rstn_counter[0]_i_1_n_0\
    );
\rstn_counter[0]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => eth_rstn_i_3_n_0,
      O => \rstn_counter[0]_i_3_n_0\
    );
\rstn_counter[0]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D850"
    )
        port map (
      I0 => eth_rstn_i_3_n_0,
      I1 => \state[1]_i_5__0_n_0\,
      I2 => rstn_counter_reg(3),
      I3 => rstn_counter0(3),
      O => \rstn_counter[0]_i_4_n_0\
    );
\rstn_counter[0]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D850"
    )
        port map (
      I0 => eth_rstn_i_3_n_0,
      I1 => \state[1]_i_5__0_n_0\,
      I2 => rstn_counter_reg(2),
      I3 => rstn_counter0(2),
      O => \rstn_counter[0]_i_5_n_0\
    );
\rstn_counter[0]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D850"
    )
        port map (
      I0 => eth_rstn_i_3_n_0,
      I1 => \state[1]_i_5__0_n_0\,
      I2 => rstn_counter_reg(1),
      I3 => rstn_counter0(1),
      O => \rstn_counter[0]_i_6_n_0\
    );
\rstn_counter[0]_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => eth_rstn_i_3_n_0,
      I1 => \state[1]_i_5__0_n_0\,
      I2 => rstn_counter_reg(0),
      O => \rstn_counter[0]_i_7_n_0\
    );
\rstn_counter[12]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F888F000"
    )
        port map (
      I0 => eth_rstn_i_3_n_0,
      I1 => \state[1]_i_5__0_n_0\,
      I2 => eth_rstn_i_6_n_0,
      I3 => rstn_counter_reg(12),
      I4 => rstn_counter0(12),
      O => \rstn_counter[12]_i_2_n_0\
    );
\rstn_counter[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D850"
    )
        port map (
      I0 => eth_rstn_i_3_n_0,
      I1 => \state[1]_i_5__0_n_0\,
      I2 => rstn_counter_reg(7),
      I3 => rstn_counter0(7),
      O => \rstn_counter[4]_i_2_n_0\
    );
\rstn_counter[4]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D850"
    )
        port map (
      I0 => eth_rstn_i_3_n_0,
      I1 => \state[1]_i_5__0_n_0\,
      I2 => rstn_counter_reg(6),
      I3 => rstn_counter0(6),
      O => \rstn_counter[4]_i_3_n_0\
    );
\rstn_counter[4]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D850"
    )
        port map (
      I0 => eth_rstn_i_3_n_0,
      I1 => \state[1]_i_5__0_n_0\,
      I2 => rstn_counter_reg(5),
      I3 => rstn_counter0(5),
      O => \rstn_counter[4]_i_4_n_0\
    );
\rstn_counter[4]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D850"
    )
        port map (
      I0 => eth_rstn_i_3_n_0,
      I1 => \state[1]_i_5__0_n_0\,
      I2 => rstn_counter_reg(4),
      I3 => rstn_counter0(4),
      O => \rstn_counter[4]_i_5_n_0\
    );
\rstn_counter[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8F880F00"
    )
        port map (
      I0 => eth_rstn_i_3_n_0,
      I1 => \state[1]_i_5__0_n_0\,
      I2 => rstn_counter_reg(12),
      I3 => rstn_counter_reg(11),
      I4 => rstn_counter0(11),
      O => \rstn_counter[8]_i_2_n_0\
    );
\rstn_counter[8]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8F880F00"
    )
        port map (
      I0 => eth_rstn_i_3_n_0,
      I1 => \state[1]_i_5__0_n_0\,
      I2 => rstn_counter_reg(12),
      I3 => rstn_counter_reg(10),
      I4 => rstn_counter0(10),
      O => \rstn_counter[8]_i_3_n_0\
    );
\rstn_counter[8]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D850"
    )
        port map (
      I0 => eth_rstn_i_3_n_0,
      I1 => \state[1]_i_5__0_n_0\,
      I2 => rstn_counter_reg(9),
      I3 => rstn_counter0(9),
      O => \rstn_counter[8]_i_4_n_0\
    );
\rstn_counter[8]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D850"
    )
        port map (
      I0 => eth_rstn_i_3_n_0,
      I1 => \state[1]_i_5__0_n_0\,
      I2 => rstn_counter_reg(8),
      I3 => rstn_counter0(8),
      O => \rstn_counter[8]_i_5_n_0\
    );
\rstn_counter_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => \rstn_counter[0]_i_1_n_0\,
      CLR => clear,
      D => \rstn_counter_reg[0]_i_2_n_7\,
      Q => rstn_counter_reg(0)
    );
\rstn_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \rstn_counter_reg[0]_i_2_n_0\,
      CO(2) => \rstn_counter_reg[0]_i_2_n_1\,
      CO(1) => \rstn_counter_reg[0]_i_2_n_2\,
      CO(0) => \rstn_counter_reg[0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \rstn_counter[0]_i_3_n_0\,
      O(3) => \rstn_counter_reg[0]_i_2_n_4\,
      O(2) => \rstn_counter_reg[0]_i_2_n_5\,
      O(1) => \rstn_counter_reg[0]_i_2_n_6\,
      O(0) => \rstn_counter_reg[0]_i_2_n_7\,
      S(3) => \rstn_counter[0]_i_4_n_0\,
      S(2) => \rstn_counter[0]_i_5_n_0\,
      S(1) => \rstn_counter[0]_i_6_n_0\,
      S(0) => \rstn_counter[0]_i_7_n_0\
    );
\rstn_counter_reg[0]_i_8\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \rstn_counter_reg[0]_i_8_n_0\,
      CO(2) => \rstn_counter_reg[0]_i_8_n_1\,
      CO(1) => \rstn_counter_reg[0]_i_8_n_2\,
      CO(0) => \rstn_counter_reg[0]_i_8_n_3\,
      CYINIT => rstn_counter_reg(0),
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => rstn_counter0(4 downto 1),
      S(3 downto 0) => rstn_counter_reg(4 downto 1)
    );
\rstn_counter_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => \rstn_counter[0]_i_1_n_0\,
      CLR => clear,
      D => \rstn_counter_reg[8]_i_1_n_5\,
      Q => rstn_counter_reg(10)
    );
\rstn_counter_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => \rstn_counter[0]_i_1_n_0\,
      CLR => clear,
      D => \rstn_counter_reg[8]_i_1_n_4\,
      Q => rstn_counter_reg(11)
    );
\rstn_counter_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => \rstn_counter[0]_i_1_n_0\,
      CLR => clear,
      D => \rstn_counter_reg[12]_i_1_n_7\,
      Q => rstn_counter_reg(12)
    );
\rstn_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \rstn_counter_reg[8]_i_1_n_0\,
      CO(3 downto 0) => \NLW_rstn_counter_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_rstn_counter_reg[12]_i_1_O_UNCONNECTED\(3 downto 1),
      O(0) => \rstn_counter_reg[12]_i_1_n_7\,
      S(3 downto 1) => B"000",
      S(0) => \rstn_counter[12]_i_2_n_0\
    );
\rstn_counter_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => \rstn_counter[0]_i_1_n_0\,
      CLR => clear,
      D => \rstn_counter_reg[0]_i_2_n_6\,
      Q => rstn_counter_reg(1)
    );
\rstn_counter_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => \rstn_counter[0]_i_1_n_0\,
      CLR => clear,
      D => \rstn_counter_reg[0]_i_2_n_5\,
      Q => rstn_counter_reg(2)
    );
\rstn_counter_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => \rstn_counter[0]_i_1_n_0\,
      CLR => clear,
      D => \rstn_counter_reg[0]_i_2_n_4\,
      Q => rstn_counter_reg(3)
    );
\rstn_counter_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => \rstn_counter[0]_i_1_n_0\,
      CLR => clear,
      D => \rstn_counter_reg[4]_i_1_n_7\,
      Q => rstn_counter_reg(4)
    );
\rstn_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \rstn_counter_reg[0]_i_2_n_0\,
      CO(3) => \rstn_counter_reg[4]_i_1_n_0\,
      CO(2) => \rstn_counter_reg[4]_i_1_n_1\,
      CO(1) => \rstn_counter_reg[4]_i_1_n_2\,
      CO(0) => \rstn_counter_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \rstn_counter_reg[4]_i_1_n_4\,
      O(2) => \rstn_counter_reg[4]_i_1_n_5\,
      O(1) => \rstn_counter_reg[4]_i_1_n_6\,
      O(0) => \rstn_counter_reg[4]_i_1_n_7\,
      S(3) => \rstn_counter[4]_i_2_n_0\,
      S(2) => \rstn_counter[4]_i_3_n_0\,
      S(1) => \rstn_counter[4]_i_4_n_0\,
      S(0) => \rstn_counter[4]_i_5_n_0\
    );
\rstn_counter_reg[4]_i_6\: unisim.vcomponents.CARRY4
     port map (
      CI => \rstn_counter_reg[0]_i_8_n_0\,
      CO(3) => \rstn_counter_reg[4]_i_6_n_0\,
      CO(2) => \rstn_counter_reg[4]_i_6_n_1\,
      CO(1) => \rstn_counter_reg[4]_i_6_n_2\,
      CO(0) => \rstn_counter_reg[4]_i_6_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => rstn_counter0(8 downto 5),
      S(3 downto 0) => rstn_counter_reg(8 downto 5)
    );
\rstn_counter_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => \rstn_counter[0]_i_1_n_0\,
      CLR => clear,
      D => \rstn_counter_reg[4]_i_1_n_6\,
      Q => rstn_counter_reg(5)
    );
\rstn_counter_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => \rstn_counter[0]_i_1_n_0\,
      CLR => clear,
      D => \rstn_counter_reg[4]_i_1_n_5\,
      Q => rstn_counter_reg(6)
    );
\rstn_counter_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => \rstn_counter[0]_i_1_n_0\,
      CLR => clear,
      D => \rstn_counter_reg[4]_i_1_n_4\,
      Q => rstn_counter_reg(7)
    );
\rstn_counter_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => \rstn_counter[0]_i_1_n_0\,
      CLR => clear,
      D => \rstn_counter_reg[8]_i_1_n_7\,
      Q => rstn_counter_reg(8)
    );
\rstn_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \rstn_counter_reg[4]_i_1_n_0\,
      CO(3) => \rstn_counter_reg[8]_i_1_n_0\,
      CO(2) => \rstn_counter_reg[8]_i_1_n_1\,
      CO(1) => \rstn_counter_reg[8]_i_1_n_2\,
      CO(0) => \rstn_counter_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \rstn_counter_reg[8]_i_1_n_4\,
      O(2) => \rstn_counter_reg[8]_i_1_n_5\,
      O(1) => \rstn_counter_reg[8]_i_1_n_6\,
      O(0) => \rstn_counter_reg[8]_i_1_n_7\,
      S(3) => \rstn_counter[8]_i_2_n_0\,
      S(2) => \rstn_counter[8]_i_3_n_0\,
      S(1) => \rstn_counter[8]_i_4_n_0\,
      S(0) => \rstn_counter[8]_i_5_n_0\
    );
\rstn_counter_reg[8]_i_6\: unisim.vcomponents.CARRY4
     port map (
      CI => \rstn_counter_reg[4]_i_6_n_0\,
      CO(3) => \NLW_rstn_counter_reg[8]_i_6_CO_UNCONNECTED\(3),
      CO(2) => \rstn_counter_reg[8]_i_6_n_1\,
      CO(1) => \rstn_counter_reg[8]_i_6_n_2\,
      CO(0) => \rstn_counter_reg[8]_i_6_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => rstn_counter0(12 downto 9),
      S(3 downto 0) => rstn_counter_reg(12 downto 9)
    );
\rstn_counter_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => \rstn_counter[0]_i_1_n_0\,
      CLR => clear,
      D => \rstn_counter_reg[8]_i_1_n_6\,
      Q => rstn_counter_reg(9)
    );
\send_countdown[0]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => send_countdown_reg(0),
      I1 => send_countdown_reg(1),
      I2 => send_countdown_reg(12),
      I3 => send_countdown_reg(7),
      O => \send_countdown[0]_i_10_n_0\
    );
\send_countdown[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000002"
    )
        port map (
      I0 => \send_countdown[0]_i_9_n_0\,
      I1 => \send_countdown[0]_i_10_n_0\,
      I2 => send_countdown_reg(10),
      I3 => send_countdown_reg(9),
      I4 => send_countdown_reg(3),
      O => \send_countdown[0]_i_4_n_0\
    );
\send_countdown[0]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => send_countdown_reg(3),
      O => \send_countdown[0]_i_5_n_0\
    );
\send_countdown[0]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => send_countdown_reg(2),
      O => \send_countdown[0]_i_6_n_0\
    );
\send_countdown[0]_i_7\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => send_countdown_reg(1),
      O => \send_countdown[0]_i_7_n_0\
    );
\send_countdown[0]_i_8\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => send_countdown_reg(0),
      O => \send_countdown[0]_i_8_n_0\
    );
\send_countdown[0]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => send_countdown_reg(8),
      I1 => send_countdown_reg(6),
      I2 => send_countdown_reg(2),
      I3 => send_countdown_reg(11),
      I4 => send_countdown_reg(4),
      I5 => send_countdown_reg(5),
      O => \send_countdown[0]_i_9_n_0\
    );
\send_countdown[12]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => send_countdown_reg(12),
      O => \send_countdown[12]_i_2_n_0\
    );
\send_countdown[4]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => send_countdown_reg(7),
      O => \send_countdown[4]_i_2_n_0\
    );
\send_countdown[4]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => send_countdown_reg(6),
      O => \send_countdown[4]_i_3_n_0\
    );
\send_countdown[4]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => send_countdown_reg(5),
      O => \send_countdown[4]_i_4_n_0\
    );
\send_countdown[4]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => send_countdown_reg(4),
      O => \send_countdown[4]_i_5_n_0\
    );
\send_countdown[8]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => send_countdown_reg(11),
      O => \send_countdown[8]_i_2_n_0\
    );
\send_countdown[8]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => send_countdown_reg(10),
      O => \send_countdown[8]_i_3_n_0\
    );
\send_countdown[8]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => send_countdown_reg(9),
      O => \send_countdown[8]_i_4_n_0\
    );
\send_countdown[8]_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => send_countdown_reg(8),
      O => \send_countdown[8]_i_5_n_0\
    );
\send_countdown_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => send_countdown0,
      D => \send_countdown_reg[0]_i_3_n_7\,
      Q => send_countdown_reg(0),
      R => Ethernet_transmitter_n_6
    );
\send_countdown_reg[0]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \send_countdown_reg[0]_i_3_n_0\,
      CO(2) => \send_countdown_reg[0]_i_3_n_1\,
      CO(1) => \send_countdown_reg[0]_i_3_n_2\,
      CO(0) => \send_countdown_reg[0]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \send_countdown_reg[0]_i_3_n_4\,
      O(2) => \send_countdown_reg[0]_i_3_n_5\,
      O(1) => \send_countdown_reg[0]_i_3_n_6\,
      O(0) => \send_countdown_reg[0]_i_3_n_7\,
      S(3) => \send_countdown[0]_i_5_n_0\,
      S(2) => \send_countdown[0]_i_6_n_0\,
      S(1) => \send_countdown[0]_i_7_n_0\,
      S(0) => \send_countdown[0]_i_8_n_0\
    );
\send_countdown_reg[10]\: unisim.vcomponents.FDSE
     port map (
      C => \^eth_refclk\,
      CE => send_countdown0,
      D => \send_countdown_reg[8]_i_1_n_5\,
      Q => send_countdown_reg(10),
      S => Ethernet_transmitter_n_6
    );
\send_countdown_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => send_countdown0,
      D => \send_countdown_reg[8]_i_1_n_4\,
      Q => send_countdown_reg(11),
      R => Ethernet_transmitter_n_6
    );
\send_countdown_reg[12]\: unisim.vcomponents.FDSE
     port map (
      C => \^eth_refclk\,
      CE => send_countdown0,
      D => \send_countdown_reg[12]_i_1_n_7\,
      Q => send_countdown_reg(12),
      S => Ethernet_transmitter_n_6
    );
\send_countdown_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \send_countdown_reg[8]_i_1_n_0\,
      CO(3 downto 0) => \NLW_send_countdown_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_send_countdown_reg[12]_i_1_O_UNCONNECTED\(3 downto 1),
      O(0) => \send_countdown_reg[12]_i_1_n_7\,
      S(3 downto 1) => B"000",
      S(0) => \send_countdown[12]_i_2_n_0\
    );
\send_countdown_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => send_countdown0,
      D => \send_countdown_reg[0]_i_3_n_6\,
      Q => send_countdown_reg(1),
      R => Ethernet_transmitter_n_6
    );
\send_countdown_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => send_countdown0,
      D => \send_countdown_reg[0]_i_3_n_5\,
      Q => send_countdown_reg(2),
      R => Ethernet_transmitter_n_6
    );
\send_countdown_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => send_countdown0,
      D => \send_countdown_reg[0]_i_3_n_4\,
      Q => send_countdown_reg(3),
      R => Ethernet_transmitter_n_6
    );
\send_countdown_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => \^eth_refclk\,
      CE => send_countdown0,
      D => \send_countdown_reg[4]_i_1_n_7\,
      Q => send_countdown_reg(4),
      S => Ethernet_transmitter_n_6
    );
\send_countdown_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \send_countdown_reg[0]_i_3_n_0\,
      CO(3) => \send_countdown_reg[4]_i_1_n_0\,
      CO(2) => \send_countdown_reg[4]_i_1_n_1\,
      CO(1) => \send_countdown_reg[4]_i_1_n_2\,
      CO(0) => \send_countdown_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \send_countdown_reg[4]_i_1_n_4\,
      O(2) => \send_countdown_reg[4]_i_1_n_5\,
      O(1) => \send_countdown_reg[4]_i_1_n_6\,
      O(0) => \send_countdown_reg[4]_i_1_n_7\,
      S(3) => \send_countdown[4]_i_2_n_0\,
      S(2) => \send_countdown[4]_i_3_n_0\,
      S(1) => \send_countdown[4]_i_4_n_0\,
      S(0) => \send_countdown[4]_i_5_n_0\
    );
\send_countdown_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => \^eth_refclk\,
      CE => send_countdown0,
      D => \send_countdown_reg[4]_i_1_n_6\,
      Q => send_countdown_reg(5),
      S => Ethernet_transmitter_n_6
    );
\send_countdown_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => \^eth_refclk\,
      CE => send_countdown0,
      D => \send_countdown_reg[4]_i_1_n_5\,
      Q => send_countdown_reg(6),
      S => Ethernet_transmitter_n_6
    );
\send_countdown_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => send_countdown0,
      D => \send_countdown_reg[4]_i_1_n_4\,
      Q => send_countdown_reg(7),
      R => Ethernet_transmitter_n_6
    );
\send_countdown_reg[8]\: unisim.vcomponents.FDSE
     port map (
      C => \^eth_refclk\,
      CE => send_countdown0,
      D => \send_countdown_reg[8]_i_1_n_7\,
      Q => send_countdown_reg(8),
      S => Ethernet_transmitter_n_6
    );
\send_countdown_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \send_countdown_reg[4]_i_1_n_0\,
      CO(3) => \send_countdown_reg[8]_i_1_n_0\,
      CO(2) => \send_countdown_reg[8]_i_1_n_1\,
      CO(1) => \send_countdown_reg[8]_i_1_n_2\,
      CO(0) => \send_countdown_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"1111",
      O(3) => \send_countdown_reg[8]_i_1_n_4\,
      O(2) => \send_countdown_reg[8]_i_1_n_5\,
      O(1) => \send_countdown_reg[8]_i_1_n_6\,
      O(0) => \send_countdown_reg[8]_i_1_n_7\,
      S(3) => \send_countdown[8]_i_2_n_0\,
      S(2) => \send_countdown[8]_i_3_n_0\,
      S(1) => \send_countdown[8]_i_4_n_0\,
      S(0) => \send_countdown[8]_i_5_n_0\
    );
\send_countdown_reg[9]\: unisim.vcomponents.FDSE
     port map (
      C => \^eth_refclk\,
      CE => send_countdown0,
      D => \send_countdown_reg[8]_i_1_n_6\,
      Q => send_countdown_reg(9),
      S => Ethernet_transmitter_n_6
    );
\state[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFC0FF05050505"
    )
        port map (
      I0 => \init_proc__0\,
      I1 => \state[1]_i_3__0_n_0\,
      I2 => state(1),
      I3 => eth_rstn_i_4_n_0,
      I4 => \state[1]_i_4__1_n_0\,
      I5 => state(0),
      O => \state[0]_i_1__0_n_0\
    );
\state[1]_i_10__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => po_counter_reg(11),
      I1 => po_counter_reg(12),
      I2 => po_counter_reg(15),
      I3 => po_counter_reg(14),
      I4 => po_counter_reg(6),
      I5 => po_counter_reg(5),
      O => \state[1]_i_10__0_n_0\
    );
\state[1]_i_11__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => po_counter_reg(3),
      I1 => po_counter_reg(2),
      I2 => po_counter_reg(0),
      I3 => po_counter_reg(4),
      I4 => po_counter_reg(1),
      O => \state[1]_i_11__0_n_0\
    );
\state[1]_i_12__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000000001FF"
    )
        port map (
      I0 => rstn_counter_reg(2),
      I1 => rstn_counter_reg(3),
      I2 => rstn_counter_reg(1),
      I3 => rstn_counter_reg(4),
      I4 => rstn_counter_reg(5),
      I5 => rstn_counter_reg(6),
      O => \state[1]_i_12__0_n_0\
    );
\state[1]_i_13__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => po_counter_reg(19),
      I1 => po_counter_reg(20),
      I2 => po_counter_reg(17),
      I3 => po_counter_reg(18),
      O => \state[1]_i_13__0_n_0\
    );
\state[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0D0FFD0D0D0D0D0"
    )
        port map (
      I0 => \state[1]_i_2__1_n_0\,
      I1 => \state[1]_i_3__0_n_0\,
      I2 => state(1),
      I3 => eth_rstn_i_4_n_0,
      I4 => \state[1]_i_4__1_n_0\,
      I5 => state(0),
      O => \state[1]_i_1__0_n_0\
    );
\state[1]_i_2__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rstn_counter_reg(12),
      I1 => \state[1]_i_5__0_n_0\,
      O => \state[1]_i_2__1_n_0\
    );
\state[1]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5500540055005500"
    )
        port map (
      I0 => \state[1]_i_5__0_n_0\,
      I1 => \state[1]_i_6__0_n_0\,
      I2 => rstn_counter_reg(0),
      I3 => rstn_counter_reg(12),
      I4 => \state[1]_i_7__0_n_0\,
      I5 => \state[1]_i_8_n_0\,
      O => \state[1]_i_3__0_n_0\
    );
\state[1]_i_4__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \state[1]_i_9__0_n_0\,
      I1 => po_counter_reg(8),
      I2 => po_counter_reg(16),
      I3 => po_counter_reg(21),
      I4 => \state[1]_i_10__0_n_0\,
      I5 => \state[1]_i_11__0_n_0\,
      O => \state[1]_i_4__1_n_0\
    );
\state[1]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1011111111111111"
    )
        port map (
      I0 => rstn_counter_reg(11),
      I1 => rstn_counter_reg(10),
      I2 => \state[1]_i_12__0_n_0\,
      I3 => rstn_counter_reg(8),
      I4 => rstn_counter_reg(9),
      I5 => rstn_counter_reg(7),
      O => \state[1]_i_5__0_n_0\
    );
\state[1]_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => rstn_counter_reg(8),
      I1 => rstn_counter_reg(9),
      I2 => rstn_counter_reg(7),
      O => \state[1]_i_6__0_n_0\
    );
\state[1]_i_7__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rstn_counter_reg(5),
      I1 => rstn_counter_reg(6),
      O => \state[1]_i_7__0_n_0\
    );
\state[1]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000008"
    )
        port map (
      I0 => rstn_counter_reg(4),
      I1 => rstn_counter_reg(1),
      I2 => rstn_counter_reg(2),
      I3 => rstn_counter_reg(3),
      I4 => rstn_counter_reg(10),
      I5 => rstn_counter_reg(11),
      O => \state[1]_i_8_n_0\
    );
\state[1]_i_9__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFBFFF"
    )
        port map (
      I0 => po_counter_reg(9),
      I1 => po_counter_reg(13),
      I2 => po_counter_reg(10),
      I3 => po_counter_reg(7),
      I4 => \state[1]_i_13__0_n_0\,
      O => \state[1]_i_9__0_n_0\
    );
\state_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => '1',
      CLR => clear,
      D => \state[0]_i_1__0_n_0\,
      Q => state(0)
    );
\state_reg[1]\: unisim.vcomponents.FDPE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^eth_refclk\,
      CE => '1',
      D => \state[1]_i_1__0_n_0\,
      PRE => clear,
      Q => state(1)
    );
tx_data_valid_reg: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => '1',
      D => Ethernet_transmitter_n_4,
      Q => tx_data_valid,
      R => '0'
    );
\udp_packet_length[5]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fifo_read_length(1),
      O => \udp_packet_length[5]_i_2_n_0\
    );
\udp_packet_length_reg[10]\: unisim.vcomponents.FDSE
     port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => udp_packet_length0(10),
      Q => udp_packet_length(10),
      S => \udp_packet_length0__0\
    );
\udp_packet_length_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => udp_packet_length0(11),
      Q => udp_packet_length(11),
      R => \udp_packet_length0__0\
    );
\udp_packet_length_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => udp_packet_length0(12),
      Q => udp_packet_length(12),
      R => \udp_packet_length0__0\
    );
\udp_packet_length_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => udp_packet_length0(13),
      Q => udp_packet_length(13),
      R => \udp_packet_length0__0\
    );
\udp_packet_length_reg[13]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_packet_length_reg[9]_i_1_n_0\,
      CO(3) => \udp_packet_length_reg[13]_i_1_n_0\,
      CO(2) => \udp_packet_length_reg[13]_i_1_n_1\,
      CO(1) => \udp_packet_length_reg[13]_i_1_n_2\,
      CO(0) => \udp_packet_length_reg[13]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => udp_packet_length0(13 downto 10),
      S(3 downto 0) => fifo_read_length(11 downto 8)
    );
\udp_packet_length_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => udp_packet_length0(14),
      Q => udp_packet_length(14),
      R => \udp_packet_length0__0\
    );
\udp_packet_length_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => udp_packet_length0(15),
      Q => udp_packet_length(15),
      R => \udp_packet_length0__0\
    );
\udp_packet_length_reg[15]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_packet_length_reg[13]_i_1_n_0\,
      CO(3 downto 1) => \NLW_udp_packet_length_reg[15]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \udp_packet_length_reg[15]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 2) => \NLW_udp_packet_length_reg[15]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => udp_packet_length0(15 downto 14),
      S(3 downto 2) => B"00",
      S(1 downto 0) => fifo_read_length(13 downto 12)
    );
\udp_packet_length_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => udp_packet_length0(2),
      Q => udp_packet_length(2),
      R => \udp_packet_length0__0\
    );
\udp_packet_length_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => udp_packet_length0(3),
      Q => udp_packet_length(3),
      S => \udp_packet_length0__0\
    );
\udp_packet_length_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => udp_packet_length0(4),
      Q => udp_packet_length(4),
      R => \udp_packet_length0__0\
    );
\udp_packet_length_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => udp_packet_length0(5),
      Q => udp_packet_length(5),
      R => \udp_packet_length0__0\
    );
\udp_packet_length_reg[5]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \udp_packet_length_reg[5]_i_1_n_0\,
      CO(2) => \udp_packet_length_reg[5]_i_1_n_1\,
      CO(1) => \udp_packet_length_reg[5]_i_1_n_2\,
      CO(0) => \udp_packet_length_reg[5]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => fifo_read_length(1),
      DI(0) => '0',
      O(3 downto 0) => udp_packet_length0(5 downto 2),
      S(3 downto 2) => fifo_read_length(3 downto 2),
      S(1) => \udp_packet_length[5]_i_2_n_0\,
      S(0) => fifo_read_length(0)
    );
\udp_packet_length_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => udp_packet_length0(6),
      Q => udp_packet_length(6),
      S => \udp_packet_length0__0\
    );
\udp_packet_length_reg[7]\: unisim.vcomponents.FDSE
     port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => udp_packet_length0(7),
      Q => udp_packet_length(7),
      S => \udp_packet_length0__0\
    );
\udp_packet_length_reg[8]\: unisim.vcomponents.FDSE
     port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => udp_packet_length0(8),
      Q => udp_packet_length(8),
      S => \udp_packet_length0__0\
    );
\udp_packet_length_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \^eth_refclk\,
      CE => db_sw,
      D => udp_packet_length0(9),
      Q => udp_packet_length(9),
      R => \udp_packet_length0__0\
    );
\udp_packet_length_reg[9]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \udp_packet_length_reg[5]_i_1_n_0\,
      CO(3) => \udp_packet_length_reg[9]_i_1_n_0\,
      CO(2) => \udp_packet_length_reg[9]_i_1_n_1\,
      CO(1) => \udp_packet_length_reg[9]_i_1_n_2\,
      CO(0) => \udp_packet_length_reg[9]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => udp_packet_length0(9 downto 6),
      S(3 downto 0) => fifo_read_length(7 downto 4)
    );
udp_packet_sending_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => arp_response_pending,
      I1 => udp_send_data_valid_reg_n_0,
      I2 => tx_data_valid,
      O => udp_packet_sending
    );
udp_send_data_valid_i_11: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fifo_read_length(14),
      I1 => fifo_read_length(15),
      O => udp_send_data_valid_i_11_n_0
    );
udp_send_data_valid_i_12: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fifo_read_length(12),
      I1 => fifo_read_length(13),
      O => udp_send_data_valid_i_12_n_0
    );
udp_send_data_valid_i_13: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fifo_read_length(10),
      I1 => fifo_read_length(11),
      O => udp_send_data_valid_i_13_n_0
    );
udp_send_data_valid_i_14: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fifo_read_length(8),
      I1 => fifo_read_length(9),
      O => udp_send_data_valid_i_14_n_0
    );
udp_send_data_valid_i_15: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fifo_read_length(15),
      I1 => fifo_read_length(14),
      O => udp_send_data_valid_i_15_n_0
    );
udp_send_data_valid_i_16: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fifo_read_length(13),
      I1 => fifo_read_length(12),
      O => udp_send_data_valid_i_16_n_0
    );
udp_send_data_valid_i_17: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fifo_read_length(11),
      I1 => fifo_read_length(10),
      O => udp_send_data_valid_i_17_n_0
    );
udp_send_data_valid_i_18: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fifo_read_length(9),
      I1 => fifo_read_length(8),
      O => udp_send_data_valid_i_18_n_0
    );
udp_send_data_valid_i_21: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fifo_read_length(6),
      I1 => fifo_read_length(7),
      O => udp_send_data_valid_i_21_n_0
    );
udp_send_data_valid_i_22: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fifo_read_length(5),
      I1 => fifo_read_length(4),
      O => udp_send_data_valid_i_22_n_0
    );
udp_send_data_valid_i_23: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fifo_read_length(2),
      I1 => fifo_read_length(3),
      O => udp_send_data_valid_i_23_n_0
    );
udp_send_data_valid_i_24: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => fifo_read_length(0),
      I1 => fifo_read_length(1),
      O => udp_send_data_valid_i_24_n_0
    );
udp_send_data_valid_i_25: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fifo_read_length(7),
      I1 => fifo_read_length(6),
      O => udp_send_data_valid_i_25_n_0
    );
udp_send_data_valid_i_26: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fifo_read_length(4),
      I1 => fifo_read_length(5),
      O => udp_send_data_valid_i_26_n_0
    );
udp_send_data_valid_i_27: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fifo_read_length(3),
      I1 => fifo_read_length(2),
      O => udp_send_data_valid_i_27_n_0
    );
udp_send_data_valid_i_28: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => fifo_read_length(1),
      I1 => fifo_read_length(0),
      O => udp_send_data_valid_i_28_n_0
    );
udp_send_data_valid_reg: unisim.vcomponents.FDCE
     port map (
      C => \^eth_refclk\,
      CE => '1',
      CLR => clear,
      D => udp_send_data_valid,
      Q => udp_send_data_valid_reg_n_0
    );
udp_send_data_valid_reg_i_10: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => udp_send_data_valid_reg_i_10_n_0,
      CO(2) => udp_send_data_valid_reg_i_10_n_1,
      CO(1) => udp_send_data_valid_reg_i_10_n_2,
      CO(0) => udp_send_data_valid_reg_i_10_n_3,
      CYINIT => '0',
      DI(3) => udp_send_data_valid_i_21_n_0,
      DI(2) => udp_send_data_valid_i_22_n_0,
      DI(1) => udp_send_data_valid_i_23_n_0,
      DI(0) => udp_send_data_valid_i_24_n_0,
      O(3 downto 0) => NLW_udp_send_data_valid_reg_i_10_O_UNCONNECTED(3 downto 0),
      S(3) => udp_send_data_valid_i_25_n_0,
      S(2) => udp_send_data_valid_i_26_n_0,
      S(1) => udp_send_data_valid_i_27_n_0,
      S(0) => udp_send_data_valid_i_28_n_0
    );
udp_send_data_valid_reg_i_5: unisim.vcomponents.CARRY4
     port map (
      CI => udp_send_data_valid_reg_i_10_n_0,
      CO(3) => udp_send_data_valid11_in,
      CO(2) => udp_send_data_valid_reg_i_5_n_1,
      CO(1) => udp_send_data_valid_reg_i_5_n_2,
      CO(0) => udp_send_data_valid_reg_i_5_n_3,
      CYINIT => '0',
      DI(3) => udp_send_data_valid_i_11_n_0,
      DI(2) => udp_send_data_valid_i_12_n_0,
      DI(1) => udp_send_data_valid_i_13_n_0,
      DI(0) => udp_send_data_valid_i_14_n_0,
      O(3 downto 0) => NLW_udp_send_data_valid_reg_i_5_O_UNCONNECTED(3 downto 0),
      S(3) => udp_send_data_valid_i_15_n_0,
      S(2) => udp_send_data_valid_i_16_n_0,
      S(1) => udp_send_data_valid_i_17_n_0,
      S(0) => udp_send_data_valid_i_18_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_ethernet_transceiver2_0_0 is
  port (
    clk100mhz : in STD_LOGIC;
    eth_rxd : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    eth_txd : inout STD_LOGIC_VECTOR ( 1 downto 0 );
    eth_crsdv : inout STD_LOGIC;
    eth_txen : inout STD_LOGIC;
    eth_rxerr : inout STD_LOGIC;
    eth_mdc : out STD_LOGIC;
    eth_mdio : inout STD_LOGIC;
    eth_refclk : out STD_LOGIC;
    eth_rstn : inout STD_LOGIC;
    led16_b : out STD_LOGIC;
    led16_g : out STD_LOGIC;
    led16_r : out STD_LOGIC;
    led17_b : out STD_LOGIC;
    led17_g : out STD_LOGIC;
    led17_r : out STD_LOGIC;
    btn_reset : in STD_LOGIC;
    led : out STD_LOGIC_VECTOR ( 15 downto 0 );
    udp_packet_checksum : in STD_LOGIC_VECTOR ( 15 downto 0 );
    udp_packet_recieved : out STD_LOGIC;
    udp_packet_sending : out STD_LOGIC;
    fifo_write_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
    fifo_write_enable : out STD_LOGIC;
    fifo_write_full : in STD_LOGIC;
    fifo_read_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
    fifo_read_enable : out STD_LOGIC;
    fifo_read_length : in STD_LOGIC_VECTOR ( 15 downto 0 );
    fifo_read_empty : in STD_LOGIC;
    ip : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of design_1_ethernet_transceiver2_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_ethernet_transceiver2_0_0 : entity is "design_1_ethernet_transceiver2_0_0,ethernet_transceiver2,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_ethernet_transceiver2_0_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of design_1_ethernet_transceiver2_0_0 : entity is "package_project";
  attribute x_core_info : string;
  attribute x_core_info of design_1_ethernet_transceiver2_0_0 : entity is "ethernet_transceiver2,Vivado 2018.3";
end design_1_ethernet_transceiver2_0_0;

architecture STRUCTURE of design_1_ethernet_transceiver2_0_0 is
  attribute ADDR_WIDTH : integer;
  attribute ADDR_WIDTH of U0 : label is 10;
  attribute DATA_WIDTH : integer;
  attribute DATA_WIDTH of U0 : label is 8;
  attribute FIFO_WIDTH : integer;
  attribute FIFO_WIDTH of U0 : label is 32;
  attribute M_clk2_5mhz1 : integer;
  attribute M_clk2_5mhz1 of U0 : label is 20;
  attribute M_clk2_5mhz2 : integer;
  attribute M_clk2_5mhz2 of U0 : label is 10;
  attribute N : integer;
  attribute N of U0 : label is 22;
  attribute x_interface_info : string;
  attribute x_interface_info of btn_reset : signal is "xilinx.com:signal:reset:1.0 btn_reset RST";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of btn_reset : signal is "XIL_INTERFACENAME btn_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute x_interface_info of eth_rstn : signal is "xilinx.com:signal:reset:1.0 eth_rstn RST";
  attribute x_interface_parameter of eth_rstn : signal is "XIL_INTERFACENAME eth_rstn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute x_interface_info of fifo_read_empty : signal is "xilinx.com:interface:fifo_read:1.0 fifo_read EMPTY";
  attribute x_interface_info of fifo_read_enable : signal is "xilinx.com:interface:fifo_read:1.0 fifo_read RD_EN";
  attribute x_interface_info of fifo_write_enable : signal is "xilinx.com:interface:fifo_write:1.0 fifo_write WR_EN";
  attribute x_interface_info of fifo_write_full : signal is "xilinx.com:interface:fifo_write:1.0 fifo_write FULL";
  attribute x_interface_info of fifo_read_data : signal is "xilinx.com:interface:fifo_read:1.0 fifo_read RD_DATA";
  attribute x_interface_info of fifo_write_data : signal is "xilinx.com:interface:fifo_write:1.0 fifo_write WR_DATA";
begin
U0: entity work.design_1_ethernet_transceiver2_0_0_ethernet_transceiver2
     port map (
      btn_reset => btn_reset,
      clk100mhz => clk100mhz,
      eth_crsdv => eth_crsdv,
      eth_mdc => eth_mdc,
      eth_mdio => eth_mdio,
      eth_refclk => eth_refclk,
      eth_rstn => eth_rstn,
      eth_rxd(1 downto 0) => eth_rxd(1 downto 0),
      eth_rxerr => eth_rxerr,
      eth_txd(1 downto 0) => eth_txd(1 downto 0),
      eth_txen => eth_txen,
      fifo_read_data(31 downto 0) => fifo_read_data(31 downto 0),
      fifo_read_empty => fifo_read_empty,
      fifo_read_enable => fifo_read_enable,
      fifo_read_length(15 downto 0) => fifo_read_length(15 downto 0),
      fifo_write_data(31 downto 0) => fifo_write_data(31 downto 0),
      fifo_write_enable => fifo_write_enable,
      fifo_write_full => fifo_write_full,
      ip(4 downto 0) => ip(4 downto 0),
      led(15 downto 0) => led(15 downto 0),
      led16_b => led16_b,
      led16_g => led16_g,
      led16_r => led16_r,
      led17_b => led17_b,
      led17_g => led17_g,
      led17_r => led17_r,
      udp_packet_checksum(15 downto 0) => udp_packet_checksum(15 downto 0),
      udp_packet_recieved => udp_packet_recieved,
      udp_packet_sending => udp_packet_sending
    );
end STRUCTURE;
