<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu May 28 23:21:23 2020" VIVADOVERSION="2018.3">

  <SYSTEMINFO ARCH="artix7" DEVICE="7a100t" NAME="design_1" PACKAGE="csg324" SPEEDGRADE="-1"/>

  <EXTERNALPORTS>
    <PORT DIR="I" NAME="reset_rtl_0" SIGIS="rst" SIGNAME="External_Ports_reset_rtl_0">
      <CONNECTIONS>
        <CONNECTION INSTANCE="negate_0" PORT="A"/>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="btn_reset"/>
        <CONNECTION INSTANCE="packaging_0" PORT="rst"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="clk_100MHz" SIGIS="clk" SIGNAME="External_Ports_clk_100MHz">
      <CONNECTIONS>
        <CONNECTION INSTANCE="fifo_input" PORT="clk"/>
        <CONNECTION INSTANCE="c_counter_binary_0" PORT="CLK"/>
        <CONNECTION INSTANCE="c_counter_binary_1" PORT="CLK"/>
        <CONNECTION INSTANCE="segment_0" PORT="clk"/>
        <CONNECTION INSTANCE="negate_0" PORT="CLK"/>
        <CONNECTION INSTANCE="fifo_output" PORT="wr_clk"/>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="clk100mhz"/>
        <CONNECTION INSTANCE="packaging_0" PORT="clk"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" LEFT="4" NAME="sw_0" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_sw_0">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="ip"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="15" NAME="led_0" RIGHT="0" SIGIS="undef" SIGNAME="xlconcat_4_dout">
      <CONNECTIONS>
        <CONNECTION INSTANCE="xlconcat_4" PORT="dout"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="led17_r_0" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_led17_r">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="led17_r"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="led17_g_0" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_led17_g">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="led17_g"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="led17_b_0" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_led17_b">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="led17_b"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="led16_r_0" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_led16_r">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="led16_r"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="led16_g_0" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_led16_g">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="led16_g"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="led16_b_0" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_led16_b">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="led16_b"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="eth_refclk_0" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_eth_refclk">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="eth_refclk"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="eth_mdio_0" SIGIS="undef" SIGNAME="External_Ports_eth_mdio_0">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="eth_mdio"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="eth_mdc_0" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_eth_mdc">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="eth_mdc"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="eth_rxerr_0" SIGIS="undef" SIGNAME="External_Ports_eth_rxerr_0">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="eth_rxerr"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="eth_txen_0" SIGIS="undef" SIGNAME="External_Ports_eth_txen_0">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="eth_txen"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="eth_crsdv_0" SIGIS="undef" SIGNAME="External_Ports_eth_crsdv_0">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="eth_crsdv"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="eth_rstn_0" SIGIS="rst" SIGNAME="External_Ports_eth_rstn_0">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="eth_rstn"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="1" NAME="eth_rxd_0" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_eth_rxd_0">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="eth_rxd"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="1" NAME="eth_txd_0" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_eth_txd_0">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="eth_txd"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="0" NAME="anodes_0" RIGHT="7" SIGIS="undef" SIGNAME="segment_0_anodes">
      <CONNECTIONS>
        <CONNECTION INSTANCE="segment_0" PORT="anodes"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="0" NAME="cathodes_0" RIGHT="7" SIGIS="undef" SIGNAME="segment_0_cathodes">
      <CONNECTIONS>
        <CONNECTION INSTANCE="segment_0" PORT="cathodes"/>
      </CONNECTIONS>
    </PORT>
  </EXTERNALPORTS>

  <EXTERNALINTERFACES/>

  <MODULES>
    <MODULE COREREVISION="12" FULLNAME="/c_counter_binary_0" HWVERSION="12.0" INSTANCE="c_counter_binary_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="c_counter_binary" VLNV="xilinx.com:ip:c_counter_binary:12.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=c_counter_binary;v=v12_0;d=pg121-c-counter-binary.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_IMPLEMENTATION" VALUE="0"/>
        <PARAMETER NAME="C_VERBOSITY" VALUE="0"/>
        <PARAMETER NAME="C_XDEVICEFAMILY" VALUE="artix7"/>
        <PARAMETER NAME="C_WIDTH" VALUE="16"/>
        <PARAMETER NAME="C_HAS_CE" VALUE="1"/>
        <PARAMETER NAME="C_HAS_SCLR" VALUE="1"/>
        <PARAMETER NAME="C_RESTRICT_COUNT" VALUE="1"/>
        <PARAMETER NAME="C_COUNT_TO" VALUE="10011100001111"/>
        <PARAMETER NAME="C_COUNT_BY" VALUE="1"/>
        <PARAMETER NAME="C_COUNT_MODE" VALUE="0"/>
        <PARAMETER NAME="C_THRESH0_VALUE" VALUE="1"/>
        <PARAMETER NAME="C_CE_OVERRIDES_SYNC" VALUE="0"/>
        <PARAMETER NAME="C_HAS_THRESH0" VALUE="0"/>
        <PARAMETER NAME="C_HAS_LOAD" VALUE="0"/>
        <PARAMETER NAME="C_LOAD_LOW" VALUE="0"/>
        <PARAMETER NAME="C_LATENCY" VALUE="1"/>
        <PARAMETER NAME="C_FB_LATENCY" VALUE="2"/>
        <PARAMETER NAME="C_AINIT_VAL" VALUE="0"/>
        <PARAMETER NAME="C_SINIT_VAL" VALUE="0"/>
        <PARAMETER NAME="C_SCLR_OVERRIDES_SSET" VALUE="1"/>
        <PARAMETER NAME="C_HAS_SSET" VALUE="0"/>
        <PARAMETER NAME="C_HAS_SINIT" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_c_counter_binary_0_0"/>
        <PARAMETER NAME="Implementation" VALUE="Fabric"/>
        <PARAMETER NAME="Output_Width" VALUE="16"/>
        <PARAMETER NAME="Increment_Value" VALUE="1"/>
        <PARAMETER NAME="Restrict_Count" VALUE="true"/>
        <PARAMETER NAME="Final_Count_Value" VALUE="270F"/>
        <PARAMETER NAME="Count_Mode" VALUE="UP"/>
        <PARAMETER NAME="Sync_Threshold_Output" VALUE="false"/>
        <PARAMETER NAME="Threshold_Value" VALUE="1"/>
        <PARAMETER NAME="CE" VALUE="true"/>
        <PARAMETER NAME="SCLR" VALUE="true"/>
        <PARAMETER NAME="SSET" VALUE="false"/>
        <PARAMETER NAME="SINIT" VALUE="false"/>
        <PARAMETER NAME="SINIT_Value" VALUE="0"/>
        <PARAMETER NAME="SyncCtrlPriority" VALUE="Reset_Overrides_Set"/>
        <PARAMETER NAME="Sync_CE_Priority" VALUE="Sync_Overrides_CE"/>
        <PARAMETER NAME="AINIT_Value" VALUE="0"/>
        <PARAMETER NAME="Load" VALUE="false"/>
        <PARAMETER NAME="Latency_Configuration" VALUE="Automatic"/>
        <PARAMETER NAME="Latency" VALUE="1"/>
        <PARAMETER NAME="Fb_Latency_Configuration" VALUE="Automatic"/>
        <PARAMETER NAME="Fb_Latency" VALUE="2"/>
        <PARAMETER NAME="Load_Sense" VALUE="Active_High"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="CLK" SIGIS="clk" SIGNAME="External_Ports_clk_100MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="clk_100MHz"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="CE" SIGIS="ce" SIGNAME="fifo_output_overflow">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_output" PORT="overflow"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="SCLR" SIGIS="rst" SIGNAME="negate_0_S">
          <CONNECTIONS>
            <CONNECTION INSTANCE="negate_0" PORT="S"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="Q" RIGHT="0" SIGIS="data" SIGNAME="c_counter_binary_0_Q">
          <CONNECTIONS>
            <CONNECTION INSTANCE="segment_0" PORT="num2"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="12" FULLNAME="/c_counter_binary_1" HWVERSION="12.0" INSTANCE="c_counter_binary_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="c_counter_binary" VLNV="xilinx.com:ip:c_counter_binary:12.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=c_counter_binary;v=v12_0;d=pg121-c-counter-binary.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_IMPLEMENTATION" VALUE="0"/>
        <PARAMETER NAME="C_VERBOSITY" VALUE="0"/>
        <PARAMETER NAME="C_XDEVICEFAMILY" VALUE="artix7"/>
        <PARAMETER NAME="C_WIDTH" VALUE="16"/>
        <PARAMETER NAME="C_HAS_CE" VALUE="1"/>
        <PARAMETER NAME="C_HAS_SCLR" VALUE="1"/>
        <PARAMETER NAME="C_RESTRICT_COUNT" VALUE="1"/>
        <PARAMETER NAME="C_COUNT_TO" VALUE="10011100001111"/>
        <PARAMETER NAME="C_COUNT_BY" VALUE="1"/>
        <PARAMETER NAME="C_COUNT_MODE" VALUE="0"/>
        <PARAMETER NAME="C_THRESH0_VALUE" VALUE="1"/>
        <PARAMETER NAME="C_CE_OVERRIDES_SYNC" VALUE="0"/>
        <PARAMETER NAME="C_HAS_THRESH0" VALUE="0"/>
        <PARAMETER NAME="C_HAS_LOAD" VALUE="0"/>
        <PARAMETER NAME="C_LOAD_LOW" VALUE="0"/>
        <PARAMETER NAME="C_LATENCY" VALUE="1"/>
        <PARAMETER NAME="C_FB_LATENCY" VALUE="2"/>
        <PARAMETER NAME="C_AINIT_VAL" VALUE="0"/>
        <PARAMETER NAME="C_SINIT_VAL" VALUE="0"/>
        <PARAMETER NAME="C_SCLR_OVERRIDES_SSET" VALUE="1"/>
        <PARAMETER NAME="C_HAS_SSET" VALUE="0"/>
        <PARAMETER NAME="C_HAS_SINIT" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_c_counter_binary_0_1"/>
        <PARAMETER NAME="Implementation" VALUE="Fabric"/>
        <PARAMETER NAME="Output_Width" VALUE="16"/>
        <PARAMETER NAME="Increment_Value" VALUE="1"/>
        <PARAMETER NAME="Restrict_Count" VALUE="true"/>
        <PARAMETER NAME="Final_Count_Value" VALUE="270F"/>
        <PARAMETER NAME="Count_Mode" VALUE="UP"/>
        <PARAMETER NAME="Sync_Threshold_Output" VALUE="false"/>
        <PARAMETER NAME="Threshold_Value" VALUE="1"/>
        <PARAMETER NAME="CE" VALUE="true"/>
        <PARAMETER NAME="SCLR" VALUE="true"/>
        <PARAMETER NAME="SSET" VALUE="false"/>
        <PARAMETER NAME="SINIT" VALUE="false"/>
        <PARAMETER NAME="SINIT_Value" VALUE="0"/>
        <PARAMETER NAME="SyncCtrlPriority" VALUE="Reset_Overrides_Set"/>
        <PARAMETER NAME="Sync_CE_Priority" VALUE="Sync_Overrides_CE"/>
        <PARAMETER NAME="AINIT_Value" VALUE="0"/>
        <PARAMETER NAME="Load" VALUE="false"/>
        <PARAMETER NAME="Latency_Configuration" VALUE="Automatic"/>
        <PARAMETER NAME="Latency" VALUE="1"/>
        <PARAMETER NAME="Fb_Latency_Configuration" VALUE="Automatic"/>
        <PARAMETER NAME="Fb_Latency" VALUE="2"/>
        <PARAMETER NAME="Load_Sense" VALUE="Active_High"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="CLK" SIGIS="clk" SIGNAME="External_Ports_clk_100MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="clk_100MHz"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="CE" SIGIS="ce" SIGNAME="fifo_input_overflow">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_input" PORT="overflow"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="SCLR" SIGIS="rst" SIGNAME="negate_0_S">
          <CONNECTIONS>
            <CONNECTION INSTANCE="negate_0" PORT="S"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="Q" RIGHT="0" SIGIS="data" SIGNAME="c_counter_binary_1_Q">
          <CONNECTIONS>
            <CONNECTION INSTANCE="segment_0" PORT="num1"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="44" FULLNAME="/ethernet_transceiver2_0" HWVERSION="1.0" INSTANCE="ethernet_transceiver2_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="ethernet_transceiver2" VLNV="xilinx.com:user:ethernet_transceiver2:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="M_clk2_5mhz1" VALUE="20"/>
        <PARAMETER NAME="M_clk2_5mhz2" VALUE="10"/>
        <PARAMETER NAME="N" VALUE="22"/>
        <PARAMETER NAME="ADDR_WIDTH" VALUE="10"/>
        <PARAMETER NAME="DATA_WIDTH" VALUE="8"/>
        <PARAMETER NAME="FIFO_WIDTH" VALUE="32"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_ethernet_transceiver2_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="clk100mhz" SIGIS="undef" SIGNAME="External_Ports_clk_100MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="clk_100MHz"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" LEFT="1" NAME="eth_rxd" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_eth_rxd_0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="eth_rxd_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" LEFT="1" NAME="eth_txd" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_eth_txd_0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="eth_txd_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="eth_crsdv" SIGIS="undef" SIGNAME="External_Ports_eth_crsdv_0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="eth_crsdv_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="eth_txen" SIGIS="undef" SIGNAME="External_Ports_eth_txen_0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="eth_txen_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="eth_rxerr" SIGIS="undef" SIGNAME="External_Ports_eth_rxerr_0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="eth_rxerr_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="eth_mdc" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_eth_mdc">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="eth_mdc_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="eth_mdio" SIGIS="undef" SIGNAME="External_Ports_eth_mdio_0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="eth_mdio_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="eth_refclk" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_eth_refclk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="eth_refclk_0"/>
            <CONNECTION INSTANCE="fifo_output" PORT="rd_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="eth_rstn" SIGIS="rst" SIGNAME="External_Ports_eth_rstn_0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="eth_rstn_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="led16_b" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_led16_b">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="led16_b_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="led16_g" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_led16_g">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="led16_g_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="led16_r" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_led16_r">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="led16_r_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="led17_b" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_led17_b">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="led17_b_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="led17_g" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_led17_g">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="led17_g_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="led17_r" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_led17_r">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="led17_r_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="btn_reset" SIGIS="rst" SIGNAME="External_Ports_reset_rtl_0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="reset_rtl_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="led" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="15" NAME="udp_packet_checksum" RIGHT="0" SIGIS="undef" SIGNAME="xlconstant_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconstant_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="udp_packet_recieved" SIGIS="undef"/>
        <PORT DIR="O" NAME="udp_packet_sending" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="fifo_write_data" RIGHT="0" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_fifo_write_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_input" PORT="din"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="fifo_write_enable" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_fifo_write_enable">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_input" PORT="wr_en"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="fifo_write_full" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_fifo_write_full">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_input" PORT="full"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="fifo_read_data" RIGHT="0" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_fifo_read_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_output" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="fifo_read_enable" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_fifo_read_enable">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_output" PORT="rd_en"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="fifo_read_length" RIGHT="0" SIGIS="undef" SIGNAME="xlconcat_5_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconcat_5" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="fifo_read_empty" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_fifo_read_empty">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_output" PORT="empty"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="4" NAME="ip" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_sw_0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="sw_0"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="ethernet_transceiver2_0_fifo_read" NAME="fifo_read" TYPE="INITIATOR" VLNV="xilinx.com:interface:fifo_read:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="RD_DATA" PHYSICAL="fifo_read_data"/>
            <PORTMAP LOGICAL="RD_EN" PHYSICAL="fifo_read_enable"/>
            <PORTMAP LOGICAL="EMPTY" PHYSICAL="fifo_read_empty"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ethernet_transceiver2_0_fifo_write" NAME="fifo_write" TYPE="INITIATOR" VLNV="xilinx.com:interface:fifo_write:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="WR_DATA" PHYSICAL="fifo_write_data"/>
            <PORTMAP LOGICAL="WR_EN" PHYSICAL="fifo_write_enable"/>
            <PORTMAP LOGICAL="FULL" PHYSICAL="fifo_write_full"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="3" FULLNAME="/fifo_input" HWVERSION="13.2" INSTANCE="fifo_input" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="fifo_generator" VLNV="xilinx.com:ip:fifo_generator:13.2">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=fifo_generator;v=v13_2;d=pg057-fifo-generator.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_COMMON_CLOCK" VALUE="1"/>
        <PARAMETER NAME="C_SELECT_XPM" VALUE="0"/>
        <PARAMETER NAME="C_COUNT_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_DATA_COUNT_WIDTH" VALUE="6"/>
        <PARAMETER NAME="C_DEFAULT_VALUE" VALUE="BlankString"/>
        <PARAMETER NAME="C_DIN_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_DOUT_RST_VAL" VALUE="0"/>
        <PARAMETER NAME="C_DOUT_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_ENABLE_RLOCS" VALUE="0"/>
        <PARAMETER NAME="C_FAMILY" VALUE="artix7"/>
        <PARAMETER NAME="C_FULL_FLAGS_RST_VAL" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ALMOST_EMPTY" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ALMOST_FULL" VALUE="0"/>
        <PARAMETER NAME="C_HAS_BACKUP" VALUE="0"/>
        <PARAMETER NAME="C_HAS_DATA_COUNT" VALUE="0"/>
        <PARAMETER NAME="C_HAS_INT_CLK" VALUE="0"/>
        <PARAMETER NAME="C_HAS_MEMINIT_FILE" VALUE="0"/>
        <PARAMETER NAME="C_HAS_OVERFLOW" VALUE="1"/>
        <PARAMETER NAME="C_HAS_RD_DATA_COUNT" VALUE="0"/>
        <PARAMETER NAME="C_HAS_RD_RST" VALUE="0"/>
        <PARAMETER NAME="C_HAS_RST" VALUE="0"/>
        <PARAMETER NAME="C_HAS_SRST" VALUE="1"/>
        <PARAMETER NAME="C_HAS_UNDERFLOW" VALUE="0"/>
        <PARAMETER NAME="C_HAS_VALID" VALUE="0"/>
        <PARAMETER NAME="C_HAS_WR_ACK" VALUE="0"/>
        <PARAMETER NAME="C_HAS_WR_DATA_COUNT" VALUE="0"/>
        <PARAMETER NAME="C_HAS_WR_RST" VALUE="0"/>
        <PARAMETER NAME="C_IMPLEMENTATION_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_INIT_WR_PNTR_VAL" VALUE="0"/>
        <PARAMETER NAME="C_MEMORY_TYPE" VALUE="2"/>
        <PARAMETER NAME="C_MIF_FILE_NAME" VALUE="BlankString"/>
        <PARAMETER NAME="C_OPTIMIZATION_MODE" VALUE="0"/>
        <PARAMETER NAME="C_OVERFLOW_LOW" VALUE="0"/>
        <PARAMETER NAME="C_PRELOAD_LATENCY" VALUE="1"/>
        <PARAMETER NAME="C_PRELOAD_REGS" VALUE="0"/>
        <PARAMETER NAME="C_PRIM_FIFO_TYPE" VALUE="512x36"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_ASSERT_VAL" VALUE="2"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_NEGATE_VAL" VALUE="3"/>
        <PARAMETER NAME="C_PROG_EMPTY_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_ASSERT_VAL" VALUE="62"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_NEGATE_VAL" VALUE="61"/>
        <PARAMETER NAME="C_PROG_FULL_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_RD_DATA_COUNT_WIDTH" VALUE="6"/>
        <PARAMETER NAME="C_RD_DEPTH" VALUE="64"/>
        <PARAMETER NAME="C_RD_FREQ" VALUE="1"/>
        <PARAMETER NAME="C_RD_PNTR_WIDTH" VALUE="6"/>
        <PARAMETER NAME="C_UNDERFLOW_LOW" VALUE="0"/>
        <PARAMETER NAME="C_USE_DOUT_RST" VALUE="1"/>
        <PARAMETER NAME="C_USE_ECC" VALUE="0"/>
        <PARAMETER NAME="C_USE_EMBEDDED_REG" VALUE="0"/>
        <PARAMETER NAME="C_USE_PIPELINE_REG" VALUE="0"/>
        <PARAMETER NAME="C_POWER_SAVING_MODE" VALUE="0"/>
        <PARAMETER NAME="C_USE_FIFO16_FLAGS" VALUE="0"/>
        <PARAMETER NAME="C_USE_FWFT_DATA_COUNT" VALUE="0"/>
        <PARAMETER NAME="C_VALID_LOW" VALUE="0"/>
        <PARAMETER NAME="C_WR_ACK_LOW" VALUE="0"/>
        <PARAMETER NAME="C_WR_DATA_COUNT_WIDTH" VALUE="6"/>
        <PARAMETER NAME="C_WR_DEPTH" VALUE="64"/>
        <PARAMETER NAME="C_WR_FREQ" VALUE="1"/>
        <PARAMETER NAME="C_WR_PNTR_WIDTH" VALUE="6"/>
        <PARAMETER NAME="C_WR_RESPONSE_LATENCY" VALUE="1"/>
        <PARAMETER NAME="C_MSGON_VAL" VALUE="1"/>
        <PARAMETER NAME="C_ENABLE_RST_SYNC" VALUE="1"/>
        <PARAMETER NAME="C_EN_SAFETY_CKT" VALUE="0"/>
        <PARAMETER NAME="C_ERROR_INJECTION_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_SYNCHRONIZER_STAGE" VALUE="2"/>
        <PARAMETER NAME="C_INTERFACE_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_AXI_TYPE" VALUE="1"/>
        <PARAMETER NAME="C_HAS_AXI_WR_CHANNEL" VALUE="1"/>
        <PARAMETER NAME="C_HAS_AXI_RD_CHANNEL" VALUE="1"/>
        <PARAMETER NAME="C_HAS_SLAVE_CE" VALUE="0"/>
        <PARAMETER NAME="C_HAS_MASTER_CE" VALUE="0"/>
        <PARAMETER NAME="C_ADD_NGC_CONSTRAINT" VALUE="0"/>
        <PARAMETER NAME="C_USE_COMMON_OVERFLOW" VALUE="0"/>
        <PARAMETER NAME="C_USE_COMMON_UNDERFLOW" VALUE="0"/>
        <PARAMETER NAME="C_USE_DEFAULT_SETTINGS" VALUE="0"/>
        <PARAMETER NAME="C_AXI_ID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXI_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_AXI_DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C_AXI_LEN_WIDTH" VALUE="8"/>
        <PARAMETER NAME="C_AXI_LOCK_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_HAS_AXI_ID" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXI_AWUSER" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXI_WUSER" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXI_BUSER" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXI_ARUSER" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXI_RUSER" VALUE="0"/>
        <PARAMETER NAME="C_AXI_ARUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXI_AWUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXI_WUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXI_BUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXI_RUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_HAS_AXIS_TDATA" VALUE="1"/>
        <PARAMETER NAME="C_HAS_AXIS_TID" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXIS_TDEST" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXIS_TUSER" VALUE="1"/>
        <PARAMETER NAME="C_HAS_AXIS_TREADY" VALUE="1"/>
        <PARAMETER NAME="C_HAS_AXIS_TLAST" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXIS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXIS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="8"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TUSER_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_AXIS_TSTRB_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TKEEP_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_WACH_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_WDCH_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_WRCH_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_RACH_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_RDCH_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_AXIS_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_IMPLEMENTATION_TYPE_WACH" VALUE="2"/>
        <PARAMETER NAME="C_IMPLEMENTATION_TYPE_WDCH" VALUE="1"/>
        <PARAMETER NAME="C_IMPLEMENTATION_TYPE_WRCH" VALUE="2"/>
        <PARAMETER NAME="C_IMPLEMENTATION_TYPE_RACH" VALUE="2"/>
        <PARAMETER NAME="C_IMPLEMENTATION_TYPE_RDCH" VALUE="1"/>
        <PARAMETER NAME="C_IMPLEMENTATION_TYPE_AXIS" VALUE="1"/>
        <PARAMETER NAME="C_APPLICATION_TYPE_WACH" VALUE="0"/>
        <PARAMETER NAME="C_APPLICATION_TYPE_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_APPLICATION_TYPE_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_APPLICATION_TYPE_RACH" VALUE="0"/>
        <PARAMETER NAME="C_APPLICATION_TYPE_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_APPLICATION_TYPE_AXIS" VALUE="0"/>
        <PARAMETER NAME="C_PRIM_FIFO_TYPE_WACH" VALUE="512x36"/>
        <PARAMETER NAME="C_PRIM_FIFO_TYPE_WDCH" VALUE="1kx36"/>
        <PARAMETER NAME="C_PRIM_FIFO_TYPE_WRCH" VALUE="512x36"/>
        <PARAMETER NAME="C_PRIM_FIFO_TYPE_RACH" VALUE="512x36"/>
        <PARAMETER NAME="C_PRIM_FIFO_TYPE_RDCH" VALUE="1kx36"/>
        <PARAMETER NAME="C_PRIM_FIFO_TYPE_AXIS" VALUE="1kx18"/>
        <PARAMETER NAME="C_USE_ECC_WACH" VALUE="0"/>
        <PARAMETER NAME="C_USE_ECC_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_USE_ECC_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_USE_ECC_RACH" VALUE="0"/>
        <PARAMETER NAME="C_USE_ECC_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_USE_ECC_AXIS" VALUE="0"/>
        <PARAMETER NAME="C_ERROR_INJECTION_TYPE_WACH" VALUE="0"/>
        <PARAMETER NAME="C_ERROR_INJECTION_TYPE_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_ERROR_INJECTION_TYPE_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_ERROR_INJECTION_TYPE_RACH" VALUE="0"/>
        <PARAMETER NAME="C_ERROR_INJECTION_TYPE_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_ERROR_INJECTION_TYPE_AXIS" VALUE="0"/>
        <PARAMETER NAME="C_DIN_WIDTH_WACH" VALUE="1"/>
        <PARAMETER NAME="C_DIN_WIDTH_WDCH" VALUE="64"/>
        <PARAMETER NAME="C_DIN_WIDTH_WRCH" VALUE="2"/>
        <PARAMETER NAME="C_DIN_WIDTH_RACH" VALUE="32"/>
        <PARAMETER NAME="C_DIN_WIDTH_RDCH" VALUE="64"/>
        <PARAMETER NAME="C_DIN_WIDTH_AXIS" VALUE="1"/>
        <PARAMETER NAME="C_WR_DEPTH_WACH" VALUE="16"/>
        <PARAMETER NAME="C_WR_DEPTH_WDCH" VALUE="1024"/>
        <PARAMETER NAME="C_WR_DEPTH_WRCH" VALUE="16"/>
        <PARAMETER NAME="C_WR_DEPTH_RACH" VALUE="16"/>
        <PARAMETER NAME="C_WR_DEPTH_RDCH" VALUE="1024"/>
        <PARAMETER NAME="C_WR_DEPTH_AXIS" VALUE="1024"/>
        <PARAMETER NAME="C_WR_PNTR_WIDTH_WACH" VALUE="4"/>
        <PARAMETER NAME="C_WR_PNTR_WIDTH_WDCH" VALUE="10"/>
        <PARAMETER NAME="C_WR_PNTR_WIDTH_WRCH" VALUE="4"/>
        <PARAMETER NAME="C_WR_PNTR_WIDTH_RACH" VALUE="4"/>
        <PARAMETER NAME="C_WR_PNTR_WIDTH_RDCH" VALUE="10"/>
        <PARAMETER NAME="C_WR_PNTR_WIDTH_AXIS" VALUE="10"/>
        <PARAMETER NAME="C_HAS_DATA_COUNTS_WACH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_DATA_COUNTS_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_DATA_COUNTS_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_DATA_COUNTS_RACH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_DATA_COUNTS_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_DATA_COUNTS_AXIS" VALUE="0"/>
        <PARAMETER NAME="C_HAS_PROG_FLAGS_WACH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_PROG_FLAGS_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_PROG_FLAGS_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_PROG_FLAGS_RACH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_PROG_FLAGS_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_PROG_FLAGS_AXIS" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_TYPE_WACH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_TYPE_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_TYPE_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_TYPE_RACH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_TYPE_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_TYPE_AXIS" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_ASSERT_VAL_WACH" VALUE="1023"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_ASSERT_VAL_WDCH" VALUE="1023"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_ASSERT_VAL_WRCH" VALUE="1023"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_ASSERT_VAL_RACH" VALUE="1023"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_ASSERT_VAL_RDCH" VALUE="1023"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_ASSERT_VAL_AXIS" VALUE="1023"/>
        <PARAMETER NAME="C_PROG_EMPTY_TYPE_WACH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_EMPTY_TYPE_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_EMPTY_TYPE_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_EMPTY_TYPE_RACH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_EMPTY_TYPE_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_EMPTY_TYPE_AXIS" VALUE="0"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH" VALUE="1022"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH" VALUE="1022"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH" VALUE="1022"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH" VALUE="1022"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH" VALUE="1022"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS" VALUE="1022"/>
        <PARAMETER NAME="C_REG_SLICE_MODE_WACH" VALUE="0"/>
        <PARAMETER NAME="C_REG_SLICE_MODE_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_REG_SLICE_MODE_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_REG_SLICE_MODE_RACH" VALUE="0"/>
        <PARAMETER NAME="C_REG_SLICE_MODE_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_REG_SLICE_MODE_AXIS" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_fifo_generator_0_1"/>
        <PARAMETER NAME="Fifo_Implementation" VALUE="Common_Clock_Distributed_RAM"/>
        <PARAMETER NAME="synchronization_stages" VALUE="2"/>
        <PARAMETER NAME="synchronization_stages_axi" VALUE="2"/>
        <PARAMETER NAME="INTERFACE_TYPE" VALUE="Native"/>
        <PARAMETER NAME="Performance_Options" VALUE="Standard_FIFO"/>
        <PARAMETER NAME="asymmetric_port_width" VALUE="false"/>
        <PARAMETER NAME="Input_Data_Width" VALUE="32"/>
        <PARAMETER NAME="Input_Depth" VALUE="64"/>
        <PARAMETER NAME="Output_Data_Width" VALUE="32"/>
        <PARAMETER NAME="Output_Depth" VALUE="64"/>
        <PARAMETER NAME="Enable_ECC" VALUE="false"/>
        <PARAMETER NAME="Use_Embedded_Registers" VALUE="false"/>
        <PARAMETER NAME="Reset_Pin" VALUE="true"/>
        <PARAMETER NAME="Enable_Reset_Synchronization" VALUE="true"/>
        <PARAMETER NAME="Reset_Type" VALUE="Synchronous_Reset"/>
        <PARAMETER NAME="Full_Flags_Reset_Value" VALUE="0"/>
        <PARAMETER NAME="Use_Dout_Reset" VALUE="true"/>
        <PARAMETER NAME="Dout_Reset_Value" VALUE="0"/>
        <PARAMETER NAME="dynamic_power_saving" VALUE="false"/>
        <PARAMETER NAME="Almost_Full_Flag" VALUE="false"/>
        <PARAMETER NAME="Almost_Empty_Flag" VALUE="false"/>
        <PARAMETER NAME="Valid_Flag" VALUE="false"/>
        <PARAMETER NAME="Valid_Sense" VALUE="Active_High"/>
        <PARAMETER NAME="Underflow_Flag" VALUE="false"/>
        <PARAMETER NAME="Underflow_Sense" VALUE="Active_High"/>
        <PARAMETER NAME="Write_Acknowledge_Flag" VALUE="false"/>
        <PARAMETER NAME="Write_Acknowledge_Sense" VALUE="Active_High"/>
        <PARAMETER NAME="Overflow_Flag" VALUE="true"/>
        <PARAMETER NAME="Overflow_Sense" VALUE="Active_High"/>
        <PARAMETER NAME="Inject_Sbit_Error" VALUE="false"/>
        <PARAMETER NAME="Inject_Dbit_Error" VALUE="false"/>
        <PARAMETER NAME="ecc_pipeline_reg" VALUE="false"/>
        <PARAMETER NAME="Use_Extra_Logic" VALUE="false"/>
        <PARAMETER NAME="Data_Count" VALUE="false"/>
        <PARAMETER NAME="Data_Count_Width" VALUE="6"/>
        <PARAMETER NAME="Write_Data_Count" VALUE="false"/>
        <PARAMETER NAME="Write_Data_Count_Width" VALUE="6"/>
        <PARAMETER NAME="Read_Data_Count" VALUE="false"/>
        <PARAMETER NAME="Read_Data_Count_Width" VALUE="6"/>
        <PARAMETER NAME="Disable_Timing_Violations" VALUE="false"/>
        <PARAMETER NAME="Read_Clock_Frequency" VALUE="1"/>
        <PARAMETER NAME="Write_Clock_Frequency" VALUE="1"/>
        <PARAMETER NAME="Programmable_Full_Type" VALUE="No_Programmable_Full_Threshold"/>
        <PARAMETER NAME="Full_Threshold_Assert_Value" VALUE="62"/>
        <PARAMETER NAME="Full_Threshold_Negate_Value" VALUE="61"/>
        <PARAMETER NAME="Programmable_Empty_Type" VALUE="No_Programmable_Empty_Threshold"/>
        <PARAMETER NAME="Empty_Threshold_Assert_Value" VALUE="2"/>
        <PARAMETER NAME="Empty_Threshold_Negate_Value" VALUE="3"/>
        <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
        <PARAMETER NAME="Clock_Type_AXI" VALUE="Common_Clock"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="false"/>
        <PARAMETER NAME="Clock_Enable_Type" VALUE="Slave_Interface_Clock_Enable"/>
        <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
        <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="ADDRESS_WIDTH" VALUE="32"/>
        <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="AWUSER_Width" VALUE="0"/>
        <PARAMETER NAME="WUSER_Width" VALUE="0"/>
        <PARAMETER NAME="BUSER_Width" VALUE="0"/>
        <PARAMETER NAME="ARUSER_Width" VALUE="0"/>
        <PARAMETER NAME="RUSER_Width" VALUE="0"/>
        <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="1"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TUSER_WIDTH" VALUE="4"/>
        <PARAMETER NAME="Enable_TREADY" VALUE="true"/>
        <PARAMETER NAME="Enable_TLAST" VALUE="false"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="false"/>
        <PARAMETER NAME="TSTRB_WIDTH" VALUE="1"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="false"/>
        <PARAMETER NAME="TKEEP_WIDTH" VALUE="1"/>
        <PARAMETER NAME="wach_type" VALUE="FIFO"/>
        <PARAMETER NAME="FIFO_Implementation_wach" VALUE="Common_Clock_Distributed_RAM"/>
        <PARAMETER NAME="FIFO_Application_Type_wach" VALUE="Data_FIFO"/>
        <PARAMETER NAME="Enable_ECC_wach" VALUE="false"/>
        <PARAMETER NAME="Inject_Sbit_Error_wach" VALUE="false"/>
        <PARAMETER NAME="Inject_Dbit_Error_wach" VALUE="false"/>
        <PARAMETER NAME="Input_Depth_wach" VALUE="16"/>
        <PARAMETER NAME="Enable_Data_Counts_wach" VALUE="false"/>
        <PARAMETER NAME="Programmable_Full_Type_wach" VALUE="No_Programmable_Full_Threshold"/>
        <PARAMETER NAME="Full_Threshold_Assert_Value_wach" VALUE="1023"/>
        <PARAMETER NAME="Programmable_Empty_Type_wach" VALUE="No_Programmable_Empty_Threshold"/>
        <PARAMETER NAME="Empty_Threshold_Assert_Value_wach" VALUE="1022"/>
        <PARAMETER NAME="wdch_type" VALUE="FIFO"/>
        <PARAMETER NAME="FIFO_Implementation_wdch" VALUE="Common_Clock_Block_RAM"/>
        <PARAMETER NAME="FIFO_Application_Type_wdch" VALUE="Data_FIFO"/>
        <PARAMETER NAME="Enable_ECC_wdch" VALUE="false"/>
        <PARAMETER NAME="Inject_Sbit_Error_wdch" VALUE="false"/>
        <PARAMETER NAME="Inject_Dbit_Error_wdch" VALUE="false"/>
        <PARAMETER NAME="Input_Depth_wdch" VALUE="1024"/>
        <PARAMETER NAME="Enable_Data_Counts_wdch" VALUE="false"/>
        <PARAMETER NAME="Programmable_Full_Type_wdch" VALUE="No_Programmable_Full_Threshold"/>
        <PARAMETER NAME="Full_Threshold_Assert_Value_wdch" VALUE="1023"/>
        <PARAMETER NAME="Programmable_Empty_Type_wdch" VALUE="No_Programmable_Empty_Threshold"/>
        <PARAMETER NAME="Empty_Threshold_Assert_Value_wdch" VALUE="1022"/>
        <PARAMETER NAME="wrch_type" VALUE="FIFO"/>
        <PARAMETER NAME="FIFO_Implementation_wrch" VALUE="Common_Clock_Distributed_RAM"/>
        <PARAMETER NAME="FIFO_Application_Type_wrch" VALUE="Data_FIFO"/>
        <PARAMETER NAME="Enable_ECC_wrch" VALUE="false"/>
        <PARAMETER NAME="Inject_Sbit_Error_wrch" VALUE="false"/>
        <PARAMETER NAME="Inject_Dbit_Error_wrch" VALUE="false"/>
        <PARAMETER NAME="Input_Depth_wrch" VALUE="16"/>
        <PARAMETER NAME="Enable_Data_Counts_wrch" VALUE="false"/>
        <PARAMETER NAME="Programmable_Full_Type_wrch" VALUE="No_Programmable_Full_Threshold"/>
        <PARAMETER NAME="Full_Threshold_Assert_Value_wrch" VALUE="1023"/>
        <PARAMETER NAME="Programmable_Empty_Type_wrch" VALUE="No_Programmable_Empty_Threshold"/>
        <PARAMETER NAME="Empty_Threshold_Assert_Value_wrch" VALUE="1022"/>
        <PARAMETER NAME="rach_type" VALUE="FIFO"/>
        <PARAMETER NAME="FIFO_Implementation_rach" VALUE="Common_Clock_Distributed_RAM"/>
        <PARAMETER NAME="FIFO_Application_Type_rach" VALUE="Data_FIFO"/>
        <PARAMETER NAME="Enable_ECC_rach" VALUE="false"/>
        <PARAMETER NAME="Inject_Sbit_Error_rach" VALUE="false"/>
        <PARAMETER NAME="Inject_Dbit_Error_rach" VALUE="false"/>
        <PARAMETER NAME="Input_Depth_rach" VALUE="16"/>
        <PARAMETER NAME="Enable_Data_Counts_rach" VALUE="false"/>
        <PARAMETER NAME="Programmable_Full_Type_rach" VALUE="No_Programmable_Full_Threshold"/>
        <PARAMETER NAME="Full_Threshold_Assert_Value_rach" VALUE="1023"/>
        <PARAMETER NAME="Programmable_Empty_Type_rach" VALUE="No_Programmable_Empty_Threshold"/>
        <PARAMETER NAME="Empty_Threshold_Assert_Value_rach" VALUE="1022"/>
        <PARAMETER NAME="rdch_type" VALUE="FIFO"/>
        <PARAMETER NAME="FIFO_Implementation_rdch" VALUE="Common_Clock_Block_RAM"/>
        <PARAMETER NAME="FIFO_Application_Type_rdch" VALUE="Data_FIFO"/>
        <PARAMETER NAME="Enable_ECC_rdch" VALUE="false"/>
        <PARAMETER NAME="Inject_Sbit_Error_rdch" VALUE="false"/>
        <PARAMETER NAME="Inject_Dbit_Error_rdch" VALUE="false"/>
        <PARAMETER NAME="Input_Depth_rdch" VALUE="1024"/>
        <PARAMETER NAME="Enable_Data_Counts_rdch" VALUE="false"/>
        <PARAMETER NAME="Programmable_Full_Type_rdch" VALUE="No_Programmable_Full_Threshold"/>
        <PARAMETER NAME="Full_Threshold_Assert_Value_rdch" VALUE="1023"/>
        <PARAMETER NAME="Programmable_Empty_Type_rdch" VALUE="No_Programmable_Empty_Threshold"/>
        <PARAMETER NAME="Empty_Threshold_Assert_Value_rdch" VALUE="1022"/>
        <PARAMETER NAME="axis_type" VALUE="FIFO"/>
        <PARAMETER NAME="FIFO_Implementation_axis" VALUE="Common_Clock_Block_RAM"/>
        <PARAMETER NAME="FIFO_Application_Type_axis" VALUE="Data_FIFO"/>
        <PARAMETER NAME="Enable_ECC_axis" VALUE="false"/>
        <PARAMETER NAME="Inject_Sbit_Error_axis" VALUE="false"/>
        <PARAMETER NAME="Inject_Dbit_Error_axis" VALUE="false"/>
        <PARAMETER NAME="Input_Depth_axis" VALUE="1024"/>
        <PARAMETER NAME="Enable_Data_Counts_axis" VALUE="false"/>
        <PARAMETER NAME="Programmable_Full_Type_axis" VALUE="No_Programmable_Full_Threshold"/>
        <PARAMETER NAME="Full_Threshold_Assert_Value_axis" VALUE="1023"/>
        <PARAMETER NAME="Programmable_Empty_Type_axis" VALUE="No_Programmable_Empty_Threshold"/>
        <PARAMETER NAME="Empty_Threshold_Assert_Value_axis" VALUE="1022"/>
        <PARAMETER NAME="Register_Slice_Mode_wach" VALUE="Fully_Registered"/>
        <PARAMETER NAME="Register_Slice_Mode_wdch" VALUE="Fully_Registered"/>
        <PARAMETER NAME="Register_Slice_Mode_wrch" VALUE="Fully_Registered"/>
        <PARAMETER NAME="Register_Slice_Mode_rach" VALUE="Fully_Registered"/>
        <PARAMETER NAME="Register_Slice_Mode_rdch" VALUE="Fully_Registered"/>
        <PARAMETER NAME="Register_Slice_Mode_axis" VALUE="Fully_Registered"/>
        <PARAMETER NAME="Underflow_Flag_AXI" VALUE="false"/>
        <PARAMETER NAME="Underflow_Sense_AXI" VALUE="Active_High"/>
        <PARAMETER NAME="Overflow_Flag_AXI" VALUE="false"/>
        <PARAMETER NAME="Overflow_Sense_AXI" VALUE="Active_High"/>
        <PARAMETER NAME="Disable_Timing_Violations_AXI" VALUE="false"/>
        <PARAMETER NAME="Add_NGC_Constraint_AXI" VALUE="false"/>
        <PARAMETER NAME="Enable_Common_Underflow" VALUE="false"/>
        <PARAMETER NAME="Enable_Common_Overflow" VALUE="false"/>
        <PARAMETER NAME="enable_read_pointer_increment_by2" VALUE="false"/>
        <PARAMETER NAME="Use_Embedded_Registers_axis" VALUE="false"/>
        <PARAMETER NAME="enable_low_latency" VALUE="false"/>
        <PARAMETER NAME="use_dout_register" VALUE="false"/>
        <PARAMETER NAME="Master_interface_Clock_enable_memory_mapped" VALUE="false"/>
        <PARAMETER NAME="Slave_interface_Clock_enable_memory_mapped" VALUE="false"/>
        <PARAMETER NAME="Output_Register_Type" VALUE="Embedded_Reg"/>
        <PARAMETER NAME="Enable_Safety_Circuit" VALUE="false"/>
        <PARAMETER NAME="Enable_ECC_Type" VALUE="Hard_ECC"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="clk" SIGIS="clk" SIGNAME="External_Ports_clk_100MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="clk_100MHz"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="srst" SIGIS="undef" SIGNAME="negate_0_S">
          <CONNECTIONS>
            <CONNECTION INSTANCE="negate_0" PORT="S"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_fifo_write_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="fifo_write_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="wr_en" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_fifo_write_enable">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="fifo_write_enable"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="rd_en" SIGIS="undef" SIGNAME="packaging_0_inpRdEn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="packaging_0" PORT="inpRdEn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="fifo_input_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="packaging_0" PORT="inputStream"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="full" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_fifo_write_full">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="fifo_write_full"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="overflow" SIGIS="undef" SIGNAME="fifo_input_overflow">
          <CONNECTIONS>
            <CONNECTION INSTANCE="c_counter_binary_1" PORT="CE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="empty" SIGIS="undef" SIGNAME="fifo_input_empty">
          <CONNECTIONS>
            <CONNECTION INSTANCE="packaging_0" PORT="inputEmpty"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="ethernet_transceiver2_0_fifo_write" NAME="FIFO_WRITE" TYPE="TARGET" VLNV="xilinx.com:interface:fifo_write:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="FULL" PHYSICAL="full"/>
            <PORTMAP LOGICAL="WR_DATA" PHYSICAL="din"/>
            <PORTMAP LOGICAL="WR_EN" PHYSICAL="wr_en"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="FIFO_READ" TYPE="TARGET" VLNV="xilinx.com:interface:fifo_read:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="EMPTY" PHYSICAL="empty"/>
            <PORTMAP LOGICAL="RD_DATA" PHYSICAL="dout"/>
            <PORTMAP LOGICAL="RD_EN" PHYSICAL="rd_en"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="3" FULLNAME="/fifo_output" HWVERSION="13.2" INSTANCE="fifo_output" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="fifo_generator" VLNV="xilinx.com:ip:fifo_generator:13.2">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=fifo_generator;v=v13_2;d=pg057-fifo-generator.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_COMMON_CLOCK" VALUE="0"/>
        <PARAMETER NAME="C_SELECT_XPM" VALUE="0"/>
        <PARAMETER NAME="C_COUNT_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_DATA_COUNT_WIDTH" VALUE="9"/>
        <PARAMETER NAME="C_DEFAULT_VALUE" VALUE="BlankString"/>
        <PARAMETER NAME="C_DIN_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_DOUT_RST_VAL" VALUE="0"/>
        <PARAMETER NAME="C_DOUT_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_ENABLE_RLOCS" VALUE="0"/>
        <PARAMETER NAME="C_FAMILY" VALUE="artix7"/>
        <PARAMETER NAME="C_FULL_FLAGS_RST_VAL" VALUE="1"/>
        <PARAMETER NAME="C_HAS_ALMOST_EMPTY" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ALMOST_FULL" VALUE="0"/>
        <PARAMETER NAME="C_HAS_BACKUP" VALUE="0"/>
        <PARAMETER NAME="C_HAS_DATA_COUNT" VALUE="0"/>
        <PARAMETER NAME="C_HAS_INT_CLK" VALUE="0"/>
        <PARAMETER NAME="C_HAS_MEMINIT_FILE" VALUE="0"/>
        <PARAMETER NAME="C_HAS_OVERFLOW" VALUE="1"/>
        <PARAMETER NAME="C_HAS_RD_DATA_COUNT" VALUE="1"/>
        <PARAMETER NAME="C_HAS_RD_RST" VALUE="0"/>
        <PARAMETER NAME="C_HAS_RST" VALUE="1"/>
        <PARAMETER NAME="C_HAS_SRST" VALUE="0"/>
        <PARAMETER NAME="C_HAS_UNDERFLOW" VALUE="0"/>
        <PARAMETER NAME="C_HAS_VALID" VALUE="0"/>
        <PARAMETER NAME="C_HAS_WR_ACK" VALUE="0"/>
        <PARAMETER NAME="C_HAS_WR_DATA_COUNT" VALUE="0"/>
        <PARAMETER NAME="C_HAS_WR_RST" VALUE="0"/>
        <PARAMETER NAME="C_IMPLEMENTATION_TYPE" VALUE="2"/>
        <PARAMETER NAME="C_INIT_WR_PNTR_VAL" VALUE="0"/>
        <PARAMETER NAME="C_MEMORY_TYPE" VALUE="2"/>
        <PARAMETER NAME="C_MIF_FILE_NAME" VALUE="BlankString"/>
        <PARAMETER NAME="C_OPTIMIZATION_MODE" VALUE="0"/>
        <PARAMETER NAME="C_OVERFLOW_LOW" VALUE="0"/>
        <PARAMETER NAME="C_PRELOAD_LATENCY" VALUE="1"/>
        <PARAMETER NAME="C_PRELOAD_REGS" VALUE="0"/>
        <PARAMETER NAME="C_PRIM_FIFO_TYPE" VALUE="512x36"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_ASSERT_VAL" VALUE="2"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_NEGATE_VAL" VALUE="3"/>
        <PARAMETER NAME="C_PROG_EMPTY_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_ASSERT_VAL" VALUE="509"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_NEGATE_VAL" VALUE="508"/>
        <PARAMETER NAME="C_PROG_FULL_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_RD_DATA_COUNT_WIDTH" VALUE="9"/>
        <PARAMETER NAME="C_RD_DEPTH" VALUE="512"/>
        <PARAMETER NAME="C_RD_FREQ" VALUE="1"/>
        <PARAMETER NAME="C_RD_PNTR_WIDTH" VALUE="9"/>
        <PARAMETER NAME="C_UNDERFLOW_LOW" VALUE="0"/>
        <PARAMETER NAME="C_USE_DOUT_RST" VALUE="1"/>
        <PARAMETER NAME="C_USE_ECC" VALUE="0"/>
        <PARAMETER NAME="C_USE_EMBEDDED_REG" VALUE="0"/>
        <PARAMETER NAME="C_USE_PIPELINE_REG" VALUE="0"/>
        <PARAMETER NAME="C_POWER_SAVING_MODE" VALUE="0"/>
        <PARAMETER NAME="C_USE_FIFO16_FLAGS" VALUE="0"/>
        <PARAMETER NAME="C_USE_FWFT_DATA_COUNT" VALUE="0"/>
        <PARAMETER NAME="C_VALID_LOW" VALUE="0"/>
        <PARAMETER NAME="C_WR_ACK_LOW" VALUE="0"/>
        <PARAMETER NAME="C_WR_DATA_COUNT_WIDTH" VALUE="9"/>
        <PARAMETER NAME="C_WR_DEPTH" VALUE="512"/>
        <PARAMETER NAME="C_WR_FREQ" VALUE="1"/>
        <PARAMETER NAME="C_WR_PNTR_WIDTH" VALUE="9"/>
        <PARAMETER NAME="C_WR_RESPONSE_LATENCY" VALUE="1"/>
        <PARAMETER NAME="C_MSGON_VAL" VALUE="1"/>
        <PARAMETER NAME="C_ENABLE_RST_SYNC" VALUE="1"/>
        <PARAMETER NAME="C_EN_SAFETY_CKT" VALUE="0"/>
        <PARAMETER NAME="C_ERROR_INJECTION_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_SYNCHRONIZER_STAGE" VALUE="2"/>
        <PARAMETER NAME="C_INTERFACE_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_AXI_TYPE" VALUE="1"/>
        <PARAMETER NAME="C_HAS_AXI_WR_CHANNEL" VALUE="1"/>
        <PARAMETER NAME="C_HAS_AXI_RD_CHANNEL" VALUE="1"/>
        <PARAMETER NAME="C_HAS_SLAVE_CE" VALUE="0"/>
        <PARAMETER NAME="C_HAS_MASTER_CE" VALUE="0"/>
        <PARAMETER NAME="C_ADD_NGC_CONSTRAINT" VALUE="0"/>
        <PARAMETER NAME="C_USE_COMMON_OVERFLOW" VALUE="0"/>
        <PARAMETER NAME="C_USE_COMMON_UNDERFLOW" VALUE="0"/>
        <PARAMETER NAME="C_USE_DEFAULT_SETTINGS" VALUE="0"/>
        <PARAMETER NAME="C_AXI_ID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXI_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_AXI_DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C_AXI_LEN_WIDTH" VALUE="8"/>
        <PARAMETER NAME="C_AXI_LOCK_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_HAS_AXI_ID" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXI_AWUSER" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXI_WUSER" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXI_BUSER" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXI_ARUSER" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXI_RUSER" VALUE="0"/>
        <PARAMETER NAME="C_AXI_ARUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXI_AWUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXI_WUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXI_BUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXI_RUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_HAS_AXIS_TDATA" VALUE="1"/>
        <PARAMETER NAME="C_HAS_AXIS_TID" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXIS_TDEST" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXIS_TUSER" VALUE="1"/>
        <PARAMETER NAME="C_HAS_AXIS_TREADY" VALUE="1"/>
        <PARAMETER NAME="C_HAS_AXIS_TLAST" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXIS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="C_HAS_AXIS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="8"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TUSER_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_AXIS_TSTRB_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TKEEP_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_WACH_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_WDCH_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_WRCH_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_RACH_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_RDCH_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_AXIS_TYPE" VALUE="0"/>
        <PARAMETER NAME="C_IMPLEMENTATION_TYPE_WACH" VALUE="2"/>
        <PARAMETER NAME="C_IMPLEMENTATION_TYPE_WDCH" VALUE="1"/>
        <PARAMETER NAME="C_IMPLEMENTATION_TYPE_WRCH" VALUE="2"/>
        <PARAMETER NAME="C_IMPLEMENTATION_TYPE_RACH" VALUE="2"/>
        <PARAMETER NAME="C_IMPLEMENTATION_TYPE_RDCH" VALUE="1"/>
        <PARAMETER NAME="C_IMPLEMENTATION_TYPE_AXIS" VALUE="1"/>
        <PARAMETER NAME="C_APPLICATION_TYPE_WACH" VALUE="0"/>
        <PARAMETER NAME="C_APPLICATION_TYPE_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_APPLICATION_TYPE_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_APPLICATION_TYPE_RACH" VALUE="0"/>
        <PARAMETER NAME="C_APPLICATION_TYPE_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_APPLICATION_TYPE_AXIS" VALUE="0"/>
        <PARAMETER NAME="C_PRIM_FIFO_TYPE_WACH" VALUE="512x36"/>
        <PARAMETER NAME="C_PRIM_FIFO_TYPE_WDCH" VALUE="1kx36"/>
        <PARAMETER NAME="C_PRIM_FIFO_TYPE_WRCH" VALUE="512x36"/>
        <PARAMETER NAME="C_PRIM_FIFO_TYPE_RACH" VALUE="512x36"/>
        <PARAMETER NAME="C_PRIM_FIFO_TYPE_RDCH" VALUE="1kx36"/>
        <PARAMETER NAME="C_PRIM_FIFO_TYPE_AXIS" VALUE="1kx18"/>
        <PARAMETER NAME="C_USE_ECC_WACH" VALUE="0"/>
        <PARAMETER NAME="C_USE_ECC_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_USE_ECC_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_USE_ECC_RACH" VALUE="0"/>
        <PARAMETER NAME="C_USE_ECC_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_USE_ECC_AXIS" VALUE="0"/>
        <PARAMETER NAME="C_ERROR_INJECTION_TYPE_WACH" VALUE="0"/>
        <PARAMETER NAME="C_ERROR_INJECTION_TYPE_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_ERROR_INJECTION_TYPE_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_ERROR_INJECTION_TYPE_RACH" VALUE="0"/>
        <PARAMETER NAME="C_ERROR_INJECTION_TYPE_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_ERROR_INJECTION_TYPE_AXIS" VALUE="0"/>
        <PARAMETER NAME="C_DIN_WIDTH_WACH" VALUE="1"/>
        <PARAMETER NAME="C_DIN_WIDTH_WDCH" VALUE="64"/>
        <PARAMETER NAME="C_DIN_WIDTH_WRCH" VALUE="2"/>
        <PARAMETER NAME="C_DIN_WIDTH_RACH" VALUE="32"/>
        <PARAMETER NAME="C_DIN_WIDTH_RDCH" VALUE="64"/>
        <PARAMETER NAME="C_DIN_WIDTH_AXIS" VALUE="1"/>
        <PARAMETER NAME="C_WR_DEPTH_WACH" VALUE="16"/>
        <PARAMETER NAME="C_WR_DEPTH_WDCH" VALUE="1024"/>
        <PARAMETER NAME="C_WR_DEPTH_WRCH" VALUE="16"/>
        <PARAMETER NAME="C_WR_DEPTH_RACH" VALUE="16"/>
        <PARAMETER NAME="C_WR_DEPTH_RDCH" VALUE="1024"/>
        <PARAMETER NAME="C_WR_DEPTH_AXIS" VALUE="1024"/>
        <PARAMETER NAME="C_WR_PNTR_WIDTH_WACH" VALUE="4"/>
        <PARAMETER NAME="C_WR_PNTR_WIDTH_WDCH" VALUE="10"/>
        <PARAMETER NAME="C_WR_PNTR_WIDTH_WRCH" VALUE="4"/>
        <PARAMETER NAME="C_WR_PNTR_WIDTH_RACH" VALUE="4"/>
        <PARAMETER NAME="C_WR_PNTR_WIDTH_RDCH" VALUE="10"/>
        <PARAMETER NAME="C_WR_PNTR_WIDTH_AXIS" VALUE="10"/>
        <PARAMETER NAME="C_HAS_DATA_COUNTS_WACH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_DATA_COUNTS_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_DATA_COUNTS_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_DATA_COUNTS_RACH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_DATA_COUNTS_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_DATA_COUNTS_AXIS" VALUE="0"/>
        <PARAMETER NAME="C_HAS_PROG_FLAGS_WACH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_PROG_FLAGS_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_PROG_FLAGS_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_PROG_FLAGS_RACH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_PROG_FLAGS_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_HAS_PROG_FLAGS_AXIS" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_TYPE_WACH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_TYPE_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_TYPE_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_TYPE_RACH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_TYPE_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_TYPE_AXIS" VALUE="0"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_ASSERT_VAL_WACH" VALUE="1023"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_ASSERT_VAL_WDCH" VALUE="1023"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_ASSERT_VAL_WRCH" VALUE="1023"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_ASSERT_VAL_RACH" VALUE="1023"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_ASSERT_VAL_RDCH" VALUE="1023"/>
        <PARAMETER NAME="C_PROG_FULL_THRESH_ASSERT_VAL_AXIS" VALUE="1023"/>
        <PARAMETER NAME="C_PROG_EMPTY_TYPE_WACH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_EMPTY_TYPE_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_EMPTY_TYPE_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_EMPTY_TYPE_RACH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_EMPTY_TYPE_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_PROG_EMPTY_TYPE_AXIS" VALUE="0"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH" VALUE="1022"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH" VALUE="1022"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH" VALUE="1022"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH" VALUE="1022"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH" VALUE="1022"/>
        <PARAMETER NAME="C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS" VALUE="1022"/>
        <PARAMETER NAME="C_REG_SLICE_MODE_WACH" VALUE="0"/>
        <PARAMETER NAME="C_REG_SLICE_MODE_WDCH" VALUE="0"/>
        <PARAMETER NAME="C_REG_SLICE_MODE_WRCH" VALUE="0"/>
        <PARAMETER NAME="C_REG_SLICE_MODE_RACH" VALUE="0"/>
        <PARAMETER NAME="C_REG_SLICE_MODE_RDCH" VALUE="0"/>
        <PARAMETER NAME="C_REG_SLICE_MODE_AXIS" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_fifo_generator_0_0"/>
        <PARAMETER NAME="Fifo_Implementation" VALUE="Independent_Clocks_Distributed_RAM"/>
        <PARAMETER NAME="synchronization_stages" VALUE="2"/>
        <PARAMETER NAME="synchronization_stages_axi" VALUE="2"/>
        <PARAMETER NAME="INTERFACE_TYPE" VALUE="Native"/>
        <PARAMETER NAME="Performance_Options" VALUE="Standard_FIFO"/>
        <PARAMETER NAME="asymmetric_port_width" VALUE="false"/>
        <PARAMETER NAME="Input_Data_Width" VALUE="32"/>
        <PARAMETER NAME="Input_Depth" VALUE="512"/>
        <PARAMETER NAME="Output_Data_Width" VALUE="32"/>
        <PARAMETER NAME="Output_Depth" VALUE="512"/>
        <PARAMETER NAME="Enable_ECC" VALUE="false"/>
        <PARAMETER NAME="Use_Embedded_Registers" VALUE="false"/>
        <PARAMETER NAME="Reset_Pin" VALUE="true"/>
        <PARAMETER NAME="Enable_Reset_Synchronization" VALUE="true"/>
        <PARAMETER NAME="Reset_Type" VALUE="Asynchronous_Reset"/>
        <PARAMETER NAME="Full_Flags_Reset_Value" VALUE="1"/>
        <PARAMETER NAME="Use_Dout_Reset" VALUE="true"/>
        <PARAMETER NAME="Dout_Reset_Value" VALUE="0"/>
        <PARAMETER NAME="dynamic_power_saving" VALUE="false"/>
        <PARAMETER NAME="Almost_Full_Flag" VALUE="false"/>
        <PARAMETER NAME="Almost_Empty_Flag" VALUE="false"/>
        <PARAMETER NAME="Valid_Flag" VALUE="false"/>
        <PARAMETER NAME="Valid_Sense" VALUE="Active_High"/>
        <PARAMETER NAME="Underflow_Flag" VALUE="false"/>
        <PARAMETER NAME="Underflow_Sense" VALUE="Active_High"/>
        <PARAMETER NAME="Write_Acknowledge_Flag" VALUE="false"/>
        <PARAMETER NAME="Write_Acknowledge_Sense" VALUE="Active_High"/>
        <PARAMETER NAME="Overflow_Flag" VALUE="true"/>
        <PARAMETER NAME="Overflow_Sense" VALUE="Active_High"/>
        <PARAMETER NAME="Inject_Sbit_Error" VALUE="false"/>
        <PARAMETER NAME="Inject_Dbit_Error" VALUE="false"/>
        <PARAMETER NAME="ecc_pipeline_reg" VALUE="false"/>
        <PARAMETER NAME="Use_Extra_Logic" VALUE="false"/>
        <PARAMETER NAME="Data_Count" VALUE="false"/>
        <PARAMETER NAME="Data_Count_Width" VALUE="9"/>
        <PARAMETER NAME="Write_Data_Count" VALUE="false"/>
        <PARAMETER NAME="Write_Data_Count_Width" VALUE="9"/>
        <PARAMETER NAME="Read_Data_Count" VALUE="true"/>
        <PARAMETER NAME="Read_Data_Count_Width" VALUE="9"/>
        <PARAMETER NAME="Disable_Timing_Violations" VALUE="false"/>
        <PARAMETER NAME="Read_Clock_Frequency" VALUE="1"/>
        <PARAMETER NAME="Write_Clock_Frequency" VALUE="1"/>
        <PARAMETER NAME="Programmable_Full_Type" VALUE="No_Programmable_Full_Threshold"/>
        <PARAMETER NAME="Full_Threshold_Assert_Value" VALUE="509"/>
        <PARAMETER NAME="Full_Threshold_Negate_Value" VALUE="508"/>
        <PARAMETER NAME="Programmable_Empty_Type" VALUE="No_Programmable_Empty_Threshold"/>
        <PARAMETER NAME="Empty_Threshold_Assert_Value" VALUE="2"/>
        <PARAMETER NAME="Empty_Threshold_Negate_Value" VALUE="3"/>
        <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
        <PARAMETER NAME="Clock_Type_AXI" VALUE="Common_Clock"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="false"/>
        <PARAMETER NAME="Clock_Enable_Type" VALUE="Slave_Interface_Clock_Enable"/>
        <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
        <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="ADDRESS_WIDTH" VALUE="32"/>
        <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="AWUSER_Width" VALUE="0"/>
        <PARAMETER NAME="WUSER_Width" VALUE="0"/>
        <PARAMETER NAME="BUSER_Width" VALUE="0"/>
        <PARAMETER NAME="ARUSER_Width" VALUE="0"/>
        <PARAMETER NAME="RUSER_Width" VALUE="0"/>
        <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="1"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TUSER_WIDTH" VALUE="4"/>
        <PARAMETER NAME="Enable_TREADY" VALUE="true"/>
        <PARAMETER NAME="Enable_TLAST" VALUE="false"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="false"/>
        <PARAMETER NAME="TSTRB_WIDTH" VALUE="1"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="false"/>
        <PARAMETER NAME="TKEEP_WIDTH" VALUE="1"/>
        <PARAMETER NAME="wach_type" VALUE="FIFO"/>
        <PARAMETER NAME="FIFO_Implementation_wach" VALUE="Common_Clock_Distributed_RAM"/>
        <PARAMETER NAME="FIFO_Application_Type_wach" VALUE="Data_FIFO"/>
        <PARAMETER NAME="Enable_ECC_wach" VALUE="false"/>
        <PARAMETER NAME="Inject_Sbit_Error_wach" VALUE="false"/>
        <PARAMETER NAME="Inject_Dbit_Error_wach" VALUE="false"/>
        <PARAMETER NAME="Input_Depth_wach" VALUE="16"/>
        <PARAMETER NAME="Enable_Data_Counts_wach" VALUE="false"/>
        <PARAMETER NAME="Programmable_Full_Type_wach" VALUE="No_Programmable_Full_Threshold"/>
        <PARAMETER NAME="Full_Threshold_Assert_Value_wach" VALUE="1023"/>
        <PARAMETER NAME="Programmable_Empty_Type_wach" VALUE="No_Programmable_Empty_Threshold"/>
        <PARAMETER NAME="Empty_Threshold_Assert_Value_wach" VALUE="1022"/>
        <PARAMETER NAME="wdch_type" VALUE="FIFO"/>
        <PARAMETER NAME="FIFO_Implementation_wdch" VALUE="Common_Clock_Block_RAM"/>
        <PARAMETER NAME="FIFO_Application_Type_wdch" VALUE="Data_FIFO"/>
        <PARAMETER NAME="Enable_ECC_wdch" VALUE="false"/>
        <PARAMETER NAME="Inject_Sbit_Error_wdch" VALUE="false"/>
        <PARAMETER NAME="Inject_Dbit_Error_wdch" VALUE="false"/>
        <PARAMETER NAME="Input_Depth_wdch" VALUE="1024"/>
        <PARAMETER NAME="Enable_Data_Counts_wdch" VALUE="false"/>
        <PARAMETER NAME="Programmable_Full_Type_wdch" VALUE="No_Programmable_Full_Threshold"/>
        <PARAMETER NAME="Full_Threshold_Assert_Value_wdch" VALUE="1023"/>
        <PARAMETER NAME="Programmable_Empty_Type_wdch" VALUE="No_Programmable_Empty_Threshold"/>
        <PARAMETER NAME="Empty_Threshold_Assert_Value_wdch" VALUE="1022"/>
        <PARAMETER NAME="wrch_type" VALUE="FIFO"/>
        <PARAMETER NAME="FIFO_Implementation_wrch" VALUE="Common_Clock_Distributed_RAM"/>
        <PARAMETER NAME="FIFO_Application_Type_wrch" VALUE="Data_FIFO"/>
        <PARAMETER NAME="Enable_ECC_wrch" VALUE="false"/>
        <PARAMETER NAME="Inject_Sbit_Error_wrch" VALUE="false"/>
        <PARAMETER NAME="Inject_Dbit_Error_wrch" VALUE="false"/>
        <PARAMETER NAME="Input_Depth_wrch" VALUE="16"/>
        <PARAMETER NAME="Enable_Data_Counts_wrch" VALUE="false"/>
        <PARAMETER NAME="Programmable_Full_Type_wrch" VALUE="No_Programmable_Full_Threshold"/>
        <PARAMETER NAME="Full_Threshold_Assert_Value_wrch" VALUE="1023"/>
        <PARAMETER NAME="Programmable_Empty_Type_wrch" VALUE="No_Programmable_Empty_Threshold"/>
        <PARAMETER NAME="Empty_Threshold_Assert_Value_wrch" VALUE="1022"/>
        <PARAMETER NAME="rach_type" VALUE="FIFO"/>
        <PARAMETER NAME="FIFO_Implementation_rach" VALUE="Common_Clock_Distributed_RAM"/>
        <PARAMETER NAME="FIFO_Application_Type_rach" VALUE="Data_FIFO"/>
        <PARAMETER NAME="Enable_ECC_rach" VALUE="false"/>
        <PARAMETER NAME="Inject_Sbit_Error_rach" VALUE="false"/>
        <PARAMETER NAME="Inject_Dbit_Error_rach" VALUE="false"/>
        <PARAMETER NAME="Input_Depth_rach" VALUE="16"/>
        <PARAMETER NAME="Enable_Data_Counts_rach" VALUE="false"/>
        <PARAMETER NAME="Programmable_Full_Type_rach" VALUE="No_Programmable_Full_Threshold"/>
        <PARAMETER NAME="Full_Threshold_Assert_Value_rach" VALUE="1023"/>
        <PARAMETER NAME="Programmable_Empty_Type_rach" VALUE="No_Programmable_Empty_Threshold"/>
        <PARAMETER NAME="Empty_Threshold_Assert_Value_rach" VALUE="1022"/>
        <PARAMETER NAME="rdch_type" VALUE="FIFO"/>
        <PARAMETER NAME="FIFO_Implementation_rdch" VALUE="Common_Clock_Block_RAM"/>
        <PARAMETER NAME="FIFO_Application_Type_rdch" VALUE="Data_FIFO"/>
        <PARAMETER NAME="Enable_ECC_rdch" VALUE="false"/>
        <PARAMETER NAME="Inject_Sbit_Error_rdch" VALUE="false"/>
        <PARAMETER NAME="Inject_Dbit_Error_rdch" VALUE="false"/>
        <PARAMETER NAME="Input_Depth_rdch" VALUE="1024"/>
        <PARAMETER NAME="Enable_Data_Counts_rdch" VALUE="false"/>
        <PARAMETER NAME="Programmable_Full_Type_rdch" VALUE="No_Programmable_Full_Threshold"/>
        <PARAMETER NAME="Full_Threshold_Assert_Value_rdch" VALUE="1023"/>
        <PARAMETER NAME="Programmable_Empty_Type_rdch" VALUE="No_Programmable_Empty_Threshold"/>
        <PARAMETER NAME="Empty_Threshold_Assert_Value_rdch" VALUE="1022"/>
        <PARAMETER NAME="axis_type" VALUE="FIFO"/>
        <PARAMETER NAME="FIFO_Implementation_axis" VALUE="Common_Clock_Block_RAM"/>
        <PARAMETER NAME="FIFO_Application_Type_axis" VALUE="Data_FIFO"/>
        <PARAMETER NAME="Enable_ECC_axis" VALUE="false"/>
        <PARAMETER NAME="Inject_Sbit_Error_axis" VALUE="false"/>
        <PARAMETER NAME="Inject_Dbit_Error_axis" VALUE="false"/>
        <PARAMETER NAME="Input_Depth_axis" VALUE="1024"/>
        <PARAMETER NAME="Enable_Data_Counts_axis" VALUE="false"/>
        <PARAMETER NAME="Programmable_Full_Type_axis" VALUE="No_Programmable_Full_Threshold"/>
        <PARAMETER NAME="Full_Threshold_Assert_Value_axis" VALUE="1023"/>
        <PARAMETER NAME="Programmable_Empty_Type_axis" VALUE="No_Programmable_Empty_Threshold"/>
        <PARAMETER NAME="Empty_Threshold_Assert_Value_axis" VALUE="1022"/>
        <PARAMETER NAME="Register_Slice_Mode_wach" VALUE="Fully_Registered"/>
        <PARAMETER NAME="Register_Slice_Mode_wdch" VALUE="Fully_Registered"/>
        <PARAMETER NAME="Register_Slice_Mode_wrch" VALUE="Fully_Registered"/>
        <PARAMETER NAME="Register_Slice_Mode_rach" VALUE="Fully_Registered"/>
        <PARAMETER NAME="Register_Slice_Mode_rdch" VALUE="Fully_Registered"/>
        <PARAMETER NAME="Register_Slice_Mode_axis" VALUE="Fully_Registered"/>
        <PARAMETER NAME="Underflow_Flag_AXI" VALUE="false"/>
        <PARAMETER NAME="Underflow_Sense_AXI" VALUE="Active_High"/>
        <PARAMETER NAME="Overflow_Flag_AXI" VALUE="false"/>
        <PARAMETER NAME="Overflow_Sense_AXI" VALUE="Active_High"/>
        <PARAMETER NAME="Disable_Timing_Violations_AXI" VALUE="false"/>
        <PARAMETER NAME="Add_NGC_Constraint_AXI" VALUE="false"/>
        <PARAMETER NAME="Enable_Common_Underflow" VALUE="false"/>
        <PARAMETER NAME="Enable_Common_Overflow" VALUE="false"/>
        <PARAMETER NAME="enable_read_pointer_increment_by2" VALUE="false"/>
        <PARAMETER NAME="Use_Embedded_Registers_axis" VALUE="false"/>
        <PARAMETER NAME="enable_low_latency" VALUE="false"/>
        <PARAMETER NAME="use_dout_register" VALUE="false"/>
        <PARAMETER NAME="Master_interface_Clock_enable_memory_mapped" VALUE="false"/>
        <PARAMETER NAME="Slave_interface_Clock_enable_memory_mapped" VALUE="false"/>
        <PARAMETER NAME="Output_Register_Type" VALUE="Embedded_Reg"/>
        <PARAMETER NAME="Enable_Safety_Circuit" VALUE="false"/>
        <PARAMETER NAME="Enable_ECC_Type" VALUE="Hard_ECC"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="rst" SIGIS="undef" SIGNAME="negate_0_S">
          <CONNECTIONS>
            <CONNECTION INSTANCE="negate_0" PORT="S"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="wr_clk" SIGIS="clk" SIGNAME="External_Ports_clk_100MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="clk_100MHz"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="rd_clk" SIGIS="clk" SIGNAME="ethernet_transceiver2_0_eth_refclk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="eth_refclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="packaging_0_outData">
          <CONNECTIONS>
            <CONNECTION INSTANCE="packaging_0" PORT="outData"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="wr_en" SIGIS="undef" SIGNAME="packaging_0_outWrEn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="packaging_0" PORT="outWrEn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="rd_en" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_fifo_read_enable">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="fifo_read_enable"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_fifo_read_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="fifo_read_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="full" SIGIS="undef" SIGNAME="fifo_output_full">
          <CONNECTIONS>
            <CONNECTION INSTANCE="packaging_0" PORT="outputFull"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="overflow" SIGIS="undef" SIGNAME="fifo_output_overflow">
          <CONNECTIONS>
            <CONNECTION INSTANCE="c_counter_binary_0" PORT="CE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="empty" SIGIS="undef" SIGNAME="ethernet_transceiver2_0_fifo_read_empty">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="fifo_read_empty"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="8" NAME="rd_data_count" RIGHT="0" SIGIS="undef" SIGNAME="fifo_output_rd_data_count">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconcat_5" PORT="In0"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="FIFO_WRITE" TYPE="TARGET" VLNV="xilinx.com:interface:fifo_write:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="FULL" PHYSICAL="full"/>
            <PORTMAP LOGICAL="WR_DATA" PHYSICAL="din"/>
            <PORTMAP LOGICAL="WR_EN" PHYSICAL="wr_en"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ethernet_transceiver2_0_fifo_read" NAME="FIFO_READ" TYPE="TARGET" VLNV="xilinx.com:interface:fifo_read:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="EMPTY" PHYSICAL="empty"/>
            <PORTMAP LOGICAL="RD_DATA" PHYSICAL="dout"/>
            <PORTMAP LOGICAL="RD_EN" PHYSICAL="rd_en"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="12" FULLNAME="/negate_0" HWVERSION="12.0" INSTANCE="negate_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="c_addsub" VLNV="xilinx.com:ip:c_addsub:12.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=c_addsub;v=v12_0;d=pg120-c-addsub.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_VERBOSITY" VALUE="0"/>
        <PARAMETER NAME="C_XDEVICEFAMILY" VALUE="artix7"/>
        <PARAMETER NAME="C_IMPLEMENTATION" VALUE="0"/>
        <PARAMETER NAME="C_A_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_B_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_OUT_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_CE_OVERRIDES_SCLR" VALUE="0"/>
        <PARAMETER NAME="C_A_TYPE" VALUE="1"/>
        <PARAMETER NAME="C_B_TYPE" VALUE="1"/>
        <PARAMETER NAME="C_LATENCY" VALUE="1"/>
        <PARAMETER NAME="C_ADD_MODE" VALUE="0"/>
        <PARAMETER NAME="C_B_CONSTANT" VALUE="1"/>
        <PARAMETER NAME="C_B_VALUE" VALUE="1"/>
        <PARAMETER NAME="C_AINIT_VAL" VALUE="0"/>
        <PARAMETER NAME="C_SINIT_VAL" VALUE="0"/>
        <PARAMETER NAME="C_CE_OVERRIDES_BYPASS" VALUE="1"/>
        <PARAMETER NAME="C_BYPASS_LOW" VALUE="0"/>
        <PARAMETER NAME="C_SCLR_OVERRIDES_SSET" VALUE="1"/>
        <PARAMETER NAME="C_HAS_C_IN" VALUE="0"/>
        <PARAMETER NAME="C_HAS_C_OUT" VALUE="0"/>
        <PARAMETER NAME="C_BORROW_LOW" VALUE="1"/>
        <PARAMETER NAME="C_HAS_CE" VALUE="0"/>
        <PARAMETER NAME="C_HAS_BYPASS" VALUE="0"/>
        <PARAMETER NAME="C_HAS_SCLR" VALUE="0"/>
        <PARAMETER NAME="C_HAS_SSET" VALUE="0"/>
        <PARAMETER NAME="C_HAS_SINIT" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_c_addsub_0_0"/>
        <PARAMETER NAME="Implementation" VALUE="Fabric"/>
        <PARAMETER NAME="A_Type" VALUE="Unsigned"/>
        <PARAMETER NAME="B_Type" VALUE="Unsigned"/>
        <PARAMETER NAME="A_Width" VALUE="1"/>
        <PARAMETER NAME="B_Width" VALUE="1"/>
        <PARAMETER NAME="Add_Mode" VALUE="Add"/>
        <PARAMETER NAME="Out_Width" VALUE="1"/>
        <PARAMETER NAME="Latency_Configuration" VALUE="Automatic"/>
        <PARAMETER NAME="Latency" VALUE="1"/>
        <PARAMETER NAME="B_Constant" VALUE="true"/>
        <PARAMETER NAME="B_Value" VALUE="1"/>
        <PARAMETER NAME="CE" VALUE="false"/>
        <PARAMETER NAME="C_In" VALUE="false"/>
        <PARAMETER NAME="C_Out" VALUE="false"/>
        <PARAMETER NAME="Borrow_Sense" VALUE="Active_Low"/>
        <PARAMETER NAME="SCLR" VALUE="false"/>
        <PARAMETER NAME="SSET" VALUE="false"/>
        <PARAMETER NAME="SINIT" VALUE="false"/>
        <PARAMETER NAME="SINIT_Value" VALUE="0"/>
        <PARAMETER NAME="Bypass" VALUE="false"/>
        <PARAMETER NAME="Bypass_Sense" VALUE="Active_High"/>
        <PARAMETER NAME="Sync_Ctrl_Priority" VALUE="Reset_Overrides_Set"/>
        <PARAMETER NAME="Sync_CE_Priority" VALUE="Sync_Overrides_CE"/>
        <PARAMETER NAME="Bypass_CE_Priority" VALUE="CE_Overrides_Bypass"/>
        <PARAMETER NAME="AINIT_Value" VALUE="0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="0" NAME="A" RIGHT="0" SIGIS="data" SIGNAME="External_Ports_reset_rtl_0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="reset_rtl_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="CLK" SIGIS="clk" SIGNAME="External_Ports_clk_100MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="clk_100MHz"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="S" RIGHT="0" SIGIS="data" SIGNAME="negate_0_S">
          <CONNECTIONS>
            <CONNECTION INSTANCE="c_counter_binary_0" PORT="SCLR"/>
            <CONNECTION INSTANCE="c_counter_binary_1" PORT="SCLR"/>
            <CONNECTION INSTANCE="fifo_input" PORT="srst"/>
            <CONNECTION INSTANCE="fifo_output" PORT="rst"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/packaging_0" HWVERSION="1.0" INSTANCE="packaging_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="packaging" VLNV="xilinx.com:module_ref:packaging:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="busWidth" VALUE="32"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_packaging_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="clk" SIGIS="clk" SIGNAME="External_Ports_clk_100MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="clk_100MHz"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="rst" SIGIS="rst" SIGNAME="External_Ports_reset_rtl_0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="reset_rtl_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="inputStream" RIGHT="0" SIGIS="undef" SIGNAME="fifo_input_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_input" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="inpRdEn" SIGIS="undef" SIGNAME="packaging_0_inpRdEn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_input" PORT="rd_en"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="inputEmpty" SIGIS="undef" SIGNAME="fifo_input_empty">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_input" PORT="empty"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="outData" RIGHT="0" SIGIS="undef" SIGNAME="packaging_0_outData">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_output" PORT="din"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="outWrEn" SIGIS="undef" SIGNAME="packaging_0_outWrEn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_output" PORT="wr_en"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="outputFull" SIGIS="undef" SIGNAME="fifo_output_full">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_output" PORT="full"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="errorCode" RIGHT="0" SIGIS="undef" SIGNAME="packaging_0_errorCode">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconcat_4" PORT="In0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="stateOut" RIGHT="0" SIGIS="undef" SIGNAME="packaging_0_stateOut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconcat_4" PORT="In1"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="4" FULLNAME="/segment_0" HWVERSION="1.0" INSTANCE="segment_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="segment" VLNV="xilinx.com:user:segment:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="Component_Name" VALUE="design_1_segment_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="15" NAME="num1" RIGHT="0" SIGIS="undef" SIGNAME="c_counter_binary_1_Q">
          <CONNECTIONS>
            <CONNECTION INSTANCE="c_counter_binary_1" PORT="Q"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="num2" RIGHT="0" SIGIS="undef" SIGNAME="c_counter_binary_0_Q">
          <CONNECTIONS>
            <CONNECTION INSTANCE="c_counter_binary_0" PORT="Q"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="clk" SIGIS="clk" SIGNAME="External_Ports_clk_100MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="clk_100MHz"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="anodes" RIGHT="7" SIGIS="undef" SIGNAME="segment_0_anodes">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="anodes_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="cathodes" RIGHT="7" SIGIS="undef" SIGNAME="segment_0_cathodes">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="cathodes_0"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/xlconcat_4" HWVERSION="2.1" INSTANCE="xlconcat_4" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconcat" VLNV="xilinx.com:ip:xlconcat:2.1">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="IN0_WIDTH" VALUE="4"/>
        <PARAMETER NAME="IN1_WIDTH" VALUE="4"/>
        <PARAMETER NAME="IN2_WIDTH" VALUE="8"/>
        <PARAMETER NAME="IN3_WIDTH" VALUE="2"/>
        <PARAMETER NAME="IN4_WIDTH" VALUE="5"/>
        <PARAMETER NAME="IN5_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN6_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN7_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN8_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN9_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN10_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN11_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN12_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN13_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN14_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN15_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN16_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN17_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN18_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN19_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN20_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN21_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN22_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN23_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN24_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN25_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN26_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN27_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN28_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN29_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN30_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN31_WIDTH" VALUE="1"/>
        <PARAMETER NAME="dout_width" VALUE="16"/>
        <PARAMETER NAME="NUM_PORTS" VALUE="3"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_xlconcat_3_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="3" NAME="In0" RIGHT="0" SIGIS="undef" SIGNAME="packaging_0_errorCode">
          <CONNECTIONS>
            <CONNECTION INSTANCE="packaging_0" PORT="errorCode"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="In1" RIGHT="0" SIGIS="undef" SIGNAME="packaging_0_stateOut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="packaging_0" PORT="stateOut"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="In2" RIGHT="0" SIGIS="undef" SIGNAME="xlslice_0_Dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlslice_0" PORT="Dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="xlconcat_4_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="led_0"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/xlconcat_5" HWVERSION="2.1" INSTANCE="xlconcat_5" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconcat" VLNV="xilinx.com:ip:xlconcat:2.1">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="IN0_WIDTH" VALUE="9"/>
        <PARAMETER NAME="IN1_WIDTH" VALUE="7"/>
        <PARAMETER NAME="IN2_WIDTH" VALUE="8"/>
        <PARAMETER NAME="IN3_WIDTH" VALUE="2"/>
        <PARAMETER NAME="IN4_WIDTH" VALUE="5"/>
        <PARAMETER NAME="IN5_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN6_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN7_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN8_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN9_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN10_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN11_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN12_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN13_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN14_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN15_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN16_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN17_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN18_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN19_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN20_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN21_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN22_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN23_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN24_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN25_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN26_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN27_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN28_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN29_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN30_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN31_WIDTH" VALUE="1"/>
        <PARAMETER NAME="dout_width" VALUE="16"/>
        <PARAMETER NAME="NUM_PORTS" VALUE="2"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_xlconcat_4_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="8" NAME="In0" RIGHT="0" SIGIS="undef" SIGNAME="fifo_output_rd_data_count">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fifo_output" PORT="rd_data_count"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="In1" RIGHT="0" SIGIS="undef" SIGNAME="xlconstant_1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconstant_1" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="xlconcat_5_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlslice_0" PORT="Din"/>
            <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="fifo_read_length"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="5" FULLNAME="/xlconstant_0" HWVERSION="1.1" INSTANCE="xlconstant_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconstant" VLNV="xilinx.com:ip:xlconstant:1.1">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="CONST_WIDTH" VALUE="16"/>
        <PARAMETER NAME="CONST_VAL" VALUE="0x0000"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_xlconstant_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" LEFT="15" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="xlconstant_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ethernet_transceiver2_0" PORT="udp_packet_checksum"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="5" FULLNAME="/xlconstant_1" HWVERSION="1.1" INSTANCE="xlconstant_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconstant" VLNV="xilinx.com:ip:xlconstant:1.1">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="CONST_WIDTH" VALUE="7"/>
        <PARAMETER NAME="CONST_VAL" VALUE="0x00"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_xlconstant_0_1"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" LEFT="6" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="xlconstant_1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconcat_5" PORT="In1"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/xlslice_0" HWVERSION="1.0" INSTANCE="xlslice_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlslice" VLNV="xilinx.com:ip:xlslice:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="16"/>
        <PARAMETER NAME="DIN_FROM" VALUE="7"/>
        <PARAMETER NAME="DIN_TO" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="design_1_xlslice_0_0"/>
        <PARAMETER NAME="DOUT_WIDTH" VALUE="8"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="15" NAME="Din" RIGHT="0" SIGIS="undef" SIGNAME="xlconcat_5_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconcat_5" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="Dout" RIGHT="0" SIGIS="undef" SIGNAME="xlslice_0_Dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconcat_4" PORT="In2"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
  </MODULES>

</EDKSYSTEM>
