<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
  <spirit:vendor>xilinx.com</spirit:vendor>
  <spirit:library>customized_ip</spirit:library>
  <spirit:name>design_1_segment_0_0</spirit:name>
  <spirit:version>1.0</spirit:version>
  <spirit:busInterfaces>
    <spirit:busInterface>
      <spirit:name>clk</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>clk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>PHASE</spirit:name>
          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>CLK_DOMAIN</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">design_1_clk_100MHz</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_RESET</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET"/>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
            </xilinx:parameterInfo>
          </spirit:vendorExtensions>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
  </spirit:busInterfaces>
  <spirit:model>
    <spirit:views>
      <spirit:view>
        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
        <spirit:displayName>Synthesis</spirit:displayName>
        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
        <spirit:modelName>segment</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
            <spirit:value>Thu May 28 15:18:27 UTC 2020</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
            <spirit:value>9:cf4e2117</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
        <spirit:language>vhdl</spirit:language>
        <spirit:modelName>design_1_segment_0_0</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
            <spirit:value>Thu May 28 18:44:53 UTC 2020</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
            <spirit:value>9:cf4e2117</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
        <spirit:displayName>Simulation</spirit:displayName>
        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
        <spirit:modelName>segment</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
            <spirit:value>Thu May 28 15:18:27 UTC 2020</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
            <spirit:value>9:9abd59d1</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
        <spirit:language>vhdl</spirit:language>
        <spirit:modelName>design_1_segment_0_0</spirit:modelName>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
            <spirit:value>Thu May 28 18:44:53 UTC 2020</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
            <spirit:value>9:9abd59d1</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
      <spirit:view>
        <spirit:name>xilinx_externalfiles</spirit:name>
        <spirit:displayName>External Files</spirit:displayName>
        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
        <spirit:fileSetRef>
          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
        </spirit:fileSetRef>
        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
            <spirit:value>Thu May 28 18:46:11 UTC 2020</spirit:value>
          </spirit:parameter>
          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
            <spirit:value>9:cf4e2117</spirit:value>
          </spirit:parameter>
        </spirit:parameters>
      </spirit:view>
    </spirit:views>
    <spirit:ports>
      <spirit:port>
        <spirit:name>num1</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="16">0x00E2</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>num2</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">15</spirit:left>
            <spirit:right spirit:format="long">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="16">0x00E2</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>clk</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>anodes</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">0</spirit:left>
            <spirit:right spirit:format="long">7</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>cathodes</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">0</spirit:left>
            <spirit:right spirit:format="long">7</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
    </spirit:ports>
  </spirit:model>
  <spirit:fileSets>
    <spirit:fileSet>
      <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>src/segment.xdc</spirit:name>
        <spirit:userFileType>xdc</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>../../ipshared/d98c/src/segment.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>synth/design_1_segment_0_0.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>../../ipshared/d98c/src/segment.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>sim/design_1_segment_0_0.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>design_1_segment_0_0.dcp</spirit:name>
        <spirit:userFileType>dcp</spirit:userFileType>
        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
      <spirit:file>
        <spirit:name>design_1_segment_0_0_stub.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
      <spirit:file>
        <spirit:name>design_1_segment_0_0_stub.vhdl</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
      <spirit:file>
        <spirit:name>design_1_segment_0_0_sim_netlist.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
      <spirit:file>
        <spirit:name>design_1_segment_0_0_sim_netlist.vhdl</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
    </spirit:fileSet>
  </spirit:fileSets>
  <spirit:description>segment_v1_0</spirit:description>
  <spirit:parameters>
    <spirit:parameter>
      <spirit:name>Component_Name</spirit:name>
      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_segment_0_0</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
  <spirit:vendorExtensions>
    <xilinx:coreExtensions>
      <xilinx:displayName>segment_v1_0</xilinx:displayName>
      <xilinx:definitionSource>package_project</xilinx:definitionSource>
      <xilinx:coreRevision>4</xilinx:coreRevision>
      <xilinx:tags>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@749e80d8_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@4d5a2e26_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@615029f0_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@1c465cf6_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6da5ca59_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@39d7574a_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@63bf7914_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@7fc16fb0_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@4d9b7294_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@a1723ac_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@4d20d57f_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@629b5dff_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@79beb46b_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@489b6fd8_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@3074f5bc_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@71800c02_ARCHIVE_LOCATION">z:/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@49a569bc_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@74ae251d_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@3f41d065_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@28681b2d_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@1d3564c5_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@8bfd351_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@6c402823_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@d7dc8ac_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@4ba251e4_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
        <xilinx:tag xilinx:name="ui.data.coregen.dd@5d55046_ARCHIVE_LOCATION">c:/Users/johan/mlfpga/ip_repo/7segment</xilinx:tag>
      </xilinx:tags>
      <xilinx:configElementInfos>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
      </xilinx:configElementInfos>
    </xilinx:coreExtensions>
    <xilinx:packagingInfo>
      <xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="a88d4390"/>
      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d53f92ad"/>
      <xilinx:checksum xilinx:scope="ports" xilinx:value="6842c7da"/>
      <xilinx:checksum xilinx:scope="parameters" xilinx:value="9f959d71"/>
    </xilinx:packagingInfo>
  </spirit:vendorExtensions>
</spirit:component>
